94 lines
3.6 KiB
C
94 lines
3.6 KiB
C
|
#ifndef RW_LOGGING_H_
|
|||
|
|
#define RW_LOGGING_H_
|
|||
|
|
|
|||
|
|
#include "stdint.h"
|
|||
|
|
|
|||
|
|
/*OLD*/
|
|||
|
|
#define Log_Type_Device_Change 0x04 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
|||
|
|
#define Log_Type_Global_Parameters 0x05 //ȫ<>ֲ<EFBFBD><D6B2><EFBFBD><EFBFBD>仯
|
|||
|
|
|
|||
|
|
|
|||
|
|
//SRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ص<EFBFBD>ַ
|
|||
|
|
/*
|
|||
|
|
2022-05-09 <EFBFBD><EFBFBD>SRAM<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>ַ SRAM_LOG_DATA_Address <EFBFBD><EFBFBD>0x090020<EFBFBD><EFBFBD>Ϊ0x090100
|
|||
|
|
ԭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Launcher<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ - <EFBFBD><EFBFBD>APPʹ<EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>PC<EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<EFBFBD><EFBFBD>Ч
|
|||
|
|
*/
|
|||
|
|
#define SRAM_LOG_Start_Address 0x090000 //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>ʼ<EFBFBD><CABC>ַ - <20><>ǰSRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ - 4Byte
|
|||
|
|
#define SRAM_TFTP_LOG_READ_Address 0x090004 //TFTP<54><50>־<EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>ȡ<EFBFBD><C8A1>ַ - 4Byte
|
|||
|
|
#define SRAM_FLASH_LOG_READ_Address 0x090008 //Flash<73><68>־д<D6BE><D0B4><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ - 4Byte
|
|||
|
|
#define SRAM_SD_LOG_READ_Start_Address 0x09000C //SD<53><44>ȡ<EFBFBD><C8A1>ʼ<EFBFBD><CABC>ַ - <20><>TFTP<54><50>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>ʱ<EFBFBD><CAB1>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ֵ<EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDд<44><D0B4>LOGʹ<47><CAB9> - 4Byte
|
|||
|
|
#define SRAM_SD_LOG_READ_End_Address 0x090010 //SD<53><44>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 4Byte
|
|||
|
|
#define SRAM_Flash_Serial_Number 0x090014 //<2F><>־<EFBFBD><D6BE><EFBFBD>ű<EFBFBD><C5B1><EFBFBD><EFBFBD><EFBFBD>ַ - 1Byte
|
|||
|
|
#define SRAM_LOGFlag_Reset_Source 0x090018 //Launcher<65><72><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> - <20><>APPʹ<50><CAB9>
|
|||
|
|
#define SRAM_LOGFlag_Addr_INIT 0x090019 //Launcher<65><72>¼<EFBFBD><C2BC>ַSRAM<41><4D>ʼ<EFBFBD><CABC>״̬<D7B4><CCAC>־λ - <20><>APPʹ<50><CAB9>
|
|||
|
|
#define SRAM_LOGFlag_Debug_Switch 0x09001A //Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ 4Byte - <20><>APPʹ<50><CAB9>
|
|||
|
|
#define SRAM_APPFlag_Reset_Source 0x09001E //App<70><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ 2Byte - <20><>Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣʹ<CFA2><CAB9> 0xBBC1
|
|||
|
|
#define SRAM_LOG_DATA_Address 0x090100 //<2F><>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>ַ
|
|||
|
|
#define SRAM_LOG_End_Address 0x2FFFFF //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 0x0AFFFF
|
|||
|
|
|
|||
|
|
#define APPFlag_UartUpgrade_Reset 0xBBC1 //APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
|
|||
|
|
//Flash<73><68><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ص<EFBFBD>ַ
|
|||
|
|
/*
|
|||
|
|
2022-04-17 <EFBFBD><EFBFBD>Flash<EFBFBD><EFBFBD>־<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>0x090000<EFBFBD><EFBFBD>Ϊ0x100000 ~ 0x1FFFFF
|
|||
|
|
*/
|
|||
|
|
#define LOG_Flash_Start_Address 0x100000 //Flash<73><68>־<EFBFBD>ռ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ
|
|||
|
|
#define LOG_Flash_Overflow_Address 0x100004 //Flash<73><68>־<EFBFBD>ռ<EFBFBD><D5BC>Ƿ<EFBFBD><C7B7>Ѵ<EFBFBD><D1B4><EFBFBD><EFBFBD><EFBFBD>־λ
|
|||
|
|
//#define LOG_Flash_Serial_Number 0x090005 //<2F><>־<EFBFBD><D6BE><EFBFBD>ű<EFBFBD><C5B1><EFBFBD><EFBFBD><EFBFBD>ַ
|
|||
|
|
#define LOG_Flash_DATA_Address 0x100020 //Flash<73><68>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>ַ
|
|||
|
|
#define LOG_Flash_End_Address 0x1FFFFF //Flash<73><68>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
|||
|
|
//<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
|
|||
|
|
#define LOG_Data_Hand 0xA5 //LOG<4F><47><EFBFBD><EFBFBD>ͷ
|
|||
|
|
#define Log_Data_End 0x5A //LOG<4F><47><EFBFBD><EFBFBD>β
|
|||
|
|
#define Log_Data_Len_MAX 512 //<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>512Byte
|
|||
|
|
|
|||
|
|
/*<2A><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ
|
|||
|
|
2021-04-02 <EFBFBD><EFBFBD><EFBFBD>Ӹ<EFBFBD>У<EFBFBD><EFBFBD>λ
|
|||
|
|
2021_11_29<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD>ȸ<EFBFBD>Ϊ2Byte
|
|||
|
|
*/
|
|||
|
|
typedef enum{
|
|||
|
|
S_Log_Hand,
|
|||
|
|
S_Log_SN, //<2F><>־ÿ<D6BE><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
|
|||
|
|
S_Log_Len,
|
|||
|
|
S_Log_Len_8,
|
|||
|
|
S_Log_Check,
|
|||
|
|
S_Log_Date_H, //<2F>꣺5bit <20>£<EFBFBD>5bit <20>գ<EFBFBD>5bit
|
|||
|
|
S_Log_Date_L,
|
|||
|
|
S_Log_Type,
|
|||
|
|
S_Log_Time8B, //Сʱʱ<CAB1><CAB1><EFBFBD><EFBFBD>
|
|||
|
|
S_Log_Time16B,
|
|||
|
|
S_Log_Time24B,
|
|||
|
|
S_Log_Time32B,
|
|||
|
|
S_Log_Data,
|
|||
|
|
}Sram_Log_Data_Format;
|
|||
|
|
|
|||
|
|
/************************************************************/
|
|||
|
|
|
|||
|
|
uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len);
|
|||
|
|
uint8_t Log_read_sram(void);
|
|||
|
|
uint32_t Get_Log_Current_Address(void);
|
|||
|
|
void Set_Log_Current_Address(uint32_t W_addr);
|
|||
|
|
void SRAM_Set_TFTP_READ_LOG_Address(uint32_t r_addr);
|
|||
|
|
uint32_t SRAM_Get_TFTP_READ_Log_Address(void);
|
|||
|
|
void SRAM_Set_FLASH_READ_LOG_Address(uint32_t r_addr);
|
|||
|
|
uint32_t SRAM_Get_FLASH_READ_LOG_Address(void);
|
|||
|
|
void SRAM_Set_SD_LOG_READ_Start_Address(uint32_t r_addr);
|
|||
|
|
uint32_t SRAM_Get_SD_LOG_READ_Start_Address(void);
|
|||
|
|
void SRAM_Set_SD_LOG_READ_End_Address(uint32_t r_addr);
|
|||
|
|
uint32_t SRAM_Get_SD_LOG_READ_End_Address(void);
|
|||
|
|
|
|||
|
|
uint32_t Log_Get_Flash_Current_Address(void);
|
|||
|
|
void Log_Set_Flash_Current_Address(uint32_t w_addr);
|
|||
|
|
void Log_set_Flash_overflow_flag(uint8_t overflow_state);
|
|||
|
|
void Log_Write_Flash(void);
|
|||
|
|
void Log_Read_Flash(void);
|
|||
|
|
void LOG_Preserve_Flash_Task(void);
|
|||
|
|
void LOG_Save_Device_Action(uint8_t type,uint8_t addr,uint16_t loop,uint16_t state);
|
|||
|
|
void LOG_Save_Device_Change(uint32_t data_addr, uint16_t data_len);
|
|||
|
|
void LOG_Save_Global_Parameters(void);
|
|||
|
|
uint8_t SRAM_PowerOn_Restore_ParaInfo(void);
|
|||
|
|
|
|||
|
|
void Retain_Flash_Register_Data(void);
|
|||
|
|
void Read_Flash_Register_Data(void);
|
|||
|
|
|
|||
|
|
#endif
|