Boonlive_RD_Embedded/BLV_MD203_Bootload
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fix:修改RS485通讯引脚

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RS485通讯引脚改为串口2，引脚：RX：PB05 TX：PB04 RS485_DR:PB03
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caocong
2026-02-25 10:29:57 +08:00
commit 2815979c8a
77 changed files with 16491 additions and 0 deletions
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Source/.cache/compile_commands.json Normal file
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@@ -0,0 +1,73 @@
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"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\mcu_initial.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\mcu_initial.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\mcu_interrupt.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\mcu_interrupt.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\mcu_interrupt.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102_ck801.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102_ck801.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\drivers\\apt32f102_ck801.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\uart.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\uart.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\uart.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\eeprom.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\eeprom.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\eeprom.o"]
}, {
"file": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\Bootload_fun.c",
"directory": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source",
"arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-ID:/C-Sky/CDK/CSKY/csi/csi_core/include/", "-ID:/C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-IUSRCTRL/inc", "-Iinclude", "-include", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\Bootload_fun.c", "-o", "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\SYSTEM\\Bootload_fun.o"]
}]

200
Source/.cache/macro.h Normal file
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@@ -0,0 +1,200 @@
#define __HQ_FBIT__ 15
#define __SFRACT_IBIT__ 0
#define __FLT_MIN__ 1.1754943508222875e-38F
#define __GCC_IEC_559_COMPLEX 0
#define __UFRACT_MAX__ 0XFFFFP-16UR
#define __DQ_FBIT__ 63
#define __ULFRACT_FBIT__ 32
#define __SACCUM_EPSILON__ 0x1P-7HK
#define __CK801__ 1
#define __USQ_IBIT__ 0
#define __ACCUM_FBIT__ 15
#define __WINT_MAX__ 0xffffffffU
#define __USFRACT_FBIT__ 8
#define __WCHAR_MAX__ 0x7fffffffL
#define __LACCUM_IBIT__ 32
#define __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L)
#define __GCC_ATOMIC_CHAR_LOCK_FREE 1
#define __GCC_IEC_559 0
#define __csky_soft_float__ 1
#define __FLT_EVAL_METHOD__ 0
#define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK
#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
#define __FRACT_FBIT__ 15
#define __UACCUM_FBIT__ 16
#define __LFRACT_IBIT__ 0
#define __LFRACT_MAX__ 0X7FFFFFFFP-31LR
#define __UINT_FAST8_MAX__ 0xffffffffU
#define __cskyabi__ 2
#define __SA_FBIT__ 15
#define __LDBL_MAX__ 1.7976931348623157e+308L
#define __FRACT_MAX__ 0X7FFFP-15R
#define __cskyLE__ 1
#define __UFRACT_FBIT__ 16
#define __UFRACT_MIN__ 0.0UR
#define __GCC_ATOMIC_BOOL_LOCK_FREE 1
#define __LLFRACT_EPSILON__ 0x1P-63LLR
#define __CHAR_UNSIGNED__ 1
#define __UINT32_MAX__ 0xffffffffUL
#define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR
#define __TA_IBIT__ 64
#define __LDBL_MAX_EXP__ 1024
#define __WINT_MIN__ 0U
#define __CSKY_REQUIRED_SCANF__ 1
#define __ULLFRACT_MIN__ 0.0ULLR
#define __WCHAR_MIN__ (-__WCHAR_MAX__ - 1)
#define __GCC_ATOMIC_POINTER_LOCK_FREE 1
#define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)
#define __USACCUM_IBIT__ 8
#define __LFRACT_MIN__ (-0.5LR-0.5LR)
#define __HA_IBIT__ 8
#define __TQ_IBIT__ 0
#define __FLT_EPSILON__ 1.1920928955078125e-7F
#define __USFRACT_IBIT__ 0
#define __LDBL_MIN__ 2.2250738585072014e-308L
#define __FRACT_MIN__ (-0.5R-0.5R)
#define __DA_IBIT__ 32
#define __INT32_MAX__ 0x7fffffffL
#define __UQQ_FBIT__ 8
#define __UACCUM_MAX__ 0XFFFFFFFFP-16UK
#define __DECIMAL_DIG__ 17
#define __LFRACT_EPSILON__ 0x1P-31LR
#define __ULFRACT_MIN__ 0.0ULR
#define __ULACCUM_IBIT__ 32
#define __UACCUM_EPSILON__ 0x1P-16UK
#define __GNUC__ 6
#define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK
#define __HQ_IBIT__ 0
#define __SIZEOF_LONG_DOUBLE__ 8
#define __BIGGEST_ALIGNMENT__ 4
#define __DQ_IBIT__ 0
#define __DBL_MAX__ ((double)1.7976931348623157e+308L)
#define __ULFRACT_IBIT__ 0
#define __cskyle__ 1
#define __ACCUM_IBIT__ 16
#define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK
#define __INT_FAST16_TYPE__ int
#define __INT_LEAST32_MAX__ 0x7fffffffL
#define __USING_SJLJ_EXCEPTIONS__ 1
#define __ACCUM_MAX__ 0X7FFFFFFFP-15K
#define __USACCUM_EPSILON__ 0x1P-8UHK
#define __SFRACT_MAX__ 0X7FP-7HR
#define __FRACT_IBIT__ 0
#define __UACCUM_MIN__ 0.0UK
#define __CSKY_SOFT_FLOAT__ 1
#define __UACCUM_IBIT__ 16
#define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK
#define __SIZEOF_WINT_T__ 4
#define __SA_IBIT__ 16
#define __ULLACCUM_MIN__ 0.0ULLK
#define __GXX_ABI_VERSION 1010
#define __UTA_FBIT__ 64
#define __USFRACT_MAX__ 0XFFP-8UHR
#define __UFRACT_IBIT__ 0
#define __DBL_MIN__ ((double)2.2250738585072014e-308L)
#define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK)
#define __ULLACCUM_FBIT__ 32
#define __ULLFRACT_EPSILON__ 0x1P-64ULLR
#define __ACCUM_MIN__ (-0X1P15K-0X1P15K)
#define __SQ_IBIT__ 0
#define __UHA_FBIT__ 8
#define __SFRACT_MIN__ (-0.5HR-0.5HR)
#define __UTQ_FBIT__ 128
#define __VERSION__ "6.3.0"
#define __ULLFRACT_FBIT__ 64
#define __CSKYABIV2__ 1
#define __ckcore__ 2
#define __FRACT_EPSILON__ 0x1P-15R
#define __ULACCUM_MIN__ 0.0ULK
#define __UDA_FBIT__ 32
#define __LLACCUM_EPSILON__ 0x1P-31LLK
#define __GCC_ATOMIC_INT_LOCK_FREE 1
#define __CSKYABI__ 2
#define __CSKY_REQUIRED_PRINTF__ 1
#define __USFRACT_MIN__ 0.0UHR
#define __UQQ_IBIT__ 0
#define __CSKYLE__ 1
#define __INT32_C(c) c ## L
#define __UHQ_FBIT__ 16
#define __LLACCUM_FBIT__ 31
#define __UDQ_FBIT__ 64
#define __ELF__ 1
#define __ULFRACT_EPSILON__ 0x1P-32ULR
#define __LLFRACT_FBIT__ 63
#define __LDBL_EPSILON__ 2.2204460492503131e-16L
#define __SACCUM_MAX__ 0X7FFFP-7HK
#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 1
#define __LACCUM_EPSILON__ 0x1P-31LK
#define __INT_FAST16_MAX__ 0x7fffffff
#define __USACCUM_MAX__ 0XFFFFP-8UHK
#define __SFRACT_EPSILON__ 0x1P-7HR
#define __USA_FBIT__ 16
#define __UINT_FAST16_TYPE__ unsigned int
#define __csky_required_scanf__ 1
#define __SACCUM_FBIT__ 7
#define __GCC_ATOMIC_LONG_LOCK_FREE 1
#define __SQ_FBIT__ 31
#define __INT_FAST8_MAX__ 0x7fffffff
#define __QQ_FBIT__ 7
#define __UTA_IBIT__ 64
#define __LDBL_MANT_DIG__ 53
#define __SFRACT_FBIT__ 7
#define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK)
#define __CKCORE__ 2
#define __WCHAR_TYPE__ long int
#define __USQ_FBIT__ 32
#define __ULLACCUM_IBIT__ 32
#define __LACCUM_FBIT__ 31
#define __USACCUM_MIN__ 0.0UHK
#define __UHA_IBIT__ 8
#define __UTQ_IBIT__ 0
#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
#define __WINT_TYPE__ unsigned int
#define __ULLFRACT_IBIT__ 0
#define __LDBL_MIN_EXP__ (-1021)
#define __UDA_IBIT__ 32
#define __ck801__ 1
#define __LFRACT_FBIT__ 31
#define __LDBL_MAX_10_EXP__ 308
#define __DBL_EPSILON__ ((double)2.2204460492503131e-16L)
#define __INT_LEAST32_TYPE__ long int
#define __SIZEOF_WCHAR_T__ 4
#define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR
#define __TQ_FBIT__ 127
#define __INT_FAST8_TYPE__ int
#define __ULLACCUM_EPSILON__ 0x1P-32ULLK
#define __UHQ_IBIT__ 0
#define __LLACCUM_IBIT__ 32
#define __TA_FBIT__ 63
#define __UDQ_IBIT__ 0
#define __ckcoreLE__ 1
#define __ACCUM_EPSILON__ 0x1P-15K
#define __FLT_DENORM_MIN__ 1.4012984643248171e-45F
#define __LLFRACT_IBIT__ 0
#define __FLT_MAX__ 3.4028234663852886e+38F
#define __USACCUM_FBIT__ 8
#define __INT32_TYPE__ long int
#define __UFRACT_EPSILON__ 0x1P-16UR
#define __GNUC_MINOR__ 3
#define __HA_FBIT__ 7
#define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L
#define __csky__ 2
#define __LLFRACT_MIN__ (-0.5LLR-0.5LLR)
#define __DA_FBIT__ 31
#define __UINT32_TYPE__ long unsigned int
#define __USA_IBIT__ 16
#define __LDBL_MIN_10_EXP__ (-307)
#define __csky_required_printf__ 1
#define __cskyabiv2__ 1
#define __ULACCUM_EPSILON__ 0x1P-32ULK
#define __SACCUM_IBIT__ 8
#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
#define __LDBL_DIG__ 15
#define __UINT_FAST16_MAX__ 0xffffffffU
#define __GCC_ATOMIC_SHORT_LOCK_FREE 1
#define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR
#define __UINT_FAST8_TYPE__ unsigned int
#define __USFRACT_EPSILON__ 0x1P-8UHR
#define __ULACCUM_FBIT__ 32
#define __QQ_IBIT__ 0
#define __CSKY__ 2

6
Source/.cache/project.conf Normal file
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@@ -0,0 +1,6 @@
{
"device": " -mcpu=ck801 ",
"toolchain": "D:\\C-Sky\\CDKRepo\\Toolchain/CKV2ElfMinilib/V3.10.29/R/",
"toolchain_includes": ["d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include"],
"application": "E:\\Git_Project_Sourcode\\BLV_MD203_Bootload\\Source\\.cache/"
}

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<?xml version="1.0" encoding="UTF-8"?>
<Session Name="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\Project.cdkws">
<int Value="1" Name="m_selectedTab"/>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\Project.cdkws" Name="m_workspaceName"/>
<TabInfoArray Name="TabInfoArray">
<TabInfo>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\main.c" Name="FileName"/>
<wxString Value="MD203F8P" Name="ProjectName"/>
<int Value="0" Name="FirstVisibleLine"/>
<int Value="8" Name="CurrentLine"/>
<wxArrayString Name="Bookmarks"/>
<IntVector Name="CollapsedFolds"/>
</TabInfo>
<TabInfo>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\mcu_initial.c" Name="FileName"/>
<wxString Value="MD203F8P" Name="ProjectName"/>
<int Value="25" Name="FirstVisibleLine"/>
<int Value="51" Name="CurrentLine"/>
<wxArrayString Name="Bookmarks"/>
<IntVector Name="CollapsedFolds"/>
</TabInfo>
<TabInfo>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\SYSTEM\uart.c" Name="FileName"/>
<wxString Value="MD203F8P" Name="ProjectName"/>
<int Value="440" Name="FirstVisibleLine"/>
<int Value="483" Name="CurrentLine"/>
<wxArrayString Name="Bookmarks"/>
<IntVector Name="CollapsedFolds"/>
</TabInfo>
<TabInfo>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\mcu_interrupt.c" Name="FileName"/>
<wxString Value="MD203F8P" Name="ProjectName"/>
<int Value="621" Name="FirstVisibleLine"/>
<int Value="669" Name="CurrentLine"/>
<wxArrayString Name="Bookmarks"/>
<IntVector Name="CollapsedFolds"/>
</TabInfo>
<TabInfo>
<wxString Value="E:\Git_Project_Sourcode\BLV_MD203_Bootload\Source\includes.h" Name="FileName"/>
<wxString Value="MD203F8P" Name="ProjectName"/>
<int Value="1" Name="FirstVisibleLine"/>
<int Value="28" Name="CurrentLine"/>
<wxArrayString Name="Bookmarks"/>
<IntVector Name="CollapsedFolds"/>
</TabInfo>
</TabInfoArray>
<SerializedObject Name="m_breakpoints">
<long Value="0" Name="Count"/>
</SerializedObject>
</Session>

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Source/.cdk/compilation.db Normal file
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Source/.cdk/refactoring.db Normal file
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287
Source/FWlib/apt32f102_bt.c Normal file
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/*
******************************************************************************
* @file apt32f102_bt.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_bt.h"
/* defines -------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_DeInit(CSP_BT_T *BTx)
{
BTx->RSSR=BT_RESET_VALUE;
BTx->CR=BT_RESET_VALUE;
BTx->PSCR=BT_RESET_VALUE;
BTx->PRDR=BT_RESET_VALUE;
BTx->CMP=BT_RESET_VALUE;
BTx->CNT=BT_RESET_VALUE;
BTx->EVTRG=BT_RESET_VALUE;
BTx->EVSWF=BT_RESET_VALUE;
BTx->RISR=BT_RESET_VALUE;
BTx->IMCR=BT_RESET_VALUE;
BTx->MISR=BT_RESET_VALUE;
BTx->ICR=BT_RESET_VALUE;
}
/*************************************************************/
//BT IO Init
//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10,
//ReturnValue:NONE
/*************************************************************/
void BT_IO_Init(BT_Pin_TypeDef BT_IONAME)
{
if(BT_IONAME==BT0_PA00)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; //BT0 PA0.0
}
if(BT_IONAME==BT0_PA02)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000600; //BT0 PA0.2
}
if(BT_IONAME==BT0_PA05)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00500000; //BT0 PA0.5
}
if(BT_IONAME==BT0_PB02)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFF0FF)|0x00000500; //BT0 PB0.2
}
if(BT_IONAME==BT0_PB05)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFF0FFFFF)|0x00700000; //BT0 PB0.5
}
if(BT_IONAME==BT0_PA11)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00008000; //BT0 PA0.11
}
if(BT_IONAME==BT0_PA13)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00800000; //BT0 PA0.13
}
if(BT_IONAME==BT0_PA15)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000; //BT0 PA0.15
}
if(BT_IONAME==BT1_PA01)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000060; //BT1 PA0.1
}
if(BT_IONAME==BT1_PA06)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x04000000; //BT1 PA0.6
}
if(BT_IONAME==BT1_PA08)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000006; //BT1 PA0.8
}
if(BT_IONAME==BT1_PA12)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00060000; //BT1 PA0.12
}
if(BT_IONAME==BT1_PA14)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14
}
if(BT_IONAME==BT1_PB00)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000008; //BT1 PB0.0
}
if(BT_IONAME==BT1_PB04)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4
}
}
/*************************************************************/
// BT start
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Start(CSP_BT_T *BTx)
{
BTx->RSSR |=0X01;
}
/*************************************************************/
// BT stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop(CSP_BT_T *BTx)
{
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT stop High
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop_High(CSP_BT_T *BTx)
{
BTx->CR |=(0x01<<6);
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT stop Low
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop_Low(CSP_BT_T *BTx)
{
BTx->CR =BTx->CR & ~(0x01<<6);
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT soft reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Soft_Reset(CSP_BT_T *BTx)
{
BTx->RSSR |= (0X5<<12);
}
/*************************************************************/
//BT Configure
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM)
{
BTx->CR |=BTCLK| BTSHDWSTP| BTOPM| BTEXTCKM;
BTx->PSCR = PSCR_DATA;
}
/*************************************************************/
//BT ControlSet
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD,
BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD)
{
BTx->CR |=BTSTART| BTIDLE| BTSYNC| BTSYNCMD| BTOSTMD| BTAREARM| BTCNTRLD;
}
/*************************************************************/
//BT Period / Compare set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA)
{
//BTx->CR|=0X01<<2;
BTx->PRDR =BTPRDR_DATA;
BTx->CMP =BTCMP_DATA;
}
/*************************************************************/
//BT COUNTER set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA)
{
BTx->CNT =BTCNT_DATA;
}
/*************************************************************/
//BT read counters
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
U16_T BT_PRDR_Read(CSP_BT_T *BTx)
{
return BTx->PRDR;
}
U16_T BT_CMP_Read(CSP_BT_T *BTx)
{
return BTx->CMP;
}
U16_T BT_CNT_Read(CSP_BT_T *BTx)
{
return BTx->CNT;
}
/*************************************************************/
//BT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE)
{
BTx->EVTRG|=BTTRG| BTTRGOE;
}
/*************************************************************/
//BT SOFT Trigger
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Soft_Tigger(CSP_BT_T *BTx)
{
BTx->EVSWF=0x01;
}
/*************************************************************/
//BT inturrpt Configure
//EntryParameter:BT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X)
{
if (NewState != DISABLE)
{
BTx->IMCR |= BT_IMSCR_X;
}
else
{
BTx->IMCR &= ~BT_IMSCR_X;
}
}
/*************************************************************/
//BT0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT0_INT_ENABLE(void)
{
INTC_ISER_WRITE(BT0_INT);
}
/*************************************************************/
//BT0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT0_INT_DISABLE(void)
{
INTC_ICER_WRITE(BT0_INT);
}
/*************************************************************/
//BT0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT1_INT_ENABLE(void)
{
INTC_ISER_WRITE(BT1_INT);
}
/*************************************************************/
//BT0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT1_INT_DISABLE(void)
{
INTC_ICER_WRITE(BT1_INT);
}

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Source/FWlib/apt32f102_gpio.c Normal file
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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_gpio.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//IO RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_DeInit(void)
{
GPIOA0->CONLR &= 0xFF000000;
GPIOA0->CONHR = GPIO_RESET_VALUE;
GPIOB0->CONLR = GPIO_RESET_VALUE;
GPIOB0->CONHR = GPIO_RESET_VALUE;
GPIOA0->WODR = GPIO_RESET_VALUE;
GPIOB0->WODR = GPIO_RESET_VALUE;
GPIOA0->SODR = GPIO_RESET_VALUE;
GPIOB0->SODR = GPIO_RESET_VALUE;
GPIOA0->CODR = GPIO_RESET_VALUE;
GPIOB0->CODR = GPIO_RESET_VALUE;
GPIOA0->ODSR = GPIO_RESET_VALUE;
GPIOB0->ODSR = GPIO_RESET_VALUE;
GPIOA0->PSDR = GPIO_RESET_VALUE;
GPIOB0->PSDR = GPIO_RESET_VALUE;
GPIOA0->FLTEN = 0xffff;
GPIOB0->FLTEN = 0x3f;
GPIOA0->PUDR = GPIO_RESET_VALUE;
GPIOB0->PUDR = GPIO_RESET_VALUE;
GPIOA0->DSCR = GPIO_RESET_VALUE;
GPIOB0->DSCR = GPIO_RESET_VALUE;
GPIOA0->OMCR = GPIO_RESET_VALUE;
GPIOB0->OMCR = GPIO_RESET_VALUE;
GPIOA0->IECR = GPIO_RESET_VALUE;
GPIOB0->IECR = GPIO_RESET_VALUE;
GPIOGRP->IGRPL = GPIO_RESET_VALUE;
GPIOGRP->IGRPH = GPIO_RESET_VALUE;
GPIOGRP->IGREX = GPIO_RESET_VALUE;
GPIOGRP->IO_CLKEN = 0xf;
}
/*************************************************************/
//IO OUTPUT INPUT SET 2
//EntryParameter:GPIOx,byte,val
//GPIOx:GPIOA0,GPIOB0
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//val:0x0000000~0xFFFFFFFF
//val=0x11111111 all IO as input
//val=0x22222222 all IO as output
//ReturnValue:NONE
/*************************************************************/
void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val)
{
if (byte==0)
{
(GPIOx)->CONLR=val;
}
else if(byte==1)
{
(GPIOx)->CONHR=val;
}
}
/*************************************************************/
//IO OUTPUT INPUT SET 1
//EntryParameter:GPIOx,GPIO_Pin(0~15),byte,Dir
//GPIOx:GPIOA0,GPIOB0
//GPIO_Pin:PIN_0~15
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//Dir:0:output 1:input
//ReturnValue:NONE
/*************************************************************/
void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir)
{
uint32_t data_temp;
uint8_t GPIO_Pin;
if(PinNum<8)
{
switch (PinNum)
{
case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
case 1:data_temp=0xffffff0f;GPIO_Pin=4;break;
case 2:data_temp=0xfffff0ff;GPIO_Pin=8;break;
case 3:data_temp=0xffff0fff;GPIO_Pin=12;break;
case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
}
if (Dir)
{
(GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
}
else
{
(GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin;
}
}
else if (PinNum<16)
{
switch (PinNum)
{
case 8:data_temp=0xfffffff0;GPIO_Pin=0;break;
case 9:data_temp=0xffffff0f;GPIO_Pin=4;break;
case 10:data_temp=0xfffff0ff;GPIO_Pin=8;break;
case 11:data_temp=0xffff0fff;GPIO_Pin=12;break;
case 12:data_temp=0xfff0ffff;GPIO_Pin=16;break;
case 13:data_temp=0xff0fffff;GPIO_Pin=20;break;
case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
case 15:data_temp=0x0fffffff;GPIO_Pin=28;break;
}
if (Dir)
{
(GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;
}
else
{
(GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;
}
}
}
/*************************************************************/
//IO OUTPUT INPUT Disable
//EntryParameter:GPIOx,GPIO_Pin(0~15)
//GPIOx:GPIOA0,GPIOB0
//GPIO_Pin:PIN_0~15
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//ReturnValue:NONE
/*************************************************************/
void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum)
{
uint32_t data_temp;
if(PinNum<8)
{
switch (PinNum)
{
case 0:data_temp=0xfffffff0;break;
case 1:data_temp=0xffffff0f;break;
case 2:data_temp=0xfffff0ff;break;
case 3:data_temp=0xffff0fff;break;
case 4:data_temp=0xfff0ffff;break;
case 5:data_temp=0xff0fffff;break;
case 6:data_temp=0xf0ffffff;break;
case 7:data_temp=0x0fffffff;break;
}
(GPIOx)->CONLR = (GPIOx)->CONLR & data_temp;
}
else if (PinNum<16)
{
switch (PinNum)
{
case 8:data_temp=0xfffffff0;break;
case 9:data_temp=0xffffff0f;break;
case 10:data_temp=0xfffff0ff;break;
case 11:data_temp=0xffff0fff;break;
case 12:data_temp=0xfff0ffff;break;
case 13:data_temp=0xff0fffff;break;
case 14:data_temp=0xf0ffffff;break;
case 15:data_temp=0x0fffffff;break;
}
(GPIOx)->CONHR = (GPIOx)->CONHR & data_temp;
}
}
/*************************************************************/
//IO OUTPUT INPUT SET
//EntryParameter:IO_MODE,GPIOx,val
//GPIOx:GPIOA0,GPIOB0
//IO_MODE:PUDR(IO PULL HIGH/LOW)
//IO_MODE:DSCR(IO DRIVE STRENGHT)
//IO_MODE:OMCR(OUTPUT MODE SET)
//IO_MODE:IECR(IO INT ENABLE)
//ReturnValue:NONE
/*************************************************************/
void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val)
{
switch (IO_MODE)
{
case PUDR:(GPIOx)->PUDR = val;break;
case DSCR:(GPIOx)->DSCR = val;break;
case OMCR:(GPIOx)->OMCR = val;break;
case IECR:(GPIOx)->IECR = val;break;
}
}
/*************************************************************/
//Write GPIO pull high/low
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x01<<(bit*2));
}
void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x02<<(bit*2));
}
void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = ((GPIOx)->PUDR) & ~(0x03<<(bit*2));
}
/*************************************************************/
//Write GPIO open drain init
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<<bit);
}
void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) & ~(0x01<<bit);
}
/*************************************************************/
//Write GPIO open drain init
//EntryParameter:GPIOx,uint8_t bit,INPUT_MODE_SETECTED_X
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//INPUT_MODE_SETECTED_X:INPUT_MODE_TTL1,INPUT_MODE_SETECTED_TTL2,INPUT_MODE_SETECTED_CMOSS
//ReturnValue:VALUE
/*************************************************************/
//默认cmos口
void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X)
{
if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_CMOS)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2+1));
}
else
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2+1));
if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL1)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<<(bit+16));
}
else if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL2)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) & ~(0x01<<(bit+16));
}
}
}
/*************************************************************/
//Write GPIO Drive Strength init
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2));
}
void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2));
}
/*************************************************************/
//IO OUTPUT INPUT SET
//EntryParameter:
//IO_MODE:IGRP(IO INT GROUP)
//PinNum：0~15
//SYSCON_EXIPIN_TypeDef:EXI_PIN0~EXI_PIN19
//EXI0~EXI15:GPIOA0,GPIOB0
//EXI16~EXI17:GPIOA0.0~GPIOA0.7
//EXI18~EXI19:GPIOB0.0~GPIOB0.3
//ReturnValue:NONE
/*************************************************************/
void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef Selete_EXI_x)
{
volatile unsigned int R_data_temp;
volatile unsigned char R_GPIO_Pin;
if(Selete_EXI_x<16)
{
if((Selete_EXI_x==0)||(Selete_EXI_x==8))
{
R_data_temp=0xfffffff0;
R_GPIO_Pin=0;
}
else if((Selete_EXI_x==1)||(Selete_EXI_x==9))
{
R_data_temp=0xffffff0f;
R_GPIO_Pin=4;
}
else if((Selete_EXI_x==2)||(Selete_EXI_x==10))
{
R_data_temp=0xfffff0ff;
R_GPIO_Pin=8;
}
else if((Selete_EXI_x==3)||(Selete_EXI_x==11))
{
R_data_temp=0xffff0fff;
R_GPIO_Pin=12;
}
else if((Selete_EXI_x==4)||(Selete_EXI_x==12))
{
R_data_temp=0xfff0ffff;
R_GPIO_Pin=16;
}
else if((Selete_EXI_x==5)||(Selete_EXI_x==13))
{
R_data_temp=0xff0fffff;
R_GPIO_Pin=20;
}
else if((Selete_EXI_x==6)||(Selete_EXI_x==14))
{
R_data_temp=0xf0ffffff;
R_GPIO_Pin=24;
}
else if((Selete_EXI_x==7)||(Selete_EXI_x==15))
{
R_data_temp=0x0fffffff;
R_GPIO_Pin=28;
}
if(Selete_EXI_x<8)
{
GPIOGRP->IGRPL =(GPIOGRP->IGRPL & R_data_temp) | (IO_MODE<<R_GPIO_Pin);
}
else if((Selete_EXI_x<16)&&(Selete_EXI_x>=8))
{
GPIOGRP->IGRPH =(GPIOGRP->IGRPH & R_data_temp) | (IO_MODE<<R_GPIO_Pin);
}
}
else if(Selete_EXI_x<20)
{
if((IO_MODE==0)&&((Selete_EXI_x==16)||((Selete_EXI_x==17)))) //PA0.0~PA0.7
{
if(Selete_EXI_x==16)
{
GPIOGRP->IGREX =(GPIOGRP->IGREX)|PinNum;
}
else if(Selete_EXI_x==17)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<4);
}
}
else if((IO_MODE==2)&&((Selete_EXI_x==18)||(Selete_EXI_x==19))) //PB0.0~PB0.3
{
if(Selete_EXI_x==18)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<8);
}
else if(Selete_EXI_x==19)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<12);
}
}
}
}
/*************************************************************/
//IO EXI SET
//EntryParameter:EXI_IO(EXI0~EXI13)
//ReturnValue:NONE
/*************************************************************/
void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
switch (EXI_IO)
{
case 0:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
case 2:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
case 3:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
case 4:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
case 5:GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
case 7:GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0X10000000;break;
case 8:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000001;break;
case 9:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0X00000010;break;
case 10:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0X00000100;break;
case 11:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0X00001000;break;
case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X01000000;break;
case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0X10000000;break;
}
}
void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
switch (EXI_IO)
{
case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
case 2:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0X00000100;break;
case 3:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0X00001000;break;
case 4:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0X00010000;break;
case 5:GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0X00100000;break;
default:break;
}
}
void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
(GPIOx)->IECR |= 1<<EXI_IO;
}
/*************************************************************/
//Write GPIO
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->SODR = (1ul<<bit);
}
void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->CODR = (1ul<<bit);
}
/*************************************************************/
//Write GPIO
//EntryParameter:GPIOx,uint8_t bitposi bitval
//GPIOx:GPIOA0,GPIOB0
//bitposi:0~15 bitval:0~1 0=low 1=high
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval)
{
if (bitval==1)
{
(GPIOx)->SODR = (1ul<<bitposi);
}
else if ((bitval==0))
{
(GPIOx)->CODR = (1ul<<bitposi);
}
}
/*************************************************************/
//Write GPIO reverse
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint32_t dat = 0;
dat=((GPIOx)->ODSR>>bit)&1ul;
{
if (dat==1)
{
(GPIOx)->CODR = (1ul<<bit);
return;
}
if (dat==0)
{
(GPIOx)->SODR = (1ul<<bit);
return;
}
}
}
/*************************************************************/
//READ PA IO STATUS
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=((GPIOx)->PSDR)&(1<<bit);
if (dat == (1<<bit))
{
value = 1;
}
return value;
}
/*************************************************************/
//READ PA OUTPUT STATUS
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=((GPIOx)->ODSR)&(1<<bit);
if (dat == (1<<bit))
{
value = 1;
}
return value;
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

89
Source/FWlib/apt32f102_hwdiv.c Normal file
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/*
******************************************************************************
* @file apt32f102_gpio.c
* @author APT AE Team
* @version V1.24
* @date 2018/10/15
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_hwdiv.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//HWDIV RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_DeInit(void)
{
HWD->DIVIDENT = HWDIV_RESET_VALUE;
HWD->DIVISOR = HWDIV_RESET_VALUE;
HWD->QUOTIENT = HWDIV_RESET_VALUE;
HWD->REMAIN = HWDIV_RESET_VALUE;
HWD->CR = HWDIV_RESET_VALUE;
}
/*************************************************************/
//HWDIV UNSIGN Configure
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_UNSIGN_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
HWD->CR |= HWDIV_UNSIGN_BIT;
}
else
{
HWD->CR &= ~HWDIV_UNSIGN_BIT;
}
}
/*************************************************************/
//HWDIV Calculate
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x)
{
HWD->DIVIDENT=DIVIDENDx;
HWD->DIVISOR=DIVISOR_x;
}
/*************************************************************/
//HWDIV Calculate result
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
U32_T HWDIV_Calc_Quotient(void)
{
return HWD->QUOTIENT;
}
/*************************************************************/
//HWDIV Calculate result
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
U32_T HWDIV_Calc_Remain(void)
{
return HWD->REMAIN;
}
/*************************************************************/
void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x)
{
HWD->DIVIDENT=DIVIDENDx;
HWD->DIVISOR=DIVISOR_x;
}

264
Source/FWlib/apt32f102_ifc.c Normal file
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/*
******************************************************************************
* @file apt32f102_ifc.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_ifc.h"
volatile unsigned int R_INT_FlashAdd;
volatile unsigned char f_Drom_writing=0;
/* define --------------------------------------------------------------------*/
extern void delay_nms(unsigned int t);
/* externs--------------------------------------------------------------------*/
/*************************************************************
//ChipErase fuction
//EntryParameter:NONE
//ReturnValue:NONE
*************************************************************/
void ChipErase(void)
{
SetUserKey;
EnChipErase;
StartErase;
while(IFC->CR!=0x0); //Wait for the operation to complete
}
/*************************************************************
//PageErase fuction
//EntryParameter:XROM_PageAdd
//XROM_PageAdd:PROM_PageAdd0~PROM_PageAdd255
//DROM_PageAdd0~DROM_PageAdd31
//ReturnValue:NONE
*************************************************************/
void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAdd)
{
SetUserKey;
EnPageErase;
IFC->FM_ADDR=XROM_PageAdd;
StartErase;
while(IFC->CR!=0x0);
}
/*************************************************************
//Enable or Disable IFC Interrupt when Operate FlashData
//EntryParameter:FlashAdd、DataSize、*BufArry
//ReturnValue:NONE
*************************************************************/
//PROM:Write at most 256 bytes once time
//DROM:Write at most 64 bytes at once time
//Interrupt mode requires multiple loop queries to complete
void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry)
{
int i,DataBuffer;
if(!f_Drom_writing)
{
f_Drom_writing=1;
R_INT_FlashAdd=FlashAdd;
ifc_step=0;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07; //Page cache wipe
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<((DataSize+3)/4);i++) //sizeof structure
{
DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24);
*(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer;
BufArry +=4;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
}
}
//Normal mode, when the call is completed once, it will delay 4.2ms in the program
void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry)
{
int i,DataBuffer;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<((DataSize+3)/4);i++) //sizeof structure
{
DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24);
*(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer;
BufArry +=4;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete
//Page erase 5
SetUserKey;
IFC->CMR=0x02;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete
//Write page cache data to flash memory 6
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete
}
void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry)
{
int i,DataBuffer;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<DataSize;i++) //sizeof structure
{
DataBuffer=*BufArry;
*(volatile unsigned int *)(FlashAdd)=DataBuffer;
BufArry +=1;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete
//Page erase 5
SetUserKey;
IFC->CMR=0x02;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete
//Write page cache data to flash memory 6
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete
}
/*************************************************************
// ReadFlashData fuction return Data arry save in Flash
// DataLength must be a multiple of 4, DataLength % 4 ==0.
//EntryParameter:RdStartAdd、DataLength、*DataArryPoint
//ReturnValue:NONE
*************************************************************/
void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint)
{
unsigned int i,Buffer;
//delay_nms(1);
for(i=0;i<((DataLength+3)/4);i++)
{
Buffer=*(volatile unsigned int *)RdStartAdd;
*DataArryPoint=Buffer;
*(DataArryPoint+1)=Buffer>>8;
*(DataArryPoint+2)=Buffer>>16;
*(DataArryPoint+3)=Buffer>>24;
RdStartAdd +=4;
DataArryPoint +=4;
}
}
/*************************************************************
//ReadFlashData fuction return Data arry save in Flash
//EntryParameter:RdStartAdd、DataLength、*DataArryPoint
//ReturnValue:NONE
*************************************************************/
void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint)
{
unsigned int i;
for (i=0;i<DataLength;i++)
{
if((i!=0)&&(i%4==0))
{
RdStartAdd +=4;
}
*DataArryPoint=*(U8_T *)(RdStartAdd+ (i%4));
DataArryPoint++;
}
}
void ReadDataArry_U32(unsigned int RdStartAdd,unsigned int DataLength,volatile U32_T *DataArryPoint)
{
unsigned int i;
for (i=0;i<DataLength;i++)
{
*DataArryPoint=*(U32_T *)(RdStartAdd);
DataArryPoint++;
}
}
/*************************************************************
//Enable or Disable IFC Interrupt when Operate FlashData
//EntryParameter:IFC_INT_x
//IFC_INT_x:ERS_END_INT,RGM_END_INT,PEP_END_INT,PROT_ERR_INT,UDEF_ERR_INT,ADDR_ERR_INT,OVW_ERR_INT
//ReturnValue:NONE
*************************************************************/
void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x)
{
if(NewState != DISABLE)
{
IFC->IMCR =IFC->IMCR|IFC_INT_x;
}
else
{
IFC->IMCR =IFC->IMCR & (~IFC_INT_x);
}
}
/*************************************************************/
//IFC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFC_Int_Enable(void)
{
IFC->ICR=0Xf007; //CLAER IFC INT status
INTC_ISER_WRITE(IFC_INT);
}
/*************************************************************/
//IFC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFC_Int_Disable(void)
{
INTC_ICER_WRITE(IFC_INT);
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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Source/FWlib/apt32f102_iostring.c Normal file
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/*
******************************************************************************
* @file apt32f102_iostring.c
* @author APT AE Team
* @version V1.00
* @date 2020/05/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/******************************************************************************
* Include Files
******************************************************************************/
#include "apt32f102.h"
#include "apt32f102_uart.h"
#include "stdarg.h"
#include "stddef.h"
#include "stdio.h"
/******************************************************************************
* Main code
******************************************************************************/
void __putchar__ (char s)
{
// UARTTxByte(UART0,s);
UARTTxByte(UART1,s);
}
char *myitoa(int value, int* string, int radix)
{
int tmp[33];
int* tp = tmp;
int i;
unsigned v;
int sign;
int* sp;
if (radix > 36 || radix <= 1)
{
return 0;
}
sign = (radix == 10 && value < 0);
if (sign)
v = -value;
else
v = (unsigned)value;
while (v || tp == tmp)
{
i = v % radix;
v = v / radix;
if (i < 10) {
*tp++ = i+'0';
} else {
*tp++ = i + 'a' - 10;
}
}
sp = string;
if (sign)
*sp++ = '-';
while (tp > tmp)
*sp++ = *--tp;
*sp = 0;
return string;
}
void my_printf(const char *fmt, ...)
{
// const char *s;
const int *s;
int d;
//char ch, *pbuf, buf[16];
char ch, *pbuf;
int buf[16];
va_list ap;
va_start(ap, fmt);
while (*fmt) {
if (*fmt != '%') {
__putchar__(*fmt++);
continue;
}
switch (*++fmt) {
case 's':
s = va_arg(ap, const char *);
for ( ; *s; s++) {
__putchar__(*s);
}
break;
case 'd':
d = va_arg(ap, int);
myitoa(d, buf, 10);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
case 'x':
case 'X':
d = va_arg(ap, int);
myitoa(d, buf, 16);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
// Add other specifiers here...
case 'c':
case 'C':
ch = (unsigned char)va_arg(ap, int);
pbuf = &ch;
__putchar__(*pbuf);
break;
default:
__putchar__(*fmt);
break;
}
fmt++;
}
va_end(ap);
}

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Source/FWlib/apt32f102_lpt.c Normal file
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/*
******************************************************************************
* @file apt32f102_lpt.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_lpt.h"
/*************************************************************/
//LPT RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_DeInit(void)
{
LPT->CEDR = 0xBE980000;
LPT->RSSR = LPT_RESET_VALUE;
LPT->PSCR = LPT_RESET_VALUE;
LPT->CR = 0X00010010;
LPT->SYNCR = LPT_RESET_VALUE;
LPT->PRDR = LPT_RESET_VALUE;
LPT->CMP = LPT_RESET_VALUE;
LPT->CNT = LPT_RESET_VALUE;
LPT->TRGFTCR = LPT_RESET_VALUE;
LPT->TRGFTWR = LPT_RESET_VALUE;
LPT->EVTRG = LPT_RESET_VALUE;
LPT->EVPS = LPT_RESET_VALUE;
LPT->EVSWF = LPT_RESET_VALUE;
LPT->RISR = LPT_RESET_VALUE;
LPT->MISR = LPT_RESET_VALUE;
LPT->IMCR = LPT_RESET_VALUE;
LPT->ICR = LPT_RESET_VALUE;
}
/*************************************************************/
//LPT IO Init
//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10,
//ReturnValue:NONE
/*************************************************************/
void LPT_IO_Init(LPT_IOSET_TypeDef IONAME)
{
if(IONAME==LPT_OUT_PA09)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000080;
}
if(IONAME==LPT_OUT_PB01)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000080;
}
if(IONAME==LPT_IN_PA10)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000800;
}
}
/*************************************************************/
//LPT Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX)
{
LPT->CEDR |=CLKX| CSSX| SHDWSTPX| (FLTCKPRSX<<8);
LPT->PSCR = PSCDIVX;
LPT->CR |=OPMX;
}
/*************************************************************/
//LPT DEBUG MODE
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Debug_Mode(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
LPT->CEDR |= LPT_DEBUG_MODE;
}
else
{
LPT->CEDR &= ~LPT_DEBUG_MODE;
}
}
/*************************************************************/
//LPT Period / Compare set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA)
{
LPT->PRDR =PRDR_DATA;
LPT->CMP =CMP_DATA;
}
/*************************************************************/
//LPT COUNTER set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_CNT_Write(U16_T CNT_DATA)
{
LPT->CNT =CNT_DATA;
}
/*************************************************************/
//LPT read counters
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
U16_T LPT_PRDR_Read(void)
{
return LPT->PRDR;
}
U16_T LPT_CMP_Read(void)
{
return LPT->CMP;
}
U16_T LPT_CNT_Read(void)
{
return LPT->CNT;
}
/*************************************************************/
//LPT ControlSet Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX)
{
LPT->CR |= SWSYNX| IDLESTX| PRDLDX| POLX| FLTDEBX| FLTDEBX| CMPLDX;
}
/*************************************************************/
//LPT SYNC Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX)
{
LPT->SYNCR |= TRGENX| OSTMDX| AREARMX;
}
/*************************************************************/
//LPT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA)
{
LPT->TRGFTCR |= SRCSELX| BLKINVX| CROSSMDX;
LPT->TRGFTWR |= OFFSET_DATA |(WINDOW_DATA<<16);
LPT->EVTRG |= TRGSRC0X |ESYN0OEX;
LPT->EVPS |=TRGEC0PRD_DATA;
}
void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA)
{
LPT->EVPS |= TRGEC0PRD_DATA |(TRGEV0CNT_DATA<<16);
}
void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA)
{
LPT->EVPS |= (TRGEV0CNT_DATA<<16);
}
void LPT_Soft_Trigger(void)
{
LPT->EVSWF = 0X01;
}
/*************************************************************/
// LPT start
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Start(void)
{
LPT->RSSR |= 0X01;
}
/*************************************************************/
// LPT stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Stop(void)
{
LPT->RSSR &= 0XFFFFFFFE;
}
/*************************************************************/
// LPT soft reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Soft_Reset(void)
{
LPT->RSSR |= (0X5<<12);
}
/*************************************************************/
// LPT soft reset at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_REARM_Write(void)
{
LPT->SYNCR |= (0X1<<16);
}
/*************************************************************/
// LPT soft read at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T LPT_REARM_Read(void)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=(LPT->SYNCR)&(1<<16);
if (dat)
{
value = 1;
}
return value;
}
/*************************************************************/
//LPT inturrpt Configure
//EntryParameter:LPT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X)
{
if (NewState != DISABLE)
{
LPT->IMCR |= LPT_IMSCR_X;
}
else
{
LPT->IMCR &= ~LPT_IMSCR_X;
}
}
/*************************************************************/
//LPT Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_INT_ENABLE(void)
{
INTC_ISER_WRITE(LPT_INT);
}
/*************************************************************/
//LPT Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_INT_DISABLE(void)
{
INTC_ICER_WRITE(LPT_INT);
}

817
Source/FWlib/apt32f102_syscon.c Normal file
View File

@@ -0,0 +1,817 @@
/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.09
* @date 2021/07/30
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_syscon.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the syscon registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_RST_VALUE(void) //reset value
{
//SYSCON->IDCCR=SYSCON_IDCCR_RST;
//SYSCON->GCER=SYSCON_GCER_RST;
//SYSCON->GCDR=SYSCON_GCDR_RST;
//SYSCON->GCSR=SYSCON_GCSR_RST;
//SYSCON->CKST=SYSCON_CKST_RST;
SYSCON->RAMCHK=SYSCON_RAMCHK_RST;
SYSCON->EFLCHK=SYSCON_EFLCHK_RST;
SYSCON->SCLKCR=SYSCON_SCLKCR_RST;
//SYSCON->PCLKCR=SYSCON_PCLKCR_RST;
//SYSCON->PCER0=SYSCON_PCER0_RST;
//SYSCON->PCDR0=SYSCON_PCDR0_RST;
//SYSCON->PCSR0=SYSCON_PCSR0_RST;
//SYSCON->PCER1=SYSCON_PCER1_RST;
//SYSCON->PCDR1=SYSCON_PCDR1_RST;
//SYSCON->PCSR1=SYSCON_PCSR1_RST;
SYSCON->OSTR=SYSCON_OSTR_RST;
SYSCON->LVDCR=SYSCON_LVDCR_RST;
//SYSCON->CLCR=SYSCON_CLCR_RST;
//SYSCON->PWRCR=SYSCON_PWRCR_RST;
//SYSCON->IMER=SYSCON_IMER_RST;
//SYSCON->IMDR=SYSCON_IMDR_RST;
//SYSCON->IMCR=SYSCON_IMCR_RST;
//SYSCON->IAR=SYSCON_IAR_RST;
//SYSCON->ICR=SYSCON_ICR_RST;
//SYSCON->RISR=SYSCON_RISR_RST;
//SYSCON->MISR=SYSCON_MISR_RST;
SYSCON->EXIRT=SYSCON_EXIRT_RST;
SYSCON->EXIFT=SYSCON_EXIFT_RST;
//SYSCON->EXIER=SYSCON_EXIER_RST;
//SYSCON->EXIDR=SYSCON_EXIDR_RST;
//SYSCON->EXIMR=SYSCON_EXIMR_RST;
//SYSCON->EXIAR=SYSCON_EXIAR_RST;
//SYSCON->EXICR=SYSCON_EXICR_RST;
//SYSCON->EXIRS=SYSCON_EXIRS_RST;
SYSCON->IWDCR=SYSCON_IWDCR_RST;
SYSCON->IWDCNT=SYSCON_IWDCNT_RST;
//SYSCON->PWROPT=SYSCON_PWROPT_RST;
SYSCON->EVTRG=SYSCON_EVTRG_RST;
SYSCON->EVPS=SYSCON_EVPS_RST;
SYSCON->EVSWF=SYSCON_EVSWF_RST;
// SYSCON->UREG0=SYSCON_UREG0_RST;
// SYSCON->UREG1=SYSCON_UREG1_RST;
// SYSCON->UREG2=SYSCON_UREG2_RST;
// SYSCON->UREG3=SYSCON_UREG3_RST;
}
/*************************************************************/
//EMOSC OSTR Config
//EM_CNT:0~0X3FF
//EM_GM:0~0X1F
//EM_FLEN;EM_FLEN_DIS,EM_FLEN_EN
//EM_FLSEL:EM_FLSEL_5ns,EM_FLSEL_10ns,EM_FLSEL_15ns,EM_FLSEL_20ns
/*************************************************************/
void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X)
{
SYSCON->OSTR=EM_CNT|(EM_GM<<11)|EM_LFSEL_X|EM_FLEN_X|EM_FLSEL_X;
}
/*************************************************************/
//SYSCON General Control
//EntryParameter:NewState:,ENDIS_X
//NewState:ENABLE,DISABLE
//ENDIS_X:ENDIS_ISOSC,ENDIS_IMOSC,ENDIS_EMOSC,ENDIS_HFOSC
//ReturnValue:NONE
/*************************************************************/
void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X )
{
if (NewState != DISABLE)
{
if(ENDIS_X==ENDIS_EMOSC)
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF00FFF)|0x00044000; //enable EMOSC PIN
SYSCON->GCER|=ENDIS_X; //enable SYSCON General Control
while(!(SYSCON->GCSR&ENDIS_X)); //check Enable?
switch(ENDIS_X)
{
case ENDIS_IMOSC:
while (!(SYSCON->CKST & ENDIS_IMOSC));
break;
case ENDIS_EMOSC:
while (!(SYSCON->CKST & ENDIS_EMOSC));
break;
case ENDIS_ISOSC:
while (!(SYSCON->CKST & ENDIS_ISOSC));
break;
case ENDIS_HFOSC:
while (!(SYSCON->CKST & ENDIS_HFOSC));
break;
case ENDIS_IDLE_PCLK:
break;
case ENDIS_SYSTICK:
break;
}
}
else
{
SYSCON->GCDR|=ENDIS_X; //disable SYSCON General Control
while(SYSCON->GCSR&ENDIS_X); //check Disable?
SYSCON->ICR|=ENDIS_X; //Clear ENDIS_X stable bit
}
}
/*************************************************************/
//Seleted system clk and seleted clk div
//EntryParameter:SYSCLK_X,HCLK_DIV_X,PCLK_DIV_X
//SYSCLK_X:SYSCLK_IMOSC,SYSCLK_EMOSC,SYSCLK_ISOSC,SYSCLK_HFOSC
//HCLK_DIV_X:HCLK_DIV_1/2/3/4/5/6/7/8/12/16/24/32/64/128/256
//PCLK_DIV_X:PCLK_DIV_1,PCLK_DIV_2,PCLK_DIV_4,PCLK_DIV_8,PCLK_DIV_16
//SystemClk_data_x:EMOSC_24M,EMOSC_16M,EMOSC_12M,EMOSC_8M,EMOSC_4M,EMOSC_36K,
//ISOSC,IMOSC,HFOSC_48M,HFOSC_24M,HFOSC_12M,HFOSC_6M
//ReturnValue:NONE
/*************************************************************/
void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x )
{
if(SystemClk_data_x==HFOSC_48M)
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X04|(0X00<<16); //High speed mode
}
if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==HFOSC_24M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X02|(0X00<<16); //Medium speed mode
}
if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==EMOSC_16M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X01|(0X00<<16); //Low speed mode
}
if((SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K)
||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_6M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X00|(0X00<<16); //Low speed mode
}
SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X;
while (!(SYSCON->CKST & (1<<8))); // waiting for sysclk stable
SYSCON->PCLKCR=PCLK_KEY|PCLK_DIV_X; //PCLK DIV 1 2 4 6 8 16
while(SYSCON->PCLKCR!=PCLK_DIV_X); //Wait PCLK DIV
}
/*************************************************************/
//clear system clk register
//ReturnValue:NONE
/*************************************************************/
void SystemCLK_Clear(void)
{
SYSCON->SCLKCR=0xd22d0000;
while(SYSCON->SCLKCR!=0);
}
/*************************************************************/
//SYSCON IMOSC SELECTE
//EntryParameter:IMOSC_SELECTE_X
//IMOSC_SELECTE_X:IMOSC_SELECTE_5556K,IMOSC_SELECTE_4194K;IMOSC_SELECTE_2097K;IMOSC_SELECTE_131K
//ReturnValue:NONE
/*************************************************************/
void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X)
{
//SYSCON_General_CMD(DISABLE,ENDIS_IMOSC); //disalbe IMOSC
SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFFC)|IMOSC_SELECTE_X; //IMOSC CLK selected
//SYSCON_General_CMD(ENABLE,ENDIS_IMOSC); //enable IMOSC
}
/*************************************************************/
//SYSCON HFOSC SELECTE
//EntryParameter:HFOSC_SELECTE_X
//HFOSC_SELECTE_X:HFOSC_SELECTE_48M,HFOSC_SELECTE_24M;HFOSC_SELECTE_12M;HFOSC_SELECTE_6M
//ReturnValue:NONE
/*************************************************************/
void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X)
{
SYSCON_General_CMD(DISABLE,ENDIS_HFOSC); //disable HFOSC
SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFCF)|HFOSC_SELECTE_X;
SYSCON_General_CMD(ENABLE,ENDIS_HFOSC); //enable HFOSC
}
/*************************************************************/
//WDT enable and disable
//EntryParameter:,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WDT_CMD(FunctionalStatus NewState)
{
if(NewState != DISABLE)
{
SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT;
while(!(SYSCON->IWDCR&Check_IWDT_BUSY));
}
else
{
SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT;
while(SYSCON->IWDCR&Check_IWDT_BUSY);
}
}
/*************************************************************/
//reload WDT CN
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void SYSCON_IWDCNT_Reload(void)
{
SYSCON->IWDCNT=CLR_IWDT;
}
/*************************************************************/
//IWDCNT Config
//EntryParameter:NewStateE_IWDT_SHORT,IWDT_TIME_X,IWDT_INTW_DIV_X
//NewStateE_IWDT_SHORT:ENABLE_IWDT_SHORT,DISABLE_IWDT_SHORT
//IWDT_TIME_X:IWDT_TIME_128MS,IWDT_TIME_256MS,IWDT_TIME_500MS,IWDT_TIME_1S,IWDT_TIME_2S,IWDT_TIME_3S,IWDT_TIME_4S,IWDT_TIME_8S
//IWDT_INTW_DIV_X:IWDT_INTW_DIV_1/2/3/4/4/5/6
//ReturnValue: NONE
/*************************************************************/
void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X )
{
SYSCON->IWDCR=IWDT_KEY|IWDT_TIME_X|IWDT_INTW_DIV_X;
}
/*************************************************************/
//LVD Config and set LVD INT
//EntryParameter:X_LVDEN,INTDET_LVL_X,RSTDET_LVL_X,X_LVD_INT
//X_LVDEN:ENABLE_LVDEN,DISABLE_LVDEN
//INTDET_LVL_X:INTDET_LVL_1_8V,INTDET_LVL_2_1V,INTDET_LVL_2_5V,INTDET_LVL_2_9V,INTDET_LVL_3_3V,INTDET_LVL_3_7V,INTDET_LVL_4_1V,INTDET_LVL_4_5V
//RSTDET_LVL_X:RSTDET_LVL_1_6V,RSTDET_LVL_2_0V,RSTDET_LVL_2_4V,RSTDET_LVL_2_8V,RSTDET_LVL_3_2V,RSTDET_LVL_3_6V,RSTDET_LVL_4_0V,RSTDET_LVL_4_4V
//X_LVD_INT:ENABLE_LVD_INT,DISABLE_LVD_INT
//INTDET_POL_X:INTDET_POL_fall,INTDET_POL_X_rise,INTDET_POL_X_riseORfall
//ReturnValue: NONE
/*************************************************************/
void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X)
{
//SYSCON->LVDCR=LVD_KEY;
SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT|INTDET_POL_X;
}
/*************************************************************/
//LVD INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Enable(void)
{
SYSCON->ICR = LVD_INT_ST; //clear LVD INT status
SYSCON->IMER |= LVD_INT_ST;
}
/*************************************************************/
//LVD INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Disable(void)
{
SYSCON->IMDR |= LVD_INT_ST;
}
/*************************************************************/
//WDT INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void IWDT_Int_Enable(void)
{
SYSCON->ICR = IWDT_INT_ST; //clear LVD INT status
SYSCON->IMER |= IWDT_INT_ST;
}
/*************************************************************/
//WDT INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void IWDT_Int_Disable(void)
{
SYSCON->IMDR |= IWDT_INT_ST;
}
/*************************************************************/
//Reset status.
//EntryParameter:NONE
//ReturnValue: rsr_dat
//rsr_dat=0x01 power on reset
//rsr_dat=0x02 low voltage reset
//rsr_dat=0x04 ex-pin reset
//rsr_dat=0x10 wdt reset
//rsr_dat=0x40 ex clock invalid reset
//rsr_dat=0x80 cpu request reset
//rsr_dat=0x100 software reset
/*************************************************************/
U32_T Read_Reset_Status(void)
{
return (SYSCON->RSR & 0x1ff);
}
/*************************************************************/
//external trigger Mode Selection Functions
//EntryParameter:NewState,EXIPIN,EXI_tringer_mode
//NewState:ENABLE,DISABLE
//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13
//EXI_tringer_mode:_EXIRT,_EXIFT
//ReturnValue: LVD detection flag
/*************************************************************/
void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode)
{
switch(EXI_tringer_mode)
{
case _EXIRT:
if(NewState != DISABLE)
{
SYSCON->EXIRT |=EXIPIN;
}
else
{
SYSCON->EXIRT &=~EXIPIN;
}
break;
case _EXIFT:
if(NewState != DISABLE)
{
SYSCON->EXIFT |=EXIPIN;
}
else
{
SYSCON->EXIFT &=~EXIPIN;
}
break;
}
}
/*************************************************************/
//external interrupt enable and disable
//EntryParameter:NewState,EXIPIN,* GPIOX
//* GPIOX:GPIOA,GPIOB
//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN)
{
SYSCON->EXICR = 0X3FFF; //Claer EXI INT status
if(NewState != DISABLE)
{
SYSCON->EXIER|=EXIPIN; //EXI4 interrupt enable
while(!(SYSCON->EXIMR&EXIPIN)); //Check EXI is enabled or not
SYSCON->EXICR |=EXIPIN; // Clear EXI status bit
}
else
{
SYSCON->EXIDR|=EXIPIN;
}
}
/*************************************************************/
//GPIO EXTI interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE)
{
GPIOX->IECR=GPIO_IECR_VALUE;
}
/*************************************************************/
//PLCK goto SLEEP mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_idle_mode(void)
{
asm ("doze"); // Enter sleep mode
}
/*************************************************************/
//PLCK goto SLEEP mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_deepsleep_mode(void)
{
SYSCON->WKCR=0X3F<<8;
asm ("stop");
}
/*************************************************************/
//EXI0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Enable(void)
{
INTC_ISER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Disable(void)
{
INTC_ICER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Enable(void)
{
INTC_ISER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI1 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Disable(void)
{
INTC_ICER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI2 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Enable(void)
{
INTC_ISER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI2 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Disable(void)
{
INTC_ICER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI3 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Enable(void)
{
INTC_ISER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI3 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Disable(void)
{
INTC_ICER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI4 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Enable(void)
{
INTC_ISER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI4 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Disable(void)
{
INTC_ICER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI0 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI1 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI1 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI2 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI2 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI3 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI3 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI4 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI4 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI4_INT);
}
/*************************************************************/
//SYSCON Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Enable(void)
{
INTC_ISER_WRITE(SYSCON_INT);
}
/*************************************************************/
//SYSCON Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Disable(void)
{
INTC_ICER_WRITE(SYSCON_INT);
}
/*************************************************************/
//SYSCON Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Enable(void)
{
INTC_IWER_WRITE(SYSCON_INT);
}
/*************************************************************/
//set PA0.0/PA0.8 as CLO output
//EntryParameter:CLO_PA02/CLO_PA08
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io)
{
if (clo_io==CLO_PA02)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000700;
}
if (clo_io==CLO_PA08)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000007;
}
}
/*************************************************************/
//set CLO clk and div
//EntryParameter:clomxr/clodivr
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr)
{
SYSCON->OPT1=(SYSCON->OPT1 & 0XFFFF00FF)|(clomxr<<8)|(clodivr<<12);
}
/*************************************************************/
//SYSCON Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(SYSCON_INT);
}
/*************************************************************/
//READ CIF0 data
//EntryParameter:None
//ReturnValue:VALUE
/*************************************************************/
U32_T SYSCON_Read_CINF0(void)
{
U32_T value = 0;
value=SYSCON->CINF0;
return value;
}
/*************************************************************/
//READ CIF1 data
//EntryParameter:None
//ReturnValue:VALUE
/*************************************************************/
U32_T SYSCON_Read_CINF1(void)
{
U32_T value = 0;
value=SYSCON->CINF1;
return value;
}
/*************************************************************/
//Software_Reset
//EntryParameter:None
//ReturnValue:MCU reset
/*************************************************************/
void SYSCON_Software_Reset(void)
{
SYSCON->IDCCR=IDCCR_KEY|SWRST;
}
/*************************************************************/
//Interrupt Priority initial
//EntryParameter:00/40/80/C0
//----------------------
//CORET_INT IRQ0
//SYSCON_INT IRQ1
//IFC_INT IRQ2
//ADC_INT IRQ3
//----------------------
//EPT0_INT IRQ4
//****DUMMY IRQ5
//WWDT_INT IRQ6
//EXI0_INT IRQ7
//----------------------
//EXI1_INT IRQ8
//GPT0_INT IRQ9
//****DUMMY IRQ10
//****DUMMY IRQ11
//----------------------
//RTC_INT IRQ12
//UART0_INT IRQ13
//UART1_INT IRQ14
//UART2_INT IRQ15
//----------------------
//****DUMMY IRQ16
//I2C_INT IRQ17
//****DUMMY IRQ18
//SPI_INT IRQ19
//----------------------
//SIO_INT IRQ20
//EXI2_INT IRQ21
//EXI3_INT IRQ22
//EXI4_INT IRQ23
//----------------------
//CA_INT IRQ24
//TKEY_INT IRQ25
//LPT_INT IRQ26
//****DUMMY IRQ27
//----------------------
//BT0_INT IRQ28
//BT1_INT IRQ29
//----------------------
//ReturnValue:None
//00:Priority 0 highest
//40:Priority 1
//80:Priority 2
//C0:Priority 3 lowest
/*************************************************************/
void SYSCON_INT_Priority(void)
{
INTC_IPR0_WRITE(0XC0C0C0C0); //IQR0-3 low bit-->high bit
INTC_IPR1_WRITE(0XC0C0C0C0); //IQR4-7
INTC_IPR2_WRITE(0XC0C0C0C0); //IQR8-11
INTC_IPR3_WRITE(0XC0C0C0C0); //IQR12-15
INTC_IPR4_WRITE(0XC0C0C0C0); //IQR16-19
INTC_IPR5_WRITE(0XC0C0C0C0); //IQR20-23
INTC_IPR6_WRITE(0XC0C000C0); //IQR24-27
INTC_IPR7_WRITE(0XC0C0C0C0); //IQR28-31
}
/*************************************************************/
//Set Interrupt Priority
//EntryParameter:
//int_name:CORET_IRQ~BT1_IRQ
//int_level:0~3 0=highest 3=lowest
//ReturnValue:None
/*************************************************************/
void Set_INT_Priority(U8_T int_name,U8_T int_level)
{
U8_T i_temp,j_temp;
U32_T k_temp;
i_temp=(int_name%4)*8;
j_temp=int_name/4;
k_temp=CK801 -> IPR[j_temp]&(~(0xff<<i_temp));
CK801 -> IPR[j_temp]=k_temp|((int_level*0x40)<<(i_temp));
}
/*************************************************************/
//IO REMAP
//EntryParameter:GPIOA0(0,1,2,3,4,5,6,7) GPIOB0(2,3),GPIOA0(8,9,10,11,12,13)
//0x00=I2C_SCL 0X01=I2C_SDA 0X02=GPT_CHA 0X03=GPT_CHB
//0X04=SPI_MOSI 0X05=SPI_MISO 0X06=SPI_SCK 0X07=SPI_NSS
//0x00=UART0_RX 0X01=UART0_TX 0X02=EPT_CHAX 0X03=PT_CHBX
//0X04=PT_CHCX 0X05=PT_CHAY 0X06=PT_CHBY 0X07=PT_CHCY
//ReturnValue:NONE
/*************************************************************/
void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data)
{
U8_T i;
if(iomap_data&0x10)
{
iomap_data=iomap_data&0X0F;
if(iomap_data==0)
{
for(i=0;i<28;i+=4)
{
if((SYSCON->IOMAP1&(0xf<<i))==0)
{
SYSCON->IOMAP1=SYSCON->IOMAP1|(0xf<<i);
}
}
}
if(bit==2){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;}
if(bit==3){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;}
if(bit==8){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFFF0) | 0x0000000A;}
if(bit==9){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFF0F) | 0x000000A0;}
if(bit==10){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFF0FF) | 0x00000A00;}
if(bit==11){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFF0FFF) | 0x0000A000;}
if(bit==12){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFF0FFFF) | 0x000A0000;}
if(bit==13){SYSCON->IOMAP1=(SYSCON->IOMAP1&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFF0FFFFF) | 0x00A00000;}
}
else
{
if(iomap_data==0)
{
for(i=0;i<28;i+=4)
{
if((SYSCON->IOMAP0&(0xf<<i))==0)
{
SYSCON->IOMAP0=SYSCON->IOMAP0|(0xf<<i);
}
}
}
if(bit==0){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFFF0) | 0x0000000A;}
if(bit==1){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFF0F) | 0x000000A0;}
if(bit==2){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;}
if(bit==3){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;}
if(bit==4){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFF0FFFF) | 0x000A0000;}
if(bit==5){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFF0FFFFF) | 0x00A00000;}
if(bit==6){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONLR =((GPIOx)->CONLR&0XF0FFFFFF) | 0x0A000000;}
if(bit==7){SYSCON->IOMAP0=(SYSCON->IOMAP0&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONLR =((GPIOx)->CONLR&0X0FFFFFFF) | 0x0A0000000;}
}
}
/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/

403
Source/FWlib/apt32f102_uart.c Normal file
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@@ -0,0 +1,403 @@
/*
******************************************************************************
* @file apt32f102_uart.c
* @author APT AE Team
* @version V1.15
* @date 2022/09/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_uart.h"
#include "apt32f102_syscon.h"
/* define --------------------------------------------------------------------*/
volatile U8_T RxDataFlag=0;
volatile U8_T TxDataFlag=0;
volatile U8_T f_Uart_send_Complete;
volatile U16_T Uart_send_Length_temp;
volatile U8_T Uart_send_Length;
volatile U8_T Uart_buffer[UART_BUFSIZE];
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//UART RESET,CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_DeInit(void)
{
UART0->DATA = UART_RESET_VALUE;
UART0->SR = UART_RESET_VALUE;
UART0->CTRL = UART_RESET_VALUE;
UART0->ISR = UART_RESET_VALUE;
UART0->BRDIV =UART_RESET_VALUE;
}
void UART1_DeInit(void)
{
UART1->DATA = UART_RESET_VALUE;
UART1->SR = UART_RESET_VALUE;
UART1->CTRL = UART_RESET_VALUE;
UART1->ISR = UART_RESET_VALUE;
UART1->BRDIV =UART_RESET_VALUE;
}
void UART2_DeInit(void)
{
UART2->DATA = UART_RESET_VALUE;
UART2->SR = UART_RESET_VALUE;
UART2->CTRL = UART_RESET_VALUE;
UART2->ISR = UART_RESET_VALUE;
UART2->BRDIV =UART_RESET_VALUE;
}
/*************************************************************/
//UART0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_Int_Enable(void)
{
UART0->ISR=0x0F; //clear UART0 INT status
INTC_ISER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_Int_Disable(void)
{
INTC_ICER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Enable(void)
{
UART1->ISR=0x0F; //clear UART1 INT status
INTC_ISER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt Disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Disable(void)
{
INTC_ICER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_Int_Enable(void)
{
UART2->ISR=0x0F; //clear UART1 INT status
INTC_ISER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt Disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_Int_Disable(void)
{
INTC_ICER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART0_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART0_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART1_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART1_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART2_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART2_INT);
}
/*************************************************************/
//UART IO Init
//EntryParameter:IO_UARTX,UART_IO_G
//IO_UARTX:IO_UART0,IO_UART1
//UART_IO_G:0 1
//ReturnValue:NONE
/*************************************************************/
void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G)
{
if (IO_UART_NUM==IO_UART0)
{
if(UART_IO_G==0)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000044; //PA0.1->RXD0, PA0.0->TXD0
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00700000; //PA0.5->RXD0, PA0.12->TXD0
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00070000;
}
}
if (IO_UART_NUM==IO_UART1)
{
if(UART_IO_G==0)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000007; //PA0.13->RXD1, PB0.0->TXD1
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00700000;
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF) | 0X00077000; //PA0.4->RXD1, PA0.3->TXD1
}
else if(UART_IO_G==2)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0X77000000; //PA0.15->RXD1, PA0.14->TXD1
}
}
if (IO_UART_NUM==IO_UART2)
{
if(UART_IO_G==0)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000077; //PA0.0->RXD2, PA0.1->TXD2
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X00FFFFFF) | 0X77000000; //PA0.7->RXD2, PA0.6->TXD2
}
else if(UART_IO_G==2)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2
}
}
}
/*************************************************************/
//UART Init
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//e.g:
//sys_clk@24MHz, 24/4(div)=6MHz, 6000000/115200bps=52,baudrate_u16=52
//sys_clk@24MHz, 24/2(div)=12MHz, 12000000/115200bps=104,baudrate_u16=104
//ReturnValue:NONE
/*************************************************************/
void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | PAR_DAT | UART_TX_DONE_INT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART init and enable RX,TX interrupt
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//ReturnValue:NONE
/*************************************************************/
void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT | UART_TX_INT | PAR_DAT | UART_TX_DONE_INT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART init and enable RX interrupt
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//ReturnValue:NONE
/*************************************************************/
void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT |PAR_DAT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART Close
//EntryParameter:UART0,UART1,UART2
//ReturnValue:NONE
/*************************************************************/
void UARTClose(CSP_UART_T *uart)
{
// Set Transmitter Disable
CSP_UART_SET_CTRL(uart, 0x00);
}
/*************************************************************/
//UART TX Byte loop send
//EntryParameter:UART0,UART1,UART2,txdata_u8
//ReturnValue:NONE
/*************************************************************/
void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8)
{
unsigned int DataI;
// Write the transmit buffer
CSP_UART_SET_DATA(uart,txdata_u8);
do
{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_TX_FULL;
}
while(DataI == UART_TX_FULL); //Loop when tx is full
}
/*************************************************************/
//UART Transmit
//EntryParameter:UART0,UART1,UART2,sourceAddress_u16,length_u16
//ReturnValue:NONE
/*************************************************************/
void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16)
{
unsigned int DataI,DataJ;
for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
{
CSP_UART_SET_DATA(uart,*sourceAddress_u16++);
do{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_TX_FULL;
SYSCON_IWDCNT_Reload();
}while(DataI == UART_TX_FULL); //Loop when tx is full
SYSCON_IWDCNT_Reload();
}
}
/*************************************************************/
//UART INT Transmit
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void UARTTTransmit_data_set(CSP_UART_T *uart )
{
if(!f_Uart_send_Complete)
{
f_Uart_send_Complete=1;
Uart_send_Length_temp++;
CSP_UART_SET_DATA(uart,Uart_buffer[0]);
}
}
void UARTTransmit_INT_Send(CSP_UART_T *uart )
{
if(f_Uart_send_Complete)
{
if(Uart_send_Length_temp>=Uart_send_Length)
{
f_Uart_send_Complete=0;
Uart_send_Length_temp=0;
}
else
{
CSP_UART_SET_DATA(uart,Uart_buffer[Uart_send_Length_temp++]);
}
}
}
/*************************************************************/
//UART RX Byte
//EntryParameter:UART0,UART1,UART2,Rxdata_u16
//ReturnValue:NONE
/*************************************************************/
U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16)
{
unsigned int DataI;
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_RX_FULL;
if(DataI != UART_RX_FULL) //Loop when rx is not full
return FALSE;
else
{
*Rxdata_u16 = CSP_UART_GET_DATA(uart);
return TRUE;
}
}
/*************************************************************/
//UART RX Return Byte
//EntryParameter:UART0,UART1,UART2
//ReturnValue:(uart)->DATA
/*************************************************************/
U8_T UART_ReturnRxByte(CSP_UART_T *uart)
{
RxDataFlag = FALSE;
while(RxDataFlag != TRUE);
return CSP_UART_GET_DATA(uart);
}
/*************************************************************/
//UART Receive
//EntryParameter:UART0,UART1,UART2，destAddress_u16，length_u16
//ReturnValue:FALSE/TRUE
/*************************************************************/
U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16)
{
unsigned int DataI,DataJ,LoopTime;
DataJ = 0;
LoopTime = 0;
do{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_RX_FULL;
if(DataI == UART_RX_FULL) //Loop when rx is full
{
*destAddress_u16++ = CSP_UART_GET_DATA(uart);
DataJ++;
LoopTime = 0;
}
if(LoopTime ++ >= 0xfff0)
return FALSE;
}while(DataJ < length_u16);
return TRUE;
}

90
Source/FWlib/apt32f102_wwdt.c Normal file
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@@ -0,0 +1,90 @@
/*
******************************************************************************
* @file apt32f102_wwdt.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_wwdt.h"
/*************************************************************/
//WWDT RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_DeInit(void)
{
WWDT->CR = 0x000000FF;
WWDT->CFGR = 0x000000FF;
WWDT->RISR = WWDT_RESET_VALUE;
WWDT->MISR = WWDT_RESET_VALUE;
WWDT->IMCR = WWDT_RESET_VALUE;
WWDT->ICR = WWDT_RESET_VALUE;
}
/*************************************************************/
//WWDT CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX)
{
WWDT->CFGR =WND_DATA;
WWDT->CFGR |= PSCDIVX |DBGENX;
}
/*************************************************************/
//WWDT ENABLE/DISABLE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
WWDT->CR |= 0x01<<8;
}
else
{
WWDT->CR &= 0xfffffeff;
}
}
/*************************************************************/
//WWDT load data
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CNT_Load(U8_T cnt_data)
{
WWDT->CR |= cnt_data; //SET
}
/*************************************************************/
//WWDT INT ENABLE/DISABLE
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void WWDT_Int_Config(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
WWDT->ICR = WWDT_EVI;
WWDT->IMCR |= WWDT_EVI;
INTC_ISER_WRITE(WWDT_INT);
}
else
{
WWDT->IMCR &= ~WWDT_EVI; //CLR
INTC_ICER_WRITE(WWDT_INT);
}
}

201
Source/MD203F8P.mk Normal file
View File

@@ -0,0 +1,201 @@
##
## Auto Generated makefile by CDK
## Do not modify this file, and any manual changes will be erased!!!
##
## BuildSet
ProjectName :=MD203F8P
ConfigurationName :=BuildSet
WorkspacePath :=./
ProjectPath :=./
IntermediateDirectory :=Obj
OutDir :=$(IntermediateDirectory)
User :=cc
Date :=06/02/2026
CDKPath :=D:/C-Sky/CDK
ToolchainPath :=D:/C-Sky/CDKRepo/Toolchain/CKV2ElfMinilib/V3.10.29/R/
LinkerName :=csky-elfabiv2-gcc
LinkerNameoption :=
SIZE :=csky-elfabiv2-size
READELF :=csky-elfabiv2-readelf
CHECKSUM :=crc32
SharedObjectLinkerName :=
ObjectSuffix :=.o
DependSuffix :=.d
PreprocessSuffix :=.i
DisassemSuffix :=.asm
IHexSuffix :=.ihex
BinSuffix :=.bin
ExeSuffix :=.elf
LibSuffix :=.a
DebugSwitch :=-g
IncludeSwitch :=-I
LibrarySwitch :=-l
OutputSwitch :=-o
ElfInfoSwitch :=-hlS
LibraryPathSwitch :=-L
PreprocessorSwitch :=-D
UnPreprocessorSwitch :=-U
SourceSwitch :=-c
ObjdumpSwitch :=-S
ObjcopySwitch :=-O ihex
ObjcopyBinSwitch :=-O binary
OutputFile :=MD203_Boot_V05_20260206
ObjectSwitch :=-o
ArchiveOutputSwitch :=
PreprocessOnlySwitch :=-E
PreprocessOnlyDisableLineSwitch :=-P
ObjectsFileList :=$(IntermediateDirectory)/MD203F8P.txt
MakeDirCommand :=mkdir
LinkOptions := -mcpu=ck801 -nostartfiles -Wl,--gc-sections -T"$(ProjectPath)/ckcpu.ld" -pipe
LinkOtherFlagsOption := -Wl,--ckmap=$(ProjectPath)/Lst/$(OutputFile).map
IncludePackagePath :=
IncludeCPath := $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/ $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_core/include/ $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_driver/include/ $(IncludeSwitch). $(IncludeSwitch)SYSTEM/inc $(IncludeSwitch)USRCTRL/inc $(IncludeSwitch)include
IncludeAPath := $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/ $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_core/include/ $(IncludeSwitch)D:/C-Sky/CDK/CSKY/csi/csi_driver/include/ $(IncludeSwitch). $(IncludeSwitch)SYSTEM $(IncludeSwitch)SYSTEM/inc $(IncludeSwitch)USRCTRL/inc
Libs := -Wl,--start-group -Wl,--end-group $(LibrarySwitch)_102ClkCalib_1_03
ArLibs := "lib_102ClkCalib_1_03"
PackagesLibPath :=
LibPath :=$(LibraryPathSwitch). $(PackagesLibPath)
##
## Common variables
## AR, CXX, CC, AS, CXXFLAGS and CFLAGS can be overriden using an environment variables
##
AR :=csky-elfabiv2-ar rcu
CXX :=csky-elfabiv2-g++
CC :=csky-elfabiv2-gcc
AS :=csky-elfabiv2-gcc
OBJDUMP :=csky-elfabiv2-objdump
OBJCOPY :=csky-elfabiv2-objcopy
CXXFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe
CFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe
ASFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CKCPU_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Wa,-gdwarf-2 -pipe
PreprocessFlags :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe
Objects0=$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) $(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) $(IntermediateDirectory)/arch_apt32f102_iostring$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_syscon$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_gpio$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_wwdt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_bt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_uart$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_ifc$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_lpt$(ObjectSuffix) \
$(IntermediateDirectory)/main$(ObjectSuffix) $(IntermediateDirectory)/mcu_initial$(ObjectSuffix) $(IntermediateDirectory)/mcu_interrupt$(ObjectSuffix) $(IntermediateDirectory)/drivers_apt32f102$(ObjectSuffix) $(IntermediateDirectory)/drivers_apt32f102_ck801$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_uart$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_eeprom$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_Bootload_fun$(ObjectSuffix) $(IntermediateDirectory)/__rt_entry$(ObjectSuffix)
Objects=$(Objects0)
##
## Main Build Targets
##
.PHONY: all
all: $(IntermediateDirectory)/$(OutputFile)
$(IntermediateDirectory)/$(OutputFile): $(Objects) Always_Link
$(LinkerName) $(OutputSwitch) $(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) $(LinkerNameoption) -Wl,--ckmap=$(ProjectPath)/Lst/$(OutputFile).map @$(ObjectsFileList) $(LinkOptions) $(LibPath) $(Libs) $(LinkOtherFlagsOption)
-@mv $(ProjectPath)/Lst/$(OutputFile).map $(ProjectPath)/Lst/$(OutputFile).temp && $(READELF) $(ElfInfoSwitch) $(ProjectPath)/Obj/$(OutputFile)$(ExeSuffix) > $(ProjectPath)/Lst/$(OutputFile).map && echo ====================================================================== >> $(ProjectPath)/Lst/$(OutputFile).map && cat $(ProjectPath)/Lst/$(OutputFile).temp >> $(ProjectPath)/Lst/$(OutputFile).map && rm -rf $(ProjectPath)/Lst/$(OutputFile).temp
$(OBJCOPY) $(ObjcopySwitch) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) $(ProjectPath)/Obj/$(OutputFile)$(IHexSuffix)
$(OBJDUMP) $(ObjdumpSwitch) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) > $(ProjectPath)/Lst/$(OutputFile)$(DisassemSuffix)
@echo size of target:
@$(SIZE) $(ProjectPath)$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix)
@echo -n checksum value of target:
@$(CHECKSUM) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix)
@MD203F8P.modify.bat $(IntermediateDirectory) $(OutputFile)$(ExeSuffix)
Always_Link:
##
## Objects
##
$(IntermediateDirectory)/arch_crt0$(ObjectSuffix): arch/crt0.S
$(AS) $(SourceSwitch) arch/crt0.S $(ASFLAGS) -MMD -MP -MT$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) -MF$(IntermediateDirectory)/arch_crt0$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) $(IncludeAPath) $(IncludePackagePath)
Lst/arch_crt0$(PreprocessSuffix): arch/crt0.S
$(CC) $(CFLAGS)$(IncludeAPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/arch_crt0$(PreprocessSuffix) arch/crt0.S
$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix): arch/mem_init.c
$(CC) $(SourceSwitch) arch/mem_init.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) -MF$(IntermediateDirectory)/arch_mem_init$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/arch_mem_init$(PreprocessSuffix): arch/mem_init.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/arch_mem_init$(PreprocessSuffix) arch/mem_init.c
$(IntermediateDirectory)/arch_apt32f102_iostring$(ObjectSuffix): arch/apt32f102_iostring.c
$(CC) $(SourceSwitch) arch/apt32f102_iostring.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/arch_apt32f102_iostring$(ObjectSuffix) -MF$(IntermediateDirectory)/arch_apt32f102_iostring$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/arch_apt32f102_iostring$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/arch_apt32f102_iostring$(PreprocessSuffix): arch/apt32f102_iostring.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/arch_apt32f102_iostring$(PreprocessSuffix) arch/apt32f102_iostring.c
$(IntermediateDirectory)/FWlib_apt32f102_syscon$(ObjectSuffix): FWlib/apt32f102_syscon.c
$(CC) $(SourceSwitch) FWlib/apt32f102_syscon.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_syscon$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_syscon$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_syscon$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_syscon$(PreprocessSuffix): FWlib/apt32f102_syscon.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_syscon$(PreprocessSuffix) FWlib/apt32f102_syscon.c
$(IntermediateDirectory)/FWlib_apt32f102_gpio$(ObjectSuffix): FWlib/apt32f102_gpio.c
$(CC) $(SourceSwitch) FWlib/apt32f102_gpio.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_gpio$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_gpio$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_gpio$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_gpio$(PreprocessSuffix): FWlib/apt32f102_gpio.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_gpio$(PreprocessSuffix) FWlib/apt32f102_gpio.c
$(IntermediateDirectory)/FWlib_apt32f102_wwdt$(ObjectSuffix): FWlib/apt32f102_wwdt.c
$(CC) $(SourceSwitch) FWlib/apt32f102_wwdt.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_wwdt$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_wwdt$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_wwdt$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_wwdt$(PreprocessSuffix): FWlib/apt32f102_wwdt.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_wwdt$(PreprocessSuffix) FWlib/apt32f102_wwdt.c
$(IntermediateDirectory)/FWlib_apt32f102_bt$(ObjectSuffix): FWlib/apt32f102_bt.c
$(CC) $(SourceSwitch) FWlib/apt32f102_bt.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_bt$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_bt$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_bt$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_bt$(PreprocessSuffix): FWlib/apt32f102_bt.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_bt$(PreprocessSuffix) FWlib/apt32f102_bt.c
$(IntermediateDirectory)/FWlib_apt32f102_uart$(ObjectSuffix): FWlib/apt32f102_uart.c
$(CC) $(SourceSwitch) FWlib/apt32f102_uart.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_uart$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_uart$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_uart$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_uart$(PreprocessSuffix): FWlib/apt32f102_uart.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_uart$(PreprocessSuffix) FWlib/apt32f102_uart.c
$(IntermediateDirectory)/FWlib_apt32f102_ifc$(ObjectSuffix): FWlib/apt32f102_ifc.c
$(CC) $(SourceSwitch) FWlib/apt32f102_ifc.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_ifc$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_ifc$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_ifc$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_ifc$(PreprocessSuffix): FWlib/apt32f102_ifc.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_ifc$(PreprocessSuffix) FWlib/apt32f102_ifc.c
$(IntermediateDirectory)/FWlib_apt32f102_lpt$(ObjectSuffix): FWlib/apt32f102_lpt.c
$(CC) $(SourceSwitch) FWlib/apt32f102_lpt.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/FWlib_apt32f102_lpt$(ObjectSuffix) -MF$(IntermediateDirectory)/FWlib_apt32f102_lpt$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/FWlib_apt32f102_lpt$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/FWlib_apt32f102_lpt$(PreprocessSuffix): FWlib/apt32f102_lpt.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/FWlib_apt32f102_lpt$(PreprocessSuffix) FWlib/apt32f102_lpt.c
$(IntermediateDirectory)/main$(ObjectSuffix): main.c
$(CC) $(SourceSwitch) main.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/main$(ObjectSuffix) -MF$(IntermediateDirectory)/main$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/main$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/main$(PreprocessSuffix): main.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/main$(PreprocessSuffix) main.c
$(IntermediateDirectory)/mcu_initial$(ObjectSuffix): mcu_initial.c
$(CC) $(SourceSwitch) mcu_initial.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/mcu_initial$(ObjectSuffix) -MF$(IntermediateDirectory)/mcu_initial$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/mcu_initial$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/mcu_initial$(PreprocessSuffix): mcu_initial.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/mcu_initial$(PreprocessSuffix) mcu_initial.c
$(IntermediateDirectory)/mcu_interrupt$(ObjectSuffix): mcu_interrupt.c
$(CC) $(SourceSwitch) mcu_interrupt.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/mcu_interrupt$(ObjectSuffix) -MF$(IntermediateDirectory)/mcu_interrupt$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/mcu_interrupt$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/mcu_interrupt$(PreprocessSuffix): mcu_interrupt.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/mcu_interrupt$(PreprocessSuffix) mcu_interrupt.c
$(IntermediateDirectory)/drivers_apt32f102$(ObjectSuffix): drivers/apt32f102.c
$(CC) $(SourceSwitch) drivers/apt32f102.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/drivers_apt32f102$(ObjectSuffix) -MF$(IntermediateDirectory)/drivers_apt32f102$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/drivers_apt32f102$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/drivers_apt32f102$(PreprocessSuffix): drivers/apt32f102.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/drivers_apt32f102$(PreprocessSuffix) drivers/apt32f102.c
$(IntermediateDirectory)/drivers_apt32f102_ck801$(ObjectSuffix): drivers/apt32f102_ck801.c
$(CC) $(SourceSwitch) drivers/apt32f102_ck801.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/drivers_apt32f102_ck801$(ObjectSuffix) -MF$(IntermediateDirectory)/drivers_apt32f102_ck801$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/drivers_apt32f102_ck801$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/drivers_apt32f102_ck801$(PreprocessSuffix): drivers/apt32f102_ck801.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/drivers_apt32f102_ck801$(PreprocessSuffix) drivers/apt32f102_ck801.c
$(IntermediateDirectory)/SYSTEM_uart$(ObjectSuffix): SYSTEM/uart.c
$(CC) $(SourceSwitch) SYSTEM/uart.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/SYSTEM_uart$(ObjectSuffix) -MF$(IntermediateDirectory)/SYSTEM_uart$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/SYSTEM_uart$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/SYSTEM_uart$(PreprocessSuffix): SYSTEM/uart.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/SYSTEM_uart$(PreprocessSuffix) SYSTEM/uart.c
$(IntermediateDirectory)/SYSTEM_eeprom$(ObjectSuffix): SYSTEM/eeprom.c
$(CC) $(SourceSwitch) SYSTEM/eeprom.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/SYSTEM_eeprom$(ObjectSuffix) -MF$(IntermediateDirectory)/SYSTEM_eeprom$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/SYSTEM_eeprom$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/SYSTEM_eeprom$(PreprocessSuffix): SYSTEM/eeprom.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/SYSTEM_eeprom$(PreprocessSuffix) SYSTEM/eeprom.c
$(IntermediateDirectory)/SYSTEM_Bootload_fun$(ObjectSuffix): SYSTEM/Bootload_fun.c
$(CC) $(SourceSwitch) SYSTEM/Bootload_fun.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/SYSTEM_Bootload_fun$(ObjectSuffix) -MF$(IntermediateDirectory)/SYSTEM_Bootload_fun$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/SYSTEM_Bootload_fun$(ObjectSuffix) $(IncludeCPath) $(IncludePackagePath)
Lst/SYSTEM_Bootload_fun$(PreprocessSuffix): SYSTEM/Bootload_fun.c
$(CC) $(CFLAGS)$(IncludeCPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/SYSTEM_Bootload_fun$(PreprocessSuffix) SYSTEM/Bootload_fun.c
$(IntermediateDirectory)/__rt_entry$(ObjectSuffix): $(IntermediateDirectory)/__rt_entry$(DependSuffix)
@$(AS) $(SourceSwitch) $(ProjectPath)/$(IntermediateDirectory)/__rt_entry.S $(ASFLAGS) $(ObjectSwitch)$(IntermediateDirectory)/__rt_entry$(ObjectSuffix) $(IncludeAPath)
$(IntermediateDirectory)/__rt_entry$(DependSuffix):
@$(CC) $(CFLAGS) $(IncludeAPath) -MG -MP -MT$(IntermediateDirectory)/__rt_entry$(ObjectSuffix) -MF$(IntermediateDirectory)/__rt_entry$(DependSuffix) -MM $(ProjectPath)/$(IntermediateDirectory)/__rt_entry.S
-include $(IntermediateDirectory)/*$(DependSuffix)

3
Source/MD203F8P.modify.bat Normal file
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@@ -0,0 +1,3 @@
@echo off
SET PATH=%Systemroot%\System32;%PATH%
forfiles.exe -P "%1" -M %2 -C "cmd /c echo %1/%2 is modified at: @fdate @ftime" | findstr modified

8
Source/Makefile Normal file
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@@ -0,0 +1,8 @@
.PHONY: clean All
All:
@echo "----------Building project:[ apt32f102 - BuildSet ]----------"
@cd "C:\Users\yupp.APT-HZ\Desktop\APT32F102_Release_V0_50_20190715\Source" && make -f "apt32f102.mk"
clean:
@echo "----------Cleaning project:[ apt32f102 - BuildSet ]----------"
@cd "C:\Users\yupp.APT-HZ\Desktop\APT32F102_Release_V0_50_20190715\Source" && make -f "apt32f102.mk" clean

1
Source/Obj/MD203F8P.txt Normal file
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@@ -0,0 +1 @@
Obj/arch_crt0.o Obj/arch_mem_init.o Obj/arch_apt32f102_iostring.o Obj/FWlib_apt32f102_syscon.o Obj/FWlib_apt32f102_gpio.o Obj/FWlib_apt32f102_wwdt.o Obj/FWlib_apt32f102_bt.o Obj/FWlib_apt32f102_uart.o Obj/FWlib_apt32f102_ifc.o Obj/FWlib_apt32f102_lpt.o Obj/main.o Obj/mcu_initial.o Obj/mcu_interrupt.o Obj/drivers_apt32f102.o Obj/drivers_apt32f102_ck801.o Obj/SYSTEM_uart.o Obj/SYSTEM_eeprom.o Obj/SYSTEM_Bootload_fun.o Obj/__rt_entry.o

BIN
Source/Obj/MD203_Boot_V05_20260206.elf Normal file
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Binary file not shown.

661
Source/Obj/MD203_Boot_V05_20260206.ihex Normal file
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@@ -0,0 +1,661 @@
:100000000C010000D6120000C6120000840100009E
:10001000CE1200008C12000084010000BE1200000D
:10002000B612000084010000840100008401000079
:1000300084010000840100008401000084010000AC
:10004000AE120000A61200009E12000096120000E0
:10005000840100008401000084010000840100008C
:10006000840100008401000084010000840100007C
:100070008401000084010000840100008E12000051
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BIN
Source/Obj/MD203_Boot_V05_20260206_0x0.bin Normal file
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139
Source/Obj/__rt_entry.S Normal file
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@@ -0,0 +1,139 @@
.global __main
.weak __main
.global __e_rom
.weak __e_rom
.global __s_ram_data_1
.weak __s_ram_data_1
.global __e_ram_data_1
.weak __e_ram_data_1
.global __s_ram_bss_1
.weak __s_ram_bss_1
.global __e_ram_bss_1
.weak __e_ram_bss_1
.global __s_ram_data_2
.weak __s_ram_data_2
.global __e_ram_data_2
.weak __e_ram_data_2
.global __s_ram_bss_2
.weak __s_ram_bss_2
.global __e_ram_bss_2
.weak __e_ram_bss_2
.global __s_ram_data_3
.weak __s_ram_data_3
.global __e_ram_data_3
.weak __e_ram_data_3
.global __s_ram_bss_3
.weak __s_ram_bss_3
.global __e_ram_bss_3
.weak __e_ram_bss_3
.global __s_ram_data_4
.weak __s_ram_data_4
.global __e_ram_data_4
.weak __e_ram_data_4
.global __s_ram_bss_4
.weak __s_ram_bss_4
.global __e_ram_bss_4
.weak __e_ram_bss_4
.global __s_ram_data_5
.weak __s_ram_data_5
.global __e_ram_data_5
.weak __e_ram_data_5
.global __s_ram_bss_5
.weak __s_ram_bss_5
.global __e_ram_bss_5
.weak __e_ram_bss_5
.global __ChipInitHandler
.weak __ChipInitHandler
.text
.align 3
__bss_initialization:
subu a2, a3
lsri a2, 2
cmpnei a2, 0
bf 2f
movi a1, 0
1:
stw a1, (a3)
addi a3, 4
subi a2, 1
cmpnei a2, 0
bt 1b
2:
jmp r15
__rom_decompression:
cmphs a1, a2
bt 4f
3:
ld.w a3, (a0, 0)
st.w a3, (a1, 0)
addi a0, 4
addi a1, 4
cmphs a1, a2
bf 3b
4:
jmp r15
__main:
mov r6, r15
lrw a3, __s_ram_bss_1
lrw a2, __e_ram_bss_1
bsr __bss_initialization
lrw a3, __s_ram_bss_2
lrw a2, __e_ram_bss_2
bsr __bss_initialization
lrw a3, __s_ram_bss_3
lrw a2, __e_ram_bss_3
bsr __bss_initialization
lrw a3, __s_ram_bss_4
lrw a2, __e_ram_bss_4
bsr __bss_initialization
lrw a3, __s_ram_bss_5
lrw a2, __e_ram_bss_5
bsr __bss_initialization
lrw a0, __e_rom
lrw a1, __s_ram_data_1
lrw a2, __e_ram_data_1
bsr __rom_decompression
lrw a1, __s_ram_data_2
lrw a2, __e_ram_data_2
bsr __rom_decompression
lrw a1, __s_ram_data_3
lrw a2, __e_ram_data_3
bsr __rom_decompression
lrw a1, __s_ram_data_4
lrw a2, __e_ram_data_4
bsr __rom_decompression
lrw a1, __s_ram_data_5
lrw a2, __e_ram_data_5
bsr __rom_decompression
#ifdef __CSKYABIV2__
subi sp, 4
stw r6, (sp, 0)
lrw a0, __ChipInitHandler
cmpnei a0, 0
bf 1f
jsr a0
1:
lrw a0, main
jsr a0
#else
subi sp, 8
stw r6, (sp, 0)
lrw a0, __ChipInitHandler
cmpnei a0, 0
bf 1f
jsri __ChipInitHandler
1:
jsri main
#endif
ldw r15, (sp, 0)
#ifdef __CSKYABIV2__
addi sp, 4
#else
addi sp, 8
#endif
jmp r15

382
Source/Project.cdkproj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Project Name="MD203F8P" Version="1">
<Description/>
<UIControl>
<Debug>
<DisableSIMConnector>yes</DisableSIMConnector>
</Debug>
</UIControl>
<Dependencies/>
<MonitorProgress>
<DebugLaunch>99</DebugLaunch>
<FlashOperate>98</FlashOperate>
</MonitorProgress>
<VirtualDirectory Name="arch">
<File Name="arch/crt0.S">
<FileOption/>
</File>
<File Name="arch/mem_init.c">
<FileOption/>
</File>
<File Name="arch/apt32f102_iostring.c">
<FileOption/>
</File>
<File Name="arch/apt32f102a.svc">
<FileOption/>
</File>
</VirtualDirectory>
<VirtualDirectory Name="FWlib">
<File Name="FWlib/apt32f102_syscon.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_gpio.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_wwdt.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_bt.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_uart.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_ifc.c">
<FileOption/>
</File>
<File Name="FWlib/apt32f102_lpt.c">
<FileOption/>
</File>
</VirtualDirectory>
<VirtualDirectory Name="inc">
<File Name="include/apt32f102.h">
<FileOption/>
</File>
<File Name="include/apt32f102_bt.h">
<FileOption/>
</File>
<File Name="include/apt32f102_ck801.h">
<FileOption/>
</File>
<File Name="include/apt32f102_gpio.h">
<FileOption/>
</File>
<File Name="include/apt32f102_ifc.h">
<FileOption/>
</File>
<File Name="include/apt32f102_syscon.h">
<FileOption/>
</File>
<File Name="include/apt32f102_uart.h">
<FileOption/>
</File>
<File Name="include/apt32f102_types_local.h">
<FileOption/>
</File>
<File Name="include/apt32f102_clkcalib.h">
<FileOption/>
</File>
<File Name="include/apt32f102_lpt.h">
<FileOption/>
</File>
</VirtualDirectory>
<VirtualDirectory Name="source">
<File Name="main.c">
<FileOption/>
</File>
<File Name="includes.h">
<FileOption/>
</File>
<File Name="mcu_initial.c">
<FileOption/>
</File>
<File Name="mcu_interrupt.c">
<FileOption/>
</File>
<File Name="ckcpu.ld">
<FileOption/>
</File>
</VirtualDirectory>
<VirtualDirectory Name="drivers">
<File Name="drivers/apt32f102.c">
<FileOption/>
</File>
<File Name="drivers/apt32f102_ck801.c">
<FileOption/>
</File>
</VirtualDirectory>
<VirtualDirectory Name="doc">
<File Name="doc/APT32F102_TKLib_Version.md">
<FileOption/>
</File>
<File Name="doc/APT32F102_Lib_Fix_Log.md">
<FileOption/>
</File>
</VirtualDirectory>
<VendorInfo>
<VendorName>NULL</VendorName>
</VendorInfo>
<VirtualDirectory Name="SYSTEM" ExcludeProjConfig="">
<File Name="SYSTEM/uart.c">
<FileOption/>
</File>
<VirtualDirectory Name="inc">
<File Name="SYSTEM/inc/uart.h">
<FileOption/>
</File>
<File Name="SYSTEM/inc/eeprom.h">
<FileOption/>
</File>
<File Name="SYSTEM/inc/Bootload_fun.h">
<FileOption/>
</File>
</VirtualDirectory>
<File Name="SYSTEM/eeprom.c">
<FileOption/>
</File>
<File Name="SYSTEM/Bootload_fun.c">
<FileOption/>
</File>
</VirtualDirectory>
<ToolsConfig>
<Compiler>
<Name>CKV2ElfMinilib</Name>
<Version>latest</Version>
</Compiler>
</ToolsConfig>
<DebugSessions>
<watchExpressions>CK801:1;i_temp:1;j_temp:1;k_temp:1;GPIOB0:1;GPIOA0:1;SYSCON:1;test_d:1;LPT:1;BT0:1;Key_Map:1;DFLASH_rdata:1;TKEYBUF:1</watchExpressions>
<memoryExpressions>0x00080140;;;</memoryExpressions>
<statistics>;;32;;MHZ;;up</statistics>
<peripheralTabs>
<Tab disFormat="Hex">SYSCON</Tab>
</peripheralTabs>
<WatchDisplayFormat>1</WatchDisplayFormat>
<LocalDisplayFormat>0</LocalDisplayFormat>
<debugLayout>layout2|name=Project View;caption=Project View;state=31459324;dir=4;layer=1;row=0;pos=0;prop=68571;bestw=456;besth=277;minw=10;minh=5;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Debugger;caption=Debugger;state=14682108;dir=3;layer=1;row=0;pos=0;prop=86169;bestw=341;besth=315;minw=10;minh=5;maxw=-1;maxh=-1;floatx=60;floaty=707;floatw=418;floath=340|name=Frame Info;caption=Frame Info;state=14698492;dir=3;layer=1;row=0;pos=1;prop=106705;bestw=400;besth=300;minw=10;minh=5;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Peripherals;caption=Peripherals;state=31459326;dir=3;layer=1;row=0;pos=4;prop=100000;bestw=11;besth=43;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Serial Pane;caption=Serial Pane;state=14682110;dir=3;layer=1;row=0;pos=4;prop=100000;bestw=400;besth=300;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Editor;caption=;state=256;dir=5;layer=0;row=0;pos=0;prop=100000;bestw=20;besth=20;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Output View;caption=Output View;state=31459326;dir=3;layer=1;row=0;pos=1;prop=100000;bestw=958;besth=244;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Disassemble;caption=Disassemble;state=2099198;dir=3;layer=1;row=0;pos=2;prop=158373;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=1746;floaty=812;floatw=216;floath=236|name=Register;caption=Register;state=2099198;dir=4;layer=1;row=0;pos=1;prop=100000;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=83;floaty=444;floatw=218;floath=240|name=Outline;caption=Outline;state=2099198;dir=2;layer=0;row=2;pos=0;prop=100000;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=1823;floaty=285;floatw=216;floath=236|dock_size(4,1,0)=210|dock_size(5,0,0)=20|dock_size(3,1,0)=335|</debugLayout>
<memoryTabColSizeExpressions>100:4;100:8;100:8;100:8;</memoryTabColSizeExpressions>
<QuickWatchDisplayFormat>1</QuickWatchDisplayFormat>
</DebugSessions>
<BuildConfigs>
<BuildConfig Name="BuildSet">
<Target>
<ROMBank Selected="1">
<ROM1>
<InUse>yes</InUse>
<Start>0x00000000</Start>
<Size>0x00010000</Size>
</ROM1>
<ROM2>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM2>
<ROM3>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM3>
<ROM4>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM4>
<ROM5>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM5>
</ROMBank>
<RAMBank>
<RAM1>
<InUse>yes</InUse>
<Start>0x20000000</Start>
<Size>0x20001000</Size>
<Init>yes</Init>
</RAM1>
<RAM2>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM2>
<RAM3>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM3>
<RAM4>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM4>
<RAM5>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM5>
</RAMBank>
<CPU>ck801</CPU>
<UseMiniLib>yes</UseMiniLib>
<Endian>little</Endian>
<UseHardFloat>no</UseHardFloat>
<UseEnhancedLRW>no</UseEnhancedLRW>
<UseContinueBuild>no</UseContinueBuild>
<UseSemiHost>no</UseSemiHost>
</Target>
<Output>
<OutputName>MD203_Boot_V05_20260206</OutputName>
<Type>Executable</Type>
<CreateHexFile>yes</CreateHexFile>
<CreateBinFile>yes</CreateBinFile>
<Preprocessor>no</Preprocessor>
<Disassmeble>yes</Disassmeble>
<CallGraph>no</CallGraph>
<Map>yes</Map>
</Output>
<User>
<BeforeCompile>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</BeforeCompile>
<BeforeMake>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</BeforeMake>
<AfterMake>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</AfterMake>
<Tools/>
</User>
<Compiler>
<Define>CONFIG_CSKY_MMU=0</Define>
<Undefine>__CSKY_ABIV2__</Undefine>
<Optim>Optimize size (-Os)</Optim>
<DebugLevel>Default (-g)</DebugLevel>
<IncludePath>$(CDKPath)/CSKY/csi/csi_core/csi_cdk/;$(CDKPath)/CSKY/csi/csi_core/include/;$(CDKPath)/CSKY/csi/csi_driver/include/;$(ProjectPath);$(ProjectPath)/SYSTEM/inc;$(ProjectPath)/USRCTRL/inc;$(ProjectPath)/include</IncludePath>
<OtherFlags>-mistack</OtherFlags>
<Verbose>no</Verbose>
<Ansi>no</Ansi>
<Syntax>no</Syntax>
<Pedantic>no</Pedantic>
<PedanticErr>no</PedanticErr>
<InhibitWarn>no</InhibitWarn>
<AllWarn>no</AllWarn>
<WarnErr>no</WarnErr>
<OneElfS>yes</OneElfS>
<OneElfSPerData>no</OneElfSPerData>
<Fstrict>no</Fstrict>
</Compiler>
<Asm>
<Define>CONFIG_CKCPU_MMU=0</Define>
<Undefine>__CSKY_ABIV2__</Undefine>
<IncludePath>$(CDKPath)/CSKY/csi/csi_core/csi_cdk/;$(CDKPath)/CSKY/csi/csi_core/include/;$(CDKPath)/CSKY/csi/csi_driver/include/;$(ProjectPath);$(ProjectPath)//SYSTEM;$(ProjectPath)/SYSTEM/inc;$(ProjectPath)/USRCTRL/inc</IncludePath>
<OtherFlags/>
<DebugLevel>gdwarf2</DebugLevel>
</Asm>
<Linker>
<Garbage>yes</Garbage>
<Garbage2>yes</Garbage2>
<LDFile>$(ProjectPath)/ckcpu.ld</LDFile>
<LibName>lib_102ClkCalib_1_03</LibName>
<LibPath>$(ProjectPath)</LibPath>
<OtherFlags/>
<AutoLDFile>no</AutoLDFile>
<LinkType/>
<IncludeAllLibs>no</IncludeAllLibs>
<LinkSpecsType>none</LinkSpecsType>
<LinkUseNewlibNano>no</LinkUseNewlibNano>
</Linker>
<Debug>
<LoadApplicationAtStartup>yes</LoadApplicationAtStartup>
<Connector>ICE</Connector>
<StopAt>yes</StopAt>
<StopAtText>main</StopAtText>
<InitFile/>
<PreInit/>
<AfterLoadFile/>
<AutoRun>yes</AutoRun>
<ResetType>Soft Reset</ResetType>
<SoftResetVal>abcd1234</SoftResetVal>
<ResetAfterLoad>no</ResetAfterLoad>
<AfterResetFile/>
<Dumpcore>no</Dumpcore>
<DumpcoreText>$(ProjectPath)/$(ProjectName).cdkcore</DumpcoreText>
<SVCFile/>
<ConfigICE>
<IP>localhost</IP>
<PORT>1025</PORT>
<CPUNumber>0</CPUNumber>
<Clock>1500</Clock>
<Delay>10</Delay>
<NResetDelay>100</NResetDelay>
<WaitReset>50</WaitReset>
<DDC>yes</DDC>
<TRST>no</TRST>
<PreReset>no</PreReset>
<DebugPrint>yes</DebugPrint>
<Connect>Normal</Connect>
<ResetType>Soft Reset</ResetType>
<SoftResetVal>abcd1234</SoftResetVal>
<RTOSType>Bare Metal</RTOSType>
<DownloadToFlash>yes</DownloadToFlash>
<ResetAfterConnect>yes</ResetAfterConnect>
<GDBName/>
<GDBServerType>Local</GDBServerType>
<OtherFlags/>
<ICEEnablePCSampling>yes</ICEEnablePCSampling>
<ICESamplingFreq>1000</ICESamplingFreq>
<RemoteICEEnablePCSampling>yes</RemoteICEEnablePCSampling>
<RemoteICESamplingPort>1026</RemoteICESamplingPort>
<Version>latest</Version>
<SupportRemoteICEAsyncDebug>no</SupportRemoteICEAsyncDebug>
</ConfigICE>
<ConfigSIM>
<SIMTarget>soccfg/cskyv2/smart_card_802_cfg.xml</SIMTarget>
<OtherFlags/>
<NoGraphic>yes</NoGraphic>
<Log>no</Log>
<SimTrace>no</SimTrace>
<Version>latest</Version>
</ConfigSIM>
<ConfigOpenOCD>
<OpenOCDExecutablePath/>
<OpenOCDLocally>yes</OpenOCDLocally>
<OpenOCDTelnetPortEnable>no</OpenOCDTelnetPortEnable>
<OpenOCDTelnetPort>4444</OpenOCDTelnetPort>
<OpenOCDTclPortEnable>no</OpenOCDTclPortEnable>
<OpenOCDTclPort>6666</OpenOCDTclPort>
<OpenOCDConfigOptions/>
<OpenOCDTimeout>5000</OpenOCDTimeout>
<OpenOCDRemoteIP>localhost</OpenOCDRemoteIP>
<OpenOCDRemotePort>3333</OpenOCDRemotePort>
<PluginID>openocd-sifive</PluginID>
<Version>latest</Version>
</ConfigOpenOCD>
</Debug>
<Flash>
<InitFile/>
<PreInit/>
<Erase>Erase Full Chip</Erase>
<Algorithms Path="">$(CDKPath)/CSKY/Flash/APT32F102_FLASHDOWN.elf</Algorithms>
<Program>yes</Program>
<Verify>yes</Verify>
<ResetAndRun>yes</ResetAndRun>
<ResetType>Soft Reset</ResetType>
<SoftResetVal>abcd1234</SoftResetVal>
<FlashIndex>no</FlashIndex>
<FlashIndexVal>0</FlashIndexVal>
<External>no</External>
<Command/>
<Arguments/>
</Flash>
</BuildConfig>
</BuildConfigs>
</Project>

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Source/Project.cdkws Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<CDK_Workspace Name="Project" Database="Project.tags" DoubleClick="Yes">
<DefaultPackPath>$(CDKWS)\__workspace_pack__</DefaultPackPath>
<Project Name="MD203F8P" Path="Project.cdkproj" RootPath="" Active="Yes"/>
<BuildMatrix>
<WorkspaceConfiguration Name="Debug" Selected="yes">
<Environment/>
<Project Name="MD203F8P" ConfigName="BuildSet"/>
</WorkspaceConfiguration>
</BuildMatrix>
</CDK_Workspace>

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Source/SYSTEM/eeprom.c Normal file
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#include "includes.h"
#include <string.h>
E_MCU_DEV_INFO g_mcu_dev;
/*******************************************************************************
* Function Name : EEPROM_Init
* Description : EEPROM 初始化函数
*******************************************************************************/
void EEPROM_Init(void)
{
U8_T rev = 0;
EnIFCClk; //使能 IFC 时钟
IFC->MR |= 0x10002; //高速模式，延迟 2 个周期
delay_nms(10);
rev = EEPROM_ReadMCUDevInfo(&g_mcu_dev);
if(rev == 0x00){
//读取成功，开始校验以下参数
EEPROM_Validate_MCUDevInfo(&g_mcu_dev);
}else{
//读取失败，恢复默认参数
EEPROM_Default_MCUDevInfo(&g_mcu_dev);
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_SYS_STATUS,"EE Use Defalut Para");
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevBootVer:%d",g_mcu_dev.dev_boot_ver);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevNameLen:%d",g_mcu_dev.dev_name_len);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevName:%s",g_mcu_dev.dev_name);
#endif
}
}
/*******************************************************************************
* Function Name : EEPROM_CheckSum
* Description : EEPROM 校验函数
*******************************************************************************/
U8_T EEPROM_CheckSum(U8_T *data,U16_T len)
{
U8_T data_sum = 0;
for(U16_T i = 0;i<len;i++)
{
data_sum += data[i];
}
return data_sum;
}
/*******************************************************************************
* Function Name : EEPROM_ReadMCUDevInfo
* Description : 从EEPROM中读取设备信息
*******************************************************************************/
U8_T EEPROM_ReadMCUDevInfo(E_MCU_DEV_INFO *info)
{
U8_T read_info[6];
U8_T para_data[EEPROM_DATA_Size_Max];
U16_T read_len = 0;
memset(read_info,0,sizeof(read_info));
memset(para_data,0,sizeof(para_data));
ReadDataArry_U8(EEPROM_MCUDevInfo_Address,4,read_info);
if(read_info[0] == EEPROM_SVAE_FLAG){
read_len = read_info[2];
read_len <<= 8;
read_len |= read_info[1];
if(read_len <= EEPROM_DATA_Size_Max){
ReadDataArry_U8(EEPROM_MCUDevInfo_Address+EEPROM_Offset_Data,read_len,para_data);
if(EEPROM_CheckSum(para_data,sizeof(E_MCU_DEV_INFO)) == read_info[3]){
//校验成功
memcpy((uint8_t *)info,para_data,sizeof(E_MCU_DEV_INFO));
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevAddr:%d",g_mcu_dev.dev_addr);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevType:%d",g_mcu_dev.dev_type);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevBootVer:%d",g_mcu_dev.dev_boot_ver);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevAppVer:%d",g_mcu_dev.dev_app_ver);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevNameLen:%d",g_mcu_dev.dev_name_len);
Dbg_Println(DBG_BIT_SYS_STATUS,"EE DevName:%s",g_mcu_dev.dev_name);
#endif
return 0x00;
}
}
}
return 0x01;
}
/*******************************************************************************
* Function Name : EEPROM_WriteMCUDevInfo
* Description : 将设备信息写入到EEPROM中
*******************************************************************************/
U8_T EEPROM_WriteMCUDevInfo(E_MCU_DEV_INFO *info)
{
U8_T save_data[EEPROM_DATA_Size_Max + 6];
U16_T save_len = sizeof(E_MCU_DEV_INFO);
if(save_len >= EEPROM_DATA_Size_Max) save_len = EEPROM_DATA_Size_Max;
save_data[0] = EEPROM_SVAE_FLAG;
save_data[1] = save_len & 0xFF;
save_data[2] = (save_len >> 8) & 0xFF;
memcpy(&save_data[4],(uint8_t *)info,save_len);
save_data[3] = EEPROM_CheckSum(&save_data[4],save_len);
save_len+=4;
Page_ProgramData(EEPROM_MCUDevInfo_Address,save_len,save_data);
return 0;
}
/*******************************************************************************
* Function Name : EEPROM_Default_MCUDevInfo
* Description : EEPROM中参数恢复默认值，且将默认参数保存至EEPROM中
*******************************************************************************/
void EEPROM_Default_MCUDevInfo(E_MCU_DEV_INFO *info)
{
#if (Project_Area == 0x01)
/*Boot 区域*/
info->dev_addr = 0x00;
info->dev_type = 0x00;
info->dev_app_ver = 0x00;
info->dev_boot_ver = Project_FW_Version;
info->dev_name_len = sizeof(Peoject_Name);
memset((char *)info->dev_name,0,EEPROM_DEV_NAME_Size);
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
EEPROM_WriteMCUDevInfo(info);
#elif (Project_Area == 0x02)
/*APP 区域*/
info->dev_addr = 0x00;
info->dev_type = Project_Type;
info->dev_app_ver = Project_FW_Version;
info->dev_name_len = sizeof(Peoject_Name);
memset((char *)info->dev_name,0,EEPROM_DEV_NAME_Size);
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
EEPROM_WriteMCUDevInfo(info);
#endif
}
/*******************************************************************************
* Function Name : EEPROM_Validate_MCUDevInfo
* Description : 校验从EEPROM 中读取的参数是否正确，如果不正确的话，便将当前正确的参数写入
APP区域中，判断APP参数与EEPROM中记录的是否一致
Boot区域中，判断Boot参数与EEPROM中记录的是否一致
*******************************************************************************/
void EEPROM_Validate_MCUDevInfo(E_MCU_DEV_INFO *info)
{
#if (Project_Area == 0x01)
/*Boot 区域*/
U8_T save_flag = 0;
if(info->dev_boot_ver != Project_FW_Version)
{
info->dev_boot_ver = Project_FW_Version;
save_flag = 0x01;
}
if(save_flag == 0x01)
{
EEPROM_WriteMCUDevInfo(info);
}
#elif (Project_Area == 0x02)
/*APP 区域*/
U8_T save_flag = 0;
if(info->dev_app_ver != Project_FW_Version)
{
info->dev_app_ver = Project_FW_Version;
save_flag = 0x01;
}
if(info->dev_type != Project_Type)
{
info->dev_type = Project_Type;
save_flag = 0x01;
}
if(info->dev_name_len != sizeof(Peoject_Name))
{
info->dev_name_len = sizeof(Peoject_Name);
save_flag = 0x01;
}
if(strncmp((char *)info->dev_name,(char *)Peoject_Name,sizeof(Peoject_Name)))
{
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
save_flag = 0x01;
}
if(save_flag == 0x01)
{
EEPROM_WriteMCUDevInfo(info);
}
#endif
}

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Source/SYSTEM/inc/Bootload_fun.h Normal file
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#ifndef _BOOTLOAD_FUNCTION_H_
#define _BOOTLOAD_FUNCTION_H_
#include "apt32f102.h"
#include "apt32f102_ifc.h"
#include "apt32f102_syscon.h"
#include "uart.h"
#define App_Procedure_Ready 0x66 //APP准备就绪标志位
#define APP_Flash_PageSize 0x100
#if DBG_LOG_EN
#define APP_Flash_StartAddr PROM_PageAdd96 //调试APP起始地址
#else
#define APP_Flash_StartAddr PROM_PageAdd40
#endif
#define APP_Flash_EndAddr PROM_PageAdd255
#define APP_FEATURE_Flash_Addr PROM_PageAdd255
#define MCU_EEPROM_PageSize 0x40
#define MCU_EEPROM_StartAddr DROM_PageAdd0
#define MCU_EEPROM_EndAddr (DROM_PageAdd31 + MCU_EEPROM_PageSize)
#define BCOMM_CMD_Handshake 0xC0
#define BCOMM_CMD_Jump 0xC1
#define BCOMM_CMD_SetInfo 0xC2
#define BCOMM_CMD_WriteFlash 0xC3
#define BCOMM_CMD_ReadFlash 0xC4
#define BCOMM_CMD_EraseFlash 0xC5
#define BCOMM_CMD_WriteEEPROM 0xC6
#define BCOMM_CMD_ReadEEPROM 0xC7
#define BCOMM_CMD_EraseEEPROM 0xC8
#define BCOMM_CMD_CheckData 0xC9
#define BCOMM_CMD_ReplySUCC 0x00
#define BCOMM_CMD_ReplyFAIL 0x01
#define BCOMM_ACKSize 300
#define BCOMM_ParaSize 280
typedef enum
{
BCOMM_FMT_TXAddr,
BCOMM_FMT_SN,
BCOMM_FMT_TYPE,
BCOMM_FMT_RXAddr,
BCOMM_FMT_LEN_L,
BCOMM_FMT_LEN_H,
BCOMM_FMT_CKS,
BCOMM_FMT_CMD,
BCOMM_FMT_PARAM,
}BOOT_COMM_FMT_e;
typedef struct{
U8_T jump_start;
U8_T sn;
U8_T cmd;
U8_T pc_addr;
U8_T ackBuffer[BCOMM_ACKSize];
U16_T ackLen;
U16_T ackValidity; //数据回复有效期
U32_T bootTimeout;
U32_T bootTick;
}BOOT_INFO_T;
typedef struct{
U8_T crcL_check;
U8_T crcH_check;
U8_T app_flag;
U8_T app_crc[241];
U16_T app_crc_size;
U16_T app_crc_len;
U32_T app_start_addr;
U32_T app_end_addr;
}APP_FEATURE_INFO_T; /*字节空间是256Byte*/
extern BOOT_INFO_T g_boot;
void Boot_Function_Init(void);
U8_T Boot_Comm_UpgradeProcess(U8_T *data,U16_T len);
void Boot_Time_Refresh(void);
void Boot_TimeOut_Task(void);
void Jump_To_APP(void);
U8_T Check_APP_Feature(void);
#endif

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#ifndef _EEPROM_H_
#define _EEPROM_H_
#include "apt32f102.h"
/*地址范围：0x10000000~0x100007FF*/
#define EEPROM_MCUDevInfo_Address 0x10000000 //MCU 设备信息地址固定为0x10000000，大小为0x40 此区域不可改动
/* EEPROM 保存数据格式：
* FLAG - 1Byte 保存标志位
* LEN - 2Byte 保存数据长度
* CHECK - 1Byte 保存数据校验
* DATA - nByte 保存数据内容
*
* */
#define EEPROM_SVAE_FLAG 0xAE
#define EEPROM_DATA_Size_Max 0x40 //目前保存数据内容最长为100Byte
#define EEPROM_PARA_Size 50
#define EEPROM_DEV_NAME_Size 32
#define EEPROM_Offset_SaveFlag 0x00
#define EEPROM_Offset_Datalen 0x01
#define EEPROM_Offset_Check 0x03
#define EEPROM_Offset_Data 0x04
typedef struct{
U8_T dev_addr; //设备地址
U8_T dev_type; //设备类型
U8_T dev_boot_ver; //设备Boot的软件版本号
U8_T dev_app_ver; //设备APP的软件版本号
U8_T dev_name_len; //设备名称的长度
U8_T dev_name[EEPROM_DEV_NAME_Size]; //设备名称
}E_MCU_DEV_INFO;
extern E_MCU_DEV_INFO g_mcu_dev;
void EEPROM_Init(void);
U8_T EEPROM_ReadMCUDevInfo(E_MCU_DEV_INFO *info);
U8_T EEPROM_WriteMCUDevInfo(E_MCU_DEV_INFO *info);
void EEPROM_Default_MCUDevInfo(E_MCU_DEV_INFO *info);
void EEPROM_Validate_MCUDevInfo(E_MCU_DEV_INFO *info);
#endif

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#ifndef _UART_H_
#define _UART_H_
#include "apt32f102.h"
#include "apt32f102_uart.h"
#define Recv_2400_TimeOut 10 //ms
#define Recv_9600_TimeOut 5 //ms
#define Recv_115200_TimeOut 3 //ms
#define USART_BUFFER_SIZE 300
#define UART_SEND_BUFFER_NUM 10
#define UART_SEND_BUFFER_SIZE 20
#define READ_RXLEVEL_STATE GPIO_Read_Status(GPIOB0,5) //485总线RX引脚
#define WRITE_HIGH_DR GPIO_Write_High(GPIOB0,3) //485 DR
#define WRITE_LOW_DR GPIO_Write_Low(GPIOB0,3) //485 DR
#define REVERISE_DR GPIO_Reverse(GPIOB0,3) //485 DR
#define UART_BUSBUSY 0x01 //总线繁忙
#define UART_BUSIDLE 0x00 //总线空闲
/*调试信息相关定义*/
#ifndef DBG_LOG_EN
#define DBG_LOG_EN 0 //DEBUG LOG 输出总开关
#endif
/*调试信息初始状态*/
#define DBG_OPT_Debug_STATUS 0 //临时调试信息打印开关
#define DBG_OPT_DEVICE_STATUS 0 //设备驱动层打印调试信息打印开关
#define DBG_OPT_SYS_STATUS 0 //系统调试信息打印开关
/*调试信息输出控制位*/
#define DBG_BIT_Debug_STATUS 2
#define DBG_BIT_DEVICE_STATUS 1
#define DBG_BIT_SYS_STATUS 0
#if DBG_LOG_EN
#define DBG_SendByte(data) UARTTxByte(UART2,data)
#define DBG_Printf(data,len) UARTTransmit(UART2,data,len)
#else
#define DBG_SendByte(data)
#define DBG_Printf
#endif
typedef U8_T (*Uart_prt)(U8_T *,U16_T);
typedef enum
{
UART_0,
UART_1,
UART_2,
UART_3,
UART_MAX,
}UART_IDX;
typedef enum
{
BUSSEND_SUCC = 0x00, //发送成功
BUSSEND_WAIT, //等待发送机会
DATA_END, //数据有效期结束
RETRY_END, //重发结束
LEN_ERR, //长度错误
}BUSSEND_REV;
typedef struct{
U8_T RecvBuffer[USART_BUFFER_SIZE];
U8_T DealBuffer[USART_BUFFER_SIZE];
U8_T Receiving;
U16_T RecvLen;
U16_T DealLen;
U32_T RecvTimeout;
U32_T RecvIdleTiming;
Uart_prt processing_cf; //处理函数指针
} UART_t;
typedef struct{ //总线繁忙判断
U8_T SendBuffer[USART_BUFFER_SIZE]; //发送缓冲
U8_T BusState_Flag; //总线繁忙标记位， 0x01:总线繁忙，0x00:总线空闲
U8_T HighBit_Flag; //串口RX高电平标记位,默认是高电平0x01.
U8_T BUSBUSY_LOCK; //锁定总线繁忙状态
U8_T ResendCnt; //当前发送次数
U8_T ASend_Flag; //主动上报发送标记
U8_T TotalCnt; //发送总次数
U8_T SetBaudFlag; //设置波特率
U16_T SendLen; //发送缓冲区数据长度
U32_T SetBaud;
U32_T Bus_DelayTime; //总线繁忙转换到空闲状态的随机延时时间
U32_T DataWait_Time; //上报数据间隔
U32_T DataValid_Time; //上报数据有效期
U32_T BusState_Tick; //总线繁忙状态判断时间戳
U32_T ASend_Tick; //主动上报发送间隔判断时间戳
U32_T BusbusyTimeout; //上报数据有效期判断时间戳
}MULIT_t;
extern U32_T Dbg_Switch;
extern volatile int RS485_Comm_Flag,RS485_Comm_Start,RS485_Comm_End,RS485_Comming;
void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf);
U16_T Get_Uart_BaudCnt(U32_T baud);
U8_T UARTx_ChangeBaud(uint8_t uart_id,uint32_t baud);
void UART2_RecvINT_Processing(char data);
void UART2_TASK(void);
void MCU485_SendData(U8_T *buff,U16_T len);
U8_T BUS485_Send(U8_T *buff,U16_T len);
U8_T MultSend_Task(U8_T *buff,U16_T len,U8_T DatSd);
void Set_GroupSend(U8_T *data,U16_T sled,U8_T SCnt,U32_T indate,U32_T tim_val);
//void Clear_SendFlag(void);
void BUS485_SetBaud(U32_T baud);
void BUS485Send_Task(void);
void BusIdle_Task(void);
void BusBusy_Task(void);
void Dbg_Print(int DbgOptBit, const char *cmd, ...);
void Dbg_Println(int DbgOptBit, const char *cmd, ...);
void Dbg_Print_Buff(int DbgOptBit, const char *cmd, U8_T *buff,U16_T len);
#endif

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#include "includes.h"
#include <string.h>
#include <stdarg.h>
#include <stdio.h>
/**
* Bootload 串口使用情况
* UART0 没有使用
* UART2 用与调试信息输出 - 512000
* UART1 用于Bootload 升级使用
* */
UART_t g_uart; //目前该项目只使用串口2 进行双向通讯
MULIT_t m_send;
void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf) {
switch(uart_id){
case UART_1:
memset(&g_uart,0,sizeof(UART_t));
memset(&m_send,0,sizeof(MULIT_t));
//串口1-RX接收中断，用于串口1的通讯总线繁忙状态判断，2025-04-16
// GPIO_PullHigh_Init(GPIOA0,15);
// GPIO_IntGroup_Set(PA0,15,Selete_EXI_PIN15); //EXI0 set PB0.2
// GPIOA0_EXI_Init(EXI15); //PB0.2 as input
// EXTI_trigger_CMD(ENABLE,EXI_PIN15,_EXIFT); //ENABLE falling edge
// EXTI_trigger_CMD(ENABLE,EXI_PIN15,_EXIRT);
// EXTI_interrupt_CMD(ENABLE,EXI_PIN15); //enable EXI
// GPIO_EXTI_interrupt(GPIOA0,0b1000000000000000); //enable GPIOB02 as EXI
// EXI4_Int_Enable();
//
// UART1_DeInit(); //clear all UART Register
// UART_IO_Init(IO_UART1,2); //use PA0.13->RXD1, PB0.0->TXD1
// UARTInitRxTxIntEn(UART1,20000,UART_PAR_NONE); //baudrate=sysclock 48M/20000=2400 tx rx int enabled
// UART1_Int_Enable();
//
// m_send.BusState_Tick = SysTick_1ms;
// m_send.HighBit_Flag = 0x01;
//
// g_uart.RecvTimeout = Recv_2400_TimeOut;
// g_uart.processing_cf = prt_cf;
//
// //485使能引脚初始化
// GPIO_Init(GPIOA0,UART485_DR_PIN,Output);
// GPIO_DriveStrength_EN(GPIOA0,UART485_DR_PIN);
// WRITE_LOW_DR;
break;
case UART_2:
//2026-02-06 使用串口2作为Bootload 升级使用
memset(&g_uart,0,sizeof(UART_t));
memset(&m_send,0,sizeof(MULIT_t));
//串口RX接收中断
GPIO_PullHigh_Init(GPIOB0,5);
GPIO_IntGroup_Set(PB0,5,Selete_EXI_PIN5); //EXI0 set PB0.5
GPIOB0_EXI_Init(EXI5); //PB0.5 as input
EXTI_trigger_CMD(ENABLE,EXI_PIN5,_EXIFT); //ENABLE falling edge
EXTI_trigger_CMD(ENABLE,EXI_PIN5,_EXIRT);
EXTI_interrupt_CMD(ENABLE,EXI_PIN5); //enable EXI
GPIO_EXTI_interrupt(GPIOB0,0b0000000000100000); //enable GPIOB05 as EXI
EXI3_Int_Enable(); //EXI4~EXI9 INT Vector
UART2_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART2,2); //use PA0.13->RXD1, PB0.0->TXD1
UARTInitRxTxIntEn(UART2,20000,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled
UART2_Int_Enable();
m_send.BusState_Tick = SysTick_1ms;
m_send.HighBit_Flag = 0x01;
g_uart.RecvTimeout = Recv_2400_TimeOut;
g_uart.processing_cf = prt_cf;
//485使能引脚初始化
GPIO_Init(GPIOB0,3,Output);
GPIO_DriveStrength_EN(GPIOB0,3);
WRITE_LOW_DR;
break;
}
}
/*******************************************************************************
* Function Name : Get_Uart_BaudCnt
* Description : Uart 获取串口波特率对于设置值
*******************************************************************************/
U16_T Get_Uart_BaudCnt(U32_T baud)
{
switch(baud){
case 2400:
return 20000;
case 4800:
return 10000;
case 9600:
return 5000;
case 19200:
return 2621;
case 56000:
return 898;
case 115200:
return 416;
case 512000:
return 98;
}
return 0x00;
}
/*******************************************************************************
* Function Name : Get_Uart_Recv_Timeout
* Description : Uart 获取串口接收超时时间
*******************************************************************************/
U32_T Get_Uart_Recv_Timeout(U32_T baud)
{
switch(baud){
case 2400:
return Recv_2400_TimeOut;
case 4800:
return Recv_2400_TimeOut;
case 9600:
return Recv_9600_TimeOut;
case 19200:
return Recv_9600_TimeOut;
case 56000:
return Recv_9600_TimeOut;
case 115200:
return Recv_115200_TimeOut;
case 512000:
return Recv_115200_TimeOut;
}
return Recv_115200_TimeOut;
}
/*******************************************************************************
* Function Name : UARTx_ChangeBaud
* Description : Uart 切换串口波特率
*******************************************************************************/
U8_T UARTx_ChangeBaud(uint8_t uart_id,uint32_t baud)
{
U16_T set_para = Get_Uart_BaudCnt(baud);
if(set_para == 0x00) return 0x01; //设置的波特率不支持
switch(uart_id){
case UART_1:
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_SYS_STATUS, "UART ID %d", uart_id);
Dbg_Println(DBG_BIT_SYS_STATUS,"UART baud %d",baud);
#endif
UARTClose(UART1);
UART1_Int_Disable();
UART1_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART1,2); //use PA0.13->RXD1, PB0.0->TXD1
UARTInitRxTxIntEn(UART1,set_para,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled
UART1_Int_Enable();
g_uart.RecvTimeout = Get_Uart_Recv_Timeout(baud);
break;
case UART_2:
UARTClose(UART2);
UART2_Int_Disable();
UART2_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART2,2); //use PA0.13->RXD1, PB0.0->TXD1
UARTInitRxTxIntEn(UART2,set_para,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled
UART2_Int_Enable();
g_uart.RecvTimeout = Get_Uart_Recv_Timeout(baud);
break;
}
}
/*******************************************************************************
* Function Name : UART1_RecvINT_Processing
* Description : 串口1 接收中断处理函数 - 接收中断调用
*******************************************************************************/
//void UART1_RecvINT_Processing(char data){
// if((g_uart.RecvLen + 1) >= USART_BUFFER_SIZE) g_uart.RecvLen = 0;
// g_uart.RecvBuffer[g_uart.RecvLen++] = (U8_T)data;
//
// g_uart.RecvIdleTiming = SysTick_1ms;
// g_uart.Receiving = 0x01;
//}
//
//
//void UART1_TASK(void){
// U8_T ret = 0x00;
// if(g_uart.Receiving == 0x01){
// if(SysTick_1ms - g_uart.RecvIdleTiming > g_uart.RecvTimeout){
//
// SYSCON_Int_Disable();
// g_uart.RecvIdleTiming = SysTick_1ms;
// memcpy(g_uart.DealBuffer,g_uart.RecvBuffer,g_uart.RecvLen);
// g_uart.DealLen = g_uart.RecvLen;
// g_uart.RecvLen = 0;
// g_uart.Receiving = 0;
// SYSCON_Int_Enable();
//
//#if DBG_LOG_EN
// Dbg_Println(DBG_BIT_SYS_STATUS, "UART recv Len %d", g_uart.DealLen);
// Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"UART buff",g_uart.DealBuffer,g_uart.DealLen);
//#endif
//
// if(g_uart.processing_cf != NULL){
// ret = g_uart.processing_cf(g_uart.DealBuffer,g_uart.DealLen);
// }
//
// }
// }
//}
/*******************************************************************************
* Function Name : UART2_RecvINT_Processing
* Description : 串口2 接收中断处理函数 - 接收中断调用
*******************************************************************************/
void UART2_RecvINT_Processing(char data){
if((g_uart.RecvLen + 1) >= USART_BUFFER_SIZE) g_uart.RecvLen = 0;
g_uart.RecvBuffer[g_uart.RecvLen++] = (U8_T)data;
g_uart.RecvIdleTiming = SysTick_1ms;
g_uart.Receiving = 0x01;
}
void UART2_TASK(void){
U8_T ret = 0x00;
if(g_uart.Receiving == 0x01){
if(SysTick_1ms - g_uart.RecvIdleTiming > g_uart.RecvTimeout){
SYSCON_Int_Disable();
g_uart.RecvIdleTiming = SysTick_1ms;
memcpy(g_uart.DealBuffer,g_uart.RecvBuffer,g_uart.RecvLen);
g_uart.DealLen = g_uart.RecvLen;
g_uart.RecvLen = 0;
g_uart.Receiving = 0;
SYSCON_Int_Enable();
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_SYS_STATUS, "UART recv Len %d", g_uart.DealLen);
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"UART buff",g_uart.DealBuffer,g_uart.DealLen);
#endif
if(g_uart.processing_cf != NULL){
ret = g_uart.processing_cf(g_uart.DealBuffer,g_uart.DealLen);
}
}
}
}
/*因为开启了UART_TX_DONE_S 中断，发送完成需要清楚该中断标志位，因此每次调用串口输出后，需调用该函数，否则会在中断出不来
* 已取消
* */
void UART_Waiting_For_Send(CSP_UART_T *uart){
unsigned int Dataval = 0,delay_cnt = 0;
do{
Dataval = CSP_UART_GET_ISR(uart);
Dataval = Dataval & UART_TX_DONE_S;
delay_cnt ++;
if(delay_cnt >= 50000){
break;
}
}while(Dataval == 0x00); //发送完成
uart->ISR=UART_TX_DONE_S;
}
volatile int RS485_Comm_Flag = 0,RS485_Comm_Start = 0,RS485_Comm_End = 0,RS485_Comming = 0;
void MCU485_SendData(U8_T *buff,U16_T len){
unsigned int Dataval = 0,delay_cnt = 0;
//等待通讯发送完成
while(RS485_Comming == 0x01){
delay_nus(100);
delay_cnt ++;
if(delay_cnt >= 100){
break;
}
REVERISE_DR;//GPIO_Reverse(GPIOB0,3);
}
WRITE_HIGH_DR;//GPIO_Write_High(GPIOB0,3);
RS485_Comm_Flag = 0x01;
RS485_Comm_Start = 0x00;
RS485_Comm_End = 0x00;
UARTTransmit(UART2,buff,len);
do{
delay_nus(100);
delay_cnt ++;
if(delay_cnt >= 100){
break;
}
}while((RS485_Comm_Start < len) || (RS485_Comm_End < len)); //发送完成
WRITE_LOW_DR;//GPIO_Write_Low(GPIOB0,3);
RS485_Comm_Flag = 0x00;
}
/**********************************************************
* @brief BUS485 数据发生函数 - 检测总线是否繁忙，空闲状态下，才发生数据；繁忙状态下，直接退出
* @retval None
* */
U8_T BUS485_Send(U8_T *buff,U16_T len)
{
unsigned int Dataval = 0,delay_cnt = 0;
//等待通讯发送完成
while(RS485_Comming == 0x01){
delay_nus(100);
delay_cnt ++;
if(delay_cnt >= 100){
break;
}
REVERISE_DR;//GPIO_Reverse(GPIOB0,3);
}
if(m_send.BusState_Flag == UART_BUSIDLE){ //总线空闲
CK_CPU_DisAllNormalIrq();
WRITE_HIGH_DR;//GPIO_Write_High(GPIOB0,3);
RS485_Comm_Flag = 0x01;
RS485_Comm_Start = 0x00;
RS485_Comm_End = 0x00;
m_send.BusState_Flag = UART_BUSBUSY;//发送前总线置位繁忙
m_send.BUSBUSY_LOCK = 0x01; //锁定总线状态
CK_CPU_EnAllNormalIrq();
UARTTransmit(UART2,buff,len);
do{
delay_nus(100);
delay_cnt ++;
if(delay_cnt >= 100){
break;
}
}while((RS485_Comm_Start < len) || (RS485_Comm_End < len)); //发送完成
CK_CPU_DisAllNormalIrq();
WRITE_LOW_DR;//GPIO_Write_Low(GPIOB0,3);
RS485_Comm_Flag = 0x00;
m_send.BusState_Tick = SysTick_1ms;
m_send.BUSBUSY_LOCK = 0x00; //解锁总线状态
CK_CPU_EnAllNormalIrq();
return UART_BUSIDLE; //发送成功
}
else{ //总线繁忙
return UART_BUSBUSY; //发送失败
}
return 0x02; //传入状态无效
}
/**********************************************************
* @brief 重发、数据有效期、超时发送判断，2025-03-25
* buff:发送数据
* len：数据长度
* DatSd：发送标记,0x00:无发送，0x01：有数据发送
*
* @retval 0x00:发送成功 0x01:等待发送 0x02:数据无效
* */
U8_T MultSend_Task(U8_T *buff,U16_T len,U8_T DatSd)
{
if( (len == 0)||(len > USART_BUFFER_SIZE) ) return LEN_ERR;
if(DatSd == 0x01)
{
if( m_send.ResendCnt < m_send.TotalCnt) //判断数据是否还在有效期，是否还有发送次数
{
if(SysTick_1ms - m_send.BusbusyTimeout < m_send.DataValid_Time)
{
if( (m_send.ResendCnt == 0x00) || (SysTick_1ms - m_send.ASend_Tick >= m_send.DataWait_Time) ){//数据发送间隔
if(BUS485_Send(buff,len) == UART_BUSIDLE){ //发送数据
m_send.ASend_Tick = SysTick_1ms;
m_send.ResendCnt++;
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_Debug_STATUS,"SendCnt:%d success",m_send.ResendCnt);
#endif
return BUSSEND_SUCC;//数据发送成功
}
}
}else{
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_Debug_STATUS,"data end");
#endif
return DATA_END;//数据有效期结束
}
}else{
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_Debug_STATUS,"retry end,%d",m_send.ResendCnt );
#endif
return RETRY_END;//没有重发次数
}
}
return BUSSEND_WAIT;//等待
}
/**********************************************************
* @brief 设置发送标志、组包、选择数据有效期档位，2025-03-25
* data: 发送数据
* sled： 数据长度
* SCnt: 设置数据发送次数
* indate： 设置数据有效期
* tim_val: 发送时间间隔
* @retval None
* */
void Set_GroupSend(U8_T *data,U16_T sled,U8_T SCnt,U32_T indate,U32_T tim_val)
{
if((sled == 0x00)|| (sled > USART_BUFFER_SIZE)) return;
memset(m_send.SendBuffer,0, USART_BUFFER_SIZE);
memcpy(m_send.SendBuffer,data,sled);
m_send.SendLen = sled;
m_send.DataValid_Time = indate;//数据有效期
m_send.TotalCnt = SCnt; //数据发送次数
m_send.DataWait_Time = tim_val;//发送数据间隔
m_send.ASend_Flag = 0x01;
m_send.ResendCnt = 0x00;
m_send.BusbusyTimeout = SysTick_1ms;
}
//清除发送标志
//void Clear_SendFlag(void)
//{
// m_send.ASend_Flag = 0x00;
//}
void BUS485_SetBaud(U32_T baud)
{
m_send.SetBaudFlag = 0x01;
m_send.SetBaud = baud;
}
/**********************************************************
* @brief 检测总线空闲，在While(1)里调用 2025-03-25
* @retval None
* */
void BUS485Send_Task(void) //2025-03-29
{
U8_T ret = 0xFF;
//空闲等待
if(m_send.ASend_Flag == 0x01)//初始化发送
{
ret = MultSend_Task(m_send.SendBuffer,m_send.SendLen,m_send.ASend_Flag);
if( (ret == DATA_END)||(ret == RETRY_END) )//判断发送数据是否有效
{
#if DBG_LOG_EN
Dbg_Println(DBG_BIT_Debug_STATUS,"send end");
#endif
m_send.ASend_Flag = 0x00;
/*设置波特率*/
if( m_send.SetBaudFlag == 0x01 ){
UARTx_ChangeBaud(UART_2,m_send.SetBaud);
m_send.SetBaudFlag = 0x00;
m_send.SetBaud = 0x00;
}
}
}
}
/**********************************************************
* @brief 检测总线空闲，在定时器中断里调用
* @retval None
* */
void BusIdle_Task(void)
{
if(m_send.BusState_Flag != UART_BUSIDLE && m_send.BUSBUSY_LOCK != 0x01)
{
CK_CPU_DisAllNormalIrq();
if( ( m_send.HighBit_Flag == 0x01 )&&( ( SysTick_1ms - m_send.BusState_Tick ) >= ( g_uart.RecvTimeout + m_send.Bus_DelayTime )) )
{
m_send.BusState_Flag = UART_BUSIDLE;
}
CK_CPU_EnAllNormalIrq();
}
}
/*******************************************************************
* @brief 检测总线繁忙，在串口接收RX引脚的外部中断服务函数里调用
* @retval None
* */
void BusBusy_Task(void)
{
CK_CPU_DisAllNormalIrq();
m_send.BusState_Flag = UART_BUSBUSY;
m_send.BusState_Tick = SysTick_1ms;
m_send.Bus_DelayTime = (SysTick_1ms - m_send.ASend_Tick)%10;//随机延时
if(READ_RXLEVEL_STATE == 0x01){
m_send.HighBit_Flag = 0x01; //高电平标志置位
}else if(READ_RXLEVEL_STATE == 0x00){
m_send.HighBit_Flag = 0x00; //低电平
}
CK_CPU_EnAllNormalIrq();
}
/*调试信息输出接口*/
U32_T Dbg_Switch = (DBG_OPT_Debug_STATUS << DBG_BIT_Debug_STATUS)
+ (DBG_OPT_DEVICE_STATUS << DBG_BIT_DEVICE_STATUS)
+ (DBG_OPT_SYS_STATUS << DBG_BIT_SYS_STATUS);
#if DBG_LOG_EN
char Dbg_Buffer[512] = {0};
U32_T SysTick_Now = 0, SysTick_Last = 0, SysTick_Diff = 0;
#endif
void Dbg_Print(int DbgOptBit, const char *cmd, ...){
#if DBG_LOG_EN
U16_T str_offset = 0;
if (Dbg_Switch & (1 << DbgOptBit)) {
SysTick_Now = SysTick_1ms;
SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差
SysTick_Last = SysTick_Now;
str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer),"%8d [%6d]: ", SysTick_Now, SysTick_Diff);
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
va_list args; //定义一个va_list类型的变量，用来储存单个参数
va_start(args, cmd); //使args指向可变参数的第一个参数
str_offset = vsnprintf(Dbg_Buffer, sizeof(Dbg_Buffer) ,cmd, args); //必须用vprintf等带V的
va_end(args); //结束可变参数的获取
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
}
#endif
}
void Dbg_Println(int DbgOptBit, const char *cmd, ...){
#if DBG_LOG_EN
U16_T str_offset = 0;
if (Dbg_Switch & (1 << DbgOptBit)) {
SysTick_Now = SysTick_1ms;
SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差
SysTick_Last = SysTick_Now;
str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%8ld [%6ld]: ", SysTick_Now, SysTick_Diff);
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
va_list args; //定义一个va_list类型的变量，用来储存单个参数
va_start(args, cmd); //使args指向可变参数的第一个参数
str_offset = vsnprintf(Dbg_Buffer, sizeof(Dbg_Buffer) ,cmd, args); //必须用vprintf等带V的
va_end(args); //结束可变参数的获取
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
DBG_Printf((U8_T *)"\r\n",2);
}
#endif
}
void Dbg_Print_Buff(int DbgOptBit, const char *cmd, U8_T *buff,U16_T len){
#if DBG_LOG_EN
U16_T str_offset = 0;
if (Dbg_Switch & (1 << DbgOptBit)) {
SysTick_Now = SysTick_1ms;
SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差
SysTick_Last = SysTick_Now;
str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%8ld [%6ld]:%s ", SysTick_Now, SysTick_Diff,cmd);
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
for (uint32_t i = 0; i < len; i++) {
SYSCON_IWDCNT_Reload();
str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%02X ", buff[i]);
DBG_Printf((U8_T *)Dbg_Buffer,str_offset);
}
DBG_Printf((U8_T *)"\r\n",2);
}
#endif
}

143
Source/arch/apt32f102_iostring.c Normal file
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/*
******************************************************************************
* @file apt32f102_iostring.c
* @author APT AE Team
* @version V1.00
* @date 2020/05/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/******************************************************************************
* Include Files
******************************************************************************/
#include "apt32f102.h"
#include "apt32f102_uart.h"
#include "stdarg.h"
#include "stddef.h"
#include "stdio.h"
#define LDCC_DATA_P 0xe001105c /* LDCC Register. */
#define LDCC_BIT_STATUS 0x80000000 /* LDCC Status bit. */
//#define _debug_uart_io
/******************************************************************************
* Main code
******************************************************************************/
void __putchar__ (char ch)
{
#ifdef _debug_uart_io
//UARTTxByte(UART0,s); //uart 0
UARTTxByte(UART1,s); //uart 1
#else
//select debug serial Pane
volatile unsigned int *pdata = (unsigned int *)LDCC_DATA_P;
while (*pdata & LDCC_BIT_STATUS); //Waiting for data read.
*pdata = ch;
#endif
}
int *myitoa(int value, int* string, int radix)
{
int tmp[33];
int* tp = tmp;
int i;
unsigned v;
int sign;
int* sp;
if (radix > 36 || radix <= 1)
{
return 0;
}
sign = (radix == 10 && value < 0);
if (sign)
v = -value;
else
v = (unsigned)value;
while (v || tp == tmp)
{
i = v % radix;
v = v / radix;
if (i < 10) {
*tp++ = i+'0';
} else {
*tp++ = i + 'a' - 10;
}
}
sp = string;
if (sign)
*sp++ = '-';
while (tp > tmp)
*sp++ = *--tp;
*sp = 0;
return string;
}
void my_printf(const char *fmt, ...)
{
// const char *s;
const int *s;
int d;
//char ch, *pbuf, buf[16];
char ch, *pbuf;
int buf[16];
va_list ap;
va_start(ap, fmt);
while (*fmt) {
if (*fmt != '%') {
__putchar__(*fmt++);
continue;
}
switch (*++fmt) {
case 's':
s = va_arg(ap, const int *);
for ( ; *s; s++) {
__putchar__(*s);
}
break;
case 'd':
d = va_arg(ap, int);
myitoa(d, buf, 10);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
case 'x':
case 'X':
d = va_arg(ap, int);
myitoa(d, buf, 16);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
// Add other specifiers here...
case 'c':
case 'C':
ch = (unsigned char)va_arg(ap, int);
pbuf = &ch;
__putchar__(*pbuf);
break;
default:
__putchar__(*fmt);
break;
}
fmt++;
}
va_end(ap);
}

3453
Source/arch/apt32f102a.svc Normal file
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File diff suppressed because it is too large Load Diff

213
Source/arch/crt0.S Normal file
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//start from __start,
//(0)initialize vector table
//(1)initialize all registers
//(2)prepare initial reg values for user process
//(3)initialize supervisor mode stack pointer
//(4)construct ASID Table
//(5)prepare PTE entry for user process start virtual address
//(6)creat a mapping between VPN:0 and PFN:0 for kernel
//(7)set VBR register
//(8)enable EE and MMU
//(9)jump to the main procedure using jsri main
#define UserOption 0x55aa0005
.export vector_table
//.import VecTable
.align 10
vector_table: //totally 256 entries
// .long __start
// .rept 128
// .long __dummy
// .endr
.long __start
.long MisalignedHandler
.long AccessErrHandler
.long DummyHandler
.long IllegalInstrHandler
.long PriviledgeVioHandler
.long DummyHandler
.long BreakPointHandler
.long UnrecExecpHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long Trap0Handler
.long Trap1Handler
.long Trap2Handler
.long Trap3Handler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long DummyHandler
.long PendTrapHandler
.long DummyHandler//CORETHandler
.long DummyHandler//SYSCONIntHandler
.long DummyHandler//IFCIntHandler
.long DummyHandler//ADCIntHandler
.long DummyHandler//EPT0IntHandler
.long DummyHandler//EPT0EMIntHandler
.long DummyHandler//WWDTHandler
.long EXI0IntHandler
.long EXI1IntHandler
.long DummyHandler//GPT0IntHandler
.long DummyHandler//GPT1IntHandler
.long DummyHandler
.long DummyHandler//RTCIntHandler
.long DummyHandler//UART0IntHandler
.long UART1IntHandler
.long UART2IntHandler//USARTIntHandler
.long DummyHandler
.long DummyHandler//I2CIntHandler
.long DummyHandler
.long DummyHandler//SPI0IntHandler
.long DummyHandler//SIO0IntHandler
.long EXI2to3IntHandler
.long EXI4to9IntHandler
.long EXI10to15IntHandler
.long DummyHandler//CNTAIntHandler
.long DummyHandler//TKEYIntHandler
.long DummyHandler//LPTIntHandler
.long DummyHandler//LEDIntHandler
.long DummyHandler//BT0IntHandler
.long BT1IntHandler
.long DummyHandler//BT2IntHandler
.long DummyHandler//BT3IntHandler
.long UserOption
.text
.export __start
.long 0x00000000
.long 0x00000000
// .long __start
__start:
//initialize all registers
movi r0, 0
movi r1, 0
movi r2, 0
movi r3, 0
movi r4, 0
movi r5, 0
movi r6, 0
movi r7, 0
//movi r8, 0
//movi r9, 0
//movi r10, 0
//movi r11, 0
//movi r12, 0
//movi r13, 0
//movi r14, 0
//movi r15, 0
//set VBR
lrw r2, vector_table
mtcr r2, cr<1,0>
//enable EE bit of psr
mfcr r2, cr<0,0>
bseti r2, r2, 8
mtcr r2, cr<0,0>
////set rom access delay
// lrw r1, 0xe00000
// lrw r2, 0x7
// st.w r2, (r1,0x0)
////enable cache
// lrw r1, 0xe000f000
// movi r2, 0x2
// st.w r2, (r1,0x0)
// lrw r2, 0x29
// st.w r2, (r1,0x4)
// movi r2, 0x1
// st.w r2, (r1,0x0)
//disable power peak
lrw r1, 0xe000ef90
movi r2, 0x0
st.w r2, (r1, 0x0)
//initialize kernel stack
lrw r7, __kernel_stack
mov r14,r7
subi r6,r7,0x4
//lrw r3, 0x40
lrw r3, 0x04
subu r4, r7, r3
lrw r5, 0x0
INIT_KERLE_STACK:
addi r4, 0x4
st.w r5, (r4)
//cmphs r7, r4
cmphs r6, r4
bt INIT_KERLE_STACK
__to_main:
lrw r0,__main
jsr r0
mov r0, r0
mov r0, r0
lrw r15, __exit
lrw r0,main
jmp r0
mov r0, r0
mov r0, r0
mov r0, r0
mov r0, r0
mov r0, r0
.export __exit
__exit:
lrw r4, 0x20003000
//lrw r5, 0x0
mov r5, r0
st.w r5, (r4)
mfcr r1, cr<0,0>
lrw r1, 0xFFFF
mtcr r1, cr<11,0>
lrw r1, 0xFFF
movi r0, 0x0
st r1, (r0)
.export __fail
__fail:
lrw r1, 0xEEEE
mtcr r1, cr<11,0>
lrw r1, 0xEEE
movi r0, 0x0
st r1, (r0)
__dummy:
br __fail
.export DummyHandler
DummyHandler:
br __fail
.data
.align 10
.long __start

44
Source/arch/mem_init.c Normal file
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/*
* Filename : mem_init.c
*
* Memory Initialization
*
* Copyrights 2015 @ APTCHIP
*
*
*/
#include "string.h"
extern char _end_rodata[];
extern char _start_data[];
extern char _end_data[];
extern char _bss_start[];
extern char _ebss[];
void __main( void )
{
char *dst = _start_data;
char *src = _end_rodata;
/* if the start of data (dst)
is not equal to end of text (src) then
copy it, else it's already in the right place
*/
if( _start_data != _end_rodata ) {
// __memcpy_fast( dst, src, (_end_data - _start_data));
memcpy( dst, src, (_end_data - _start_data));
}
/* zero the bss
*/
if( _ebss - _bss_start ) {
// __memset_fast( _bss_start, 0x00, ( _ebss - _bss_start ));
memset( _bss_start, 0x00, ( _ebss - _bss_start ));
}
}

14
Source/cdkws.mk Normal file
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.PHONY: clean All Project_Title Project_Build
All: Project_Title Project_Build
Project_Title:
@echo "----------Building project:[ MD203F8P - BuildSet ]----------"
Project_Build:
@make -r -f MD203F8P.mk -j 8 -C ./
clean:
@echo "----------Cleaning project:[ MD203F8P - BuildSet ]----------"

58
Source/ckcpu.ld Normal file
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MEMORY
{
ROM(RX) : ORIGIN = 0x00000000, LENGTH = 10K
RAM(RWX) : ORIGIN = 0x20000000, LENGTH = 4K
}
__kernel_stack = ORIGIN(RAM) + LENGTH(RAM) -8 ;
ENTRY(__start)
SECTIONS {
.text :
{
. = ALIGN(0x4) ;
*crt0.o (.text)
*(.text)
} >ROM
.RomCode :
{
. = ALIGN(0x4) ;
*(.text)
} >ROM
.rodata :
{
. = ALIGN(0x4) ;
*(.rodata)
*(.rodata.*)
. = ALIGN(0x4) ;
_end_rodata = .;
} >ROM
.data : AT(_end_rodata)
{
. = ALIGN(0x4) ;
_start_data = .;
*( .data );
. = ALIGN(0x4) ;
_end_data = .;
} >RAM
.bss :
{
. = ALIGN(0x4) ;
_bss_start = . ;
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(0x4) ;
_ebss = . ;
_end = . ;
end = . ;
} >RAM
}

84
Source/doc/APT32F102_Lib_Fix_Log.md Normal file
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#20180129 V1.00 初版
#20180131 V1.02：
1.apt32f102_i2c.h，修改I2C_Slave_CONFIG(); PA0.1定义错误
2.apt32f102_i2c.c，修改void I2C_Slave_Receive(void)
3.apt32f102_interrupt.c，修改LPTIntHandler();
4.syscon.h，修改“SYSCON_SCLKCR_RST ((CSP_REGISTER_T)0xD22Dul<<16)”
5.syscon.C， SYSCON_RST_VALUE(void) ；
5.EPT.C &EPT.H 修改
6.syscon.h，修改 INTDET_POL_X_TypeDef枚举;
7.apt32f102_initial.c ，修改EPT0_Config()；
8.apt32f102_interrupt.c，修改EPT0IntHandler();
9.修改了CRC输入函数，分32/16/8bit数据输入
10.增加了GPT同步及触发事件函数
11.增加了WWDT初始化函数
#20201124 V1.02：
1.修改UART_IO_Init(); PA0.15 PA0.14初始化
2.删除SYSCON_CONFIG()；"EVTRG function 程序屏蔽"
3.删除了tkey相关残留的程序
#20201124 V1.03：
1.增加了touch key库文件
#20201202 V1.04：
1.修改了SYSCON_General_CMD();函数，fix 使用外部晶振后调试口被占用的问题
2.修改了BT PB0.0配置错误的问题
3.修改了外部中断向量EXI9错误的问题
4.修改了外部中断向量EXI4to9IntHandle，EXI10to15IntHandler
5.修改了GPT.h中PB0.1定义错误的问题
6.增加了IFC读ReadDataArry_U8函数，读数据时字节长度可不按4的倍数
7.修改了spi.c中PA0.8配置错误的问题
#20200121 V1.05：
1.修改了ADC初始化中的错误
2.修改了apt32f102_interrupt.c中EXI15的错误
3.修改了BT.c中BT0和BT1混淆的问题
4.修复了使用触摸FVR参考时，调用ADC造成触摸失灵的问题
5.增加了tkey的睡眠睡醒功能
6.修改了1.04 .s文件中外部中断定义错误的问题
#20210601 V1.06：
1.修改了COUNTERA IO配置错误
2.修改了BT中IO配置错误
3.修改了EPT PB0.5 CHAY配置错误
4.修改了EPT 外部触发端口使能配置相反的错误
5.增加了I2C做从机时配置i2c中断优先级为最高的配置
6.修改了调用GPIO_DeInit后调试口被修改的问题
7.修复了TK在FVR模式以外开启TCH3后触摸初始化卡死的问题
8.修改了TK参数配置中，使能TK的方式，采用更直观的方式
9.修改了TK参数配置中，EC默认电压为3V，FVR参考默认2.048V，防止客户使用3.3V工作电压时一开始TK无法工作的问题
#20210621 V1.08：
1.解决了触摸长时间睡眠后，唤醒失败的问题（功耗增加10uA）
2.修改了注释为英文
3.修改了不同版本的触摸库文件方便不同应用
#20210801 V1.09：
1.修改了syscon.c，解决了系统主频在切换时偶尔遇到的时钟卡死问题
2.增加了IO remap功能函数
3.修正1_09和1_09M这两个版本.a库，多键模式按键误清零的问题
4.删除之前版本initial.c中对EVTRG function的配置，以解决因此产生的某些情况下睡眠后功耗异常的问题
#20210825 V1.10：
1.修改了SPI做从机时，PA0.14/PA0.15配置错误的问题
2.修改了RTC中参数的定义为volatile，解决某些意外情况下进位时小时位出现错误值的问题
3.增加了BT中控制波形stop时输出高/低电平函数
4.修改gpio.c中配置外部组扩展配置时PB0组IO无法配置的问题,增加了EXI16~19的中断函数
5.syscon中加入clo输出配置函数
6.在syscon.c中增加Set_INT_Priority();函数，可直接配置中断优先级
7.在fwlib文件夹增加了iostring.c文件
8.修改库文件包名称为APT32F102x_StdPeriph_Lib
#20211101 V1.11：
1.修改了SIO做RX时，配置错误的问题
2.增加了debug print功能
3.增加了芯片svc文件，方便查看芯片register内容
4.解决了TK和ADC选择不同参考源时造成的互相影响的问题，修改了ADC.c和TK库文件
5.修改了EPT中EVTRG配置移位错误
#20211122 V1.12：
1.修改了GPT 同步触发模式的配置定义错误
2.增加了频率校准函数std_clk_calib();支持HFOSC IMOSC频率软件校准；
3.lib_102ClkCalib_1_03，修改了1.02的校准库在与触摸低功耗共同使用时，会造成睡眠功耗偏大到1.2mA的问题
#20211213 V1.13：
1.修改了在使用ADC时，因为配置ADC序列和序列个数不一致而可能引起的ADC卡死问题
2.修改了UART初始化使能函数，解决了因配置顺序导致INT_TX_DONE中断无法进入的问题
3.修改了IFC_MR中不同时钟频率下WAIT和SPEED默认值
4.解除了TK使用FVR模式参考电压固定选择4.096V的限制，可选择2.048V"抗干扰能力低于4.096V"
#20220825 V1.15：
1.修改去除部分编译中出现的警告
2.修改触摸库函数，增加因异常情况overflow后造成的按键扫描卡住问题
3.修改部分代码中注释的书写问题
4.修改了uart初始化中奇偶校验错误的问题

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#Touch Key库最新版本V1.15
#Touch Key中断扫描版本
lib_102TKey_1_15.a 触摸库文件完整版(默认库文件)
lib_102TKey_1_15C.a 触摸库文件精简版，程序占用空间更小，扫描速度更快，抗干扰性能降低，睡眠功耗更低
#Touch Key主循环扫描版本
lib_102TKey_1_15M.a 触摸库文件主循环扫描完整版，不支持睡眠唤醒
lib_102TKey_1_15MC.a 触摸库文件主循环扫描精简版，程序占用空间更小，扫描速度更快，抗干扰性能降低，去除coret占用，没有长按强制更新功能，不支持睡眠唤醒
#说明：
C---Compression
M---Main Loop
#注意：
1. 使用Touch Key主循环扫描版本，需要在主循环中添加tk_prgm();函数，每次执行时间在1~1.8ms之间
2. 未使用coret功能的版本，需要在apt32f102_interrupt.c中重新打开CORETHandler()入口
3. 中断扫描版本：每一轮的按键扫描时间可控，触摸体验良好；会占用中断资源，如果有高时序要求的中断，没有配置中断好中断优先级的话会影响高时序要求的中断
4. 主循环版本：不会占用中断资源，对别的中断不会有影响；每一轮的按键扫描时间不可控，如果主循环一次循环里有函数占用大量时间，会影响按键的触摸体验
5. 使用1.15版本，必须在linker中包含libm数学库

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/*
******************************************************************************
* @file apt32f102.c
* @author APT AE Team
* @version V1.01
* @date 2019/04/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/**
* @addtogroup Struct pointer assignment Functions
* @{
*/
CSP_CK801_T *CK801 = (CSP_CK801_T *)CK801_BASEADDR ;
CSP_IFC_T *IFC = (CSP_IFC_T *)APB_IFCBase ;
CSP_SYSCON_T *SYSCON = (CSP_SYSCON_T *)APB_SYSCONBase ;
CSP_TKEY_T *TKEY = (CSP_TKEY_T *)APB_TKEYBase ;
CSP_TKEYBUF_T *TKEYBUF = (CSP_TKEYBUF_T *)APB_TKEYBUFBase;
CSP_ADC12_T *ADC0 = (CSP_ADC12_T *)APB_ADC0Base ;
CSP_GPIO_T *GPIOA0 = (CSP_GPIO_T *)APB_GPIOA0Base ; // A0
CSP_GPIO_T *GPIOB0 = (CSP_GPIO_T *)APB_GPIOB0Base ; // B0
CSP_IGRP_T *GPIOGRP = (CSP_IGRP_T *)APB_IGRPBase;
CSP_UART_T *UART0 = (CSP_UART_T *)APB_UART0Base ;
CSP_UART_T *UART1 = (CSP_UART_T *)APB_UART1Base ;
CSP_UART_T *UART2 = (CSP_UART_T *)APB_UART2Base ;
CSP_SSP_T *SPI0 = (CSP_SSP_T *)APB_SPI0Base ;
CSP_I2C_T *I2C0 = (CSP_I2C_T *)APB_I2C0Base ;
CSP_SIO_T *SIO0 = (CSP_SIO_T *)APB_SIO0Base ;
CSP_CA_T *CA0 = (CSP_CA_T *)APB_CNTABase ;
CSP_GPT_T *GPT0 = (CSP_GPT_T *)APB_GPT0Base;
CSP_EPT_T *EPT0 = (CSP_EPT_T *)APB_EPT0Base ;
CSP_ETCB_T *ETCB = (CSP_ETCB_T *)APB_ETCBBase ;
CSP_RTC_T *RTC = (CSP_RTC_T *)APB_RTCBase ;
CSP_LPT_T *LPT = (CSP_LPT_T *)APB_LPTBase ;
CSP_WWDT_T *WWDT = (CSP_WWDT_T *)APB_WWDTBase ;
CSP_BT_T *BT0 = (CSP_BT_T *)APB_BT0Base ;
CSP_BT_T *BT1 = (CSP_BT_T *)APB_BT1Base ;
CSP_CRC_T *CRC = (CSP_CRC_T *)AHB_CRCBase ;
CSP_HWD_T *HWD = (CSP_HWD_T *)APB_HWDBase ;
int __divsi3 ( int a, int b)
{
int PSR;
__asm volatile(
"mfcr %0 , psr \n\r"
"psrclr ie \n\r"
: "=r"(PSR)
);
HWD->CR = 0;
HWD->DIVIDENT = a;
HWD->DIVISOR = b;
PSR |= 0x80000000;
__asm volatile(
"mtcr %0 , psr \n\r"
:
:"r"(PSR)
);
return HWD->QUOTIENT;
}
unsigned int __udivsi3 ( unsigned int a, unsigned int b)
{
int PSR;
__asm volatile(
"mfcr %0 , psr \n\r"
"psrclr ie \n\r"
: "=r"(PSR)
);
HWD->CR = 1;
HWD->DIVIDENT = a;
HWD->DIVISOR = b;
PSR |= 0x80000000;
__asm volatile(
"mtcr %0 , psr \n\r"
:
:"r"(PSR)
);
return HWD->QUOTIENT;
}
int __modsi3 ( int a, int b)
{
int PSR;
__asm volatile(
"mfcr %0 , psr \n\r"
"psrclr ie \n\r"
: "=r"(PSR)
);
HWD->CR = 0;
HWD->DIVIDENT = a;
HWD->DIVISOR = b;
PSR |= 0x80000000;
__asm volatile(
"mtcr %0 , psr \n\r"
:
:"r"(PSR)
);
return HWD->REMAIN;
}
unsigned int __umodsi3 ( unsigned int a, unsigned int b)
{
int PSR;
__asm volatile(
"mfcr %0 , psr \n\r"
"psrclr ie \n\r"
: "=r"(PSR)
);
HWD->CR = 1;
HWD->DIVIDENT = a;
HWD->DIVISOR = b;
PSR |= 0x80000000;
__asm volatile(
"mtcr %0 , psr \n\r"
:
:"r"(PSR)
);
return HWD->REMAIN;
}
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ck801.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#include "apt32f102_ck801.h"
void CK801_Init(void)
{
/* Initial the Interrupt source priority level registers */
CK801->IPR[0] = 0xC0804000;
CK801->IPR[1] = 0xC0004000;
CK801->IPR[2] = 0xC0804000;
CK801->IPR[3] = 0xC0804000;
CK801->IPR[4] = 0xC0804000;
CK801->IPR[5] = 0xC0804000;
CK801->IPR[6] = 0xC0804000;
CK801->IPR[7] = 0xC0804000;
CK801->IPTR = 0x00000000;//disable threshold
}
void force_interrupt(IRQn_Type IRQn)
{
CK801->ISPR = (1 << (uint32_t)(IRQn));
}
void CK_CPU_EnAllNormalIrq(void)
{
asm ("psrset ee,ie");
}
void CK_CPU_DisAllNormalIrq(void)
{
asm ("psrclr ie");
}
/* ########################## NVIC functions #################################### */
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn The positive number of the external interrupt to enable
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
__INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
CK801->ISER = 1 << (uint32_t)(IRQn);
}
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn The positive number of the external interrupt to disable
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
__INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
CK801->ICER = 1 << (uint32_t)(IRQn);
}
/**
* @brief Read the interrupt pending bit for a device specific interrupt source
*
* @param IRQn The number of the device specifc interrupt
* @return always 0
*/
__INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return (uint32_t)(CK801->ISPR);
}
/**
* @brief Set the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for set pending
*
* No effect.
*/
__INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
CK801->ISPR = (1 << (uint32_t)(IRQn));
}
/**
* @brief Clear the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for clear pending
*
* No effect.
*/
__INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
CK801->ICPR = (1 << (uint32_t)(IRQn));
}
/**
* @brief Read the active bit for an external interrupt
*
* @return always 0
*
*/
__INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return (CK801->IABR & (1 << IRQn));
}
__INLINE uint32_t NVIC_GetActiveVector(void)
{
unsigned int vectactive = 0;
//isr low 8bits gives the active vector
vectactive = (CK801 ->ISR & 0xff);
return vectactive;
}
/**
* @brief Set the priority for an interrupt
*
* @param IRQn The number of the interrupt for set priority
* @param priority The priority to set ,the number rang: [0-3]
*
* Set the priority for the specified interrupt. The interrupt
* number must be positive to specify an external (device specific)
* interrupt.
*/
__INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
uint32_t tmp = ((IRQn & 0x03) << 3);
uint8_t index = IRQn>>2;
if(IRQn >= 0) {
CK801->IPR[index] &= ~(0xff << tmp);
CK801->IPR[index] |= priority << (tmp+6);
}
}
/**
* @brief Read the priority for an interrupt
*
* @param IRQn The number of the interrupt for get priority
* @return The priority for the interrupt
*
* Read the priority for the specified interrupt. The interrupt
* number must be positive to specify an external (device specific)
* interrupt.
*/
__INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
uint32_t tmp = ((IRQn & 0x03) << 3);
uint8_t index = IRQn>>2;
return (uint32_t)(CK801->IPR[index])>>(tmp + 6);
}
/*###################################################################*/
/*############# Threshold Enable & Set Threshold ###############*/
/*###################################################################*/
/************************************************************
* @brief enable NVIC threshold
* @name: NVIC_EnableThreshold
* @no param
*
*/
__INLINE void NVIC_EnableThreshold(void)
{
CK801 ->IPTR |= 0x80000000;
}
/************************************************************
* @brief disnable NVIC threshold
* @name: NVIC_DisableThreshold
* @no param
*
*/
__INLINE void NVIC_DisableThreshold(void)
{
CK801 ->IPTR &= ~0x80000000;
}
/************************************************************
* @brief set NVIC Priothreshold
* @name: NVIC_SetPrioThreshold
* @param prioshreshold the priority of threshold[0,3]
*
*/
__INLINE void NVIC_SetPrioThreshold(uint8_t prioshreshold)
{
CK801 -> IPTR &= 0xffffff00;
CK801 -> IPTR |= (prioshreshold << 6);
}
/************************************************************
* @brief set NVIC Vectthreshold
* @name: NVIC_SetVectThreshold
* @param vectthreshold the vector of threshold[0,31]
*
*/
__INLINE void NVIC_SetVectThreshold(uint8_t vectthreshold)
{
CK801 -> IPTR &= 0xffff00ff;
CK801 -> IPTR |= ((vectthreshold + 32) << 8);
}
/*###################################################################*/
/*################ Low Power Wakeup Enable ###################*/
/*###################################################################*/
/*************************************************************
* @name: NVIC_PowerWakeUp_Enable
* @brief: enable the bit for Power wake up
* @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn
*/
__INLINE void NVIC_PowerWakeUp_Enable(IRQn_Type irqn)
{
CK801->IWER |= (1 << irqn);
}
/*************************************************************
* @name: NVIC_PowerWakeUp_Disable
* @func: disable the bit for Power wake up
* @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn
*/
__INLINE void NVIC_PowerWakeUp_Disable(IRQn_Type irqn)
{
CK801->IWDR |= (1 << irqn);
}
/*************************************************************
* @name: NVIC_PowerWakeUp_EnableAll
* @func: enable all bits for Power wake up
* @param: none
*/
__INLINE void NVIC_PowerWakeUp_EnableAll(void)
{
CK801->IWER = 0xffffffff;
}
/*************************************************************
* @name: NVIC_PowerWakeUp_EnableAll
* @func: disable all bits for Power wake up
* @param: none
*/
__INLINE void NVIC_PowerWakeUp_DisableAll(void)
{
CK801->IWDR = 0xffffffff;
}
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_initial.c
* @author APT AE Team
* @version V1.08
* @date 2018/11/01
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_H
#define _apt32f102_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_types_local.h"
#include "apt32f102_ck801.h"
/**
@brief CK801 bits Structure
*/
typedef struct {
volatile unsigned int ReservedA[4]; //0xE000E000
volatile unsigned int CORET_CSR; //0xE000E010
volatile unsigned int CORET_RVR; //0xE000E014
volatile unsigned int CORET_CVR; //0xE000E018
volatile unsigned int CORET_CALIB; //0xE000E01C
volatile unsigned int ReservedB[56]; //0xE000E020
volatile unsigned int ISER; //0xE000E100
volatile unsigned int ReservedC[15]; //
volatile unsigned int IWER; //0xE000E140
volatile unsigned int ReservedD[15]; //
volatile unsigned int ICER; //0xE000E180
volatile unsigned int ReservedE[15]; //
volatile unsigned int IWDR; //0xE000E1C0
volatile unsigned int ReservedF[15]; //
volatile unsigned int ISPR; //0xE000E200
volatile unsigned int ReservedG[31]; //
volatile unsigned int ICPR; //0xE000E280
volatile unsigned int ReservedH[31]; //
volatile unsigned int IABR; //0xE000E300
volatile unsigned int ReservedI[63]; //
volatile unsigned int IPR[8]; //0xE000E400 ~ 0xE000E41C
volatile unsigned int ReservedJ[504]; //
volatile unsigned int ISR; //0xE000EC00
volatile unsigned int IPTR; //0xE000EC04
} CSP_CK801_T;
/**
@brief IFC bits Structure
*/
typedef volatile struct {
volatile unsigned int IDR ;
volatile unsigned int CEDR ;
volatile unsigned int SRR ;
volatile unsigned int CMR ;
volatile unsigned int CR ;
volatile unsigned int MR ;
volatile unsigned int FM_ADDR ;
volatile unsigned int Reserved ;
volatile unsigned int KR ;
volatile unsigned int IMCR ;
volatile unsigned int RISR ;
volatile unsigned int MISR ;
volatile unsigned int ICR ;
} CSP_IFC_T ;
/**
@brief SYSCON bits Structure
*/
typedef volatile struct { /*!< SYSCON Structure */
volatile unsigned int IDCCR; /*!< 0x000: Identification & System Controller Clock Control Register */
volatile unsigned int GCER; /*!< 0x004: System Controller General Control Enable Register */
volatile unsigned int GCDR; /*!< 0x008: System Controller General Control Disable Register */
volatile unsigned int GCSR; /*!< 0x00C: System Controller General Control Status Register */
volatile unsigned int CKST; /*!< 0x010*/
volatile unsigned int RAMCHK; /*!< 0x014*/
volatile unsigned int EFLCHK; /*!< 0x018*/
volatile unsigned int SCLKCR; /*!< 0x01C: System Controller System Clock Selection & Division Register */
volatile unsigned int PCLKCR; /*!< 0x020: System Controller Peripheral Clock Selection & Division Register */
volatile unsigned int _RSVD0; /*!< 0x024*/
volatile unsigned int PCER0; /*!< 0x028: System Controller Peripheral Clock Enable Register */
volatile unsigned int PCDR0; /*!< 0x02C: System Controller Peripheral Clock Disable Register */
volatile unsigned int PCSR0; /*!< 0x030: System Controller Peripheral Clock Status Register */
volatile unsigned int PCER1; /*!< 0x034: System Controller Peripheral Clock Enable Register */
volatile unsigned int PCDR1; /*!< 0x038: System Controller Peripheral Clock Disable Register */
volatile unsigned int PCSR1; /*!< 0x03C: System Controller Peripheral Clock Status Register */
volatile unsigned int OSTR; /*!< 0x040: System Controller External OSC Stable Time Control Register */
volatile unsigned int _RSVD1; /*!< 0x044: System Controller PLL Stable Time Control Register */
volatile unsigned int _RSVD2; /*!< 0x048: System Controller PLL PMS Value Control Register */
volatile unsigned int LVDCR; /*!< 0x04C: System Controller LVD Control Register */
volatile unsigned int CLCR; /*!< 0x050: System Controller IMOSC Fine Adjustment Register*/
volatile unsigned int PWRCR; /*!< 0x054: System Controller Power Control Register */
volatile unsigned int PWRKEY; /*!< 0x058: System Controller Power Control Register */
volatile unsigned int _RSVD3; /*!< 0x05C: */
volatile unsigned int _RSVD4; /*!< 0x060: */
volatile unsigned int OPT1; /*!< 0x064: System Controller OSC Trim Control Register */
volatile unsigned int OPT0; /*!< 0x068: System Controller Protection Control Register */
volatile unsigned int WKCR; /*!< 0x06C: System Controller Clock Quality Check Control Register */
volatile unsigned int _RSVD5; /*!< 0x070: System Controller Clock Quality Check Control Register */
volatile unsigned int IMER; /*!< 0x074: System Controller Interrupt Enable Register */
volatile unsigned int IMDR; /*!< 0x078: System Controller Interrupt Disable Register */
volatile unsigned int IMCR; /*!< 0x07C: System Controller Interrupt Mask Register */
volatile unsigned int IAR; /*!< 0x080: System Controller Interrupt Active Register */
volatile unsigned int ICR; /*!< 0x084: System Controller Clear Status Register */
volatile unsigned int RISR; /*!< 0x088: System Controller Raw Interrupt Status Register */
volatile unsigned int MISR; /*!< 0x08C: System Controller Raw Interrupt Status Register */
volatile unsigned int RSR; /*!< 0x090: System Controller Raw Interrupt Status Register */
volatile unsigned int EXIRT; /*!< 0x094: System Controller Reset Status Register */
volatile unsigned int EXIFT; /*!< 0x098: System Controller External Interrupt Mode 1 (Positive Edge) Register */
volatile unsigned int EXIER; /*!< 0x09C: System Controller External Interrupt Mode 2 (Negative Edge) Register */
volatile unsigned int EXIDR; /*!< 0x0A0: System Controller External Interrupt Enable Register */
volatile unsigned int EXIMR; /*!< 0x0A4: System Controller External Interrupt Disable Register */
volatile unsigned int EXIAR; /*!< 0x0A8: System Controller External Interrupt Mask Register */
volatile unsigned int EXICR; /*!< 0x0AC: System Controller External Interrupt Active Register */
volatile unsigned int EXIRS; /*!< 0x0B0: System Controller External Interrupt Clear Status Register */
volatile unsigned int IWDCR; /*!< 0x0B4: System Controller Independent Watchdog Control Register */
volatile unsigned int IWDCNT; /*!< 0x0B8: SystCem Controller Independent Watchdog Counter Value Register */
volatile unsigned int IWDEDR; /*!< 0x0BC: System Controller Independent Watchdog Enable/disable Register*/
volatile unsigned int IOMAP0; /*!< 0x0C0: Customer Information Content mirror of 1st byte*/
volatile unsigned int IOMAP1; /*!< 0x0C4: Customer Information Content mirror of 1st byte*/
volatile unsigned int CINF0; /*!< 0x0C8: Customer Information Content mirror of 1st byte*/
volatile unsigned int CINF1; /*!< 0x0CC: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF0; /*!< 0x0D0: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF1; /*!< 0x0D4: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF2; /*!< 0x0D8: Customer Information Content mirror of 1st byte*/
volatile unsigned int _RSVD6; /*!< 0x0DC: Customer Information Content mirror of 1st byte*/
volatile unsigned int ERRINF; /*!< 0x0E0:*/
volatile unsigned int UID0 ; /*!< 0x0E4: Customer Information Content mirror of 1st byte*/
volatile unsigned int UID1 ; /*!< 0x0E8: Customer Information Content mirror of 1st byte*/
volatile unsigned int UID2 ; /*!< 0x0EC: Customer Information Content mirror of 1st byte*/
volatile unsigned int PWROPT; /*!< 0x0F0: Power recovery timmming control */
volatile unsigned int EVTRG; /*!< 0x0F4: Trigger gen */
volatile unsigned int EVPS; /*!< 0x0F8: Trigger prs */
volatile unsigned int EVSWF; /*!< 0x0FC: Trigger software force */
volatile unsigned int UREG0; /*!< 0x100: User defined reg0 */
volatile unsigned int UREG1; /*!< 0x104: User defined reg1 */
volatile unsigned int UREG2; /*!< 0x108: User defined reg0 */
volatile unsigned int UREG3; /*!< 0x10C: User defined reg1 */
} CSP_SYSCON_T;
/**
@brief ETCB bits Structure
*/
typedef volatile struct
{
volatile unsigned int EN; /* ETCB Enable */
volatile unsigned int SWTRG; /* ETCB Software Trigger Generator */
volatile unsigned int CH0CON0; /* ETCB Channel 0 Control Register 0 */
volatile unsigned int CH0CON1; /* ETCB Channel 0 Control Register 1 */
volatile unsigned int CH1CON0; /* ETCB Channel 1 Control Register 0 */
volatile unsigned int CH1CON1; /* ETCB Channel 1 Control Register 1 */
volatile unsigned int CH2CON0; /* ETCB Channel 2 Control Register 0 */
volatile unsigned int CH2CON1; /* ETCB Channel 2 Control Register 1 */
volatile unsigned int _RSVD0;
volatile unsigned int _RSVD1;
volatile unsigned int _RSVD2;
volatile unsigned int _RSVD3;
volatile unsigned int CH3CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH4CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH5CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH6CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH7CON; /* ETCB Channel 3 Control Register */
} CSP_ETCB_T, *CSP_ETCB_PTR;
/**
@brief TKEY bits Structure
*/
typedef volatile struct
{
volatile unsigned int TCH_CCR; /* Control Register */
volatile unsigned int TCH_CON0; /* Control Register */
volatile unsigned int TCH_CON1; /* Control Register */
volatile unsigned int TCH_SCCR; /* Hardmacro control */
volatile unsigned int TCH_SENPRD; /* Sensing target value */
volatile unsigned int TCH_VALBUF; /* Reference value capture value*/
volatile unsigned int TCH_SENCNT; /* Sensing counter value*/
volatile unsigned int TCH_TCHCNT; /* Reference counter value*/
volatile unsigned int TCH_THR; /* Match Status */
volatile unsigned int Reserved0;
volatile unsigned int TCH_RISR; /* Interrupt Enable */
volatile unsigned int TCH_IER; /* Interrupt Clear */
volatile unsigned int TCH_ICR; /* Sensing target value */
volatile unsigned int TCH_RWSR; /* Reference value capture value*/
volatile unsigned int TCH_OVW_THR; /* Sensing counter value*/
volatile unsigned int TCH_OVF; /* Reference counter value*/
volatile unsigned int TCH_OVT; /* Match Status */
volatile unsigned int TCH_SYNCR; /* Interrupt Enable */
volatile unsigned int TCH_EVTRG; /* Interrupt Clear */
volatile unsigned int TCH_EVPS; /* Sensing target value */
volatile unsigned int TCH_EVSWF; /* Reference value capture value*/
} CSP_TKEY_T, *CSP_TKEY_PTR;
/**
@brief TKEY advance bits Structure
*/
typedef volatile struct
{
volatile unsigned int TCH_CHVAL[18]; /* Reference value capture value */
volatile unsigned int TCH_SEQCON[18]; /* SEQ Hardmacro control */
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;
/**
@brief ADC0 bits Structure
*/
typedef volatile struct
{
volatile unsigned int ECR; /**< Clock Enable Register */
volatile unsigned int DCR; /**< Clock Disable Register */
volatile unsigned int PMSR; /**< Power Management Status Register */
volatile unsigned int Reserved0;
volatile unsigned int CR; /**< Control Register */
volatile unsigned int MR; /**< Mode Register */
volatile unsigned int SHR;
volatile unsigned int CSR; /**< Clear Status Register */
volatile unsigned int SR; /**< Status Register */
volatile unsigned int IER; /**< Interrupt Enable Register */
volatile unsigned int IDR; /**< Interrupt Disable Register */
volatile unsigned int IMR; /**< Interrupt Mask Register */
volatile unsigned int SEQ[16]; /**< Conversion Mode Register 0~11 */
volatile unsigned int PRI; /**< Conversion Priority Register */
volatile unsigned int TDL0; /**< Trigger Delay control Register */
volatile unsigned int TDL1; /**< Trigger Delay control Register */
volatile unsigned int SYNCR; /**< Sync Control Register */
volatile unsigned int Reserved1; /**< Trigger Filter Control Register */
volatile unsigned int Reserved2; /**< Trigger Filter Window Register */
volatile unsigned int EVTRG; /**< Event Trigger Control Register */
volatile unsigned int EVPS; /**< Event Prescale Register */
volatile unsigned int EVSWF; /**< Event Softtrig Register */
volatile unsigned int ReservedD[27];
volatile unsigned int DR[16]; /**< Convert Data Register */
volatile unsigned int CMP0; /**< Comparison Data Register */
volatile unsigned int CMP1; /**< Comparison Data Register */
volatile unsigned int DRMASK;
} CSP_ADC12_T, *CSP_ADC12_PTR;
/**
@brief GPIOX bits Structure
*/
typedef volatile struct
{
volatile unsigned int CONLR; /**< Control Low Register */
volatile unsigned int CONHR; /**< Control High Register */
volatile unsigned int WODR; /**< Write Output Data Register */
volatile unsigned int SODR; /**< Set Output Data (bit-wise) Register */
volatile unsigned int CODR; /**< Clear Output Data (bit-wise) Register*/
volatile unsigned int ODSR; /**< Output Data Status Register */
volatile unsigned int PSDR; /**< Pin Data Status Register */
volatile unsigned int FLTEN;
volatile unsigned int PUDR; /**< IO Pullup_Pulldown Register */
volatile unsigned int DSCR; /**< Output Driving Strength Register */
volatile unsigned int OMCR; /**< Slew-rate, Open-Drain Control */
volatile unsigned int IECR; /**< EXI enable control */
volatile unsigned int IEER;
volatile unsigned int IEDR;
} CSP_GPIO_T, *CSP_GPIO_PTR;
typedef volatile struct
{
volatile unsigned int IGRPL; /**< EXI group control */
volatile unsigned int IGRPH; /**< EXI group control */
volatile unsigned int IGREX;
volatile unsigned int IO_CLKEN;
} CSP_IGRP_T, *CSP_IGRP_PTR;
/**
@brief UART0~UART1 bits Structure
*/
typedef volatile struct
{
volatile unsigned int DATA; /**< Write and Read Data Register */
volatile unsigned int SR; /**< Status Register */
volatile unsigned int CTRL; /**< Control Register */
volatile unsigned int ISR; /**< Interrupt Status Register */
volatile unsigned int BRDIV; /**< Baud Rate Generator Register */
volatile unsigned int ReservedA[20];
} CSP_UART_T, *CSP_UART_PTR;
/**
@brief SPI0 bits Structure
*/
typedef struct
{
volatile unsigned int CR0; /**< Control Register 0 */
volatile unsigned int CR1; /**< Control Register 1 */
volatile unsigned int DR; /**< Receive FIFO(read) and transmit FIFO data register(write) */
volatile unsigned int SR; /**< Status register */
volatile unsigned int CPSR; /**< Clock prescale register */
volatile unsigned int IMSCR; /**< Interrupt mask set and clear register */
volatile unsigned int RISR; /**< Raw interrupt status register */
volatile unsigned int MISR; /**< Masked interrupt status register */
volatile unsigned int ICR; /**< Interrupt clear register */
} CSP_SSP_T, *CSP_SSP_PTR;
/**
@brief SIO0 bits Structure
*/
typedef struct
{
volatile unsigned int CR;
volatile unsigned int TXCR0;
volatile unsigned int TXCR1;
volatile unsigned int TXBUF;
volatile unsigned int RXCR0;
volatile unsigned int RXCR1;
volatile unsigned int RXCR2;
volatile unsigned int RXBUF;
volatile unsigned int RISR;
volatile unsigned int MISR;
volatile unsigned int IMCR;
volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;
/**
@brief I2C0 bits Structure
*/
typedef volatile struct
{
unsigned int CR; /* I2C Control */
unsigned int TADDR; /* I2C Target Address */
unsigned int SADDR; /* I2C Slave Address */
unsigned int ReservedD;
unsigned int DATA_CMD; /* I2C Rx/Tx Data Buffer and Command */
unsigned int SS_SCLH; /* I2C Standard Speed SCL High Count */
unsigned int SS_SCLL; /* I2C Standard Speed SCL Low Count */
unsigned int FS_SCLH; /* I2C Fast mode and Fast Plus SCL High Count*/
unsigned int FS_SCLL; /* I2C Fast mode and Fast Plus SCL Low Count*/
unsigned int ReservedA; /* I2C High Speed SCL High Count */
unsigned int ReservedC; /* I2C High Speed SCL Low Count */
unsigned int RX_FLSEL; /* I2C Receive FIFO Threshold */
unsigned int TX_FLSEL; /* I2C Transmit FIFO Threshold */
unsigned int RX_FL; /* I2C Receive FIFO Level */
unsigned int TX_FL; /* I2C Transmit FIFO Level */
unsigned int ENABLE; /* I2C Enable */
unsigned int STATUS; /* I2C Status */
unsigned int ReservedB; /* I2C Enable Status */
unsigned int SDA_TSETUP; /* I2C SDA Setup Time */
unsigned int SDA_THOLD; /* I2C SDA hold time length */
unsigned int SPKLEN; /* I2C SS and FS Spike Suppression Limit */
//unsigned int HS_SPKLEN; /* I2C HS Spike Suppression Limit */
unsigned int ReservedE;
unsigned int MISR; /* I2C Masked Interrupt Status */
unsigned int IMSCR; /* I2C Interrupt Enable */
unsigned int RISR; /* I2C Raw Interrupt Status */
unsigned int ICR; /* I2C Interrupt Clear */
unsigned int ReservedF;
unsigned int SCL_TOUT; /* I2C SCL Stuck at Low Timeout */
unsigned int SDA_TOUT; /* I2C SDA Stuck at Low Timeout */
unsigned int TX_ABRT; /* I2C Transmit Abort Status */
unsigned int GCALL; /* I2C ACK General Call */
unsigned int NACK; /* I2C Generate SLV_DATA_NACK */
} CSP_I2C_T, *CSP_I2C_PTR;
/**
@brief CA0 bits Structure
*/
typedef struct
{
volatile unsigned int CADATAH; /**< DATA High Register */
volatile unsigned int CADATAL; /**< DATA Low Register */
volatile unsigned int CACON; /**< Control Register */
volatile unsigned int INTMASK; /**< Interrupt Mask CR */
} CSP_CA_T, *CSP_CA_PTR;
/**
@brief GPTX bits Structure
*/
typedef struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int GLDCR; //0x0014 Global load control reg
volatile unsigned int GLDCFG; //0x0018 Global load config
volatile unsigned int GLDCR2; //0x001C Global load control reg2
volatile unsigned int Reserved0; //0x0020
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int Reserved1; //0x0028
volatile unsigned int CMPA; //0x002C Compare Value A
volatile unsigned int CMPB; //0x0030 Compare Value B
volatile unsigned int Reserved2; //0x0034
volatile unsigned int Reserved3; //0x0038
volatile unsigned int CMPLDR; //0x003C Cmp reg load control
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int AQLDR; //0x0044 AQ reg load control
volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A
volatile unsigned int AQCRB; //0x004C Action qualify of ch-B
volatile unsigned int Reserved4; //0x0050
volatile unsigned int Reserved5; //0x0054
volatile unsigned int Reserved6; //0x0058
volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing
volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing
volatile unsigned int Reserved7; //0x0064
volatile unsigned int Reserved8; //0x0068
volatile unsigned int Reserved9; //0x006c
volatile unsigned int Reserved10; //0x0070
volatile unsigned int Reserved11; //0x0074
volatile unsigned int Reserved12; //0x0078
volatile unsigned int Reserved13; //0x007c
volatile unsigned int Reserved14; //0x0080
volatile unsigned int Reserved15; //0x0084
volatile unsigned int Reserved16; //0x0088
volatile unsigned int Reserved17; //0x008c
volatile unsigned int Reserved18; //0x0090
volatile unsigned int Reserved19; //0x0094
volatile unsigned int Reserved20; //0x0098
volatile unsigned int Reserved21; //0x009c
volatile unsigned int Reserved22; //0x00a0
volatile unsigned int Reserved23; //0x00a4
volatile unsigned int Reserved24; //0x00a8
volatile unsigned int Reserved25; //0x00ac
volatile unsigned int Reserved26; //0x00b0
volatile unsigned int Reserved27; //0x00b4
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVCNTINIT; //0x00C8
volatile unsigned int EVSWF; //0x00CC Event software forcing
volatile unsigned int RISR; //0x00D0 Interrupt RISR
volatile unsigned int MISR; //0x00D4 Interrupt MISR
volatile unsigned int IMCR; //0x00D8 Interrupt IMCR
volatile unsigned int ICR; //0x00DC Interrupt clear
volatile unsigned int REGLINK; //0x00E0 Register link
}CSP_GPT_T,*CSP_GPT_PTR;
/**
@brief EPT0 bits Structure
*/
typedef struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int GLDCR; //0x0014 Global load control reg
volatile unsigned int GLDCFG; //0x0018 Global load config
volatile unsigned int GLDCR2; //0x001C Global load control reg2
volatile unsigned int HRCFG; //0x0020
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int PHSR; //0x0028 Phase control reg
volatile unsigned int CMPA; //0x002C Compare Value A
volatile unsigned int CMPB; //0x0030 Compare Value B
volatile unsigned int CMPC; //0x0034 Compare Value C
volatile unsigned int CMPD; //0x0038 Compare Value D
volatile unsigned int CMPLDR; //0x003C Cmp reg load control
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int AQLDR; //0x0044 AQ reg load control
volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A
volatile unsigned int AQCRB; //0x004C Action qualify of ch-B
volatile unsigned int AQCRC; //0x0050 Action qualify of ch-C
volatile unsigned int AQCRD; //0x0054 Action qualify of ch-D
volatile unsigned int AQTSCR; //0x0058 T event selection
volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing
volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing
volatile unsigned int DBLDR; //0x0064 Deadband control reg load control
volatile unsigned int DBCR; //0x0068 Deadband control reg
volatile unsigned int DPSCR; //0x006C Deadband clock prescaler
volatile unsigned int DBDTR; //0x0070 Deadband rising delay control
volatile unsigned int DBDTF; //0x0074 Deadband falling delay control
volatile unsigned int CPCR; //0x0078 Chop control
volatile unsigned int EMSRC; //0x007C EM source setting
volatile unsigned int EMSRC2; //0x0080 EM source setting
volatile unsigned int EMPOL; //0x0084 EM polarity setting
volatile unsigned int EMECR; //0x0088 EM enable control
volatile unsigned int EMOSR; //0x008C EM trip out status setting
volatile unsigned int Reserved; //0x0090 Reserved
volatile unsigned int EMSLSR; //0x0094 Softlock status
volatile unsigned int EMSLCLR; //0x0098 Softlock clear
volatile unsigned int EMHLSR; //0x009C Hardlock status
volatile unsigned int EMHLCLR; //0x00A0 Hardlock clear
volatile unsigned int EMFRCR; //0x00A4 Software forcing EM
volatile unsigned int EMRISR; //0x00A8 EM RISR
volatile unsigned int EMMISR; //0x00AC EM MISR
volatile unsigned int EMIMCR; //0x00B0 EM masking enable
volatile unsigned int EMICR; //0x00B4 EM pending clear
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVCNTINIT; //0x00C8
volatile unsigned int EVSWF; //0x00CC Event software forcing
volatile unsigned int RISR; //0x00D0 Interrupt RISR
volatile unsigned int MISR; //0x00D4 Interrupt MISR
volatile unsigned int IMCR; //0x00D8 Interrupt IMCR
volatile unsigned int ICR; //0x00DC Interrupt clear
volatile unsigned int REGLINK; //0x00E0 Register link
volatile unsigned int REGLINK2; //0x00E4 Register link2
volatile unsigned int REGPROT; //0x00E8 Register protection
} CSP_EPT_T, *CSP_EPT_PTR;
/**
@brief LPT bits Structure
*/
typedef volatile struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int CMP; //0x002C Compare Value A
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVSWF; //0x00C8 Event software forcing
volatile unsigned int RISR; //0x00CC Interrupt RISR
volatile unsigned int MISR; //0x00D0 Interrupt MISR
volatile unsigned int IMCR; //0x00D4 Interrupt IMCR
volatile unsigned int ICR; //0x00D8 Interrupt clear
} CSP_LPT_T, *CSP_LPT_PTR;
/**
@brief BT0 bits Structure
*/
typedef struct
{
volatile unsigned int RSSR; //0x0000 Reset/Start Control
volatile unsigned int CR; //0x0004 General Control
volatile unsigned int PSCR; //0x0008 Prescaler
volatile unsigned int PRDR; //0x000C Period
volatile unsigned int CMP; //0X0010
volatile unsigned int CNT; //0x0014 Counter
volatile unsigned int EVTRG; //0x0018 Event Trigger
volatile unsigned int EVPS; //0x001C Event Prescaler
volatile unsigned int EVCNTINTI; //0x0020 Event Counter
volatile unsigned int EVSWF; //0x0024 Software force Event Trigger
volatile unsigned int RISR; //0x0028
volatile unsigned int IMCR; //0x002C
volatile unsigned int MISR; //0x0030
volatile unsigned int ICR; //0x0034
} CSP_BT_T, *CSP_BT_PTR;
/**
@brief CRC bits Structure
*/
typedef struct
{
volatile unsigned int IDR; /**< ID Register */
volatile unsigned int CEDR; /**< Clock Enable/Disable Register */
volatile unsigned int SRR; /**< Software Reset Register */
volatile unsigned int CR; /**< Control Register */
volatile unsigned int SEED; /**< Seed Value Register */
volatile unsigned int DATAIN; /**< Data in Value Register */
volatile unsigned int DATAOUT; /**< Data out Value Register */
// TBD... //
} CSP_CRC_T, *CSP_CRC_PTR;
/**
@brief RTC bits Structure
*/
typedef struct
{
volatile unsigned int TIMR; //0x0000 Time Control Register
volatile unsigned int DATR; //0x0004 Date Control Register
volatile unsigned int CR; //0x0008 Control Register
volatile unsigned int CCR; //0x000C Clock Control register
volatile unsigned int ALRAR; //0x0010 Alarm A
volatile unsigned int ALRBR; //0x0014 Alarm B
volatile unsigned int SSR; //0x0018 Sub second
volatile unsigned int CAL; //0x001C Calibration
volatile unsigned int RISR; //0x0020
volatile unsigned int IMCR; //0x0024
volatile unsigned int MISR; //0x0028
volatile unsigned int ICR; //0x002C
volatile unsigned int KEY; //0x0030
volatile unsigned int EVTRG; //0x0034
volatile unsigned int EVPS; //0x0038
volatile unsigned int EVSWF; //0x003C
} CSP_RTC_T, *CSP_RTC_PTR;
/**
@brief WWDT bits Structure
*/
typedef struct
{
volatile unsigned int CR;
volatile unsigned int CFGR;
volatile unsigned int RISR;
volatile unsigned int MISR;
volatile unsigned int IMCR;
volatile unsigned int ICR;
}CSP_WWDT_T,*CSP_WWDT_PTR;
/**
@brief HWD bits Structure
*/
typedef struct
{
volatile S32_T DIVIDENT;
volatile S32_T DIVISOR;
volatile S32_T QUOTIENT;
volatile S32_T REMAIN;
volatile unsigned int CR;
}CSP_HWD_T,*CSP_HWD_PTR;
#define FLASHBase 0x00000000
#define FLASHSize 0x00010000
#define FLASHLimit (FLASHBase + FLASHSize)
#define DFLASHBase 0x10000000
#define DFLASHSize 0x10001000
#define DFLASHLimit (FLASHBase + FLASHSize)
#ifdef REMAP
#define SRAMBase 0x00000000
#define SRAMSize 0x00000800
#define SRAMLimit (SRAMBase + SRAMSize)
#define MEMVectorBase 0x00000700
#define MEMVectorSize (0x50<<2)
#else
#define SRAMBase 0x20000000
#define SRAMSize 0x00001000
#define SRAMLimit (SRAMBase + SRAMSize)
#define MEMVectorBase 0x20000F00
#define MEMVectorSize (0x50<<2)
#endif
//--Peripheral Address Setting
#define APBPeriBase 0x40000000
//--Each Peripheral Address Setting
//#define APB_SFMBase (APBPeriBase + 0x10000)
#define APB_IFCBase (APBPeriBase + 0x10000)
#define APB_SYSCONBase (APBPeriBase + 0x11000)
#define APB_ETCBBase (APBPeriBase + 0x12000)
#define APB_TKEYBase (APBPeriBase + 0x20000)
#define APB_TKEYBUFBase (APBPeriBase + 0x21000)
#define APB_ADC0Base (APBPeriBase + 0x30000)
#define AHBGPIOBase 0x60000000
#define APB_GPIOA0Base (AHBGPIOBase + 0x0000) //A0
#define APB_GPIOB0Base (AHBGPIOBase + 0x2000) //B0
#define APB_IGRPBase (AHBGPIOBase + 0xF000)
#define APB_BT1Base (APBPeriBase + 0x52000)
#define APB_BT0Base (APBPeriBase + 0x51000)
#define APB_CNTABase (APBPeriBase + 0x50000)
#define APB_GPT0Base (APBPeriBase + 0x55000)
#define APB_EPT0Base (APBPeriBase + 0x59000)
#define APB_RTCBase (APBPeriBase + 0x60000)
#define APB_LPTBase (APBPeriBase + 0x61000)
#define APB_WWDTBase (APBPeriBase + 0x62000)
#define APB_UART0Base (APBPeriBase + 0x80000)
#define APB_UART1Base (APBPeriBase + 0x81000)
#define APB_UART2Base (APBPeriBase + 0x82000)
#define APB_SPI0Base (APBPeriBase + 0x90000)
#define APB_SIO0Base (APBPeriBase + 0xB0000)
#define APB_I2C0Base (APBPeriBase + 0xA0000)
#define AHB_CRCBase 0x50000000
#define APB_HWDBase 0x70000000
//--Interrupt Bit Position
#define CORET_INT (0x01ul<<0) //IRQ0
#define SYSCON_INT (0x01ul<<1) //IRQ1
#define IFC_INT (0x01ul<<2) //IRQ2
#define ADC_INT (0x01ul<<3) //IRQ3
#define EPT0_INT (0x01ul<<4) //IRQ4
//DUMMY //IRQ5
#define WWDT_INT (0x01ul<<6) //IRQ6
#define EXI0_INT (0x01ul<<7) //IRQ7
#define EXI1_INT (0x01ul<<8) //IRQ8
#define GPT0_INT (0x01ul<<9) //IRQ9
//DUMMY //IRQ10
//DUMMY //IRQ11
#define RTC_INT (0x01ul<<12) //IRQ12
#define UART0_INT (0x01ul<<13) //IRQ13
#define UART1_INT (0x01ul<<14) //IRQ14
#define UART2_INT (0x01ul<<15) //IRQ15
//DUMMY //IRQ16
#define I2C_INT (0x01ul<<17) //IRQ17
//DUMMY //IRQ18
#define SPI_INT (0x01ul<<19) //IRQ19
#define SIO_INT (0x01ul<<20) //IRQ20
#define EXI2_INT (0x01ul<<21) //IRQ21
#define EXI3_INT (0x01ul<<22) //IRQ22
#define EXI4_INT (0x01ul<<23) //IRQ23
#define CA_INT (0x01ul<<24) //IRQ24
#define TKEY_INT (0x01ul<<25) //IRQ25
#define LPT_INT (0x01ul<<26) //IRQ26
//DUMMY //IRQ27
#define BT0_INT (0x01ul<<28) //IRQ28
#define BT1_INT (0x01ul<<29) //IRQ29
//DUMMY //IRQ30
//DUMMY //IRQ31
extern CSP_CK801_T *CK801 ;
extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;
extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;
extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;
extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;
extern CSP_GPT_T *GPT0 ;
extern CSP_EPT_T *EPT0 ;
extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;
extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;
//ISR Define for generating special interrupt related ASM (CK802), with compile option -mistack
void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));
void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));
extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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Source/include/apt32f102_bt.h Normal file
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/*
******************************************************************************
* @file apt32f102_bt.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_bt_H
#define _apt32f102_bt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define BT_RESET_VALUE (0x00000000)
/**
* @brief bt pin numbner
*/
typedef enum
{
BT0_PA00 = 0, /*!< Pin 0 selected */
BT0_PA02 = 1, /*!< Pin 1 selected */
BT0_PA05 = 2, /*!< Pin 2 selected */
BT0_PB02 = 3, /*!< Pin 3 selected */
BT0_PB05 = 4, /*!< Pin 4 selected */
BT0_PA11 = 5, /*!< Pin 5 selected */
BT0_PA13 = 6, /*!< Pin 6 selected */
BT0_PA15 = 7, /*!< Pin 7 selected */
BT1_PA01 = 8, /*!< Pin 8 selected */
BT1_PA06 = 9, /*!< Pin 9 selected */
BT1_PA08 = 10, /*!< Pin 10 selected */
BT1_PA12 = 11, /*!< Pin 11 selected */
BT1_PA14 = 12, /*!< Pin 12 selected */
BT1_PB00 = 13, /*!< Pin 13 selected */
BT1_PB04 = 14, /*!< Pin 13 selected */
}BT_Pin_TypeDef;
/**
* @brief BT CLK EN register
*/
typedef enum
{
BTCLK_DIS = 0,
BTCLK_EN = 1,
}BT_CLK_TypeDef;
/**
* @brief BT START SHADOW register
*/
typedef enum
{
BT_SHADOW = (0<<3),
BT_IMMEDIATE= (1<<3),
}BT_SHDWSTP_TypeDef;
/**
* @brief BT OPM register
*/
typedef enum
{
BT_CONTINUOUS= (0<<4),
BT_ONCE= (1<<4),
}BT_OPM_TypeDef;
/**
* @brief BT EXTCKM register
*/
typedef enum
{
BT_PCLKDIV= (0<<5),
BT_EXTCKM= (1<<5),
}BT_EXTCKM_TypeDef;
/**
* @brief BT IDLEST register
*/
typedef enum
{
BT_IDLE_LOW= (0<<6),
BT_IDLE_HIGH= (1<<6),
}BT_IDLEST_TypeDef;
/**
* @brief BT STARTST register
*/
typedef enum
{
BT_START_LOW= (0<<7),
BT_START_HIGH= (1<<7),
}BT_STARTST_TypeDef;
/**
* @brief BT STARTST register
*/
typedef enum
{
BT_SYNC_DIS= (0<<8),
BT_SYNC_EN= (1<<8),
}BT_SYNCEN_TypeDef;
/**
* @brief BT OSTMDX register
*/
typedef enum
{
BT_OSTMDX_CONTINUOUS= (0<<10),
BT_OSTMDX_ONCE= (1<<10),
}BT_OSTMDX_TypeDef;
/**
* @brief BT AREARM register
*/
typedef enum
{
BT_AREARM_DIS= (0<<14),
BT_AREARM_EN= (1<<14),
}BT_AREARM_TypeDef;
/**
* @brief BT SYNCMD register
*/
typedef enum
{
BT_SYNCMD_DIS= (0<<15),
BT_SYNCMD_EN= (1<<15),
}BT_SYNCMD_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_CNTRLD_EN= (0<<16),
BT_CNTRLD_DIS= (1<<16),
}BT_CNTRLD_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_TRGSRC_DIS= (0<<0),
BT_TRGSRC_PEND= (1<<0),
BT_TRGSRC_CMP= (2<<0),
BT_TRGSRC_OVF= (3<<0),
}BT_TRGSRC_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_TRGOE_DIS= (0<<20),
BT_TRGOE_EN= (1<<20),
}BT_TRGOE_TypeDef;
/**
* @brief BT INT MASK SET/CLR Set
*/
typedef enum
{
BT_PEND = (0x01 << 0),
BT_CMP = (0x01 << 1),
BT_OVF = (0x01 << 2),
BT_EVTRG = (0x01 << 3),
}BT_IMSCR_TypeDef;
extern void BT_DeInit(CSP_BT_T *BTx);
extern void BT_IO_Init(BT_Pin_TypeDef BT_IONAME);
extern void BT_Start(CSP_BT_T *BTx);
extern void BT_Stop(CSP_BT_T *BTx);
extern void BT_Soft_Reset(CSP_BT_T *BTx);
extern void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM);
extern void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD,
BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD);
extern void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA);
extern void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA);
extern U16_T BT_PRDR_Read(CSP_BT_T *BTx);
extern U16_T BT_CMP_Read(CSP_BT_T *BTx);
extern U16_T BT_CNT_Read(CSP_BT_T *BTx);
extern void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE);
extern void BT_Soft_Tigger(CSP_BT_T *BTx);
extern void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X);
extern void BT0_INT_ENABLE(void);
extern void BT0_INT_DISABLE(void);
extern void BT1_INT_ENABLE(void);
extern void BT1_INT_DISABLE(void);
extern void BT_Stop_High(CSP_BT_T *BTx);
extern void BT_Stop_Low(CSP_BT_T *BTx);
#endif /**< apt32f102_bt_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ck801.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_ck801_H
#define _apt32f102_ck801_H
//----------------------------------------------------------------------------
// Interrupt Controller
//----------------------------------------------------------------------------
//#define CK801_BASEADDR ((unsigned int) 0xE000E000)
#define CK801_BASEADDR 0xE000E000
#define INTC_ISER CK801_BASEADDR+0x100 //INTC interrupt enable register
#define INTC_IWER CK801_BASEADDR+0x140 //INTC wake-up interrupt enable register
#define INTC_ICER CK801_BASEADDR+0x180 //INTC interrupt enable clear register
#define INTC_IWDR CK801_BASEADDR+0x1C0 //INTC wake-up interrupt enable clear register
#define INTC_ISPR CK801_BASEADDR+0x200 //INTC interrupt pending register
#define INTC_ICPR CK801_BASEADDR+0x280 //INTC interrupt pending clear register
#define INTC_IABR CK801_BASEADDR+0x300 //INTC interrupt acknowledge status register
#define INTC_IPR0 CK801_BASEADDR+0x400 //INTC interrupt priority register
#define INTC_IPR1 CK801_BASEADDR+0x404 //INTC interrupt priority register
#define INTC_IPR2 CK801_BASEADDR+0x408 //INTC interrupt priority register
#define INTC_IPR3 CK801_BASEADDR+0x40C //INTC interrupt priority register
#define INTC_IPR4 CK801_BASEADDR+0x410 //INTC interrupt priority register
#define INTC_IPR5 CK801_BASEADDR+0x414 //INTC interrupt priority register
#define INTC_IPR6 CK801_BASEADDR+0x418 //INTC interrupt priority register
#define INTC_IPR7 CK801_BASEADDR+0x41C //INTC interrupt priority register
#define INTC_ISR CK801_BASEADDR+0xC00 //INTC interrupt status register
#define INTC_IPTR CK801_BASEADDR+0xC04 //INTC interrupt pending threshold register
#define INTC_ISER_WRITE(val) *(volatile UINT32 *) (INTC_ISER ) = val
#define INTC_IWER_WRITE(val) *(volatile UINT32 *) (INTC_IWER ) = val
#define INTC_ICER_WRITE(val) *(volatile UINT32 *) (INTC_ICER ) = val
#define INTC_IWDR_WRITE(val) *(volatile UINT32 *) (INTC_IWDR ) = val
#define INTC_ISPR_WRITE(val) *(volatile UINT32 *) (INTC_ISPR ) = val
#define INTC_ICPR_WRITE(val) *(volatile UINT32 *) (INTC_ICPR ) = val
#define INTC_IABR_WRITE(val) *(volatile UINT32 *) (INTC_IABR ) = val
#define INTC_IPR0_WRITE(val) *(volatile UINT32 *) (INTC_IPR0 ) = val
#define INTC_IPR1_WRITE(val) *(volatile UINT32 *) (INTC_IPR1 ) = val
#define INTC_IPR2_WRITE(val) *(volatile UINT32 *) (INTC_IPR2 ) = val
#define INTC_IPR3_WRITE(val) *(volatile UINT32 *) (INTC_IPR3 ) = val
#define INTC_IPR4_WRITE(val) *(volatile UINT32 *) (INTC_IPR4 ) = val
#define INTC_IPR5_WRITE(val) *(volatile UINT32 *) (INTC_IPR5 ) = val
#define INTC_IPR6_WRITE(val) *(volatile UINT32 *) (INTC_IPR6 ) = val
#define INTC_IPR7_WRITE(val) *(volatile UINT32 *) (INTC_IPR7 ) = val
#define INTC_ISR_WRITE(val) *(volatile UINT32 *) (INTC_ISR ) = val
#define INTC_IPTR_WRITE(val) *(volatile UINT32 *) (INTC_IPTR ) = val
#define INTC_ISER_READ(intc) (intc->ISER )
#define INTC_IWER_READ(intc) (intc->IWER )
#define INTC_ICER_READ(intc) (intc->ICER )
#define INTC_IWDR_READ(intc) (intc->IWDR )
#define INTC_ISPR_READ(intc) (intc->ISPR )
#define INTC_ICPR_READ(intc) (intc->ICPR )
#define INTC_IABR_READ(intc) (intc->IABR )
#define INTC_IPR0_READ(intc) (intc->IPR0 )
#define INTC_IPR1_READ(intc) (intc->IPR1 )
#define INTC_IPR2_READ(intc) (intc->IPR2 )
#define INTC_IPR3_READ(intc) (intc->IPR3 )
#define INTC_IPR4_READ(intc) (intc->IPR4 )
#define INTC_IPR5_READ(intc) (intc->IPR5 )
#define INTC_IPR6_READ(intc) (intc->IPR6 )
#define INTC_IPR7_READ(intc) (intc->IPR7 )
#define INTC_ISR_READ(intc) (intc->ISR )
#define INTC_IPTR_READ(intc) (intc->IPTR )
typedef enum IRQn
{
ISR_Restart = -32,
ISR_Misaligned_Access = -31,
ISR_Access_Error = -30,
ISR_Divided_By_Zero = -29,
ISR_Illegal = -28,
ISR_Privlege_Violation = -27,
ISR_Trace_Exection = -26,
ISR_Breakpoint_Exception = -25,
ISR_Unrecoverable_Error = -24,
ISR_Idly4_Error = -23,
ISR_Auto_INT = -22,
ISR_Auto_FINT = -21,
ISR_Reserved_HAI = -20,
ISR_Reserved_FP = -19,
ISR_TLB_Ins_Empty = -18,
ISR_TLB_Data_Empty = -17,
INTC_CORETIM_IRQn = 0,
INTC_TIME1_IRQn = 1,
INTC_UART0_IRQn = 2,
INTC_GPIOA2_IRQn = 8,
} IRQn_Type;
void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);
void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef uint32_t
#define uint32_t unsigned int
#endif
#ifndef uint8_t
#define uint8_t unsigned char
#endif
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/******************************************************************************
* @file apt32f102_clkcalib.h
* @author APT AE Team
* @version V1.22
* @date 2021/11/22
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#include "apt32f102.h"
/**
* @brief CALIB OSC SELECTE SET
*/
typedef enum
{
CLK_HFOSC_48M = (0x0ul),
CLK_HFOSC_24M = (0x1ul),
CLK_HFOSC_12M = (0x2ul),
CLK_HFOSC_6M = (0x3ul),
CLK_IMOSC_5556K = (0x4ul),
CLK_IMOSC_4194K = (0x5ul),
CLK_IMOSC_2097K = (0x6ul),
CLK_IMOSC_131K = (0x7ul)
}CALIB_OSC_SELECTE_TypeDef;
extern U8_T std_clk_calib(CALIB_OSC_SELECTE_TypeDef OSC_CALIB_X);

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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_gpio_H
#define _apt32f102_gpio_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define GPIO_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------GPIO value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief GPIO pin numbner
*/
typedef enum
{
PIN_0 = 0, /*!< Pin 0 selected */
PIN_1 = 4, /*!< Pin 1 selected */
PIN_2 = 8, /*!< Pin 2 selected */
PIN_3 = 12, /*!< Pin 3 selected */
PIN_4 = 16, /*!< Pin 4 selected */
PIN_5 = 20, /*!< Pin 5 selected */
PIN_6 = 24, /*!< Pin 6 selected */
PIN_7 = 28, /*!< Pin 7 selected */
PIN_8 = 0, /*!< Pin 8 selected */
PIN_9 = 4, /*!< Pin 9 selected */
PIN_10 = 8, /*!< Pin 10 selected */
PIN_11 = 12, /*!< Pin 11 selected */
PIN_12 = 16, /*!< Pin 12 selected */
PIN_13 = 20, /*!< Pin 13 selected */
PIN_14 = 24, /*!< Pin 13 selected */
PIN_15 = 28, /*!< Pin 13 selected */
}GPIO_Pin_TypeDef;
/**
* @brief GPIO high/low register
*/
typedef enum
{
LowByte = 0,
HighByte = 1,
}GPIO_byte_TypeDef;
/**
* @brief GPIO IO status
*/
typedef enum
{
Intput = 1,
Output = 0,
}GPIO_Dir_TypeDef;
/**
* @brief GPIO IO mode
*/
typedef enum
{
PUDR = 0, //pull high or low
DSCR =1, //drive strenth
OMCR =2, //open drain
IECR =3, //int
}GPIO_Mode_TypeDef;
/**
* @brief GPIO IO Group
*/
typedef enum
{
PA0 = 0,
PB0 = 2,
GPIOA = 0,
GPIOB = 2,
}GPIO_Group_TypeDef;
/**
* @brief GPIO exi number
*/
typedef enum
{
EXI0 = 0,
EXI1 = 1,
EXI2 = 2,
EXI3 = 3,
EXI4 = 4,
EXI5 = 5,
EXI6 = 6,
EXI7 = 7,
EXI8 = 8,
EXI9 = 9,
EXI10 = 10,
EXI11 = 11,
EXI12 = 12,
EXI13 = 13,
EXI14 = 14,
EXI15 = 15,
}GPIO_EXI_TypeDef;
/**
* @brief EXI PIN
*/
typedef enum
{
Selete_EXI_PIN0 = (CSP_REGISTER_T)(0),
Selete_EXI_PIN1 = (CSP_REGISTER_T)(1),
Selete_EXI_PIN2 = (CSP_REGISTER_T)(2),
Selete_EXI_PIN3 = (CSP_REGISTER_T)(3),
Selete_EXI_PIN4 = (CSP_REGISTER_T)(4),
Selete_EXI_PIN5 = (CSP_REGISTER_T)(5),
Selete_EXI_PIN6 = (CSP_REGISTER_T)(6),
Selete_EXI_PIN7 = (CSP_REGISTER_T)(7),
Selete_EXI_PIN8 = (CSP_REGISTER_T)(8),
Selete_EXI_PIN9 = (CSP_REGISTER_T)(9),
Selete_EXI_PIN10 = (CSP_REGISTER_T)(10),
Selete_EXI_PIN11 = (CSP_REGISTER_T)(11),
Selete_EXI_PIN12 = (CSP_REGISTER_T)(12),
Selete_EXI_PIN13 = (CSP_REGISTER_T)(13),
Selete_EXI_PIN14 = (CSP_REGISTER_T)(14),
Selete_EXI_PIN15 = (CSP_REGISTER_T)(15),
Selete_EXI_PIN16 = (CSP_REGISTER_T)(16),
Selete_EXI_PIN17 = (CSP_REGISTER_T)(17),
Selete_EXI_PIN18 = (CSP_REGISTER_T)(18),
Selete_EXI_PIN19 = (CSP_REGISTER_T)(19)
}GPIO_EXIPIN_TypeDef;
/**
* @brief GPIO INPUT MODE SETECTED
*/
typedef enum
{
INPUT_MODE_SETECTED_CMOS = 0,
INPUT_MODE_SETECTED_TTL1 = 1,
INPUT_MODE_SETECTED_TTL2 = 2
}INPUT_MODE_SETECTED_TypeDef;
#define nop asm ("nop")
#define SetPA0(n) (GPIOA0->SODR = (1ul<<n))
#define ClrPA0(n) (GPIOA0->CODR = (1ul<<n))
#define SetPB0(n) (GPIOB0->SODR = (1ul<<n))
#define ClrPB0(n) (GPIOB0->CODR = (1ul<<n))
#define PA0in(n) (((GPIOA0->PSDR)>>n) & 1ul)
#define PB0in(n) (((GPIOB0->PSDR)>>n) & 1ul)
#define CSP_GPIO_SET_CONLR(cm,val) ((cm)->CONLR = val)
#define CSP_GPIO_GET_CONLR(cm) ((cm)->CONLR)
#define CSP_GPIO_SET_CONHR(cm,val) ((cm)->CONHR = val)
#define CSP_GPIO_GET_CONHR(cm) ((cm)->CONHR)
#define CSP_GPIO_SET_WODR(cm,val) ((cm)->WODR = val)
#define CSP_GPIO_SET_SODR(cm,val) ((cm)->SODR = val)
#define CSP_GPIO_SET_CODR(cm,val) ((cm)->CODR = val)
#define CSP_GPIO_GET_PSDR(cm) ((cm)->PSDR)
#define CSP_GPIO_SET_PUDR(cm,val) ((cm)->PUDR = val)
#define CSP_GPIO_GET_PUDR(cm) ((cm)->PUDR)
#define CSP_GPIO_SET_DSCR(cm,val) ((cm)->DSCR = val)
#define CSP_GPIO_GET_DSCR(cm) ((cm)->DSCR)
#define CSP_GPIO_SET_OMCR(cm,val) ((cm)->OMCR = val)
#define CSP_GPIO_GET_OMCR(cm) ((cm)->OMCR)
#define CSP_GPIO_SET_IECR(cm,val) ((cm)->IECR = val)
#define CSP_GPIO_GET_IECR(cm) ((cm)->IECR)
#define CSP_GPIO_SET_IGRP(cm,val) ((cm)->IGRP = val)
#define CSP_GPIO_GET_IGRP(cm) ((cm)->IGRP)
/******************************************************************************
************************** Exported functions ************************
******************************************************************************/
extern void GPIOA0_DeInit(GPIO_Pin_TypeDef GPIO_Pin);
extern void GPIO_DeInit(void);
extern void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X);
extern void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val);
extern void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum);
extern void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir);
extern void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val);
extern uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit);
extern uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval);
extern void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_Debug_IO_12_13(void);
extern void GPIO_Debug_IO_01_02(void);
extern void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef EXIPIN_x);
extern void GPIOA00_Set_ResetPin();
extern void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
/*************************************************************/
#endif /**< apt32f102_gpio_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_hwdiv.h
* @author APT AE Team
* @version V1.02
* @date 2019/04/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_hwdiv_H
#define _apt32f102_hwdiv_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define HWDIV_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------HWDIV value enum define--------------------------
//--------------------------------------------------------------------------------
#define HWDIV_UNSIGN_BIT (0X01<<0)
extern U32_T HWDIV_Calc_Remain(void);
extern U32_T HWDIV_Calc_Quotient(void);
extern void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x);
extern void HWDIV_UNSIGN_CMD(FunctionalStatus NewState);
extern void HWDIV_DeInit(void);
extern void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x);
extern void HWDIV_Calc_float(float DIVIDENDx,float DIVISOR_x);
#endif /**< apt32f102_hwdiv_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ifc.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_ifc_H
#define _apt32f102_ifc_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************ ifc Registers Definition *************************
******************************************************************************/
#define IFC_CLK_EN (0x01ul)
#define IFC_CLK_DIS (0xfeul)
#define EnIFCClk (IFC->CEDR = (IFC_CLK_EN))
#define DisIFCClk (IFC->CEDR = (IFC_CLK_DIS))
#define USER_KEY (0x5A5A5A5Aul)
#define SetUserKey (IFC->KR = (USER_KEY))
#define StartOp (0x01ul)
#define IFC_CLKEN (0x01ul) //IFC CLKEN
#define IFC_SWRST (0x01ul) //IFC SWRST
#define HIDM0 ((0x0ul)<<8) //HID0
#define HIDM1 ((0x1ul)<<8) //HID1
#define HIDM2 ((0x2ul)<<8) //HID2
#define HIDM3 ((0x3ul)<<8) //HID3
// IFC Command
#define PROGRAM (0x01ul)
#define PAGE_ERASE (0x02ul)
#define CHIP_ERASE (0x04ul)
#define OPTION_ERASE (0x05ul)
#define PEP_ENABLE (0x06ul) //预编程设定
#define PAGE_BUF_CLR (0x07ul) //页缓存清除
#define DIS_SWD_SET (0x0Dul) //SWD 禁止重映射
#define EN_SWD_SET (0x0Eul) //SWD 使能重映射
#define USER_OPTION (0x0Ful) //User OPTION操作
#define USER_KEY (0x5A5A5A5Aul)
#define CSP_IFC_SET_KR(ifc, val) (ifc->KR = (val))
//
#define StartErase (IFC->CR=(StartOp))
#define EnChipErase (IFC->CMR=(CHIP_ERASE|HIDM1))
#define EnPageErase (IFC->CMR=(PAGE_ERASE|HIDM0))
/**
* @brief IFC page address
*/
typedef enum
{
PROM_PageAdd0 = ((CSP_REGISTER_T)0x00000000), //PROM 每页256BYTE
PROM_PageAdd1 = ((CSP_REGISTER_T)0x00000100),
PROM_PageAdd2 = ((CSP_REGISTER_T)0x00000200),
PROM_PageAdd3 = ((CSP_REGISTER_T)0x00000300),
PROM_PageAdd4 = ((CSP_REGISTER_T)0x00000400),
PROM_PageAdd5 = ((CSP_REGISTER_T)0x00000500),
PROM_PageAdd6 = ((CSP_REGISTER_T)0x00000600),
PROM_PageAdd7 = ((CSP_REGISTER_T)0x00000700),
PROM_PageAdd8 = ((CSP_REGISTER_T)0x00000800),
PROM_PageAdd9 = ((CSP_REGISTER_T)0x00000900),
PROM_PageAdd10 = ((CSP_REGISTER_T)0x00000A00),
PROM_PageAdd11 = ((CSP_REGISTER_T)0x00000B00),
PROM_PageAdd12 = ((CSP_REGISTER_T)0x00000C00),
PROM_PageAdd13 = ((CSP_REGISTER_T)0x00000D00),
PROM_PageAdd14 = ((CSP_REGISTER_T)0x00000E00),
PROM_PageAdd15 = ((CSP_REGISTER_T)0x00000F00),
PROM_PageAdd16 = ((CSP_REGISTER_T)0x00001000),
PROM_PageAdd17 = ((CSP_REGISTER_T)0x00001100),
PROM_PageAdd18 = ((CSP_REGISTER_T)0x00001200),
PROM_PageAdd19 = ((CSP_REGISTER_T)0x00001300),
PROM_PageAdd20 = ((CSP_REGISTER_T)0x00001400),
PROM_PageAdd21 = ((CSP_REGISTER_T)0x00001500),
PROM_PageAdd22 = ((CSP_REGISTER_T)0x00001600),
PROM_PageAdd23 = ((CSP_REGISTER_T)0x00001700),
PROM_PageAdd24 = ((CSP_REGISTER_T)0x00001800),
PROM_PageAdd25 = ((CSP_REGISTER_T)0x00001900),
PROM_PageAdd26 = ((CSP_REGISTER_T)0x00001A00),
PROM_PageAdd27 = ((CSP_REGISTER_T)0x00001B00),
PROM_PageAdd28 = ((CSP_REGISTER_T)0x00001C00),
PROM_PageAdd29 = ((CSP_REGISTER_T)0x00001D00),
PROM_PageAdd30 = ((CSP_REGISTER_T)0x00001E00),
PROM_PageAdd31 = ((CSP_REGISTER_T)0x00001F00),
PROM_PageAdd32 = ((CSP_REGISTER_T)0x00002000),
PROM_PageAdd33 = ((CSP_REGISTER_T)0x00002100),
PROM_PageAdd34 = ((CSP_REGISTER_T)0x00002200),
PROM_PageAdd35 = ((CSP_REGISTER_T)0x00002300),
PROM_PageAdd36 = ((CSP_REGISTER_T)0x00002400),
PROM_PageAdd37 = ((CSP_REGISTER_T)0x00002500),
PROM_PageAdd38 = ((CSP_REGISTER_T)0x00002600),
PROM_PageAdd39 = ((CSP_REGISTER_T)0x00002700),
PROM_PageAdd40 = ((CSP_REGISTER_T)0x00002800),
PROM_PageAdd41 = ((CSP_REGISTER_T)0x00002900),
PROM_PageAdd42 = ((CSP_REGISTER_T)0x00002A00),
PROM_PageAdd43 = ((CSP_REGISTER_T)0x00002B00),
PROM_PageAdd44 = ((CSP_REGISTER_T)0x00002C00),
PROM_PageAdd45 = ((CSP_REGISTER_T)0x00002D00),
PROM_PageAdd46 = ((CSP_REGISTER_T)0x00002E00),
PROM_PageAdd47 = ((CSP_REGISTER_T)0x00002F00),
PROM_PageAdd48 = ((CSP_REGISTER_T)0x00003000),
PROM_PageAdd49 = ((CSP_REGISTER_T)0x00003100),
PROM_PageAdd50 = ((CSP_REGISTER_T)0x00003200),
PROM_PageAdd51 = ((CSP_REGISTER_T)0x00003300),
PROM_PageAdd52 = ((CSP_REGISTER_T)0x00003400),
PROM_PageAdd53 = ((CSP_REGISTER_T)0x00003500),
PROM_PageAdd54 = ((CSP_REGISTER_T)0x00003600),
PROM_PageAdd55 = ((CSP_REGISTER_T)0x00003700),
PROM_PageAdd56 = ((CSP_REGISTER_T)0x00003800),
PROM_PageAdd57 = ((CSP_REGISTER_T)0x00003900),
PROM_PageAdd58 = ((CSP_REGISTER_T)0x00003A00),
PROM_PageAdd59 = ((CSP_REGISTER_T)0x00003B00),
PROM_PageAdd60 = ((CSP_REGISTER_T)0x00003C00),
PROM_PageAdd61 = ((CSP_REGISTER_T)0x00003D00),
PROM_PageAdd62 = ((CSP_REGISTER_T)0x00003E00),
PROM_PageAdd63 = ((CSP_REGISTER_T)0x00003F00),
PROM_PageAdd64 = ((CSP_REGISTER_T)0x00004000),
PROM_PageAdd65 = ((CSP_REGISTER_T)0x00004100),
PROM_PageAdd66 = ((CSP_REGISTER_T)0x00004200),
PROM_PageAdd67 = ((CSP_REGISTER_T)0x00004300),
PROM_PageAdd68 = ((CSP_REGISTER_T)0x00004400),
PROM_PageAdd69 = ((CSP_REGISTER_T)0x00004500),
PROM_PageAdd70 = ((CSP_REGISTER_T)0x00004600),
PROM_PageAdd71 = ((CSP_REGISTER_T)0x00004700),
PROM_PageAdd72 = ((CSP_REGISTER_T)0x00004800),
PROM_PageAdd73 = ((CSP_REGISTER_T)0x00004900),
PROM_PageAdd74 = ((CSP_REGISTER_T)0x00004A00),
PROM_PageAdd75 = ((CSP_REGISTER_T)0x00004B00),
PROM_PageAdd76 = ((CSP_REGISTER_T)0x00004C00),
PROM_PageAdd77 = ((CSP_REGISTER_T)0x00004D00),
PROM_PageAdd78 = ((CSP_REGISTER_T)0x00004E00),
PROM_PageAdd79 = ((CSP_REGISTER_T)0x00004F00),
PROM_PageAdd80 = ((CSP_REGISTER_T)0x00005000),
PROM_PageAdd81 = ((CSP_REGISTER_T)0x00005100),
PROM_PageAdd82 = ((CSP_REGISTER_T)0x00005200),
PROM_PageAdd83 = ((CSP_REGISTER_T)0x00005300),
PROM_PageAdd84 = ((CSP_REGISTER_T)0x00005400),
PROM_PageAdd85 = ((CSP_REGISTER_T)0x00005500),
PROM_PageAdd86 = ((CSP_REGISTER_T)0x00005600),
PROM_PageAdd87 = ((CSP_REGISTER_T)0x00005700),
PROM_PageAdd88 = ((CSP_REGISTER_T)0x00005800),
PROM_PageAdd89 = ((CSP_REGISTER_T)0x00005900),
PROM_PageAdd90 = ((CSP_REGISTER_T)0x00005A00),
PROM_PageAdd91 = ((CSP_REGISTER_T)0x00005B00),
PROM_PageAdd92 = ((CSP_REGISTER_T)0x00005C00),
PROM_PageAdd93 = ((CSP_REGISTER_T)0x00005D00),
PROM_PageAdd94 = ((CSP_REGISTER_T)0x00005E00),
PROM_PageAdd95 = ((CSP_REGISTER_T)0x00005F00),
PROM_PageAdd96 = ((CSP_REGISTER_T)0x00006000),
PROM_PageAdd97 = ((CSP_REGISTER_T)0x00006100),
PROM_PageAdd98 = ((CSP_REGISTER_T)0x00006200),
PROM_PageAdd99 = ((CSP_REGISTER_T)0x00006300),
PROM_PageAdd100 = ((CSP_REGISTER_T)0x00006400),
PROM_PageAdd101 = ((CSP_REGISTER_T)0x00006500),
PROM_PageAdd102 = ((CSP_REGISTER_T)0x00006600),
PROM_PageAdd103 = ((CSP_REGISTER_T)0x00006700),
PROM_PageAdd104 = ((CSP_REGISTER_T)0x00006800),
PROM_PageAdd105 = ((CSP_REGISTER_T)0x00006900),
PROM_PageAdd106 = ((CSP_REGISTER_T)0x00006A00),
PROM_PageAdd107 = ((CSP_REGISTER_T)0x00006B00),
PROM_PageAdd108 = ((CSP_REGISTER_T)0x00006C00),
PROM_PageAdd109 = ((CSP_REGISTER_T)0x00006D00),
PROM_PageAdd110 = ((CSP_REGISTER_T)0x00006E00),
PROM_PageAdd111 = ((CSP_REGISTER_T)0x00006F00),
PROM_PageAdd112 = ((CSP_REGISTER_T)0x00007000),
PROM_PageAdd113 = ((CSP_REGISTER_T)0x00007100),
PROM_PageAdd114 = ((CSP_REGISTER_T)0x00007200),
PROM_PageAdd115 = ((CSP_REGISTER_T)0x00007300),
PROM_PageAdd116 = ((CSP_REGISTER_T)0x00007400),
PROM_PageAdd117 = ((CSP_REGISTER_T)0x00007500),
PROM_PageAdd118 = ((CSP_REGISTER_T)0x00007600),
PROM_PageAdd119 = ((CSP_REGISTER_T)0x00007700),
PROM_PageAdd120 = ((CSP_REGISTER_T)0x00007800),
PROM_PageAdd121 = ((CSP_REGISTER_T)0x00007900),
PROM_PageAdd122 = ((CSP_REGISTER_T)0x00007A00),
PROM_PageAdd123 = ((CSP_REGISTER_T)0x00007B00),
PROM_PageAdd124 = ((CSP_REGISTER_T)0x00007C00),
PROM_PageAdd125 = ((CSP_REGISTER_T)0x00007D00),
PROM_PageAdd126 = ((CSP_REGISTER_T)0x00007E00),
PROM_PageAdd127 = ((CSP_REGISTER_T)0x00007F00),
PROM_PageAdd128 = ((CSP_REGISTER_T)0x00008000),
PROM_PageAdd129 = ((CSP_REGISTER_T)0x00008100),
PROM_PageAdd130 = ((CSP_REGISTER_T)0x00008200),
PROM_PageAdd131 = ((CSP_REGISTER_T)0x00008300),
PROM_PageAdd132 = ((CSP_REGISTER_T)0x00008400),
PROM_PageAdd133 = ((CSP_REGISTER_T)0x00008500),
PROM_PageAdd134 = ((CSP_REGISTER_T)0x00008600),
PROM_PageAdd135 = ((CSP_REGISTER_T)0x00008700),
PROM_PageAdd136 = ((CSP_REGISTER_T)0x00008800),
PROM_PageAdd137 = ((CSP_REGISTER_T)0x00008900),
PROM_PageAdd138 = ((CSP_REGISTER_T)0x00008A00),
PROM_PageAdd139 = ((CSP_REGISTER_T)0x00008B00),
PROM_PageAdd140 = ((CSP_REGISTER_T)0x00008C00),
PROM_PageAdd141 = ((CSP_REGISTER_T)0x00008D00),
PROM_PageAdd142 = ((CSP_REGISTER_T)0x00008E00),
PROM_PageAdd143 = ((CSP_REGISTER_T)0x00008F00),
PROM_PageAdd144 = ((CSP_REGISTER_T)0x00009000),
PROM_PageAdd145 = ((CSP_REGISTER_T)0x00009100),
PROM_PageAdd146 = ((CSP_REGISTER_T)0x00009200),
PROM_PageAdd147 = ((CSP_REGISTER_T)0x00009300),
PROM_PageAdd148 = ((CSP_REGISTER_T)0x00009400),
PROM_PageAdd149 = ((CSP_REGISTER_T)0x00009500),
PROM_PageAdd150 = ((CSP_REGISTER_T)0x00009600),
PROM_PageAdd151 = ((CSP_REGISTER_T)0x00009700),
PROM_PageAdd152 = ((CSP_REGISTER_T)0x00009800),
PROM_PageAdd153 = ((CSP_REGISTER_T)0x00009900),
PROM_PageAdd154 = ((CSP_REGISTER_T)0x00009A00),
PROM_PageAdd155 = ((CSP_REGISTER_T)0x00009B00),
PROM_PageAdd156 = ((CSP_REGISTER_T)0x00009C00),
PROM_PageAdd157 = ((CSP_REGISTER_T)0x00009D00),
PROM_PageAdd158 = ((CSP_REGISTER_T)0x00009E00),
PROM_PageAdd159 = ((CSP_REGISTER_T)0x00009F00),
PROM_PageAdd160 = ((CSP_REGISTER_T)0x0000A000),
PROM_PageAdd161 = ((CSP_REGISTER_T)0x0000A100),
PROM_PageAdd162 = ((CSP_REGISTER_T)0x0000A200),
PROM_PageAdd163 = ((CSP_REGISTER_T)0x0000A300),
PROM_PageAdd164 = ((CSP_REGISTER_T)0x0000A400),
PROM_PageAdd165 = ((CSP_REGISTER_T)0x0000A500),
PROM_PageAdd166 = ((CSP_REGISTER_T)0x0000A600),
PROM_PageAdd167 = ((CSP_REGISTER_T)0x0000A700),
PROM_PageAdd168 = ((CSP_REGISTER_T)0x0000A800),
PROM_PageAdd169 = ((CSP_REGISTER_T)0x0000A900),
PROM_PageAdd170 = ((CSP_REGISTER_T)0x0000AA00),
PROM_PageAdd171 = ((CSP_REGISTER_T)0x0000AB00),
PROM_PageAdd172 = ((CSP_REGISTER_T)0x0000AC00),
PROM_PageAdd173 = ((CSP_REGISTER_T)0x0000AD00),
PROM_PageAdd174 = ((CSP_REGISTER_T)0x0000AE00),
PROM_PageAdd175 = ((CSP_REGISTER_T)0x0000AF00),
PROM_PageAdd176 = ((CSP_REGISTER_T)0x0000B000),
PROM_PageAdd177 = ((CSP_REGISTER_T)0x0000B100),
PROM_PageAdd178 = ((CSP_REGISTER_T)0x0000B200),
PROM_PageAdd179 = ((CSP_REGISTER_T)0x0000B300),
PROM_PageAdd180 = ((CSP_REGISTER_T)0x0000B400),
PROM_PageAdd181 = ((CSP_REGISTER_T)0x0000B500),
PROM_PageAdd182 = ((CSP_REGISTER_T)0x0000B600),
PROM_PageAdd183 = ((CSP_REGISTER_T)0x0000B700),
PROM_PageAdd184 = ((CSP_REGISTER_T)0x0000B800),
PROM_PageAdd185 = ((CSP_REGISTER_T)0x0000B900),
PROM_PageAdd186 = ((CSP_REGISTER_T)0x0000BA00),
PROM_PageAdd187 = ((CSP_REGISTER_T)0x0000BB00),
PROM_PageAdd188 = ((CSP_REGISTER_T)0x0000BC00),
PROM_PageAdd189 = ((CSP_REGISTER_T)0x0000BD00),
PROM_PageAdd190 = ((CSP_REGISTER_T)0x0000BE00),
PROM_PageAdd191 = ((CSP_REGISTER_T)0x0000BF00),
PROM_PageAdd192 = ((CSP_REGISTER_T)0x0000C000),
PROM_PageAdd193 = ((CSP_REGISTER_T)0x0000C100),
PROM_PageAdd194 = ((CSP_REGISTER_T)0x0000C200),
PROM_PageAdd195 = ((CSP_REGISTER_T)0x0000C300),
PROM_PageAdd196 = ((CSP_REGISTER_T)0x0000C400),
PROM_PageAdd197 = ((CSP_REGISTER_T)0x0000C500),
PROM_PageAdd198 = ((CSP_REGISTER_T)0x0000C600),
PROM_PageAdd199 = ((CSP_REGISTER_T)0x0000C700),
PROM_PageAdd200 = ((CSP_REGISTER_T)0x0000C800),
PROM_PageAdd201 = ((CSP_REGISTER_T)0x0000C900),
PROM_PageAdd202 = ((CSP_REGISTER_T)0x0000CA00),
PROM_PageAdd203 = ((CSP_REGISTER_T)0x0000CB00),
PROM_PageAdd204 = ((CSP_REGISTER_T)0x0000CC00),
PROM_PageAdd205 = ((CSP_REGISTER_T)0x0000CD00),
PROM_PageAdd206 = ((CSP_REGISTER_T)0x0000CE00),
PROM_PageAdd207 = ((CSP_REGISTER_T)0x0000CF00),
PROM_PageAdd208 = ((CSP_REGISTER_T)0x0000D000),
PROM_PageAdd209 = ((CSP_REGISTER_T)0x0000D100),
PROM_PageAdd210 = ((CSP_REGISTER_T)0x0000D200),
PROM_PageAdd211 = ((CSP_REGISTER_T)0x0000D300),
PROM_PageAdd212 = ((CSP_REGISTER_T)0x0000D400),
PROM_PageAdd213 = ((CSP_REGISTER_T)0x0000D500),
PROM_PageAdd214 = ((CSP_REGISTER_T)0x0000D600),
PROM_PageAdd215 = ((CSP_REGISTER_T)0x0000D700),
PROM_PageAdd216 = ((CSP_REGISTER_T)0x0000D800),
PROM_PageAdd217 = ((CSP_REGISTER_T)0x0000D900),
PROM_PageAdd218 = ((CSP_REGISTER_T)0x0000DA00),
PROM_PageAdd219 = ((CSP_REGISTER_T)0x0000DB00),
PROM_PageAdd220 = ((CSP_REGISTER_T)0x0000DC00),
PROM_PageAdd221 = ((CSP_REGISTER_T)0x0000DD00),
PROM_PageAdd222 = ((CSP_REGISTER_T)0x0000DE00),
PROM_PageAdd223 = ((CSP_REGISTER_T)0x0000DF00),
PROM_PageAdd224 = ((CSP_REGISTER_T)0x0000E000),
PROM_PageAdd225 = ((CSP_REGISTER_T)0x0000E100),
PROM_PageAdd226 = ((CSP_REGISTER_T)0x0000E200),
PROM_PageAdd227 = ((CSP_REGISTER_T)0x0000E300),
PROM_PageAdd228 = ((CSP_REGISTER_T)0x0000E400),
PROM_PageAdd229 = ((CSP_REGISTER_T)0x0000E500),
PROM_PageAdd230 = ((CSP_REGISTER_T)0x0000E600),
PROM_PageAdd231 = ((CSP_REGISTER_T)0x0000E700),
PROM_PageAdd232 = ((CSP_REGISTER_T)0x0000E800),
PROM_PageAdd233 = ((CSP_REGISTER_T)0x0000E900),
PROM_PageAdd234 = ((CSP_REGISTER_T)0x0000EA00),
PROM_PageAdd235 = ((CSP_REGISTER_T)0x0000EB00),
PROM_PageAdd236 = ((CSP_REGISTER_T)0x0000EC00),
PROM_PageAdd237 = ((CSP_REGISTER_T)0x0000ED00),
PROM_PageAdd238 = ((CSP_REGISTER_T)0x0000EE00),
PROM_PageAdd239 = ((CSP_REGISTER_T)0x0000EF00),
PROM_PageAdd240 = ((CSP_REGISTER_T)0x0000F000),
PROM_PageAdd241 = ((CSP_REGISTER_T)0x0000F100),
PROM_PageAdd242 = ((CSP_REGISTER_T)0x0000F200),
PROM_PageAdd243 = ((CSP_REGISTER_T)0x0000F300),
PROM_PageAdd244 = ((CSP_REGISTER_T)0x0000F400),
PROM_PageAdd245 = ((CSP_REGISTER_T)0x0000F50),
PROM_PageAdd246 = ((CSP_REGISTER_T)0x0000F600),
PROM_PageAdd247 = ((CSP_REGISTER_T)0x0000F700),
PROM_PageAdd248 = ((CSP_REGISTER_T)0x0000F800),
PROM_PageAdd249 = ((CSP_REGISTER_T)0x0000F900),
PROM_PageAdd250 = ((CSP_REGISTER_T)0x0000FA00),
PROM_PageAdd251 = ((CSP_REGISTER_T)0x0000FB00),
PROM_PageAdd252 = ((CSP_REGISTER_T)0x0000FC00),
PROM_PageAdd253 = ((CSP_REGISTER_T)0x0000FD00),
PROM_PageAdd254 = ((CSP_REGISTER_T)0x0000FE00),
PROM_PageAdd255 = ((CSP_REGISTER_T)0x0000FF00),
DROM_PageAdd0 = ((CSP_REGISTER_T)0x10000000), //DROM 每页64BYTE
DROM_PageAdd1 = ((CSP_REGISTER_T)0x10000040),
DROM_PageAdd2 = ((CSP_REGISTER_T)0x10000080),
DROM_PageAdd3 = ((CSP_REGISTER_T)0x100000C0),
DROM_PageAdd4 = ((CSP_REGISTER_T)0x10000100),
DROM_PageAdd5 = ((CSP_REGISTER_T)0x10000140),
DROM_PageAdd6 = ((CSP_REGISTER_T)0x10000180),
DROM_PageAdd7 = ((CSP_REGISTER_T)0x100001C0),
DROM_PageAdd8 = ((CSP_REGISTER_T)0x10000200),
DROM_PageAdd9 = ((CSP_REGISTER_T)0x10000240),
DROM_PageAdd10 = ((CSP_REGISTER_T)0x10000280),
DROM_PageAdd11 = ((CSP_REGISTER_T)0x100002C0),
DROM_PageAdd12 = ((CSP_REGISTER_T)0x10000300),
DROM_PageAdd13 = ((CSP_REGISTER_T)0x10000340),
DROM_PageAdd14 = ((CSP_REGISTER_T)0x10000380),
DROM_PageAdd15 = ((CSP_REGISTER_T)0x100003C0),
DROM_PageAdd16 = ((CSP_REGISTER_T)0x10000400),
DROM_PageAdd17 = ((CSP_REGISTER_T)0x10000440),
DROM_PageAdd18 = ((CSP_REGISTER_T)0x10000480),
DROM_PageAdd19 = ((CSP_REGISTER_T)0x100004C0),
DROM_PageAdd20 = ((CSP_REGISTER_T)0x10000500),
DROM_PageAdd21 = ((CSP_REGISTER_T)0x10000540),
DROM_PageAdd22 = ((CSP_REGISTER_T)0x10000580),
DROM_PageAdd23 = ((CSP_REGISTER_T)0x100005C0),
DROM_PageAdd24 = ((CSP_REGISTER_T)0x10000600),
DROM_PageAdd25 = ((CSP_REGISTER_T)0x10000640),
DROM_PageAdd26 = ((CSP_REGISTER_T)0x10000680),
DROM_PageAdd27 = ((CSP_REGISTER_T)0x100006C0),
DROM_PageAdd28 = ((CSP_REGISTER_T)0x10000700),
DROM_PageAdd29 = ((CSP_REGISTER_T)0x10000740),
DROM_PageAdd30 = ((CSP_REGISTER_T)0x10000780),
DROM_PageAdd31 = ((CSP_REGISTER_T)0x100007C0)
}IFC_ROMSELETED_TypeDef;
/**
* @brief IFC INT mode
*/
typedef enum
{
ERS_END_INT = (0x01ul),
RGM_END_INT = ((0x01ul)<<1),
PEP_END_INT = ((0x01ul)<<2),
PROT_ERR_INT = ((0x01ul)<<12),
UDEF_ERR_INT = ((0x01ul)<<13),
ADDR_ERR_INT = ((0x01ul)<<14),
OVW_ERR_INT = ((0x01ul)<<15)
}IFC_INT_TypeDef;
extern void ChipErase(void);
extern void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAd);
extern void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x);
extern void IFC_Int_Enable(void);
extern void IFC_Int_Disable(void);
extern void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern volatile unsigned int R_INT_FlashAdd;
extern volatile unsigned char f_Drom_write_complete;
extern volatile unsigned char f_Drom_writing;
extern volatile unsigned char ifc_step;
extern void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry);
extern void ReadDataArry_U32(unsigned int RdStartAdd,unsigned int DataLength,volatile U32_T *DataArryPoint);
#endif /**< apt32f102_ifc_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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Source/include/apt32f102_lpt.h Normal file
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@@ -0,0 +1,280 @@
/*
******************************************************************************
* @file apt32f102_lpt.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_lpt_H
#define _apt32f102_lpt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define LPT_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------LPT value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief LPT CLK EN register
*/
typedef enum
{
LPTCLK_DIS = 0,
LPTCLK_EN = 1,
}LPT_CLK_TypeDef;
/**
* @brief LPT CLK source register
*/
typedef enum
{
LPT_PCLK_DIV4= (0<<2),
LPT_ISCLK = (1<<2),
LPT_IMCLK_DIV4 = (2<<2),
LPT_EMCLK = (3<<2),
LPT_IN_RISE = (4<<2),
LPT_IN_FALL = (5<<2),
}LPT_CSS_TypeDef;
/**
* @brief LPT START SHADOW register
*/
typedef enum
{
LPT_SHADOW = (0<<6),
LPT_IMMEDIATE= (1<<6),
}LPT_SHDWSTP_TypeDef;
/**
* @brief LPT CLK div register
*/
typedef enum
{
LPT_PSC_DIV0= 0,
LPT_PSC_DIV2= 1,
LPT_PSC_DIV4= 2,
LPT_PSC_DIV8= 3,
LPT_PSC_DIV16= 4,
LPT_PSC_DIV32= 5,
LPT_PSC_DIV64= 6,
LPT_PSC_DIV128= 7,
LPT_PSC_DIV256= 8,
LPT_PSC_DIV512= 9,
LPT_PSC_DIV1024= 0X0A,
LPT_PSC_DIV2048= 0X0B,
LPT_PSC_DIV4096= 0X0C,
}LPT_PSCDIV_TypeDef;
/**
* @brief LPT START SYN EN register
*/
typedef enum
{
LPT_SWSYNDIS= (0<<2),
LPT_SWSYNEN= (1<<2),
}LPT_SWSYN_TypeDef;
/**
* @brief LPT IO stop status register
*/
typedef enum
{
LPT_IDLE_Z= (0<<3), //High-impedance output
LPT_IDLE_LOW= (1<<3),
}LPT_IDLEST_TypeDef;
/**
* @brief LPT PRDLD register
*/
typedef enum
{
LPT_PRDLD_IMMEDIATELY= (0<<4),
LPT_PRDLD_DUTY_END= (1<<4),
}LPT_PRDLD_TypeDef;
/**
* @brief LPT POL register
*/
typedef enum
{
LPT_POL_HIGH= (0<<5),
LPT_POL_LOW= (1<<5),
}LPT_POL_TypeDef;
/**
* @brief LPT OPM register
*/
typedef enum
{
LPT_OPM_CONTINUOUS= (0<<6),
LPT_OPM_ONCE= (1<<6),
}LPT_OPM_TypeDef;
/**
* @brief LPT FLTIPSCLD register
*/
typedef enum
{
LPT_FLTIPSCLD_NULL= (0<<10),
LPT_FLTIPSCLD_EN= (1<<10),
}LPT_FLTIPSCLD_TypeDef;
/**
* @brief LPT FLTDEB register
*/
typedef enum
{
LPT_FLTDEB_00= (0<<13),
LPT_FLTDEB_02= (1<<13),
LPT_FLTDEB_03= (2<<13),
LPT_FLTDEB_04= (3<<13),
LPT_FLTDEB_06= (4<<13),
LPT_FLTDEB_08= (5<<13),
LPT_FLTDEB_16= (6<<13),
LPT_FLTDEB_32= (7<<13),
}LPT_FLTDEB_TypeDef;
/**
* @brief LPT PSCLD register
*/
typedef enum
{
LPT_PSCLD_0= (0<<16), //PSCR
LPT_PSCLD_1= (1<<16),
}LPT_PSCLD_TypeDef;
/**
* @brief LPT CMPLD register
*/
typedef enum
{
LPT_CMPLD_IMMEDIATELY= (0<<17),
LPT_CMPLD_DUTY_END= (1<<17),
}LPT_CMPLD_TypeDef;
/**
* @brief LPT TRGENX register
*/
typedef enum
{
LPT_TRGEN_DIS= (0<<0),
LPT_TRGEN_EN= (1<<0),
}LPT_TRGENX_TypeDef;
/**
* @brief LPT OSTMDX register
*/
typedef enum
{
LPT_OSTMD_CONTINUOUS= (0<<8),
LPT_OSTMD_ONCE= (1<<8),
}LPT_OSTMDX_TypeDef;
/**
* @brief LPT AREARM register
*/
typedef enum
{
LPT_AREARM_DIS= (0<<30),
LPT_AREARM_EN= (1<<30),
}LPT_AREARM_TypeDef;
/**
* @brief LPT SRCSEL register
*/
typedef enum
{
LPT_SRCSEL_DIS= (0<<0),
LPT_SRCSEL_EN= (1<<0),
}LPT_SRCSEL_TypeDef;
/**
* @brief LPT BLKINV register
*/
typedef enum
{
LPT_BLKINV_DIS= (0<<4),
LPT_BLKINV_EN= (1<<4),
}LPT_BLKINV_TypeDef;
/**
* @brief LPT CROSSMD register
*/
typedef enum
{
LPT_CROSSMD_DIS= (0<<7),
LPT_CROSSMD_EN= (1<<7),
}LPT_CROSSMD_TypeDef;
/**
* @brief LPT TRGSRC0 register
*/
typedef enum
{
LPT_TRGSRC0_DIS= (0<<0),
LPT_TRGSRC0_ZRO= (1<<0),
LPT_TRGSRC0_PRD= (2<<0),
LPT_TRGSRC0_ZRO_PRD= (3<<0),
LPT_TRGSRC0_CMP= (4<<0),
}LPT_TRGSRC0_TypeDef;
/**
* @brief LPT ESYN0OE register
*/
typedef enum
{
LPT_ESYN0OE_DIS= (0<<20),
LPT_ESYN0OE_EN= (1<<20),
}LPT_ESYN0OE_TypeDef;
/**
* @brief LPT INT MASK SET/CLR Set
*/
typedef enum
{
LPT_TRGEV0 = (0x01 << 0),
LPT_MATCH = (0x01 << 1),
LPT_PEND = (0x01 << 2),
}LPT_IMSCR_TypeDef;
/**
* @brief LPT IO Set
*/
typedef enum
{
LPT_OUT_PA09 = 0,
LPT_OUT_PB01 = 1,
LPT_IN_PA10 = 2,
}LPT_IOSET_TypeDef;
#define LPT_DEBUG_MODE (0X01<<1)
extern void LPT_DeInit(void);
extern void LPT_IO_Init(LPT_IOSET_TypeDef IONAME);
extern void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,
LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX);
extern void LPT_Debug_Mode(FunctionalStatus NewState);
extern void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA);
extern void LPT_CNT_Write(U16_T CNT_DATA);
extern U16_T LPT_PRDR_Read(void);
extern U16_T LPT_CMP_Read(void);
extern U16_T LPT_CNT_Read(void);
extern void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX);
extern void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX);
extern void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA);
extern void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA);
extern void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA);
extern void LPT_Soft_Trigger(void);
extern void LPT_Start(void);
extern void LPT_Stop(void);
extern void LPT_Soft_Reset(void);
extern void LPT_REARM_Write(void);
extern U8_T LPT_REARM_Read(void);
extern void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X);
extern void LPT_INT_ENABLE(void);
extern void LPT_INT_DISABLE(void);
/*************************************************************/
#endif /**< apt32f102_lpt_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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Source/include/apt32f102_syscon.h Normal file
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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.09
* @date 2021/07/30
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_syscon_H
#define _apt32f102_syscon_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* syscon Registers Definition *************************
******************************************************************************/
/** @addtogroup SYSCON Registers Reset Value
* @{
*/
#define SYSCON_IDCCR_RST ((CSP_REGISTER_T)0x00000001)
#define SYSCON_GCER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_GCDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_GCSR_RST ((CSP_REGISTER_T)0x00081103)
#define SYSCON_CKST_RST ((CSP_REGISTER_T)0x00000103)
#define SYSCON_RAMCHK_RST ((CSP_REGISTER_T)0x0000ffff)
#define SYSCON_EFLCHK_RST ((CSP_REGISTER_T)(0X0<<24)|0xffffff)
#define SYSCON_SCLKCR_RST ((CSP_REGISTER_T)0xD22Dul<<16)
#define SYSCON_PCLKCR_RST ((CSP_REGISTER_T)0x00000100)
#define SYSCON_PCER0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCDR0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCSR0_RST ((CSP_REGISTER_T)0x005107d1)
#define SYSCON_PCER1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCDR1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCSR1_RST ((CSP_REGISTER_T)0x3023f80)
#define SYSCON_OSTR_RST ((CSP_REGISTER_T)0x70ff3bff)
#define SYSCON_LVDCR_RST ((CSP_REGISTER_T)0x0000000a)
#define SYSCON_CLCR_RST ((CSP_REGISTER_T)0x00000100)
#define SYSCON_PWRCR_RST ((CSP_REGISTER_T)0x141f1f00)
#define SYSCON_IMER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IMDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IMCR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IAR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_ICR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_RISR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_MISR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIRT_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIFT_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIMR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIAR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXICR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIRS_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IWDCR_RST ((CSP_REGISTER_T)0x0000070C)
#define SYSCON_IWDCNT_RST ((CSP_REGISTER_T)0x000003fe)
#define SYSCON_PWROPT_RST ((CSP_REGISTER_T)0x00004040)
#define SYSCON_EVTRG_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EVPS_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EVSWF_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG2_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG3_RST ((CSP_REGISTER_T)0x00000000)
//SCLKCR
#define SYSCLK_KEY (0xD22Dul<<16)
//PCLK CONTROL
#define PCLK_KEY (0xC33Cul<<16)
//IDCCR
#define CLKEN (0X01ul)
#define CPUFTRST_EN (0X00<<1)
#define CPUFTRST_DIS (0XA<<1)
#define SWRST (0X01ul<<7)
#define IDCCR_KEY (0xE11Eul<<16)
//LVDCR
#define LVDFLAG (0x01ul<<15) //0: VDD is higher than LVD threshold selected with INTDET_LVL bits. 1: VDD is lower than LVD threshold selected with INTDET_LVL bits
#define LVD_KEY (0xB44Bul<<16)
//IECR IEDR IAR ICR IMSR RISR ISR
//Interrupt Enable/Disable/Active/Clear Control Register
//Interrupt Masking/Raw Interrupt/Masked Status Register
#define ISOSC_ST (0x01ul)
#define IMOSC_ST (0x01ul<<1)
#define ESOSC_ST (0x01ul<<2)
#define EMOSC_ST (0x01ul<<3)
#define HFOSC_ST (0x01ul<<4)
#define SYSCLK_ST (0x01ul<<7)
#define IWDT_INT_ST (0x01ul<<8)
#define WKI_INT_ST (0x01ul<<9)
#define RAMERRINT_ST (0X01ul<<10)
#define LVD_INT_ST (0x01ul<<11)
#define HWD_ERR_ST (0X01ul<<12)
#define EFL_ERR_ST (0X01ul<<13)
#define OPTERR_INT (0X01ul<<14)
#define EM_CMLST_ST (0x01ul<<18)
#define EM_EVTRG0_ST (0x01ul<<19)
#define EM_EVTRG1_ST (0x01ul<<20)
#define EM_EVTRG2_ST (0x01ul<<21)
#define EM_EVTRG3_ST (0x01ul<<22)
#define CMD_ERR_ST (0x01ul<<29)
//RSR
//SYSCON Reset Status Register
#define PORST (0X01ul)
#define LVRRST (0X01ul<<1)
#define EXTRST (0X01ul<<2)
#define ALVRST (0X01ul<<3)
#define IWDRST (0X01ul<<4)
#define EMCMRST (0X01ul<<6)
#define CPURSTREQ (0X01ul<<7)
#define SWRST_RSR (0X01ul<<8)
#define CPUFAULT_RSR (0X01ul<<9)
#define SRAM_RSR (0X01ul<<11)
#define EFL_ERR (0X01ul<<12)
#define WWDTRST (0X01ul<<13)
//IWDCR
#define Check_IWDT_BUSY (0x01ul<<12) //Indicates the independent watchdog operation
#define IWDT_KEY (0x8778ul<<16)
//IWDCNT
#define CLR_IWDT (0x5aul<<24)
//IWDEDR
#define Enable_IWDT (0x0)
#define Disable_IWDT (0x55aa)
#define IWDTEDR_KEY (0x7887ul<<16)
#define CORET_IRQ 0
#define SYSCON_IRQ 1
#define IFC_IRQ 2
#define ADC_IRQ 3
#define EPT0_IRQ 4
#define WWDT_IRQ 6
#define EXI0_IRQ 7
#define EXI1_IRQ 8
#define GPT0_IRQ 9
#define RTC_IRQ 12
#define UART0_IRQ 13
#define UART1_IRQ 14
#define UART2_IRQ 15
#define I2C_IRQ 17
#define SPI_IRQ 19
#define SIO_IRQ 20
#define EXI2_IRQ 21
#define EXI3_IRQ 22
#define EXI4_IRQ 23
#define CA_IRQ 24
#define TKEY_IRQ 25
#define LPT_IRQ 26
#define BT0_IRQ 28
#define BT1_IRQ 29
/**
* @brief SYSCON General Control
*/
typedef enum
{
ENDIS_ISOSC = (CSP_REGISTER_T)(0x01ul),
ENDIS_IMOSC = (CSP_REGISTER_T)(0x01ul<<1),
ENDIS_EMOSC = (CSP_REGISTER_T)(0x01ul<<3),
ENDIS_HFOSC = (CSP_REGISTER_T)(0x01ul<<4),
ENDIS_IDLE_PCLK = (CSP_REGISTER_T)(0x01ul<<8),
ENDIS_SYSTICK = (CSP_REGISTER_T)(0x01ul<<11)
}SYSCON_General_CMD_TypeDef;
/**
* @brief Selected SYSCON CLK
*/
typedef enum
{
SYSCLK_IMOSC = (CSP_REGISTER_T)0x0ul, //IMOSC selected
SYSCLK_EMOSC = (CSP_REGISTER_T)0x1ul, //EMOSC selected
SYSCLK_HFOSC = (CSP_REGISTER_T)0x2ul, //HFOSC selected
SYSCLK_ISOSC = (CSP_REGISTER_T)0x4ul //ISOSC selected
}SystemCLK_TypeDef;
/**
* @brief SYSCON CLK Div
*/
typedef enum
{
HCLK_DIV_1 = (CSP_REGISTER_T)(0x1ul<<8),
HCLK_DIV_2 = (CSP_REGISTER_T)(0x2ul<<8),
HCLK_DIV_3 = (CSP_REGISTER_T)(0x3ul<<8),
HCLK_DIV_4 = (CSP_REGISTER_T)(0x4ul<<8),
HCLK_DIV_5 = (CSP_REGISTER_T)(0x5ul<<8),
HCLK_DIV_6 = (CSP_REGISTER_T)(0x6ul<<8),
HCLK_DIV_7 = (CSP_REGISTER_T)(0x7ul<<8),
HCLK_DIV_8 = (CSP_REGISTER_T)(0x8ul<<8),
HCLK_DIV_12 = (CSP_REGISTER_T)(0x9ul<<8),
HCLK_DIV_16 = (CSP_REGISTER_T)(0xAul<<8),
HCLK_DIV_24 = (CSP_REGISTER_T)(0xBul<<8),
HCLK_DIV_32 = (CSP_REGISTER_T)(0xCul<<8),
HCLK_DIV_64 = (CSP_REGISTER_T)(0xDul<<8),
HCLK_DIV_128 = (CSP_REGISTER_T)(0xEul<<8),
HCLK_DIV_256 = (CSP_REGISTER_T)(0xFul<<8)
}SystemCLK_Div_TypeDef;
/**
* @brief PCLK Div
*/
typedef enum
{
PCLK_DIV_1 = (CSP_REGISTER_T)(0x00ul<<8),
PCLK_DIV_2 = (CSP_REGISTER_T)(0x01ul<<8),
PCLK_DIV_4 = (CSP_REGISTER_T)(0x02ul<<8),
PCLK_DIV_8 = (CSP_REGISTER_T)(0x04ul<<8),
PCLK_DIV_16 = (CSP_REGISTER_T)(0x08ul<<8)
}PCLK_Div_TypeDef;
/**
* @brief LVD enable and disable
*/
typedef enum
{
ENABLE_LVDEN = (CSP_REGISTER_T)0x00, //Power down LVD module
DISABLE_LVDEN = (CSP_REGISTER_T)0x0a //Power down LVD module
}X_LVDEN_TypeDef;
/**
* @brief Detection voltage level to trigger the LVD interrupt
*/
typedef enum
{
INTDET_LVL_2_1V = (CSP_REGISTER_T)(0X00ul<<8), //2.1V
INTDET_LVL_2_4V = (CSP_REGISTER_T)(0X01ul<<8), //2.4V
INTDET_LVL_2_7V = (CSP_REGISTER_T)(0X02ul<<8), //2.7V
INTDET_LVL_3_0V = (CSP_REGISTER_T)(0X03ul<<8), //3.0V
INTDET_LVL_3_3V = (CSP_REGISTER_T)(0X04ul<<8), //3.3V
INTDET_LVL_3_6V = (CSP_REGISTER_T)(0X05ul<<8), //3.6V
INTDET_LVL_3_9V = (CSP_REGISTER_T)(0X06ul<<8), //3.9V
}INTDET_LVL_X_TypeDef;
/**
* @brief Detection voltage level to generate reset
*/
typedef enum
{
RSTDET_LVL_1_9V = (CSP_REGISTER_T)(0X00ul<<12), //1.9V
RSTDET_LVL_2_2V = (CSP_REGISTER_T)(0X01ul<<12), //2.2V
RSTDET_LVL_2_5V = (CSP_REGISTER_T)(0X02ul<<12), //2.5V
RSTDET_LVL_2_8V = (CSP_REGISTER_T)(0X03ul<<12), //2.8V
RSTDET_LVL_3_1V = (CSP_REGISTER_T)(0X04ul<<12), //3.1V
RSTDET_LVL_3_4V = (CSP_REGISTER_T)(0X05ul<<12), //3.4V
RSTDET_LVL_3_7V = (CSP_REGISTER_T)(0X06ul<<12), //3.7V
RSTDET_LVL_4_0V = (CSP_REGISTER_T)(0X07ul<<12) //4.0V
}RSTDET_LVL_X_TypeDef;
/**
* @brief Detection voltage level to trigger the LVD interrupt
*/
typedef enum
{
ENABLE_LVD_INT = (CSP_REGISTER_T)(0X01ul<<11), //ENABLE LVD INT
DISABLE_LVD_INT = (CSP_REGISTER_T)(0X00ul<<11) //DISABLE LVD INT
}X_LVD_INT_TypeDef;
/**
* @brief EXI PIN
*/
typedef enum
{
EXI_PIN0 = (CSP_REGISTER_T)(0X01ul),
EXI_PIN1 = (CSP_REGISTER_T)(0X01ul<<1),
EXI_PIN2 = (CSP_REGISTER_T)(0X01ul<<2),
EXI_PIN3 = (CSP_REGISTER_T)(0X01ul<<3),
EXI_PIN4 = (CSP_REGISTER_T)(0X01ul<<4),
EXI_PIN5 = (CSP_REGISTER_T)(0X01ul<<5),
EXI_PIN6 = (CSP_REGISTER_T)(0X01ul<<6),
EXI_PIN7 = (CSP_REGISTER_T)(0X01ul<<7),
EXI_PIN8 = (CSP_REGISTER_T)(0X01ul<<8),
EXI_PIN9 = (CSP_REGISTER_T)(0X01ul<<9),
EXI_PIN10 = (CSP_REGISTER_T)(0X01ul<<10),
EXI_PIN11 = (CSP_REGISTER_T)(0X01ul<<11),
EXI_PIN12 = (CSP_REGISTER_T)(0X01ul<<12),
EXI_PIN13 = (CSP_REGISTER_T)(0X01ul<<13),
EXI_PIN14 = (CSP_REGISTER_T)(0X01ul<<14),
EXI_PIN15 = (CSP_REGISTER_T)(0X01ul<<15),
EXI_PIN16 = (CSP_REGISTER_T)(0X01ul<<16),
EXI_PIN17 = (CSP_REGISTER_T)(0X01ul<<17),
EXI_PIN18 = (CSP_REGISTER_T)(0X01ul<<18),
EXI_PIN19 = (CSP_REGISTER_T)(0X01ul<<19),
}SYSCON_EXIPIN_TypeDef;
/**
* @brief EXT register
*/
typedef enum
{
_EXIRT = 0,
_EXIFT = 1,
}EXI_tringer_mode_TypeDef;
/**
* @brief SYSON IWDT TIME SET
*/
typedef enum
{
IWDT_TIME_125MS = (CSP_REGISTER_T)(0x00ul<<8), //IWDT_TIME 0x00fff
IWDT_TIME_250MS = (CSP_REGISTER_T)(0x01ul<<8), //IWDT_TIME 0x01fff
IWDT_TIME_500MS = (CSP_REGISTER_T)(0x02ul<<8), //IWDT_TIME 0x03fff
IWDT_TIME_1S = (CSP_REGISTER_T)(0x03ul<<8), //IWDT_TIME 0x07fff
IWDT_TIME_2S = (CSP_REGISTER_T)(0x04ul<<8), //IWDT_TIME 0x0ffff //2M ISOSC 2sec
IWDT_TIME_3S = (CSP_REGISTER_T)(0x05ul<<8), //IWDT_TIME 0x16fff
IWDT_TIME_4S = (CSP_REGISTER_T)(0x06ul<<8), //IWDT_TIME 0x1ffff
IWDT_TIME_8S = (CSP_REGISTER_T)(0x07ul<<8) //IWDT_TIME 0x3ffff
}IWDT_TIME_TypeDef;
/**
* @brief SYSON IWDT TIME DIV SET
*/
typedef enum
{
IWDT_INTW_DIV_1 = (0x00ul<<2), //1/8 of IWDT_TIME
IWDT_INTW_DIV_2 = (0x01ul<<2), //2/8 of IWDT_TIME
IWDT_INTW_DIV_3 = (0x02ul<<2), //3/8 of IWDT_TIME
IWDT_INTW_DIV_4 = (0x03ul<<2), //4/8 of IWDT_TIME
IWDT_INTW_DIV_5 = (0x04ul<<2), //5/8 of IWDT_TIME
IWDT_INTW_DIV_6 = (0x05ul<<2), //6/8 of IWDT_TIME
IWDT_INTW_DIV_7 = (0x06ul<<2) //7/8 of IWDT_TIME
}IWDT_TIMEDIV_TypeDef;
/**
* @brief IMOSC SELECTE SET
*/
typedef enum
{
IMOSC_SELECTE_5556K = (0x00ul<<0),
IMOSC_SELECTE_4194K = (0x01ul<<0),
IMOSC_SELECTE_2097K = (0x02ul<<0),
IMOSC_SELECTE_131K = (0x03ul<<0)
}IMOSC_SELECTE_TypeDef;
/**
* @brief HFOSC SELECTE SET
*/
typedef enum
{
HFOSC_SELECTE_48M = (0x0ul<<4),
HFOSC_SELECTE_24M = (0x1ul<<4),
HFOSC_SELECTE_12M = (0x2ul<<4),
HFOSC_SELECTE_6M = (0x3ul<<4)
}HFOSC_SELECTE_TypeDef;
/**
* @brief EM Filter set
*/
typedef enum
{
EM_FLSEL_5ns = (0x0ul<<26),
EM_FLSEL_10ns = (0x1ul<<26),
EM_FLSEL_15ns = (0x2ul<<26),
EM_FLSEL_20ns = (0x3ul<<26)
}EM_Filter_TypeDef;
/**
* @brief EM Filter CMD
*/
typedef enum
{
EM_FLEN_DIS = (0x0ul<<25),
EM_FLEN_EN = (0x1ul<<25)
}EM_Filter_CMD_TypeDef;
/**
* @brief EM LFSEL BIT
*/
typedef enum
{
EM_LFSEL_DIS = (0x0ul<<10),
EM_LFSEL_EN = (0x1ul<<10)
}EM_LFSEL_TypeDef;
/**
* @brief EM Systemclk data
*/
typedef enum
{
EMOSC_24M = 0,
EMOSC_16M = 1,
EMOSC_12M = 2,
EMOSC_8M = 3,
EMOSC_4M = 4,
EMOSC_36K = 5,
IMOSC = 6,
ISOSC = 7,
HFOSC_48M = 8,
HFOSC_24M = 9,
HFOSC_12M = 10,
HFOSC_6M = 11
}SystemClk_data_TypeDef;
typedef enum
{
CLO_PA02 = 0, //PA0.0 as clo
CLO_PA08 = 1, //PA0.8 as clo
}CLO_IO_TypeDef;
typedef enum
{
INTDET_POL_fall = (1<<6), //fall Trigger
INTDET_POL_X_rise = (2<<6), //rise Trigger
INTDET_POL_X_riseORfall = (3<<6), //fall or rise Trigger
}INTDET_POL_X_TypeDef;
typedef enum
{
//IOMAP0
PIN_I2C_SCL = 0X00, //
PIN_I2C_SDA = 0X01, //
PIN_GPT_CHA = 0X02, //
PIN_GPT_CHB = 0X03, //
PIN_SPI_MOSI = 0X04, //
PIN_SPI_MISO = 0X05, //
PIN_SPI_SCK = 0X06, //
PIN_SPI_NSS = 0X07, //
//IOMAP1
PIN_UART0_RX = 0X10, //
PIN_UART0_TX = 0X11, //
PIN_EPT_CHAX = 0X12, //
PIN_EPT_CHBX = 0X13, //
PIN_EPT_CHCX = 0X14, //
PIN_EPT_CHAY = 0X15, //
PIN_EPT_CHBY = 0X16, //
PIN_EPT_CHCY = 0X17, //
}IOMAP_DIR_TypeDef;
/**
* @brief CLOMX Systemclk data
*/
typedef enum
{
CLO_ISCLK = 0,
CLO_IMCLK = 1,
CLO_EMCLK = 3,
CLO_HFCLK = 4,
CLO_RTCCLK = 6,
CLO_PCLK = 7,
CLO_HCLK = 8,
CLO_IWDTCLK = 9,
CLO_SYSCLK = 0X0D,
}SystemClk_CLOMX_TypeDef;
/**
* @brief CLOMX Systemclk data
*/
typedef enum
{
CLO_DIV0 = 1,
CLO_DIV4 = 0,
CLO_DIV2 = 2,
CLO_DIV8 = 4,
CLO_DIV16 = 5,
}SystemClk_CLODIV_TypeDef;
/** @addtogroup SYSCON_Exported_functions
* @{
*/
extern void SYSCON_RST_VALUE(void);
extern void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X );
extern void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X);
extern void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x );
extern void SYSCON_WDT_CMD(FunctionalStatus NewState);
extern void SYSCON_IWDCNT_Reload(void);
extern void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X );
extern void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X);
extern void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode);
extern void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN);
extern void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io);
extern U32_T SYSCON_Read_CINF0(void);
extern U32_T SYSCON_Read_CINF1(void);
extern void SYSCON_INT_Priority(void);
extern void EXI0_Int_Enable(void);
extern void EXI0_Int_Disable(void);
extern void EXI1_Int_Enable(void);
extern void EXI1_Int_Disable(void);
extern void EXI2_Int_Enable(void);
extern void EXI2_Int_Disable(void);
extern void EXI3_Int_Enable(void);
extern void EXI3_Int_Disable(void);
extern void EXI4_Int_Enable(void);
extern void EXI4_Int_Disable(void);
extern void SYSCON_Int_Enable(void);
extern void SYSCON_Int_Disable(void);
extern void PCLK_goto_idle_mode(void);
extern void PCLK_goto_deepsleep_mode(void);
extern void LVD_Int_Enable(void);
extern void LVD_Int_Disable(void);
extern void IWDT_Int_Enable(void);
extern void IWDT_Int_Disable(void);
extern void EXI0_WakeUp_Enable(void);
extern void EXI0_WakeUp_Disable(void);
extern void EXI1_WakeUp_Enable(void);
extern void EXI1_WakeUp_Disable(void);
extern void EXI2_WakeUp_Enable(void);
extern void EXI2_WakeUp_Disable(void);
extern void EXI3_WakeUp_Enable(void);
extern void EXI3_WakeUp_Disable(void);
extern void EXI4_WakeUp_Enable(void);
extern void EXI4_WakeUp_Disable(void);
extern void SYSCON_WakeUp_Enable(void);
extern void SYSCON_WakeUp_Disable(void);
extern void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE);
extern void SYSCON_Software_Reset(void);
extern void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X);
extern void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X);
extern void SystemCLK_Clear(void);
extern void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data);
extern void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr);
extern void Set_INT_Priority(U8_T int_name,U8_T int_level);
extern U32_T Read_Reset_Status(void);
#endif /**< apt32f102_syscon_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_types_local.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#ifndef TYPES_LOCAL_H
#define TYPES_LOCAL_H
/**************************************************************************/
/**************************************************************************
STANDARD DEFINES
**************************************************************************/
#define NIL '\000'
#define TRUE 1
#define FALSE 0
#define YES 1
#define NO 0
#define ON 1
#define OFF 0
#define GOOD 1
#define BAD 0
#define BELL 7 /* Ring the bell */
#define MAX_SINT16 32767
#define CPNULL ((char *)0)
#define NONENTRY -1.0E12
#define DPIE (DOUBLE)3.141592653589793
/* other stuff... */
#define STRNCPY(a,b,c) strncpy (a,b,c); (*((a)+(c)) = 0x00);
/**************************************************************************
STANDARD TYPEDEFS
The ANSI C std defines:
short <= int <= long
char >= 8 bits
short >= 16 bits
long >= 32 bits
(from Harbison & Steele, "C, A Ref. Manual" 3rd ed. p. 99)
so all ANSI C compliant compilers will accept the following.
**************************************************************************/
#ifndef CSP_TYPES_H
#define CSP_TYPES_H
/* Signed Types */
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;
/* Unsigned Types */
typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;
/* Float Types */
typedef float F32_T;
typedef double F64_T;
/* Boolean types declared as U8_T, as enums are generated as 16 bit */
typedef U8_T B_T;
/* Definitions for the two members of the Boolean type */
#ifndef FALSE
#define FALSE ((B_T) 0)
#endif
#ifndef TRUE
#define TRUE ((B_T) 1)
#endif
/* UNUSED Definition for unused Interrupt numbers * and unused PDC channels */
/* in the CHIP structure. (cf. CSP.C file) */
#ifndef UNUSED
#define UNUSED ((U8_T) 0xFF)
#endif
/* NULL definition */
#ifndef NULL
#define NULL 0
#endif
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
/******************************************************************************
* Peripherals Type
******************************************************************************/
typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;
#endif /* CSP_TYPE_H */
/* define 8 bit types */
typedef unsigned char UINT8;
typedef signed char SINT8;
/* define 16 bit types */
typedef unsigned short UINT16;
typedef signed short SINT16;
/* define 32 bit types */
typedef unsigned long UINT32;
typedef signed long SINT32;
typedef void VOID;
typedef signed char CHAR; /* be careful of EOF!!! (EOF = -1) */
typedef unsigned char BOOL;
typedef signed long TIME_T;
typedef float SINGLE;
#ifdef DOUBLE
#undef DOUBLE
#endif
typedef double DOUBLE;
typedef struct
{
unsigned bit0 : 1;
unsigned bit1 : 1;
unsigned bit2 : 1;
unsigned bit3 : 1;
unsigned bit4 : 1;
unsigned bit5 : 1;
unsigned bit6 : 1;
unsigned bit7 : 1;
} REG8;
typedef struct
{
unsigned bit0 : 1;
unsigned bit1 : 1;
unsigned bit2 : 1;
unsigned bit3 : 1;
unsigned bit4 : 1;
unsigned bit5 : 1;
unsigned bit6 : 1;
unsigned bit7 : 1;
unsigned bit8 : 1;
unsigned bit9 : 1;
unsigned bit10: 1;
unsigned bit11: 1;
unsigned bit12: 1;
unsigned bit13: 1;
unsigned bit14: 1;
unsigned bit15: 1;
} REG16;
/**************************************************************************
STANDARD STRING TYPEDEFS
**************************************************************************/
typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
/********************************************/
/* STANDARD SYSTEM SIZES */
/********************************************/
#define SIZE_UINT8 (size_t)(sizeof (UINT8 ))
#define SIZE_SINT8 (size_t)(sizeof (SINT8 ))
#define SIZE_UINT16 (size_t)(sizeof (UINT16))
#define SIZE_SINT16 (size_t)(sizeof (SINT16))
#define SIZE_UINT32 (size_t)(sizeof (UINT32))
#define SIZE_SINT32 (size_t)(sizeof (SINT32))
#define SIZE_VOID (size_t)(sizeof (VOID ))
#define SIZE_CHAR (size_t)(sizeof (CHAR ))
#define SIZE_BOOL (size_t)(sizeof (BOOL ))
#define SIZE_TIME_T (size_t)(sizeof (TIME_T))
#define SIZE_SINGLE (size_t)(sizeof (SINGLE))
#define SIZE_DOUBLE (size_t)(sizeof (DOUBLE))
#define SIZE_STRING_3 (size_t)(sizeof (STRING_3 ))
#define SIZE_STRING_5 (size_t)(sizeof (STRING_5 ))
#define SIZE_STRING_8 (size_t)(sizeof (STRING_8 ))
#define SIZE_STRING_10 (size_t)(sizeof (STRING_10 ))
#define SIZE_STRING_12 (size_t)(sizeof (STRING_12 ))
#define SIZE_STRING_16 (size_t)(sizeof (STRING_16 ))
#define SIZE_STRING_24 (size_t)(sizeof (STRING_24 ))
#define SIZE_STRING_30 (size_t)(sizeof (STRING_30 ))
#define SIZE_STRING_32 (size_t)(sizeof (STRING_32 ))
#define SIZE_STRING_48 (size_t)(sizeof (STRING_48 ))
#define SIZE_STRING_50 (size_t)(sizeof (STRING_50 ))
#define SIZE_STRING_60 (size_t)(sizeof (STRING_60 ))
#define SIZE_STRING_80 (size_t)(sizeof (STRING_80 ))
#define SIZE_STRING_132 (size_t)(sizeof (STRING_132))
#define SIZE_STRING_256 (size_t)(sizeof (STRING_256))
#define SIZE_STRING_512 (size_t)(sizeof (STRING_512))
/**************************************************************************
STANDARD BIT MANIPULATIONS
**************************************************************************/
#define SETBIT( target, bit ) ((target) |= (1u << (bit)))
#define CLRBIT( target, bit ) ((target) &= ~(1u << (bit)))
#define TOGBIT( target, bit ) ((target) ^= (1u << (bit)))
#define ISBITSET( target, bit ) (!!((target) & (1u << (bit))))
#define ISBITCLR( target, bit ) ( !((target) & (1u << (bit))))
/**************************************************************************/
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_uart.h
* @author APT AE Team
* @version V1.13
* @date 2021/12/13
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_uart_H
#define _apt32f102_uart_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
typedef enum
{
UART_PAR_NONE =0<<8, //无校验位
UART_PAR_EVEN =4<<8, //偶校验位
UART_PAR_ODD =5<<8, //奇校验位
UART_PAR_SPACE =6<<8, //0校验位
UART_PAR_MARK =7<<8 //1校验位
}UART_PAR_TypeDef;
/**
* @brief UART IO setting
*/
typedef enum
{
IO_UART0 = 0,
IO_UART1 = 1,
IO_UART2 = 2,
}UART_NUM_TypeDef;
/*****************************************************************************
************************** UART Function defined *****************************
******************************************************************************/
#define UART_RESET_VALUE (0x00000000)
/** SR : UART Status Register */
#define UART_TX_FULL (0x01ul << 0) /**< Transmitter full */
#define UART_RX_FULL (0x01ul << 1) /**< Receiver full */
#define UART_TX_OVER (0x01ul << 2) /**< Transmitter buff over */
#define UART_RX_OVER (0x01ul << 3) /**< Receiver buff over */
/** CTRL : UART Control Register */
#define UART_TX (0x01ul << 0) /**< Transmitter Enable/disable */
#define UART_RX (0x01ul << 1) /**< Receiver Enable/disable */
#define UART_TX_INT (0x01ul << 2) /**< Transmitter INT Enable/disable */
#define UART_RX_INT (0x01ul << 3) /**< Receiver INT Enable/disable */
#define UART_TX_IOV (0x01ul << 4) /**< Transmitter INTOver Enable/disable*/
#define UART_RX_IOV (0x01ul << 5) /**< Receiver INTOver Enable/disable */
#define UART_PARUTY_ERR_INT (0x01ul << 7) /**< PARUTY ERROR Status */
#define UART_TX_FIFO_INT (0x01ul << 12) /**< TX fifo int Enable/disable */
#define UART_RX_FIFO_INT (0x01ul << 13) /**< RX fifo int Enable/disable */
#define UART_RX_FIFOOV_INT (0x01ul << 18) /**< RX fifo int over Enable/disable */
#define UART_TX_DONE_INT (0x01ul << 19) /**< Receiver TX done Enable/disable */
//#define UART_TEST_MODE (0x01ul << 6) /**< =1 Test mode */
/** ISR : UART Interrupt Status Register */
#define UART_TX_INT_S (0x01ul << 0) /**< Transmitter INT Status */
#define UART_RX_INT_S (0x01ul << 1) /**< Receiver INTStatus */
#define UART_TX_IOV_S (0x01ul << 2) /**< Transmitter INTOver Status */
#define UART_RX_IOV_S (0x01ul << 3) /**< Receiver INTOver Status */
#define UART_PARUTY_ERR_S (0x01ul << 4) /**< PARUTY ERROR Status */
#define UART_TXMIS_S (0x01ul << 5) /**< tx fifo Status */
#define UART_RXMIS_S (0x01ul << 6) /**< rx fifo Status */
#define UART_RORMIS_S (0x01ul << 7) /**< rx fifo over Status */
#define UART_TX_DONE_S (0x01ul << 19) /**< Receiver INTOver Status */
/** Set DATA register */
#define CSP_UART_SET_DATA(uart, val) ((uart)->DATA = (val))
/** Get DATA register */
#define CSP_UART_GET_DATA(uart) ((uart)->DATA)
/** Set SR register */
#define CSP_UART_SET_SR(uart, val) ((uart)->SR = (val))
/** Get SR register */
#define CSP_UART_GET_SR(uart) ((uart)->SR)
/** Set CTRL register */
#define CSP_UART_SET_CTRL(uart, val) ((uart)->CTRL = (val))
/** Get CTRL register */
#define CSP_UART_GET_CTRL(uart) ((uart)->CTRL)
/** Set ISR register */
#define CSP_UART_SET_ISR(uart, val) ((uart)->ISR = (val))
/** Get ISR register */
#define CSP_UART_GET_ISR(uart) ((uart)->ISR)
/** Set BRDIV register */
#define CSP_UART_SET_BRDIV(uart, val) ((uart)->BRDIV = (val))
/** Get BRDIV register */
#define CSP_UART_GET_BRDIV(uart) ((uart)->BRDIV)
/** UART External Variable Declaration */
#define UART_BUFSIZE 32
extern volatile U16_T RxDataBuf[12];
extern volatile U16_T RxDataPtr;
extern volatile U16_T TxDataPtr;
extern volatile U8_T RxDataFlag;
extern volatile U8_T TxDataFlag;
extern volatile U8_T Uart_send_Length;
extern volatile U16_T Uart_send_Length_temp;
extern volatile U8_T Uart_buffer[UART_BUFSIZE];
/** UART External Functions Declaration */
extern void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTClose(CSP_UART_T *uart);
extern void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8);
extern void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16);
extern U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16);
extern U8_T UART_ReturnRxByte(CSP_UART_T *uart);
extern U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16);
extern void UART0_DeInit(void);
extern void UART1_DeInit(void);
extern void UART2_DeInit(void);
extern void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G);
extern void UART0_Int_Enable(void);
extern void UART1_Int_Enable(void);
extern void UART2_Int_Enable(void);
extern void UART0_Int_Disable(void);
extern void UART1_Int_Disable(void);
extern void UART2_Int_Disable(void);
extern void UART0_WakeUp_Enable(void);
extern void UART1_WakeUp_Enable(void);
extern void UART2_WakeUp_Enable(void);
extern void UART0_WakeUp_Disable(void);
extern void UART1_WakeUp_Disable(void);
extern void UART2_WakeUp_Disable(void);
extern void UART0_CONFIG(void);
extern void UART1_CONFIG(void);
extern void UART2_CONFIG(void);
extern void UARTTTransmit_data_set(CSP_UART_T *uart );
extern void UARTTransmit_INT_Send(CSP_UART_T *uart );
#endif /**< apt32f102_types_local_H */
/******************* (C) COPYRIGHT 2016 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_wwdt.h
* @author APT AE Team
* @version V1.02
* @date 2020/11/20
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_wwdt_H
#define _apt32f102_wwdt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define WWDT_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------wwdt value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief PSC DIV register
*/
typedef enum
{
PCLK_4096_DIV0 = (0<<8),
PCLK_4096_DIV2 = (1<<8),
PCLK_4096_DIV4 = (2<<8),
PCLK_4096_DIV8 = (3<<8),
}WWDT_PSCDIV_TypeDef;
/**
* @brief WWDT DEBUG MODE register
*/
typedef enum
{
WWDT_DBGDIS = (0<<10),
WWDT_DBGEN = (1<<10),
}WWDT_DBGEN_TypeDef;
#define WWDT_EVI 0X01
extern void WWDT_DeInit(void);
extern void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX);
extern void WWDT_CMD(FunctionalStatus NewState);
extern void WWDT_CNT_Load(U8_T cnt_data);
extern void WWDT_Int_Config(FunctionalStatus NewState);
/*************************************************************/
#endif /**< apt32f102_wwdt_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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#ifndef _INCLUDES_H_
#define _INCLUDES_H_
#include "apt32f102.h"
#include "apt32f102_bt.h"
#include "apt32f102_gpio.h"
#include "apt32f102_ifc.h"
#include "apt32f102_lpt.h"
#include "apt32f102_syscon.h"
#include "apt32f102_uart.h"
#include "apt32f102_wwdt.h"
#include "apt32f102_types_local.h"
#include "apt32f102_clkcalib.h"
/*应用代码头文件*/
#include "uart.h"
#include "eeprom.h"
#include "Bootload_fun.h"
/*工程名称及软件版本号
此定义在每个工程中必须定义，用于识别当前工程对应的机型
Boot中会通过读取EEPROM中保存的设备信息来判断当前是什么机型
如果EEPROM 中没有保存设备信息，那么当前就是Boot程序，设备地址为0x00，设备类型为0x00
*/
#define Project_Area 0x01 //工程所处区域为Boot区域 0x01:Boot区域；0x02:APP区域
#define Peoject_Name "MD203_Bootload" //工程名称
#define Project_FW_Version 0x05 //工程对应的软件版本号
#define Project_Type 0x00 //工程对应的设备类型 Boot默认设备类型
extern volatile U32_T SysTick_100us;
extern volatile U32_T SysTick_1ms;
#endif

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#include "includes.h"
extern void delay_nms(unsigned int t);
extern void APT32F102_init(void);
int main(void)
{
APT32F102_init(); //102 initial
while(1)
{
SYSCON_IWDCNT_Reload(); //IWDT Clear
UART2_TASK();
BUS485Send_Task();
Boot_TimeOut_Task();
}
}

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#include "includes.h"
/*************************************************************/
//software delay
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void delay_nms(unsigned int t)
{
volatile unsigned int i,j ,k=0;
j = 50* t;
for ( i = 0; i < j; i++ )
{
k++;
SYSCON_IWDCNT_Reload();
}
}
void delay_nus(unsigned int t)
{
volatile unsigned int i,j ,k=0;
j = 1* t;
for ( i = 0; i < j; i++ )
{
k++;
}
}
/*************************************************************/
//GPIO Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_CONFIG(void)
{
//GPIO初始化 - 将GPIO设置为输入下拉
GPIO_DeInit();
GPIO_Init(GPIOA0,0,Intput);
GPIO_Init(GPIOA0,1,Intput);
GPIO_Init(GPIOA0,2,Intput);
GPIO_Init(GPIOA0,3,Intput);
GPIO_Init(GPIOA0,4,Intput);
GPIO_Init(GPIOA0,5,Intput);
/* PA6 - SWC ,PA7 - SWD */
GPIO_Init(GPIOA0,8,Intput);
GPIO_Init(GPIOA0,9,Intput);
GPIO_Init(GPIOA0,10,Intput);
GPIO_Init(GPIOA0,11,Intput);
GPIO_Init(GPIOA0,12,Intput);
GPIO_Init(GPIOA0,13,Intput);
GPIO_Init(GPIOA0,14,Intput);
GPIO_Init(GPIOA0,15,Intput);
GPIO_Init(GPIOB0,0,Intput);
GPIO_Init(GPIOB0,1,Intput);
GPIO_Init(GPIOB0,2,Intput);
GPIO_Init(GPIOB0,3,Intput);
// GPIO_Init(GPIOB0,4,Intput); //默认为Boot 烧录串口2
// GPIO_Init(GPIOB0,5,Intput); //默认为Boot 烧录串口2
GPIO_PullLow_Init(GPIOA0,0);
GPIO_PullLow_Init(GPIOA0,1);
GPIO_PullLow_Init(GPIOA0,2);
GPIO_PullLow_Init(GPIOA0,3);
GPIO_PullLow_Init(GPIOA0,4);
GPIO_PullLow_Init(GPIOA0,5);
GPIO_PullLow_Init(GPIOA0,8);
GPIO_PullLow_Init(GPIOA0,9);
GPIO_PullLow_Init(GPIOA0,10);
GPIO_PullLow_Init(GPIOA0,11);
GPIO_PullLow_Init(GPIOA0,12);
GPIO_PullLow_Init(GPIOA0,13);
GPIO_PullLow_Init(GPIOA0,14);
GPIO_PullLow_Init(GPIOA0,15);
GPIO_PullLow_Init(GPIOB0,0);
GPIO_PullLow_Init(GPIOB0,1);
GPIO_PullLow_Init(GPIOB0,2);
GPIO_PullLow_Init(GPIOB0,3);
// GPIO_PullLow_Init(GPIOB0,4); //默认为Boot 烧录串口2
// GPIO_PullLow_Init(GPIOB0,5); //默认为Boot 烧录串口2
}
/*************************************************************/
//BT Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_CONFIG(void)
{
//PB 保护电流PWM_CURR_LMT
// BT_DeInit(BT0);
// BT_IO_Init(BT0_PB02);
// BT_Configure(BT0,BTCLK_EN,0,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);//TCLK=PCLK/(0+1)
// BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN);
// //BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_EN,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN);
// //BT_Trigger_Configure(BT0,BT_TRGSRC_PEND,BT_TRGOE_EN);
// BT_Period_CMP_Write(BT0,50,1);
// BT_Start(BT0);
// BT_ConfigInterrupt_CMD(BT0,ENABLE,BT_PEND);
// BT0_INT_ENABLE();
//100us 定时器初始化
BT_DeInit(BT1);
BT_Configure(BT1,BTCLK_EN,0,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);
BT_ControlSet_Configure(BT1,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN);
BT_Period_CMP_Write(BT1,4780,1);
BT_Start(BT1);
BT_ConfigInterrupt_CMD(BT1,ENABLE,BT_CMP);
BT1_INT_ENABLE();
}
/*************************************************************/
//UART0 CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_CONFIG(void)
{
UART0_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART0,0); //use PA0.1->RXD0, PA0.0->TXD0
UARTInit(UART0,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200
UARTInitRxTxIntEn(UART0,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200,tx rx int enabled
UART0_Int_Enable();
}
/*************************************************************/
//UART1 CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_CONFIG(void)
{
UART1_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART1,0); //use PA0.13->RXD1, PB0.0->TXD1
UARTInit(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200
UARTInitRxTxIntEn(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled
UART1_Int_Enable();
}
/*************************************************************/
//UART2 CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_CONFIG(void)
{
UART2_DeInit(); //clear all UART Register
UART_IO_Init(IO_UART2,2); //use PA0.7->RXD2, PA0.6->TXD2
UARTInit(UART2,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200
//UARTInitRxTxIntEn(UART2,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled
//UART2_Int_Enable();
}
/*************************************************************/
//syscon Functions
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CONFIG(void)
{
//------SYSTEM CLK AND PCLK FUNTION---------------------------/
SYSCON_RST_VALUE(); //SYSCON all register clr
SYSCON_General_CMD(ENABLE,ENDIS_ISOSC); //SYSCON enable/disable clock source
//EMOSC_OSTR_Config(0XAD,0X1f,EM_LFSEL_EN,EM_FLEN_EN,EM_FLSEL_10ns); //EM_CNT=0X3FF,0xAD(36K),EM_GM=0,Low F modedisable,EM filter disable,if enable,cont set 5ns
//SYSCON_General_CMD(ENABLE,ENDIS_EMOSC);
SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_48M); //HFOSC selected 48MHz
SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_HFOSC,HCLK_DIV_1,PCLK_DIV_1,HFOSC_48M);//system clock set, Hclk div ,Pclk div set system clock=SystemCLK/Hclk div/Pclk div
//------------ WDT FUNTION --------------------------------/
SYSCON_IWDCNT_Config(IWDT_TIME_125MS,IWDT_INTW_DIV_7); //WDT TIME 1s,WDT alarm interrupt time=1s-1s*1/8=0.875S
SYSCON_WDT_CMD(ENABLE); //enable/disable WDT
SYSCON_IWDCNT_Reload(); //reload WDT
IWDT_Int_Enable();
//------------ WWDT FUNTION --------------------------------/
// WWDT_CNT_Load(0xFF);
// WWDT_CONFIG(PCLK_4096_DIV0,0xFF,WWDT_DBGDIS);
// WWDT_Int_Config(ENABLE);
//WWDT_CMD(ENABLE); //enable wwdt
//------------ CLO Output --------------------------------/
//SYSCON_CLO_CONFIG(CLO_PA08); //CLO output setting
//SYSCON_CLO_SRC_SET(CLO_HFCLK,CLO_DIV16); //CLO output clock and div
//------------ LVD FUNTION --------------------------------/
SYSCON_LVD_Config(ENABLE_LVDEN,INTDET_LVL_3_9V,RSTDET_LVL_1_9V,ENABLE_LVD_INT,INTDET_POL_fall); //LVD LVR Enable/Disable
LVD_Int_Enable();
//------------ SYSCON Vector --------------------------------/
SYSCON_Int_Enable(); //SYSCON VECTOR
//SYSCON_WakeUp_Enable(); //Enable WDT wakeup INT
//------------------------------------------------------------/
//OSC CLOCK Calibration
//------------------------------------------------------------/
std_clk_calib(CLK_HFOSC_48M); //Select the same clock source as the system
}
/*********************************************************************************/
/*********************************************************************************/
//APT32F102_init /
//EntryParameter:NONE /
//ReturnValue:NONE /
/*********************************************************************************/
void APT32F102_init(void)
{
//------------------------------------------------------------/
//Peripheral clock enable and disable
//EntryParameter:NONE
//ReturnValue:NONE
//------------------------------------------------------------/
SYSCON->PCER0=0xFFFFFFF; //PCLK Enable
SYSCON->PCER1=0xFFFFFFF; //PCLK Enable
while(!(SYSCON->PCSR0&0x1)); //Wait PCLK enabled
//------------------------------------------------------------/
//ISOSC/IMOSC/EMOSC/SYSCLK/IWDT/LVD/EM_CMFAIL/EM_CMRCV/CMD_ERR OSC stable interrupt
//EntryParameter:NONE
//ReturnValue:NONE
//------------------------------------------------------------/
SYSCON_CONFIG(); //syscon initial
CK_CPU_EnAllNormalIrq(); //enable all IRQ
SYSCON_INT_Priority(); //initial all Priority=0xC0
//设置中断优先级 0最高，3最低
Set_INT_Priority(UART2_IRQ,1); //串口优先级最高
GPIO_CONFIG();
BT_CONFIG(); //BT initial
// UARTx_Init(UART_1,Boot_Comm_UpgradeProcess);
UARTx_Init(UART_2,Boot_Comm_UpgradeProcess); //通讯串口
Boot_Function_Init();
}
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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#include "includes.h"
/****************************************************
//define
*****************************************************/
volatile int R_CMPA_BUF,R_CMPB_BUF;
//volatile int R_SIOTX_count,R_SIORX_count;
volatile int R_SIORX_buf[10];
/****************************************************
//extern
*****************************************************/
extern void delay_nms(unsigned int t);
/*************************************************************/
//CORET Interrupt
//If you use a touch library file that does not contain coret
//you need to open this interrupt entry
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
//void CORETHandler(void)
//{
// // ISR content ...
//}
/*************************************************************/
//SYSCON Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCONIntHandler(void)
{
// ISR content ...
nop;
if((SYSCON->MISR&ISOSC_ST)==ISOSC_ST) //ISOSC stable interrupt
{
SYSCON->ICR = ISOSC_ST;
}
else if((SYSCON->MISR&IMOSC_ST)==IMOSC_ST) //IMOSC stable interrupt
{
SYSCON->ICR = IMOSC_ST;
}
else if((SYSCON->MISR&EMOSC_ST)==EMOSC_ST) //EMOSC stable interrupt
{
SYSCON->ICR = EMOSC_ST;
}
else if((SYSCON->MISR&HFOSC_ST)==HFOSC_ST) //HFOSC stable interrupt
{
SYSCON->ICR = HFOSC_ST;
}
else if((SYSCON->MISR&SYSCLK_ST)==SYSCLK_ST) //SYSCLK change end & stable interrupt
{
SYSCON->ICR = SYSCLK_ST;
}
else if((SYSCON->MISR&IWDT_INT_ST)==IWDT_INT_ST) //IWDT alarm window interrupt
{
SYSCON->ICR = IWDT_INT_ST;
// SYSCON->IWDCNT=0x5aul<<24;
}
else if((SYSCON->MISR&WKI_INT_ST)==WKI_INT_ST)
{
SYSCON->ICR = WKI_INT_ST;
}
else if((SYSCON->MISR&RAMERRINT_ST)==RAMERRINT_ST) //SRAM check fail interrupt
{
SYSCON->ICR = RAMERRINT_ST;
}
else if((SYSCON->MISR&LVD_INT_ST)==LVD_INT_ST) //LVD threshold interrupt
{
nop;
SYSCON->ICR = LVD_INT_ST;
}
else if((SYSCON->MISR&HWD_ERR_ST)==HWD_ERR_ST) //Hardware Divider divisor = 0 interrupt
{
SYSCON->ICR = HWD_ERR_ST;
}
else if((SYSCON->MISR&EFL_ERR_ST)==EFL_ERR_ST) //Flash check fail interrupt
{
SYSCON->ICR = EFL_ERR_ST;
}
else if((SYSCON->MISR&OPTERR_INT)==OPTERR_INT) //Option load fail interrupt
{
SYSCON->ICR = OPTERR_INT;
}
else if((SYSCON->MISR&EM_CMLST_ST)==EM_CMLST_ST) //EMOSC clock monitor fail interrupt
{
SYSCON->ICR = EM_CMLST_ST;
}
else if((SYSCON->MISR&EM_EVTRG0_ST)==EM_EVTRG0_ST) //Event Trigger Channel 0 Interrupt
{
SYSCON->ICR = EM_EVTRG0_ST;
}
else if((SYSCON->MISR&EM_EVTRG1_ST)==EM_EVTRG1_ST) //Event Trigger Channel 1 Interrupt
{
SYSCON->ICR = EM_EVTRG1_ST;
}
else if((SYSCON->MISR&EM_EVTRG2_ST)==EM_EVTRG2_ST) //Event Trigger Channel 2 Interrupt
{
SYSCON->ICR = EM_EVTRG2_ST;
}
else if((SYSCON->MISR&EM_EVTRG3_ST)==EM_EVTRG3_ST) //Event Trigger Channel 3 Interrupt
{
SYSCON->ICR = EM_EVTRG3_ST;
}
else if((SYSCON->MISR&CMD_ERR_ST)==CMD_ERR_ST) //Command error interrupt
{
SYSCON->ICR = CMD_ERR_ST;
}
}
/*************************************************************/
//IFC Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFCIntHandler(void)
{
// ISR content ...
if(IFC->MISR&ERS_END_INT)
{
IFC->ICR=ERS_END_INT;
}
else if(IFC->MISR&RGM_END_INT)
{
IFC->ICR=RGM_END_INT;
}
else if(IFC->MISR&PEP_END_INT)
{
IFC->ICR=PEP_END_INT;
}
else if(IFC->MISR&PROT_ERR_INT)
{
IFC->ICR=PROT_ERR_INT;
}
else if(IFC->MISR&UDEF_ERR_INT)
{
IFC->ICR=UDEF_ERR_INT;
}
else if(IFC->MISR&ADDR_ERR_INT)
{
IFC->ICR=ADDR_ERR_INT;
}
else if(IFC->MISR&OVW_ERR_INT)
{
IFC->ICR=OVW_ERR_INT;
}
}
/*************************************************************/
//EPT0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT0IntHandler(void)
{
// ISR content ...
// if((EPT0->MISR&EPT_TRGEV0_INT)==EPT_TRGEV0_INT) //TRGEV0 interrupt
// {
// EPT0->ICR=EPT_TRGEV0_INT;
// }
// else if((EPT0->MISR&EPT_TRGEV1_INT)==EPT_TRGEV1_INT) //TRGEV1 interrupt
// {
// EPT0->ICR=EPT_TRGEV1_INT;
// }
// else if((EPT0->MISR&EPT_TRGEV2_INT)==EPT_TRGEV2_INT) //TRGEV2 interrupt
// {
// EPT0->ICR=EPT_TRGEV2_INT;
// }
// else if((EPT0->MISR&EPT_TRGEV3_INT)==EPT_TRGEV3_INT) //TRGEV3 interrupt
// {
// EPT0->ICR=EPT_TRGEV3_INT;
// }
// else if((EPT0->MISR&EPT_CAP_LD0)==EPT_CAP_LD0) //Capture Load to CMPA interrupt
// {
// EPT0->ICR=EPT_CAP_LD0;
// EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIRT);
// EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT);
// R_CMPA_BUF=EPT0->CMPA; //Low voltage counter
// }
// else if((EPT0->MISR&EPT_CAP_LD1)==EPT_CAP_LD1) //Capture Load to CMPB interrupt
// {
// EPT0->ICR=EPT_CAP_LD1;
// EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIRT);
// EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT);
// R_CMPB_BUF=EPT0->CMPB; //Duty counter
// }
// else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2) //Capture Load to CMPC interrupt
// {
// EPT0->ICR=EPT_CAP_LD2;
// }
// else if((EPT0->MISR&EPT_CAP_LD3)==EPT_CAP_LD3) //Capture Load to CMPD interrupt
// {
// EPT0->ICR=EPT_CAP_LD3;
// }
// else if((EPT0->MISR&EPT_CAU)==EPT_CAU) //Up-Counting phase CNT = CMPA interrupt
// {
// EPT0->ICR=EPT_CAU;
// }
// else if((EPT0->MISR&EPT_CAD)==EPT_CAD) //Down-Counting phase CNT = CMPA interrupt
// {
// EPT0->ICR=EPT_CAD;
// }
// else if((EPT0->MISR&EPT_CBU)==EPT_CBU) //Up-Counting phase CNT = CMPB interrupt
// {
// EPT0->ICR=EPT_CBU;
// }
// else if((EPT0->MISR&EPT_CBD)==EPT_CBD) //Down-Counting phase CNT = CMPB interrupt
// {
// EPT0->ICR=EPT_CBD;
// }
// else if((EPT0->MISR&EPT_CCU)==EPT_CCU) //Up-Counting phase CNT = CMPC interrupt
// {
// EPT0->ICR=EPT_CCU;
// }
// else if((EPT0->MISR&EPT_CCD)==EPT_CCD) //Down-Counting phase CNT = CMPC interrupt
// {
// EPT0->ICR=EPT_CCD;
// }
// else if((EPT0->MISR&EPT_CDU)==EPT_CDU) //Up-Counting phase CNT = CMPD interrupt
// {
// EPT0->ICR=EPT_CDU;
// }
// else if((EPT0->MISR&EPT_CDD)==EPT_CDD) //Down-Counting phase CNT = CMPD interrupt
// {
// EPT0->ICR=EPT_CDD;
// }
// else if((EPT0->MISR&EPT_PEND)==EPT_PEND) //End of cycle interrupt
// {
// EPT0->ICR=EPT_PEND;
// //EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(50,0,50,0,0);
// EPT_Stop();
// }
// //Emergency interruption
// if((EPT0->EMMISR&EPT_EP0_EMINT)==EPT_EP0_EMINT) //interrupt flag of EP0 event
// {
// EPT0->EMICR=EPT_EP0_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP1_EMINT)==EPT_EP1_EMINT) //interrupt flag of EP1 event
// {
// EPT0->EMICR=EPT_EP1_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP2_EMINT)==EPT_EP2_EMINT) //interrupt flag of EP2 event
// {
// EPT0->EMICR=EPT_EP2_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP3_EMINT)==EPT_EP3_EMINT) //interrupt flag of EP3 event
// {
// EPT0->EMICR=EPT_EP3_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP4_EMINT)==EPT_EP4_EMINT) //interrupt flag of EP4 event
// {
// EPT0->EMICR=EPT_EP4_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP5_EMINT)==EPT_EP5_EMINT) //interrupt flag of EP5 event
// {
// EPT0->EMICR=EPT_EP5_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT) //interrupt flag of EP6 event
// {
// EPT0->EMICR=EPT_EP6_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EP7_EMINT)==EPT_EP7_EMINT) //interrupt flag of EP7 event
// {
// EPT0->EMICR=EPT_EP7_EMINT;
// }
// else if((EPT0->EMMISR&EPT_CPU_FAULT_EMINT)==EPT_CPU_FAULT_EMINT) //interrupt flag of CPU_FAULT event
// {
// EPT0->EMICR=EPT_CPU_FAULT_EMINT;
// }
// else if((EPT0->EMMISR&EPT_MEM_FAULT_EMINT)==EPT_MEM_FAULT_EMINT) //interrupt flag of MEM_FAULT event
// {
// EPT0->EMICR=EPT_MEM_FAULT_EMINT;
// }
// else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT) //interrupt flag of EOM_FAULT event
// {
// EPT0->EMICR=EPT_EOM_FAULT_EMINT;
// }
}
/*************************************************************/
//WWDT Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDTHandler(void)
{
WWDT->ICR=0X01;
WWDT_CNT_Load(0xFF);
if((WWDT->MISR&WWDT_EVI)==WWDT_EVI) //WWDT EVI interrupt
{
WWDT->ICR = WWDT_EVI;
}
}
/*************************************************************/
//GPT0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT0IntHandler(void)
{
// ISR content ...
// if((GPT0->MISR&GPT_INT_TRGEV0)==GPT_INT_TRGEV0) //TRGEV0 interrupt
// {
// GPT0->ICR = GPT_INT_TRGEV0;
// }
// else if((GPT0->MISR&GPT_INT_TRGEV1)==GPT_INT_TRGEV1) //TRGEV1 interrupt
// {
// GPT0->ICR = GPT_INT_TRGEV1;
// }
// else if((GPT0->MISR&GPT_INT_CAPLD0)==GPT_INT_CAPLD0) //Capture Load to CMPA interrupt
// {
// GPT0->ICR = GPT_INT_CAPLD0;
// }
// else if((GPT0->MISR&GPT_INT_CAPLD1)==GPT_INT_CAPLD1) //Capture Load to CMPB interrupt
// {
// GPT0->ICR = GPT_INT_CAPLD1;
// }
// else if((GPT0->MISR&GPT_INT_CAU)==GPT_INT_CAU) //Up-Counting phase CNT = CMPA Interrupt
// {
// GPT0->ICR = GPT_INT_CAU;
// }
// else if((GPT0->MISR&GPT_INT_CAD)==GPT_INT_CAD) //Down-Counting phase CNT = CMPA Interrupt
// {
// GPT0->ICR = GPT_INT_CAD;
// }
// else if((GPT0->MISR&GPT_INT_CBU)==GPT_INT_CBU) //Up-Counting phase CNT = CMPB Interrupt
// {
// GPT0->ICR = GPT_INT_CBU;
// }
// else if((GPT0->MISR&GPT_INT_CBD)==GPT_INT_CBD) //Down-Counting phase CNT = CMPB Interrupt
// {
// GPT0->ICR = GPT_INT_CBD;
// }
// else if((GPT0->MISR&GPT_INT_PEND)==GPT_INT_PEND) //End of cycle interrupt
// {
// GPT0->ICR = GPT_INT_PEND;
// }
}
/*************************************************************/
//UART0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0IntHandler(void)
{
char inchar = 0;
// ISR content ...
if ((UART0->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
{
UART0->ISR=UART_RX_INT_S;
// inchar = CSP_UART_GET_DATA(UART0);
// UARTTxByte(UART0,inchar);
}
else if( (UART0->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
{
UART0->ISR=UART_TX_INT_S;
//TxDataFlag = TRUE;
}
else if ((UART0->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
{
UART0->ISR=UART_RX_IOV_S;
}
else if ((UART0->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
{
UART0->ISR=UART_TX_IOV_S;
}
}
/*************************************************************/
//UART1 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1IntHandler(void)
{
char inchar = 0;
// ISR content ...
if ((UART1->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
{
UART1->ISR=UART_RX_INT_S;
// inchar = CSP_UART_GET_DATA(UART1);
// UART1_RecvINT_Processing(inchar);
}
else if( (UART1->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
{
UART1->ISR=UART_TX_INT_S;
// RS485_Comming = 0x01;
//
// if(RS485_Comm_Flag == 0x01){
// RS485_Comm_Start ++;
// }
}
else if ((UART1->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
{
UART1->ISR=UART_RX_IOV_S;
}
else if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
{
UART1->ISR=UART_TX_IOV_S;
}
else if ((UART1->ISR&UART_TX_DONE_S)==UART_TX_DONE_S)
{
UART1->ISR=UART_TX_DONE_S;
// RS485_Comming = 0x00;
// if(RS485_Comm_Flag == 0x01){
// RS485_Comm_End ++;
// }
}
}
/*************************************************************/
//UART2 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2IntHandler(void)
{
char inchar = 0;
// ISR content ...
if ((UART2->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
{
UART2->ISR=UART_RX_INT_S;
inchar = CSP_UART_GET_DATA(UART2);
UART2_RecvINT_Processing(inchar);
}
else if( (UART2->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
{
UART2->ISR=UART_TX_INT_S;
RS485_Comming = 0x01;
if(RS485_Comm_Flag == 0x01){
RS485_Comm_Start ++;
}
}
else if ((UART2->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
{
UART2->ISR=UART_RX_IOV_S;
}
else if ((UART2->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
{
UART2->ISR=UART_TX_IOV_S;
}
else if ((UART2->ISR&UART_TX_DONE_S)==UART_TX_DONE_S)
{
UART2->ISR=UART_TX_DONE_S;
RS485_Comming = 0x00;
if(RS485_Comm_Flag == 0x01){
RS485_Comm_End ++;
}
}
}
/*************************************************************/
//I2C Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2CIntHandler(void)
{
// ISR content ...
//I2C_Slave_Receive(); //I2C slave receive function in interruption
}
/*************************************************************/
//SIO Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO0IntHandler(void)
{
// ISR content ...
//The sequence is more than 16bit to send the program
//1.disable interrupt in main loop 2.set the highest priority in the interrupt
/*CK801->IPR[0]=0X40404040;
CK801->IPR[1]=0X40404040;
CK801->IPR[2]=0X40404040;
CK801->IPR[3]=0X40404040;
CK801->IPR[4]=0X40404040;
CK801->IPR[5]=0X40404000;
CK801->IPR[6]=0X40404040;
CK801->IPR[7]=0X40404040;*/
//TXBUFEMPT The sequence length exceeds 15bit needs to be updated into this interrupt
if(SIO0->MISR&0X04)
{
SIO0->ICR=0X04;
}
if(SIO0->MISR&0X01) //TXDNE 发送完成
{
SIO0->ICR=0X01;
//SIO0->TXBUF=0x00; //0:D0,1:D1,2:DL,3:DH;
//INTC_ICER_WRITE(SIO_INT);
}
//The sequence is less than 16bit to send the program
/*if(SIO0->MISR&0X01) //TXDNE
{
SIO0->ICR=0X01;
delay_nms(10);
SIO0->TXBUF=(0x03<<30)|(0x02<<28)|(0x03<<26)|(0x02<<24)|(0x03<<22)|(0x02<<20)|(0x03<<18)|(0x02<<16)|
(0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x00<<4)|(0x01<<2)|(0x0<<0); //0:D0,1:D1,2:DL,3:DH;
}*/
if(SIO0->MISR&0X02) //RXDNE
{
SIO0->ICR=0X02;
// if(R_SIORX_count>=1)
// {
// R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF&0xff000000; //8bit
// nop;
// R_SIORX_count=0;
// }
}
else if(SIO0->MISR&0X08) //RXBUFFULL
{
SIO0->ICR=0X08;
// if(R_SIORX_count<1)
// {
// R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF; //32bit
// R_SIORX_count++;
// }
}
else if(SIO0->MISR&0X010) //BREAK
{
SIO0->ICR=0X10;
}
else if(SIO0->MISR&0X020) //TIMEOUT
{
SIO0->ICR=0X20;
}
}
/*************************************************************/
//EXT0/16 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0IntHandler(void)
{
// ISR content ...
if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0) //EXT0 Interrupt
{
SYSCON->EXICR = EXI_PIN0;
}
else if ((SYSCON->EXIRS&EXI_PIN16)==EXI_PIN16) //EXT16 Interrupt
{
SYSCON->EXICR = EXI_PIN16;
}
}
/*************************************************************/
//EXT1/17 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1IntHandler(void)
{
// ISR content ...
if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1) //EXT1 Interrupt
{
SYSCON->EXICR = EXI_PIN1;
}
else if ((SYSCON->EXIRS&EXI_PIN17)==EXI_PIN17) //EXT17 Interrupt
{
SYSCON->EXICR = EXI_PIN17;
}
}
/*************************************************************/
//EXI2~3 18~19Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2to3IntHandler(void)
{
// ISR content ...
if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2) //EXT2 Interrupt
{
SYSCON->EXICR = EXI_PIN2;
}
else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) //EXT3 Interrupt
{
SYSCON->EXICR = EXI_PIN3;
}
else if ((SYSCON->EXIRS&EXI_PIN18)==EXI_PIN18) //EXT18 Interrupt
{
SYSCON->EXICR = EXI_PIN18;
}
else if ((SYSCON->EXIRS&EXI_PIN19)==EXI_PIN19) //EXT19 Interrupt
{
SYSCON->EXICR = EXI_PIN19;
}
}
/*************************************************************/
//EXI4~9 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4to9IntHandler(void)
{
// ISR content ...
if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4) //EXT4 Interrupt
{
SYSCON->EXICR = EXI_PIN4;
}
else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5) //EXT5 Interrupt
{
SYSCON->EXICR = EXI_PIN5;
BusBusy_Task();
}
else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) //EXT6 Interrupt
{
SYSCON->EXICR = EXI_PIN6;
}
else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7) //EXT7 Interrupt
{
SYSCON->EXICR = EXI_PIN7;
}
else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8) //EXT8 Interrupt
{
SYSCON->EXICR = EXI_PIN8;
}
else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) //EXT9 Interrupt
{
SYSCON->EXICR = EXI_PIN9;
}
}
/*************************************************************/
//EXI4 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI10to15IntHandler(void)
{
// ISR content ...
if ((SYSCON->EXIRS&EXI_PIN10)==EXI_PIN10) //EXT10 Interrupt
{
SYSCON->EXICR = EXI_PIN10;
}
else if ((SYSCON->EXIRS&EXI_PIN11)==EXI_PIN11) //EXT11 Interrupt
{
SYSCON->EXICR = EXI_PIN11;
}
else if ((SYSCON->EXIRS&EXI_PIN12)==EXI_PIN12) //EXT12 Interrupt
{
SYSCON->EXICR = EXI_PIN12;
}
else if ((SYSCON->EXIRS&EXI_PIN13)==EXI_PIN13) //EXT13 Interrupt
{
SYSCON->EXICR = EXI_PIN13;
}
else if ((SYSCON->EXIRS&EXI_PIN14)==EXI_PIN14) //EXT14 Interrupt
{
SYSCON->EXICR = EXI_PIN14;
}
else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) //EXT15 Interrupt
{
SYSCON->EXICR = EXI_PIN15;
}
}
/*************************************************************/
//CONTA Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CNTAIntHandler(void)
{
// ISR content ...
}
/*************************************************************/
//LPT Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPTIntHandler(void)
{
// ISR content ...
// if((LPT->MISR&LPT_TRGEV0)==LPT_TRGEV0) //TRGEV0 interrupt
// {
// LPT->ICR = LPT_TRGEV0;
// }
// else if((LPT->MISR&LPT_MATCH)==LPT_MATCH) //MATCH interrupt
// {
// LPT->ICR = LPT_MATCH;
// }
// else if((LPT->MISR&LPT_PEND)==LPT_PEND) //PEND interrupt
// {
// LPT->ICR = LPT_PEND;
// }
}
/*************************************************************/
//BT0 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T BT_TEMP_State = 1;
void BT0IntHandler(void)
{
// ISR content ...
if((BT0->MISR&BT_PEND)==BT_PEND) //BT0 PEND interrupt
{
BT0->ICR = BT_PEND;
//BT_Stop_Low(BT0);
BT0->CR =BT0->CR & ~(0x01<<6);
BT0->RSSR &=0X0;
}
else if((BT0->MISR&BT_CMP)==BT_CMP) //BT0 CMP Match interrupt
{
BT0->ICR = BT_CMP;
}
else if((BT0->MISR&BT_OVF)==BT_OVF) //BT0 OVF interrupt
{
BT0->ICR = BT_OVF;
}
else if((BT0->MISR&BT_EVTRG)==BT_EVTRG) //BT0 Event trigger interrupt
{
BT0->ICR = BT_EVTRG;
}
}
volatile U32_T SysTick_100us = 0;
volatile U32_T SysTick_1ms = 0;
/*************************************************************/
//BT1 Interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT1IntHandler(void)
{
static U8_T NUM = 0;
// ISR content ...
if((BT1->MISR&BT_PEND)==BT_PEND) //BT1 PEND interrupt
{
BT1->ICR = BT_PEND;
}
else if((BT1->MISR&BT_CMP)==BT_CMP) //BT1 CMP Match interrupt
{
BT1->ICR = BT_CMP;
NUM++;
SysTick_100us++;
if(NUM >= 10){
NUM = 0;
SysTick_1ms++;
BusIdle_Task();
}
}
else if((BT1->MISR&BT_OVF)==BT_OVF) //BT1 OVF interrupt
{
BT1->ICR = BT_OVF;
}
else if((BT1->MISR&BT_EVTRG)==BT_EVTRG) //BT1 Event trigger interrupt
{
BT1->ICR = BT_EVTRG;
}
}
/*************************************************************/
/*************************************************************/
/*************************************************************/
//void TKEYIntHandler(void)
//{
// // ISR content ...
//
//}
void PriviledgeVioHandler(void)
{
// ISR content ...
}
void SystemDesPtr(void)
{
// ISR content ...
}
void MisalignedHandler(void)
{
// ISR content ...
}
void IllegalInstrHandler(void)
{
// ISR content ...
}
void AccessErrHandler(void)
{
// ISR content ...
}
void BreakPointHandler(void)
{
// ISR content ...
}
void UnrecExecpHandler(void)
{
// ISR content ...
}
void Trap0Handler(void)
{
// ISR content ...
}
void Trap1Handler(void)
{
// ISR content ...
}
void Trap2Handler(void)
{
// ISR content ...
}
void Trap3Handler(void)
{
// ISR content ...
}
void PendTrapHandler(void)
{
// ISR content ...
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/