146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
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/*
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******************************************************************************
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* @file apt32f102.c
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* @author APT AE Team
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* @version V1.01
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* @date 2019/04/05
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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/**
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* @addtogroup Struct pointer assignment Functions
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* @{
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*/
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CSP_CK801_T *CK801 = (CSP_CK801_T *)CK801_BASEADDR ;
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CSP_IFC_T *IFC = (CSP_IFC_T *)APB_IFCBase ;
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CSP_SYSCON_T *SYSCON = (CSP_SYSCON_T *)APB_SYSCONBase ;
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CSP_TKEY_T *TKEY = (CSP_TKEY_T *)APB_TKEYBase ;
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CSP_TKEYBUF_T *TKEYBUF = (CSP_TKEYBUF_T *)APB_TKEYBUFBase;
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CSP_ADC12_T *ADC0 = (CSP_ADC12_T *)APB_ADC0Base ;
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CSP_GPIO_T *GPIOA0 = (CSP_GPIO_T *)APB_GPIOA0Base ; // A0
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CSP_GPIO_T *GPIOB0 = (CSP_GPIO_T *)APB_GPIOB0Base ; // B0
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CSP_IGRP_T *GPIOGRP = (CSP_IGRP_T *)APB_IGRPBase;
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CSP_UART_T *UART0 = (CSP_UART_T *)APB_UART0Base ;
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CSP_UART_T *UART1 = (CSP_UART_T *)APB_UART1Base ;
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CSP_UART_T *UART2 = (CSP_UART_T *)APB_UART2Base ;
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CSP_SSP_T *SPI0 = (CSP_SSP_T *)APB_SPI0Base ;
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CSP_I2C_T *I2C0 = (CSP_I2C_T *)APB_I2C0Base ;
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CSP_SIO_T *SIO0 = (CSP_SIO_T *)APB_SIO0Base ;
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CSP_CA_T *CA0 = (CSP_CA_T *)APB_CNTABase ;
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CSP_GPT_T *GPT0 = (CSP_GPT_T *)APB_GPT0Base;
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CSP_EPT_T *EPT0 = (CSP_EPT_T *)APB_EPT0Base ;
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CSP_ETCB_T *ETCB = (CSP_ETCB_T *)APB_ETCBBase ;
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CSP_RTC_T *RTC = (CSP_RTC_T *)APB_RTCBase ;
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CSP_LPT_T *LPT = (CSP_LPT_T *)APB_LPTBase ;
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CSP_WWDT_T *WWDT = (CSP_WWDT_T *)APB_WWDTBase ;
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CSP_BT_T *BT0 = (CSP_BT_T *)APB_BT0Base ;
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CSP_BT_T *BT1 = (CSP_BT_T *)APB_BT1Base ;
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CSP_CRC_T *CRC = (CSP_CRC_T *)AHB_CRCBase ;
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CSP_HWD_T *HWD = (CSP_HWD_T *)APB_HWDBase ;
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int __divsi3 ( int a, int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 0;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->QUOTIENT;
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}
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unsigned int __udivsi3 ( unsigned int a, unsigned int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 1;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->QUOTIENT;
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}
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int __modsi3 ( int a, int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 0;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->REMAIN;
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}
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unsigned int __umodsi3 ( unsigned int a, unsigned int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 1;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->REMAIN;
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}
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/
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