commit f25132cbe3820e1588d1847166bddb5bcc60a4b0 Author: yanghongfeng Date: Mon Jan 19 15:32:11 2026 +0800 修复开关控制组控的控制异常问题 修改PB开关状态组控处理，解决后32路的开关状态会复用上前32个回路的数据 diff --git a/FLASHDOWN/APT32F102_FLASHDOWN.elf b/FLASHDOWN/APT32F102_FLASHDOWN.elf new file mode 100644 index 0000000..1472d1d Binary files /dev/null and b/FLASHDOWN/APT32F102_FLASHDOWN.elf differ diff --git a/Readme.txt b/Readme.txt new file mode 100644 index 0000000..4d94020 --- /dev/null +++ b/Readme.txt @@ -0,0 +1,65 @@ +2026-01-17 + 发布文件版本：V07 + 修改PB空格状态群控处理，解决后32路的开关状态会复用上前32个回路的数据 + +2024-07-04 + 发布文件版本：V06 + 初步测试没问题 + +2024-07-02 + 增加PB - LS 相对调节命令 + 修改灯带控制 - 在灯带不管开关状态，循环调光控制状态下，亮度值还是变化的，但是实际输出根据开关状态与当前亮度来判断 + +2024-06-17 软件版本发布文件: V03 + 1ms定时器中调节PWM非常耗时，导致串口接收中断被抢占，接收数据不对，导致主机下发数据无法响应 + 解决方式：PWM调节使用另外一个优先级较低的定时器中断控制 + +2024-05-29 软件版本发布文件：V02 + + 修改PB PS输入电源检测 范围为10~38V电压，之前只有判定输入电压下限，没有上限判定 + +2024-04-10 + 1、修改PB总线软启动时间 5S 改为 3S + +2024-04-01 + 1、修改PB总线发送，中断方式发送数据 + 2、解决EEPROM中恢复默认参数时可调上限为零的问题 + +2024-03-22 + 修改PB通讯协议 + 保存PB参数，上电时将PB参数同步 + +2024-01-03 + 修改 调光控制步进方式 - 步进值改为浮点数 + 修改 调光自动调节，不能停止调光问题、无法取反调节控制问题 + +2023-11-13 + 修改通讯协议 + +2023-11-11 + 新功能，增加空闲发送心跳包，设备端一段时间内没有接收到数据便自动关闭灯光 + +2023-10-31 + 增加PIR自动感应功能 +2023-10-23 + 增加串口命令 +2023-10-20 更换PB20通讯协议 + 在测试灯的时候需要先将全局亮度调节至100%，在开关否则检测灯的电流将不对 + + PB BUS自检 + + 1、关闭全部灯 - + 读取回来的电流小于某个值，便认为全关 + 2、将全局亮度设置为100%，渐变时间为0 + + 3、开启第一个灯 + 读取电流 + 关闭第一灯，开第二个灯 + 读取电流 + 。。。。。 + + 协议上问题点： + 之前协议中单回路上0x00,表示该参数对全部回路都有效 现在是否也同样使用 + + 00 01 30 01 07 00 20 + \ No newline at end of file diff --git a/Source/.cache/.cache/clangd/index/ansidef.h.8DC9EC4A871FC34A.idx b/Source/.cache/.cache/clangd/index/ansidef.h.8DC9EC4A871FC34A.idx new file mode 100644 index 0000000..c99a7a3 Binary files /dev/null and b/Source/.cache/.cache/clangd/index/ansidef.h.8DC9EC4A871FC34A.idx differ diff --git a/Source/.cache/.cache/clangd/index/apt32f102.c.1FBA865D43C96F2B.idx b/Source/.cache/.cache/clangd/index/apt32f102.c.1FBA865D43C96F2B.idx new file mode 100644 index 0000000..edbbfc6 Binary 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"-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/include/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-Iinclude", "-include", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\drivers\\apt32f102_ck801.c", "-o", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\drivers\\apt32f102_ck801.o"] + }, { + "file": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\uart.c", + "directory": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source", + "arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/include/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-Iinclude", "-include", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\uart.c", "-o", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\uart.o"] + }, { + "file": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pb_fun.c", + "directory": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source", + "arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/include/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-Iinclude", "-include", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pb_fun.c", "-o", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pb_fun.o"] + }, { + "file": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pwm.c", + "directory": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source", + "arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/include/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-Iinclude", "-include", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pwm.c", "-o", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\pwm.o"] + }, { + "file": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\eeprom.c", + "directory": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source", + "arguments": ["csky-elfabiv2-gcc", "-nostdlibinc", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "-isystem", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_core/include/", "-I../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/", "-I.", "-ISYSTEM/inc", "-Iinclude", "-include", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache\\macro.h", "-DCONFIG_CSKY_MMU=0", "-U__CSKY_ABIV2__", "-c", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\eeprom.c", "-o", "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\SYSTEM\\eeprom.o"] + }] \ No newline at end of file diff --git a/Source/.cache/macro.h b/Source/.cache/macro.h new file mode 100644 index 0000000..1c2239e --- /dev/null +++ b/Source/.cache/macro.h @@ -0,0 +1,200 @@ +#define __HQ_FBIT__ 15 +#define __SFRACT_IBIT__ 0 +#define __FLT_MIN__ 1.1754943508222875e-38F +#define __GCC_IEC_559_COMPLEX 0 +#define __UFRACT_MAX__ 0XFFFFP-16UR +#define __DQ_FBIT__ 63 +#define __ULFRACT_FBIT__ 32 +#define __SACCUM_EPSILON__ 0x1P-7HK +#define __CK801__ 1 +#define __USQ_IBIT__ 0 +#define __ACCUM_FBIT__ 15 +#define __WINT_MAX__ 0xffffffffU +#define __USFRACT_FBIT__ 8 +#define __WCHAR_MAX__ 0x7fffffffL +#define __LACCUM_IBIT__ 32 +#define __DBL_DENORM_MIN__ ((double)4.9406564584124654e-324L) +#define __GCC_ATOMIC_CHAR_LOCK_FREE 1 +#define __GCC_IEC_559 0 +#define __csky_soft_float__ 1 +#define __FLT_EVAL_METHOD__ 0 +#define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK +#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1 +#define __FRACT_FBIT__ 15 +#define __UACCUM_FBIT__ 16 +#define __LFRACT_IBIT__ 0 +#define __LFRACT_MAX__ 0X7FFFFFFFP-31LR +#define __UINT_FAST8_MAX__ 0xffffffffU +#define __cskyabi__ 2 +#define __SA_FBIT__ 15 +#define __LDBL_MAX__ 1.7976931348623157e+308L +#define __FRACT_MAX__ 0X7FFFP-15R +#define __cskyLE__ 1 +#define __UFRACT_FBIT__ 16 +#define __UFRACT_MIN__ 0.0UR +#define __GCC_ATOMIC_BOOL_LOCK_FREE 1 +#define __LLFRACT_EPSILON__ 0x1P-63LLR +#define __CHAR_UNSIGNED__ 1 +#define __UINT32_MAX__ 0xffffffffUL +#define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR +#define __TA_IBIT__ 64 +#define __LDBL_MAX_EXP__ 1024 +#define __WINT_MIN__ 0U +#define __CSKY_REQUIRED_SCANF__ 1 +#define __ULLFRACT_MIN__ 0.0ULLR +#define __WCHAR_MIN__ (-__WCHAR_MAX__ - 1) +#define __GCC_ATOMIC_POINTER_LOCK_FREE 1 +#define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK) +#define __USACCUM_IBIT__ 8 +#define __LFRACT_MIN__ (-0.5LR-0.5LR) +#define __HA_IBIT__ 8 +#define __TQ_IBIT__ 0 +#define __FLT_EPSILON__ 1.1920928955078125e-7F +#define __USFRACT_IBIT__ 0 +#define __LDBL_MIN__ 2.2250738585072014e-308L +#define __FRACT_MIN__ (-0.5R-0.5R) +#define __DA_IBIT__ 32 +#define __INT32_MAX__ 0x7fffffffL +#define __UQQ_FBIT__ 8 +#define __UACCUM_MAX__ 0XFFFFFFFFP-16UK +#define __DECIMAL_DIG__ 17 +#define __LFRACT_EPSILON__ 0x1P-31LR +#define __ULFRACT_MIN__ 0.0ULR +#define __ULACCUM_IBIT__ 32 +#define __UACCUM_EPSILON__ 0x1P-16UK +#define __GNUC__ 6 +#define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK +#define __HQ_IBIT__ 0 +#define __SIZEOF_LONG_DOUBLE__ 8 +#define __BIGGEST_ALIGNMENT__ 4 +#define __DQ_IBIT__ 0 +#define __DBL_MAX__ ((double)1.7976931348623157e+308L) +#define __ULFRACT_IBIT__ 0 +#define __cskyle__ 1 +#define __ACCUM_IBIT__ 16 +#define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK +#define __INT_FAST16_TYPE__ int +#define __INT_LEAST32_MAX__ 0x7fffffffL +#define __USING_SJLJ_EXCEPTIONS__ 1 +#define __ACCUM_MAX__ 0X7FFFFFFFP-15K +#define __USACCUM_EPSILON__ 0x1P-8UHK +#define __SFRACT_MAX__ 0X7FP-7HR +#define __FRACT_IBIT__ 0 +#define __UACCUM_MIN__ 0.0UK +#define __CSKY_SOFT_FLOAT__ 1 +#define __UACCUM_IBIT__ 16 +#define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK +#define __SIZEOF_WINT_T__ 4 +#define __SA_IBIT__ 16 +#define __ULLACCUM_MIN__ 0.0ULLK +#define __GXX_ABI_VERSION 1010 +#define __UTA_FBIT__ 64 +#define __USFRACT_MAX__ 0XFFP-8UHR +#define __UFRACT_IBIT__ 0 +#define __DBL_MIN__ ((double)2.2250738585072014e-308L) +#define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK) +#define __ULLACCUM_FBIT__ 32 +#define __ULLFRACT_EPSILON__ 0x1P-64ULLR +#define __ACCUM_MIN__ (-0X1P15K-0X1P15K) +#define __SQ_IBIT__ 0 +#define __UHA_FBIT__ 8 +#define __SFRACT_MIN__ (-0.5HR-0.5HR) +#define __UTQ_FBIT__ 128 +#define __VERSION__ "6.3.0" +#define __ULLFRACT_FBIT__ 64 +#define __CSKYABIV2__ 1 +#define __ckcore__ 2 +#define __FRACT_EPSILON__ 0x1P-15R +#define __ULACCUM_MIN__ 0.0ULK +#define __UDA_FBIT__ 32 +#define __LLACCUM_EPSILON__ 0x1P-31LLK +#define __GCC_ATOMIC_INT_LOCK_FREE 1 +#define __CSKYABI__ 2 +#define __CSKY_REQUIRED_PRINTF__ 1 +#define __USFRACT_MIN__ 0.0UHR +#define __UQQ_IBIT__ 0 +#define __CSKYLE__ 1 +#define __INT32_C(c) c ## L +#define __UHQ_FBIT__ 16 +#define __LLACCUM_FBIT__ 31 +#define __UDQ_FBIT__ 64 +#define __ELF__ 1 +#define __ULFRACT_EPSILON__ 0x1P-32ULR +#define __LLFRACT_FBIT__ 63 +#define __LDBL_EPSILON__ 2.2204460492503131e-16L +#define __SACCUM_MAX__ 0X7FFFP-7HK +#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 1 +#define __LACCUM_EPSILON__ 0x1P-31LK +#define __INT_FAST16_MAX__ 0x7fffffff +#define __USACCUM_MAX__ 0XFFFFP-8UHK +#define __SFRACT_EPSILON__ 0x1P-7HR +#define __USA_FBIT__ 16 +#define __UINT_FAST16_TYPE__ unsigned int +#define __csky_required_scanf__ 1 +#define __SACCUM_FBIT__ 7 +#define __GCC_ATOMIC_LONG_LOCK_FREE 1 +#define __SQ_FBIT__ 31 +#define __INT_FAST8_MAX__ 0x7fffffff +#define __QQ_FBIT__ 7 +#define __UTA_IBIT__ 64 +#define __LDBL_MANT_DIG__ 53 +#define __SFRACT_FBIT__ 7 +#define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK) +#define __CKCORE__ 2 +#define __WCHAR_TYPE__ long int +#define __USQ_FBIT__ 32 +#define __ULLACCUM_IBIT__ 32 +#define __LACCUM_FBIT__ 31 +#define __USACCUM_MIN__ 0.0UHK +#define __UHA_IBIT__ 8 +#define __UTQ_IBIT__ 0 +#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1 +#define __WINT_TYPE__ unsigned int +#define __ULLFRACT_IBIT__ 0 +#define __LDBL_MIN_EXP__ (-1021) +#define __UDA_IBIT__ 32 +#define __ck801__ 1 +#define __LFRACT_FBIT__ 31 +#define __LDBL_MAX_10_EXP__ 308 +#define __DBL_EPSILON__ ((double)2.2204460492503131e-16L) +#define __INT_LEAST32_TYPE__ long int +#define __SIZEOF_WCHAR_T__ 4 +#define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR +#define __TQ_FBIT__ 127 +#define __INT_FAST8_TYPE__ int +#define __ULLACCUM_EPSILON__ 0x1P-32ULLK +#define __UHQ_IBIT__ 0 +#define __LLACCUM_IBIT__ 32 +#define __TA_FBIT__ 63 +#define __UDQ_IBIT__ 0 +#define __ckcoreLE__ 1 +#define __ACCUM_EPSILON__ 0x1P-15K +#define __FLT_DENORM_MIN__ 1.4012984643248171e-45F +#define __LLFRACT_IBIT__ 0 +#define __FLT_MAX__ 3.4028234663852886e+38F +#define __USACCUM_FBIT__ 8 +#define __INT32_TYPE__ long int +#define __UFRACT_EPSILON__ 0x1P-16UR +#define __GNUC_MINOR__ 3 +#define __HA_FBIT__ 7 +#define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L +#define __csky__ 2 +#define __LLFRACT_MIN__ (-0.5LLR-0.5LLR) +#define __DA_FBIT__ 31 +#define __UINT32_TYPE__ long unsigned int +#define __USA_IBIT__ 16 +#define __LDBL_MIN_10_EXP__ (-307) +#define __csky_required_printf__ 1 +#define __cskyabiv2__ 1 +#define __ULACCUM_EPSILON__ 0x1P-32ULK +#define __SACCUM_IBIT__ 8 +#define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +#define __LDBL_DIG__ 15 +#define __UINT_FAST16_MAX__ 0xffffffffU +#define __GCC_ATOMIC_SHORT_LOCK_FREE 1 +#define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR +#define __UINT_FAST8_TYPE__ unsigned int +#define __USFRACT_EPSILON__ 0x1P-8UHR +#define __ULACCUM_FBIT__ 32 +#define __QQ_IBIT__ 0 +#define __CSKY__ 2 diff --git a/Source/.cache/project.conf b/Source/.cache/project.conf new file mode 100644 index 0000000..bcf0a99 --- /dev/null +++ b/Source/.cache/project.conf @@ -0,0 +1,6 @@ +{ + "device": " -mcpu=ck801 ", + "toolchain": "D:\\C-Sky\\CDKRepo\\Toolchain/CKV2ElfMinilib/V3.10.29/R/", + "toolchain_includes": ["d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\csky-elfabiv2", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include\\c++\\6.3.0\\backward", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\lib\\gcc\\csky-elfabiv2\\6.3.0\\include-fixed", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\sys-include", "d:\\C-Sky\\CDKRepo\\toolchain\\ckv2elfminilib\\v3.10.29\\R\\csky-elfabiv2\\include"], + "application": "D:\\Project_git\\MCU\\RCU_BUS485_PLC_MASTER\\Source\\.cache/" +} \ No newline at end of file diff --git a/Source/.cdk/Project.session b/Source/.cdk/Project.session new file mode 100644 index 0000000..93e482f --- /dev/null +++ b/Source/.cdk/Project.session @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/Source/.cdk/compilation.db b/Source/.cdk/compilation.db new file mode 100644 index 0000000..ffe8a39 Binary files /dev/null and b/Source/.cdk/compilation.db differ diff --git a/Source/.cdk/refactoring.db b/Source/.cdk/refactoring.db new file mode 100644 index 0000000..2a04ba3 Binary files /dev/null and b/Source/.cdk/refactoring.db differ diff --git a/Source/FWlib/apt32f102_adc.c b/Source/FWlib/apt32f102_adc.c new file mode 100644 index 0000000..d59e771 --- /dev/null +++ b/Source/FWlib/apt32f102_adc.c @@ -0,0 +1,500 @@ +/* + ****************************************************************************** + * @file apt32f102_adc.c + * @author APT AE Team + * @version V1.13 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_adc.h" + +/* defines -------------------------------------------------------------------*/ +/* externs--------------------------------------------------------------------*/ +/*************************************************************/ +//ADC12 RESET VALUE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_RESET_VALUE(void) +{ + ADC0->ECR = ADC_ECR_RST; /**< ECR reset value */ + ADC0->DCR = ADC_DCR_RST; /**< DCR reset value */ + ADC0->PMSR = ADC_PMSR_RST; /**< PMSR reset value */ + //ADC0->CR = ADC_CR_RST; /**< CR reset value */ + ADC0->MR = ADC_MR_RST; /**< MR reset value */ + ADC0->CSR = ADC_CSR_RST; /**< CSR reset value */ + ADC0->SR = ADC_SR_RST; /**< SR reset value */ + ADC0->IER = ADC_IER_RST; /**< IER reset value */ + ADC0->IDR = ADC_IDR_RST; /**< IDR reset value */ + ADC0->IMR = ADC_IMR_RST; /**< IMR reset value */ + ADC0->SEQ[0]= ADC_SEQx_RST; /**< SEQ0 reset value */ + ADC0->SEQ[1]= ADC_SEQx_RST; /**< SEQ1 reset value */ + ADC0->SEQ[2]= ADC_SEQx_RST; /**< SEQ2 reset value */ + ADC0->SEQ[3]= ADC_SEQx_RST; /**< SEQ3 reset value */ + ADC0->SEQ[4]= ADC_SEQx_RST; /**< SEQ4 reset value */ + ADC0->SEQ[5]= ADC_SEQx_RST; /**< SEQ5 reset value */ + ADC0->SEQ[6]= ADC_SEQx_RST; /**< SEQ6 reset value */ + ADC0->SEQ[7]= ADC_SEQx_RST; /**< SEQ7 reset value */ + ADC0->SEQ[8]= ADC_SEQx_RST; /**< SEQ8 reset value */ + ADC0->SEQ[9]= ADC_SEQx_RST; /**< SEQ9 reset value */ + ADC0->SEQ[10]= ADC_SEQx_RST; /**< SEQ10 reset value */ + ADC0->SEQ[11]= ADC_SEQx_RST; /**< SEQ11 reset value */ + ADC0->SEQ[12]= ADC_SEQx_RST; /**< SEQ12 reset value */ + ADC0->SEQ[13]= ADC_SEQx_RST; /**< SEQ13 reset value */ + ADC0->SEQ[14]= ADC_SEQx_RST; /**< SEQ14 reset value */ + ADC0->SEQ[15]= ADC_SEQx_RST; /**< SEQ15 reset value */ + ADC0->DR[0] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[1] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[2] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[3] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[4] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[5] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[6] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[7] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[8] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[9] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[10] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[11] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[12] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[13] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[14] = ADC_DR_RST; /**< DR reset value */ + ADC0->DR[15] = ADC_DR_RST; /**< DR reset value */ + ADC0->CMP0 = ADC_CMP0_RST; /**< CMP1 reset value */ + ADC0->CMP1 = ADC_CMP1_RST; /**< CMP2 reset value */ +} +/*************************************************************/ +//ADC12 Control +//EntryParameter:ADC12_Control_x +//ADC12_Control_x:ADC12_SWRST , ADC12_ADCEN , ADC12_ADCDIS, ADC12_START, ADC12_STOP,ADC12_SWTRG +//ReturnValue:NONE +/*************************************************************/ + //control:ADC enable/disable ,start/stop,swrst +void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x ) +{ + ADC0->CR |= ADC12_Control_x; // +} +/*************************************************************/ +//ADC12 Interrupt ENABLE AND DISABLE +//EntryParameter:ADC_IMR_X,NewState +//ADC_IMR_X:ADC12_EOC,ADC12_READY,ADC12_OVR,ADC12_CMP0H,ADC12_CMP0L,ADC12_CMP1H,ADC12_CMP1L,ADC12_SEQ_END0~15 +//NewState:ENABLE , DISABLE +//ReturnValue:NONE +/*************************************************************/ + //ADC12_EOC:End of conversion interrupt + //ADC12_READY:ADC ready for conversion interrupt + //ADC12_OVR:Overrun interrupt + //ADC12_CMP0H:Higher than ADC_CMP1 interrupt + //ADC12_CMP0L:Lower than ADC_CMP1 interrupt + //ADC12_CMP1H:Higher than ADC_CMP2 interrupt + //ADC12_CMP1L:Lower than ADC_CMP2 interrupt + //ADC12_SEQ_END0~15:SEQx convert end interrupt +void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + ADC0->IER |= ADC_IMR_X; //SET + } + else + { + ADC0->IDR |= ADC_IMR_X; //CLR + } +} +/*************************************************************/ +//Read ADC12 Interrupt ENABLE status +//EntryParameter:EnStatus_bit +//EnStatus_bit:ADC12_EOC,ADC12_READY,ADC12_OVR,ADC12_CMP1H,ADC12_CMP1L,ADC12_CMP2H,ADC12_CMP2L,ADC12_SEQ_END0~15 +//ReturnValue:1=enabled/0=disabled +/*************************************************************/ +uint8_t ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit) +{ + uint8_t value = 0; + uint32_t dat = 0; + dat= ADC0->IMR&EnStatus_bit; + if (dat == EnStatus_bit) + { + value = 1; + } + return value; +} +/*************************************************************/ +//ADC12 CLK ENABLE AND DISABLE +//EntryParameter:ADC_CLK_CMD,NewState +//ADC_CLK_CMD:ADC_CLK_CR,ADC_DEBUG_MODE +//NewState:ENABLE , DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + ADC0->ECR |= ADC_CLK_CMD; //ENABLE + while(!(ADC0->PMSR&ADC_CLK_CMD)); + } + else + { + ADC0->DCR |= ADC_CLK_CMD; //DISABLE + while(ADC0->PMSR&ADC_CLK_CMD); + } +} +/*************************************************************/ +//ADC12 software reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_Software_Reset(void) +{ + ADC12_Control(ADC12_SWRST); +} +/*************************************************************/ +//ADC12 ENABLE +//EntryParameter:NewState +//NewState:ENABLE , DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_CMD(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + ADC12_Control(ADC12_ADCEN); //ADC12 ENABLE + while(!(ADC0->SR &ADC12_ADCENS)); + } + else + { + ADC12_Control(ADC12_ADCDIS); //ADC12 DISABLE + while(ADC0->SR&ADC12_ADCENS); + } +} +/*************************************************************/ +//ADC12 READY wait +//EntryParameter:NONE +//ReturnValue:ADC12 READ FLAG +/*************************************************************/ +void ADC12_ready_wait(void) +{ + while(!(ADC0->SR&ADC12_READY)); // Waiting for ADC0 Ready +} +/*************************************************************/ +//ADC12 End of conversion wait +//EntryParameter:NONE +//ReturnValue:ADC12 EOC +/*************************************************************/ +void ADC12_EOC_wait(void) +{ + while(!(ADC0->SR & ADC12_EOC)); // EOC wait +} +/*************************************************************/ +//ADC12 End of conversion wait +//EntryParameter:NONE +//ReturnValue:ADC12 EOC +/*************************************************************/ +void ADC12_SEQEND_wait(U8_T val) +{ + while(!(ADC0->SR & (0x01ul << (16+val)))); // EOC wait +} +/*************************************************************/ +//ADC12 Data Register output +//EntryParameter:NONE +//ReturnValue:ADC12 DR +/*************************************************************/ +U16_T ADC12_DATA_OUPUT(U16_T Data_index ) +{ + return(ADC0->DR[Data_index]); +} +/*************************************************************/ +//ADC12 Configure +//EntryParameter:ADC12_BIT_SELECTED,ADC12_ConverMode,ADC12_DIV,NumConver +//ADC12_BIT_SELECTED:ADC12_12BIT,ADC12_10BIT +//ADC12_ConverMode:One_shot_mode,Continuous_mode +//ADC12_PRI:0~15 +//adc12_SHR:0~255 +//ADC12_DIV:0~31 +//NumConver:Number of Conversions value=(1~12); +//ReturnValue:NONE +/*************************************************************/ + //10BIT or 12BIT adc ; + //ADC12_BIT_SELECTED:ADC12_12BIT/ADC12_10BIT; + //ADC12_ConverMode:One_shot_mode/Continuous_mode; + //adc date output=last number of Conversions; +void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver ) +{ + ADC0->MR=ADC12_DIV|((NumConver-1)<<10); + if(ADC12_ConverMode==One_shot_mode) + { + ADC0->MR&=~CONTCV; //one short mode + while(ADC0->SR&ADC12_CTCVS); + } + else if(ADC12_ConverMode==Continuous_mode) + { + ADC0->MR|=CONTCV; //Continuous mode + while(!(ADC0->SR&ADC12_CTCVS)); + } + ADC12_CMD(ENABLE); //ADC0 enable + if(ADC12_BIT_SELECTED) + { + ADC0->CR|=ADC12_10BITor12BIT; + } + else + { + ADC0->CR&=~ADC12_10BITor12BIT; + } + //ADC0->CR|=ADC12_VREF_VDD | ADC12_FVR_DIS; + ADC0->PRI=ADC12_PRI; + ADC0->SHR=adc12_SHR; //adc Sampling & Holding cycles +} +/*************************************************************/ +//ADC12 VREF slection=VDD +//EntryParameter:NONE +//ReturnValue:None +/*************************************************************/ +void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X ) +{ + if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_VSS) + { + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x00<<6); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_VSS) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x01<<6); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_VSS) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x02<<6)|(0X01<<24)|(0X00<<25); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_VSS) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x03<<6)|(0X01<<24)|(0X01<<25); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_VSS) + { + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x04<<6)|(0X00<<16)|(0X02<<17); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x08<<6); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x09<<6); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0A<<6)|(0X01<<24)|(0X00<<25); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0B<<6)|(0X01<<24)|(0X01<<25); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17); + } +} +/*************************************************************/ +//ADC12 Compare function set +//EntryParameter:ConverNum_CM0,ConverNum_CM1,CMP0_data,CMP1_data +//ConverNum_CM0:VALUE=(0~15) +//ConverNum_CM1:VALUE=(0~15) +//CMP0_data:VALUE=(1~(0X3FF/0XFFF)) +//CMP1_data:VALUE=(1~(0X3FF/0XFFF)) +//ReturnValue:NONE +/*************************************************************/ + //ConverNum_CM0:Number of Conversions for Compare Function + //ConverNum_CM1:Number of Conversions for Compare Function + //ADC will generate a CMPxH/CMPxL interrupt when result of this number of conversion is higher/lower than data set in ADC_CMPx register. + //ConverNum_CM1Number of Conversions for Compare Function + //ADC will generate a CMP1H/CMP1L interrupt when result of this number of conversion is greater/less than data set in ADC_CMP1 register. + +void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data ) +{ + ADC0->MR|=((ConverNum_CM0-0)<<16)|((ConverNum_CM1-0)<<22); + ADC0->CMP0=CMP0_data; + ADC0->CMP1=CMP1_data; +} +/*************************************************************/ +//ADC12 Conversion chanle seting +//EntryParameter:ADC12_3/4/6/8CYCLES,SEQx,ADC12_ADCINX,ADC12_CV_RepeatNum1/2/4/8/16/32/64/128 +//SEQx:VALUE=(1~18) +//ADC12_ADCINX:ADC12_ADCIN0~ADC12_ADCIN17,ADC12_INTVREF,ADC12_DIV4_VDD,ADC12_VSS +//ReturnValue:NONE +/*************************************************************/ +void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX , + ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx) +{ + U8_T i; + for(i=0;i<15;i++) + { + ADC0->SEQ[i] &=~(0x01<<7); + } + switch(ADC12_ADCINX) + { + case 0: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC0 PB0.1 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0x00000010; + break; + case 1: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000001; //ADC1 PA0.0 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 2: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000010; //ADC2 PA0.1 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 3: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00001000; //ADC3 PA0.3 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 4: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00100000; //ADC4 PA0.5 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 5: + GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x01000000; //ADC5 PA0.6 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 6: + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x10000000; //ADC6 PA0.7 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 7: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC7 PB0.2 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000100; + break; + case 8: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC8 PB0.3 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0x00001000; + break; + case 9: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC9 PA0.8 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000001; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 10: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC10 PA0.9 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0x00000010; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 11: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC11 PA0.10 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0x00000100; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 12: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC12 PA0.11 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0x00001000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 13: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC13 PA0.12 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00010000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 14: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC14 PA0.13 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00100000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 15: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC15 PB0.0 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000001; + break; + //case 18: break; + //case 19: break; + //case 20: break; + //case 21: break; + //case 22: break; + //case 23: break; + //case 24: break; + //case 25: break; + //case 26: break; + //case 27: break; + case 0x1Cul: break; + case 0x1Dul: break; + case 0x1Eul: break; + } + ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0; + ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | CV_RepeatTime | AVG_Set; +} +/*************************************************************/ +//ADC12 Compare statue output +//EntryParameter:NBRCMPx_TypeDef,NBRCMPX_L_TypeDef +//NBRCMPx_TypeDef:NBRCMP0_TypeDef,NBRCMP1_TypeDef +//NBRCMPX_L_TypeDef:NBRCMPX_L_TypeDef,NBRCMPX_H_TypeDef +//ReturnValue:ADC12 Compare result flag +/*************************************************************/ + //output statue:ADC-SR(ADC12_CMP0H/ADC12_CMP0L/ADC12_CMP1H/ADC12_CMP1L) +U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL) +{ + if(ADC12_NBRCMPx==NBRCMP0_TypeDef) + { + if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef) + { + return((ADC0->SR)&ADC12_CMP0L); + } + else + { + return((ADC0->SR)&ADC12_CMP0H); + } + + } + else + { + if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef) + { + return((ADC0->SR)&ADC12_CMP1L); + } + else + { + return((ADC0->SR)&ADC12_CMP1H); + } + } +} +/*************************************************************/ +//ADC Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC_Int_Enable(void) +{ + ADC0->CSR=0xFFFFFFFF; + INTC_ISER_WRITE(ADC_INT); +} +/*************************************************************/ +//ADC Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC_Int_Disable(void) +{ + INTC_ICER_WRITE(ADC_INT); +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_bt.c b/Source/FWlib/apt32f102_bt.c new file mode 100644 index 0000000..d560b42 --- /dev/null +++ b/Source/FWlib/apt32f102_bt.c @@ -0,0 +1,287 @@ +/* + ****************************************************************************** + * @file apt32f102_bt.c + * @author APT AE Team + * @version V1.10 + * @date 2021/08/25 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_bt.h" + +/* defines -------------------------------------------------------------------*/ +/* externs--------------------------------------------------------------------*/ + + +/*************************************************************/ +//Deinitializes the registers to their default reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_DeInit(CSP_BT_T *BTx) +{ + BTx->RSSR=BT_RESET_VALUE; + BTx->CR=BT_RESET_VALUE; + BTx->PSCR=BT_RESET_VALUE; + BTx->PRDR=BT_RESET_VALUE; + BTx->CMP=BT_RESET_VALUE; + BTx->CNT=BT_RESET_VALUE; + BTx->EVTRG=BT_RESET_VALUE; + BTx->EVSWF=BT_RESET_VALUE; + BTx->RISR=BT_RESET_VALUE; + BTx->IMCR=BT_RESET_VALUE; + BTx->MISR=BT_RESET_VALUE; + BTx->ICR=BT_RESET_VALUE; +} +/*************************************************************/ +//BT IO Init +//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10, +//ReturnValue:NONE +/*************************************************************/ +void BT_IO_Init(BT_Pin_TypeDef BT_IONAME) +{ + if(BT_IONAME==BT0_PA00) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; //BT0 PA0.0 + } + if(BT_IONAME==BT0_PA02) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000600; //BT0 PA0.2 + } + if(BT_IONAME==BT0_PA05) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00500000; //BT0 PA0.5 + } + if(BT_IONAME==BT0_PB02) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFF0FF)|0x00000500; //BT0 PB0.2 + } + if(BT_IONAME==BT0_PB05) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFF0FFFFF)|0x00700000; //BT0 PB0.5 + } + if(BT_IONAME==BT0_PA11) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00008000; //BT0 PA0.11 + } + if(BT_IONAME==BT0_PA13) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00800000; //BT0 PA0.13 + } + if(BT_IONAME==BT0_PA15) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000; //BT0 PA0.15 + } + if(BT_IONAME==BT1_PA01) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000060; //BT1 PA0.1 + } + if(BT_IONAME==BT1_PA06) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x04000000; //BT1 PA0.6 + } + if(BT_IONAME==BT1_PA08) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000006; //BT1 PA0.8 + } + if(BT_IONAME==BT1_PA12) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00060000; //BT1 PA0.12 + } + if(BT_IONAME==BT1_PA14) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14 + } + if(BT_IONAME==BT1_PB00) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000008; //BT1 PB0.0 + } + if(BT_IONAME==BT1_PB04) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4 + } +} +/*************************************************************/ +// BT start +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Start(CSP_BT_T *BTx) +{ + BTx->RSSR |=0X01; +} +/*************************************************************/ +// BT stop +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Stop(CSP_BT_T *BTx) +{ + BTx->RSSR &=0X0; +} +/*************************************************************/ +// BT stop High +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Stop_High(CSP_BT_T *BTx) +{ + BTx->CR |=(0x01<<6); + BTx->RSSR &=0X0; +} +/*************************************************************/ +// BT stop Low +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Stop_Low(CSP_BT_T *BTx) +{ + BTx->CR =BTx->CR & ~(0x01<<6); + BTx->RSSR &=0X0; +} +/*************************************************************/ +// BT soft reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Soft_Reset(CSP_BT_T *BTx) +{ + BTx->RSSR |= (0X5<<12); +} +/*************************************************************/ +//BT Configure +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM) +{ + BTx->CR |=BTCLK| BTSHDWSTP| BTOPM| BTEXTCKM; + BTx->PSCR = PSCR_DATA; +} +/*************************************************************/ +//BT ControlSet +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD, + BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD) +{ + BTx->CR |=BTSTART| BTIDLE| BTSYNC| BTSYNCMD| BTOSTMD| BTAREARM| BTCNTRLD; +} +/*************************************************************/ +//BT Period / Compare set +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA) +{ + //BTx->CR|=0X01<<2; + BTx->PRDR =BTPRDR_DATA; + BTx->CMP =BTCMP_DATA; +} +/*************************************************************/ +//BT COUNTER set +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA) +{ + BTx->CNT =BTCNT_DATA; +} +/*************************************************************/ +//BT read counters +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +U16_T BT_PRDR_Read(CSP_BT_T *BTx) +{ + return BTx->PRDR; +} +U16_T BT_CMP_Read(CSP_BT_T *BTx) +{ + return BTx->CMP; +} +U16_T BT_CNT_Read(CSP_BT_T *BTx) +{ + return BTx->CNT; +} +/*************************************************************/ +//BT Trigger Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE) +{ + BTx->EVTRG|=BTTRG| BTTRGOE; +} +/*************************************************************/ +//BT SOFT Trigger +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_Soft_Tigger(CSP_BT_T *BTx) +{ + BTx->EVSWF=0x01; +} +/*************************************************************/ +//BT inturrpt Configure +//EntryParameter:BT_IMSCR_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X) +{ + if (NewState != DISABLE) + { + BTx->IMCR |= BT_IMSCR_X; + } + else + { + BTx->IMCR &= ~BT_IMSCR_X; + } +} +/*************************************************************/ +//BT0 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT0_INT_ENABLE(void) +{ + INTC_ISER_WRITE(BT0_INT); +} +/*************************************************************/ +//BT0 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT0_INT_DISABLE(void) +{ + INTC_ICER_WRITE(BT0_INT); +} +/*************************************************************/ +//BT0 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT1_INT_ENABLE(void) +{ + INTC_ISER_WRITE(BT1_INT); +} +/*************************************************************/ +//BT0 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT1_INT_DISABLE(void) +{ + INTC_ICER_WRITE(BT1_INT); +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_coret.c b/Source/FWlib/apt32f102_coret.c new file mode 100644 index 0000000..255e73c --- /dev/null +++ b/Source/FWlib/apt32f102_coret.c @@ -0,0 +1,147 @@ +/* + ****************************************************************************** + * @file apt32f102_CORET.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_coret.h" +#include "apt32f102_syscon.h" + + +/* defines -------------------------------------------------------------------*/ +/* externs--------------------------------------------------------------------*/ + + +/*************************************************************/ +//Deinitializes the syscon registers to their default reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_DeInit(void) +{ + CK801->CORET_CSR=CORET_CSR_RST; + CK801->CORET_RVR=CORET_RVR_RST; + CK801->CORET_CVR=CORET_CVR_RST; + CK801->CORET_CALIB=CORET_CALIB_RST; +} + +/*************************************************************/ +//CORET Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_Int_Enable(void) +{ + CK801->CORET_CVR = 0x0; // Clear counter and flag + INTC_ISER_WRITE(CORET_INT); +} + +/*************************************************************/ +//CORET Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_Int_Disable(void) +{ + INTC_ICER_WRITE(CORET_INT); +} + +/*************************************************************/ +// CORET Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(CORET_INT); +} + +/*************************************************************/ +// CORET Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(CORET_INT); +} + +/*************************************************************/ +// CORET START +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_start(void) +{ + CK801->CORET_CSR|=0x01; +} +/*************************************************************/ +// CORET stop +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_stop(void) +{ + CK801->CORET_CSR&=0Xfffffffe; +} +/*************************************************************/ +// CORET CLKSOURC EX +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_CLKSOURCE_EX(void) +{ + CK801->CORET_CSR&=0Xfffffffb; +} +/*************************************************************/ +// CORET CLKSOURC IN +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_CLKSOURCE_IN(void) +{ + CK801->CORET_CSR|=0x04; +} +/*************************************************************/ +//CORET TICKINT enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_TICKINT_Enable(void) +{ + CK801->CORET_CSR|=0x02; +} + +/*************************************************************/ +//CORET TICKINT enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_TICKINT_Disable(void) +{ + CK801->CORET_CSR&=0Xfffffffd; +} + +/*************************************************************/ +// CORET reload +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORET_reload(void) +{ + CK801->CORET_CVR = 0x0; // Clear counter and flag +} + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_countera.c b/Source/FWlib/apt32f102_countera.c new file mode 100644 index 0000000..60dea0b --- /dev/null +++ b/Source/FWlib/apt32f102_countera.c @@ -0,0 +1,153 @@ +/* + ****************************************************************************** + * @file apt32f102_countera.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_countera.h" +/* defines -------------------------------------------------------------------*/ + +/* externs--------------------------------------------------------------------*/ + + +/*************************************************************/ +//Count A RESET,CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void COUNT_DeInit(void) +{ + CA0->CADATAH = CA_RESET_VALUE; + CA0->CADATAL = CA_RESET_VALUE; + CA0->CACON = CA_RESET_VALUE; + CA0->INTMASK = CA_RESET_VALUE; +} + +/*************************************************************/ +//CountA Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Int_Enable(void) +{ + INTC_ISER_WRITE(CA_INT); +} +/*************************************************************/ +//CountA Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Int_Disable(void) +{ + INTC_ICER_WRITE(CA_INT); +} +/*************************************************************/ +//CountA Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Wakeup_Enable(void) +{ + INTC_IWER_WRITE(CA_INT); +} +/*************************************************************/ +//CountA Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Wakeup_Disable(void) +{ + INTC_IWDR_WRITE(CA_INT); +} +/*************************************************************/ +//CountA Init +//EntryParameter:Data_H,Data_L,INT_Mode,DIVx,Mode,Carrier,OSP_Mode +//Data_H,Data_L:0x0000~0xFFFF +//INT_MODE:Period_NA/Period_H/Period_L/Period_H_L +//DIVx:DIV1/DIV2/DIV4/DIV8 +//Mode:ONESHOT_MODE / REPEAT_MODE +//Carrier:CARRIER_OFF / CARRIER_ON +//OSP_Mode:OSP_LOW /OSP_HIGH +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Init(uint32_t Data_H,uint32_t Data_L,CA_INT_TypeDef INT_Mode, + CA_CLKDIV_TypeDef DIVx,CA_Mode_TypeDef Mode,CA_CARRIER_TypeDef Carrier, + CA_OSP_TypeDef OSP_Mode) +{ + COUNT_DeInit(); + CA0->CADATAH = Data_H;//0x0000~0xFFFF time(us)/(1/F Mhz) eg:10us/(1/4)=10us/0.25us=40,Data_H=40 + CA0->CADATAL = Data_L;//0x0000~0xFFFF + CA0->CACON = DIVx | Mode | Carrier | OSP_Mode ; + CA0->INTMASK = INT_Mode ; +} +/*************************************************************/ +//CountA config +//EntryParameter:STROBE,Pend_val,Match_val,Stat_val,ENVELOPE +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Config(CA_STROBE_TypeDef STROBE,CA_PENDREM_TypeDef Pend_CON, + CA_MATCHREM_TypeDef Match_CON,CA_REMSTAT_TypeDef Stat_CON,CA_ENVELOPE_TypeDef ENVELOPE ) +{ + CA0->CACON = CA0->CACON | STROBE | Pend_CON | Match_CON | Stat_CON | ENVELOPE; +} +/*************************************************************/ +//CountA Start +//EntryParameter:none +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Start(void) +{ + CA0->CACON=(CA0->CACON&0xFFFFFFF3)|0X04; //bit 2,This bit be cleared automatically +} +/*************************************************************/ +//CountA Stop +//EntryParameter:none +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Stop(void) +{ + CA0->CACON=(CA0->CACON&0xFFFFFFF7)|0X08; //bit 4 +} +/*************************************************************/ +//CountA data update +//EntryParameter:none +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_Data_Update(uint32_t Data_H,uint32_t Data_L) +{ + CA0->CADATAH = Data_H;//0x0000~0xFFFF time(us)/(1/F Mhz) eg:10us/(1/4)=10us/0.25us=40,Data_H=40 + CA0->CADATAL = Data_L;//0x0000~0xFFFF + CA0->CACON = CA0->CACON | (1ul<<16); +} +/*************************************************************/ +//CountA Stop +//EntryParameter:COUNTA_IO_G0 +//COUNTA_IO_G:0 PB0.01 1 PA0.05 2 PA0.11 +//ReturnValue:NONE +/*************************************************************/ +void COUNTA_IO_Init(CA_COUNTAIO_TypeDef COUNTA_IO_G) +{ + if(COUNTA_IO_G==0) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000040; //BUZZ (PB0.01->AF1) + } + else if(COUNTA_IO_G==1) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00600000; //BUZZ (PA0.05->AF4) + } + else if(COUNTA_IO_G==2) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00007000; //BUZZ (PA0.11->AF3) + } +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_crc.c b/Source/FWlib/apt32f102_crc.c new file mode 100644 index 0000000..b5d6ec3 --- /dev/null +++ b/Source/FWlib/apt32f102_crc.c @@ -0,0 +1,150 @@ +/* + ****************************************************************************** + * @file apt32f102_crc.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + + + /* Includes ------------------------------------------------------------------*/ +#include "apt32f102_crc.h" + +/*************************************************************/ +// CRC enable/disable +//EntryParameter:ENABLE/DISABLE +//ReturnValue:NONE +/*************************************************************/ +void CRC_CMD(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + CRC->CEDR =0X01; //SET + } + else + { + CRC->CEDR =0X00; //CLR + } +} + +/*************************************************************/ +//CRC RESET +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CRC_Soft_Reset(void) +{ + CRC->SRR = 0X01; +} + +/*************************************************************/ +//CRC CONTROL +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CRC_Configure(CRC_COMPIN_TypeDef COMPINX,CRC_COMPOUT_TypeDef COMPOUTX,CRC_ENDIANIN_TypeDef ENDIANINX, + CRC_ENDIANOUT_TypeDef ENDIANOUT,CRC_POLY_TypeDef POLYX) +{ + CRC->CR = 0; + CRC->CR |= COMPINX |COMPOUTX |ENDIANINX |ENDIANOUT| POLYX; +} + +/*************************************************************/ +//CRC seed write +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CRC_Seed_Write(U32_T seed_data) +{ + CRC->SEED = seed_data; +} + +/*************************************************************/ +//CRC seed read +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U32_T CRC_Seed_Read(void) +{ + return CRC->SEED; +} + +/*************************************************************/ +//CRC datain +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CRC_Datain(U32_T data_in) +{ + CRC->DATAIN=data_in; +} + +/*************************************************************/ +//CRC Result read +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U32_T CRC_Result_Read(void) +{ + return CRC->DATAOUT; +} +/*************************************************************/ +//CRC calc 32bit input +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U32_T Chip_CRC_CRC32(U32_T *data, U32_T words) +{ + while (words > 0) { + CRC_Datain(*data); + data++; + words--; + } + return CRC_Result_Read(); +} +/*************************************************************/ +//CRC calc 16bit input +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U32_T Chip_CRC_CRC16(U16_T *data, U32_T size) +{ + U32_T i,j; + U8_T data_temp; + for (i=0; i>8; + if(j==1)data_temp=*data&0xff; + *(U8_T *)(AHB_CRCBase + 0x14 + (i%4)) = data_temp; + } + data++; + } + return CRC_Result_Read(); +} +/*************************************************************/ +//CRC calc 8bit input +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U32_T Chip_CRC_CRC8(U8_T *data, U32_T size) +{ + U32_T i; + for (i=0; iCEDR|=0X01; + EPT0->RSSR=(EPT0->RSSR&0XFFFF0FFF)|(0X05<<12); +} +/*************************************************************/ +//Deinitializes the EPT start prg +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Start(void) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->RSSR|=0X01; + while(!(EPT0->RSSR&0x01)); +} +/*************************************************************/ +//Deinitializes the EPT stop prg +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Stop(void) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->RSSR&=0Xfe; + while(EPT0->RSSR&0x01); +} +/*************************************************************/ +//Deinitializes the EPT IO Config,IO_Num_X +//EntryParameter:EPT_IO_Mode_Type +//EPT_IO_X:EPT_IO_CHAX,EPT_IO_CHAY,EPT_IO_CHBX,EPT_IO_CHBY,EPT_IO_CHCX,EPT_IO_CHCX,EPT_IO_CHD,EPT_IO_EPI +//ReturnValue:NONE +/*************************************************************/ +void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X) +{ + if(EPT_IO_X==EPT_IO_CHAX) + { + if(IO_Num_X==IO_NUM_PA07) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X60000000; //PA0.7 + } + else if(IO_Num_X==IO_NUM_PA10) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)|0X00000500; //PA0.10 + } + else if(IO_Num_X==IO_NUM_PA15) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF)|0X40000000; //PA0.15 + } + } + else if(EPT_IO_X==EPT_IO_CHAY) + { + if(IO_Num_X==IO_NUM_PB03) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00005000; //PB0.3 + } + else if(IO_Num_X==IO_NUM_PB05) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00500000; //PB0.5 + } + else if(IO_Num_X==IO_NUM_PA12) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)|0X00050000; //PA0.12 + } + } + else if(EPT_IO_X==EPT_IO_CHBX) + { + if(IO_Num_X==IO_NUM_PB02) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000600; //PB0.2 + } + else if(IO_Num_X==IO_NUM_PA11) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)|0X00005000; //PA0.11 + } + else if(IO_Num_X==IO_NUM_PA14) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)|0X04000000; //PA0.14 + } + } + else if(EPT_IO_X==EPT_IO_CHBY) + { + if(IO_Num_X==IO_NUM_PB04) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00050000; //PB0.4 + } + else if(IO_Num_X==IO_NUM_PA05) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)|0X00800000; //PA0.5 + } + else if(IO_Num_X==IO_NUM_PA08) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000005; //PA0.8 + } + } + else if(EPT_IO_X==EPT_IO_CHCX) + { + if(IO_Num_X==IO_NUM_PB05) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00400000; //PB0.5 + } + else if(IO_Num_X==IO_NUM_PA03) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF)|0X00005000; //PA0.3 + } + else if(IO_Num_X==IO_NUM_PB03) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00004000; //PB0.3 + } + else if(IO_Num_X==IO_NUM_PB00) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)|0X00000005; //PB0.0 + } + } + else if(EPT_IO_X==EPT_IO_CHCY) + { + if(IO_Num_X==IO_NUM_PB04) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00040000; //PB0.4 + } + else if(IO_Num_X==IO_NUM_PA04) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF)|0X00050000; //PA0.4 + } + else if(IO_Num_X==IO_NUM_PA09) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)|0X00000070; //PA0.9 + } + else if(IO_Num_X==IO_NUM_PA013) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00500000; //PA0.13 + } + } + else if(EPT_IO_X==EPT_IO_CHD) + { + if(IO_Num_X==IO_NUM_PB03) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00006000; //PB0.3 + } + else if(IO_Num_X==IO_NUM_PA08) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000004; //PA0.8 + } + } + else if(EPT_IO_X==EPT_IO_EPI) + { + if(IO_Num_X==IO_NUM_PA07) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X50000000; //PA0.7 EPI0 + } + else if(IO_Num_X==IO_NUM_PA013) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00400000; //PA0.13 EPI1 + } + else if(IO_Num_X==IO_NUM_PB03) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00007000; //PB0.3 EPI2 + } + else if(IO_Num_X==IO_NUM_PB02) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3 + } + } +} +/*************************************************************/ +//Deinitializes the EPT PWM Config +//EntryParameter:EPT_TCLK_Selecte_X,EPT_CNTMD_SELECTE_X,EPT_OPM_SELECTE_X,EPT_PSCR +//EPT_TCLK_Selecte_X:EPT_Selecte_PCLK,EPT_Selecte_SYNCUSR3 +//EPT_CNTMD_SELECTE_X:EPT_CNTMD_increase,EPT_CNTMD_decrease,EPT_CNTMD_increaseTOdecrease +//EPT_OPM_SELECTE_X:EPT_OPM_Once,EPT_OPM_Continue +//EPT_PSCR:0~0XFFFF +//ReturnValue:NONE +/*************************************************************/ +//Fclk=Fpclk/(PSC+1) +void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X + , U16_T EPT_PSCR) +{ + EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6)); + if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK) + { + EPT0->PSCR=EPT_PSCR; + } + EPT0->CR=(EPT0->CR&0xfff8ffc0)|EPT_CNTMD_SELECTE_X|(0x1<<2)|(0x0<<3)|(0x0<<4)|EPT_OPM_SELECTE_X|(0X0<<16)|(0x1<<18); +} +/*************************************************************/ +//Deinitializes the EPT PWM Config +//EntryParameter:EPT_CGSRC_TIN_Selecte_X,EPT_CGFLT_DIV,EPT_CGFLT_CNT,EPT_BURST_CMD +//EPT_CGSRC_TIN_Selecte_X:EPT_CGSRC_TIN_BT0OUT,EPT_CGSRC_TIN_BT1OUT,EPT_CGSRC_CHAX,EPT_CGSRC_CHBX,EPT_CGSRC_DIS +//EPT_CGFLT_DIV:0~255 +//EPT_CGFLT_CNT:0~7 +//EPT_BURST_CMD:EPT_BURST_ENABLE,EPT_BURST_DISABLE +//ReturnValue:NONE +/*************************************************************/ +void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD) +{ + EPT0->CR=(EPT0->CR&0xffff01ff)|EPT_BURST_CMD|EPT_CGFLT_CNT<<13|0x01<<10; + EPT0->CEDR=(EPT0->CEDR&0XFFFF00CF)|(EPT_CGFLT_DIV<<8); + if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_DIS) + { + EPT0->CEDR|=0X00<<4; + EPT0->CR|=0X03<<11; + } + else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT0OUT) + { + EPT0->CEDR|=0X01<<4; + EPT0->CR|=0X02<<11; + } + else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT1OUT) + { + EPT0->CEDR|=0X02<<4; + EPT0->CR|=0X02<<11; + } + else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHAX) + { + EPT0->CEDR|=0X00<<4; + EPT0->CR|=0X00<<11; + } + else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHBX) + { + EPT0->CEDR|=0X00<<4; + EPT0->CR|=0X01<<11; + } +} +/*************************************************************/ +//Deinitializes the EPT Caputer Config +//EntryParameter:EPT_TCLK_Selecte_X,EPT_CNTMD_SELECTE_X,EPT_CAPMD_SELECTE_X,EPT_LOAD_CMPA_RST_CMD~EPT_LOAD_CMPD_RST_CMD,EPT_STOP_WRAP,EPT_PSCR +//EPT_TCLK_Selecte_X:EPT_Selecte_PCLK,EPT_Selecte_SYNCUSR3 +//EPT_CNTMD_SELECTE_X:EPT_CNTMD_increase,EPT_CNTMD_decrease,EPT_CNTMD_increaseTOdecrease +//EPT_CAPMD_SELECTE_X:EPT_CAPMD_Once,EPT_CAPMD_Continue +//EPT_LOAD_CMPA_RST_CMD:EPT_LDARST_EN,EPT_LDARST_DIS +//EPT_LOAD_CMPB_RST_CMD:EPT_LDBRST_EN,EPT_LDBRST_DIS +//EPT_LOAD_CMPC_RST_CMD:EPT_LDCRST_EN,EPT_LDCRST_DIS +//EPT_LOAD_CMPD_RST_CMD:EPT_LDDRST_EN,EPT_LDDRST_DIS +//EPT_STOP_WRAP:0~3 +//EPT_PSCR:0~0XFFFF +//ReturnValue:NONE +/*************************************************************/ +void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD + , EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD + , EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR) +{ + EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6)); + if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK) + { + EPT0->PSCR=EPT_PSCR; + } + EPT0->CR=(EPT0->CR&0xf800fec0)|EPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|EPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(EPT_STOP_WRAP<<21)| + EPT_LOAD_CMPA_RST_CMD|EPT_LOAD_CMPB_RST_CMD|EPT_LOAD_CMPC_RST_CMD|EPT_LOAD_CMPD_RST_CMD; +} + +/*************************************************************/ +//Deinitializes the EPT SYNCR Config +//EntryParameter:EPT_Triggle_X,EPT_SYNCR_EN,EPT_SYNCUSR0_REARMTrig_Selecte,EPT_TRGSRC0_ExtSync_Selected,EPT_TRGSRC1_ExtSync_Selected +//EPT_Triggle_X:EPT_Triggle_Continue,EPT_Triggle_Once +//EPT_SYNCUSR0_REARMTrig_Selecte:EPT_SYNCUSR0_REARMTrig_DIS,EPT_SYNCUSR0_REARMTrig_T1,EPT_SYNCUSR0_REARMTrig_T2 +//EPT_SYNCUSR0_REARMTrig_T1T2 +//EPT_TRGSRC0_ExtSync_Selected:EPT_TRGSRC0_ExtSync_SYNCUSR0~EPT_TRGSRC0_ExtSync_SYNCUSR5 +//EPT_TRGSRC1_ExtSync_Selected:EPT_TRGSRC1_ExtSync_SYNCUSR0~EPT_TRGSRC1_ExtSync_SYNCUSR5 +//EPT_SYNCR_EN:0~0X3F +//ReturnValue:NONE +/*************************************************************/ +void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected , + EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->SYNCR = (EPT0->SYNCR&0XC03F0000) |EPT_SYNCR_EN|EPT_Triggle_X|EPT_SYNCUSR0_REARMTrig_Selecte|EPT_TRGSRC0_ExtSync_Selected|EPT_TRGSRC1_ExtSync_Selected; +} +/*************************************************************/ +//Deinitializes the EPT CPCR Config +//EntryParameter:EPT_CPCR_CMD,EPT_CPCR_Source_X,EPT_CDUTY_X,EPT_CPCR_OSPWTH,EPT_CPCR_CDIV +//EPT_CPCR_CMD:EPT_CPCR_ENALBE,EPT_CPCR_Disable +//EPT_CPCR_Source_X:EPT_CPCR_Source_TCLK,EPT_CPCR_Source_TIN_BT0OUT,EPT_CPCR_Source_TIN_BT1OUT +//EPT_CDUTY_X:EPT_CDUTY_7_8~EPT_CDUTY_DIS +//EPT_CPCR_OSPWTH:0~0X1F +//EPT_CPCR_CDIV:0~0xf +//ReturnValue:NONE +/*************************************************************/ +//Fchop=PCLK/((CDIV+1)/8) //Carrier frequency setting (CDIV>=1) +//Twidth=Tchop*OSPWTH //First pulse width setting +void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV) +{ + if(EPT_CPCR_Source_X==EPT_CPCR_Source_TCLK) + { + EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x00<<14); + } + else + { + EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x01<<14); + if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT0OUT) + { + EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x01<<4); + } + if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT1OUT) + { + EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x02<<4); + } + } +} +/*************************************************************/ +//Deinitializes the EPT DBCR Config +//EntryParameter:EPT_CHX_Selecte,EPT_INSEL_X,EPT_OUTSEL_X,EPT_OUT_POLARITY_X,EPT_OUT_SWAP_X +//EPT_CHX_Selecte:EPT_CHA_Selecte,EPT_CHB_Selecte,EPT_CHC_Selecte +//EPT_INSEL_X:EPT_PWMA_RISE_FALL,EPT_PWMB_RISE_PWMA_FALL,EPT_PWMA_RISE_PWMB_FALL,EPT_PWMB_RISE_FALL +//EPT_OUTSEL_X:EPT_OUTSEL_PWMA_PWMB_Bypass,EPT_OUTSEL_DisRise_EnFall,EPT_OUTSEL_EnRise_DisFall,EPT_OUTSEL_EnRise_EnFall +//EPT_OUT_POLARITY_X:EPT_PA_PB_OUT_Direct,EPT_PA_OUT_Reverse,EPT_PB_OUT_Reverse,EPT_PA_PB_OUT_Reverse +//EPT_OUT_SWAP_X:EPT_PAtoCHX_PBtoCHY,EPT_PBtoCHX_PBtoCHY,EPT_PAtoCHX_PAtoCHY,EPT_PBtoCHX_PAtoCHY +//ReturnValue:NONE +/*************************************************************/ +void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X) +{ + if(EPT_CHX_Selecte==EPT_CHA_Selecte) + { + EPT0->DBCR=(EPT0->DBCR&0XFFFFFF00)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<2)|(EPT_OUT_SWAP_X<<6); + } + else if(EPT_CHX_Selecte==EPT_CHB_Selecte) + { + EPT0->DBCR=(EPT0->DBCR&0XFFFF00FF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<10)|(EPT_OUT_SWAP_X<<14); + } + else if(EPT_CHX_Selecte==EPT_CHC_Selecte) + { + EPT0->DBCR=(EPT0->DBCR&0XFF00FFFF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<18)|(EPT_OUT_SWAP_X<<22); + } + EPT0->DBCR|=0x01<<24; +} +/*************************************************************/ +//Deinitializes the EPT DB CLK Config +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +//Fdbclk=Fhclk/(DPSC+1) +void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF) +{ + EPT0->DPSCR=DPSC; + EPT0->DBDTR=DTR; + EPT0->DBDTF=DTF; +} +/*************************************************************/ +//Deinitializes the EPT PWMA~PWMD Control +//EntryParameter:EPT_PWMX_Selecte,EPT_CA_Selecte_X,EPT_CB_Selecte_X, +//EPT_PWMX_Selecte:EPT_PWMA,EPT_PWMB,EPT_PWMC,EPT_PWMD +//EPT_CA_Selecte_X:EPT_CA_Selecte_CMPA,EPT_CA_Selecte_CMPB,EPT_CA_Selecte_CMPC,EPT_CA_Selecte_CMPD +//EPT_CB_Selecte_X:EPT_CB_Selecte_CMPA,EPT_CB_Selecte_CMPB,EPT_CB_Selecte_CMPC,EPT_CB_Selecte_CMPD +//ReturnValue:NONE +/*************************************************************/ +void EPT_PWMX_Output_Control( + EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X , + EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output , + EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output , + EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output , + EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output , + EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output + ) +{ + if(EPT_PWMX_Selecte==EPT_PWMA) + { + EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + } + else if(EPT_PWMX_Selecte==EPT_PWMB) + { + EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + } + else if(EPT_PWMX_Selecte==EPT_PWMC) + { + EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + } + else if(EPT_PWMX_Selecte==EPT_PWMD) + { + EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + } + +} +/*************************************************************/ +//Deinitializes the EPT Tevent selecte +//EntryParameter:EPT_T1_Selecte,EPT_T2_Selecte +//EPT_T1_Selecte:0->SYNCUSR4,1->EP0,2->EP1,3->EP2,4->EP3,5->EP4,6->EP5,7->EP6 +//EPT_T2_Selecte:0->SYNCUSR5,1->EP0,2->EP1,3->EP2,4->EP3,5->EP4,6->EP5,7->EP6 +//ReturnValue:NONE +/*************************************************************/ +void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte) +{ + EPT0->AQTSCR=EPT_T1_Selecte|(EPT_T2_Selecte<<4); +} +/*************************************************************/ +//Deinitializes the EPT PHSEN Config +//EntryParameter:EPT_PHSEN_CMD,EPT_PHSDIR,PHSR +//EPT_PHSEN_CMD:EPT_PHSEN_EN,EPT_PHSEN_DIS +//EPT_PHSDIR:EPT_PHSDIR_increase,EPT_PHSEN_decrease +//PHSR:0~0xffff +//ReturnValue:NONE +/*************************************************************/ +void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR) +{ + EPT0->CR=(EPT0->CR&0xffffff7f)|EPT_PHSEN_CMD; + EPT0->PHSR=PHSR|EPT_PHSDIR; +} +/*************************************************************/ +//Deinitializes the EPT PRDR CMPA CMPB CMPC CMPD_Config +//EntryParameter:EPT_PRDR_Value,EPT_CMPA_Value,EPT_CMPB_Value,EPT_CMPC_Value,EPT_CMPD_Value +//EPT_PRDR_Value:0~0xff +//EPT_CMPA_Value:0~0xff +//EPT_CMPB_Value:0~0xff +//EPT_CMPC_Value:0~0xff +//EPT_CMPD_Value:0~0xff +/*************************************************************/ +void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value) +{ + EPT0->PRDR=EPT_PRDR_Value; + EPT0->CMPA=EPT_CMPA_Value; + EPT0->CMPB=EPT_CMPB_Value; + EPT0->CMPC=EPT_CMPC_Value; + EPT0->CMPD=EPT_CMPD_Value; +} +/*************************************************************/ +//Deinitializes the EPT SYNCR Rearm +//EntryParameter:EPT_REARMX,EPT_REARM_MODE +//EPT_REARMX:EPT_REARM_SYNCEN0,EPT_REARM_SYNCEN1,EPT_REARM_SYNCEN2,EPT_REARM_SYNCEN3,EPT_REARM_SYNCEN4,EPT_REARM_SYNCEN5 +//ReturnValue:NONE +/*************************************************************/ +void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX ) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->SYNCR = (EPT0->SYNCR&0X3FC0FFFF)|EPT_REARMX; +} +/*************************************************************/ +//Deinitializes the EPT Caputer Rearm +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +//EPT Caputer Rearm:clear counter， enable CAPLDEN automatic +void EPT_Caputure_Rearm(void) +{ + EPT0->CR=(EPT0->CR&0xfffdffff)|(0x01<<19); +} +/*************************************************************/ +//Deinitializes the EPT Globle Event Load +//EntryParameter:EPT_GLDMD_Selecte_X,GLDCFG_EN,EPT_GLD_OneShot_CMD,GLDPRD_CNT +//EPT_GLD_OneShot_CMD:EPT_GLD_OneShot_DIS,EPT_GLD_OneShot_EN +//EPT_GLDMD_Selecte_X:EPT_GLDMD_Selecte_ZRO,EPT_GLDMD_Selecte_PRD,EPT_GLDMD_Selecte_ZRO_PRD,EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC +//EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC,EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC, +//GLDPRD_CNT:0~7(0->Trigger immediately,1->trigger when the event happens the 2nd time,7->trigger when the event happens the 7th time) +//GLDCFG_EN:0~0x3fff +//ReturnValue:NONE +/*************************************************************/ +//PRDR/CMPA/CMPB/CMPC/CMPD/DBDTR/DBCR/AQCRA/AQCRB/AQCRD/AQCSF/EMPSR load config +void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN) +{ + EPT0->GLDCR=0X01|EPT_GLD_OneShot_CMD|EPT_GLDMD_Selecte_X|(GLDPRD_CNT<<7); + EPT0->GLDCFG=GLDCFG_EN; + /*if(EPT_GLDMD_Selecte_X==EPT_GLDMD_Selecte_SW) + { + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->GLDCR2=0X02; + }*/ +} +/*************************************************************/ +//Deinitializes the EPT Globle SW Load +//EntryParameter:GLDCFG_EN +//GLDCFG_EN:0X0~0X3FFF +//EPT_GLDMD_Selecte_X: +/*************************************************************/ +//PRDR/CMPA/CMPB/CMPC/CMPD/DBDTR/DBCR/AQCRA/AQCRB/AQCRD/AQCSF/EMPSR load config +void EPT_Globle_SwLoad_CMD(void) +{ + //EPT0->GLDCR=0X01|EPT_GLDMD_Selecte_SW; + //EPT0->GLDCFG=GLDCFG_EN; + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->GLDCR2=0X03; +} +/*************************************************************/ +//Deinitializes the EPT PRDR Load +//EntryParameter:EPT_PRDR_EventLoad_x +//EPT_PRDR_EventLoad_x:EPT_PRDR_EventLoad_PEND,EPT_PRDR_EventLoad_ExiLoad_SYNC,EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC, +//EPT_PRDR_EventLoad_Immediate +/*************************************************************/ +void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x) +{ + EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations + EPT0->CR=(EPT0->CR&0xffffffcf)|EPT_PRDR_EventLoad_x; +} +/*************************************************************/ +//Deinitializes the EPT CMPX Load Config +//EntryParameter:EPT_CMPX_EventLoad_x +//EPT_CMPX_EventLoad_x:EPT_CMPX_EventLoad_DIS,EPT_CMPX_EventLoad_Immediate,EPT_CMPX_EventLoad_ZRO, +//EPT_CMPX_EventLoad_PRD,EPT_CMPX_EventLoad_ExiLoad_SYNC +/*************************************************************/ +//Unified load register:CMPA,CMPB,CMPC,CMPD +void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x) +{ + EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations + if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_DIS) + { + EPT0->CMPLDR=0; + } + else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_Immediate) + { + EPT0->CMPLDR=0xf; + } + else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ZRO) + { + EPT0->CMPLDR=0x2410; + } + else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_PRD) + { + EPT0->CMPLDR=0x4920; + } + else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ExiLoad_SYNC) + { + EPT0->CMPLDR=0x8240; + } +} +/*************************************************************/ +//Deinitializes the EPT AQCRX Load Config +//EntryParameter:EPT_AQCRX_EventLoad_X +//EPT_AQCRX_EventLoad_X:EPT_AQCRX_EventLoad_DIS,EPT_AQCRX_EventLoad_Immediate,EPT_AQCRX_EventLoad_ZRO, +//EPT_AQCRX_EventLoad_PRD,EPT_AQCRX_EventLoad_ExiLoad_SYNC +/*************************************************************/ +//Unified load register:AQCRA,AQCRB,AQCRC,AQCRD +void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X) +{ + EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations + if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_DIS) + { + EPT0->AQLDR=0; + } + else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_Immediate) + { + EPT0->AQLDR=0x303; + } + else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ZRO) + { + EPT0->AQLDR=0x2424; + } + else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_PRD) + { + EPT0->AQLDR=0x4848; + } + else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ExiLoad_SYNC) + { + EPT0->AQLDR=0x9090; + } +} +/*************************************************************/ +//Deinitializes the EPT DB Load Config +//EntryParameter:EPT_DB_EventLoad_X +//EPT_DB_EventLoad_X:EPT_DB_EventLoad_DIS,EPT_DB_EventLoad_Immediate,EPT_DB_EventLoad_ZRO, +//EPT_DB_EventLoad_PRD,EPT_DB_EventLoad_ZRO_PRD +/*************************************************************/ +//Unified load register:DBCR,DBDTR,DBDTF,DPSCR +void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X) +{ + EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations + if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_DIS) + { + EPT0->DBLDR=0X249; + } + else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_Immediate) + { + EPT0->DBLDR=0; + } + else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO) + { + EPT0->DBLDR=0X249|(0X01<<1)|(0X01<<4)|(0X01<<7)|(0X01<<10); + } + else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_PRD) + { + EPT0->DBLDR=0X249|(0X02<<1)|(0X02<<4)|(0X02<<7)|(0X02<<10); + } + else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO_PRD) + { + EPT0->DBLDR=0X249|(0X03<<1)|(0X03<<4)|(0X03<<7)|(0X03<<10); + } +} +/*************************************************************/ +//EPT EVTRG Config +//EntryParameter:EPT_TRGSRCX_Select,EPT_EVTRG_TRGSRCX_X,EPT_TRGSRCX_CMD,TRGEVXPRD +//EPT_TRGSRCX_Select:EPT_TRGSRC0,EPT_TRGSRC1,EPT_TRGSRC2,EPT_TRGSRC3 +//EPT_EVTRG_TRGSRCX_X: +//EPT_TRGSRCX_CMD: +//TRGEVXPRD:0~0xf +//ReturnValue: NONE +/*************************************************************/ +void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD) +{ + if(EPT_TRGSRCX_Select==EPT_TRGSRC0) + { + EPT0->EVTRG=(EPT0->EVTRG&0xffeffff0)|(EPT_EVTRG_TRGSRCX_X<<0)|(EPT_TRGSRCX_CMD<<20); + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC1) + { + EPT0->EVTRG=(EPT0->EVTRG&0xffdfff0f)|(EPT_EVTRG_TRGSRCX_X<<4)|(EPT_TRGSRCX_CMD<<21); + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC2) + { + EPT0->EVTRG=(EPT0->EVTRG&0xffbff0ff)|(EPT_EVTRG_TRGSRCX_X<<8)|(EPT_TRGSRCX_CMD<<22); + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC3) + { + EPT0->EVTRG=(EPT0->EVTRG&0xff7f0fff)|(EPT_EVTRG_TRGSRCX_X<<12)|(EPT_TRGSRCX_CMD<<23); + } + EPT0->EVTRG|=0x0f0f0000; +} +/*************************************************************/ +//EPT EVTRG SWFTRG +//EntryParameter:EPT_TRGSRCX_Select +//EPT_TRGSRCX_Select:EPT_TRGSRC0,EPT_TRGSRC1,EPT_TRGSRC2,EPT_TRGSRC3 +//ReturnValue: NONE +/*************************************************************/ +void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select) +{ + if(EPT_TRGSRCX_Select==EPT_TRGSRC0) + { + EPT0->EVSWF|=0X01; + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC1) + { + EPT0->EVSWF|=0X02; + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC2) + { + EPT0->EVSWF|=0X04; + } + else if(EPT_TRGSRCX_Select==EPT_TRGSRC3) + { + EPT0->EVSWF|=0X08; + } +} +/*************************************************************/ +//EPT INT ENABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT) +{ + EPT0->ICR = EPT_X_INT; //clear LVD INT status + EPT0->IMCR |= EPT_X_INT; +} +/*************************************************************/ +//EPT INT DISABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT) +{ + EPT0->IMCR &= ~EPT_X_INT; +} +/*************************************************************/ +//EPT EMINT ENABLE. +//EntryParameter:EPT_X_EMINT +//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT +//ReturnValue: NONE +/*************************************************************/ +void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT) +{ + EPT0->EMICR = EPT_X_EMINT; //clear LVD INT status + EPT0->EMIMCR |= EPT_X_EMINT; +} +/*************************************************************/ +//EPT EMINT DISABLE. +//EntryParameter:EPT_X_EMINT +//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT +//ReturnValue: NONE +/*************************************************************/ +void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT) +{ + EPT0->EMIMCR &= ~EPT_X_EMINT; +} +/*************************************************************/ +//EPT INT VECTOR enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Vector_Int_Enable(void) +{ + INTC_ISER_WRITE(EPT0_INT); +} +/*************************************************************/ +//EPT INT VECTOR disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Vector_Int_Disable(void) +{ + INTC_ICER_WRITE(EPT0_INT); +} +/*************************************************************/ +//Deinitializes the EPT EP0~EP7 Config +//EntryParameter:EPT_EPX,EPT_Input_selecte_x,EPT_FLT_PACE0_x,EPT_FLT_PACE1_x,EPT_EPIX_POL +//EPT_EPX:EPT_EP0,EPT_EP1,EPT_EP2,EPT_EP3,EPT_EP4,EPT_EP5,EPT_EP6,EPT_EP7 +//EPT_Input_selecte_x:EPT_Input_selecte_EPI0~EPT_Input_selecte_EPI5,EPT_Input_selecte_ORL0,EPT_Input_selecte_ORL1 +//EPT_FLT_PACE0_x:EPT_FLT_PACE0_DIS~EPT_FLT_PACE0_4CLK(EP0~EP3) +//EPT_FLT_PACE1_x:EPT_FLT_PACE1_DIS~EPT_FLT_PACE1_4CLK(EP4~EP7) +//ReturnValue:NONE +/*************************************************************/ +void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + if(EPT_EPX==EPT_EP0) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFFF0)|(EPT_Input_selecte_x<<0); + } + else if(EPT_EPX==EPT_EP1) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFF0F)|(EPT_Input_selecte_x<<4); + } + else if(EPT_EPX==EPT_EP2) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFFFFF0FF)|(EPT_Input_selecte_x<<8); + } + else if(EPT_EPX==EPT_EP3) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFFFF0FFF)|(EPT_Input_selecte_x<<12); + } + else if(EPT_EPX==EPT_EP4) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFFF0FFFF)|(EPT_Input_selecte_x<<16); + } + else if(EPT_EPX==EPT_EP5) + { + EPT0->EMSRC=(EPT0->EMSRC&0XFF0FFFFF)|(EPT_Input_selecte_x<<20); + } + else if(EPT_EPX==EPT_EP6) + { + EPT0->EMSRC=(EPT0->EMSRC&0XF0FFFFFF)|(EPT_Input_selecte_x<<24); + } + else if(EPT_EPX==EPT_EP7) + { + EPT0->EMSRC=(EPT0->EMSRC&0X0FFFFFFF)|(EPT_Input_selecte_x<<28); + } + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->EMSRC2=ORL0_EPIx|(ORL1_EPIx<<16)|EPT_FLT_PACE0_x|EPT_FLT_PACE1_x; +} +/*************************************************************/ +//Deinitializes EPT_EPIX POL Config +//EntryParameter:EPT_EPIX_POL +//EPT_EPIX_POL:BIT0->EPI0(0:Active high 1:Active low),BIT1->EPI1(0:Active high 1:Active low), +//BIT2->EPI2(0:Active high 1:Active low),BIT3->EPI3(0:Active high 1:Active low),BIT4->EPI4(0:Active high 1:Active low) +//ReturnValue:NONE +/*************************************************************/ +void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->EMPOL=EPT_EPIX_POL; +} +/*************************************************************/ +//EPT EM Config +//EntryParameter:EPT_LKCR_TRG_X,EPT_LKCR_Mode_X +//EPT_LKCR_TRG_X:EPT_LKCR_TRG_EP0~EPT_LKCR_TRG_EP7,EPT_LKCR_TRG_CPU_FAULT,EPT_LKCR_TRG_MEM_FAULT,EPT_LKCR_TRG_EOM_FAULT +//EPT_LKCR_Mode_X:EPT_LKCR_Mode_LOCK_DIS,EPT_LKCR_Mode_SLOCK_EN,EPT_LKCR_Mode_HLOCK_EN,EPT_LKCR_TRG_X_FAULT_HLOCK_EN,EPT_LKCR_TRG_X_FAULT_HLOCK_DIS +//ReturnValue:NONE +/*************************************************************/ +void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->EMECR|=(0X01<<21)|(0X01<<22)|(0X02<<24); //EMOSR CNT=ZRO load，Automatically clear soft lock when CNT=ZRO&PRD + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_CPU_FAULT) + { + if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN) + { + EPT0->EMECR|=(0x01<<28); + } + else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS) + { + EPT0->EMECR&=~(0x01<<28); + } + } + else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_MEM_FAULT) + { + if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN) + { + EPT0->EMECR|=(0x01<<29); + } + else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS) + { + EPT0->EMECR&=~(0x01<<29); + } + } + else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_EOM_FAULT) + { + if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN) + { + EPT0->EMECR|=(0x01<<30); + } + else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS) + { + EPT0->EMECR&=~(0x01<<30); + } + } + else + { + EPT0->EMECR|=(EPT_LKCR_Mode_X<<(EPT_LKCR_TRG_X))|(0X01<<26); + } +} +/*************************************************************/ +//EPT EM Config +//EntryParameter:EPT_OUTPUT_Channel_X,EPT_SHLOCK_OUTPUT_X +//EPT_OUTPUT_Channel_X:EPT_OUTPUT_Channel_CHAX,EPT_OUTPUT_Channel_CHAY,EPT_OUTPUT_Channel_CHBX,EPT_OUTPUT_Channel_CHBY +//EPT_OUTPUT_Channel_CHCX,EPT_OUTPUT_Channel_CHCY,EPT_OUTPUT_Channel_CHD +//EPT_SHLOCK_OUTPUT_X:EPT_SHLOCK_OUTPUT_HImpedance,EPT_SHLOCK_OUTPUT_High,EPT_SHLOCK_OUTPUT_Low,EPT_SHLOCK_OUTPUT_Nochange +//ReturnValue:NONE +/*************************************************************/ +void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->EMOSR|=EPT_SHLOCK_OUTPUT_X<EMSLCLR|=EPT_X_EMINT; +} +/*************************************************************/ +//EPT H lock clr +//EntryParameter:EPT_X_EMINT +//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT +//ReturnValue:NONE +/*************************************************************/ +void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT) +{ + EPT0->EMHLCLR|=EPT_X_EMINT; +} +/*************************************************************/ +//EPT software lock SET +//EntryParameter:EPT_X_EMINT +//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT +//ReturnValue:NONE +/*************************************************************/ +void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + EPT0->EMFRCR|=EPT_X_EMINT; +} +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_et.c b/Source/FWlib/apt32f102_et.c new file mode 100644 index 0000000..f633abc --- /dev/null +++ b/Source/FWlib/apt32f102_et.c @@ -0,0 +1,274 @@ +/* + ****************************************************************************** + * @file apt32f102_et.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + + + /* Includes ------------------------------------------------------------------*/ +#include "apt32f102_et.h" + + +/*************************************************************/ +//ET RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ET_DeInit(void) +{ + ETCB->EN = ET_RESET_VALUE; + ETCB->SWTRG = ET_RESET_VALUE; + ETCB->CH0CON0 = ET_RESET_VALUE; + ETCB->CH0CON1 = ET_RESET_VALUE; + ETCB->CH1CON0 = ET_RESET_VALUE; + ETCB->CH1CON1 = ET_RESET_VALUE; + ETCB->CH2CON0 = ET_RESET_VALUE; + ETCB->CH2CON1 = ET_RESET_VALUE; + ETCB->CH3CON = ET_RESET_VALUE; + ETCB->CH4CON = ET_RESET_VALUE; + ETCB->CH5CON = ET_RESET_VALUE; + ETCB->CH6CON = ET_RESET_VALUE; + ETCB->CH7CON = ET_RESET_VALUE; +} +/*************************************************************/ +//ET ENABLE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ET_ENABLE(void) +{ + ETCB->EN = 0x01; +} +/*************************************************************/ +//ET DISABLE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ET_DISABLE(void) +{ + ETCB->EN = 0x00; +} +/*************************************************************/ +//ET SWTRG Configure +//EntryParameter:ETSWTRG_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_SWTRG_CMD(CRC_ETSWTRG_TypeDef ETSWTRG_X,FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + ETCB->SWTRG |= ETSWTRG_X; + } + else + { + ETCB->SWTRG &= ~ETSWTRG_X; + } +} +/*************************************************************/ +//ET CH0 source selection Configure +//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH0_SRCSEL(CRC_ESRCSEL_TypeDef ESRCSEL_X,FunctionalStatus NewState,U8_T SRCSEL_X) +{ + if (NewState != DISABLE) + { + if(ESRCSEL_X==0) + { + ETCB->CH0CON0 |= 0X01| (SRCSEL_X<<1); + } + if(ESRCSEL_X==1) + { + ETCB->CH0CON0 |= (0X01<<10)| (SRCSEL_X<<11); + } + if(ESRCSEL_X==2) + { + ETCB->CH0CON0 |= (0X01<<20)| (SRCSEL_X<<21); + } + } + else + { + if(ESRCSEL_X==0) + { + ETCB->CH0CON0 &= 0X01| (SRCSEL_X<<1); + } + if(ESRCSEL_X==1) + { + ETCB->CH0CON0 &= (0X00<<10)| (SRCSEL_X<<11); + } + if(ESRCSEL_X==2) + { + ETCB->CH0CON0 &= (0X00<<20)| (SRCSEL_X<<21); + } + } +} +/*************************************************************/ +//ET CHO CONTROL Configure +//EntryParameter:NewState,TRIGMODEX,DSTSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH0_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + ETCB->CH0CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX; + } + else + { + ETCB->CH0CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX; + } + +} +/*************************************************************/ +//ET CHI1 source selection Configure +//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH1_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + if(DST_X==0) + { + ETCB->CH1CON0 |= 0X01| (DSTSEL_X<<1); + } + if(DST_X==1) + { + ETCB->CH1CON0 |= (0X01<<10)| (DSTSEL_X<<11); + } + if(DST_X==2) + { + ETCB->CH1CON0 |= (0X01<<20)| (DSTSEL_X<<21); + } + } + else + { + if(DST_X==0) + { + ETCB->CH1CON0 &= 0X01| (DSTSEL_X<<1); + } + if(DST_X==1) + { + ETCB->CH1CON0 &= (0X00<<10)| (DSTSEL_X<<11); + } + if(DST_X==2) + { + ETCB->CH1CON0 &= (0X00<<20)| (DSTSEL_X<<21); + } + } +} +/*************************************************************/ +//ET CH1 CONTROL Configure +//EntryParameter:NewState,TRIGMODEX,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH1_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + ETCB->CH1CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX; + } + else + { + ETCB->CH1CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX; + } + +} +/*************************************************************/ +//ET CHI2 source selection Configure +//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH2_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + if(DST_X==0) + { + ETCB->CH2CON0 |= 0X01| (DSTSEL_X<<1); + } + if(DST_X==1) + { + ETCB->CH2CON0 |= (0X01<<10)| (DSTSEL_X<<11); + } + if(DST_X==2) + { + ETCB->CH2CON0 |= (0X01<<20)| (DSTSEL_X<<21); + } + } + else + { + if(DST_X==0) + { + ETCB->CH2CON0 &= 0X01| (DSTSEL_X<<1); + } + if(DST_X==1) + { + ETCB->CH2CON0 &= (0X00<<10)| (DSTSEL_X<<11); + } + if(DST_X==2) + { + ETCB->CH2CON0 &= (0X00<<20)| (DSTSEL_X<<21); + } + } +} +/*************************************************************/ +//ET CH2 CONTROL Configure +//EntryParameter:NewState,TRIGMODEX,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CH2_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + ETCB->CH2CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX; + } + else + { + ETCB->CH2CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX; + } + +} +/*************************************************************/ +//ET CH3~7 source selection/CONTROL Configure +//EntryParameter:NewState,TRIGMODEX,SRCSEL_X +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ET_CHx_CONTROL(CRC_ETCHX_TypeDef ETCHX,FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T SRCSEL_X,U8_T DSTSEL_X) +{ + if (NewState != DISABLE) + { + if(ETCHX==0)ETCB->CH3CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==1)ETCB->CH4CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==2)ETCB->CH5CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==3)ETCB->CH6CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==4)ETCB->CH7CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + } + else + { + if(ETCHX==0)ETCB->CH3CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==1)ETCB->CH4CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==2)ETCB->CH5CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==3)ETCB->CH6CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + if(ETCHX==4)ETCB->CH7CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX; + } +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_gpio.c b/Source/FWlib/apt32f102_gpio.c new file mode 100644 index 0000000..15c6744 --- /dev/null +++ b/Source/FWlib/apt32f102_gpio.c @@ -0,0 +1,508 @@ +/* + ****************************************************************************** + * @file main.c + * @author APT AE Team + * @version V1.10 + * @date 2021/08/25 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_gpio.h" + +/* define --------------------------------------------------------------------*/ + +/* externs--------------------------------------------------------------------*/ +/*************************************************************/ +//IO RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPIO_DeInit(void) +{ + GPIOA0->CONLR &= 0xFF000000; + GPIOA0->CONHR = GPIO_RESET_VALUE; + GPIOB0->CONLR = GPIO_RESET_VALUE; + GPIOB0->CONHR = GPIO_RESET_VALUE; + GPIOA0->WODR = GPIO_RESET_VALUE; + GPIOB0->WODR = GPIO_RESET_VALUE; + GPIOA0->SODR = GPIO_RESET_VALUE; + GPIOB0->SODR = GPIO_RESET_VALUE; + GPIOA0->CODR = GPIO_RESET_VALUE; + GPIOB0->CODR = GPIO_RESET_VALUE; + GPIOA0->ODSR = GPIO_RESET_VALUE; + GPIOB0->ODSR = GPIO_RESET_VALUE; + GPIOA0->PSDR = GPIO_RESET_VALUE; + GPIOB0->PSDR = GPIO_RESET_VALUE; + GPIOA0->FLTEN = 0xffff; + GPIOB0->FLTEN = 0x3f; + GPIOA0->PUDR = GPIO_RESET_VALUE; + GPIOB0->PUDR = GPIO_RESET_VALUE; + GPIOA0->DSCR = GPIO_RESET_VALUE; + GPIOB0->DSCR = GPIO_RESET_VALUE; + GPIOA0->OMCR = GPIO_RESET_VALUE; + GPIOB0->OMCR = GPIO_RESET_VALUE; + GPIOA0->IECR = GPIO_RESET_VALUE; + GPIOB0->IECR = GPIO_RESET_VALUE; + GPIOGRP->IGRPL = GPIO_RESET_VALUE; + GPIOGRP->IGRPH = GPIO_RESET_VALUE; + GPIOGRP->IGREX = GPIO_RESET_VALUE; + GPIOGRP->IO_CLKEN = 0xf; +} +/*************************************************************/ +//IO OUTPUT INPUT SET 2 +//EntryParameter:GPIOx,byte,val +//GPIOx:GPIOA0,GPIOB0 +//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15) +//val:0x0000000~0xFFFFFFFF +//val=0x11111111 all IO as input +//val=0x22222222 all IO as output +//ReturnValue:NONE +/*************************************************************/ +void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val) +{ + if (byte==0) + { + (GPIOx)->CONLR=val; + } + else if(byte==1) + { + (GPIOx)->CONHR=val; + } +} +/*************************************************************/ +//IO OUTPUT INPUT SET 1 +//EntryParameter:GPIOx,GPIO_Pin(0~15),byte,Dir +//GPIOx:GPIOA0,GPIOB0 +//GPIO_Pin:PIN_0~15 +//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15) +//Dir:0:output 1:input +//ReturnValue:NONE +/*************************************************************/ +void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir) +{ + uint32_t data_temp; + uint8_t GPIO_Pin; + if(PinNum<8) + { + switch (PinNum) + { + case 0:data_temp=0xfffffff0;GPIO_Pin=0;break; + case 1:data_temp=0xffffff0f;GPIO_Pin=4;break; + case 2:data_temp=0xfffff0ff;GPIO_Pin=8;break; + case 3:data_temp=0xffff0fff;GPIO_Pin=12;break; + case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break; + case 5:data_temp=0xff0fffff;GPIO_Pin=20;break; + case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break; + case 7:data_temp=0x0fffffff;GPIO_Pin=28;break; + } + if (Dir) + { + (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<CONLR = ((GPIOx)->CONLR & data_temp) | 2<CONHR = ((GPIOx)->CONHR & data_temp) | 1<CONHR = ((GPIOx)->CONHR & data_temp) | 2<CONLR = (GPIOx)->CONLR & data_temp; + } + else if (PinNum<16) + { + switch (PinNum) + { + case 8:data_temp=0xfffffff0;break; + case 9:data_temp=0xffffff0f;break; + case 10:data_temp=0xfffff0ff;break; + case 11:data_temp=0xffff0fff;break; + case 12:data_temp=0xfff0ffff;break; + case 13:data_temp=0xff0fffff;break; + case 14:data_temp=0xf0ffffff;break; + case 15:data_temp=0x0fffffff;break; + } + (GPIOx)->CONHR = (GPIOx)->CONHR & data_temp; + } +} +/*************************************************************/ +//IO OUTPUT INPUT SET +//EntryParameter:IO_MODE,GPIOx,val +//GPIOx:GPIOA0,GPIOB0 +//IO_MODE:PUDR(IO PULL HIGH/LOW) +//IO_MODE:DSCR(IO DRIVE STRENGHT) +//IO_MODE:OMCR(OUTPUT MODE SET) +//IO_MODE:IECR(IO INT ENABLE) +//ReturnValue:NONE +/*************************************************************/ +void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val) +{ + switch (IO_MODE) + { + case PUDR:(GPIOx)->PUDR = val;break; + case DSCR:(GPIOx)->DSCR = val;break; + case OMCR:(GPIOx)->OMCR = val;break; + case IECR:(GPIOx)->IECR = val;break; + } +} +/*************************************************************/ +//Write GPIO pull high/low +//EntryParameter:GPIOx,uint8_t bit +//GPIOx:GPIOA0,GPIOB0 +//bit:0~15 +//ReturnValue:VALUE +/*************************************************************/ +void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x01<<(bit*2)); +} +void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x02<<(bit*2)); +} +void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->PUDR = ((GPIOx)->PUDR) & ~(0x03<<(bit*2)); +} +/*************************************************************/ +//Write GPIO open drain init +//EntryParameter:GPIOx,uint8_t bit +//GPIOx:GPIOA0,GPIOB0 +//bit:0~15 +//ReturnValue:VALUE +/*************************************************************/ +void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<OMCR = ((GPIOx)->OMCR) & ~(0x01<DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2+1)); + } + else + { + (GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2+1)); + if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL1) + { + (GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<<(bit+16)); + } + else if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL2) + { + (GPIOx)->OMCR = ((GPIOx)->OMCR) & ~(0x01<<(bit+16)); + } + } +} +/*************************************************************/ +//Write GPIO Drive Strength init +//EntryParameter:GPIOx,uint8_t bit +//GPIOx:GPIOA0,GPIOB0 +//bit:0~15 +//ReturnValue:VALUE +/*************************************************************/ +void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2)); +} +void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2)); +} +/*************************************************************/ +//IO OUTPUT INPUT SET +//EntryParameter: +//IO_MODE:IGRP(IO INT GROUP) +//PinNum：0~15 +//SYSCON_EXIPIN_TypeDef:EXI_PIN0~EXI_PIN19 +//EXI0~EXI15:GPIOA0,GPIOB0 +//EXI16~EXI17:GPIOA0.0~GPIOA0.7 +//EXI18~EXI19:GPIOB0.0~GPIOB0.3 +//ReturnValue:NONE +/*************************************************************/ +void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef Selete_EXI_x) +{ + volatile unsigned int R_data_temp; + volatile unsigned char R_GPIO_Pin; + if(Selete_EXI_x<16) + { + if((Selete_EXI_x==0)||(Selete_EXI_x==8)) + { + R_data_temp=0xfffffff0; + R_GPIO_Pin=0; + } + else if((Selete_EXI_x==1)||(Selete_EXI_x==9)) + { + R_data_temp=0xffffff0f; + R_GPIO_Pin=4; + } + else if((Selete_EXI_x==2)||(Selete_EXI_x==10)) + { + R_data_temp=0xfffff0ff; + R_GPIO_Pin=8; + } + else if((Selete_EXI_x==3)||(Selete_EXI_x==11)) + { + R_data_temp=0xffff0fff; + R_GPIO_Pin=12; + } + else if((Selete_EXI_x==4)||(Selete_EXI_x==12)) + { + R_data_temp=0xfff0ffff; + R_GPIO_Pin=16; + } + else if((Selete_EXI_x==5)||(Selete_EXI_x==13)) + { + R_data_temp=0xff0fffff; + R_GPIO_Pin=20; + } + else if((Selete_EXI_x==6)||(Selete_EXI_x==14)) + { + R_data_temp=0xf0ffffff; + R_GPIO_Pin=24; + } + else if((Selete_EXI_x==7)||(Selete_EXI_x==15)) + { + R_data_temp=0x0fffffff; + R_GPIO_Pin=28; + } + if(Selete_EXI_x<8) + { + GPIOGRP->IGRPL =(GPIOGRP->IGRPL & R_data_temp) | (IO_MODE<=8)) + { + GPIOGRP->IGRPH =(GPIOGRP->IGRPH & R_data_temp) | (IO_MODE<IGREX =(GPIOGRP->IGREX)|PinNum; + } + else if(Selete_EXI_x==17) + { + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<4); + } + } + else if((IO_MODE==2)&&((Selete_EXI_x==18)||(Selete_EXI_x==19))) //PB0.0~PB0.3 + { + if(Selete_EXI_x==18) + { + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<8); + } + else if(Selete_EXI_x==19) + { + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<12); + } + } + } +} +/*************************************************************/ +//IO EXI SET +//EntryParameter:EXI_IO(EXI0~EXI13) +//ReturnValue:NONE +/*************************************************************/ +void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO) +{ + switch (EXI_IO) + { + case 0:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break; + case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break; + case 2:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break; + case 3:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break; + case 4:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break; + case 5:GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break; + case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break; + case 7:GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0X10000000;break; + case 8:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000001;break; + case 9:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0X00000010;break; + case 10:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0X00000100;break; + case 11:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0X00001000;break; + case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break; + case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break; + case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X01000000;break; + case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0X10000000;break; + } +} +void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO) +{ + switch (EXI_IO) + { + case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break; + case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break; + case 2:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0X00000100;break; + case 3:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0X00001000;break; + case 4:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0X00010000;break; + case 5:GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0X00100000;break; + default:break; + } +} +void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO) +{ + (GPIOx)->IECR |= 1<SODR = (1ul<CODR = (1ul<SODR = (1ul<CODR = (1ul<ODSR>>bit)&1ul; + { + if (dat==1) + { + (GPIOx)->CODR = (1ul<SODR = (1ul<PSDR)&(1<ODSR)&(1<CEDR = 0xBE980000; + GPT0->RSSR = GPT_RESET_VALUE; + GPT0->PSCR = GPT_RESET_VALUE; + GPT0->CR = 0X00010010; + GPT0->SYNCR = GPT_RESET_VALUE; + GPT0->GLDCR = GPT_RESET_VALUE; + GPT0->GLDCFG = GPT_RESET_VALUE; + GPT0->GLDCR2 = GPT_RESET_VALUE; + GPT0->PRDR = GPT_RESET_VALUE; + GPT0->CMPA = GPT_RESET_VALUE; + GPT0->CMPB = GPT_RESET_VALUE; + GPT0->CMPLDR = 0X00002490; + GPT0->CNT = GPT_RESET_VALUE; + GPT0->AQLDR = 0X00000024; + GPT0->AQCRA = GPT_RESET_VALUE; + GPT0->AQCRB = GPT_RESET_VALUE; + GPT0->AQOSF = 0X00000100; + GPT0->AQCSF = GPT_RESET_VALUE; + GPT0->TRGFTCR = GPT_RESET_VALUE; + GPT0->TRGFTWR = GPT_RESET_VALUE; + GPT0->EVTRG = GPT_RESET_VALUE; + GPT0->EVPS = GPT_RESET_VALUE; + GPT0->EVCNTINIT = GPT_RESET_VALUE; + GPT0->EVSWF = GPT_RESET_VALUE; + GPT0->RISR = GPT_RESET_VALUE; + GPT0->MISR = GPT_RESET_VALUE; + GPT0->IMCR = GPT_RESET_VALUE; + GPT0->ICR = GPT_RESET_VALUE; + GPT0->REGLINK = GPT_RESET_VALUE; +} +/*************************************************************/ +//GPT IO Init +//EntryParameter:GPT_CHA_PB01,GPT_CHA_PA09,GPT_CHA_PA010,GPT_CHB_PA010,GPT_CHB_PA011,GPT_CHB_PB00,GPT_CHB_PB01 +//ReturnValue:NONE +/*************************************************************/ +void GPT_IO_Init(GPT_IOSET_TypeDef IONAME) +{ + if(IONAME==GPT_CHA_PB01) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050; + } + if(IONAME==GPT_CHA_PA09) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000050; + } + if(IONAME==GPT_CHA_PA010) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000600; + } + if(IONAME==GPT_CHB_PA010) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000700; + } + if(IONAME==GPT_CHB_PA011) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00006000; + } + if(IONAME==GPT_CHB_PB00) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000004; + } + if(IONAME==GPT_CHB_PB01) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000060; + } +} + +/*************************************************************/ +//GPT Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX) +{ + GPT0->CEDR = GPTCLKX| GCSSX|GSHDWSTPX; + GPT0->PSCR=GPSCX; +} +/*************************************************************/ +//GPT Wave control Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +//GPT0->CR = (0X0<<0)|(0x00<<2)|(0x01<<3)|(0x00<<4)|(0X00<<6)|(0x01<<18)|(0x00<<9)|(0X00<<10)|(0x00<<11)|(0x00<<13) ; +//GPT0->CMPLDR=(0X00<<0)|(0X00<<1)|(0X03<<4)|(0X03<<7); +void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX, + GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX) +{ + GPT0->CR =GCNTMDX|GSWSYNX|GIDLEX|GPRDLD0|GOPMX|GBURSTX|GCKS|CGSRCX|CGFLT|PSCLDX|GPT_WAVE_MODE; +} + +/*************************************************************/ +//GPT Wave control Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX) +{ + GPT0->AQLDR=SHDWAQAX|SHDWAQBX|AQLDAX|AQLDBX; +} +/*************************************************************/ +//GPT Wave A OUT Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX, + U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX) +{ + if(GPTCHX==GPT_CHA) + { + GPT0->AQCRA=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18); + } + if(GPTCHX==GPT_CHB) + { + GPT0->AQCRB=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18); + } +} +/*************************************************************/ +//Deinitializes the GPT Caputer Config +//EntryParameter:GPT_CNTMD_SELECTE_X,GPT_CAPMD_SELECTE_X,GPT_LOAD_CMPA_RST_CMD~GPT_LOAD_CMPB_RST_CMD,GPT_STOP_WRAP,GPT_PSCR +//GPT_CNTMD_SELECTE_X:GPT_CNTMD_increase,GPT_CNTMD_decrease,GPT_CNTMD_increaseTOdecrease +//GPT_CAPMD_SELECTE_X:GPT_CAPMD_Once,GPT_CAPMD_Continue +//GPT_LOAD_CMPA_RST_CMD:GPT_LDARST_EN,GPT_LDARST_DIS +//GPT_LOAD_CMPB_RST_CMD:GPT_LDBRST_EN,GPT_LDBRST_DIS +//GPT_STOP_WRAP:0~3 +//GPT_PSCR:0~0XFFFF +//ReturnValue:NONE +/*************************************************************/ +void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD + , GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD , + GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP ) +{ + GPT0->CR=(GPT0->CR&0xf800fec0)|GPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|GPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(GPT_STOP_WRAP<<21)| + GPT_LOAD_CMPA_RST_CMD|GPT_LOAD_CMPB_RST_CMD|GPT_LOAD_CMPC_RST_CMD|GPT_LOAD_CMPD_RST_CMD; +} +/*************************************************************/ +//GPT SYNC Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx, + GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx) +{ + GPT0->SYNCR |= SYNCENx| OSTMDx| TXREARM0x |TRGO0SELx|TRGO1SELx|AREARMx; +} +/*************************************************************/ +//GPT Trigger Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx, + U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA) +{ + GPT0->TRGFTCR |= SRCSELx| BLKINVx|ALIGNMDx| CROSSMDx; + GPT0->TRGFTWR |= G_OFFSET_DATA |(G_WINDOW_DATA<<16); + +} +/*************************************************************/ +//GPT Trigger Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx, + GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt) +{ + GPT0->EVTRG |= TRGSRC0x |TRGSRC1x|ESYN0OEx|ESYN1OEx|CNT0INITx|CNT1INITx; + GPT0->EVPS |= TRGEV0prd|(TRGEV1prd<<4)|(TRGEV0cnt<<16)|(TRGEV1cnt<<20); +} +/*************************************************************/ +//GPT OneceForce Out +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX) +{ + GPT0->AQOSF =CHAFORCEX|CHBFORCEX|FORCELDX|(AFORCE_STATUS<<1)|(BFORCE_STATUS<<5); +} +/*************************************************************/ +//GPT Continue Force Out +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX) +{ + GPT0->AQCSF =FORCEAX|FORCEBX; +} +/*************************************************************/ +//GPT Wave Compare Load Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX) +{ + GPT0->CMPLDR=SHDWCMPAX|SHDWCMPBX|LDAMDX|LDBMDX; +} +/*************************************************************/ +//GPT DEBUG MODE +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Debug_Mode(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + GPT0->CEDR |= GPT_DEBUG_MODE; + } + else + { + GPT0->CEDR &= ~GPT_DEBUG_MODE; + } +} +/*************************************************************/ +// GPT start +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Start(void) +{ + GPT0->RSSR |= 0X01; +} +/*************************************************************/ +// GPT stop +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Stop(void) +{ + GPT0->RSSR &= 0XFFFFFFFE; +} +/*************************************************************/ +// GPT soft reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Soft_Reset(void) +{ + GPT0->RSSR |= (0X5<<12); +} +/*************************************************************/ +// GPT Capture rearm +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Cap_Rearm(void) +{ + GPT0->CR |= (0X01<<19); +} +/*************************************************************/ +// GPT MODE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Mode_CMD(GPT_WAVE_TypeDef WAVEX) +{ + GPT0->CR |= WAVEX; +} +/*************************************************************/ +// GPT soft reset at once sync mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_REARM_Write(void) +{ + GPT0->SYNCR |= (0X1<<16); +} +/*************************************************************/ +// GPT soft read at once sync mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U8_T GPT_REARM_Read(void) +{ + uint8_t value = 0; + uint32_t dat = 0; + dat=(GPT0->SYNCR)&(1<<16); + if (dat) + { + value = 1; + } + return value; +} +/*************************************************************/ +//GPT Period / Compare set +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA) +{ + GPT0->PRDR =PRDR_DATA; + GPT0->CMPA =CMPA_DATA; + GPT0->CMPB =CMPB_DATA; +} +/*************************************************************/ +//GPT read counters +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +U16_T GPT_PRDR_Read(void) +{ + return GPT0->PRDR; +} +U16_T GPT_CMPA_Read(void) +{ + return GPT0->CMPA; +} +U16_T GPT_CMPB_Read(void) +{ + return GPT0->CMPB; +} +U16_T GPT_CNT_Read(void) +{ + return GPT0->CNT; +} +/*************************************************************/ +//GPT inturrpt Configure +//EntryParameter:LPT_IMSCR_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X) +{ + if (NewState != DISABLE) + { + GPT0->IMCR |= GPT_IMSCR_X; + } + else + { + GPT0->IMCR &= ~GPT_IMSCR_X; + } +} + +/*************************************************************/ +//GPT Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_INT_ENABLE(void) +{ + INTC_ISER_WRITE(GPT0_INT); +} +/*************************************************************/ +//LPT Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_INT_DISABLE(void) +{ + INTC_ICER_WRITE(GPT0_INT); +} + + \ No newline at end of file diff --git a/Source/FWlib/apt32f102_hwdiv.c b/Source/FWlib/apt32f102_hwdiv.c new file mode 100644 index 0000000..a9a7c91 --- /dev/null +++ b/Source/FWlib/apt32f102_hwdiv.c @@ -0,0 +1,89 @@ +/* + ****************************************************************************** + * @file apt32f102_gpio.c + * @author APT AE Team + * @version V1.24 + * @date 2018/10/15 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_hwdiv.h" + +/* define --------------------------------------------------------------------*/ +/* externs--------------------------------------------------------------------*/ +/*************************************************************/ +//HWDIV RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void HWDIV_DeInit(void) +{ + HWD->DIVIDENT = HWDIV_RESET_VALUE; + HWD->DIVISOR = HWDIV_RESET_VALUE; + HWD->QUOTIENT = HWDIV_RESET_VALUE; + HWD->REMAIN = HWDIV_RESET_VALUE; + HWD->CR = HWDIV_RESET_VALUE; +} +/*************************************************************/ +//HWDIV UNSIGN Configure +//EntryParameter:NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void HWDIV_UNSIGN_CMD(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + HWD->CR |= HWDIV_UNSIGN_BIT; + } + else + { + HWD->CR &= ~HWDIV_UNSIGN_BIT; + } +} +/*************************************************************/ +//HWDIV Calculate +//EntryParameter:NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x) +{ + HWD->DIVIDENT=DIVIDENDx; + HWD->DIVISOR=DIVISOR_x; +} +/*************************************************************/ +//HWDIV Calculate result +//EntryParameter:NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +U32_T HWDIV_Calc_Quotient(void) +{ + return HWD->QUOTIENT; +} +/*************************************************************/ +//HWDIV Calculate result +//EntryParameter:NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +U32_T HWDIV_Calc_Remain(void) +{ + return HWD->REMAIN; +} +/*************************************************************/ +void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x) +{ + HWD->DIVIDENT=DIVIDENDx; + HWD->DIVISOR=DIVISOR_x; +} diff --git a/Source/FWlib/apt32f102_i2c.c b/Source/FWlib/apt32f102_i2c.c new file mode 100644 index 0000000..998f0e9 --- /dev/null +++ b/Source/FWlib/apt32f102_i2c.c @@ -0,0 +1,569 @@ +/* + ****************************************************************************** + * @file apt32f102_i2c.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ +#include "apt32f102_i2c.h" +volatile uint8_t I2CWrBuffer[BUFSIZE]; +volatile uint8_t I2CRdBuffer[BUFSIZE]; +volatile uint8_t RdIndex = 0; +volatile uint8_t WrIndex = 0; +volatile uint8_t I2C_Data_Adress; +volatile uint8_t I2C_St_Adress; +volatile U8_T f_ERROR=0; +volatile U32_T R_IIC_ERROR_CONT; +extern void delay_nms(unsigned int t); +/*************************************************************/ +//I2C RESET,CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_DeInit(void) +{ + I2C0->ENABLE = 0; + I2C0->IMSCR = 0; + I2C0->ICR = 0X7FFF; +} +/*************************************************************/ +//I2C MASTER Initial +//EntryParameter:SPEEDMODE,MASTERBITS, +//SPEEDMODE:FAST_MODE(>100K),STANDARD_MODE(<100K) +//MASTERBITS:I2C_MASTRER_7BIT/I2C_MASTRER_10BIT +//ReturnValue:NONE +/*************************************************************/ +void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE, + I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX) +{ + //SDA IO Initial + if(I2C_SDA_IO==I2C_SDA_PA00) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005; //PA0.0->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA03) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000; //PA0.3->SDA + } + else if (I2C_SDA_IO==I2C_SDA_PA07) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000; //PA0.7->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA013) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000; //PA0.13->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA014) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000; //PA0.14->SDA + } + //SCL IO Initial + if (I2C_SCL_IO==I2C_SCL_PB00) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006; //PB0.0->SCL + } + else if (I2C_SCL_IO==I2C_SCL_PB02) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400; //PB0.2->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA01) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050; //PA0.1->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA04) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000; //PA0.4->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA06) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000; //PA0.6->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA015) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000; //PA0.15->SCL + } + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE; + I2C0->CR =(I2C0->CR&0XFFFFF000)|I2C_MASTER_EN |I2C_SLAVE_DIS| SPEEDMODE | MASTERBITS | I2C_RESTART_EN; //Repeat start bit enable + I2C0->TADDR =I2C_MASTER_ADDS; + if(SPEEDMODE==FAST_MODE) + { + I2C0->FS_SCLH = SS_SCLHX; //SCL high time + I2C0->FS_SCLL = SS_SCLLX; //SCL low time + } + else if(SPEEDMODE==STANDARD_MODE) + { + I2C0->SS_SCLH = SS_SCLHX; //SCL high time + I2C0->SS_SCLL = SS_SCLLX; //SCL low time + } + +} +/*************************************************************/ +//I2C SLAVE Initial +//EntryParameter:SPEEDMODE,SLAVEBITS,I2C_SALVE_ADD +//SPEEDMODE:FAST_MODE(>100K),STANDARD_MODE(<100K) +//SLAVEBITS:I2C_SLAVE_7BIT/I2C_SLAVE_10BIT +//I2C_SALVE_ADD:I2C SLAVE ADDRESS +//ReturnValue:NONE +/*************************************************************/ +void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE, + I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX) +{ + //SDA IO Initial + if(I2C_SDA_IO==I2C_SDA_PA00) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005; //PA0.0->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA03) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000; //PA0.3->SDA /// + } + else if (I2C_SDA_IO==I2C_SDA_PA07) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000; //PA0.7->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA013) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000; //PA0.13->SDA + } + else if(I2C_SDA_IO==I2C_SDA_PA014) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000; //PA0.14->SDA + } + //SCL IO Initial + if (I2C_SCL_IO==I2C_SCL_PB00) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006; //PB0.0->SCL + } + else if (I2C_SCL_IO==I2C_SCL_PB02) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400; //PB0.2->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA01) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050; //PA0.1->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA04) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000; //PA0.4->SCL // + } + else if(I2C_SCL_IO==I2C_SCL_PA06) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000; //PA0.6->SCL + } + else if(I2C_SCL_IO==I2C_SCL_PA015) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000; //PA0.15->SCL + } + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE; + I2C0->CR =(I2C0->CR&0XFFFFF000)| I2C_MASTER_DIS |I2C_SLAVE_EN | SPEEDMODE | SLAVEBITS; + I2C0->SADDR = I2C_SALVE_ADDS; + if(SPEEDMODE==FAST_MODE) + { + I2C0->FS_SCLH = SS_SCLHX; //SCL high time + I2C0->FS_SCLL = SS_SCLLX; //SCL low time + } + else if(SPEEDMODE==STANDARD_MODE) + { + I2C0->SS_SCLH = SS_SCLHX; //SCL high time + I2C0->SS_SCLL = SS_SCLLX; //SCL low time + } + INTC_IPR4_WRITE(0X40400040); //setting highest INT Priority when using i2c as salve +} +/*************************************************************/ +//I2C SDA TSETUP THOLD CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD) +{ + I2C0->SDA_TSETUP=SDA_TSETUP; + I2C0->SDA_THOLD=(SDA_RX_THOLD<<16)|SDA_TX_THOLD; +} +/*************************************************************/ +//I2C INT CONFIG +//EntryParameter:I2C_RX_UNDER,I2C_RX_OVER,I2C_RX_FULL,I2C_TX_OVER +// I2C_TX_EMPTY,I2C_RD_REQ,I2C_TX_ABRT,I2C_RX_DONE +// I2C_INT_BUSY,I2C_STOP_DET,I2C_START_DET,I2C_GEN_CALL +// I2C_RESTART_DET,I2C_MST_ON_HOLD,I2C_SCL_SLOW +//NewState:ENABLE/DISABLE +//ReturnValue:NONE +/*************************************************************/ +void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE) +{ + if(NewState != DISABLE) + { + I2C0->IMSCR |= INT_TYPE; + } + else + { + I2C0->IMSCR &= (~INT_TYPE); + } +} +/*************************************************************/ +//I2C FIFO trigger data +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL) +{ + I2C0->RX_FLSEL = RX_FLSEL; + I2C0->TX_FLSEL = TX_FLSEL; +} +/*************************************************************/ +//I2C Stop +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Stop(void) +{ + I2C0->DATA_CMD = (I2C0->DATA_CMD&0XFFFFFDFF)|I2C_CMD_STOP; //Enable I2C +} +/*************************************************************/ +//I2C enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Enable(void) +{ + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_ENABLE; //Enable I2C + while((I2C0->STATUS&0x1000)!=0x1000); +} +/*************************************************************/ +//I2C disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Disable(void) +{ + I2C0->ENABLE =(I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE; //Disable I2C + while((I2C0->STATUS&0x1000)==0x1000); +} +/*************************************************************/ +//I2C Abort enable in master mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Abort_EN(void) +{ + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFD)|I2C_ABORT; //Enable Abort +} +/*************************************************************/ +//I2C Abort status +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U8_T I2C_Abort_Status(void) +{ + uint8_t value = 0; + uint32_t dat = 0; + dat=(I2C0->ENABLE)&0x02; + if (dat == 0x02) + { + value = 1; //aborting + } + return value; //no abort or abort over +} +/*************************************************************/ +//I2C RECOVER enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_SDA_Recover_EN(void) +{ + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|I2C_SDA_REC_EN; //Enable Recover Enable +} +/*************************************************************/ +//I2C RECOVER enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_SDA_Recover_DIS(void) +{ + I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|I2C_SDA_REC_DIS; //Enable Recover Disable +} +/*************************************************************/ +//I2C Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Int_Enable(void) +{ + INTC_ISER_WRITE(I2C_INT); //Enable I2C interrupt +} +/*************************************************************/ +//I2C Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Int_Disable(void) +{ + INTC_ICER_WRITE(I2C_INT); //Disable I2C interrupt +} +/*************************************************************/ +//I2C WRITE OneByte +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data) +{ + U16_T R_EEROR_CONT=0; + + I2C0->DATA_CMD = I2C_CMD_WRITE|write_adds ; + I2C0->DATA_CMD = i2c_data |I2C_CMD_STOP; + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + I2C_Disable(); + I2C_Enable(); + break; + } + } + while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + I2C_Disable(); + I2C_Enable(); + break; + } + } + while(((I2C0->STATUS) & I2C_TFE) != I2C_TFE); +} +/*************************************************************/ +//I2C WRITE nByte +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite) +{ + U16_T R_EEROR_CONT=0; + U8_T i; + I2C0->DATA_CMD = I2C_CMD_WRITE|write_adds ; + for(i=0;i=NumByteToWrite-1) + { + I2C0->DATA_CMD = *(i2c_data+i) |I2C_CMD_STOP; + } + else + { + I2C0->DATA_CMD = *(i2c_data+i); + } + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + I2C_Disable(); + I2C_Enable(); + break; + } + } + while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + I2C_Disable(); + I2C_Enable(); + break; + } + } + while(((I2C0->STATUS) & I2C_TFNF) != I2C_TFNF); + } +} +/*************************************************************/ +//I2C READ OneByte +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U8_T I2C_READ_Byte(U8_T read_adds) +{ + U8_T value; + U16_T R_EEROR_CONT=0; + I2C0->DATA_CMD = I2C_CMD_WRITE|read_adds|I2C_CMD_RESTART1; + I2C0->DATA_CMD = I2C_CMD_READ |I2C_CMD_STOP; + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + break; + } + } + while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + break; + } + } + while( (I2C0->STATUS & I2C_RFNE) != I2C_RFNE ); //Wait for RX done + value=I2C0->DATA_CMD &0XFF; + return value; +} +/*************************************************************/ +//I2C READ nByte +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite) +{ + U16_T R_EEROR_CONT=0; + U8_T i; + I2C0->DATA_CMD = I2C_CMD_WRITE|read_adds|I2C_CMD_RESTART1; + for(i=0;i=NumByteToWrite-1) + { + I2C0->DATA_CMD = I2C_CMD_READ |I2C_CMD_STOP; + } + else + { + I2C0->DATA_CMD = I2C_CMD_READ; + } + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + break; + } + } + while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working + do + { + if(R_EEROR_CONT++>=10000) + { + R_EEROR_CONT=0; + f_ERROR=1; + break; + } + } + while( (I2C0->STATUS & I2C_RFNE) != I2C_RFNE ); //Wait for RX done + *(i2c_data+i)=I2C0->DATA_CMD &0XFF; + } +} +U16_T R_READ_BUF=0; +/*************************************************************/ +//I2C slave Receive +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2C_Slave_Receive(void) +{ + + if(!(((I2C0->MISR&I2C_SCL_SLOW)==I2C_SCL_SLOW) + ||((I2C0->MISR&I2C_TX_ABRT)==I2C_TX_ABRT))) //IIC is aborted when sclk locked)) + { + if((I2C0->MISR&I2C_RX_FULL)==I2C_RX_FULL) //Data received？ + { + if(RdIndex==0) + { + RdIndex=1; + I2C_Data_Adress=I2C0->DATA_CMD&0XFF; + I2C_St_Adress=I2C_Data_Adress; + } + else + { + if(I2C_Data_AdressDATA_CMD&0XFF; + } + I2C_Data_Adress++; + } + I2C0->ICR = I2C_RX_FULL; + R_IIC_ERROR_CONT=0; + } + + if((I2C0->MISR&I2C_RD_REQ)==I2C_RD_REQ) //Read request generated + { + if(RdIndex==1) + { + RdIndex=2; + WrIndex = I2C_St_Adress; + //I2C_ConfigInterrupt_CMD(ENABLE,I2C_TX_EMPTY); + if(WrIndexDATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex]; + } + } + I2C0->ICR = I2C_RD_REQ; + R_IIC_ERROR_CONT=0; + } + + if((I2C0->MISR&I2C_TX_EMPTY)==I2C_TX_EMPTY) //IIC send empty + { + if(RdIndex==2) + { + if(WrIndex+1DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex+1]; + } + WrIndex++; + } + else + { + if(R_IIC_ERROR_CONT>10000) + { + I2C_Disable(); + I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00); + I2C_SLAVE_CONFIG(); + R_IIC_ERROR_CONT=0; + } + else + { + R_IIC_ERROR_CONT++; + } + } + I2C0->CR = I2C_TX_EMPTY; + } + + else if((I2C0->MISR&I2C_STOP_DET)==I2C_STOP_DET) + { + I2C0->ICR =I2C_STOP_DET; + if(RdIndex!=0) + { + RdIndex=0; + //I2C_ConfigInterrupt_CMD(DISABLE,I2C_TX_EMPTY); + } + R_READ_BUF=I2C0->DATA_CMD&0XFF; + R_IIC_ERROR_CONT=0; + } +} +else +{ + I2C_Disable(); + I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00); + I2C_SLAVE_CONFIG(); + RdIndex=0; + //I2C_ConfigInterrupt_CMD(ENABLE,I2C_TX_EMPTY); + I2C0->ICR = I2C_SCL_SLOW|I2C_TX_ABRT; + R_IIC_ERROR_CONT=0; + +} +} +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_ifc.c b/Source/FWlib/apt32f102_ifc.c new file mode 100644 index 0000000..bd23380 --- /dev/null +++ b/Source/FWlib/apt32f102_ifc.c @@ -0,0 +1,264 @@ +/* + ****************************************************************************** + * @file apt32f102_ifc.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_ifc.h" +volatile unsigned int R_INT_FlashAdd; +volatile unsigned char f_Drom_writing=0; +/* define --------------------------------------------------------------------*/ +extern void delay_nms(unsigned int t); +/* externs--------------------------------------------------------------------*/ +/************************************************************* +//ChipErase fuction +//EntryParameter:NONE +//ReturnValue:NONE +*************************************************************/ +void ChipErase(void) +{ + SetUserKey; + EnChipErase; + StartErase; + while(IFC->CR!=0x0); //Wait for the operation to complete +} +/************************************************************* +//PageErase fuction +//EntryParameter:XROM_PageAdd +//XROM_PageAdd:PROM_PageAdd0~PROM_PageAdd255 +//DROM_PageAdd0~DROM_PageAdd31 +//ReturnValue:NONE +*************************************************************/ +void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAdd) +{ + SetUserKey; + EnPageErase; + IFC->FM_ADDR=XROM_PageAdd; + StartErase; + while(IFC->CR!=0x0); +} +/************************************************************* +//Enable or Disable IFC Interrupt when Operate FlashData +//EntryParameter:FlashAdd、DataSize、*BufArry +//ReturnValue:NONE +*************************************************************/ +//PROM:Write at most 256 bytes once time +//DROM:Write at most 64 bytes at once time +//Interrupt mode requires multiple loop queries to complete +void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry) +{ + int i,DataBuffer; + if(!f_Drom_writing) + { + f_Drom_writing=1; + R_INT_FlashAdd=FlashAdd; + ifc_step=0; + //Page cache wipe 1 + SetUserKey; + IFC->CMR=0x07; //Page cache wipe + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Write data to the cache 2 + for(i=0;i<((DataSize+3)/4);i++) //sizeof structure + { + DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24); + *(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer; + BufArry +=4; + } + //Pre-programmed operation settings 3 + SetUserKey; + IFC->CMR=0x06; + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Perform pre-programming 4 + SetUserKey; + IFC->CMR=0x01; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + } +} +//Normal mode, when the call is completed once, it will delay 4.2ms in the program +void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry) +{ + int i,DataBuffer; + + //Page cache wipe 1 + SetUserKey; + IFC->CMR=0x07; + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Write data to the cache 2 + for(i=0;i<((DataSize+3)/4);i++) //sizeof structure + { + DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24); + *(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer; + BufArry +=4; + } + //Pre-programmed operation settings 3 + SetUserKey; + IFC->CMR=0x06; + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Perform pre-programming 4 + SetUserKey; + IFC->CMR=0x01; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete + //Page erase 5 + SetUserKey; + IFC->CMR=0x02; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete + //Write page cache data to flash memory 6 + SetUserKey; + IFC->CMR=0x01; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete +} +void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry) +{ + int i,DataBuffer; + + //Page cache wipe 1 + SetUserKey; + IFC->CMR=0x07; + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Write data to the cache 2 + for(i=0;iCMR=0x06; + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + while(IFC->CR!=0x0); //Wait for the operation to complete + //Perform pre-programming 4 + SetUserKey; + IFC->CMR=0x01; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete + //Page erase 5 + SetUserKey; + IFC->CMR=0x02; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete + //Write page cache data to flash memory 6 + SetUserKey; + IFC->CMR=0x01; + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete +} +/************************************************************* +// ReadFlashData fuction return Data arry save in Flash +// DataLength must be a multiple of 4, DataLength % 4 ==0. +//EntryParameter:RdStartAdd、DataLength、*DataArryPoint +//ReturnValue:NONE +*************************************************************/ +void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint) +{ + unsigned int i,Buffer; + //delay_nms(1); + for(i=0;i<((DataLength+3)/4);i++) + { + Buffer=*(volatile unsigned int *)RdStartAdd; + *DataArryPoint=Buffer; + *(DataArryPoint+1)=Buffer>>8; + *(DataArryPoint+2)=Buffer>>16; + *(DataArryPoint+3)=Buffer>>24; + RdStartAdd +=4; + DataArryPoint +=4; + } +} +/************************************************************* +//ReadFlashData fuction return Data arry save in Flash +//EntryParameter:RdStartAdd、DataLength、*DataArryPoint +//ReturnValue:NONE +*************************************************************/ +void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint) +{ + unsigned int i; + for (i=0;iIMCR =IFC->IMCR|IFC_INT_x; + } + else + { + IFC->IMCR =IFC->IMCR & (~IFC_INT_x); + } +} +/*************************************************************/ +//IFC Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void IFC_Int_Enable(void) +{ + IFC->ICR=0Xf007; //CLAER IFC INT status + INTC_ISER_WRITE(IFC_INT); +} + +/*************************************************************/ +//IFC Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void IFC_Int_Disable(void) +{ + INTC_ICER_WRITE(IFC_INT); +} +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_iostring.c b/Source/FWlib/apt32f102_iostring.c new file mode 100644 index 0000000..1a9420a --- /dev/null +++ b/Source/FWlib/apt32f102_iostring.c @@ -0,0 +1,133 @@ +/* + ****************************************************************************** + * @file apt32f102_iostring.c + * @author APT AE Team + * @version V1.00 + * @date 2020/05/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ +/****************************************************************************** +* Include Files +******************************************************************************/ +#include "apt32f102.h" +#include "apt32f102_uart.h" +#include "stdarg.h" +#include "stddef.h" +#include "stdio.h" +/****************************************************************************** +* Main code +******************************************************************************/ +void __putchar__ (char s) +{ +// UARTTxByte(UART0,s); + UARTTxByte(UART1,s); +} + +char *myitoa(int value, int* string, int radix) +{ + + int tmp[33]; + int* tp = tmp; + int i; + unsigned v; + int sign; + int* sp; + + if (radix > 36 || radix <= 1) + { + return 0; + } + + sign = (radix == 10 && value < 0); + if (sign) + v = -value; + else + v = (unsigned)value; + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) { + *tp++ = i+'0'; + + } else { + *tp++ = i + 'a' - 10; + + } + + } + + sp = string; + + if (sign) + *sp++ = '-'; + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + return string; +} + + +void my_printf(const char *fmt, ...) +{ + +// const char *s; + const int *s; + int d; + //char ch, *pbuf, buf[16]; + char ch, *pbuf; + int buf[16]; + va_list ap; + va_start(ap, fmt); + while (*fmt) { + if (*fmt != '%') { + __putchar__(*fmt++); + continue; + } + switch (*++fmt) { + case 's': + s = va_arg(ap, const char *); + for ( ; *s; s++) { + __putchar__(*s); + } + break; + case 'd': + d = va_arg(ap, int); + myitoa(d, buf, 10); + for (s = buf; *s; s++) { + __putchar__(*s); + } + break; + + case 'x': + case 'X': + d = va_arg(ap, int); + myitoa(d, buf, 16); + for (s = buf; *s; s++) { + __putchar__(*s); + } + break; + // Add other specifiers here... + case 'c': + case 'C': + ch = (unsigned char)va_arg(ap, int); + pbuf = &ch; + __putchar__(*pbuf); + break; + default: + __putchar__(*fmt); + break; + } + fmt++; + } + va_end(ap); +} + diff --git a/Source/FWlib/apt32f102_lpt.c b/Source/FWlib/apt32f102_lpt.c new file mode 100644 index 0000000..1e5751c --- /dev/null +++ b/Source/FWlib/apt32f102_lpt.c @@ -0,0 +1,260 @@ +/* + ****************************************************************************** + * @file apt32f102_lpt.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_lpt.h" + +/*************************************************************/ +//LPT RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_DeInit(void) +{ + LPT->CEDR = 0xBE980000; + LPT->RSSR = LPT_RESET_VALUE; + LPT->PSCR = LPT_RESET_VALUE; + LPT->CR = 0X00010010; + LPT->SYNCR = LPT_RESET_VALUE; + LPT->PRDR = LPT_RESET_VALUE; + LPT->CMP = LPT_RESET_VALUE; + LPT->CNT = LPT_RESET_VALUE; + LPT->TRGFTCR = LPT_RESET_VALUE; + LPT->TRGFTWR = LPT_RESET_VALUE; + LPT->EVTRG = LPT_RESET_VALUE; + LPT->EVPS = LPT_RESET_VALUE; + LPT->EVSWF = LPT_RESET_VALUE; + LPT->RISR = LPT_RESET_VALUE; + LPT->MISR = LPT_RESET_VALUE; + LPT->IMCR = LPT_RESET_VALUE; + LPT->ICR = LPT_RESET_VALUE; +} +/*************************************************************/ +//LPT IO Init +//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10, +//ReturnValue:NONE +/*************************************************************/ +void LPT_IO_Init(LPT_IOSET_TypeDef IONAME) +{ + if(IONAME==LPT_OUT_PA09) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000080; + } + if(IONAME==LPT_OUT_PB01) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000080; + } + if(IONAME==LPT_IN_PA10) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000800; + } +} +/*************************************************************/ +//LPT Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX) +{ + LPT->CEDR |=CLKX| CSSX| SHDWSTPX| (FLTCKPRSX<<8); + LPT->PSCR = PSCDIVX; + LPT->CR |=OPMX; +} +/*************************************************************/ +//LPT DEBUG MODE +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_Debug_Mode(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + LPT->CEDR |= LPT_DEBUG_MODE; + } + else + { + LPT->CEDR &= ~LPT_DEBUG_MODE; + } +} +/*************************************************************/ +//LPT Period / Compare set +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA) +{ + LPT->PRDR =PRDR_DATA; + LPT->CMP =CMP_DATA; +} +/*************************************************************/ +//LPT COUNTER set +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_CNT_Write(U16_T CNT_DATA) +{ + LPT->CNT =CNT_DATA; +} +/*************************************************************/ +//LPT read counters +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +U16_T LPT_PRDR_Read(void) +{ + return LPT->PRDR; +} +U16_T LPT_CMP_Read(void) +{ + return LPT->CMP; +} +U16_T LPT_CNT_Read(void) +{ + return LPT->CNT; +} +/*************************************************************/ +//LPT ControlSet Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX, + LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX) +{ + LPT->CR |= SWSYNX| IDLESTX| PRDLDX| POLX| FLTDEBX| FLTDEBX| CMPLDX; +} +/*************************************************************/ +//LPT SYNC Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX) +{ + LPT->SYNCR |= TRGENX| OSTMDX| AREARMX; +} +/*************************************************************/ +//LPT Trigger Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X, + LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA) +{ + LPT->TRGFTCR |= SRCSELX| BLKINVX| CROSSMDX; + LPT->TRGFTWR |= OFFSET_DATA |(WINDOW_DATA<<16); + LPT->EVTRG |= TRGSRC0X |ESYN0OEX; + LPT->EVPS |=TRGEC0PRD_DATA; +} +void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA) +{ + LPT->EVPS |= TRGEC0PRD_DATA |(TRGEV0CNT_DATA<<16); +} +void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA) +{ + LPT->EVPS |= (TRGEV0CNT_DATA<<16); +} +void LPT_Soft_Trigger(void) +{ + LPT->EVSWF = 0X01; +} +/*************************************************************/ +// LPT start +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_Start(void) +{ + LPT->RSSR |= 0X01; +} +/*************************************************************/ +// LPT stop +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_Stop(void) +{ + LPT->RSSR &= 0XFFFFFFFE; +} +/*************************************************************/ +// LPT soft reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_Soft_Reset(void) +{ + LPT->RSSR |= (0X5<<12); +} +/*************************************************************/ +// LPT soft reset at once sync mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_REARM_Write(void) +{ + LPT->SYNCR |= (0X1<<16); +} +/*************************************************************/ +// LPT soft read at once sync mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +U8_T LPT_REARM_Read(void) +{ + uint8_t value = 0; + uint32_t dat = 0; + dat=(LPT->SYNCR)&(1<<16); + if (dat) + { + value = 1; + } + return value; +} +/*************************************************************/ +//LPT inturrpt Configure +//EntryParameter:LPT_IMSCR_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X) +{ + if (NewState != DISABLE) + { + LPT->IMCR |= LPT_IMSCR_X; + } + else + { + LPT->IMCR &= ~LPT_IMSCR_X; + } +} + +/*************************************************************/ +//LPT Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_INT_ENABLE(void) +{ + INTC_ISER_WRITE(LPT_INT); +} +/*************************************************************/ +//LPT Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_INT_DISABLE(void) +{ + INTC_ICER_WRITE(LPT_INT); +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_rtc.c b/Source/FWlib/apt32f102_rtc.c new file mode 100644 index 0000000..654813a --- /dev/null +++ b/Source/FWlib/apt32f102_rtc.c @@ -0,0 +1,316 @@ +/* + ****************************************************************************** + * @file apt32f102_interrupt.c + * @author APT AE Team + * @version V1.11 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_rtc.h" +/* define --------------------------------------------------------------------*/ +RTC_time_t RTC_TimeDate_buf; +RTC_Alarmset_T RTC_AlarmA_buf; +RTC_Alarmset_T RTC_AlarmB_buf; +/* externs--------------------------------------------------------------------*/ + +/*************************************************************/ +//Deinitializes the RTC registers to their default reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTC_RST_VALUE(void) //reset value +{ + RTC->TIMR=RTC_TIMR_RST; + RTC->DATR=RTC_DATR_RST; + RTC->CR=RTC_CR_RST; + RTC->CCR=RTC_CCR_RST; + RTC->ALRAR=RTC_ALRAR_RST; + RTC->ALRBR=RTC_ALRBR_RST; + RTC->SSR=RTC_SSR_RST; + RTC->CAL=RTC_CAL_RST; + RTC->IMCR=RTC_IMCR_RST; + RTC->EVTRG=RTC_EVTRG_RST; + RTC->EVPS=RTC_EVPS_RST; +} +/*************************************************************/ +//Deinitializes the RTC GPIO +//EntryParameter:Rtc_Output_Mode_TypeDef +//Rtc_Output_Mode_x:Alarm_A_pulse_output,Alarm_A_High,Alarm_A_Low,Alarm_B_pulse_output,Alarm_B_High,Alarm_B_Low +//ReturnValue:NONE +/*************************************************************/ +void RTC_ALM_IO_SET(Rtc_Output_Mode_TypeDef Rtc_Output_Mode_x ) +{ + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF)|0X00000500; + RTC->KEY=0XCA53; + RTC->CR=(RTC->CR&0XFFFFE3FF)|Rtc_Output_Mode_x; + while(RTC->CR&0x02); +} +/*************************************************************/ +//Deinitializes the RTC clk config +//EntryParameter:CLKSRC_X,DIVS,DIVA +//CLKSRC_X:CLKSRC_ISOSC,CLKSRC_IMOSC,CLKSRC_EMOSC +//DIVS:0~0X7FFF +//DIVA:0~0X7F +//ReturnValue:NONE +/*************************************************************/ +//RTC CLK=(EMCLK/4)/(DIVS+1)/(DIVA+1)/4 +// (ISCLK)/(DIVS+1)/(DIVA+1)/4 +// (IMCLK/4)/(DIVS+1)/(DIVA+1)/4 +void RTCCLK_CONFIG(U16_T DIVS , U16_T DIVA , RTC_CLKSRC_TypeDef CLKSRC_X) +{ + RTC->KEY=0XCA53; + RTC->CCR|=(0X01<<27); + while(!(RTC->CCR&0x04000000)); //Wait for RTC to stabilize + RTC->CCR=(RTC->CCR&0xfc000000)|DIVS|(DIVA<<16)|(0X01<<23)|CLKSRC_X; + while(!(RTC->CCR&0x04000000)); //Wait for RTC to stabilize +} +/*************************************************************/ +//Deinitializes the RTC function config +//EntryParameter:RTC_FMT_MODE_TypeDef,RTC_CPRD_TypeDef,Rtc_ClockOutput_Mode_TypeDe +//RTC_FMT_MODE:RTC_24H,RTC_12H +//RTC_CPRD_x:CPRD_NONE,CPRD_05S,CPRD_1S,CPRD_1MIN,CPRD_1HOUR,CPRD_1DAY,CPRD_1MONTH +//Rtc_ClockOutput_x:COSEL_Cali_512hz,COSEL_Cali_1hz,COSEL_NoCali_512hz,COSEL_NoCali_1hz +//ReturnValue:NONE +/*************************************************************/ +void RTC_Function_Config(RTC_FMT_MODE_TypeDef RTC_FMT_MODE , RTC_CPRD_TypeDef RTC_CPRD_x , Rtc_ClockOutput_Mode_TypeDef Rtc_ClockOutput_x) +{ + RTC->KEY=0XCA53; + RTC->CR=(RTC->CR&0xffff1cdf)|RTC_FMT_MODE|RTC_CPRD_x|Rtc_ClockOutput_x|0X01<<16;//enable read +} +/*************************************************************/ +//Deinitializes the RTC Start +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void RTC_Start(void) +{ + RTC->KEY=0XCA53; + RTC->CR=RTC->CR&0xfffffffe; + while((RTC->CR&0x01)!=0||(RTC->CR&0x02)==2); +} +/*************************************************************/ +//Deinitializes the RTC Stop +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void RTC_Stop(void) +{ + RTC->KEY=0XCA53; + RTC->CR=RTC->CR|0x01; + while((RTC->CR&0x01)!=1||(RTC->CR&0x02)==2); +} +/*************************************************************/ +//Deinitializes the RTC timer date set +//EntryParameter:*RTC_TimeDate +//ReturnValue:NONE +/*************************************************************/ +void RTC_TIMR_DATR_SET(RTC_time_t *RTC_TimeDate) +{ + RTC->KEY=0XCA53; + RTC->TIMR=(RTC_TimeDate->u8Hour<<16)|(RTC_TimeDate->u8Minute<<8)|(RTC_TimeDate->u8Second); //Hour bit6->0:am 1:pm + RTC->DATR=(RTC_TimeDate->u8DayOfWeek<<24)|(RTC_TimeDate->u8Year<<16)|(RTC_TimeDate->u8Month<<8)|(RTC_TimeDate->u8Day<<0); + while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written +} +/*************************************************************/ +//Deinitializes the RTC timer date Read +//EntryParameter:*RTC_TimeDate +//ReturnValue:NONE +/*************************************************************/ +void RTC_TIMR_DATR_Read(RTC_time_t *RTC_TimeDate) +{ + RTC->KEY=0XCA53; + //RTC->CR|=0X01<<16; //enable read + //while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written + RTC_TimeDate->u8Second=(RTC->TIMR)&0x7f; + RTC_TimeDate->u8Minute=(RTC->TIMR>>8)&0x7f; + RTC_TimeDate->u8Hour=(RTC->TIMR>>16)&0x7f; + RTC_TimeDate->u8Day=(RTC->DATR)&0x7f; + RTC_TimeDate->u8Month=(RTC->DATR>>8)&0x7f; + RTC_TimeDate->u8Year=(RTC->DATR>>16)&0x7f; + RTC_TimeDate->u8DayOfWeek=(RTC->DATR>>24)&0x7f; + //RTC->CR&=0XFFFEFFFF; //disable read +} +/*************************************************************/ +//Deinitializes the RTC AlarmA set +//EntryParameter:*RTC_AlarmA,RTC_Alarm_Second_mask_TypeDef,RTC_Alarm_Minute_mask_TypeDef, +// RTC_Alarm_Hour_mask_TypeDef,RTC_Alarm_DataOrWeek_mask_TypeDef,RTC_Alarm_WeekData_select_TypeDef, +// RTC_Alarm_Register_select_TypeDef +//RTC_Alarm_Second_x:Alarm_Second_EN,Alarm_Second_DIS +//RTC_Alarm_Minute_x:Alarm_Minute_EN,Alarm_Minute_DIS +//RTC_Alarm_Hour_x:Alarm_Hour_EN,Alarm_Hour_DIS +//RTC_Alarm_DataOrWeek_x:Alarm_DataOrWeek_EN,Alarm_DataOrWeek_DIS +//Alarm_x_selecte:Alarm_data_selecte,Alarm_week_selecte +//Alarm_x:Alarm_A,Alarm_B +//ReturnValue:NONE +/*************************************************************/ +void RTC_Alarm_TIMR_DATR_SET(RTC_Alarm_Register_select_TypeDef Alarm_x , RTC_Alarmset_T *RTC_AlarmA , RTC_Alarm_Second_mask_TypeDef RTC_Alarm_Second_x , + RTC_Alarm_Minute_mask_TypeDef RTC_Alarm_Minute_x , RTC_Alarm_Hour_mask_TypeDef RTC_Alarm_Hour_x, + RTC_Alarm_DataOrWeek_mask_TypeDef RTC_Alarm_DataOrWeek_x, + RTC_Alarm_WeekData_select_TypeDef Alarm_x_selecte) +{ + RTC->KEY=0XCA53; + if(Alarm_x==Alarm_A) + { + RTC->CR=RTC->CR&0xfffffff7; + RTC->ALRAR=(Alarm_x_selecte)|(RTC_Alarm_DataOrWeek_x)|(RTC_Alarm_Hour_x)|(RTC_Alarm_Minute_x)|(RTC_Alarm_Second_x)| + (RTC_AlarmA->u8WeekOrData<<24)|(RTC_AlarmA->u8Hour<<16)|(RTC_AlarmA->u8Minute<<8)|(RTC_AlarmA->u8Second); + while(RTC->CR&0x02); + RTC->CR|=Alarm_A_EN; + } + if(Alarm_x==Alarm_B) + { + RTC->CR=RTC->CR&0xffffffef; + RTC->ALRBR=(Alarm_x_selecte)|(RTC_Alarm_DataOrWeek_x)|(RTC_Alarm_Hour_x)|(RTC_Alarm_Minute_x)|(RTC_Alarm_Second_x)| + (RTC_AlarmA->u8WeekOrData<<24)|(RTC_AlarmA->u8Hour<<16)|(RTC_AlarmA->u8Minute<<8)|(RTC_AlarmA->u8Second); + while(RTC->CR&0x02); + RTC->CR|=Alarm_B_EN; + } + RTC->KEY = 0; + while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written +} +/*************************************************************/ +//Deinitializes the RTC AlarmA read +//EntryParameter:*RTC_AlarmA +//ReturnValue:NONE +/*************************************************************/ +void RTC_AlarmA_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmA) +{ + RTC->KEY=0XCA53; + //RTC->CR|=0X01<<16; //enable read + //while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written + RTC_AlarmA->u8Second=(RTC->ALRAR)&0x7f; + RTC_AlarmA->u8Minute=(RTC->ALRAR>>8)&0x7f; + RTC_AlarmA->u8Hour=(RTC->ALRAR>>16)&0x7f; + RTC_AlarmA->u8WeekOrData=(RTC->ALRAR>>24)&0x3f; + //RTC->CR&=0XFFFEFFFF; //disable read +} +/*************************************************************/ +//Deinitializes the RTC AlarmB read +//EntryParameter:*RTC_AlarmB +//ReturnValue:NONE +/*************************************************************/ +void RTC_AlarmB_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmB) +{ + RTC->KEY=0XCA53; + //RTC->CR|=0X01<<16; //enable read + //while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written + RTC_AlarmB->u8Second=(RTC->ALRBR)&0x7f; + RTC_AlarmB->u8Minute=(RTC->ALRBR>>8)&0x7f; + RTC_AlarmB->u8Hour=(RTC->ALRBR>>16)&0x7f; + RTC_AlarmB->u8WeekOrData=(RTC->ALRBR>>24)&0x3f; + //RTC->CR&=0XFFFEFFFF; //disable read +} +/*************************************************************/ +//RTC EVTRG Config +//EntryParameter:RTC_EVTRG_TRGSRC0_x,RTC_TRGSRCX_CMD,Trgev0Prd +//RTC_EVTRG_TRGSRC0_x:RTC_EVTRG_TRGSRC0_DIS,RTC_EVTRG_TRGSRC0_AlarmA, +//RTC_EVTRG_TRGSRC0_AlarmB,RTC_EVTRG_TRGSRC0_AlarmAB,RTC_EVTRG_TRGSRC0_CPRD +//RTC_TRGSRCX_CMD:RTC_TRGSRC0_EN,RTC_TRGSRC0_DIS +//Trgev0Prd:0~0x0f +//ReturnValue: NONE +/*************************************************************/ +void RTC_TRGSRC0_Config(RTC_EVTRG_TRGSRC0_TypeDef RTC_EVTRG_TRGSRC0_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev0Prd) +{ + RTC->EVTRG=(RTC->EVTRG&0XFFEFFFF0)|RTC_EVTRG_TRGSRC0_x|RTC_TRGSRCX_CMD; + RTC->EVPS=(RTC->EVPS&0XFFFFFFF0)|Trgev0Prd; +} +/*************************************************************/ +//RTC EVTRG SWFTRG +//EntryParameter:RTC_EVTRG_TRGSRC1_x,RTC_TRGSRCX_CMD,Trgev1Prd +//RTC_EVTRG_TRGSRC1_x:RTC_EVTRG_TRGSRC1_DIS,RTC_EVTRG_TRGSRC1_AlarmA, +//RTC_EVTRG_TRGSRC1_AlarmB,RTC_EVTRG_TRGSRC1_AlarmAB,RTC_EVTRG_TRGSRC1_CPRD +//RTC_TRGSRCX_CMD:RTC_TRGSRC1_EN,RTC_TRGSRC1_DIS +//Trgev1Prd:0~0x0f +//ReturnValue: NONE +/*************************************************************/ +void RTC_TRGSRC1_Config(RTC_EVTRG_TRGSRC1_TypeDef RTC_EVTRG_TRGSRC1_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev1Prd) +{ + RTC->EVTRG=(RTC->EVTRG&0XFFDFFF0F)|RTC_EVTRG_TRGSRC1_x|RTC_TRGSRCX_CMD; + RTC->EVPS=(RTC->EVPS&0XFFFFFF0F)|Trgev1Prd<<4; +} +/*************************************************************/ +//RTC EVTRG SWFTRG +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void RTC_TRGSRC0_SWFTRG(void) +{ + RTC->EVSWF|=0X01; +} +/*************************************************************/ +//RTC EVTRG SWFTRG +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void RTC_TRGSRC1_SWFTRG(void) +{ + RTC->EVSWF|=0X02; +} +/*************************************************************/ +//RTC INT ENABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void RTC_Int_Enable(RTC_INT_TypeDef RTC_X_INT) +{ + RTC->ICR = RTC_X_INT; //clear LVD INT status + RTC->IMCR |= RTC_X_INT; +} +/*************************************************************/ +//RTC INT DISABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void RTC_Int_Disable(RTC_INT_TypeDef RTC_X_INT) +{ + RTC->IMCR &= ~RTC_X_INT; +} +/*************************************************************/ +//RTC Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTC_Vector_Int_Enable(void) +{ + INTC_ISER_WRITE(RTC_INT); +} +/*************************************************************/ +//RTC Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTC_Vector_Int_Disable(void) +{ + INTC_ICER_WRITE(RTC_INT); +} +/*************************************************************/ +//RTC Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTC_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(RTC_INT); +} + +/*************************************************************/ +//RTC Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTC_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(RTC_INT); +} + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_sio.c b/Source/FWlib/apt32f102_sio.c new file mode 100644 index 0000000..48259f0 --- /dev/null +++ b/Source/FWlib/apt32f102_sio.c @@ -0,0 +1,161 @@ +/* + ****************************************************************************** + * @file apt32f102_sio.c + * @author APT AE Team + * @version V1.11 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_sio.h" + + +/*************************************************************/ +//SIO RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_DeInit(void) +{ + SIO0->CR = SIO_RESET_VALUE; + SIO0->TXCR0 = SIO_RESET_VALUE; + SIO0->TXCR1 = SIO_RESET_VALUE; + //SIO0->TXBUF = SIO_RESET_VALUE; + SIO0->RXCR0 = SIO_RESET_VALUE; + SIO0->RXCR1 = SIO_RESET_VALUE; + SIO0->RXCR1 = SIO_RESET_VALUE; + //SIO0->RXBUF = SIO_RESET_VALUE; + SIO0->RISR = SIO_RESET_VALUE; + SIO0->MISR = SIO_RESET_VALUE; + SIO0->IMCR = SIO_RESET_VALUE; + SIO0->ICR = SIO_RESET_VALUE; +} +/*************************************************************/ +//SIO IO Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_IO_Init(SIO_IOG_TypeDef IOGx) +{ + if(IOGx==SIO_PA02) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000400; + } + if(IOGx==SIO_PA03) + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFF0FFF)|0x00008000; + } + if(IOGx==SIO_PA012) + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00080000; + } + if(IOGx==SIO_PB01) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000070; + } +} +/*************************************************************/ +//SIO TX Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_TX_Init(SIO_CLK_TypeDef CLKX,U8_T TCKPRSX) +{ + SIO0->CR =CLKX | (TCKPRSX<<16) |(0X00<<8); + +} +/*************************************************************/ +//SIO TX Configure +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_TX_Configure(SIO_IDLEST_TypeDef IDLEX,SIO_TXDIR_TypeDef TXDIRX,U8_T TXBUFLENX,U8_T TXCNTX,U8_T D0DURX,U8_T D1DURX,SIO_LENOBH_TypeDef LENOBHX, + SIO_LENOBL_TypeDef LENOBLX,U8_T HSQX,U8_T LSQX) +{ + SIO0->TXCR0 =IDLEX | TXDIRX | (TXBUFLENX<<4) |(TXCNTX<<8); + SIO0->TXCR1=(D0DURX<<2)|(D1DURX<<5)|LENOBHX|LENOBLX|(HSQX<<16)|(LSQX<<24); +} +/*************************************************************/ +//SIO TX BUFFER SET +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_TXBUF_Set(U8_T D30,U8_T D28,U8_T D26,U8_T D24,U8_T D22,U8_T D20,U8_T D18,U8_T D16, + U8_T D14,U8_T D12,U8_T D10,U8_T D08,U8_T D06,U8_T D04,U8_T D02,U8_T D00) +{ + SIO0->TXBUF=(D30<<30)|(D28<<28)|(D26<<26)|(D24<<24)|(D22<<22)|(D20<<20)|(D18<<18)|(D16<<16)| + (D14<<14)|(D12<<12)|(D10<<10)|(D08<<8)|(D06<<6)|(D04<<4)|(D02<<2)|(D00<<0); +} +/*************************************************************/ +//SIO RX Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_RX_Init(SIO_CLK_TypeDef CLKX,SIO_RXDEB_TypeDef RXDEBX,U8_T DEBCKSX) +{ + SIO0->CR =CLKX | RXDEBX |(0X01<<8) | (DEBCKSX<<4); +} +/*************************************************************/ +//SIO RX Basic Configure +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_RX_Configure0(SIO_BSTSEL_TypeDef BSTSELX,SIO_TRGMODE_TypeDef TRGMX,U8_T SPLCNTX,U8_T EXTRACTX,U8_T HITHRX, + SIO_ALIGNEN_TypeDef ALIGNX,SIO_RXDIR_TypeDef RXDIRX,SIO_RXMODE_TypeDef RXMODEX,U8_T RXLENX,U8_T RXBUFLENX,U8_T RXKPRSX) +{ + SIO0->RXCR0=BSTSELX|TRGMX|(SPLCNTX<<4)|(EXTRACTX<<10)|(HITHRX<<16)|(ALIGNX)|RXDIRX|RXMODEX; + SIO0->RXCR1=(RXLENX)|(RXBUFLENX<<8)|(RXKPRSX<<16); +} +/*************************************************************/ +//SIO RX Configure 1 +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_RX_Configure1(SIO_BREAKEN_TypeDef BREAKX,SIO_BREAKLVL_TypeDef BREAKLVLX,U8_T BREKCNTX,SIO_TORSTEN_TypeDef TORSTX,U8_T TOCNTX) +{ + SIO0->RXCR2=BREAKX|BREAKLVLX|(BREKCNTX<<3)|TORSTX|(TOCNTX<<16); +} +/*************************************************************/ +//SIO inturrpt Configure +//EntryParameter:LPT_IMSCR_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void SIO_ConfigInterrupt_CMD(FunctionalStatus NewState,SIO_IMSCR_TypeDef SIO_IMSCR_X) +{ + if (NewState != DISABLE) + { + SIO0->IMCR |= SIO_IMSCR_X; + } + else + { + SIO0->IMCR &= ~SIO_IMSCR_X; + } +} +/*************************************************************/ +//SIO Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_INT_ENABLE(void) +{ + INTC_ISER_WRITE(SIO_INT); +} +/*************************************************************/ +//SIO Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO_INT_DISABLE(void) +{ + INTC_ICER_WRITE(SIO_INT); +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_spi.c b/Source/FWlib/apt32f102_spi.c new file mode 100644 index 0000000..48e9d4d --- /dev/null +++ b/Source/FWlib/apt32f102_spi.c @@ -0,0 +1,212 @@ +/* + ****************************************************************************** + * @file apt32f102_spi.c + * @author APT AE Team + * @version V1.10 + * @date 2021/08/25 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#include "apt32f102_spi.h" +/* defines -------------------------------------------------------------------*/ + +/* -------- variables ---------------------------------------------------------*/ + +/* externs--------------------------------------------------------------------*/ +extern void delay_nus(unsigned int t); +/*************************************************************/ +//SPI RESET,CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_DeInit(void) +{ + SPI0->CR0 = SPI_CR0_RST; + SPI0->CR1 = SPI_CR1_RST; + //SPI0->DR = SPI_DR_RST; + SPI0->SR = SPI_SR_RST; + SPI0->CPSR = SPI_CPSR_RST; + SPI0->IMSCR = SPI_IMSCR_RST; + SPI0->RISR = SPI_RISR_RST; + SPI0->MISR = SPI_MISR_RST; + SPI0->ICR = SPI_ICR_RST; +} +/*************************************************************/ +//SPI NSS IO Initial +//ReturnValue:NONE +/*************************************************************/ +void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP) +{ + if(SPI_NSS_IO_GROUP==0) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x05000000; //PA0.6 + } + else if(SPI_NSS_IO_GROUP==1) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0x00800000; //PB0.5 + } +} +/*************************************************************/ +//SPI Master Init +//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_SPO_X,SPI_SPH_X,SPI_LBM_X,SPI_SCR,SPI_CPSDVSR +//SPI_IO:SPI_G0,SPI_G1,SPI_G2 +//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT +//SPI_SPO_X:SPI_SPO_0,SPI_SPO_1 +//SPI_SPH_X:SPI_SPH_0,SPI_SPH_1 +//SPI_LBM_X:SPI_LBM_0,SPI_LBM_1 +//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2 +//SPI_SCR:0~255 +//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254 +//ReturnValue:NONE +/*************************************************************/ +//SPI Baud rate:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR)) +//FPCLK (max) → 2 × FSSPCLKOUT (max) master Fastest speed +void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR ) +{ + if (SPI_IO==SPI_G0) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800; + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MOSI,PA0.8->SPI_MIS0 + } + else if(SPI_IO==SPI_G1) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MOSI,PA0.11->SPI_MIS0 + } + else if(SPI_IO==SPI_G2) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4 + GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15 + } + SPI0->CPSR=SPI_CPSDVSR; + + SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPO_X<<6)|(SPI_SPH_X<<7)|(SPI_SCR<<8); + SPI0->CR1|=0X02|SPI_LBM_X|(SPI_RXIFLSEL_X<<4); +} +/*************************************************************/ +//SPI Slave Init +//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_RXIFLSEL_X,SPI_SCR,SPI_CPSDVSR +//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT +//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2 +//SPI_SCR:0~255 +//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254 +//ReturnValue:NONE +/*************************************************************/ +//SPI波特率:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR)) +//FPCLK (max) → 12 × FSSPCLKIN (max) slave Fastest speed +void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR) +{ + if (SPI_IO==SPI_G0) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800; + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MISO,PA0.8->SPI_MOSI + } + else if(SPI_IO==SPI_G1) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MISO,PA0.11->SPI_MOSI + } + else if(SPI_IO==SPI_G2) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4 + GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15 + } + SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPH_X<<7)|(SPI_SCR<<8); + SPI0->CPSR=SPI_CPSDVSR; + SPI0->CR1|=0X06|(SPI_RXIFLSEL_X<<4); +} +/*************************************************************/ +//SPI WRITE BYTE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_WRITE_BYTE(U16_T wdata) +{ + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); + SPI0->DR = wdata; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //wait for transmition finish +} +/*************************************************************/ +//SPI READ BYTE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth) +{ + U8_T i; + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = wdata; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + delay_nus(1); + *rdata = SPI0->DR; + for(i=0;iSR) & SSP_TNF) != SSP_TNF); + SPI0->DR=0; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); + *(rdata+i) = SPI0->DR; //get data from FIFO + } +} +/*************************************************************/ +//SPI inturrpt Configure +//EntryParameter:SPI_IMSCR_X,NewState +//SPI_IMSCR_X:SPI_PORIM,SPI_RTIM,SPI_RXIM,SPI_TXIM +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X) +{ + if (NewState != DISABLE) + { + SPI0->IMSCR |= SPI_IMSCR_X; //SET + } + else + { + SPI0->IMSCR &= ~SPI_IMSCR_X; //CLR + } +} +/*************************************************************/ +//SPI Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_Int_Enable(void) +{ + INTC_ISER_WRITE(SPI_INT); +} +/*************************************************************/ +//SPI Interrupt disalbe +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_Int_Disable(void) +{ + INTC_ICER_WRITE(SPI_INT); +} +/*************************************************************/ +//SPI Interrupt wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_Wakeup_Enable(void) +{ + INTC_IWER_WRITE(SPI_INT); +} + +/*************************************************************/ +//SPI Interrupt wake up disalbe +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI_Wakeup_Disable(void) +{ + INTC_IWDR_WRITE(SPI_INT); +} +/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_syscon.c b/Source/FWlib/apt32f102_syscon.c new file mode 100644 index 0000000..86ab86b --- /dev/null +++ b/Source/FWlib/apt32f102_syscon.c @@ -0,0 +1,817 @@ +/* + ****************************************************************************** + * @file main.c + * @author APT AE Team + * @version V1.09 + * @date 2021/07/30 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_syscon.h" +/* define --------------------------------------------------------------------*/ + +/* externs--------------------------------------------------------------------*/ + +/*************************************************************/ +//Deinitializes the syscon registers to their default reset +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_RST_VALUE(void) //reset value +{ + //SYSCON->IDCCR=SYSCON_IDCCR_RST; + //SYSCON->GCER=SYSCON_GCER_RST; + //SYSCON->GCDR=SYSCON_GCDR_RST; + //SYSCON->GCSR=SYSCON_GCSR_RST; + //SYSCON->CKST=SYSCON_CKST_RST; + SYSCON->RAMCHK=SYSCON_RAMCHK_RST; + SYSCON->EFLCHK=SYSCON_EFLCHK_RST; + SYSCON->SCLKCR=SYSCON_SCLKCR_RST; + //SYSCON->PCLKCR=SYSCON_PCLKCR_RST; + //SYSCON->PCER0=SYSCON_PCER0_RST; + //SYSCON->PCDR0=SYSCON_PCDR0_RST; + //SYSCON->PCSR0=SYSCON_PCSR0_RST; + //SYSCON->PCER1=SYSCON_PCER1_RST; + //SYSCON->PCDR1=SYSCON_PCDR1_RST; + //SYSCON->PCSR1=SYSCON_PCSR1_RST; + SYSCON->OSTR=SYSCON_OSTR_RST; + SYSCON->LVDCR=SYSCON_LVDCR_RST; + //SYSCON->CLCR=SYSCON_CLCR_RST; + //SYSCON->PWRCR=SYSCON_PWRCR_RST; + //SYSCON->IMER=SYSCON_IMER_RST; + //SYSCON->IMDR=SYSCON_IMDR_RST; + //SYSCON->IMCR=SYSCON_IMCR_RST; + //SYSCON->IAR=SYSCON_IAR_RST; + //SYSCON->ICR=SYSCON_ICR_RST; + //SYSCON->RISR=SYSCON_RISR_RST; + //SYSCON->MISR=SYSCON_MISR_RST; + SYSCON->EXIRT=SYSCON_EXIRT_RST; + SYSCON->EXIFT=SYSCON_EXIFT_RST; + //SYSCON->EXIER=SYSCON_EXIER_RST; + //SYSCON->EXIDR=SYSCON_EXIDR_RST; + //SYSCON->EXIMR=SYSCON_EXIMR_RST; + //SYSCON->EXIAR=SYSCON_EXIAR_RST; + //SYSCON->EXICR=SYSCON_EXICR_RST; + //SYSCON->EXIRS=SYSCON_EXIRS_RST; + SYSCON->IWDCR=SYSCON_IWDCR_RST; + SYSCON->IWDCNT=SYSCON_IWDCNT_RST; + //SYSCON->PWROPT=SYSCON_PWROPT_RST; + SYSCON->EVTRG=SYSCON_EVTRG_RST; + SYSCON->EVPS=SYSCON_EVPS_RST; + SYSCON->EVSWF=SYSCON_EVSWF_RST; + SYSCON->UREG0=SYSCON_UREG0_RST; + SYSCON->UREG1=SYSCON_UREG1_RST; + SYSCON->UREG2=SYSCON_UREG2_RST; + SYSCON->UREG3=SYSCON_UREG3_RST; +} +/*************************************************************/ +//EMOSC OSTR Config +//EM_CNT:0~0X3FF +//EM_GM:0~0X1F +//EM_FLEN;EM_FLEN_DIS,EM_FLEN_EN +//EM_FLSEL:EM_FLSEL_5ns,EM_FLSEL_10ns,EM_FLSEL_15ns,EM_FLSEL_20ns +/*************************************************************/ +void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X) +{ + SYSCON->OSTR=EM_CNT|(EM_GM<<11)|EM_LFSEL_X|EM_FLEN_X|EM_FLSEL_X; +} +/*************************************************************/ +//SYSCON General Control +//EntryParameter:NewState:,ENDIS_X +//NewState:ENABLE,DISABLE +//ENDIS_X:ENDIS_ISOSC,ENDIS_IMOSC,ENDIS_EMOSC,ENDIS_HFOSC +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X ) +{ + if (NewState != DISABLE) + { + if(ENDIS_X==ENDIS_EMOSC) + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF00FFF)|0x00044000; //enable EMOSC PIN + SYSCON->GCER|=ENDIS_X; //enable SYSCON General Control + while(!(SYSCON->GCSR&ENDIS_X)); //check Enable? + switch(ENDIS_X) + { + case ENDIS_IMOSC: + while (!(SYSCON->CKST & ENDIS_IMOSC)); + break; + case ENDIS_EMOSC: + while (!(SYSCON->CKST & ENDIS_EMOSC)); + break; + case ENDIS_ISOSC: + while (!(SYSCON->CKST & ENDIS_ISOSC)); + break; + case ENDIS_HFOSC: + while (!(SYSCON->CKST & ENDIS_HFOSC)); + break; + case ENDIS_IDLE_PCLK: + break; + case ENDIS_SYSTICK: + break; + } + } + else + { + SYSCON->GCDR|=ENDIS_X; //disable SYSCON General Control + while(SYSCON->GCSR&ENDIS_X); //check Disable? + SYSCON->ICR|=ENDIS_X; //Clear ENDIS_X stable bit + } +} + +/*************************************************************/ +//Seleted system clk and seleted clk div +//EntryParameter:SYSCLK_X,HCLK_DIV_X,PCLK_DIV_X +//SYSCLK_X:SYSCLK_IMOSC,SYSCLK_EMOSC,SYSCLK_ISOSC,SYSCLK_HFOSC +//HCLK_DIV_X:HCLK_DIV_1/2/3/4/5/6/7/8/12/16/24/32/64/128/256 +//PCLK_DIV_X:PCLK_DIV_1,PCLK_DIV_2,PCLK_DIV_4,PCLK_DIV_8,PCLK_DIV_16 +//SystemClk_data_x:EMOSC_24M,EMOSC_16M,EMOSC_12M,EMOSC_8M,EMOSC_4M,EMOSC_36K, +//ISOSC,IMOSC,HFOSC_48M,HFOSC_24M,HFOSC_12M,HFOSC_6M +//ReturnValue:NONE +/*************************************************************/ +void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x ) +{ + if(SystemClk_data_x==HFOSC_48M) + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X04|(0X00<<16); //High speed mode + } + if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==HFOSC_24M)) + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X02|(0X00<<16); //Medium speed mode + } + if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==EMOSC_16M)) + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X01|(0X00<<16); //Low speed mode + } + if((SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K) + ||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_6M)) + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X00|(0X00<<16); //Low speed mode + } + SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X; + while (!(SYSCON->CKST & (1<<8))); // waiting for sysclk stable + SYSCON->PCLKCR=PCLK_KEY|PCLK_DIV_X; //PCLK DIV 1 2 4 6 8 16 + while(SYSCON->PCLKCR!=PCLK_DIV_X); //Wait PCLK DIV +} +/*************************************************************/ +//clear system clk register +//ReturnValue:NONE +/*************************************************************/ +void SystemCLK_Clear(void) +{ + SYSCON->SCLKCR=0xd22d0000; + while(SYSCON->SCLKCR!=0); +} +/*************************************************************/ +//SYSCON IMOSC SELECTE +//EntryParameter:IMOSC_SELECTE_X +//IMOSC_SELECTE_X:IMOSC_SELECTE_5556K,IMOSC_SELECTE_4194K;IMOSC_SELECTE_2097K;IMOSC_SELECTE_131K +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X) +{ + //SYSCON_General_CMD(DISABLE,ENDIS_IMOSC); //disalbe IMOSC + SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFFC)|IMOSC_SELECTE_X; //IMOSC CLK selected + //SYSCON_General_CMD(ENABLE,ENDIS_IMOSC); //enable IMOSC +} +/*************************************************************/ +//SYSCON HFOSC SELECTE +//EntryParameter:HFOSC_SELECTE_X +//HFOSC_SELECTE_X:HFOSC_SELECTE_48M,HFOSC_SELECTE_24M;HFOSC_SELECTE_12M;HFOSC_SELECTE_6M +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X) +{ + SYSCON_General_CMD(DISABLE,ENDIS_HFOSC); //disable HFOSC + SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFCF)|HFOSC_SELECTE_X; + SYSCON_General_CMD(ENABLE,ENDIS_HFOSC); //enable HFOSC +} +/*************************************************************/ +//WDT enable and disable +//EntryParameter:,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_WDT_CMD(FunctionalStatus NewState) +{ + if(NewState != DISABLE) + { + SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT; + while(!(SYSCON->IWDCR&Check_IWDT_BUSY)); + } + else + { + SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT; + while(SYSCON->IWDCR&Check_IWDT_BUSY); + } +} +/*************************************************************/ +//reload WDT CN +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_IWDCNT_Reload(void) +{ + SYSCON->IWDCNT=CLR_IWDT; +} +/*************************************************************/ +//IWDCNT Config +//EntryParameter:NewStateE_IWDT_SHORT,IWDT_TIME_X,IWDT_INTW_DIV_X +//NewStateE_IWDT_SHORT:ENABLE_IWDT_SHORT,DISABLE_IWDT_SHORT +//IWDT_TIME_X:IWDT_TIME_128MS,IWDT_TIME_256MS,IWDT_TIME_500MS,IWDT_TIME_1S,IWDT_TIME_2S,IWDT_TIME_3S,IWDT_TIME_4S,IWDT_TIME_8S +//IWDT_INTW_DIV_X:IWDT_INTW_DIV_1/2/3/4/4/5/6 +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X ) +{ + SYSCON->IWDCR=IWDT_KEY|IWDT_TIME_X|IWDT_INTW_DIV_X; +} +/*************************************************************/ +//LVD Config and set LVD INT +//EntryParameter:X_LVDEN,INTDET_LVL_X,RSTDET_LVL_X,X_LVD_INT +//X_LVDEN:ENABLE_LVDEN,DISABLE_LVDEN +//INTDET_LVL_X:INTDET_LVL_1_8V,INTDET_LVL_2_1V,INTDET_LVL_2_5V,INTDET_LVL_2_9V,INTDET_LVL_3_3V,INTDET_LVL_3_7V,INTDET_LVL_4_1V,INTDET_LVL_4_5V +//RSTDET_LVL_X:RSTDET_LVL_1_6V,RSTDET_LVL_2_0V,RSTDET_LVL_2_4V,RSTDET_LVL_2_8V,RSTDET_LVL_3_2V,RSTDET_LVL_3_6V,RSTDET_LVL_4_0V,RSTDET_LVL_4_4V +//X_LVD_INT:ENABLE_LVD_INT,DISABLE_LVD_INT +//INTDET_POL_X:INTDET_POL_fall,INTDET_POL_X_rise,INTDET_POL_X_riseORfall +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X) +{ + //SYSCON->LVDCR=LVD_KEY; + SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT|INTDET_POL_X; +} +/*************************************************************/ +//LVD INT ENABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void LVD_Int_Enable(void) +{ + SYSCON->ICR = LVD_INT_ST; //clear LVD INT status + SYSCON->IMER |= LVD_INT_ST; +} +/*************************************************************/ +//LVD INT DISABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void LVD_Int_Disable(void) +{ + SYSCON->IMDR |= LVD_INT_ST; +} +/*************************************************************/ +//WDT INT ENABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void IWDT_Int_Enable(void) +{ + SYSCON->ICR = IWDT_INT_ST; //clear LVD INT status + SYSCON->IMER |= IWDT_INT_ST; +} +/*************************************************************/ +//WDT INT DISABLE. +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void IWDT_Int_Disable(void) +{ + SYSCON->IMDR |= IWDT_INT_ST; +} +/*************************************************************/ +//Reset status. +//EntryParameter:NONE +//ReturnValue: rsr_dat +//rsr_dat=0x01 power on reset +//rsr_dat=0x02 low voltage reset +//rsr_dat=0x04 ex-pin reset +//rsr_dat=0x10 wdt reset +//rsr_dat=0x40 ex clock invalid reset +//rsr_dat=0x80 cpu request reset +//rsr_dat=0x100 software reset +/*************************************************************/ +U32_T Read_Reset_Status(void) +{ + return (SYSCON->RSR & 0x1ff); +} +/*************************************************************/ +//external trigger Mode Selection Functions +//EntryParameter:NewState,EXIPIN,EXI_tringer_mode +//NewState:ENABLE,DISABLE +//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13 +//EXI_tringer_mode:_EXIRT,_EXIFT +//ReturnValue: LVD detection flag +/*************************************************************/ +void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode) +{ + switch(EXI_tringer_mode) + { + case _EXIRT: + if(NewState != DISABLE) + { + SYSCON->EXIRT |=EXIPIN; + } + else + { + SYSCON->EXIRT &=~EXIPIN; + } + break; + case _EXIFT: + if(NewState != DISABLE) + { + SYSCON->EXIFT |=EXIPIN; + } + else + { + SYSCON->EXIFT &=~EXIPIN; + } + break; + } +} +/*************************************************************/ +//external interrupt enable and disable +//EntryParameter:NewState,EXIPIN,* GPIOX +//* GPIOX:GPIOA,GPIOB +//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13 +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN) +{ + SYSCON->EXICR = 0X3FFF; //Claer EXI INT status + if(NewState != DISABLE) + { + SYSCON->EXIER|=EXIPIN; //EXI4 interrupt enable + while(!(SYSCON->EXIMR&EXIPIN)); //Check EXI is enabled or not + SYSCON->EXICR |=EXIPIN; // Clear EXI status bit + } + else + { + SYSCON->EXIDR|=EXIPIN; + } +} +/*************************************************************/ +//GPIO EXTI interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE) +{ + GPIOX->IECR=GPIO_IECR_VALUE; +} +/*************************************************************/ +//PLCK goto SLEEP mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void PCLK_goto_idle_mode(void) +{ + asm ("doze"); // Enter sleep mode +} +/*************************************************************/ +//PLCK goto SLEEP mode +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void PCLK_goto_deepsleep_mode(void) +{ + SYSCON->WKCR=0X3F<<8; + asm ("stop"); +} +/*************************************************************/ +//EXI0 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI0_INT); +} + +/*************************************************************/ +//EXI0 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0_Int_Disable(void) +{ + INTC_ICER_WRITE(EXI0_INT); +} + +/*************************************************************/ +//EXI1 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI1_INT); +} + +/*************************************************************/ +//EXI1 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1_Int_Disable(void) +{ + INTC_ICER_WRITE(EXI1_INT); +} + +/*************************************************************/ +//EXI2 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI2_INT); +} + +/*************************************************************/ +//EXI2 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2_Int_Disable(void) +{ + INTC_ICER_WRITE(EXI2_INT); +} + +/*************************************************************/ +//EXI3 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI3_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI3_INT); +} + +/*************************************************************/ +//EXI3 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI3_Int_Disable(void) +{ + INTC_ICER_WRITE(EXI3_INT); +} + +/*************************************************************/ +//EXI4 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI4_INT); +} + +/*************************************************************/ +//EXI4 Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4_Int_Disable(void) +{ + INTC_ICER_WRITE(EXI4_INT); +} +/*************************************************************/ +//EXI0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(EXI0_INT); +} + +/*************************************************************/ +//EXI0 Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(EXI0_INT); +} + +/*************************************************************/ +//EXI1 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(EXI1_INT); +} + +/*************************************************************/ +//EXI1 Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(EXI1_INT); +} + +/*************************************************************/ +//EXI2 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(EXI2_INT); +} + +/*************************************************************/ +//EXI2 Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(EXI2_INT); +} + +/*************************************************************/ +//EXI3 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI3_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(EXI3_INT); +} + +/*************************************************************/ +//EXI3 Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI3_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(EXI3_INT); +} + +/*************************************************************/ +//EXI4 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(EXI4_INT); +} + +/*************************************************************/ +//EXI4 Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(EXI4_INT); +} +/*************************************************************/ +//SYSCON Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_Int_Enable(void) +{ + INTC_ISER_WRITE(SYSCON_INT); +} + +/*************************************************************/ +//SYSCON Interrupt disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_Int_Disable(void) +{ + INTC_ICER_WRITE(SYSCON_INT); +} +/*************************************************************/ +//SYSCON Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(SYSCON_INT); +} +/*************************************************************/ +//set PA0.0/PA0.8 as CLO output +//EntryParameter:CLO_PA02/CLO_PA08 +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io) +{ + if (clo_io==CLO_PA02) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000700; + } + if (clo_io==CLO_PA08) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000007; + } + +} +/*************************************************************/ +//set CLO clk and div +//EntryParameter:clomxr/clodivr +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr) +{ + SYSCON->OPT1=(SYSCON->OPT1 & 0XFFFF00FF)|(clomxr<<8)|(clodivr<<12); +} +/*************************************************************/ +//SYSCON Wake up disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(SYSCON_INT); +} +/*************************************************************/ +//READ CIF0 data +//EntryParameter:None +//ReturnValue:VALUE +/*************************************************************/ +U32_T SYSCON_Read_CINF0(void) +{ + U32_T value = 0; + value=SYSCON->CINF0; + return value; +} +/*************************************************************/ +//READ CIF1 data +//EntryParameter:None +//ReturnValue:VALUE +/*************************************************************/ +U32_T SYSCON_Read_CINF1(void) +{ + U32_T value = 0; + value=SYSCON->CINF1; + return value; +} +/*************************************************************/ +//Software_Reset +//EntryParameter:None +//ReturnValue:MCU reset +/*************************************************************/ +void SYSCON_Software_Reset(void) +{ + SYSCON->IDCCR=IDCCR_KEY|SWRST; +} +/*************************************************************/ +//Interrupt Priority initial +//EntryParameter:00/40/80/C0 +//---------------------- +//CORET_INT IRQ0 +//SYSCON_INT IRQ1 +//IFC_INT IRQ2 +//ADC_INT IRQ3 +//---------------------- +//EPT0_INT IRQ4 +//****DUMMY IRQ5 +//WWDT_INT IRQ6 +//EXI0_INT IRQ7 +//---------------------- +//EXI1_INT IRQ8 +//GPT0_INT IRQ9 +//****DUMMY IRQ10 +//****DUMMY IRQ11 +//---------------------- +//RTC_INT IRQ12 +//UART0_INT IRQ13 +//UART1_INT IRQ14 +//UART2_INT IRQ15 +//---------------------- +//****DUMMY IRQ16 +//I2C_INT IRQ17 +//****DUMMY IRQ18 +//SPI_INT IRQ19 +//---------------------- +//SIO_INT IRQ20 +//EXI2_INT IRQ21 +//EXI3_INT IRQ22 +//EXI4_INT IRQ23 +//---------------------- +//CA_INT IRQ24 +//TKEY_INT IRQ25 +//LPT_INT IRQ26 +//****DUMMY IRQ27 +//---------------------- +//BT0_INT IRQ28 +//BT1_INT IRQ29 +//---------------------- +//ReturnValue:None +//00:Priority 0 highest +//40:Priority 1 +//80:Priority 2 +//C0:Priority 3 lowest +/*************************************************************/ +void SYSCON_INT_Priority(void) +{ + INTC_IPR0_WRITE(0XC0C0C0C0); //IQR0-3 low bit-->high bit + INTC_IPR1_WRITE(0XC0C0C0C0); //IQR4-7 + INTC_IPR2_WRITE(0XC0C0C0C0); //IQR8-11 + INTC_IPR3_WRITE(0XC0C0C0C0); //IQR12-15 + INTC_IPR4_WRITE(0XC0C0C0C0); //IQR16-19 + INTC_IPR5_WRITE(0XC0C0C0C0); //IQR20-23 + INTC_IPR6_WRITE(0XC0C000C0); //IQR24-27 + INTC_IPR7_WRITE(0XC0C0C0C0); //IQR28-31 +} +/*************************************************************/ +//Set Interrupt Priority +//EntryParameter: +//int_name:CORET_IRQ~BT1_IRQ +//int_level:0~3 0=highest 3=lowest +//ReturnValue:None +/*************************************************************/ +void Set_INT_Priority(U8_T int_name,U8_T int_level) +{ + U8_T i_temp,j_temp; + U32_T k_temp; + i_temp=(int_name%4)*8; + j_temp=int_name/4; + k_temp=CK801 -> IPR[j_temp]&(~(0xff< IPR[j_temp]=k_temp|((int_level*0x40)<<(i_temp)); +} +/*************************************************************/ +//IO REMAP +//EntryParameter:GPIOA0(0,1,2,3,4,5,6,7) GPIOB0(2,3),GPIOA0(8,9,10,11,12,13) +//0x00=I2C_SCL 0X01=I2C_SDA 0X02=GPT_CHA 0X03=GPT_CHB +//0X04=SPI_MOSI 0X05=SPI_MISO 0X06=SPI_SCK 0X07=SPI_NSS +//0x00=UART0_RX 0X01=UART0_TX 0X02=EPT_CHAX 0X03=PT_CHBX +//0X04=PT_CHCX 0X05=PT_CHAY 0X06=PT_CHBY 0X07=PT_CHCY +//ReturnValue:NONE +/*************************************************************/ +void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data) +{ + U8_T i; + if(iomap_data&0x10) + { + iomap_data=iomap_data&0X0F; + if(iomap_data==0) + { + for(i=0;i<28;i+=4) + { + if((SYSCON->IOMAP1&(0xf<IOMAP1=SYSCON->IOMAP1|(0xf<IOMAP1=(SYSCON->IOMAP1&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;} + if(bit==3){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;} + if(bit==8){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFFF0) | 0x0000000A;} + if(bit==9){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFF0F) | 0x000000A0;} + if(bit==10){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFF0FF) | 0x00000A00;} + if(bit==11){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFF0FFF) | 0x0000A000;} + if(bit==12){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFF0FFFF) | 0x000A0000;} + if(bit==13){SYSCON->IOMAP1=(SYSCON->IOMAP1&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFF0FFFFF) | 0x00A00000;} + } + else + { + if(iomap_data==0) + { + for(i=0;i<28;i+=4) + { + if((SYSCON->IOMAP0&(0xf<IOMAP0=SYSCON->IOMAP0|(0xf<IOMAP0=(SYSCON->IOMAP0&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFFF0) | 0x0000000A;} + if(bit==1){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFF0F) | 0x000000A0;} + if(bit==2){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;} + if(bit==3){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;} + if(bit==4){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFF0FFFF) | 0x000A0000;} + if(bit==5){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFF0FFFFF) | 0x00A00000;} + if(bit==6){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONLR =((GPIOx)->CONLR&0XF0FFFFFF) | 0x0A000000;} + if(bit==7){SYSCON->IOMAP0=(SYSCON->IOMAP0&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONLR =((GPIOx)->CONLR&0X0FFFFFFF) | 0x0A0000000;} + } +} +/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/FWlib/apt32f102_tkey_parameter.c b/Source/FWlib/apt32f102_tkey_parameter.c new file mode 100644 index 0000000..67f2fc9 --- /dev/null +++ b/Source/FWlib/apt32f102_tkey_parameter.c @@ -0,0 +1,99 @@ +/* + ****************************************************************************** + * @file apt32f102_tkey_parameter.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ +#include "apt32f102_tkey.h" + + + +void tk_parameter_init(void) +{ +/**************************************************** +//TK parameter define +*****************************************************/ + TK_IO_ENABLE=TCH_EN(4)|TCH_EN(5)|TCH_EN(7)|TCH_EN(8); + //TK IO ENABLE Bit16-->Bit0;0=DISABLE 1=ENABLE + TK_senprd[0]=30; //TCH0 scan period = TCH0 sens + TK_senprd[1]=50; //TCH1 scan period = TCH1 sens + TK_senprd[2]=50; //TCH2 scan period = TCH2 sens + TK_senprd[3]=50; //TCH3 scan period = TCH3 sens + TK_senprd[4]=140; //TCH4 scan period = TCH4 sens + TK_senprd[5]=50; //TCH5 scan period = TCH5 sens + TK_senprd[6]=50; //TCH6 scan period = TCH6 sens + TK_senprd[7]=50; //TCH7 scan period = TCH7 sens + TK_senprd[8]=50; //TCH8 scan period = TCH8 sens + TK_senprd[9]=50; //TCH9 scan period = TCH9 sens + TK_senprd[10]=50; //TCH10 scan period = TCH10 sens + TK_senprd[11]=50; //TCH11 scan period = TCH11 sens + TK_senprd[12]=50; //TCH12 scan period = TCH12 sens + TK_senprd[13]=50; //TCH13 scan period = TCH13 sens + TK_senprd[14]=50; //TCH14 scan period = TCH14 sens + TK_senprd[15]=50; //TCH15 scan period = TCH15 sens + TK_senprd[16]=50; //TCH16 scan period = TCH16 sens + TK_Triggerlevel[0]=60; //TCH0 TK_Trigger level + TK_Triggerlevel[1]=60; //TCH1 TK_Trigger level + TK_Triggerlevel[2]=60; //TCH2 TK_Trigger level + TK_Triggerlevel[3]=60; //TCH3 TK_Trigger level + TK_Triggerlevel[4]=60; //TCH4 TK_Trigger level + TK_Triggerlevel[5]=60; //TCH5 TK_Trigger level + TK_Triggerlevel[6]=60; //TCH6 TK_Trigger level + TK_Triggerlevel[7]=60; //TCH7 TK_Trigger level + TK_Triggerlevel[8]=60; //TCH8 TK_Trigger level + TK_Triggerlevel[9]=60; //TCH9 TK_Trigger level + TK_Triggerlevel[10]=60; //TCH10 TK_Trigger level + TK_Triggerlevel[11]=60; //TCH11 TK_Trigger level + TK_Triggerlevel[12]=60; //TCH12 TK_Trigger level + TK_Triggerlevel[13]=60; //TCH13 TK_Trigger level + TK_Triggerlevel[14]=60; //TCH14 TK_Trigger level + TK_Triggerlevel[15]=60; //TCH15 TK_Trigger level + TK_Triggerlevel[16]=60; //TCH16 TK_Trigger level + Press_debounce_data=5; //Press debounce 1~10 + Release_debounce_data=5; //Release debounce 1~10 + Key_mode=1; //Key mode 0=single key 1=multi key + MultiTimes_Filter=0; //MultiTimes Filter,>4 ENABLE <4 DISABLE + Valid_Key_Num=4; //Valid Key number when touched + Base_Speed=10; //baseline update speed + TK_longpress_time=16; //longpress rebuild time = _TK_longpress_time1*1s 0=disable + TK_BaseCnt=59999; //10ms TK_BaseCnt=10ms*48M/8-1,this register need to modify when mcu's Freq changed +/**************************************************** +//TK low power function define +*****************************************************/ + TK_Lowpower_mode=DISABLE; //touch key can goto sleep when TK lowpower mode enable + TK_Lowpower_level=2; //0=20ms 1=50ms 2=100ms 3=150ms 4=200ms,Scan interval when sleep + TK_Wakeup_level=50; //touch key Trigger level in sleep +/**************************************************** +//TK special parameter define +*****************************************************/ + TK_PSEL_MODE=TK_PSEL_AVDD; //tk power sel:TK_PSEL_FVR/TK_PSEL_AVDD when select TK_PSEL_FVR PA0.2(TCH3) need a 104 cap + TK_FVR_LEVEL=TK_FVR_4096V; //FVR level:TK_FVR_2048V/TK_FVR_4096V + TK_EC_LEVEL=TK_EC_3_6V; //C0 voltage sel:TK_EC_1V/TK_EC_2V/TK_EC_3V/TK_EC_3_6V + TK_icon[0]=5; //TCH0 TK Scan icon range 0~7 + TK_icon[1]=4; //TCH1 TK Scan icon range 0~7 + TK_icon[2]=4; //TCH2 TK Scan icon range 0~7 + TK_icon[3]=4; //TCH3 TK Scan icon range 0~7 + TK_icon[4]=4; //TCH4 TK Scan icon range 0~7 + TK_icon[5]=4; //TCH5 TK Scan icon range 0~7 + TK_icon[6]=4; //TCH6 TK Scan icon range 0~7 + TK_icon[7]=4; //TCH7 TK Scan icon range 0~7 + TK_icon[8]=4; //TCH8 TK Scan icon range 0~7 + TK_icon[9]=4; //TCH9 TK Scan icon range 0~7 + TK_icon[10]=4; //TCH10 TK Scan icon range 0~7 + TK_icon[11]=4; //TCH11 TK Scan icon range 0~7 + TK_icon[12]=4; //TCH12 TK Scan icon range 0~7 + TK_icon[13]=4; //TCH13 TK Scan icon range 0~7 + TK_icon[14]=4; //TCH14 TK Scan icon range 0~7 + TK_icon[15]=4; //TCH15 TK Scan icon range 0~7 + TK_icon[16]=4; //TCH16 TK Scan icon range 0~7 +} \ No newline at end of file diff --git a/Source/FWlib/apt32f102_uart.c b/Source/FWlib/apt32f102_uart.c new file mode 100644 index 0000000..25d4b9a --- /dev/null +++ b/Source/FWlib/apt32f102_uart.c @@ -0,0 +1,397 @@ +/* + ****************************************************************************** + * @file apt32f102_uart.c + * @author APT AE Team + * @version V1.15 + * @date 2022/09/05 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_uart.h" + + +/* define --------------------------------------------------------------------*/ +volatile U8_T RxDataFlag=0; +volatile U8_T TxDataFlag=0; +volatile U8_T f_Uart_send_Complete; +volatile U16_T Uart_send_Length_temp; +volatile U8_T Uart_send_Length; +volatile U8_T Uart_buffer[UART_BUFSIZE]; +/* externs--------------------------------------------------------------------*/ + + +/*************************************************************/ +//UART RESET,CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_DeInit(void) +{ + UART0->DATA = UART_RESET_VALUE; + UART0->SR = UART_RESET_VALUE; + UART0->CTRL = UART_RESET_VALUE; + UART0->ISR = UART_RESET_VALUE; + UART0->BRDIV =UART_RESET_VALUE; +} +void UART1_DeInit(void) +{ + UART1->DATA = UART_RESET_VALUE; + UART1->SR = UART_RESET_VALUE; + UART1->CTRL = UART_RESET_VALUE; + UART1->ISR = UART_RESET_VALUE; + UART1->BRDIV =UART_RESET_VALUE; +} +void UART2_DeInit(void) +{ + UART2->DATA = UART_RESET_VALUE; + UART2->SR = UART_RESET_VALUE; + UART2->CTRL = UART_RESET_VALUE; + UART2->ISR = UART_RESET_VALUE; + UART2->BRDIV =UART_RESET_VALUE; +} +/*************************************************************/ +//UART0 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_Int_Enable(void) +{ + UART0->ISR=0x0F; //clear UART0 INT status + INTC_ISER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART0 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_Int_Disable(void) +{ + INTC_ICER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART1 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_Int_Enable(void) +{ + UART1->ISR=0x0F; //clear UART1 INT status + INTC_ISER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART1 Interrupt Disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_Int_Disable(void) +{ + INTC_ICER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART1 Interrupt enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2_Int_Enable(void) +{ + UART2->ISR=0x0F; //clear UART1 INT status + INTC_ISER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART1 Interrupt Disable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2_Int_Disable(void) +{ + INTC_ICER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802 +} +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(UART0_INT); +} + +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(UART0_INT); +} +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(UART1_INT); +} + +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(UART1_INT); +} +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2_WakeUp_Enable(void) +{ + INTC_IWER_WRITE(UART2_INT); +} + +/*************************************************************/ +//UART0 Wake up enable +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2_WakeUp_Disable(void) +{ + INTC_IWDR_WRITE(UART2_INT); +} +/*************************************************************/ +//UART IO Init +//EntryParameter:IO_UARTX,UART_IO_G +//IO_UARTX:IO_UART0,IO_UART1 +//UART_IO_G:0 1 +//ReturnValue:NONE +/*************************************************************/ +void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G) +{ + if (IO_UART_NUM==IO_UART0) + { + if(UART_IO_G==0) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000004; //PA0.1->RXD0, PA0.0->TXD0 + } + else if(UART_IO_G==1) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00700000; //PA0.5->RXD0, PA0.12->TXD0 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00070000; + } + } + if (IO_UART_NUM==IO_UART1) + { + if(UART_IO_G==0) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000007; //PA0.13->RXD1, PB0.0->TXD1 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00700000; + } + else if(UART_IO_G==1) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF) | 0X00077000; //PA0.4->RXD1, PA0.3->TXD1 + } + else if(UART_IO_G==2) + { + GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0X77000000; //PA0.15->RXD1, PA0.14->TXD1 + } + } + if (IO_UART_NUM==IO_UART2) + { + if(UART_IO_G==0) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000077; //PA0.0->RXD2, PA0.1->TXD2 + } + else if(UART_IO_G==1) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X00FFFFFF) | 0X77000000; //PA0.7->RXD2, PA0.6->TXD2 + } + else if(UART_IO_G==2) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2 + } + } +} +/*************************************************************/ +//UART Init +//EntryParameter:UART0,UART1,UART2 ,baudrate_u16 +//e.g: +//sys_clk@24MHz, 24/4(div)=6MHz, 6000000/115200bps=52,baudrate_u16=52 +//sys_clk@24MHz, 24/2(div)=12MHz, 12000000/115200bps=104,baudrate_u16=104 +//ReturnValue:NONE +/*************************************************************/ +void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT) +{ + // Set Transmitter Enable + CSP_UART_SET_CTRL(uart, UART_TX | UART_RX |PAR_DAT); + // Set Baudrate + CSP_UART_SET_BRDIV(uart, baudrate_u16); +} +/*************************************************************/ +//UART init and enable RX,TX interrupt +//EntryParameter:UART0,UART1,UART2 ,baudrate_u16 +//ReturnValue:NONE +/*************************************************************/ +void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT) +{ + // Set Transmitter Enable + CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT | UART_TX_INT|PAR_DAT); + // Set Baudrate + CSP_UART_SET_BRDIV(uart, baudrate_u16); +} +/*************************************************************/ +//UART init and enable RX interrupt +//EntryParameter:UART0,UART1,UART2 ,baudrate_u16 +//ReturnValue:NONE +/*************************************************************/ +void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT) +{ + // Set Transmitter Enable + CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT |PAR_DAT); + // Set Baudrate + CSP_UART_SET_BRDIV(uart, baudrate_u16); + +} +/*************************************************************/ +//UART Close +//EntryParameter:UART0,UART1,UART2 +//ReturnValue:NONE +/*************************************************************/ +void UARTClose(CSP_UART_T *uart) +{ + // Set Transmitter Disable + CSP_UART_SET_CTRL(uart, 0x00); +} +/*************************************************************/ +//UART TX Byte loop send +//EntryParameter:UART0,UART1,UART2,txdata_u8 +//ReturnValue:NONE +/*************************************************************/ +void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8) +{ + unsigned int DataI; + // Write the transmit buffer + CSP_UART_SET_DATA(uart,txdata_u8); + do + { + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_TX_FULL; + } + while(DataI == UART_TX_FULL); //Loop when tx is full +} +/*************************************************************/ +//UART Transmit +//EntryParameter:UART0,UART1,UART2,sourceAddress_u16,length_u16 +//ReturnValue:NONE +/*************************************************************/ +void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16) +{ + unsigned int DataI,DataJ; + for(DataJ = 0;DataJ < length_u16 ;DataJ ++) + { + CSP_UART_SET_DATA(uart,*sourceAddress_u16++); + do{ + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_TX_FULL; + }while(DataI == UART_TX_FULL); //Loop when tx is full + } +} +/*************************************************************/ +//UART INT Transmit +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void UARTTTransmit_data_set(CSP_UART_T *uart ) +{ + if(!f_Uart_send_Complete) + { + f_Uart_send_Complete=1; + Uart_send_Length_temp++; + CSP_UART_SET_DATA(uart,Uart_buffer[0]); + } +} +void UARTTransmit_INT_Send(CSP_UART_T *uart ) +{ + if(f_Uart_send_Complete) + { + if(Uart_send_Length_temp>=Uart_send_Length) + { + f_Uart_send_Complete=0; + Uart_send_Length_temp=0; + } + else + { + CSP_UART_SET_DATA(uart,Uart_buffer[Uart_send_Length_temp++]); + } + } +} +/*************************************************************/ +//UART RX Byte +//EntryParameter:UART0,UART1,UART2,Rxdata_u16 +//ReturnValue:NONE +/*************************************************************/ +U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16) +{ + unsigned int DataI; + + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_RX_FULL; + if(DataI != UART_RX_FULL) //Loop when rx is not full + return FALSE; + else + { + *Rxdata_u16 = CSP_UART_GET_DATA(uart); + return TRUE; + } +} + +/*************************************************************/ +//UART RX Return Byte +//EntryParameter:UART0,UART1,UART2 +//ReturnValue:(uart)->DATA +/*************************************************************/ +U8_T UART_ReturnRxByte(CSP_UART_T *uart) +{ + RxDataFlag = FALSE; + while(RxDataFlag != TRUE); + return CSP_UART_GET_DATA(uart); +} + +/*************************************************************/ +//UART Receive +//EntryParameter:UART0,UART1,UART2，destAddress_u16，length_u16 +//ReturnValue:FALSE/TRUE +/*************************************************************/ +U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16) +{ + unsigned int DataI,DataJ,LoopTime; + + DataJ = 0; + LoopTime = 0; + do{ + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_RX_FULL; + if(DataI == UART_RX_FULL) //Loop when rx is full + { + *destAddress_u16++ = CSP_UART_GET_DATA(uart); + DataJ++; + LoopTime = 0; + } + if(LoopTime ++ >= 0xfff0) + return FALSE; + }while(DataJ < length_u16); + return TRUE; +} diff --git a/Source/FWlib/apt32f102_wwdt.c b/Source/FWlib/apt32f102_wwdt.c new file mode 100644 index 0000000..35591a1 --- /dev/null +++ b/Source/FWlib/apt32f102_wwdt.c @@ -0,0 +1,90 @@ +/* + ****************************************************************************** + * @file apt32f102_wwdt.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + + + /* Includes ------------------------------------------------------------------*/ +#include "apt32f102_wwdt.h" + + +/*************************************************************/ +//WWDT RESET CLEAR ALL REGISTER +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_DeInit(void) +{ + WWDT->CR = 0x000000FF; + WWDT->CFGR = 0x000000FF; + WWDT->RISR = WWDT_RESET_VALUE; + WWDT->MISR = WWDT_RESET_VALUE; + WWDT->IMCR = WWDT_RESET_VALUE; + WWDT->ICR = WWDT_RESET_VALUE; +} +/*************************************************************/ +//WWDT CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX) +{ + WWDT->CFGR =WND_DATA; + WWDT->CFGR |= PSCDIVX |DBGENX; +} +/*************************************************************/ +//WWDT ENABLE/DISABLE +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_CMD(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + WWDT->CR |= 0x01<<8; + } + else + { + WWDT->CR &= 0xfffffeff; + } +} +/*************************************************************/ +//WWDT load data +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_CNT_Load(U8_T cnt_data) +{ + WWDT->CR |= cnt_data; //SET +} +/*************************************************************/ +//WWDT INT ENABLE/DISABLE +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void WWDT_Int_Config(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + { + WWDT->ICR = WWDT_EVI; + WWDT->IMCR |= WWDT_EVI; + INTC_ISER_WRITE(WWDT_INT); + } + else + { + WWDT->IMCR &= ~WWDT_EVI; //CLR + INTC_ICER_WRITE(WWDT_INT); + } +} \ No newline at end of file diff --git a/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.asm b/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.asm new file mode 100644 index 0000000..0305b76 --- /dev/null +++ b/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.asm @@ -0,0 +1,15920 @@ + +.//Obj/BLV_C8_PLC_MASTER_V07_20260117.elf: file format elf32-csky-little + + +Disassembly of section .text: + +00000000 : + 0: 0000010c .long 0x0000010c + 4: 00002e06 .long 0x00002e06 + 8: 00002df6 .long 0x00002df6 + c: 00000184 .long 0x00000184 + 10: 00002dfe .long 0x00002dfe + 14: 00002dbc .long 0x00002dbc + 18: 00000184 .long 0x00000184 + 1c: 00002dee .long 0x00002dee + 20: 00002de6 .long 0x00002de6 + 24: 00000184 .long 0x00000184 + 28: 00000184 .long 0x00000184 + 2c: 00000184 .long 0x00000184 + 30: 00000184 .long 0x00000184 + 34: 00000184 .long 0x00000184 + 38: 00000184 .long 0x00000184 + 3c: 00000184 .long 0x00000184 + 40: 00002dde .long 0x00002dde + 44: 00002dd6 .long 0x00002dd6 + 48: 00002dce .long 0x00002dce + 4c: 00002dc6 .long 0x00002dc6 + 50: 00000184 .long 0x00000184 + 54: 00000184 .long 0x00000184 + 58: 00000184 .long 0x00000184 + 5c: 00000184 .long 0x00000184 + 60: 00000184 .long 0x00000184 + 64: 00000184 .long 0x00000184 + 68: 00000184 .long 0x00000184 + 6c: 00000184 .long 0x00000184 + 70: 00000184 .long 0x00000184 + 74: 00000184 .long 0x00000184 + 78: 00000184 .long 0x00000184 + 7c: 00002dbe .long 0x00002dbe + 80: 00002e26 .long 0x00002e26 + 84: 00002488 .long 0x00002488 + 88: 00002578 .long 0x00002578 + 8c: 000025e0 .long 0x000025e0 + 90: 00002648 .long 0x00002648 + 94: 00000184 .long 0x00000184 + 98: 000027f0 .long 0x000027f0 + 9c: 00002b6c .long 0x00002b6c + a0: 00002b9c .long 0x00002b9c + a4: 00002824 .long 0x00002824 + a8: 00000184 .long 0x00000184 + ac: 00000184 .long 0x00000184 + b0: 000028b0 .long 0x000028b0 + b4: 00002920 .long 0x00002920 + b8: 00002974 .long 0x00002974 + bc: 000029c4 .long 0x000029c4 + c0: 00000184 .long 0x00000184 + c4: 00002e1e .long 0x00002e1e + c8: 00000184 .long 0x00000184 + cc: 00002a00 .long 0x00002a00 + d0: 00002ae8 .long 0x00002ae8 + d4: 00002bd8 .long 0x00002bd8 + d8: 00002c20 .long 0x00002c20 + dc: 00002c7c .long 0x00002c7c + e0: 00002e16 .long 0x00002e16 + e4: 00002e0e .long 0x00002e0e + e8: 00002cdc .long 0x00002cdc + ec: 00000184 .long 0x00000184 + f0: 00002d10 .long 0x00002d10 + f4: 00002d4c .long 0x00002d4c + f8: 00000184 .long 0x00000184 + fc: 00000184 .long 0x00000184 + 100: 55aa0005 .long 0x55aa0005 + ... + +0000010c <__start>: +// .long __start +__start: + + + //initialize all registers + movi r0, 0 + 10c: 3000 movi r0, 0 + movi r1, 0 + 10e: 3100 movi r1, 0 + movi r2, 0 + 110: 3200 movi r2, 0 + movi r3, 0 + 112: 3300 movi r3, 0 + movi r4, 0 + 114: 3400 movi r4, 0 + movi r5, 0 + 116: 3500 movi r5, 0 + movi r6, 0 + 118: 3600 movi r6, 0 + movi r7, 0 + 11a: 3700 movi r7, 0 + //movi r13, 0 + //movi r14, 0 + //movi r15, 0 + +//set VBR + lrw r2, vector_table + 11c: 105b lrw r2, 0x0 // 188 + mtcr r2, cr<1,0> + 11e: c0026421 mtcr r2, cr<1, 0> + +//enable EE bit of psr + mfcr r2, cr<0,0> + 122: c0006022 mfcr r2, cr<0, 0> + bseti r2, r2, 8 + 126: 3aa8 bseti r2, 8 + mtcr r2, cr<0,0> + 128: c0026420 mtcr r2, cr<0, 0> +// st.w r2, (r1,0x4) +// movi r2, 0x1 +// st.w r2, (r1,0x0) + +//disable power peak + lrw r1, 0xe000ef90 + 12c: 1038 lrw r1, 0xe000ef90 // 18c + movi r2, 0x0 + 12e: 3200 movi r2, 0 + st.w r2, (r1, 0x0) + 130: b140 st.w r2, (r1, 0x0) + + + +//initialize kernel stack + lrw r7, __kernel_stack + 132: 10f8 lrw r7, 0x20000ff8 // 190 + mov r14,r7 + 134: 6f9f mov r14, r7 + subi r6,r7,0x4 + 136: 5fcf subi r6, r7, 4 + + //lrw r3, 0x40 + lrw r3, 0x04 + 138: 3304 movi r3, 4 + + subu r4, r7, r3 + 13a: 5f8d subu r4, r7, r3 + lrw r5, 0x0 + 13c: 3500 movi r5, 0 + +0000013e : +INIT_KERLE_STACK: + addi r4, 0x4 + 13e: 2403 addi r4, 4 + st.w r5, (r4) + 140: b4a0 st.w r5, (r4, 0x0) + //cmphs r7, r4 + cmphs r6, r4 + 142: 6518 cmphs r6, r4 + bt INIT_KERLE_STACK + 144: 0bfd bt 0x13e // 13e + +00000146 <__to_main>: + +__to_main: + lrw r0,__main + 146: 1014 lrw r0, 0xce0 // 194 + jsr r0 + 148: 7bc1 jsr r0 + mov r0, r0 + 14a: 6c03 mov r0, r0 + mov r0, r0 + 14c: 6c03 mov r0, r0 + + + + lrw r15, __exit + 14e: ea8f0013 lrw r15, 0x160 // 198 + lrw r0,main + 152: 1013 lrw r0, 0x2064 // 19c + jmp r0 + 154: 7800 jmp r0 + mov r0, r0 + 156: 6c03 mov r0, r0 + mov r0, r0 + 158: 6c03 mov r0, r0 + mov r0, r0 + 15a: 6c03 mov r0, r0 + mov r0, r0 + 15c: 6c03 mov r0, r0 + mov r0, r0 + 15e: 6c03 mov r0, r0 + +00000160 <__exit>: + +.export __exit +__exit: + + lrw r4, 0x20003000 + 160: 1090 lrw r4, 0x20003000 // 1a0 + //lrw r5, 0x0 + mov r5, r0 + 162: 6d43 mov r5, r0 + st.w r5, (r4) + 164: b4a0 st.w r5, (r4, 0x0) + + mfcr r1, cr<0,0> + 166: c0006021 mfcr r1, cr<0, 0> + lrw r1, 0xFFFF + 16a: 102f lrw r1, 0xffff // 1a4 + mtcr r1, cr<11,0> + 16c: c001642b mtcr r1, cr<11, 0> + lrw r1, 0xFFF + 170: 102e lrw r1, 0xfff // 1a8 + movi r0, 0x0 + 172: 3000 movi r0, 0 + st r1, (r0) + 174: b020 st.w r1, (r0, 0x0) + +00000176 <__fail>: + +.export __fail +__fail: + lrw r1, 0xEEEE + 176: 102e lrw r1, 0xeeee // 1ac + mtcr r1, cr<11,0> + 178: c001642b mtcr r1, cr<11, 0> + lrw r1, 0xEEE + 17c: 102d lrw r1, 0xeee // 1b0 + movi r0, 0x0 + 17e: 3000 movi r0, 0 + st r1, (r0) + 180: b020 st.w r1, (r0, 0x0) + +00000182 <__dummy>: + +__dummy: + br __fail + 182: 07fa br 0x176 // 176 <__fail> + +00000184 : + +.export DummyHandler +DummyHandler: + br __fail + 184: 07f9 br 0x176 // 176 <__fail> + 186: 0000 .short 0x0000 + 188: 00000000 .long 0x00000000 + 18c: e000ef90 .long 0xe000ef90 + 190: 20000ff8 .long 0x20000ff8 + 194: 00000ce0 .long 0x00000ce0 + 198: 00000160 .long 0x00000160 + 19c: 00002064 .long 0x00002064 + 1a0: 20003000 .long 0x20003000 + 1a4: 0000ffff .long 0x0000ffff + 1a8: 00000fff .long 0x00000fff + 1ac: 0000eeee .long 0x0000eeee + 1b0: 00000eee .long 0x00000eee + +000001b4 <___gnu_csky_case_uqi>: + 1b4: 1421 subi r14, r14, 4 + 1b6: b820 st.w r1, (r14, 0x0) + 1b8: 6c7f mov r1, r15 + 1ba: 6040 addu r1, r0 + 1bc: 8120 ld.b r1, (r1, 0x0) + 1be: 4121 lsli r1, r1, 1 + 1c0: 63c4 addu r15, r1 + 1c2: 9820 ld.w r1, (r14, 0x0) + 1c4: 1401 addi r14, r14, 4 + 1c6: 783c jmp r15 + +000001c8 <___gnu_csky_case_shi>: + 1c8: 1422 subi r14, r14, 8 + 1ca: b801 st.w r0, (r14, 0x4) + 1cc: b820 st.w r1, (r14, 0x0) + 1ce: 6c7f mov r1, r15 + 1d0: 4001 lsli r0, r0, 1 + 1d2: 6040 addu r1, r0 + 1d4: 8920 ld.h r1, (r1, 0x0) + 1d6: 7447 sexth r1, r1 + 1d8: 4121 lsli r1, r1, 1 + 1da: 63c4 addu r15, r1 + 1dc: 9801 ld.w r0, (r14, 0x4) + 1de: 9820 ld.w r1, (r14, 0x0) + 1e0: 1402 addi r14, r14, 8 + 1e2: 783c jmp r15 + +000001e4 <__fixunssfsi>: + 1e4: 14d1 push r4, r15 + 1e6: 319e movi r1, 158 + 1e8: 4137 lsli r1, r1, 23 + 1ea: 6d03 mov r4, r0 + 1ec: e00000ea bsr 0x3c0 // 3c0 <__gesf2> + 1f0: 38df btsti r0, 31 + 1f2: 0c05 bf 0x1fc // 1fc <__fixunssfsi+0x18> + 1f4: 6c13 mov r0, r4 + 1f6: e000014f bsr 0x494 // 494 <__fixsfsi> + 1fa: 1491 pop r4, r15 + 1fc: 319e movi r1, 158 + 1fe: 4137 lsli r1, r1, 23 + 200: 6c13 mov r0, r4 + 202: e00000c5 bsr 0x38c // 38c <__subsf3> + 206: e0000147 bsr 0x494 // 494 <__fixsfsi> + 20a: 3380 movi r3, 128 + 20c: 4378 lsli r3, r3, 24 + 20e: 600c addu r0, r3 + 210: 1491 pop r4, r15 + ... + +00000214 <_fpadd_parts>: + 214: 14c4 push r4-r7 + 216: 1421 subi r14, r14, 4 + 218: 9060 ld.w r3, (r0, 0x0) + 21a: 3b01 cmphsi r3, 2 + 21c: 0c3b bf 0x292 // 292 <_fpadd_parts+0x7e> + 21e: 9180 ld.w r4, (r1, 0x0) + 220: 3c01 cmphsi r4, 2 + 222: 0c3a bf 0x296 // 296 <_fpadd_parts+0x82> + 224: 3b44 cmpnei r3, 4 + 226: 0c76 bf 0x312 // 312 <_fpadd_parts+0xfe> + 228: 3c44 cmpnei r4, 4 + 22a: 0c36 bf 0x296 // 296 <_fpadd_parts+0x82> + 22c: 3c42 cmpnei r4, 2 + 22e: 0c5c bf 0x2e6 // 2e6 <_fpadd_parts+0xd2> + 230: 3b42 cmpnei r3, 2 + 232: 0c32 bf 0x296 // 296 <_fpadd_parts+0x82> + 234: 90a2 ld.w r5, (r0, 0x8) + 236: 91e2 ld.w r7, (r1, 0x8) + 238: 5d9d subu r4, r5, r7 + 23a: 9063 ld.w r3, (r0, 0xc) + 23c: 3cdf btsti r4, 31 + 23e: b860 st.w r3, (r14, 0x0) + 240: 6d93 mov r6, r4 + 242: 9163 ld.w r3, (r1, 0xc) + 244: 086f bt 0x322 // 322 <_fpadd_parts+0x10e> + 246: 3e3f cmplti r6, 32 + 248: 082a bt 0x29c // 29c <_fpadd_parts+0x88> + 24a: 655d cmplt r7, r5 + 24c: 0c5f bf 0x30a // 30a <_fpadd_parts+0xf6> + 24e: 3300 movi r3, 0 + 250: 9001 ld.w r0, (r0, 0x4) + 252: 9121 ld.w r1, (r1, 0x4) + 254: 6442 cmpne r0, r1 + 256: 0c33 bf 0x2bc // 2bc <_fpadd_parts+0xa8> + 258: 3840 cmpnei r0, 0 + 25a: 9820 ld.w r1, (r14, 0x0) + 25c: 0c54 bf 0x304 // 304 <_fpadd_parts+0xf0> + 25e: 60c6 subu r3, r1 + 260: 3bdf btsti r3, 31 + 262: 0863 bt 0x328 // 328 <_fpadd_parts+0x114> + 264: 3100 movi r1, 0 + 266: b221 st.w r1, (r2, 0x4) + 268: b2a2 st.w r5, (r2, 0x8) + 26a: b263 st.w r3, (r2, 0xc) + 26c: 5b23 subi r1, r3, 1 + 26e: 119b lrw r4, 0x3fffffff // 358 <_fpadd_parts+0x144> + 270: 6504 cmphs r1, r4 + 272: 080b bt 0x288 // 288 <_fpadd_parts+0x74> + 274: 9222 ld.w r1, (r2, 0x8) + 276: 2900 subi r1, 1 + 278: 4361 lsli r3, r3, 1 + 27a: 5b03 subi r0, r3, 1 + 27c: 6410 cmphs r4, r0 + 27e: 6d47 mov r5, r1 + 280: 2900 subi r1, 1 + 282: 0bfb bt 0x278 // 278 <_fpadd_parts+0x64> + 284: b263 st.w r3, (r2, 0xc) + 286: b2a2 st.w r5, (r2, 0x8) + 288: 3103 movi r1, 3 + 28a: 3bdf btsti r3, 31 + 28c: b220 st.w r1, (r2, 0x0) + 28e: 0821 bt 0x2d0 // 2d0 <_fpadd_parts+0xbc> + 290: 6c0b mov r0, r2 + 292: 1401 addi r14, r14, 4 + 294: 1484 pop r4-r7 + 296: 6c07 mov r0, r1 + 298: 1401 addi r14, r14, 4 + 29a: 1484 pop r4-r7 + 29c: 3c20 cmplti r4, 1 + 29e: 084c bt 0x336 // 336 <_fpadd_parts+0x122> + 2a0: 3401 movi r4, 1 + 2a2: 7118 lsl r4, r6 + 2a4: 2c00 subi r4, 1 + 2a6: 6dcf mov r7, r3 + 2a8: 68d0 and r3, r4 + 2aa: 3b40 cmpnei r3, 0 + 2ac: 9001 ld.w r0, (r0, 0x4) + 2ae: 3300 movi r3, 0 + 2b0: 9121 ld.w r1, (r1, 0x4) + 2b2: 60cd addc r3, r3 + 2b4: 71d9 lsr r7, r6 + 2b6: 6442 cmpne r0, r1 + 2b8: 6cdc or r3, r7 + 2ba: 0bcf bt 0x258 // 258 <_fpadd_parts+0x44> + 2bc: 9820 ld.w r1, (r14, 0x0) + 2be: 604c addu r1, r3 + 2c0: 6cc7 mov r3, r1 + 2c2: b223 st.w r1, (r2, 0xc) + 2c4: 3bdf btsti r3, 31 + 2c6: 3103 movi r1, 3 + 2c8: b201 st.w r0, (r2, 0x4) + 2ca: b2a2 st.w r5, (r2, 0x8) + 2cc: b220 st.w r1, (r2, 0x0) + 2ce: 0fe1 bf 0x290 // 290 <_fpadd_parts+0x7c> + 2d0: 3001 movi r0, 1 + 2d2: 4b21 lsri r1, r3, 1 + 2d4: 68c0 and r3, r0 + 2d6: 6cc4 or r3, r1 + 2d8: b263 st.w r3, (r2, 0xc) + 2da: 9262 ld.w r3, (r2, 0x8) + 2dc: 2300 addi r3, 1 + 2de: 6c0b mov r0, r2 + 2e0: b262 st.w r3, (r2, 0x8) + 2e2: 1401 addi r14, r14, 4 + 2e4: 1484 pop r4-r7 + 2e6: 3b42 cmpnei r3, 2 + 2e8: 0bd5 bt 0x292 // 292 <_fpadd_parts+0x7e> + 2ea: b260 st.w r3, (r2, 0x0) + 2ec: 9061 ld.w r3, (r0, 0x4) + 2ee: b261 st.w r3, (r2, 0x4) + 2f0: 9062 ld.w r3, (r0, 0x8) + 2f2: b262 st.w r3, (r2, 0x8) + 2f4: 9063 ld.w r3, (r0, 0xc) + 2f6: 9121 ld.w r1, (r1, 0x4) + 2f8: b263 st.w r3, (r2, 0xc) + 2fa: 9061 ld.w r3, (r0, 0x4) + 2fc: 68c4 and r3, r1 + 2fe: b261 st.w r3, (r2, 0x4) + 300: 6c0b mov r0, r2 + 302: 07c8 br 0x292 // 292 <_fpadd_parts+0x7e> + 304: 604e subu r1, r3 + 306: 6cc7 mov r3, r1 + 308: 07ac br 0x260 // 260 <_fpadd_parts+0x4c> + 30a: 3400 movi r4, 0 + 30c: 6d5f mov r5, r7 + 30e: b880 st.w r4, (r14, 0x0) + 310: 07a0 br 0x250 // 250 <_fpadd_parts+0x3c> + 312: 3c44 cmpnei r4, 4 + 314: 0bbf bt 0x292 // 292 <_fpadd_parts+0x7e> + 316: 9041 ld.w r2, (r0, 0x4) + 318: 9161 ld.w r3, (r1, 0x4) + 31a: 64ca cmpne r2, r3 + 31c: 0fbb bf 0x292 // 292 <_fpadd_parts+0x7e> + 31e: 1010 lrw r0, 0x58e8 // 35c <_fpadd_parts+0x148> + 320: 07b9 br 0x292 // 292 <_fpadd_parts+0x7e> + 322: 3600 movi r6, 0 + 324: 6192 subu r6, r4 + 326: 0790 br 0x246 // 246 <_fpadd_parts+0x32> + 328: 3101 movi r1, 1 + 32a: b221 st.w r1, (r2, 0x4) + 32c: 3100 movi r1, 0 + 32e: 596d subu r3, r1, r3 + 330: b2a2 st.w r5, (r2, 0x8) + 332: b263 st.w r3, (r2, 0xc) + 334: 079c br 0x26c // 26c <_fpadd_parts+0x58> + 336: 3c40 cmpnei r4, 0 + 338: 0f8c bf 0x250 // 250 <_fpadd_parts+0x3c> + 33a: 3401 movi r4, 1 + 33c: 98e0 ld.w r7, (r14, 0x0) + 33e: 7118 lsl r4, r6 + 340: 71d9 lsr r7, r6 + 342: 6158 addu r5, r6 + 344: 2c00 subi r4, 1 + 346: 98c0 ld.w r6, (r14, 0x0) + 348: 6918 and r4, r6 + 34a: 3c40 cmpnei r4, 0 + 34c: 3400 movi r4, 0 + 34e: 6111 addc r4, r4 + 350: 6dd0 or r7, r4 + 352: b8e0 st.w r7, (r14, 0x0) + 354: 077e br 0x250 // 250 <_fpadd_parts+0x3c> + 356: 0000 bkpt + 358: 3fffffff .long 0x3fffffff + 35c: 000058e8 .long 0x000058e8 + +00000360 <__addsf3>: + 360: 14d0 push r15 + 362: 142e subi r14, r14, 56 + 364: b800 st.w r0, (r14, 0x0) + 366: b821 st.w r1, (r14, 0x4) + 368: 6c3b mov r0, r14 + 36a: 1902 addi r1, r14, 8 + 36c: e000028a bsr 0x880 // 880 <__unpack_f> + 370: 1906 addi r1, r14, 24 + 372: 1801 addi r0, r14, 4 + 374: e0000286 bsr 0x880 // 880 <__unpack_f> + 378: 1a0a addi r2, r14, 40 + 37a: 1906 addi r1, r14, 24 + 37c: 1802 addi r0, r14, 8 + 37e: e3ffff4b bsr 0x214 // 214 <_fpadd_parts> + 382: e0000223 bsr 0x7c8 // 7c8 <__pack_f> + 386: 140e addi r14, r14, 56 + 388: 1490 pop r15 + ... + +0000038c <__subsf3>: + 38c: 14d0 push r15 + 38e: 142e subi r14, r14, 56 + 390: b800 st.w r0, (r14, 0x0) + 392: b821 st.w r1, (r14, 0x4) + 394: 6c3b mov r0, r14 + 396: 1902 addi r1, r14, 8 + 398: e0000274 bsr 0x880 // 880 <__unpack_f> + 39c: 1906 addi r1, r14, 24 + 39e: 1801 addi r0, r14, 4 + 3a0: e0000270 bsr 0x880 // 880 <__unpack_f> + 3a4: 9867 ld.w r3, (r14, 0x1c) + 3a6: 3201 movi r2, 1 + 3a8: 6cc9 xor r3, r2 + 3aa: 1906 addi r1, r14, 24 + 3ac: 1a0a addi r2, r14, 40 + 3ae: 1802 addi r0, r14, 8 + 3b0: b867 st.w r3, (r14, 0x1c) + 3b2: e3ffff31 bsr 0x214 // 214 <_fpadd_parts> + 3b6: e0000209 bsr 0x7c8 // 7c8 <__pack_f> + 3ba: 140e addi r14, r14, 56 + 3bc: 1490 pop r15 + ... + +000003c0 <__gesf2>: + 3c0: 14d0 push r15 + 3c2: 142a subi r14, r14, 40 + 3c4: b800 st.w r0, (r14, 0x0) + 3c6: b821 st.w r1, (r14, 0x4) + 3c8: 6c3b mov r0, r14 + 3ca: 1902 addi r1, r14, 8 + 3cc: e000025a bsr 0x880 // 880 <__unpack_f> + 3d0: 1906 addi r1, r14, 24 + 3d2: 1801 addi r0, r14, 4 + 3d4: e0000256 bsr 0x880 // 880 <__unpack_f> + 3d8: 9862 ld.w r3, (r14, 0x8) + 3da: 3b01 cmphsi r3, 2 + 3dc: 0c0a bf 0x3f0 // 3f0 <__gesf2+0x30> + 3de: 9866 ld.w r3, (r14, 0x18) + 3e0: 3b01 cmphsi r3, 2 + 3e2: 0c07 bf 0x3f0 // 3f0 <__gesf2+0x30> + 3e4: 1906 addi r1, r14, 24 + 3e6: 1802 addi r0, r14, 8 + 3e8: e000028e bsr 0x904 // 904 <__fpcmp_parts_f> + 3ec: 140a addi r14, r14, 40 + 3ee: 1490 pop r15 + 3f0: 3000 movi r0, 0 + 3f2: 2800 subi r0, 1 + 3f4: 140a addi r14, r14, 40 + 3f6: 1490 pop r15 + +000003f8 <__lesf2>: + 3f8: 14d0 push r15 + 3fa: 142a subi r14, r14, 40 + 3fc: b800 st.w r0, (r14, 0x0) + 3fe: b821 st.w r1, (r14, 0x4) + 400: 6c3b mov r0, r14 + 402: 1902 addi r1, r14, 8 + 404: e000023e bsr 0x880 // 880 <__unpack_f> + 408: 1906 addi r1, r14, 24 + 40a: 1801 addi r0, r14, 4 + 40c: e000023a bsr 0x880 // 880 <__unpack_f> + 410: 9862 ld.w r3, (r14, 0x8) + 412: 3b01 cmphsi r3, 2 + 414: 0c0a bf 0x428 // 428 <__lesf2+0x30> + 416: 9866 ld.w r3, (r14, 0x18) + 418: 3b01 cmphsi r3, 2 + 41a: 0c07 bf 0x428 // 428 <__lesf2+0x30> + 41c: 1906 addi r1, r14, 24 + 41e: 1802 addi r0, r14, 8 + 420: e0000272 bsr 0x904 // 904 <__fpcmp_parts_f> + 424: 140a addi r14, r14, 40 + 426: 1490 pop r15 + 428: 3001 movi r0, 1 + 42a: 140a addi r14, r14, 40 + 42c: 1490 pop r15 + ... + +00000430 <__floatsisf>: + 430: 14d1 push r4, r15 + 432: 1424 subi r14, r14, 16 + 434: 3303 movi r3, 3 + 436: b860 st.w r3, (r14, 0x0) + 438: 3840 cmpnei r0, 0 + 43a: 487f lsri r3, r0, 31 + 43c: b861 st.w r3, (r14, 0x4) + 43e: 0808 bt 0x44e // 44e <__floatsisf+0x1e> + 440: 3302 movi r3, 2 + 442: b860 st.w r3, (r14, 0x0) + 444: 6c3b mov r0, r14 + 446: e00001c1 bsr 0x7c8 // 7c8 <__pack_f> + 44a: 1404 addi r14, r14, 16 + 44c: 1491 pop r4, r15 + 44e: 331e movi r3, 30 + 450: 38df btsti r0, 31 + 452: b862 st.w r3, (r14, 0x8) + 454: 080f bt 0x472 // 472 <__floatsisf+0x42> + 456: 6d03 mov r4, r0 + 458: 6c13 mov r0, r4 + 45a: e0000197 bsr 0x788 // 788 <__clzsi2> + 45e: 5863 subi r3, r0, 1 + 460: 3b40 cmpnei r3, 0 + 462: 0c14 bf 0x48a // 48a <__floatsisf+0x5a> + 464: 6c13 mov r0, r4 + 466: 321e movi r2, 30 + 468: 700c lsl r0, r3 + 46a: 5a6d subu r3, r2, r3 + 46c: b803 st.w r0, (r14, 0xc) + 46e: b862 st.w r3, (r14, 0x8) + 470: 07ea br 0x444 // 444 <__floatsisf+0x14> + 472: 3380 movi r3, 128 + 474: 4378 lsli r3, r3, 24 + 476: 64c2 cmpne r0, r3 + 478: 0c0b bf 0x48e // 48e <__floatsisf+0x5e> + 47a: 3400 movi r4, 0 + 47c: 6102 subu r4, r0 + 47e: 6c13 mov r0, r4 + 480: e0000184 bsr 0x788 // 788 <__clzsi2> + 484: 5863 subi r3, r0, 1 + 486: 3b40 cmpnei r3, 0 + 488: 0bee bt 0x464 // 464 <__floatsisf+0x34> + 48a: b883 st.w r4, (r14, 0xc) + 48c: 07dc br 0x444 // 444 <__floatsisf+0x14> + 48e: 30cf movi r0, 207 + 490: 4018 lsli r0, r0, 24 + 492: 07dc br 0x44a // 44a <__floatsisf+0x1a> + +00000494 <__fixsfsi>: + 494: 14d0 push r15 + 496: 1425 subi r14, r14, 20 + 498: b800 st.w r0, (r14, 0x0) + 49a: 1901 addi r1, r14, 4 + 49c: 6c3b mov r0, r14 + 49e: e00001f1 bsr 0x880 // 880 <__unpack_f> + 4a2: 9861 ld.w r3, (r14, 0x4) + 4a4: 3b02 cmphsi r3, 3 + 4a6: 0c1b bf 0x4dc // 4dc <__fixsfsi+0x48> + 4a8: 3b44 cmpnei r3, 4 + 4aa: 0c06 bf 0x4b6 // 4b6 <__fixsfsi+0x22> + 4ac: 9863 ld.w r3, (r14, 0xc) + 4ae: 3bdf btsti r3, 31 + 4b0: 0816 bt 0x4dc // 4dc <__fixsfsi+0x48> + 4b2: 3b3e cmplti r3, 31 + 4b4: 0809 bt 0x4c6 // 4c6 <__fixsfsi+0x32> + 4b6: 9862 ld.w r3, (r14, 0x8) + 4b8: 3b40 cmpnei r3, 0 + 4ba: 3000 movi r0, 0 + 4bc: 6001 addc r0, r0 + 4be: 106a lrw r3, 0x7fffffff // 4e4 <__fixsfsi+0x50> + 4c0: 600c addu r0, r3 + 4c2: 1405 addi r14, r14, 20 + 4c4: 1490 pop r15 + 4c6: 321e movi r2, 30 + 4c8: 5a6d subu r3, r2, r3 + 4ca: 9804 ld.w r0, (r14, 0x10) + 4cc: 700d lsr r0, r3 + 4ce: 9862 ld.w r3, (r14, 0x8) + 4d0: 3b40 cmpnei r3, 0 + 4d2: 0ff8 bf 0x4c2 // 4c2 <__fixsfsi+0x2e> + 4d4: 3300 movi r3, 0 + 4d6: 5b01 subu r0, r3, r0 + 4d8: 1405 addi r14, r14, 20 + 4da: 1490 pop r15 + 4dc: 3000 movi r0, 0 + 4de: 1405 addi r14, r14, 20 + 4e0: 1490 pop r15 + 4e2: 0000 bkpt + 4e4: 7fffffff .long 0x7fffffff + +000004e8 <__extendsfdf2>: + 4e8: 14d1 push r4, r15 + 4ea: 1426 subi r14, r14, 24 + 4ec: b801 st.w r0, (r14, 0x4) + 4ee: 1902 addi r1, r14, 8 + 4f0: 1801 addi r0, r14, 4 + 4f2: e00001c7 bsr 0x880 // 880 <__unpack_f> + 4f6: 9865 ld.w r3, (r14, 0x14) + 4f8: 4b82 lsri r4, r3, 2 + 4fa: 9844 ld.w r2, (r14, 0x10) + 4fc: 437e lsli r3, r3, 30 + 4fe: 9823 ld.w r1, (r14, 0xc) + 500: 9802 ld.w r0, (r14, 0x8) + 502: b880 st.w r4, (r14, 0x0) + 504: e0000116 bsr 0x730 // 730 <__make_dp> + 508: 1406 addi r14, r14, 24 + 50a: 1491 pop r4, r15 + +0000050c <__floatunsisf>: + 50c: 14d2 push r4-r5, r15 + 50e: 1424 subi r14, r14, 16 + 510: 3840 cmpnei r0, 0 + 512: 3300 movi r3, 0 + 514: 6d03 mov r4, r0 + 516: b861 st.w r3, (r14, 0x4) + 518: 0c15 bf 0x542 // 542 <__floatunsisf+0x36> + 51a: 3303 movi r3, 3 + 51c: 351e movi r5, 30 + 51e: b860 st.w r3, (r14, 0x0) + 520: b8a2 st.w r5, (r14, 0x8) + 522: e0000133 bsr 0x788 // 788 <__clzsi2> + 526: 3840 cmpnei r0, 0 + 528: 5863 subi r3, r0, 1 + 52a: 0c13 bf 0x550 // 550 <__floatunsisf+0x44> + 52c: 3b40 cmpnei r3, 0 + 52e: 0c1d bf 0x568 // 568 <__floatunsisf+0x5c> + 530: 710c lsl r4, r3 + 532: 614e subu r5, r3 + 534: b883 st.w r4, (r14, 0xc) + 536: b8a2 st.w r5, (r14, 0x8) + 538: 6c3b mov r0, r14 + 53a: e0000147 bsr 0x7c8 // 7c8 <__pack_f> + 53e: 1404 addi r14, r14, 16 + 540: 1492 pop r4-r5, r15 + 542: 3302 movi r3, 2 + 544: 6c3b mov r0, r14 + 546: b860 st.w r3, (r14, 0x0) + 548: e0000140 bsr 0x7c8 // 7c8 <__pack_f> + 54c: 1404 addi r14, r14, 16 + 54e: 1492 pop r4-r5, r15 + 550: 3301 movi r3, 1 + 552: 68d0 and r3, r4 + 554: 4c81 lsri r4, r4, 1 + 556: 6d0c or r4, r3 + 558: 6c3b mov r0, r14 + 55a: 331f movi r3, 31 + 55c: b883 st.w r4, (r14, 0xc) + 55e: b862 st.w r3, (r14, 0x8) + 560: e0000134 bsr 0x7c8 // 7c8 <__pack_f> + 564: 1404 addi r14, r14, 16 + 566: 1492 pop r4-r5, r15 + 568: b883 st.w r4, (r14, 0xc) + 56a: 07e7 br 0x538 // 538 <__floatunsisf+0x2c> + +0000056c <__divdf3>: + 56c: 14d4 push r4-r7, r15 + 56e: 1432 subi r14, r14, 72 + 570: b804 st.w r0, (r14, 0x10) + 572: b825 st.w r1, (r14, 0x14) + 574: 1804 addi r0, r14, 16 + 576: 1908 addi r1, r14, 32 + 578: b867 st.w r3, (r14, 0x1c) + 57a: b846 st.w r2, (r14, 0x18) + 57c: e00002da bsr 0xb30 // b30 <__unpack_d> + 580: 190d addi r1, r14, 52 + 582: 1806 addi r0, r14, 24 + 584: e00002d6 bsr 0xb30 // b30 <__unpack_d> + 588: 9868 ld.w r3, (r14, 0x20) + 58a: 3b01 cmphsi r3, 2 + 58c: 0c66 bf 0x658 // 658 <__divdf3+0xec> + 58e: 982d ld.w r1, (r14, 0x34) + 590: 3901 cmphsi r1, 2 + 592: 0c92 bf 0x6b6 // 6b6 <__divdf3+0x14a> + 594: 9849 ld.w r2, (r14, 0x24) + 596: 980e ld.w r0, (r14, 0x38) + 598: 6c81 xor r2, r0 + 59a: 3b44 cmpnei r3, 4 + 59c: b849 st.w r2, (r14, 0x24) + 59e: 0c62 bf 0x662 // 662 <__divdf3+0xf6> + 5a0: 3b42 cmpnei r3, 2 + 5a2: 0c60 bf 0x662 // 662 <__divdf3+0xf6> + 5a4: 3944 cmpnei r1, 4 + 5a6: 0c62 bf 0x66a // 66a <__divdf3+0xfe> + 5a8: 3942 cmpnei r1, 2 + 5aa: 0c82 bf 0x6ae // 6ae <__divdf3+0x142> + 5ac: 982a ld.w r1, (r14, 0x28) + 5ae: 986f ld.w r3, (r14, 0x3c) + 5b0: 604e subu r1, r3 + 5b2: 9890 ld.w r4, (r14, 0x40) + 5b4: 98b1 ld.w r5, (r14, 0x44) + 5b6: 984b ld.w r2, (r14, 0x2c) + 5b8: 986c ld.w r3, (r14, 0x30) + 5ba: 654c cmphs r3, r5 + 5bc: b82a st.w r1, (r14, 0x28) + 5be: 6d93 mov r6, r4 + 5c0: 6dd7 mov r7, r5 + 5c2: 0c05 bf 0x5cc // 5cc <__divdf3+0x60> + 5c4: 64d6 cmpne r5, r3 + 5c6: 080b bt 0x5dc // 5dc <__divdf3+0x70> + 5c8: 6508 cmphs r2, r4 + 5ca: 0809 bt 0x5dc // 5dc <__divdf3+0x70> + 5cc: 4a9f lsri r4, r2, 31 + 5ce: 4301 lsli r0, r3, 1 + 5d0: 42a1 lsli r5, r2, 1 + 5d2: 6d00 or r4, r0 + 5d4: 2900 subi r1, 1 + 5d6: 6c97 mov r2, r5 + 5d8: 6cd3 mov r3, r4 + 5da: b82a st.w r1, (r14, 0x28) + 5dc: 3000 movi r0, 0 + 5de: 3100 movi r1, 0 + 5e0: b802 st.w r0, (r14, 0x8) + 5e2: b823 st.w r1, (r14, 0xc) + 5e4: 3180 movi r1, 128 + 5e6: 343d movi r4, 61 + 5e8: 3000 movi r0, 0 + 5ea: 4135 lsli r1, r1, 21 + 5ec: b8c0 st.w r6, (r14, 0x0) + 5ee: b8e1 st.w r7, (r14, 0x4) + 5f0: 98a0 ld.w r5, (r14, 0x0) + 5f2: 98c1 ld.w r6, (r14, 0x4) + 5f4: 658c cmphs r3, r6 + 5f6: 0c10 bf 0x616 // 616 <__divdf3+0xaa> + 5f8: 64da cmpne r6, r3 + 5fa: 0803 bt 0x600 // 600 <__divdf3+0x94> + 5fc: 6548 cmphs r2, r5 + 5fe: 0c0c bf 0x616 // 616 <__divdf3+0xaa> + 600: 98a2 ld.w r5, (r14, 0x8) + 602: 98c3 ld.w r6, (r14, 0xc) + 604: 6d40 or r5, r0 + 606: 6d84 or r6, r1 + 608: b8a2 st.w r5, (r14, 0x8) + 60a: b8c3 st.w r6, (r14, 0xc) + 60c: 98a0 ld.w r5, (r14, 0x0) + 60e: 98c1 ld.w r6, (r14, 0x4) + 610: 6488 cmphs r2, r2 + 612: 6097 subc r2, r5 + 614: 60db subc r3, r6 + 616: 41bf lsli r5, r1, 31 + 618: 48e1 lsri r7, r0, 1 + 61a: 6d97 mov r6, r5 + 61c: 49a1 lsri r5, r1, 1 + 61e: 6d9c or r6, r7 + 620: 6c57 mov r1, r5 + 622: 4abf lsri r5, r2, 31 + 624: 6c1b mov r0, r6 + 626: 2c00 subi r4, 1 + 628: 6d97 mov r6, r5 + 62a: 43a1 lsli r5, r3, 1 + 62c: 6d94 or r6, r5 + 62e: 4261 lsli r3, r2, 1 + 630: 3c40 cmpnei r4, 0 + 632: 6dcf mov r7, r3 + 634: 6c8f mov r2, r3 + 636: 6cdb mov r3, r6 + 638: 0bdc bt 0x5f0 // 5f0 <__divdf3+0x84> + 63a: 30ff movi r0, 255 + 63c: 3100 movi r1, 0 + 63e: 9882 ld.w r4, (r14, 0x8) + 640: 98a3 ld.w r5, (r14, 0xc) + 642: 6900 and r4, r0 + 644: 6944 and r5, r1 + 646: 6c13 mov r0, r4 + 648: 6c57 mov r1, r5 + 64a: 3480 movi r4, 128 + 64c: 6502 cmpne r0, r4 + 64e: 0c15 bf 0x678 // 678 <__divdf3+0x10c> + 650: 9862 ld.w r3, (r14, 0x8) + 652: 9883 ld.w r4, (r14, 0xc) + 654: b86b st.w r3, (r14, 0x2c) + 656: b88c st.w r4, (r14, 0x30) + 658: 1808 addi r0, r14, 32 + 65a: e000019d bsr 0x994 // 994 <__pack_d> + 65e: 1412 addi r14, r14, 72 + 660: 1494 pop r4-r7, r15 + 662: 644e cmpne r3, r1 + 664: 0bfa bt 0x658 // 658 <__divdf3+0xec> + 666: 1016 lrw r0, 0x58f8 // 6bc <__divdf3+0x150> + 668: 07f9 br 0x65a // 65a <__divdf3+0xee> + 66a: 3300 movi r3, 0 + 66c: 3400 movi r4, 0 + 66e: b86b st.w r3, (r14, 0x2c) + 670: b88c st.w r4, (r14, 0x30) + 672: b86a st.w r3, (r14, 0x28) + 674: 1808 addi r0, r14, 32 + 676: 07f2 br 0x65a // 65a <__divdf3+0xee> + 678: 3940 cmpnei r1, 0 + 67a: 0beb bt 0x650 // 650 <__divdf3+0xe4> + 67c: 3180 movi r1, 128 + 67e: 4121 lsli r1, r1, 1 + 680: 9882 ld.w r4, (r14, 0x8) + 682: 98a3 ld.w r5, (r14, 0xc) + 684: 6850 and r1, r4 + 686: 3940 cmpnei r1, 0 + 688: 0be4 bt 0x650 // 650 <__divdf3+0xe4> + 68a: 6c98 or r2, r6 + 68c: 3a40 cmpnei r2, 0 + 68e: 0fe1 bf 0x650 // 650 <__divdf3+0xe4> + 690: 3280 movi r2, 128 + 692: 3300 movi r3, 0 + 694: 6c13 mov r0, r4 + 696: 6c57 mov r1, r5 + 698: 6401 cmplt r0, r0 + 69a: 6009 addc r0, r2 + 69c: 604d addc r1, r3 + 69e: 6c83 mov r2, r0 + 6a0: 6cc7 mov r3, r1 + 6a2: 6c0b mov r0, r2 + 6a4: 31ff movi r1, 255 + 6a6: 6805 andn r0, r1 + 6a8: b802 st.w r0, (r14, 0x8) + 6aa: b863 st.w r3, (r14, 0xc) + 6ac: 07d2 br 0x650 // 650 <__divdf3+0xe4> + 6ae: 3304 movi r3, 4 + 6b0: b868 st.w r3, (r14, 0x20) + 6b2: 1808 addi r0, r14, 32 + 6b4: 07d3 br 0x65a // 65a <__divdf3+0xee> + 6b6: 180d addi r0, r14, 52 + 6b8: 07d1 br 0x65a // 65a <__divdf3+0xee> + 6ba: 0000 bkpt + 6bc: 000058f8 .long 0x000058f8 + +000006c0 <__floatsidf>: + 6c0: 14d1 push r4, r15 + 6c2: 1425 subi r14, r14, 20 + 6c4: 3303 movi r3, 3 + 6c6: b860 st.w r3, (r14, 0x0) + 6c8: 3840 cmpnei r0, 0 + 6ca: 487f lsri r3, r0, 31 + 6cc: b861 st.w r3, (r14, 0x4) + 6ce: 0808 bt 0x6de // 6de <__floatsidf+0x1e> + 6d0: 3302 movi r3, 2 + 6d2: b860 st.w r3, (r14, 0x0) + 6d4: 6c3b mov r0, r14 + 6d6: e000015f bsr 0x994 // 994 <__pack_d> + 6da: 1405 addi r14, r14, 20 + 6dc: 1491 pop r4, r15 + 6de: 38df btsti r0, 31 + 6e0: 0812 bt 0x704 // 704 <__floatsidf+0x44> + 6e2: 6d03 mov r4, r0 + 6e4: 6c13 mov r0, r4 + 6e6: e0000051 bsr 0x788 // 788 <__clzsi2> + 6ea: 321d movi r2, 29 + 6ec: 6080 addu r2, r0 + 6ee: 2802 subi r0, 3 + 6f0: 38df btsti r0, 31 + 6f2: 0810 bt 0x712 // 712 <__floatsidf+0x52> + 6f4: 7100 lsl r4, r0 + 6f6: 3300 movi r3, 0 + 6f8: b884 st.w r4, (r14, 0x10) + 6fa: b863 st.w r3, (r14, 0xc) + 6fc: 333c movi r3, 60 + 6fe: 60ca subu r3, r2 + 700: b862 st.w r3, (r14, 0x8) + 702: 07e9 br 0x6d4 // 6d4 <__floatsidf+0x14> + 704: 3380 movi r3, 128 + 706: 4378 lsli r3, r3, 24 + 708: 64c2 cmpne r0, r3 + 70a: 0c0d bf 0x724 // 724 <__floatsidf+0x64> + 70c: 3400 movi r4, 0 + 70e: 6102 subu r4, r0 + 710: 07ea br 0x6e4 // 6e4 <__floatsidf+0x24> + 712: 311f movi r1, 31 + 714: 4c61 lsri r3, r4, 1 + 716: 604a subu r1, r2 + 718: 6c13 mov r0, r4 + 71a: 70c5 lsr r3, r1 + 71c: 7008 lsl r0, r2 + 71e: b864 st.w r3, (r14, 0x10) + 720: b803 st.w r0, (r14, 0xc) + 722: 07ed br 0x6fc // 6fc <__floatsidf+0x3c> + 724: 3000 movi r0, 0 + 726: 1022 lrw r1, 0xc1e00000 // 72c <__floatsidf+0x6c> + 728: 07d9 br 0x6da // 6da <__floatsidf+0x1a> + 72a: 0000 bkpt + 72c: c1e00000 .long 0xc1e00000 + +00000730 <__make_dp>: + 730: 1421 subi r14, r14, 4 + 732: 14d1 push r4, r15 + 734: 1425 subi r14, r14, 20 + 736: b867 st.w r3, (r14, 0x1c) + 738: 9867 ld.w r3, (r14, 0x1c) + 73a: 9888 ld.w r4, (r14, 0x20) + 73c: b800 st.w r0, (r14, 0x0) + 73e: 6c3b mov r0, r14 + 740: b821 st.w r1, (r14, 0x4) + 742: b842 st.w r2, (r14, 0x8) + 744: b863 st.w r3, (r14, 0xc) + 746: b884 st.w r4, (r14, 0x10) + 748: e0000126 bsr 0x994 // 994 <__pack_d> + 74c: 1405 addi r14, r14, 20 + 74e: d9ee2001 ld.w r15, (r14, 0x4) + 752: 9880 ld.w r4, (r14, 0x0) + 754: 1403 addi r14, r14, 12 + 756: 783c jmp r15 + +00000758 <__truncdfsf2>: + 758: 14d0 push r15 + 75a: 1427 subi r14, r14, 28 + 75c: b800 st.w r0, (r14, 0x0) + 75e: b821 st.w r1, (r14, 0x4) + 760: 6c3b mov r0, r14 + 762: 1902 addi r1, r14, 8 + 764: e00001e6 bsr 0xb30 // b30 <__unpack_d> + 768: 9845 ld.w r2, (r14, 0x14) + 76a: 4a3e lsri r1, r2, 30 + 76c: 9866 ld.w r3, (r14, 0x18) + 76e: 4242 lsli r2, r2, 2 + 770: 4362 lsli r3, r3, 2 + 772: 3a40 cmpnei r2, 0 + 774: 6cc4 or r3, r1 + 776: 0c02 bf 0x77a // 77a <__truncdfsf2+0x22> + 778: 3ba0 bseti r3, 0 + 77a: 9844 ld.w r2, (r14, 0x10) + 77c: 9823 ld.w r1, (r14, 0xc) + 77e: 9802 ld.w r0, (r14, 0x8) + 780: e00000fe bsr 0x97c // 97c <__make_fp> + 784: 1407 addi r14, r14, 28 + 786: 1490 pop r15 + +00000788 <__clzsi2>: + 788: 106d lrw r3, 0xffff // 7bc <__clzsi2+0x34> + 78a: 640c cmphs r3, r0 + 78c: 0c07 bf 0x79a // 79a <__clzsi2+0x12> + 78e: 33ff movi r3, 255 + 790: 640c cmphs r3, r0 + 792: 0c0f bf 0x7b0 // 7b0 <__clzsi2+0x28> + 794: 3320 movi r3, 32 + 796: 3200 movi r2, 0 + 798: 0406 br 0x7a4 // 7a4 <__clzsi2+0x1c> + 79a: 106a lrw r3, 0xffffff // 7c0 <__clzsi2+0x38> + 79c: 640c cmphs r3, r0 + 79e: 080c bt 0x7b6 // 7b6 <__clzsi2+0x2e> + 7a0: 3308 movi r3, 8 + 7a2: 3218 movi r2, 24 + 7a4: 7009 lsr r0, r2 + 7a6: 1048 lrw r2, 0x590c // 7c4 <__clzsi2+0x3c> + 7a8: 6008 addu r0, r2 + 7aa: 8040 ld.b r2, (r0, 0x0) + 7ac: 5b09 subu r0, r3, r2 + 7ae: 783c jmp r15 + 7b0: 3318 movi r3, 24 + 7b2: 3208 movi r2, 8 + 7b4: 07f8 br 0x7a4 // 7a4 <__clzsi2+0x1c> + 7b6: 3310 movi r3, 16 + 7b8: 3210 movi r2, 16 + 7ba: 07f5 br 0x7a4 // 7a4 <__clzsi2+0x1c> + 7bc: 0000ffff .long 0x0000ffff + 7c0: 00ffffff .long 0x00ffffff + 7c4: 0000590c .long 0x0000590c + +000007c8 <__pack_f>: + 7c8: 14c2 push r4-r5 + 7ca: 9040 ld.w r2, (r0, 0x0) + 7cc: 3a01 cmphsi r2, 2 + 7ce: 9063 ld.w r3, (r0, 0xc) + 7d0: 9021 ld.w r1, (r0, 0x4) + 7d2: 0c27 bf 0x820 // 820 <__pack_f+0x58> + 7d4: 3a44 cmpnei r2, 4 + 7d6: 0c22 bf 0x81a // 81a <__pack_f+0x52> + 7d8: 3a42 cmpnei r2, 2 + 7da: 0c1d bf 0x814 // 814 <__pack_f+0x4c> + 7dc: 3b40 cmpnei r3, 0 + 7de: 0c1b bf 0x814 // 814 <__pack_f+0x4c> + 7e0: 3400 movi r4, 0 + 7e2: 9042 ld.w r2, (r0, 0x8) + 7e4: 2c7d subi r4, 126 + 7e6: 6509 cmplt r2, r4 + 7e8: 082a bt 0x83c // 83c <__pack_f+0x74> + 7ea: 347f movi r4, 127 + 7ec: 6491 cmplt r4, r2 + 7ee: 0816 bt 0x81a // 81a <__pack_f+0x52> + 7f0: 690c and r4, r3 + 7f2: 3540 movi r5, 64 + 7f4: 6552 cmpne r4, r5 + 7f6: 0c1a bf 0x82a // 82a <__pack_f+0x62> + 7f8: 233e addi r3, 63 + 7fa: 3bdf btsti r3, 31 + 7fc: 081d bt 0x836 // 836 <__pack_f+0x6e> + 7fe: 227e addi r2, 127 + 800: 4302 lsli r0, r3, 2 + 802: 4809 lsri r0, r0, 9 + 804: 74c8 zextb r3, r2 + 806: 4009 lsli r0, r0, 9 + 808: 4377 lsli r3, r3, 23 + 80a: 4809 lsri r0, r0, 9 + 80c: 413f lsli r1, r1, 31 + 80e: 6c0c or r0, r3 + 810: 6c04 or r0, r1 + 812: 1482 pop r4-r5 + 814: 3300 movi r3, 0 + 816: 3000 movi r0, 0 + 818: 07f7 br 0x806 // 806 <__pack_f+0x3e> + 81a: 33ff movi r3, 255 + 81c: 3000 movi r0, 0 + 81e: 07f4 br 0x806 // 806 <__pack_f+0x3e> + 820: 4303 lsli r0, r3, 3 + 822: 480a lsri r0, r0, 10 + 824: 38b6 bseti r0, 22 + 826: 33ff movi r3, 255 + 828: 07ef br 0x806 // 806 <__pack_f+0x3e> + 82a: 3080 movi r0, 128 + 82c: 680c and r0, r3 + 82e: 3840 cmpnei r0, 0 + 830: 0fe5 bf 0x7fa // 7fa <__pack_f+0x32> + 832: 60d0 addu r3, r4 + 834: 07e3 br 0x7fa // 7fa <__pack_f+0x32> + 836: 4b61 lsri r3, r3, 1 + 838: 227f addi r2, 128 + 83a: 07e3 br 0x800 // 800 <__pack_f+0x38> + 83c: 610a subu r4, r2 + 83e: 3c39 cmplti r4, 26 + 840: 0fea bf 0x814 // 814 <__pack_f+0x4c> + 842: 3201 movi r2, 1 + 844: 7090 lsl r2, r4 + 846: 2a00 subi r2, 1 + 848: 6c0f mov r0, r3 + 84a: 68c8 and r3, r2 + 84c: 3b40 cmpnei r3, 0 + 84e: 3300 movi r3, 0 + 850: 7011 lsr r0, r4 + 852: 60cd addc r3, r3 + 854: 6cc0 or r3, r0 + 856: 307f movi r0, 127 + 858: 680c and r0, r3 + 85a: 3240 movi r2, 64 + 85c: 6482 cmpne r0, r2 + 85e: 080d bt 0x878 // 878 <__pack_f+0xb0> + 860: 3280 movi r2, 128 + 862: 688c and r2, r3 + 864: 3a40 cmpnei r2, 0 + 866: 0c02 bf 0x86a // 86a <__pack_f+0xa2> + 868: 60c0 addu r3, r0 + 86a: 1045 lrw r2, 0x3fffffff // 87c <__pack_f+0xb4> + 86c: 64c8 cmphs r2, r3 + 86e: 4302 lsli r0, r3, 2 + 870: 64c3 mvcv r3 + 872: 4809 lsri r0, r0, 9 + 874: 74cc zextb r3, r3 + 876: 07c8 br 0x806 // 806 <__pack_f+0x3e> + 878: 233e addi r3, 63 + 87a: 07f8 br 0x86a // 86a <__pack_f+0xa2> + 87c: 3fffffff .long 0x3fffffff + +00000880 <__unpack_f>: + 880: 14c1 push r4 + 882: 8861 ld.h r3, (r0, 0x2) + 884: 4371 lsli r3, r3, 17 + 886: 9040 ld.w r2, (r0, 0x0) + 888: 4b78 lsri r3, r3, 24 + 88a: 8003 ld.b r0, (r0, 0x3) + 88c: 4249 lsli r2, r2, 9 + 88e: 4807 lsri r0, r0, 7 + 890: 3b40 cmpnei r3, 0 + 892: 4a49 lsri r2, r2, 9 + 894: b101 st.w r0, (r1, 0x4) + 896: 0811 bt 0x8b8 // 8b8 <__unpack_f+0x38> + 898: 3a40 cmpnei r2, 0 + 89a: 0c1a bf 0x8ce // 8ce <__unpack_f+0x4e> + 89c: 3303 movi r3, 3 + 89e: b160 st.w r3, (r1, 0x0) + 8a0: 3300 movi r3, 0 + 8a2: 4247 lsli r2, r2, 7 + 8a4: 2b7e subi r3, 127 + 8a6: 1096 lrw r4, 0x3fffffff // 8fc <__unpack_f+0x7c> + 8a8: 4241 lsli r2, r2, 1 + 8aa: 6490 cmphs r4, r2 + 8ac: 6c0f mov r0, r3 + 8ae: 2b00 subi r3, 1 + 8b0: 0bfc bt 0x8a8 // 8a8 <__unpack_f+0x28> + 8b2: b102 st.w r0, (r1, 0x8) + 8b4: b143 st.w r2, (r1, 0xc) + 8b6: 1481 pop r4 + 8b8: 30ff movi r0, 255 + 8ba: 640e cmpne r3, r0 + 8bc: 0c0c bf 0x8d4 // 8d4 <__unpack_f+0x54> + 8be: 2b7e subi r3, 127 + 8c0: 4247 lsli r2, r2, 7 + 8c2: b162 st.w r3, (r1, 0x8) + 8c4: 3abe bseti r2, 30 + 8c6: 3303 movi r3, 3 + 8c8: b160 st.w r3, (r1, 0x0) + 8ca: b143 st.w r2, (r1, 0xc) + 8cc: 1481 pop r4 + 8ce: 3302 movi r3, 2 + 8d0: b160 st.w r3, (r1, 0x0) + 8d2: 1481 pop r4 + 8d4: 3a40 cmpnei r2, 0 + 8d6: 0c0d bf 0x8f0 // 8f0 <__unpack_f+0x70> + 8d8: 3380 movi r3, 128 + 8da: 436f lsli r3, r3, 15 + 8dc: 68c8 and r3, r2 + 8de: 3b40 cmpnei r3, 0 + 8e0: 0c0b bf 0x8f6 // 8f6 <__unpack_f+0x76> + 8e2: 3301 movi r3, 1 + 8e4: b160 st.w r3, (r1, 0x0) + 8e6: 1067 lrw r3, 0x2000007f // 900 <__unpack_f+0x80> + 8e8: 4247 lsli r2, r2, 7 + 8ea: 688d andn r2, r3 + 8ec: b143 st.w r2, (r1, 0xc) + 8ee: 1481 pop r4 + 8f0: 3304 movi r3, 4 + 8f2: b160 st.w r3, (r1, 0x0) + 8f4: 1481 pop r4 + 8f6: b160 st.w r3, (r1, 0x0) + 8f8: 07f7 br 0x8e6 // 8e6 <__unpack_f+0x66> + 8fa: 0000 bkpt + 8fc: 3fffffff .long 0x3fffffff + 900: 2000007f .long 0x2000007f + +00000904 <__fpcmp_parts_f>: + 904: 14c1 push r4 + 906: 9060 ld.w r3, (r0, 0x0) + 908: 3b01 cmphsi r3, 2 + 90a: 0c12 bf 0x92e // 92e <__fpcmp_parts_f+0x2a> + 90c: 9140 ld.w r2, (r1, 0x0) + 90e: 3a01 cmphsi r2, 2 + 910: 0c0f bf 0x92e // 92e <__fpcmp_parts_f+0x2a> + 912: 3b44 cmpnei r3, 4 + 914: 0c17 bf 0x942 // 942 <__fpcmp_parts_f+0x3e> + 916: 3a44 cmpnei r2, 4 + 918: 0c0f bf 0x936 // 936 <__fpcmp_parts_f+0x32> + 91a: 3b42 cmpnei r3, 2 + 91c: 0c0b bf 0x932 // 932 <__fpcmp_parts_f+0x2e> + 91e: 3a42 cmpnei r2, 2 + 920: 0c13 bf 0x946 // 946 <__fpcmp_parts_f+0x42> + 922: 9061 ld.w r3, (r0, 0x4) + 924: 9141 ld.w r2, (r1, 0x4) + 926: 648e cmpne r3, r2 + 928: 0c14 bf 0x950 // 950 <__fpcmp_parts_f+0x4c> + 92a: 3b40 cmpnei r3, 0 + 92c: 0808 bt 0x93c // 93c <__fpcmp_parts_f+0x38> + 92e: 3001 movi r0, 1 + 930: 1481 pop r4 + 932: 3a42 cmpnei r2, 2 + 934: 0c1e bf 0x970 // 970 <__fpcmp_parts_f+0x6c> + 936: 9161 ld.w r3, (r1, 0x4) + 938: 3b40 cmpnei r3, 0 + 93a: 0bfa bt 0x92e // 92e <__fpcmp_parts_f+0x2a> + 93c: 3000 movi r0, 0 + 93e: 2800 subi r0, 1 + 940: 1481 pop r4 + 942: 3a44 cmpnei r2, 4 + 944: 0c18 bf 0x974 // 974 <__fpcmp_parts_f+0x70> + 946: 9061 ld.w r3, (r0, 0x4) + 948: 3b40 cmpnei r3, 0 + 94a: 0bf9 bt 0x93c // 93c <__fpcmp_parts_f+0x38> + 94c: 3001 movi r0, 1 + 94e: 07f1 br 0x930 // 930 <__fpcmp_parts_f+0x2c> + 950: 9082 ld.w r4, (r0, 0x8) + 952: 9142 ld.w r2, (r1, 0x8) + 954: 6509 cmplt r2, r4 + 956: 0bea bt 0x92a // 92a <__fpcmp_parts_f+0x26> + 958: 6491 cmplt r4, r2 + 95a: 0807 bt 0x968 // 968 <__fpcmp_parts_f+0x64> + 95c: 9003 ld.w r0, (r0, 0xc) + 95e: 9143 ld.w r2, (r1, 0xc) + 960: 6408 cmphs r2, r0 + 962: 0fe4 bf 0x92a // 92a <__fpcmp_parts_f+0x26> + 964: 6480 cmphs r0, r2 + 966: 0805 bt 0x970 // 970 <__fpcmp_parts_f+0x6c> + 968: 3b40 cmpnei r3, 0 + 96a: 0fe9 bf 0x93c // 93c <__fpcmp_parts_f+0x38> + 96c: 3001 movi r0, 1 + 96e: 07e1 br 0x930 // 930 <__fpcmp_parts_f+0x2c> + 970: 3000 movi r0, 0 + 972: 1481 pop r4 + 974: 9161 ld.w r3, (r1, 0x4) + 976: 9041 ld.w r2, (r0, 0x4) + 978: 5b09 subu r0, r3, r2 + 97a: 1481 pop r4 + +0000097c <__make_fp>: + 97c: 14d0 push r15 + 97e: 1424 subi r14, r14, 16 + 980: b800 st.w r0, (r14, 0x0) + 982: 6c3b mov r0, r14 + 984: b821 st.w r1, (r14, 0x4) + 986: b842 st.w r2, (r14, 0x8) + 988: b863 st.w r3, (r14, 0xc) + 98a: e3ffff1f bsr 0x7c8 // 7c8 <__pack_f> + 98e: 1404 addi r14, r14, 16 + 990: 1490 pop r15 + ... + +00000994 <__pack_d>: + 994: 14c4 push r4-r7 + 996: 1422 subi r14, r14, 8 + 998: 9060 ld.w r3, (r0, 0x0) + 99a: 3b01 cmphsi r3, 2 + 99c: 90c3 ld.w r6, (r0, 0xc) + 99e: 90e4 ld.w r7, (r0, 0x10) + 9a0: 9021 ld.w r1, (r0, 0x4) + 9a2: 0c46 bf 0xa2e // a2e <__pack_d+0x9a> + 9a4: 3b44 cmpnei r3, 4 + 9a6: 0c40 bf 0xa26 // a26 <__pack_d+0x92> + 9a8: 3b42 cmpnei r3, 2 + 9aa: 0c27 bf 0x9f8 // 9f8 <__pack_d+0x64> + 9ac: 6cdb mov r3, r6 + 9ae: 6cdc or r3, r7 + 9b0: 3b40 cmpnei r3, 0 + 9b2: 0c23 bf 0x9f8 // 9f8 <__pack_d+0x64> + 9b4: 9062 ld.w r3, (r0, 0x8) + 9b6: 125a lrw r2, 0xfffffc02 // b1c <__pack_d+0x188> + 9b8: 648d cmplt r3, r2 + 9ba: 0855 bt 0xa64 // a64 <__pack_d+0xd0> + 9bc: 1259 lrw r2, 0x3ff // b20 <__pack_d+0x18c> + 9be: 64c9 cmplt r2, r3 + 9c0: 0833 bt 0xa26 // a26 <__pack_d+0x92> + 9c2: 34ff movi r4, 255 + 9c4: 3500 movi r5, 0 + 9c6: 6918 and r4, r6 + 9c8: 695c and r5, r7 + 9ca: 3280 movi r2, 128 + 9cc: 6492 cmpne r4, r2 + 9ce: 0c3f bf 0xa4c // a4c <__pack_d+0xb8> + 9d0: 347f movi r4, 127 + 9d2: 3500 movi r5, 0 + 9d4: 6599 cmplt r6, r6 + 9d6: 6191 addc r6, r4 + 9d8: 61d5 addc r7, r5 + 9da: 1253 lrw r2, 0x1fffffff // b24 <__pack_d+0x190> + 9dc: 65c8 cmphs r2, r7 + 9de: 0c1a bf 0xa12 // a12 <__pack_d+0x7e> + 9e0: 1290 lrw r4, 0x3ff // b20 <__pack_d+0x18c> + 9e2: 610c addu r4, r3 + 9e4: 4718 lsli r0, r7, 24 + 9e6: 4f68 lsri r3, r7, 8 + 9e8: 4e48 lsri r2, r6, 8 + 9ea: 6c80 or r2, r0 + 9ec: 430c lsli r0, r3, 12 + 9ee: 486c lsri r3, r0, 12 + 9f0: 120e lrw r0, 0x7ff // b28 <__pack_d+0x194> + 9f2: 6d4b mov r5, r2 + 9f4: 6900 and r4, r0 + 9f6: 0404 br 0x9fe // 9fe <__pack_d+0x6a> + 9f8: 3400 movi r4, 0 + 9fa: 3200 movi r2, 0 + 9fc: 3300 movi r3, 0 + 9fe: 430c lsli r0, r3, 12 + a00: 480c lsri r0, r0, 12 + a02: 4474 lsli r3, r4, 20 + a04: 419f lsli r4, r1, 31 + a06: 6c43 mov r1, r0 + a08: 6c4c or r1, r3 + a0a: 6c50 or r1, r4 + a0c: 6c0b mov r0, r2 + a0e: 1402 addi r14, r14, 8 + a10: 1484 pop r4-r7 + a12: 479f lsli r4, r7, 31 + a14: 4e01 lsri r0, r6, 1 + a16: 6d00 or r4, r0 + a18: 6d93 mov r6, r4 + a1a: 3480 movi r4, 128 + a1c: 4f41 lsri r2, r7, 1 + a1e: 4483 lsli r4, r4, 3 + a20: 6dcb mov r7, r2 + a22: 610c addu r4, r3 + a24: 07e0 br 0x9e4 // 9e4 <__pack_d+0x50> + a26: 1281 lrw r4, 0x7ff // b28 <__pack_d+0x194> + a28: 3200 movi r2, 0 + a2a: 3300 movi r3, 0 + a2c: 07e9 br 0x9fe // 9fe <__pack_d+0x6a> + a2e: 4e08 lsri r0, r6, 8 + a30: 4798 lsli r4, r7, 24 + a32: 6d00 or r4, r0 + a34: 3580 movi r5, 128 + a36: 4705 lsli r0, r7, 5 + a38: 6c93 mov r2, r4 + a3a: 486d lsri r3, r0, 13 + a3c: 3400 movi r4, 0 + a3e: 45ac lsli r5, r5, 12 + a40: 6c90 or r2, r4 + a42: 6cd4 or r3, r5 + a44: 430c lsli r0, r3, 12 + a46: 486c lsri r3, r0, 12 + a48: 1198 lrw r4, 0x7ff // b28 <__pack_d+0x194> + a4a: 07da br 0x9fe // 9fe <__pack_d+0x6a> + a4c: 3d40 cmpnei r5, 0 + a4e: 0bc1 bt 0x9d0 // 9d0 <__pack_d+0x3c> + a50: 4241 lsli r2, r2, 1 + a52: 6898 and r2, r6 + a54: 3a40 cmpnei r2, 0 + a56: 0fc2 bf 0x9da // 9da <__pack_d+0x46> + a58: 3480 movi r4, 128 + a5a: 3500 movi r5, 0 + a5c: 6599 cmplt r6, r6 + a5e: 6191 addc r6, r4 + a60: 61d5 addc r7, r5 + a62: 07bc br 0x9da // 9da <__pack_d+0x46> + a64: 5a6d subu r3, r2, r3 + a66: 3238 movi r2, 56 + a68: 64c9 cmplt r2, r3 + a6a: 0bc7 bt 0x9f8 // 9f8 <__pack_d+0x64> + a6c: 3200 movi r2, 0 + a6e: 2a1f subi r2, 32 + a70: 608c addu r2, r3 + a72: 3adf btsti r2, 31 + a74: 0848 bt 0xb04 // b04 <__pack_d+0x170> + a76: 6c1f mov r0, r7 + a78: 7009 lsr r0, r2 + a7a: b800 st.w r0, (r14, 0x0) + a7c: 3000 movi r0, 0 + a7e: b801 st.w r0, (r14, 0x4) + a80: 3adf btsti r2, 31 + a82: 083c bt 0xafa // afa <__pack_d+0x166> + a84: 3301 movi r3, 1 + a86: 70c8 lsl r3, r2 + a88: 6d4f mov r5, r3 + a8a: 3300 movi r3, 0 + a8c: 6d0f mov r4, r3 + a8e: 3200 movi r2, 0 + a90: 3300 movi r3, 0 + a92: 2a00 subi r2, 1 + a94: 2b00 subi r3, 1 + a96: 6511 cmplt r4, r4 + a98: 6109 addc r4, r2 + a9a: 614d addc r5, r3 + a9c: 6990 and r6, r4 + a9e: 69d4 and r7, r5 + aa0: 6d9c or r6, r7 + aa2: 3e40 cmpnei r6, 0 + aa4: 3000 movi r0, 0 + aa6: 6001 addc r0, r0 + aa8: 6c83 mov r2, r0 + aaa: 3300 movi r3, 0 + aac: 9880 ld.w r4, (r14, 0x0) + aae: 98a1 ld.w r5, (r14, 0x4) + ab0: 6d08 or r4, r2 + ab2: 6d4c or r5, r3 + ab4: 32ff movi r2, 255 + ab6: 3300 movi r3, 0 + ab8: 6890 and r2, r4 + aba: 68d4 and r3, r5 + abc: 3080 movi r0, 128 + abe: 640a cmpne r2, r0 + ac0: 081b bt 0xaf6 // af6 <__pack_d+0x162> + ac2: 3b40 cmpnei r3, 0 + ac4: 0819 bt 0xaf6 // af6 <__pack_d+0x162> + ac6: 3380 movi r3, 128 + ac8: 4361 lsli r3, r3, 1 + aca: 68d0 and r3, r4 + acc: 3b40 cmpnei r3, 0 + ace: 0c06 bf 0xada // ada <__pack_d+0x146> + ad0: 3280 movi r2, 128 + ad2: 3300 movi r3, 0 + ad4: 6511 cmplt r4, r4 + ad6: 6109 addc r4, r2 + ad8: 614d addc r5, r3 + ada: 4518 lsli r0, r5, 24 + adc: 4c48 lsri r2, r4, 8 + ade: 4d68 lsri r3, r5, 8 + ae0: 1093 lrw r4, 0xfffffff // b2c <__pack_d+0x198> + ae2: 6c80 or r2, r0 + ae4: 6550 cmphs r4, r5 + ae6: 430c lsli r0, r3, 12 + ae8: 486c lsri r3, r0, 12 + aea: 3001 movi r0, 1 + aec: 0c02 bf 0xaf0 // af0 <__pack_d+0x15c> + aee: 3000 movi r0, 0 + af0: 108e lrw r4, 0x7ff // b28 <__pack_d+0x194> + af2: 6900 and r4, r0 + af4: 0785 br 0x9fe // 9fe <__pack_d+0x6a> + af6: 327f movi r2, 127 + af8: 07ed br 0xad2 // ad2 <__pack_d+0x13e> + afa: 3201 movi r2, 1 + afc: 708c lsl r2, r3 + afe: 3500 movi r5, 0 + b00: 6d0b mov r4, r2 + b02: 07c6 br 0xa8e // a8e <__pack_d+0xfa> + b04: 341f movi r4, 31 + b06: 610e subu r4, r3 + b08: 4701 lsli r0, r7, 1 + b0a: 7010 lsl r0, r4 + b0c: 6d1b mov r4, r6 + b0e: 710d lsr r4, r3 + b10: 6d00 or r4, r0 + b12: 6c1f mov r0, r7 + b14: 700d lsr r0, r3 + b16: b880 st.w r4, (r14, 0x0) + b18: b801 st.w r0, (r14, 0x4) + b1a: 07b3 br 0xa80 // a80 <__pack_d+0xec> + b1c: fffffc02 .long 0xfffffc02 + b20: 000003ff .long 0x000003ff + b24: 1fffffff .long 0x1fffffff + b28: 000007ff .long 0x000007ff + b2c: 0fffffff .long 0x0fffffff + +00000b30 <__unpack_d>: + b30: 1423 subi r14, r14, 12 + b32: b880 st.w r4, (r14, 0x0) + b34: b8c1 st.w r6, (r14, 0x4) + b36: b8e2 st.w r7, (r14, 0x8) + b38: 8843 ld.h r2, (r0, 0x6) + b3a: 4251 lsli r2, r2, 17 + b3c: 9061 ld.w r3, (r0, 0x4) + b3e: 9080 ld.w r4, (r0, 0x0) + b40: 4a55 lsri r2, r2, 21 + b42: 8007 ld.b r0, (r0, 0x7) + b44: 436c lsli r3, r3, 12 + b46: 4807 lsri r0, r0, 7 + b48: 3a40 cmpnei r2, 0 + b4a: 4b6c lsri r3, r3, 12 + b4c: b101 st.w r0, (r1, 0x4) + b4e: 0819 bt 0xb80 // b80 <__unpack_d+0x50> + b50: 6c93 mov r2, r4 + b52: 6c8c or r2, r3 + b54: 3a40 cmpnei r2, 0 + b56: 0c2d bf 0xbb0 // bb0 <__unpack_d+0x80> + b58: 4c58 lsri r2, r4, 24 + b5a: 4368 lsli r3, r3, 8 + b5c: 6cc8 or r3, r2 + b5e: 3203 movi r2, 3 + b60: 4408 lsli r0, r4, 8 + b62: b140 st.w r2, (r1, 0x0) + b64: 1181 lrw r4, 0xfffffc01 // be8 <__unpack_d+0xb8> + b66: 11c2 lrw r6, 0xfffffff // bec <__unpack_d+0xbc> + b68: 485f lsri r2, r0, 31 + b6a: 4361 lsli r3, r3, 1 + b6c: 6cc8 or r3, r2 + b6e: 64d8 cmphs r6, r3 + b70: 6c93 mov r2, r4 + b72: 4001 lsli r0, r0, 1 + b74: 2c00 subi r4, 1 + b76: 0bf9 bt 0xb68 // b68 <__unpack_d+0x38> + b78: b142 st.w r2, (r1, 0x8) + b7a: b103 st.w r0, (r1, 0xc) + b7c: b164 st.w r3, (r1, 0x10) + b7e: 0414 br 0xba6 // ba6 <__unpack_d+0x76> + b80: 101c lrw r0, 0x7ff // bf0 <__unpack_d+0xc0> + b82: 640a cmpne r2, r0 + b84: 0c19 bf 0xbb6 // bb6 <__unpack_d+0x86> + b86: 1019 lrw r0, 0xfffffc01 // be8 <__unpack_d+0xb8> + b88: 6080 addu r2, r0 + b8a: b142 st.w r2, (r1, 0x8) + b8c: 3203 movi r2, 3 + b8e: 43e8 lsli r7, r3, 8 + b90: b140 st.w r2, (r1, 0x0) + b92: 3380 movi r3, 128 + b94: 4c58 lsri r2, r4, 24 + b96: 6dc8 or r7, r2 + b98: 44c8 lsli r6, r4, 8 + b9a: 3200 movi r2, 0 + b9c: 4375 lsli r3, r3, 21 + b9e: 6d88 or r6, r2 + ba0: 6dcc or r7, r3 + ba2: b1c3 st.w r6, (r1, 0xc) + ba4: b1e4 st.w r7, (r1, 0x10) + ba6: 98e2 ld.w r7, (r14, 0x8) + ba8: 98c1 ld.w r6, (r14, 0x4) + baa: 9880 ld.w r4, (r14, 0x0) + bac: 1403 addi r14, r14, 12 + bae: 783c jmp r15 + bb0: 3302 movi r3, 2 + bb2: b160 st.w r3, (r1, 0x0) + bb4: 07f9 br 0xba6 // ba6 <__unpack_d+0x76> + bb6: 6c93 mov r2, r4 + bb8: 6c8c or r2, r3 + bba: 3a40 cmpnei r2, 0 + bbc: 0c10 bf 0xbdc // bdc <__unpack_d+0xac> + bbe: 3280 movi r2, 128 + bc0: 424c lsli r2, r2, 12 + bc2: 688c and r2, r3 + bc4: 3a40 cmpnei r2, 0 + bc6: 0c0e bf 0xbe2 // be2 <__unpack_d+0xb2> + bc8: 3201 movi r2, 1 + bca: b140 st.w r2, (r1, 0x0) + bcc: 4c58 lsri r2, r4, 24 + bce: 4368 lsli r3, r3, 8 + bd0: 6cc8 or r3, r2 + bd2: 4408 lsli r0, r4, 8 + bd4: 3b9b bclri r3, 27 + bd6: b103 st.w r0, (r1, 0xc) + bd8: b164 st.w r3, (r1, 0x10) + bda: 07e6 br 0xba6 // ba6 <__unpack_d+0x76> + bdc: 3304 movi r3, 4 + bde: b160 st.w r3, (r1, 0x0) + be0: 07e3 br 0xba6 // ba6 <__unpack_d+0x76> + be2: b140 st.w r2, (r1, 0x0) + be4: 07f4 br 0xbcc // bcc <__unpack_d+0x9c> + be6: 0000 bkpt + be8: fffffc01 .long 0xfffffc01 + bec: 0fffffff .long 0x0fffffff + bf0: 000007ff .long 0x000007ff + +00000bf4 <__memset_fast>: + bf4: 14c3 push r4-r6 + bf6: 7444 zextb r1, r1 + bf8: 3a40 cmpnei r2, 0 + bfa: 0c1f bf 0xc38 // c38 <__memset_fast+0x44> + bfc: 6d43 mov r5, r0 + bfe: 6d03 mov r4, r0 + c00: 3603 movi r6, 3 + c02: 6918 and r4, r6 + c04: 3c40 cmpnei r4, 0 + c06: 0c1a bf 0xc3a // c3a <__memset_fast+0x46> + c08: a520 st.b r1, (r5, 0x0) + c0a: 2a00 subi r2, 1 + c0c: 3a40 cmpnei r2, 0 + c0e: 0c15 bf 0xc38 // c38 <__memset_fast+0x44> + c10: 2500 addi r5, 1 + c12: 6d17 mov r4, r5 + c14: 3603 movi r6, 3 + c16: 6918 and r4, r6 + c18: 3c40 cmpnei r4, 0 + c1a: 0c10 bf 0xc3a // c3a <__memset_fast+0x46> + c1c: a520 st.b r1, (r5, 0x0) + c1e: 2a00 subi r2, 1 + c20: 3a40 cmpnei r2, 0 + c22: 0c0b bf 0xc38 // c38 <__memset_fast+0x44> + c24: 2500 addi r5, 1 + c26: 6d17 mov r4, r5 + c28: 3603 movi r6, 3 + c2a: 6918 and r4, r6 + c2c: 3c40 cmpnei r4, 0 + c2e: 0c06 bf 0xc3a // c3a <__memset_fast+0x46> + c30: a520 st.b r1, (r5, 0x0) + c32: 2a00 subi r2, 1 + c34: 2500 addi r5, 1 + c36: 0402 br 0xc3a // c3a <__memset_fast+0x46> + c38: 1483 pop r4-r6 + c3a: 4168 lsli r3, r1, 8 + c3c: 6c4c or r1, r3 + c3e: 4170 lsli r3, r1, 16 + c40: 6c4c or r1, r3 + c42: 3a2f cmplti r2, 16 + c44: 0809 bt 0xc56 // c56 <__memset_fast+0x62> + c46: b520 st.w r1, (r5, 0x0) + c48: b521 st.w r1, (r5, 0x4) + c4a: b522 st.w r1, (r5, 0x8) + c4c: b523 st.w r1, (r5, 0xc) + c4e: 2a0f subi r2, 16 + c50: 250f addi r5, 16 + c52: 3a2f cmplti r2, 16 + c54: 0ff9 bf 0xc46 // c46 <__memset_fast+0x52> + c56: 3a23 cmplti r2, 4 + c58: 0806 bt 0xc64 // c64 <__memset_fast+0x70> + c5a: 2a03 subi r2, 4 + c5c: b520 st.w r1, (r5, 0x0) + c5e: 2503 addi r5, 4 + c60: 3a23 cmplti r2, 4 + c62: 0ffc bf 0xc5a // c5a <__memset_fast+0x66> + c64: 3a40 cmpnei r2, 0 + c66: 0fe9 bf 0xc38 // c38 <__memset_fast+0x44> + c68: 2a00 subi r2, 1 + c6a: a520 st.b r1, (r5, 0x0) + c6c: 3a40 cmpnei r2, 0 + c6e: 0fe5 bf 0xc38 // c38 <__memset_fast+0x44> + c70: 2a00 subi r2, 1 + c72: a521 st.b r1, (r5, 0x1) + c74: 3a40 cmpnei r2, 0 + c76: 0fe1 bf 0xc38 // c38 <__memset_fast+0x44> + c78: a522 st.b r1, (r5, 0x2) + c7a: 1483 pop r4-r6 + +00000c7c <__memcpy_fast>: + c7c: 14c3 push r4-r6 + c7e: 6d83 mov r6, r0 + c80: 6d07 mov r4, r1 + c82: 6d18 or r4, r6 + c84: 3303 movi r3, 3 + c86: 690c and r4, r3 + c88: 3c40 cmpnei r4, 0 + c8a: 0c0b bf 0xca0 // ca0 <__memcpy_fast+0x24> + c8c: 3a40 cmpnei r2, 0 + c8e: 0c08 bf 0xc9e // c9e <__memcpy_fast+0x22> + c90: 8160 ld.b r3, (r1, 0x0) + c92: 2100 addi r1, 1 + c94: 2a00 subi r2, 1 + c96: a660 st.b r3, (r6, 0x0) + c98: 2600 addi r6, 1 + c9a: 3a40 cmpnei r2, 0 + c9c: 0bfa bt 0xc90 // c90 <__memcpy_fast+0x14> + c9e: 1483 pop r4-r6 + ca0: 3a2f cmplti r2, 16 + ca2: 080e bt 0xcbe // cbe <__memcpy_fast+0x42> + ca4: 91a0 ld.w r5, (r1, 0x0) + ca6: 9161 ld.w r3, (r1, 0x4) + ca8: 9182 ld.w r4, (r1, 0x8) + caa: b6a0 st.w r5, (r6, 0x0) + cac: 91a3 ld.w r5, (r1, 0xc) + cae: b661 st.w r3, (r6, 0x4) + cb0: b682 st.w r4, (r6, 0x8) + cb2: b6a3 st.w r5, (r6, 0xc) + cb4: 2a0f subi r2, 16 + cb6: 210f addi r1, 16 + cb8: 260f addi r6, 16 + cba: 3a2f cmplti r2, 16 + cbc: 0ff4 bf 0xca4 // ca4 <__memcpy_fast+0x28> + cbe: 3a23 cmplti r2, 4 + cc0: 0808 bt 0xcd0 // cd0 <__memcpy_fast+0x54> + cc2: 9160 ld.w r3, (r1, 0x0) + cc4: 2a03 subi r2, 4 + cc6: 2103 addi r1, 4 + cc8: b660 st.w r3, (r6, 0x0) + cca: 2603 addi r6, 4 + ccc: 3a23 cmplti r2, 4 + cce: 0ffa bf 0xcc2 // cc2 <__memcpy_fast+0x46> + cd0: 3a40 cmpnei r2, 0 + cd2: 0fe6 bf 0xc9e // c9e <__memcpy_fast+0x22> + cd4: 8160 ld.b r3, (r1, 0x0) + cd6: 2100 addi r1, 1 + cd8: 2a00 subi r2, 1 + cda: a660 st.b r3, (r6, 0x0) + cdc: 2600 addi r6, 1 + cde: 07f9 br 0xcd0 // cd0 <__memcpy_fast+0x54> + +Disassembly of section .text.__main: + +00000ce0 <__main>: +extern char _bss_start[]; +extern char _ebss[]; + + +void __main( void ) +{ + ce0: 14d0 push r15 + + /* if the start of data (dst) + is not equal to end of text (src) then + copy it, else it's already in the right place + */ + if( _start_data != _end_rodata ) { + ce2: 1009 lrw r0, 0x20000000 // d04 <__main+0x24> + ce4: 1029 lrw r1, 0x60dc // d08 <__main+0x28> + ce6: 6442 cmpne r0, r1 + ce8: 0c05 bf 0xcf2 // cf2 <__main+0x12> +// __memcpy_fast( dst, src, (_end_data - _start_data)); + memcpy( dst, src, (_end_data - _start_data)); + cea: 1049 lrw r2, 0x20000068 // d0c <__main+0x2c> + cec: 6082 subu r2, r0 + cee: e3ffffc7 bsr 0xc7c // c7c <__memcpy_fast> + } + + /* zero the bss + */ + if( _ebss - _bss_start ) { + cf2: 1048 lrw r2, 0x200007bc // d10 <__main+0x30> + cf4: 1008 lrw r0, 0x20000068 // d14 <__main+0x34> + cf6: 640a cmpne r2, r0 + cf8: 0c05 bf 0xd02 // d02 <__main+0x22> +// __memset_fast( _bss_start, 0x00, ( _ebss - _bss_start )); + memset( _bss_start, 0x00, ( _ebss - _bss_start )); + cfa: 6082 subu r2, r0 + cfc: 3100 movi r1, 0 + cfe: e3ffff7b bsr 0xbf4 // bf4 <__memset_fast> + } + + +} + d02: 1490 pop r15 + d04: 20000000 .long 0x20000000 + d08: 000060dc .long 0x000060dc + d0c: 20000068 .long 0x20000068 + d10: 200007bc .long 0x200007bc + d14: 20000068 .long 0x20000068 + +Disassembly of section .text.SYSCON_General_CMD.part.0: + +00000d18 : +/*************************************************************/ +void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X ) +{ + if (NewState != DISABLE) + { + if(ENDIS_X==ENDIS_EMOSC) + d18: 3848 cmpnei r0, 8 + d1a: 080a bt 0xd2e // d2e + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF00FFF)|0x00044000; //enable EMOSC PIN + d1c: 107a lrw r3, 0x2000004c // d84 + d1e: 32ff movi r2, 255 + d20: 9320 ld.w r1, (r3, 0x0) + d22: 9160 ld.w r3, (r1, 0x0) + d24: 424c lsli r2, r2, 12 + d26: 68c9 andn r3, r2 + d28: 3bae bseti r3, 14 + d2a: 3bb2 bseti r3, 18 + d2c: b160 st.w r3, (r1, 0x0) + SYSCON->GCER|=ENDIS_X; //enable SYSCON General Control + d2e: 1077 lrw r3, 0x2000005c // d88 + d30: 9360 ld.w r3, (r3, 0x0) + d32: 9341 ld.w r2, (r3, 0x4) + d34: 6c80 or r2, r0 + d36: b341 st.w r2, (r3, 0x4) + while(!(SYSCON->GCSR&ENDIS_X)); //check Enable? + d38: 9343 ld.w r2, (r3, 0xc) + d3a: 6880 and r2, r0 + d3c: 3a40 cmpnei r2, 0 + d3e: 0ffd bf 0xd38 // d38 + switch(ENDIS_X) + d40: 3842 cmpnei r0, 2 + d42: 0807 bt 0xd50 // d50 + { + case ENDIS_IMOSC: + while (!(SYSCON->CKST & ENDIS_IMOSC)); + d44: 3102 movi r1, 2 + d46: 9344 ld.w r2, (r3, 0x10) + d48: 6884 and r2, r1 + d4a: 3a40 cmpnei r2, 0 + d4c: 0ffd bf 0xd46 // d46 + { + SYSCON->GCDR|=ENDIS_X; //disable SYSCON General Control + while(SYSCON->GCSR&ENDIS_X); //check Disable? + SYSCON->ICR|=ENDIS_X; //Clear ENDIS_X stable bit + } +} + d4e: 783c jmp r15 + switch(ENDIS_X) + d50: 3802 cmphsi r0, 3 + d52: 0809 bt 0xd64 // d64 + d54: 3841 cmpnei r0, 1 + d56: 0bfc bt 0xd4e // d4e + while (!(SYSCON->CKST & ENDIS_ISOSC)); + d58: 3101 movi r1, 1 + d5a: 9344 ld.w r2, (r3, 0x10) + d5c: 6884 and r2, r1 + d5e: 3a40 cmpnei r2, 0 + d60: 0ffd bf 0xd5a // d5a + d62: 07f6 br 0xd4e // d4e + switch(ENDIS_X) + d64: 3848 cmpnei r0, 8 + d66: 0807 bt 0xd74 // d74 + while (!(SYSCON->CKST & ENDIS_EMOSC)); + d68: 3108 movi r1, 8 + d6a: 9344 ld.w r2, (r3, 0x10) + d6c: 6884 and r2, r1 + d6e: 3a40 cmpnei r2, 0 + d70: 0ffd bf 0xd6a // d6a + d72: 07ee br 0xd4e // d4e + switch(ENDIS_X) + d74: 3850 cmpnei r0, 16 + d76: 0bec bt 0xd4e // d4e + while (!(SYSCON->CKST & ENDIS_HFOSC)); + d78: 3110 movi r1, 16 + d7a: 9344 ld.w r2, (r3, 0x10) + d7c: 6884 and r2, r1 + d7e: 3a40 cmpnei r2, 0 + d80: 0ffd bf 0xd7a // d7a + d82: 07e6 br 0xd4e // d4e + d84: 2000004c .long 0x2000004c + d88: 2000005c .long 0x2000005c + +Disassembly of section .text.SYSCON_RST_VALUE: + +00000d8c : + SYSCON->RAMCHK=SYSCON_RAMCHK_RST; + d8c: 106f lrw r3, 0x2000005c // dc8 + d8e: 1050 lrw r2, 0xffff // dcc + d90: 9360 ld.w r3, (r3, 0x0) + d92: b345 st.w r2, (r3, 0x14) + SYSCON->EFLCHK=SYSCON_EFLCHK_RST; + d94: 104f lrw r2, 0xffffff // dd0 + d96: b346 st.w r2, (r3, 0x18) + SYSCON->SCLKCR=SYSCON_SCLKCR_RST; + d98: 104f lrw r2, 0xd22d0000 // dd4 + d9a: b347 st.w r2, (r3, 0x1c) + SYSCON->OSTR=SYSCON_OSTR_RST; + d9c: 104f lrw r2, 0x70ff3bff // dd8 + d9e: b350 st.w r2, (r3, 0x40) + SYSCON->EXIRT=SYSCON_EXIRT_RST; + da0: 3180 movi r1, 128 + SYSCON->LVDCR=SYSCON_LVDCR_RST; + da2: 320a movi r2, 10 + da4: b353 st.w r2, (r3, 0x4c) + SYSCON->EXIRT=SYSCON_EXIRT_RST; + da6: 604c addu r1, r3 + da8: 3200 movi r2, 0 + SYSCON->IWDCR=SYSCON_IWDCR_RST; + daa: 100d lrw r0, 0x70c // ddc + SYSCON->EXIRT=SYSCON_EXIRT_RST; + dac: b145 st.w r2, (r1, 0x14) + SYSCON->UREG0=SYSCON_UREG0_RST; + dae: 23ff addi r3, 256 + SYSCON->EXIFT=SYSCON_EXIFT_RST; + db0: b146 st.w r2, (r1, 0x18) + SYSCON->IWDCR=SYSCON_IWDCR_RST; + db2: b10d st.w r0, (r1, 0x34) + SYSCON->IWDCNT=SYSCON_IWDCNT_RST; + db4: 100b lrw r0, 0x3fe // de0 + db6: b10e st.w r0, (r1, 0x38) + SYSCON->EVTRG=SYSCON_EVTRG_RST; + db8: b15d st.w r2, (r1, 0x74) + SYSCON->EVPS=SYSCON_EVPS_RST; + dba: b15e st.w r2, (r1, 0x78) + SYSCON->EVSWF=SYSCON_EVSWF_RST; + dbc: b15f st.w r2, (r1, 0x7c) + SYSCON->UREG0=SYSCON_UREG0_RST; + dbe: b340 st.w r2, (r3, 0x0) + SYSCON->UREG1=SYSCON_UREG1_RST; + dc0: b341 st.w r2, (r3, 0x4) + SYSCON->UREG2=SYSCON_UREG2_RST; + dc2: b342 st.w r2, (r3, 0x8) + SYSCON->UREG3=SYSCON_UREG3_RST; + dc4: b343 st.w r2, (r3, 0xc) +} + dc6: 783c jmp r15 + dc8: 2000005c .long 0x2000005c + dcc: 0000ffff .long 0x0000ffff + dd0: 00ffffff .long 0x00ffffff + dd4: d22d0000 .long 0xd22d0000 + dd8: 70ff3bff .long 0x70ff3bff + ddc: 0000070c .long 0x0000070c + de0: 000003fe .long 0x000003fe + +Disassembly of section .text.SYSCON_General_CMD: + +00000de4 : +{ + de4: 14d0 push r15 + if (NewState != DISABLE) + de6: 3840 cmpnei r0, 0 + de8: 0c05 bf 0xdf2 // df2 + dea: 6c07 mov r0, r1 + dec: e3ffff96 bsr 0xd18 // d18 +} + df0: 1490 pop r15 + SYSCON->GCDR|=ENDIS_X; //disable SYSCON General Control + df2: 1068 lrw r3, 0x2000005c // e10 + df4: 9360 ld.w r3, (r3, 0x0) + df6: 9342 ld.w r2, (r3, 0x8) + df8: 6c84 or r2, r1 + dfa: b342 st.w r2, (r3, 0x8) + while(SYSCON->GCSR&ENDIS_X); //check Disable? + dfc: 9343 ld.w r2, (r3, 0xc) + dfe: 6884 and r2, r1 + e00: 3a40 cmpnei r2, 0 + e02: 0bfd bt 0xdfc // dfc + SYSCON->ICR|=ENDIS_X; //Clear ENDIS_X stable bit + e04: 237f addi r3, 128 + e06: 9301 ld.w r0, (r3, 0x4) + e08: 6c40 or r1, r0 + e0a: b321 st.w r1, (r3, 0x4) +} + e0c: 07f2 br 0xdf0 // df0 + e0e: 0000 bkpt + e10: 2000005c .long 0x2000005c + +Disassembly of section .text.SystemCLK_HCLKDIV_PCLKDIV_Config: + +00000e14 : +//SystemClk_data_x:EMOSC_24M,EMOSC_16M,EMOSC_12M,EMOSC_8M,EMOSC_4M,EMOSC_36K, +//ISOSC,IMOSC,HFOSC_48M,HFOSC_24M,HFOSC_12M,HFOSC_6M +//ReturnValue:NONE +/*************************************************************/ +void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x ) +{ + e14: 14c2 push r4-r5 + if(SystemClk_data_x==HFOSC_48M) + e16: 3b48 cmpnei r3, 8 + e18: 0828 bt 0xe68 // e68 + { + IFC->CEDR=0X01; //CLKEN + e1a: 109d lrw r4, 0x20000060 // e8c + e1c: 3501 movi r5, 1 + e1e: 9480 ld.w r4, (r4, 0x0) + e20: b4a1 st.w r5, (r4, 0x4) + IFC->MR=0X04|(0X00<<16); //High speed mode + e22: 3504 movi r5, 4 + e24: b4a5 st.w r5, (r4, 0x14) + if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==HFOSC_24M)) + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X02|(0X00<<16); //Medium speed mode + } + if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==EMOSC_16M)) + e26: 5b83 subi r4, r3, 1 + e28: 3c01 cmphsi r4, 2 + e2a: 0c2b bf 0xe80 // e80 + { + IFC->CEDR=0X01; //CLKEN + IFC->MR=0X01|(0X00<<16); //Low speed mode + } + if((SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K) + ||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_6M)) + e2c: 5b8b subi r4, r3, 3 + if((SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K) + e2e: 3c04 cmphsi r4, 5 + e30: 0c03 bf 0xe36 // e36 + ||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_6M)) + e32: 3b4b cmpnei r3, 11 + e34: 0807 bt 0xe42 // e42 + { + IFC->CEDR=0X01; //CLKEN + e36: 1076 lrw r3, 0x20000060 // e8c + e38: 3401 movi r4, 1 + e3a: 9360 ld.w r3, (r3, 0x0) + e3c: b381 st.w r4, (r3, 0x4) + IFC->MR=0X00|(0X00<<16); //Low speed mode + e3e: 3400 movi r4, 0 + e40: b385 st.w r4, (r3, 0x14) + } + SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X; + e42: 1094 lrw r4, 0xd22d0000 // e90 + e44: 6c10 or r0, r4 + e46: 1074 lrw r3, 0x2000005c // e94 + e48: 6c40 or r1, r0 + e4a: 9360 ld.w r3, (r3, 0x0) + while (!(SYSCON->CKST & (1<<8))); // waiting for sysclk stable + e4c: 3080 movi r0, 128 + SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X; + e4e: b327 st.w r1, (r3, 0x1c) + while (!(SYSCON->CKST & (1<<8))); // waiting for sysclk stable + e50: 4001 lsli r0, r0, 1 + e52: 9324 ld.w r1, (r3, 0x10) + e54: 6840 and r1, r0 + e56: 3940 cmpnei r1, 0 + e58: 0ffd bf 0xe52 // e52 + SYSCON->PCLKCR=PCLK_KEY|PCLK_DIV_X; //PCLK DIV 1 2 4 6 8 16 + e5a: 1030 lrw r1, 0xc33c0000 // e98 + e5c: 6c48 or r1, r2 + e5e: b328 st.w r1, (r3, 0x20) + while(SYSCON->PCLKCR!=PCLK_DIV_X); //Wait PCLK DIV + e60: 9328 ld.w r1, (r3, 0x20) + e62: 644a cmpne r2, r1 + e64: 0bfe bt 0xe60 // e60 +} + e66: 1482 pop r4-r5 + if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==HFOSC_24M)) + e68: 3b40 cmpnei r3, 0 + e6a: 0c03 bf 0xe70 // e70 + e6c: 3b49 cmpnei r3, 9 + e6e: 0807 bt 0xe7c // e7c + IFC->CEDR=0X01; //CLKEN + e70: 1087 lrw r4, 0x20000060 // e8c + e72: 3501 movi r5, 1 + e74: 9480 ld.w r4, (r4, 0x0) + e76: b4a1 st.w r5, (r4, 0x4) + IFC->MR=0X02|(0X00<<16); //Medium speed mode + e78: 3502 movi r5, 2 + e7a: b4a5 st.w r5, (r4, 0x14) + if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==EMOSC_16M)) + e7c: 3b4a cmpnei r3, 10 + e7e: 0bd4 bt 0xe26 // e26 + IFC->CEDR=0X01; //CLKEN + e80: 1083 lrw r4, 0x20000060 // e8c + e82: 3501 movi r5, 1 + e84: 9480 ld.w r4, (r4, 0x0) + e86: b4a1 st.w r5, (r4, 0x4) + IFC->MR=0X01|(0X00<<16); //Low speed mode + e88: b4a5 st.w r5, (r4, 0x14) + e8a: 07d1 br 0xe2c // e2c + e8c: 20000060 .long 0x20000060 + e90: d22d0000 .long 0xd22d0000 + e94: 2000005c .long 0x2000005c + e98: c33c0000 .long 0xc33c0000 + +Disassembly of section .text.SYSCON_HFOSC_SELECTE: + +00000e9c : +//EntryParameter:HFOSC_SELECTE_X +//HFOSC_SELECTE_X:HFOSC_SELECTE_48M,HFOSC_SELECTE_24M;HFOSC_SELECTE_12M;HFOSC_SELECTE_6M +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X) +{ + e9c: 14d1 push r4, r15 + e9e: 6d03 mov r4, r0 + SYSCON_General_CMD(DISABLE,ENDIS_HFOSC); //disable HFOSC + ea0: 3110 movi r1, 16 + ea2: 3000 movi r0, 0 + ea4: e3ffffa0 bsr 0xde4 // de4 + SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFCF)|HFOSC_SELECTE_X; + ea8: 1066 lrw r3, 0x2000005c // ec0 + eaa: 9360 ld.w r3, (r3, 0x0) + eac: 9319 ld.w r0, (r3, 0x64) + eae: 3884 bclri r0, 4 + eb0: 3885 bclri r0, 5 + eb2: 6c10 or r0, r4 + eb4: b319 st.w r0, (r3, 0x64) + eb6: 3010 movi r0, 16 + eb8: e3ffff30 bsr 0xd18 // d18 + SYSCON_General_CMD(ENABLE,ENDIS_HFOSC); //enable HFOSC +} + ebc: 1491 pop r4, r15 + ebe: 0000 bkpt + ec0: 2000005c .long 0x2000005c + +Disassembly of section .text.SYSCON_WDT_CMD: + +00000ec4 : +//EntryParameter:,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_WDT_CMD(FunctionalStatus NewState) +{ + ec4: 106c lrw r3, 0x2000005c // ef4 + if(NewState != DISABLE) + ec6: 3840 cmpnei r0, 0 + { + SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT; + ec8: 9360 ld.w r3, (r3, 0x0) + eca: 237f addi r3, 128 + if(NewState != DISABLE) + ecc: 0c0a bf 0xee0 // ee0 + SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT; + ece: 104b lrw r2, 0x78870000 // ef8 + while(!(SYSCON->IWDCR&Check_IWDT_BUSY)); + ed0: 3180 movi r1, 128 + SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT; + ed2: b34f st.w r2, (r3, 0x3c) + while(!(SYSCON->IWDCR&Check_IWDT_BUSY)); + ed4: 4125 lsli r1, r1, 5 + ed6: 934d ld.w r2, (r3, 0x34) + ed8: 6884 and r2, r1 + eda: 3a40 cmpnei r2, 0 + edc: 0ffd bf 0xed6 // ed6 + else + { + SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT; + while(SYSCON->IWDCR&Check_IWDT_BUSY); + } +} + ede: 783c jmp r15 + SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT; + ee0: 1047 lrw r2, 0x788755aa // efc + while(SYSCON->IWDCR&Check_IWDT_BUSY); + ee2: 3180 movi r1, 128 + SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT; + ee4: b34f st.w r2, (r3, 0x3c) + while(SYSCON->IWDCR&Check_IWDT_BUSY); + ee6: 4125 lsli r1, r1, 5 + ee8: 934d ld.w r2, (r3, 0x34) + eea: 6884 and r2, r1 + eec: 3a40 cmpnei r2, 0 + eee: 0bfd bt 0xee8 // ee8 + ef0: 07f7 br 0xede // ede + ef2: 0000 bkpt + ef4: 2000005c .long 0x2000005c + ef8: 78870000 .long 0x78870000 + efc: 788755aa .long 0x788755aa + +Disassembly of section .text.SYSCON_IWDCNT_Reload: + +00000f00 : +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_IWDCNT_Reload(void) +{ + SYSCON->IWDCNT=CLR_IWDT; + f00: 1064 lrw r3, 0x2000005c // f10 + f02: 32b4 movi r2, 180 + f04: 9360 ld.w r3, (r3, 0x0) + f06: 237f addi r3, 128 + f08: 4257 lsli r2, r2, 23 + f0a: b34e st.w r2, (r3, 0x38) +} + f0c: 783c jmp r15 + f0e: 0000 bkpt + f10: 2000005c .long 0x2000005c + +Disassembly of section .text.SYSCON_IWDCNT_Config: + +00000f14 : +//IWDT_INTW_DIV_X:IWDT_INTW_DIV_1/2/3/4/4/5/6 +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X ) +{ + SYSCON->IWDCR=IWDT_KEY|IWDT_TIME_X|IWDT_INTW_DIV_X; + f14: 1044 lrw r2, 0x87780000 // f24 + f16: 1065 lrw r3, 0x2000005c // f28 + f18: 6c48 or r1, r2 + f1a: 9360 ld.w r3, (r3, 0x0) + f1c: 6c04 or r0, r1 + f1e: 237f addi r3, 128 + f20: b30d st.w r0, (r3, 0x34) +} + f22: 783c jmp r15 + f24: 87780000 .long 0x87780000 + f28: 2000005c .long 0x2000005c + +Disassembly of section .text.SYSCON_LVD_Config: + +00000f2c : +//X_LVD_INT:ENABLE_LVD_INT,DISABLE_LVD_INT +//INTDET_POL_X:INTDET_POL_fall,INTDET_POL_X_rise,INTDET_POL_X_riseORfall +//ReturnValue: NONE +/*************************************************************/ +void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X) +{ + f2c: 14c3 push r4-r6 + f2e: 9883 ld.w r4, (r14, 0xc) + //SYSCON->LVDCR=LVD_KEY; + SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT|INTDET_POL_X; + f30: 10c5 lrw r6, 0xb44b0000 // f44 + f32: 6d18 or r4, r6 + f34: 6cd0 or r3, r4 + f36: 6c8c or r2, r3 + f38: 6c48 or r1, r2 + f3a: 10a4 lrw r5, 0x2000005c // f48 + f3c: 6c04 or r0, r1 + f3e: 95a0 ld.w r5, (r5, 0x0) + f40: b513 st.w r0, (r5, 0x4c) +} + f42: 1483 pop r4-r6 + f44: b44b0000 .long 0xb44b0000 + f48: 2000005c .long 0x2000005c + +Disassembly of section .text.LVD_Int_Enable: + +00000f4c : +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void LVD_Int_Enable(void) +{ + SYSCON->ICR = LVD_INT_ST; //clear LVD INT status + f4c: 1066 lrw r3, 0x2000005c // f64 + f4e: 3180 movi r1, 128 + f50: 9360 ld.w r3, (r3, 0x0) + f52: 3280 movi r2, 128 + f54: 604c addu r1, r3 + f56: 4244 lsli r2, r2, 4 + f58: b141 st.w r2, (r1, 0x4) + SYSCON->IMER |= LVD_INT_ST; + f5a: 935d ld.w r2, (r3, 0x74) + f5c: 3aab bseti r2, 11 + f5e: b35d st.w r2, (r3, 0x74) +} + f60: 783c jmp r15 + f62: 0000 bkpt + f64: 2000005c .long 0x2000005c + +Disassembly of section .text.IWDT_Int_Enable: + +00000f68 : +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void IWDT_Int_Enable(void) +{ + SYSCON->ICR = IWDT_INT_ST; //clear LVD INT status + f68: 1066 lrw r3, 0x2000005c // f80 + f6a: 3180 movi r1, 128 + f6c: 9360 ld.w r3, (r3, 0x0) + f6e: 3280 movi r2, 128 + f70: 604c addu r1, r3 + f72: 4241 lsli r2, r2, 1 + f74: b141 st.w r2, (r1, 0x4) + SYSCON->IMER |= IWDT_INT_ST; + f76: 935d ld.w r2, (r3, 0x74) + f78: 3aa8 bseti r2, 8 + f7a: b35d st.w r2, (r3, 0x74) +} + f7c: 783c jmp r15 + f7e: 0000 bkpt + f80: 2000005c .long 0x2000005c + +Disassembly of section .text.EXTI_trigger_CMD: + +00000f84 : +//EXI_tringer_mode:_EXIRT,_EXIFT +//ReturnValue: LVD detection flag +/*************************************************************/ +void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode) +{ + switch(EXI_tringer_mode) + f84: 3a40 cmpnei r2, 0 + f86: 0c04 bf 0xf8e // f8e + f88: 3a41 cmpnei r2, 1 + f8a: 0c0e bf 0xfa6 // fa6 + { + SYSCON->EXIFT &=~EXIPIN; + } + break; + } +} + f8c: 783c jmp r15 + f8e: 106d lrw r3, 0x2000005c // fc0 + if(NewState != DISABLE) + f90: 3840 cmpnei r0, 0 + SYSCON->EXIRT |=EXIPIN; + f92: 9360 ld.w r3, (r3, 0x0) + f94: 237f addi r3, 128 + f96: 9345 ld.w r2, (r3, 0x14) + if(NewState != DISABLE) + f98: 0c04 bf 0xfa0 // fa0 + SYSCON->EXIRT |=EXIPIN; + f9a: 6c48 or r1, r2 + f9c: b325 st.w r1, (r3, 0x14) + f9e: 07f7 br 0xf8c // f8c + SYSCON->EXIRT &=~EXIPIN; + fa0: 6885 andn r2, r1 + fa2: b345 st.w r2, (r3, 0x14) + fa4: 07f4 br 0xf8c // f8c + fa6: 1067 lrw r3, 0x2000005c // fc0 + if(NewState != DISABLE) + fa8: 3840 cmpnei r0, 0 + SYSCON->EXIFT |=EXIPIN; + faa: 9360 ld.w r3, (r3, 0x0) + fac: 237f addi r3, 128 + fae: 9346 ld.w r2, (r3, 0x18) + if(NewState != DISABLE) + fb0: 0c04 bf 0xfb8 // fb8 + SYSCON->EXIFT |=EXIPIN; + fb2: 6c48 or r1, r2 + fb4: b326 st.w r1, (r3, 0x18) + fb6: 07eb br 0xf8c // f8c + SYSCON->EXIFT &=~EXIPIN; + fb8: 6885 andn r2, r1 + fba: b346 st.w r2, (r3, 0x18) +} + fbc: 07e8 br 0xf8c // f8c + fbe: 0000 bkpt + fc0: 2000005c .long 0x2000005c + +Disassembly of section .text.EXTI_interrupt_CMD: + +00000fc4 : +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN) +{ + SYSCON->EXICR = 0X3FFF; //Claer EXI INT status + fc4: 106b lrw r3, 0x2000005c // ff0 + fc6: 104c lrw r2, 0x3fff // ff4 + fc8: 9360 ld.w r3, (r3, 0x0) + fca: 237f addi r3, 128 + if(NewState != DISABLE) + fcc: 3840 cmpnei r0, 0 + SYSCON->EXICR = 0X3FFF; //Claer EXI INT status + fce: b34b st.w r2, (r3, 0x2c) + if(NewState != DISABLE) + fd0: 0c0c bf 0xfe8 // fe8 + { + SYSCON->EXIER|=EXIPIN; //EXI4 interrupt enable + fd2: 9347 ld.w r2, (r3, 0x1c) + fd4: 6c84 or r2, r1 + fd6: b347 st.w r2, (r3, 0x1c) + while(!(SYSCON->EXIMR&EXIPIN)); //Check EXI is enabled or not + fd8: 9349 ld.w r2, (r3, 0x24) + fda: 6884 and r2, r1 + fdc: 3a40 cmpnei r2, 0 + fde: 0ffd bf 0xfd8 // fd8 + SYSCON->EXICR |=EXIPIN; // Clear EXI status bit + fe0: 934b ld.w r2, (r3, 0x2c) + fe2: 6c48 or r1, r2 + fe4: b32b st.w r1, (r3, 0x2c) + } + else + { + SYSCON->EXIDR|=EXIPIN; + } +} + fe6: 783c jmp r15 + SYSCON->EXIDR|=EXIPIN; + fe8: 9348 ld.w r2, (r3, 0x20) + fea: 6c48 or r1, r2 + fec: b328 st.w r1, (r3, 0x20) +} + fee: 07fc br 0xfe6 // fe6 + ff0: 2000005c .long 0x2000005c + ff4: 00003fff .long 0x00003fff + +Disassembly of section .text.GPIO_EXTI_interrupt: + +00000ff8 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE) +{ + GPIOX->IECR=GPIO_IECR_VALUE; + ff8: b02b st.w r1, (r0, 0x2c) +} + ffa: 783c jmp r15 + +Disassembly of section .text.EXI1_Int_Enable: + +00000ffc : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1_Int_Enable(void) +{ + INTC_ISER_WRITE(EXI1_INT); + ffc: 3380 movi r3, 128 + ffe: 4361 lsli r3, r3, 1 + 1000: 1042 lrw r2, 0xe000e100 // 1008 + 1002: b260 st.w r3, (r2, 0x0) +} + 1004: 783c jmp r15 + 1006: 0000 bkpt + 1008: e000e100 .long 0xe000e100 + +Disassembly of section .text.SYSCON_Int_Enable: + +0000100c : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_Int_Enable(void) +{ + INTC_ISER_WRITE(SYSCON_INT); + 100c: 3202 movi r2, 2 + 100e: 1062 lrw r3, 0xe000e100 // 1014 + 1010: b340 st.w r2, (r3, 0x0) +} + 1012: 783c jmp r15 + 1014: e000e100 .long 0xe000e100 + +Disassembly of section .text.SYSCON_INT_Priority: + +00001018 : +//80:Priority 2 +//C0:Priority 3 lowest +/*************************************************************/ +void SYSCON_INT_Priority(void) +{ + INTC_IPR0_WRITE(0XC0C0C0C0); //IQR0-3 low bit-->high bit + 1018: 1066 lrw r3, 0xe000e400 // 1030 + 101a: 1047 lrw r2, 0xc0c0c0c0 // 1034 + INTC_IPR1_WRITE(0XC0C0C0C0); //IQR4-7 + INTC_IPR2_WRITE(0XC0C0C0C0); //IQR8-11 + INTC_IPR3_WRITE(0XC0C0C0C0); //IQR12-15 + INTC_IPR4_WRITE(0XC0C0C0C0); //IQR16-19 + INTC_IPR5_WRITE(0XC0C0C0C0); //IQR20-23 + INTC_IPR6_WRITE(0XC0C000C0); //IQR24-27 + 101c: 1027 lrw r1, 0xc0c000c0 // 1038 + INTC_IPR0_WRITE(0XC0C0C0C0); //IQR0-3 low bit-->high bit + 101e: b340 st.w r2, (r3, 0x0) + INTC_IPR1_WRITE(0XC0C0C0C0); //IQR4-7 + 1020: b341 st.w r2, (r3, 0x4) + INTC_IPR2_WRITE(0XC0C0C0C0); //IQR8-11 + 1022: b342 st.w r2, (r3, 0x8) + INTC_IPR3_WRITE(0XC0C0C0C0); //IQR12-15 + 1024: b343 st.w r2, (r3, 0xc) + INTC_IPR4_WRITE(0XC0C0C0C0); //IQR16-19 + 1026: b344 st.w r2, (r3, 0x10) + INTC_IPR5_WRITE(0XC0C0C0C0); //IQR20-23 + 1028: b345 st.w r2, (r3, 0x14) + INTC_IPR6_WRITE(0XC0C000C0); //IQR24-27 + 102a: b326 st.w r1, (r3, 0x18) + INTC_IPR7_WRITE(0XC0C0C0C0); //IQR28-31 + 102c: b347 st.w r2, (r3, 0x1c) +} + 102e: 783c jmp r15 + 1030: e000e400 .long 0xe000e400 + 1034: c0c0c0c0 .long 0xc0c0c0c0 + 1038: c0c000c0 .long 0xc0c000c0 + +Disassembly of section .text.Set_INT_Priority: + +0000103c : +//int_name:CORET_IRQ~BT1_IRQ +//int_level:0~3 0=highest 3=lowest +//ReturnValue:None +/*************************************************************/ +void Set_INT_Priority(U8_T int_name,U8_T int_level) +{ + 103c: 14c1 push r4 + 103e: 4862 lsri r3, r0, 2 + 1040: 4342 lsli r2, r3, 2 + 1042: 106a lrw r3, 0x20000064 // 1068 + U8_T i_temp,j_temp; + U32_T k_temp; + i_temp=(int_name%4)*8; + 1044: 3403 movi r4, 3 + 1046: 9360 ld.w r3, (r3, 0x0) + 1048: 60c8 addu r3, r2 + j_temp=int_name/4; + k_temp=CK801 -> IPR[j_temp]&(~(0xff< IPR[j_temp]&(~(0xff< IPR[j_temp]=k_temp|((int_level*0x40)<<(i_temp)); + 105a: 4126 lsli r1, r1, 6 + k_temp=CK801 -> IPR[j_temp]&(~(0xff< IPR[j_temp]=k_temp|((int_level*0x40)<<(i_temp)); + 105e: 7040 lsl r1, r0 + 1060: 6c48 or r1, r2 + 1062: b320 st.w r1, (r3, 0x0) +} + 1064: 1481 pop r4 + 1066: 0000 bkpt + 1068: 20000064 .long 0x20000064 + +Disassembly of section .text.GPIO_Init: + +0000106c : +//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15) +//Dir:0:output 1:input +//ReturnValue:NONE +/*************************************************************/ +void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir) +{ + 106c: 14d1 push r4, r15 + uint32_t data_temp; + uint8_t GPIO_Pin; + if(PinNum<8) + 106e: 3907 cmphsi r1, 8 +{ + 1070: 6d03 mov r4, r0 + if(PinNum<8) + 1072: 0830 bt 0x10d2 // 10d2 + { + switch (PinNum) + 1074: 5903 subi r0, r1, 1 + 1076: 3806 cmphsi r0, 7 + 1078: 0827 bt 0x10c6 // 10c6 + 107a: e3fff89d bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 107e: 1004 .short 0x1004 + 1080: 1d1a1613 .long 0x1d1a1613 + 1084: 0021 .short 0x0021 + { + case 0:data_temp=0xfffffff0;GPIO_Pin=0;break; + case 1:data_temp=0xffffff0f;GPIO_Pin=4;break; + 1086: 3300 movi r3, 0 + 1088: 3104 movi r1, 4 + 108a: 2bf0 subi r3, 241 + case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break; + case 5:data_temp=0xff0fffff;GPIO_Pin=20;break; + case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break; + case 7:data_temp=0x0fffffff;GPIO_Pin=28;break; + } + if (Dir) + 108c: 3a40 cmpnei r2, 0 + { + (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1< + (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<CONLR = ((GPIOx)->CONLR & data_temp) | 2<CONHR = ((GPIOx)->CONHR & data_temp) | 2< + 10a2: 07f5 br 0x108c // 108c + case 3:data_temp=0xffff0fff;GPIO_Pin=12;break; + 10a4: 310c movi r1, 12 + 10a6: 1166 lrw r3, 0xffff0fff // 113c + 10a8: 07f2 br 0x108c // 108c + case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break; + 10aa: 3110 movi r1, 16 + 10ac: 1165 lrw r3, 0xfff10000 // 1140 + case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break; + 10ae: 2b00 subi r3, 1 + 10b0: 07ee br 0x108c // 108c + case 5:data_temp=0xff0fffff;GPIO_Pin=20;break; + 10b2: 3114 movi r1, 20 + 10b4: 1164 lrw r3, 0xff100000 // 1144 + 10b6: 07fc br 0x10ae // 10ae + case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break; + 10b8: 33f1 movi r3, 241 + 10ba: 3118 movi r1, 24 + 10bc: 4378 lsli r3, r3, 24 + 10be: 07f8 br 0x10ae // 10ae + case 7:data_temp=0x0fffffff;GPIO_Pin=28;break; + 10c0: 311c movi r1, 28 + 10c2: 1162 lrw r3, 0xfffffff // 1148 + 10c4: 07e4 br 0x108c // 108c + case 0:data_temp=0xfffffff0;GPIO_Pin=0;break; + 10c6: 3300 movi r3, 0 + 10c8: 3100 movi r1, 0 + 10ca: 2b0f subi r3, 16 + 10cc: 07e0 br 0x108c // 108c + (GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2< + else if (PinNum<16) + 10d2: 390f cmphsi r1, 16 + 10d4: 0be4 bt 0x109c // 109c + switch (PinNum) + 10d6: 2908 subi r1, 9 + 10d8: 3906 cmphsi r1, 7 + 10da: 6c07 mov r0, r1 + 10dc: 0827 bt 0x112a // 112a + 10de: e3fff86b bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 10e2: 1004 .short 0x1004 + 10e4: 1d1a1613 .long 0x1d1a1613 + 10e8: 0021 .short 0x0021 + case 9:data_temp=0xffffff0f;GPIO_Pin=4;break; + 10ea: 3300 movi r3, 0 + 10ec: 3104 movi r1, 4 + 10ee: 2bf0 subi r3, 241 + if (Dir) + 10f0: 3a40 cmpnei r2, 0 + (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1< + (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<CONHR = ((GPIOx)->CONHR & data_temp) | 2< + case 10:data_temp=0xfffff0ff;GPIO_Pin=8;break; + 1102: 3108 movi r1, 8 + 1104: 106d lrw r3, 0xfffff0ff // 1138 + 1106: 07f5 br 0x10f0 // 10f0 + case 11:data_temp=0xffff0fff;GPIO_Pin=12;break; + 1108: 310c movi r1, 12 + 110a: 106d lrw r3, 0xffff0fff // 113c + 110c: 07f2 br 0x10f0 // 10f0 + case 12:data_temp=0xfff0ffff;GPIO_Pin=16;break; + 110e: 3110 movi r1, 16 + 1110: 106c lrw r3, 0xfff10000 // 1140 + case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break; + 1112: 2b00 subi r3, 1 + 1114: 07ee br 0x10f0 // 10f0 + case 13:data_temp=0xff0fffff;GPIO_Pin=20;break; + 1116: 3114 movi r1, 20 + 1118: 106b lrw r3, 0xff100000 // 1144 + 111a: 07fc br 0x1112 // 1112 + case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break; + 111c: 33f1 movi r3, 241 + 111e: 3118 movi r1, 24 + 1120: 4378 lsli r3, r3, 24 + 1122: 07f8 br 0x1112 // 1112 + case 15:data_temp=0x0fffffff;GPIO_Pin=28;break; + 1124: 311c movi r1, 28 + 1126: 1069 lrw r3, 0xfffffff // 1148 + 1128: 07e4 br 0x10f0 // 10f0 + case 8:data_temp=0xfffffff0;GPIO_Pin=0;break; + 112a: 3300 movi r3, 0 + 112c: 3100 movi r1, 0 + 112e: 2b0f subi r3, 16 + 1130: 07e0 br 0x10f0 // 10f0 + (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2< + 1136: 0000 bkpt + 1138: fffff0ff .long 0xfffff0ff + 113c: ffff0fff .long 0xffff0fff + 1140: fff10000 .long 0xfff10000 + 1144: ff100000 .long 0xff100000 + 1148: 0fffffff .long 0x0fffffff + +Disassembly of section .text.GPIO_DriveStrength_EN: + +0000114c : +//bit:0~15 +//ReturnValue:VALUE +/*************************************************************/ +void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2)); + 114c: 4121 lsli r1, r1, 1 + 114e: 3301 movi r3, 1 + 1150: 9049 ld.w r2, (r0, 0x24) + 1152: 70c4 lsl r3, r1 + 1154: 6cc8 or r3, r2 + 1156: b069 st.w r3, (r0, 0x24) +} + 1158: 783c jmp r15 + +Disassembly of section .text.GPIO_IntGroup_Set: + +0000115c : +//EXI16~EXI17:GPIOA0.0~GPIOA0.7 +//EXI18~EXI19:GPIOB0.0~GPIOB0.3 +//ReturnValue:NONE +/*************************************************************/ +void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef Selete_EXI_x) +{ + 115c: 14c1 push r4 + 115e: 1422 subi r14, r14, 8 + volatile unsigned int R_data_temp; + volatile unsigned char R_GPIO_Pin; + if(Selete_EXI_x<16) + 1160: 3a0f cmphsi r2, 16 + 1162: 084f bt 0x1200 // 1200 + { + if((Selete_EXI_x==0)||(Selete_EXI_x==8)) + 1164: 6ccb mov r3, r2 + 1166: 3b83 bclri r3, 3 + 1168: 3b40 cmpnei r3, 0 + 116a: 0813 bt 0x1190 // 1190 + { + R_data_temp=0xfffffff0; + 116c: 2b0f subi r3, 16 + 116e: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=0; + 1170: 3300 movi r3, 0 + else if((Selete_EXI_x==7)||(Selete_EXI_x==15)) + { + R_data_temp=0x0fffffff; + R_GPIO_Pin=28; + } + if(Selete_EXI_x<8) + 1172: 3a07 cmphsi r2, 8 + R_GPIO_Pin=28; + 1174: dc6e0003 st.b r3, (r14, 0x3) + 1178: 1176 lrw r3, 0x20000044 // 1250 + if(Selete_EXI_x<8) + 117a: 0c38 bf 0x11ea // 11ea + { + GPIOGRP->IGRPL =(GPIOGRP->IGRPL & R_data_temp) | (IO_MODE<=8)) + { + GPIOGRP->IGRPH =(GPIOGRP->IGRPH & R_data_temp) | (IO_MODE< + else if((Selete_EXI_x==1)||(Selete_EXI_x==9)) + 1190: 3b41 cmpnei r3, 1 + 1192: 0806 bt 0x119e // 119e + R_data_temp=0xffffff0f; + 1194: 3300 movi r3, 0 + 1196: 2bf0 subi r3, 241 + 1198: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=4; + 119a: 3304 movi r3, 4 + 119c: 07eb br 0x1172 // 1172 + else if((Selete_EXI_x==2)||(Selete_EXI_x==10)) + 119e: 3b42 cmpnei r3, 2 + 11a0: 0805 bt 0x11aa // 11aa + R_data_temp=0xfffff0ff; + 11a2: 116d lrw r3, 0xfffff0ff // 1254 + 11a4: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=8; + 11a6: 3308 movi r3, 8 + 11a8: 07e5 br 0x1172 // 1172 + else if((Selete_EXI_x==3)||(Selete_EXI_x==11)) + 11aa: 3b43 cmpnei r3, 3 + 11ac: 0805 bt 0x11b6 // 11b6 + R_data_temp=0xffff0fff; + 11ae: 116b lrw r3, 0xffff0fff // 1258 + 11b0: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=12; + 11b2: 330c movi r3, 12 + 11b4: 07df br 0x1172 // 1172 + else if((Selete_EXI_x==4)||(Selete_EXI_x==12)) + 11b6: 3b44 cmpnei r3, 4 + 11b8: 0806 bt 0x11c4 // 11c4 + R_data_temp=0xfff0ffff; + 11ba: 1169 lrw r3, 0xfff10000 // 125c + 11bc: 2b00 subi r3, 1 + 11be: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=16; + 11c0: 3310 movi r3, 16 + 11c2: 07d8 br 0x1172 // 1172 + else if((Selete_EXI_x==5)||(Selete_EXI_x==13)) + 11c4: 3b45 cmpnei r3, 5 + 11c6: 0806 bt 0x11d2 // 11d2 + R_data_temp=0xff0fffff; + 11c8: 1166 lrw r3, 0xff100000 // 1260 + 11ca: 2b00 subi r3, 1 + 11cc: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=20; + 11ce: 3314 movi r3, 20 + 11d0: 07d1 br 0x1172 // 1172 + else if((Selete_EXI_x==6)||(Selete_EXI_x==14)) + 11d2: 3b46 cmpnei r3, 6 + 11d4: 0807 bt 0x11e2 // 11e2 + R_data_temp=0xf0ffffff; + 11d6: 33f1 movi r3, 241 + 11d8: 4378 lsli r3, r3, 24 + 11da: 2b00 subi r3, 1 + 11dc: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=24; + 11de: 3318 movi r3, 24 + 11e0: 07c9 br 0x1172 // 1172 + R_data_temp=0x0fffffff; + 11e2: 1161 lrw r3, 0xfffffff // 1264 + 11e4: b861 st.w r3, (r14, 0x4) + R_GPIO_Pin=28; + 11e6: 331c movi r3, 28 + 11e8: 07c5 br 0x1172 // 1172 + GPIOGRP->IGRPL =(GPIOGRP->IGRPL & R_data_temp) | (IO_MODE<IGREX=(GPIOGRP->IGREX)|(PinNum<<12); + } + } + } +} + 11fc: 1402 addi r14, r14, 8 + 11fe: 1481 pop r4 + else if(Selete_EXI_x<20) + 1200: 3a13 cmphsi r2, 20 + 1202: 0bfd bt 0x11fc // 11fc + if((IO_MODE==0)&&((Selete_EXI_x==16)||((Selete_EXI_x==17)))) //PA0.0~PA0.7 + 1204: 3840 cmpnei r0, 0 + 1206: 0814 bt 0x122e // 122e + 1208: 3300 movi r3, 0 + 120a: 2b0f subi r3, 16 + 120c: 60c8 addu r3, r2 + 120e: 3b01 cmphsi r3, 2 + 1210: 0bf6 bt 0x11fc // 11fc + if(Selete_EXI_x==16) + 1212: 3a50 cmpnei r2, 16 + 1214: 106f lrw r3, 0x20000044 // 1250 + 1216: 0806 bt 0x1222 // 1222 + GPIOGRP->IGREX =(GPIOGRP->IGREX)|PinNum; + 1218: 9340 ld.w r2, (r3, 0x0) + 121a: 9262 ld.w r3, (r2, 0x8) + 121c: 6c4c or r1, r3 + 121e: b222 st.w r1, (r2, 0x8) + 1220: 07ee br 0x11fc // 11fc + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<4); + 1222: 9360 ld.w r3, (r3, 0x0) + 1224: 9342 ld.w r2, (r3, 0x8) + 1226: 4124 lsli r1, r1, 4 + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<12); + 1228: 6c48 or r1, r2 + 122a: b322 st.w r1, (r3, 0x8) +} + 122c: 07e8 br 0x11fc // 11fc + else if((IO_MODE==2)&&((Selete_EXI_x==18)||(Selete_EXI_x==19))) //PB0.0~PB0.3 + 122e: 3842 cmpnei r0, 2 + 1230: 0be6 bt 0x11fc // 11fc + 1232: 3300 movi r3, 0 + 1234: 2b11 subi r3, 18 + 1236: 60c8 addu r3, r2 + 1238: 3b01 cmphsi r3, 2 + 123a: 0be1 bt 0x11fc // 11fc + 123c: 1065 lrw r3, 0x20000044 // 1250 + if(Selete_EXI_x==18) + 123e: 3a52 cmpnei r2, 18 + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<8); + 1240: 9360 ld.w r3, (r3, 0x0) + 1242: 9342 ld.w r2, (r3, 0x8) + if(Selete_EXI_x==18) + 1244: 0803 bt 0x124a // 124a + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<8); + 1246: 4128 lsli r1, r1, 8 + 1248: 07f0 br 0x1228 // 1228 + GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<12); + 124a: 412c lsli r1, r1, 12 + 124c: 07ee br 0x1228 // 1228 + 124e: 0000 bkpt + 1250: 20000044 .long 0x20000044 + 1254: fffff0ff .long 0xfffff0ff + 1258: ffff0fff .long 0xffff0fff + 125c: fff10000 .long 0xfff10000 + 1260: ff100000 .long 0xff100000 + 1264: 0fffffff .long 0x0fffffff + +Disassembly of section .text.GPIO_Write_High: + +00001268 : +//bit:0~15 +//ReturnValue:VALUE +/*************************************************************/ +void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->SODR = (1ul<: +void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + (GPIOx)->CODR = (1ul<: +/*************************************************************/ +uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit) +{ + uint8_t value = 0; + uint32_t dat = 0; + dat=((GPIOx)->PSDR)&(1<: +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPT_Soft_Reset(void) +{ + LPT->RSSR |= (0X5<<12); + 1288: 1064 lrw r3, 0x20000014 // 1298 + 128a: 9340 ld.w r2, (r3, 0x0) + 128c: 9261 ld.w r3, (r2, 0x4) + 128e: 3bac bseti r3, 12 + 1290: 3bae bseti r3, 14 + 1292: b261 st.w r3, (r2, 0x4) +} + 1294: 783c jmp r15 + 1296: 0000 bkpt + 1298: 20000014 .long 0x20000014 + +Disassembly of section .text.WWDT_CONFIG: + +0000129c : +//WWDT CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX) +{ + 129c: 14c1 push r4 + WWDT->CFGR =WND_DATA; + 129e: 1065 lrw r3, 0x20000010 // 12b0 + 12a0: 9380 ld.w r4, (r3, 0x0) + 12a2: b421 st.w r1, (r4, 0x4) + WWDT->CFGR |= PSCDIVX |DBGENX; + 12a4: 9461 ld.w r3, (r4, 0x4) + 12a6: 6c8c or r2, r3 + 12a8: 6c08 or r0, r2 + 12aa: b401 st.w r0, (r4, 0x4) +} + 12ac: 1481 pop r4 + 12ae: 0000 bkpt + 12b0: 20000010 .long 0x20000010 + +Disassembly of section .text.WWDT_CNT_Load: + +000012b4 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDT_CNT_Load(U8_T cnt_data) +{ + WWDT->CR |= cnt_data; //SET + 12b4: 1063 lrw r3, 0x20000010 // 12c0 + 12b6: 9360 ld.w r3, (r3, 0x0) + 12b8: 9340 ld.w r2, (r3, 0x0) + 12ba: 6c08 or r0, r2 + 12bc: b300 st.w r0, (r3, 0x0) +} + 12be: 783c jmp r15 + 12c0: 20000010 .long 0x20000010 + +Disassembly of section .text.WWDT_Int_Config: + +000012c4 : +//EntryParameter:NONE +//ReturnValue: NONE +/*************************************************************/ +void WWDT_Int_Config(FunctionalStatus NewState) +{ + if (NewState != DISABLE) + 12c4: 3840 cmpnei r0, 0 + 12c6: 106a lrw r3, 0x20000010 // 12ec + 12c8: 0c0b bf 0x12de // 12de + { + WWDT->ICR = WWDT_EVI; + 12ca: 9360 ld.w r3, (r3, 0x0) + 12cc: 3101 movi r1, 1 + 12ce: b325 st.w r1, (r3, 0x14) + WWDT->IMCR |= WWDT_EVI; + 12d0: 9344 ld.w r2, (r3, 0x10) + 12d2: 6c84 or r2, r1 + 12d4: b344 st.w r2, (r3, 0x10) + INTC_ISER_WRITE(WWDT_INT); + 12d6: 3240 movi r2, 64 + 12d8: 1066 lrw r3, 0xe000e100 // 12f0 + } + else + { + WWDT->IMCR &= ~WWDT_EVI; //CLR + INTC_ICER_WRITE(WWDT_INT); + 12da: b340 st.w r2, (r3, 0x0) + } + 12dc: 783c jmp r15 + WWDT->IMCR &= ~WWDT_EVI; //CLR + 12de: 9340 ld.w r2, (r3, 0x0) + 12e0: 9264 ld.w r3, (r2, 0x10) + 12e2: 3b80 bclri r3, 0 + 12e4: b264 st.w r3, (r2, 0x10) + INTC_ICER_WRITE(WWDT_INT); + 12e6: 3240 movi r2, 64 + 12e8: 1063 lrw r3, 0xe000e180 // 12f4 + 12ea: 07f8 br 0x12da // 12da + 12ec: 20000010 .long 0x20000010 + 12f0: e000e100 .long 0xe000e100 + 12f4: e000e180 .long 0xe000e180 + +Disassembly of section .text.BT_DeInit: + +000012f8 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_DeInit(CSP_BT_T *BTx) +{ + BTx->RSSR=BT_RESET_VALUE; + 12f8: 3300 movi r3, 0 + 12fa: b060 st.w r3, (r0, 0x0) + BTx->CR=BT_RESET_VALUE; + 12fc: b061 st.w r3, (r0, 0x4) + BTx->PSCR=BT_RESET_VALUE; + 12fe: b062 st.w r3, (r0, 0x8) + BTx->PRDR=BT_RESET_VALUE; + 1300: b063 st.w r3, (r0, 0xc) + BTx->CMP=BT_RESET_VALUE; + 1302: b064 st.w r3, (r0, 0x10) + BTx->CNT=BT_RESET_VALUE; + 1304: b065 st.w r3, (r0, 0x14) + BTx->EVTRG=BT_RESET_VALUE; + 1306: b066 st.w r3, (r0, 0x18) + BTx->EVSWF=BT_RESET_VALUE; + 1308: b069 st.w r3, (r0, 0x24) + BTx->RISR=BT_RESET_VALUE; + 130a: b06a st.w r3, (r0, 0x28) + BTx->IMCR=BT_RESET_VALUE; + 130c: b06b st.w r3, (r0, 0x2c) + BTx->MISR=BT_RESET_VALUE; + 130e: b06c st.w r3, (r0, 0x30) + BTx->ICR=BT_RESET_VALUE; + 1310: b06d st.w r3, (r0, 0x34) +} + 1312: 783c jmp r15 + +Disassembly of section .text.BT_IO_Init: + +00001314 : +//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10, +//ReturnValue:NONE +/*************************************************************/ +void BT_IO_Init(BT_Pin_TypeDef BT_IONAME) +{ + if(BT_IONAME==BT0_PA00) + 1314: 3840 cmpnei r0, 0 + 1316: 080a bt 0x132a // 132a + { + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; //BT0 PA0.0 + 1318: 1270 lrw r3, 0x2000004c // 1458 + 131a: 310f movi r1, 15 + 131c: 9340 ld.w r2, (r3, 0x0) + 131e: 9260 ld.w r3, (r2, 0x0) + 1320: 68c5 andn r3, r1 + 1322: 3ba1 bseti r3, 1 + 1324: 3ba2 bseti r3, 2 + { + GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14 + } + if(BT_IONAME==BT1_PB00) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000008; //BT1 PB0.0 + 1326: b260 st.w r3, (r2, 0x0) + 1328: 044e br 0x13c4 // 13c4 + if(BT_IONAME==BT0_PA02) + 132a: 3841 cmpnei r0, 1 + 132c: 080b bt 0x1342 // 1342 + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000600; //BT0 PA0.2 + 132e: 126b lrw r3, 0x2000004c // 1458 + 1330: 32f0 movi r2, 240 + 1332: 9320 ld.w r1, (r3, 0x0) + 1334: 9160 ld.w r3, (r1, 0x0) + 1336: 4244 lsli r2, r2, 4 + 1338: 68c9 andn r3, r2 + 133a: 3ba9 bseti r3, 9 + 133c: 3baa bseti r3, 10 + } + if(BT_IONAME==BT1_PB04) + { + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4 + 133e: b160 st.w r3, (r1, 0x0) + } +} + 1340: 0442 br 0x13c4 // 13c4 + if(BT_IONAME==BT0_PA05) + 1342: 3842 cmpnei r0, 2 + 1344: 080a bt 0x1358 // 1358 + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00500000; //BT0 PA0.5 + 1346: 1265 lrw r3, 0x2000004c // 1458 + 1348: 32f0 movi r2, 240 + 134a: 9320 ld.w r1, (r3, 0x0) + 134c: 9160 ld.w r3, (r1, 0x0) + 134e: 4250 lsli r2, r2, 16 + 1350: 68c9 andn r3, r2 + 1352: 3bb4 bseti r3, 20 + 1354: 3bb6 bseti r3, 22 + 1356: 07f4 br 0x133e // 133e + if(BT_IONAME==BT0_PB02) + 1358: 3843 cmpnei r0, 3 + 135a: 080a bt 0x136e // 136e + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFF0FF)|0x00000500; //BT0 PB0.2 + 135c: 1260 lrw r3, 0x20000048 // 145c + 135e: 32f0 movi r2, 240 + 1360: 9320 ld.w r1, (r3, 0x0) + 1362: 9160 ld.w r3, (r1, 0x0) + 1364: 4244 lsli r2, r2, 4 + 1366: 68c9 andn r3, r2 + 1368: 3ba8 bseti r3, 8 + 136a: 3baa bseti r3, 10 + 136c: 07e9 br 0x133e // 133e + if(BT_IONAME==BT0_PB05) + 136e: 3844 cmpnei r0, 4 + 1370: 080b bt 0x1386 // 1386 + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFF0FFFFF)|0x00700000; //BT0 PB0.5 + 1372: 117b lrw r3, 0x20000048 // 145c + 1374: 32f0 movi r2, 240 + 1376: 9320 ld.w r1, (r3, 0x0) + 1378: 4250 lsli r2, r2, 16 + 137a: 9160 ld.w r3, (r1, 0x0) + 137c: 68c9 andn r3, r2 + 137e: 32e0 movi r2, 224 + 1380: 424f lsli r2, r2, 15 + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4 + 1382: 6cc8 or r3, r2 + 1384: 07dd br 0x133e // 133e + if(BT_IONAME==BT0_PA11) + 1386: 3845 cmpnei r0, 5 + 1388: 080a bt 0x139c // 139c + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00008000; //BT0 PA0.11 + 138a: 1174 lrw r3, 0x2000004c // 1458 + 138c: 32f0 movi r2, 240 + 138e: 9320 ld.w r1, (r3, 0x0) + 1390: 9161 ld.w r3, (r1, 0x4) + 1392: 4248 lsli r2, r2, 8 + 1394: 68c9 andn r3, r2 + 1396: 3baf bseti r3, 15 + GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14 + 1398: b161 st.w r3, (r1, 0x4) + 139a: 0415 br 0x13c4 // 13c4 + if(BT_IONAME==BT0_PA13) + 139c: 3846 cmpnei r0, 6 + 139e: 0809 bt 0x13b0 // 13b0 + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00800000; //BT0 PA0.13 + 13a0: 116e lrw r3, 0x2000004c // 1458 + 13a2: 32f0 movi r2, 240 + 13a4: 9320 ld.w r1, (r3, 0x0) + 13a6: 9161 ld.w r3, (r1, 0x4) + 13a8: 4250 lsli r2, r2, 16 + 13aa: 68c9 andn r3, r2 + 13ac: 3bb7 bseti r3, 23 + 13ae: 07f5 br 0x1398 // 1398 + if(BT_IONAME==BT0_PA15) + 13b0: 3847 cmpnei r0, 7 + 13b2: 080a bt 0x13c6 // 13c6 + GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000; //BT0 PA0.15 + 13b4: 1169 lrw r3, 0x2000004c // 1458 + 13b6: 9340 ld.w r2, (r3, 0x0) + 13b8: 9261 ld.w r3, (r2, 0x4) + 13ba: 4364 lsli r3, r3, 4 + 13bc: 4b64 lsri r3, r3, 4 + 13be: 3bbc bseti r3, 28 + 13c0: 3bbe bseti r3, 30 + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000006; //BT1 PA0.8 + 13c2: b261 st.w r3, (r2, 0x4) +} + 13c4: 783c jmp r15 + if(BT_IONAME==BT1_PA01) + 13c6: 3848 cmpnei r0, 8 + 13c8: 0809 bt 0x13da // 13da + GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000060; //BT1 PA0.1 + 13ca: 1164 lrw r3, 0x2000004c // 1458 + 13cc: 31f0 movi r1, 240 + 13ce: 9340 ld.w r2, (r3, 0x0) + 13d0: 9260 ld.w r3, (r2, 0x0) + 13d2: 68c5 andn r3, r1 + 13d4: 3ba5 bseti r3, 5 + 13d6: 3ba6 bseti r3, 6 + 13d8: 07a7 br 0x1326 // 1326 + if(BT_IONAME==BT1_PA06) + 13da: 3849 cmpnei r0, 9 + 13dc: 0809 bt 0x13ee // 13ee + GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x04000000; //BT1 PA0.6 + 13de: 107f lrw r3, 0x2000004c // 1458 + 13e0: 32f0 movi r2, 240 + 13e2: 9320 ld.w r1, (r3, 0x0) + 13e4: 9160 ld.w r3, (r1, 0x0) + 13e6: 4254 lsli r2, r2, 20 + 13e8: 68c9 andn r3, r2 + 13ea: 3bba bseti r3, 26 + 13ec: 07a9 br 0x133e // 133e + if(BT_IONAME==BT1_PA08) + 13ee: 384a cmpnei r0, 10 + 13f0: 0809 bt 0x1402 // 1402 + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000006; //BT1 PA0.8 + 13f2: 107a lrw r3, 0x2000004c // 1458 + 13f4: 310f movi r1, 15 + 13f6: 9340 ld.w r2, (r3, 0x0) + 13f8: 9261 ld.w r3, (r2, 0x4) + 13fa: 68c5 andn r3, r1 + 13fc: 3ba1 bseti r3, 1 + 13fe: 3ba2 bseti r3, 2 + 1400: 07e1 br 0x13c2 // 13c2 + if(BT_IONAME==BT1_PA12) + 1402: 384b cmpnei r0, 11 + 1404: 080a bt 0x1418 // 1418 + GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00060000; //BT1 PA0.12 + 1406: 1075 lrw r3, 0x2000004c // 1458 + 1408: 32f0 movi r2, 240 + 140a: 9320 ld.w r1, (r3, 0x0) + 140c: 9161 ld.w r3, (r1, 0x4) + 140e: 424c lsli r2, r2, 12 + 1410: 68c9 andn r3, r2 + 1412: 3bb1 bseti r3, 17 + 1414: 3bb2 bseti r3, 18 + 1416: 07c1 br 0x1398 // 1398 + if(BT_IONAME==BT1_PA14) + 1418: 384c cmpnei r0, 12 + 141a: 080a bt 0x142e // 142e + GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14 + 141c: 106f lrw r3, 0x2000004c // 1458 + 141e: 32f0 movi r2, 240 + 1420: 9320 ld.w r1, (r3, 0x0) + 1422: 9161 ld.w r3, (r1, 0x4) + 1424: 4254 lsli r2, r2, 20 + 1426: 68c9 andn r3, r2 + 1428: 3bb8 bseti r3, 24 + 142a: 3bba bseti r3, 26 + 142c: 07b6 br 0x1398 // 1398 + if(BT_IONAME==BT1_PB00) + 142e: 384d cmpnei r0, 13 + 1430: 0808 bt 0x1440 // 1440 + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000008; //BT1 PB0.0 + 1432: 106b lrw r3, 0x20000048 // 145c + 1434: 310f movi r1, 15 + 1436: 9340 ld.w r2, (r3, 0x0) + 1438: 9260 ld.w r3, (r2, 0x0) + 143a: 68c5 andn r3, r1 + 143c: 3ba3 bseti r3, 3 + 143e: 0774 br 0x1326 // 1326 + if(BT_IONAME==BT1_PB04) + 1440: 384e cmpnei r0, 14 + 1442: 0bc1 bt 0x13c4 // 13c4 + GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4 + 1444: 1066 lrw r3, 0x20000048 // 145c + 1446: 32f0 movi r2, 240 + 1448: 9320 ld.w r1, (r3, 0x0) + 144a: 424c lsli r2, r2, 12 + 144c: 9160 ld.w r3, (r1, 0x0) + 144e: 68c9 andn r3, r2 + 1450: 32e0 movi r2, 224 + 1452: 424b lsli r2, r2, 11 + 1454: 0797 br 0x1382 // 1382 + 1456: 0000 bkpt + 1458: 2000004c .long 0x2000004c + 145c: 20000048 .long 0x20000048 + +Disassembly of section .text.BT_Start: + +00001460 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Start(CSP_BT_T *BTx) +{ + BTx->RSSR |=0X01; + 1460: 9060 ld.w r3, (r0, 0x0) + 1462: 3ba0 bseti r3, 0 + 1464: b060 st.w r3, (r0, 0x0) +} + 1466: 783c jmp r15 + +Disassembly of section .text.BT_Soft_Reset: + +00001468 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_Soft_Reset(CSP_BT_T *BTx) +{ + BTx->RSSR |= (0X5<<12); + 1468: 9060 ld.w r3, (r0, 0x0) + 146a: 3bac bseti r3, 12 + 146c: 3bae bseti r3, 14 + 146e: b060 st.w r3, (r0, 0x0) +} + 1470: 783c jmp r15 + +Disassembly of section .text.BT_Configure: + +00001472 : +//BT Configure +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM) +{ + 1472: 14c3 push r4-r6 + 1474: 98a4 ld.w r5, (r14, 0x10) + 1476: 6d97 mov r6, r5 + 1478: 9883 ld.w r4, (r14, 0xc) + BTx->CR |=BTCLK| BTSHDWSTP| BTOPM| BTEXTCKM; + 147a: 6d18 or r4, r6 + 147c: 6cd0 or r3, r4 + 147e: 90a1 ld.w r5, (r0, 0x4) + 1480: 6c4c or r1, r3 + 1482: 6c54 or r1, r5 + 1484: b021 st.w r1, (r0, 0x4) + BTx->PSCR = PSCR_DATA; + 1486: b042 st.w r2, (r0, 0x8) +} + 1488: 1483 pop r4-r6 + +Disassembly of section .text.BT_ControlSet_Configure: + +0000148a : +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD, + BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD) +{ + 148a: 14c4 push r4-r7 + 148c: 1421 subi r14, r14, 4 + 148e: 9885 ld.w r4, (r14, 0x14) + 1490: 6dd3 mov r7, r4 + 1492: 9886 ld.w r4, (r14, 0x18) + 1494: b880 st.w r4, (r14, 0x0) + 1496: 9887 ld.w r4, (r14, 0x1c) + 1498: 6d93 mov r6, r4 + 149a: 98a8 ld.w r5, (r14, 0x20) + BTx->CR |=BTSTART| BTIDLE| BTSYNC| BTSYNCMD| BTOSTMD| BTAREARM| BTCNTRLD; + 149c: 6d58 or r5, r6 + 149e: 98c0 ld.w r6, (r14, 0x0) + 14a0: 6d58 or r5, r6 + 14a2: 6d5c or r5, r7 + 14a4: 6cd4 or r3, r5 + 14a6: 6c8c or r2, r3 + 14a8: 9081 ld.w r4, (r0, 0x4) + 14aa: 6c48 or r1, r2 + 14ac: 6d04 or r4, r1 + 14ae: 6d9f mov r6, r7 + 14b0: b081 st.w r4, (r0, 0x4) +} + 14b2: 1401 addi r14, r14, 4 + 14b4: 1484 pop r4-r7 + +Disassembly of section .text.BT_Period_CMP_Write: + +000014b6 : +//ReturnValue:NONE +/*************************************************************/ +void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA) +{ + //BTx->CR|=0X01<<2; + BTx->PRDR =BTPRDR_DATA; + 14b6: b023 st.w r1, (r0, 0xc) + BTx->CMP =BTCMP_DATA; + 14b8: b044 st.w r2, (r0, 0x10) +} + 14ba: 783c jmp r15 + +Disassembly of section .text.BT_ConfigInterrupt_CMD: + +000014bc : +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X) +{ + if (NewState != DISABLE) + 14bc: 3940 cmpnei r1, 0 + { + BTx->IMCR |= BT_IMSCR_X; + 14be: 906b ld.w r3, (r0, 0x2c) + if (NewState != DISABLE) + 14c0: 0c04 bf 0x14c8 // 14c8 + BTx->IMCR |= BT_IMSCR_X; + 14c2: 6c8c or r2, r3 + 14c4: b04b st.w r2, (r0, 0x2c) + } + else + { + BTx->IMCR &= ~BT_IMSCR_X; + } +} + 14c6: 783c jmp r15 + BTx->IMCR &= ~BT_IMSCR_X; + 14c8: 68c9 andn r3, r2 + 14ca: b06b st.w r3, (r0, 0x2c) +} + 14cc: 07fd br 0x14c6 // 14c6 + +Disassembly of section .text.BT1_INT_ENABLE: + +000014d0 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT1_INT_ENABLE(void) +{ + INTC_ISER_WRITE(BT1_INT); + 14d0: 3380 movi r3, 128 + 14d2: 4376 lsli r3, r3, 22 + 14d4: 1042 lrw r2, 0xe000e100 // 14dc + 14d6: b260 st.w r3, (r2, 0x0) +} + 14d8: 783c jmp r15 + 14da: 0000 bkpt + 14dc: e000e100 .long 0xe000e100 + +Disassembly of section .text.GPT_Configure: + +000014e0 : +//GPT Init +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX) +{ + 14e0: 14c1 push r4 + GPT0->CEDR = GPTCLKX| GCSSX|GSHDWSTPX; + 14e2: 6c48 or r1, r2 + 14e4: 1083 lrw r4, 0x20000024 // 14f0 + 14e6: 6c04 or r0, r1 + 14e8: 9480 ld.w r4, (r4, 0x0) + 14ea: b400 st.w r0, (r4, 0x0) + GPT0->PSCR=GPSCX; + 14ec: b462 st.w r3, (r4, 0x8) +} + 14ee: 1481 pop r4 + 14f0: 20000024 .long 0x20000024 + +Disassembly of section .text.GPT_WaveCtrl_Configure: + +000014f4 : +/*************************************************************/ +//GPT0->CR = (0X0<<0)|(0x00<<2)|(0x01<<3)|(0x00<<4)|(0X00<<6)|(0x01<<18)|(0x00<<9)|(0X00<<10)|(0x00<<11)|(0x00<<13) ; +//GPT0->CMPLDR=(0X00<<0)|(0X00<<1)|(0X03<<4)|(0X03<<7); +void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX, + GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX) +{ + 14f4: 14c4 push r4-r7 + 14f6: 1423 subi r14, r14, 12 + 14f8: 9887 ld.w r4, (r14, 0x1c) + 14fa: 6dd3 mov r7, r4 + 14fc: 9888 ld.w r4, (r14, 0x20) + 14fe: b880 st.w r4, (r14, 0x0) + 1500: 9889 ld.w r4, (r14, 0x24) + 1502: b881 st.w r4, (r14, 0x4) + 1504: 988a ld.w r4, (r14, 0x28) + 1506: b882 st.w r4, (r14, 0x8) + 1508: 988b ld.w r4, (r14, 0x2c) + 150a: 6d93 mov r6, r4 + 150c: 988c ld.w r4, (r14, 0x30) + GPT0->CR =GCNTMDX|GSWSYNX|GIDLEX|GPRDLD0|GOPMX|GBURSTX|GCKS|CGSRCX|CGFLT|PSCLDX|GPT_WAVE_MODE; + 150e: 3cb2 bseti r4, 18 + 1510: 6d18 or r4, r6 + 1512: 98c2 ld.w r6, (r14, 0x8) + 1514: 6d18 or r4, r6 + 1516: 98c1 ld.w r6, (r14, 0x4) + 1518: 6d18 or r4, r6 + 151a: 98c0 ld.w r6, (r14, 0x0) + 151c: 6d18 or r4, r6 + 151e: 6d1c or r4, r7 + 1520: 6cd0 or r3, r4 + 1522: 6c8c or r2, r3 + 1524: 6c48 or r1, r2 + 1526: 10a4 lrw r5, 0x20000024 // 1534 + 1528: 6c04 or r0, r1 + 152a: 95a0 ld.w r5, (r5, 0x0) + 152c: 6d9f mov r6, r7 + 152e: b503 st.w r0, (r5, 0xc) +} + 1530: 1403 addi r14, r14, 12 + 1532: 1484 pop r4-r7 + 1534: 20000024 .long 0x20000024 + +Disassembly of section .text.GPT_Start: + +00001538 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_Start(void) +{ + GPT0->RSSR |= 0X01; + 1538: 1063 lrw r3, 0x20000024 // 1544 + 153a: 9340 ld.w r2, (r3, 0x0) + 153c: 9261 ld.w r3, (r2, 0x4) + 153e: 3ba0 bseti r3, 0 + 1540: b261 st.w r3, (r2, 0x4) +} + 1542: 783c jmp r15 + 1544: 20000024 .long 0x20000024 + +Disassembly of section .text.GPT_Period_CMP_Write: + +00001548 : +//EntryParameter: +//ReturnValue:NONE +/*************************************************************/ +void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA) +{ + GPT0->PRDR =PRDR_DATA; + 1548: 1063 lrw r3, 0x20000024 // 1554 + 154a: 9360 ld.w r3, (r3, 0x0) + 154c: b309 st.w r0, (r3, 0x24) + GPT0->CMPA =CMPA_DATA; + 154e: b32b st.w r1, (r3, 0x2c) + GPT0->CMPB =CMPB_DATA; + 1550: b34c st.w r2, (r3, 0x30) +} + 1552: 783c jmp r15 + 1554: 20000024 .long 0x20000024 + +Disassembly of section .text.GPT_ConfigInterrupt_CMD: + +00001558 : +//EntryParameter:LPT_IMSCR_X,NewState +//NewState:ENABLE,DISABLE +//ReturnValue:NONE +/*************************************************************/ +void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X) +{ + 1558: 1066 lrw r3, 0x20000024 // 1570 + if (NewState != DISABLE) + 155a: 3840 cmpnei r0, 0 + { + GPT0->IMCR |= GPT_IMSCR_X; + 155c: 9360 ld.w r3, (r3, 0x0) + 155e: 237f addi r3, 128 + 1560: 9356 ld.w r2, (r3, 0x58) + if (NewState != DISABLE) + 1562: 0c04 bf 0x156a // 156a + GPT0->IMCR |= GPT_IMSCR_X; + 1564: 6c48 or r1, r2 + 1566: b336 st.w r1, (r3, 0x58) + } + else + { + GPT0->IMCR &= ~GPT_IMSCR_X; + } +} + 1568: 783c jmp r15 + GPT0->IMCR &= ~GPT_IMSCR_X; + 156a: 6885 andn r2, r1 + 156c: b356 st.w r2, (r3, 0x58) +} + 156e: 07fd br 0x1568 // 1568 + 1570: 20000024 .long 0x20000024 + +Disassembly of section .text.GPT_INT_ENABLE: + +00001574 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT_INT_ENABLE(void) +{ + INTC_ISER_WRITE(GPT0_INT); + 1574: 3380 movi r3, 128 + 1576: 4362 lsli r3, r3, 2 + 1578: 1042 lrw r2, 0xe000e100 // 1580 + 157a: b260 st.w r3, (r2, 0x0) +} + 157c: 783c jmp r15 + 157e: 0000 bkpt + 1580: e000e100 .long 0xe000e100 + +Disassembly of section .text.UART0_DeInit: + +00001584 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_DeInit(void) +{ + UART0->DATA = UART_RESET_VALUE; + 1584: 1065 lrw r3, 0x20000040 // 1598 + 1586: 3200 movi r2, 0 + 1588: 9360 ld.w r3, (r3, 0x0) + 158a: b340 st.w r2, (r3, 0x0) + UART0->SR = UART_RESET_VALUE; + 158c: b341 st.w r2, (r3, 0x4) + UART0->CTRL = UART_RESET_VALUE; + 158e: b342 st.w r2, (r3, 0x8) + UART0->ISR = UART_RESET_VALUE; + 1590: b343 st.w r2, (r3, 0xc) + UART0->BRDIV =UART_RESET_VALUE; + 1592: b344 st.w r2, (r3, 0x10) +} + 1594: 783c jmp r15 + 1596: 0000 bkpt + 1598: 20000040 .long 0x20000040 + +Disassembly of section .text.UART1_DeInit: + +0000159c : +void UART1_DeInit(void) +{ + UART1->DATA = UART_RESET_VALUE; + 159c: 1065 lrw r3, 0x2000003c // 15b0 + 159e: 3200 movi r2, 0 + 15a0: 9360 ld.w r3, (r3, 0x0) + 15a2: b340 st.w r2, (r3, 0x0) + UART1->SR = UART_RESET_VALUE; + 15a4: b341 st.w r2, (r3, 0x4) + UART1->CTRL = UART_RESET_VALUE; + 15a6: b342 st.w r2, (r3, 0x8) + UART1->ISR = UART_RESET_VALUE; + 15a8: b343 st.w r2, (r3, 0xc) + UART1->BRDIV =UART_RESET_VALUE; + 15aa: b344 st.w r2, (r3, 0x10) +} + 15ac: 783c jmp r15 + 15ae: 0000 bkpt + 15b0: 2000003c .long 0x2000003c + +Disassembly of section .text.UART2_DeInit: + +000015b4 : +void UART2_DeInit(void) +{ + UART2->DATA = UART_RESET_VALUE; + 15b4: 1065 lrw r3, 0x20000038 // 15c8 + 15b6: 3200 movi r2, 0 + 15b8: 9360 ld.w r3, (r3, 0x0) + 15ba: b340 st.w r2, (r3, 0x0) + UART2->SR = UART_RESET_VALUE; + 15bc: b341 st.w r2, (r3, 0x4) + UART2->CTRL = UART_RESET_VALUE; + 15be: b342 st.w r2, (r3, 0x8) + UART2->ISR = UART_RESET_VALUE; + 15c0: b343 st.w r2, (r3, 0xc) + UART2->BRDIV =UART_RESET_VALUE; + 15c2: b344 st.w r2, (r3, 0x10) +} + 15c4: 783c jmp r15 + 15c6: 0000 bkpt + 15c8: 20000038 .long 0x20000038 + +Disassembly of section .text.UART0_Int_Enable: + +000015cc : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_Int_Enable(void) +{ + UART0->ISR=0x0F; //clear UART0 INT status + 15cc: 1065 lrw r3, 0x20000040 // 15e0 + 15ce: 320f movi r2, 15 + 15d0: 9360 ld.w r3, (r3, 0x0) + 15d2: b343 st.w r2, (r3, 0xc) + INTC_ISER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802 + 15d4: 3380 movi r3, 128 + 15d6: 4366 lsli r3, r3, 6 + 15d8: 1043 lrw r2, 0xe000e100 // 15e4 + 15da: b260 st.w r3, (r2, 0x0) +} + 15dc: 783c jmp r15 + 15de: 0000 bkpt + 15e0: 20000040 .long 0x20000040 + 15e4: e000e100 .long 0xe000e100 + +Disassembly of section .text.UART1_Int_Enable: + +000015e8 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_Int_Enable(void) +{ + UART1->ISR=0x0F; //clear UART1 INT status + 15e8: 1065 lrw r3, 0x2000003c // 15fc + 15ea: 320f movi r2, 15 + 15ec: 9360 ld.w r3, (r3, 0x0) + 15ee: b343 st.w r2, (r3, 0xc) + INTC_ISER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802 + 15f0: 3380 movi r3, 128 + 15f2: 4367 lsli r3, r3, 7 + 15f4: 1043 lrw r2, 0xe000e100 // 1600 + 15f6: b260 st.w r3, (r2, 0x0) +} + 15f8: 783c jmp r15 + 15fa: 0000 bkpt + 15fc: 2000003c .long 0x2000003c + 1600: e000e100 .long 0xe000e100 + +Disassembly of section .text.UART_IO_Init: + +00001604 : +//UART_IO_G:0 1 +//ReturnValue:NONE +/*************************************************************/ +void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G) +{ + if (IO_UART_NUM==IO_UART0) + 1604: 3840 cmpnei r0, 0 + 1606: 0820 bt 0x1646 // 1646 + { + if(UART_IO_G==0) + 1608: 3940 cmpnei r1, 0 + 160a: 0809 bt 0x161c // 161c + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000004; //PA0.1->RXD0, PA0.0->TXD0 + 160c: 1176 lrw r3, 0x2000004c // 16e4 + 160e: 310f movi r1, 15 + 1610: 9340 ld.w r2, (r3, 0x0) + 1612: 9260 ld.w r3, (r2, 0x0) + 1614: 68c5 andn r3, r1 + 1616: 3ba2 bseti r3, 2 + } + if (IO_UART_NUM==IO_UART2) + { + if(UART_IO_G==0) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000077; //PA0.0->RXD2, PA0.1->TXD2 + 1618: b260 st.w r3, (r2, 0x0) + 161a: 0415 br 0x1644 // 1644 + else if(UART_IO_G==1) + 161c: 3941 cmpnei r1, 1 + 161e: 0813 bt 0x1644 // 1644 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00700000; //PA0.5->RXD0, PA0.12->TXD0 + 1620: 1171 lrw r3, 0x2000004c // 16e4 + 1622: 31f0 movi r1, 240 + 1624: 9340 ld.w r2, (r3, 0x0) + 1626: 9260 ld.w r3, (r2, 0x0) + 1628: 4130 lsli r1, r1, 16 + 162a: 68c5 andn r3, r1 + 162c: 31e0 movi r1, 224 + 162e: 412f lsli r1, r1, 15 + 1630: 6cc4 or r3, r1 + 1632: b260 st.w r3, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00070000; + 1634: 31f0 movi r1, 240 + 1636: 9261 ld.w r3, (r2, 0x4) + 1638: 412c lsli r1, r1, 12 + 163a: 68c5 andn r3, r1 + 163c: 31e0 movi r1, 224 + 163e: 412b lsli r1, r1, 11 + 1640: 6cc4 or r3, r1 + 1642: b261 st.w r3, (r2, 0x4) + else if(UART_IO_G==2) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2 + } + } +} + 1644: 783c jmp r15 + if (IO_UART_NUM==IO_UART1) + 1646: 3841 cmpnei r0, 1 + 1648: 082d bt 0x16a2 // 16a2 + if(UART_IO_G==0) + 164a: 3940 cmpnei r1, 0 + 164c: 0814 bt 0x1674 // 1674 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000007; //PA0.13->RXD1, PB0.0->TXD1 + 164e: 1167 lrw r3, 0x20000048 // 16e8 + 1650: 310f movi r1, 15 + 1652: 9340 ld.w r2, (r3, 0x0) + 1654: 9260 ld.w r3, (r2, 0x0) + 1656: 68c5 andn r3, r1 + 1658: 3107 movi r1, 7 + 165a: 6cc4 or r3, r1 + 165c: b260 st.w r3, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00700000; + 165e: 32f0 movi r2, 240 + 1660: 1161 lrw r3, 0x2000004c // 16e4 + 1662: 4250 lsli r2, r2, 16 + 1664: 9320 ld.w r1, (r3, 0x0) + 1666: 9161 ld.w r3, (r1, 0x4) + 1668: 68c9 andn r3, r2 + 166a: 32e0 movi r2, 224 + 166c: 424f lsli r2, r2, 15 + GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0X77000000; //PA0.15->RXD1, PA0.14->TXD1 + 166e: 6cc8 or r3, r2 + 1670: b161 st.w r3, (r1, 0x4) + 1672: 07e9 br 0x1644 // 1644 + else if(UART_IO_G==1) + 1674: 3941 cmpnei r1, 1 + 1676: 080c bt 0x168e // 168e + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF) | 0X00077000; //PA0.4->RXD1, PA0.3->TXD1 + 1678: 107b lrw r3, 0x2000004c // 16e4 + 167a: 32ff movi r2, 255 + 167c: 9320 ld.w r1, (r3, 0x0) + 167e: 424c lsli r2, r2, 12 + 1680: 9160 ld.w r3, (r1, 0x0) + 1682: 68c9 andn r3, r2 + 1684: 32ee movi r2, 238 + 1686: 424b lsli r2, r2, 11 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2 + 1688: 6cc8 or r3, r2 + 168a: b160 st.w r3, (r1, 0x0) +} + 168c: 07dc br 0x1644 // 1644 + else if(UART_IO_G==2) + 168e: 3942 cmpnei r1, 2 + 1690: 0bda bt 0x1644 // 1644 + GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0X77000000; //PA0.15->RXD1, PA0.14->TXD1 + 1692: 1075 lrw r3, 0x2000004c // 16e4 + 1694: 32ee movi r2, 238 + 1696: 9320 ld.w r1, (r3, 0x0) + 1698: 9161 ld.w r3, (r1, 0x4) + 169a: 4368 lsli r3, r3, 8 + 169c: 4b68 lsri r3, r3, 8 + 169e: 4257 lsli r2, r2, 23 + 16a0: 07e7 br 0x166e // 166e + if (IO_UART_NUM==IO_UART2) + 16a2: 3842 cmpnei r0, 2 + 16a4: 0bd0 bt 0x1644 // 1644 + if(UART_IO_G==0) + 16a6: 3940 cmpnei r1, 0 + 16a8: 0809 bt 0x16ba // 16ba + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000077; //PA0.0->RXD2, PA0.1->TXD2 + 16aa: 106f lrw r3, 0x2000004c // 16e4 + 16ac: 31ff movi r1, 255 + 16ae: 9340 ld.w r2, (r3, 0x0) + 16b0: 9260 ld.w r3, (r2, 0x0) + 16b2: 68c5 andn r3, r1 + 16b4: 3177 movi r1, 119 + 16b6: 6cc4 or r3, r1 + 16b8: 07b0 br 0x1618 // 1618 + else if(UART_IO_G==1) + 16ba: 3941 cmpnei r1, 1 + 16bc: 0809 bt 0x16ce // 16ce + GPIOA0->CONLR = (GPIOA0->CONLR&0X00FFFFFF) | 0X77000000; //PA0.7->RXD2, PA0.6->TXD2 + 16be: 106a lrw r3, 0x2000004c // 16e4 + 16c0: 32ee movi r2, 238 + 16c2: 9320 ld.w r1, (r3, 0x0) + 16c4: 9160 ld.w r3, (r1, 0x0) + 16c6: 4368 lsli r3, r3, 8 + 16c8: 4b68 lsri r3, r3, 8 + 16ca: 4257 lsli r2, r2, 23 + 16cc: 07de br 0x1688 // 1688 + else if(UART_IO_G==2) + 16ce: 3942 cmpnei r1, 2 + 16d0: 0bba bt 0x1644 // 1644 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2 + 16d2: 1066 lrw r3, 0x20000048 // 16e8 + 16d4: 32ff movi r2, 255 + 16d6: 9320 ld.w r1, (r3, 0x0) + 16d8: 4250 lsli r2, r2, 16 + 16da: 9160 ld.w r3, (r1, 0x0) + 16dc: 68c9 andn r3, r2 + 16de: 32cc movi r2, 204 + 16e0: 424f lsli r2, r2, 15 + 16e2: 07d3 br 0x1688 // 1688 + 16e4: 2000004c .long 0x2000004c + 16e8: 20000048 .long 0x20000048 + +Disassembly of section .text.UARTInitRxTxIntEn: + +000016ec : +//ReturnValue:NONE +/*************************************************************/ +void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT) +{ + // Set Transmitter Enable + CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT | UART_TX_INT|PAR_DAT); + 16ec: 330f movi r3, 15 + 16ee: 6c8c or r2, r3 + 16f0: b042 st.w r2, (r0, 0x8) + // Set Baudrate + CSP_UART_SET_BRDIV(uart, baudrate_u16); + 16f2: b024 st.w r1, (r0, 0x10) +} + 16f4: 783c jmp r15 + +Disassembly of section .text.UARTTxByte: + +000016f6 : +/*************************************************************/ +void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8) +{ + unsigned int DataI; + // Write the transmit buffer + CSP_UART_SET_DATA(uart,txdata_u8); + 16f6: b020 st.w r1, (r0, 0x0) + do + { + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_TX_FULL; + 16f8: 3201 movi r2, 1 + DataI = CSP_UART_GET_SR(uart); + 16fa: 9061 ld.w r3, (r0, 0x4) + DataI = DataI & UART_TX_FULL; + 16fc: 68c8 and r3, r2 + } + while(DataI == UART_TX_FULL); //Loop when tx is full + 16fe: 3b40 cmpnei r3, 0 + 1700: 0bfd bt 0x16fa // 16fa +} + 1702: 783c jmp r15 + +Disassembly of section .text.UARTTransmit: + +00001704 : +//UART Transmit +//EntryParameter:UART0,UART1,UART2,sourceAddress_u16,length_u16 +//ReturnValue:NONE +/*************************************************************/ +void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16) +{ + 1704: 14c2 push r4-r5 + unsigned int DataI,DataJ; + for(DataJ = 0;DataJ < length_u16 ;DataJ ++) + 1706: 6cc7 mov r3, r1 + { + CSP_UART_SET_DATA(uart,*sourceAddress_u16++); + do{ + DataI = CSP_UART_GET_SR(uart); + DataI = DataI & UART_TX_FULL; + 1708: 3501 movi r5, 1 + for(DataJ = 0;DataJ < length_u16 ;DataJ ++) + 170a: 5b85 subu r4, r3, r1 + 170c: 6490 cmphs r4, r2 + 170e: 0c02 bf 0x1712 // 1712 + }while(DataI == UART_TX_FULL); //Loop when tx is full + } +} + 1710: 1482 pop r4-r5 + CSP_UART_SET_DATA(uart,*sourceAddress_u16++); + 1712: 8380 ld.b r4, (r3, 0x0) + 1714: b080 st.w r4, (r0, 0x0) + DataI = CSP_UART_GET_SR(uart); + 1716: 9081 ld.w r4, (r0, 0x4) + DataI = DataI & UART_TX_FULL; + 1718: 6914 and r4, r5 + }while(DataI == UART_TX_FULL); //Loop when tx is full + 171a: 3c40 cmpnei r4, 0 + 171c: 0bfd bt 0x1716 // 1716 + 171e: 2300 addi r3, 1 + 1720: 07f5 br 0x170a // 170a + +Disassembly of section .text.EPT_Software_Prg: + +00001724 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Software_Prg(void) +{ + EPT0->CEDR|=0X01; + 1724: 1067 lrw r3, 0x20000020 // 1740 + EPT0->RSSR=(EPT0->RSSR&0XFFFF0FFF)|(0X05<<12); + 1726: 31f0 movi r1, 240 + EPT0->CEDR|=0X01; + 1728: 9340 ld.w r2, (r3, 0x0) + 172a: 9260 ld.w r3, (r2, 0x0) + 172c: 3ba0 bseti r3, 0 + 172e: b260 st.w r3, (r2, 0x0) + EPT0->RSSR=(EPT0->RSSR&0XFFFF0FFF)|(0X05<<12); + 1730: 9261 ld.w r3, (r2, 0x4) + 1732: 4128 lsli r1, r1, 8 + 1734: 68c5 andn r3, r1 + 1736: 3bac bseti r3, 12 + 1738: 3bae bseti r3, 14 + 173a: b261 st.w r3, (r2, 0x4) +} + 173c: 783c jmp r15 + 173e: 0000 bkpt + 1740: 20000020 .long 0x20000020 + +Disassembly of section .text.EPT_Start: + +00001744 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT_Start(void) +{ + EPT0->REGPROT = (0xA55A<<16) | 0xC73A; + 1744: 1068 lrw r3, 0x20000020 // 1764 + 1746: 3280 movi r2, 128 + 1748: 9360 ld.w r3, (r3, 0x0) + 174a: 608c addu r2, r3 + 174c: 1027 lrw r1, 0xa55ac73a // 1768 + 174e: b23a st.w r1, (r2, 0x68) + EPT0->RSSR|=0X01; + 1750: 9341 ld.w r2, (r3, 0x4) + 1752: 3aa0 bseti r2, 0 + 1754: b341 st.w r2, (r3, 0x4) + while(!(EPT0->RSSR&0x01)); + 1756: 3101 movi r1, 1 + 1758: 9341 ld.w r2, (r3, 0x4) + 175a: 6884 and r2, r1 + 175c: 3a40 cmpnei r2, 0 + 175e: 0ffd bf 0x1758 // 1758 +} + 1760: 783c jmp r15 + 1762: 0000 bkpt + 1764: 20000020 .long 0x20000020 + 1768: a55ac73a .long 0xa55ac73a + +Disassembly of section .text.EPT_IO_SET: + +0000176c : +//EPT_IO_X:EPT_IO_CHAX,EPT_IO_CHAY,EPT_IO_CHBX,EPT_IO_CHBY,EPT_IO_CHCX,EPT_IO_CHCX,EPT_IO_CHD,EPT_IO_EPI +//ReturnValue:NONE +/*************************************************************/ +void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X) +{ + if(EPT_IO_X==EPT_IO_CHAX) + 176c: 3840 cmpnei r0, 0 + 176e: 0822 bt 0x17b2 // 17b2 + { + if(IO_Num_X==IO_NUM_PA07) + 1770: 3950 cmpnei r1, 16 + 1772: 080a bt 0x1786 // 1786 + { + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X60000000; //PA0.7 + 1774: 0375 lrw r3, 0x2000004c // 199c + 1776: 9340 ld.w r2, (r3, 0x0) + 1778: 9260 ld.w r3, (r2, 0x0) + 177a: 4364 lsli r3, r3, 4 + 177c: 4b64 lsri r3, r3, 4 + 177e: 3bbd bseti r3, 29 + 1780: 3bbe bseti r3, 30 + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00004000; //PB0.3 + } + else if(IO_Num_X==IO_NUM_PB00) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)|0X00000005; //PB0.0 + 1782: b260 st.w r3, (r2, 0x0) + else if(IO_Num_X==IO_NUM_PB02) + { + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3 + } + } +} + 1784: 783c jmp r15 + else if(IO_Num_X==IO_NUM_PA10) + 1786: 3951 cmpnei r1, 17 + 1788: 080b bt 0x179e // 179e + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)|0X00000500; //PA0.10 + 178a: 037a lrw r3, 0x2000004c // 199c + 178c: 32f0 movi r2, 240 + 178e: 9320 ld.w r1, (r3, 0x0) + 1790: 9161 ld.w r3, (r1, 0x4) + 1792: 4244 lsli r2, r2, 4 + 1794: 68c9 andn r3, r2 + 1796: 3ba8 bseti r3, 8 + 1798: 3baa bseti r3, 10 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00400000; //PA0.13 EPI1 + 179a: b161 st.w r3, (r1, 0x4) + 179c: 07f4 br 0x1784 // 1784 + else if(IO_Num_X==IO_NUM_PA15) + 179e: 3952 cmpnei r1, 18 + 17a0: 0bf2 bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF)|0X40000000; //PA0.15 + 17a2: 137f lrw r3, 0x2000004c // 199c + 17a4: 9340 ld.w r2, (r3, 0x0) + 17a6: 9261 ld.w r3, (r2, 0x4) + 17a8: 4364 lsli r3, r3, 4 + 17aa: 4b64 lsri r3, r3, 4 + 17ac: 3bbe bseti r3, 30 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000004; //PA0.8 + 17ae: b261 st.w r3, (r2, 0x4) + 17b0: 07ea br 0x1784 // 1784 + else if(EPT_IO_X==EPT_IO_CHAY) + 17b2: 3841 cmpnei r0, 1 + 17b4: 0823 bt 0x17fa // 17fa + if(IO_Num_X==IO_NUM_PB03) + 17b6: 3953 cmpnei r1, 19 + 17b8: 080a bt 0x17cc // 17cc + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00005000; //PB0.3 + 17ba: 137a lrw r3, 0x20000048 // 19a0 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF)|0X00005000; //PA0.3 + 17bc: 9320 ld.w r1, (r3, 0x0) + 17be: 32f0 movi r2, 240 + 17c0: 9160 ld.w r3, (r1, 0x0) + 17c2: 4248 lsli r2, r2, 8 + 17c4: 68c9 andn r3, r2 + 17c6: 3bac bseti r3, 12 + 17c8: 3bae bseti r3, 14 + 17ca: 040b br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PB05) + 17cc: 3954 cmpnei r1, 20 + 17ce: 080b bt 0x17e4 // 17e4 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00500000; //PB0.5 + 17d0: 1374 lrw r3, 0x20000048 // 19a0 + 17d2: 32f0 movi r2, 240 + 17d4: 9320 ld.w r1, (r3, 0x0) + 17d6: 9160 ld.w r3, (r1, 0x0) + 17d8: 4250 lsli r2, r2, 16 + 17da: 68c9 andn r3, r2 + 17dc: 3bb4 bseti r3, 20 + 17de: 3bb6 bseti r3, 22 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3 + 17e0: b160 st.w r3, (r1, 0x0) +} + 17e2: 07d1 br 0x1784 // 1784 + else if(IO_Num_X==IO_NUM_PA12) + 17e4: 3955 cmpnei r1, 21 + 17e6: 0bcf bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)|0X00050000; //PA0.12 + 17e8: 136d lrw r3, 0x2000004c // 199c + 17ea: 32f0 movi r2, 240 + 17ec: 9320 ld.w r1, (r3, 0x0) + 17ee: 9161 ld.w r3, (r1, 0x4) + 17f0: 424c lsli r2, r2, 12 + 17f2: 68c9 andn r3, r2 + 17f4: 3bb0 bseti r3, 16 + 17f6: 3bb2 bseti r3, 18 + 17f8: 07d1 br 0x179a // 179a + else if(EPT_IO_X==EPT_IO_CHBX) + 17fa: 3842 cmpnei r0, 2 + 17fc: 0821 bt 0x183e // 183e + if(IO_Num_X==IO_NUM_PB02) + 17fe: 3956 cmpnei r1, 22 + 1800: 080a bt 0x1814 // 1814 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000600; //PB0.2 + 1802: 1368 lrw r3, 0x20000048 // 19a0 + 1804: 32f0 movi r2, 240 + 1806: 9320 ld.w r1, (r3, 0x0) + 1808: 9160 ld.w r3, (r1, 0x0) + 180a: 4244 lsli r2, r2, 4 + 180c: 68c9 andn r3, r2 + 180e: 3ba9 bseti r3, 9 + 1810: 3baa bseti r3, 10 + 1812: 07e7 br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA11) + 1814: 3957 cmpnei r1, 23 + 1816: 080a bt 0x182a // 182a + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)|0X00005000; //PA0.11 + 1818: 1361 lrw r3, 0x2000004c // 199c + 181a: 32f0 movi r2, 240 + 181c: 9320 ld.w r1, (r3, 0x0) + 181e: 9161 ld.w r3, (r1, 0x4) + 1820: 4248 lsli r2, r2, 8 + 1822: 68c9 andn r3, r2 + 1824: 3bac bseti r3, 12 + 1826: 3bae bseti r3, 14 + 1828: 07b9 br 0x179a // 179a + else if(IO_Num_X==IO_NUM_PA14) + 182a: 3958 cmpnei r1, 24 + 182c: 0bac bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)|0X04000000; //PA0.14 + 182e: 127c lrw r3, 0x2000004c // 199c + 1830: 32f0 movi r2, 240 + 1832: 9320 ld.w r1, (r3, 0x0) + 1834: 9161 ld.w r3, (r1, 0x4) + 1836: 4254 lsli r2, r2, 20 + 1838: 68c9 andn r3, r2 + 183a: 3bba bseti r3, 26 + 183c: 07af br 0x179a // 179a + else if(EPT_IO_X==EPT_IO_CHBY) + 183e: 3843 cmpnei r0, 3 + 1840: 0820 bt 0x1880 // 1880 + if(IO_Num_X==IO_NUM_PB04) + 1842: 3959 cmpnei r1, 25 + 1844: 080a bt 0x1858 // 1858 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00050000; //PB0.4 + 1846: 1277 lrw r3, 0x20000048 // 19a0 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF)|0X00050000; //PA0.4 + 1848: 9320 ld.w r1, (r3, 0x0) + 184a: 32f0 movi r2, 240 + 184c: 9160 ld.w r3, (r1, 0x0) + 184e: 424c lsli r2, r2, 12 + 1850: 68c9 andn r3, r2 + 1852: 3bb0 bseti r3, 16 + 1854: 3bb2 bseti r3, 18 + 1856: 07c5 br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA05) + 1858: 395a cmpnei r1, 26 + 185a: 0809 bt 0x186c // 186c + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)|0X00800000; //PA0.5 + 185c: 1270 lrw r3, 0x2000004c // 199c + 185e: 32f0 movi r2, 240 + 1860: 9320 ld.w r1, (r3, 0x0) + 1862: 9160 ld.w r3, (r1, 0x0) + 1864: 4250 lsli r2, r2, 16 + 1866: 68c9 andn r3, r2 + 1868: 3bb7 bseti r3, 23 + 186a: 07bb br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA08) + 186c: 395b cmpnei r1, 27 + 186e: 0b8b bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000005; //PA0.8 + 1870: 126b lrw r3, 0x2000004c // 199c + 1872: 310f movi r1, 15 + 1874: 9340 ld.w r2, (r3, 0x0) + 1876: 9261 ld.w r3, (r2, 0x4) + 1878: 68c5 andn r3, r1 + 187a: 3ba0 bseti r3, 0 + 187c: 3ba2 bseti r3, 2 + 187e: 0798 br 0x17ae // 17ae + else if(EPT_IO_X==EPT_IO_CHCX) + 1880: 3844 cmpnei r0, 4 + 1882: 0823 bt 0x18c8 // 18c8 + if(IO_Num_X==IO_NUM_PB05) + 1884: 3954 cmpnei r1, 20 + 1886: 0809 bt 0x1898 // 1898 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00400000; //PB0.5 + 1888: 1266 lrw r3, 0x20000048 // 19a0 + 188a: 32f0 movi r2, 240 + 188c: 9320 ld.w r1, (r3, 0x0) + 188e: 9160 ld.w r3, (r1, 0x0) + 1890: 4250 lsli r2, r2, 16 + 1892: 68c9 andn r3, r2 + 1894: 3bb6 bseti r3, 22 + 1896: 07a5 br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA03) + 1898: 395c cmpnei r1, 28 + 189a: 0803 bt 0x18a0 // 18a0 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF)|0X00005000; //PA0.3 + 189c: 1260 lrw r3, 0x2000004c // 199c + 189e: 078f br 0x17bc // 17bc + else if(IO_Num_X==IO_NUM_PB03) + 18a0: 3953 cmpnei r1, 19 + 18a2: 0809 bt 0x18b4 // 18b4 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00004000; //PB0.3 + 18a4: 117f lrw r3, 0x20000048 // 19a0 + 18a6: 32f0 movi r2, 240 + 18a8: 9320 ld.w r1, (r3, 0x0) + 18aa: 9160 ld.w r3, (r1, 0x0) + 18ac: 4248 lsli r2, r2, 8 + 18ae: 68c9 andn r3, r2 + 18b0: 3bae bseti r3, 14 + 18b2: 0797 br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PB00) + 18b4: 395d cmpnei r1, 29 + 18b6: 0b67 bt 0x1784 // 1784 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)|0X00000005; //PB0.0 + 18b8: 117a lrw r3, 0x20000048 // 19a0 + 18ba: 310f movi r1, 15 + 18bc: 9340 ld.w r2, (r3, 0x0) + 18be: 9260 ld.w r3, (r2, 0x0) + 18c0: 68c5 andn r3, r1 + 18c2: 3ba0 bseti r3, 0 + 18c4: 3ba2 bseti r3, 2 + 18c6: 075e br 0x1782 // 1782 + else if(EPT_IO_X==EPT_IO_CHCY) + 18c8: 3845 cmpnei r0, 5 + 18ca: 0825 bt 0x1914 // 1914 + if(IO_Num_X==IO_NUM_PB04) + 18cc: 3959 cmpnei r1, 25 + 18ce: 0809 bt 0x18e0 // 18e0 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00040000; //PB0.4 + 18d0: 1174 lrw r3, 0x20000048 // 19a0 + 18d2: 32f0 movi r2, 240 + 18d4: 9320 ld.w r1, (r3, 0x0) + 18d6: 9160 ld.w r3, (r1, 0x0) + 18d8: 424c lsli r2, r2, 12 + 18da: 68c9 andn r3, r2 + 18dc: 3bb2 bseti r3, 18 + 18de: 0781 br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA04) + 18e0: 395e cmpnei r1, 30 + 18e2: 0803 bt 0x18e8 // 18e8 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF)|0X00050000; //PA0.4 + 18e4: 116e lrw r3, 0x2000004c // 199c + 18e6: 07b1 br 0x1848 // 1848 + else if(IO_Num_X==IO_NUM_PA09) + 18e8: 395f cmpnei r1, 31 + 18ea: 0809 bt 0x18fc // 18fc + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)|0X00000070; //PA0.9 + 18ec: 116c lrw r3, 0x2000004c // 199c + 18ee: 31f0 movi r1, 240 + 18f0: 9340 ld.w r2, (r3, 0x0) + 18f2: 9261 ld.w r3, (r2, 0x4) + 18f4: 68c5 andn r3, r1 + 18f6: 3170 movi r1, 112 + 18f8: 6cc4 or r3, r1 + 18fa: 075a br 0x17ae // 17ae + else if(IO_Num_X==IO_NUM_PA013) + 18fc: 3320 movi r3, 32 + 18fe: 64c6 cmpne r1, r3 + 1900: 0b42 bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00500000; //PA0.13 + 1902: 1167 lrw r3, 0x2000004c // 199c + 1904: 32f0 movi r2, 240 + 1906: 9320 ld.w r1, (r3, 0x0) + 1908: 9161 ld.w r3, (r1, 0x4) + 190a: 4250 lsli r2, r2, 16 + 190c: 68c9 andn r3, r2 + 190e: 3bb4 bseti r3, 20 + 1910: 3bb6 bseti r3, 22 + 1912: 0744 br 0x179a // 179a + else if(EPT_IO_X==EPT_IO_CHD) + 1914: 3846 cmpnei r0, 6 + 1916: 0815 bt 0x1940 // 1940 + if(IO_Num_X==IO_NUM_PB03) + 1918: 3953 cmpnei r1, 19 + 191a: 080a bt 0x192e // 192e + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00006000; //PB0.3 + 191c: 1161 lrw r3, 0x20000048 // 19a0 + 191e: 32f0 movi r2, 240 + 1920: 9320 ld.w r1, (r3, 0x0) + 1922: 9160 ld.w r3, (r1, 0x0) + 1924: 4248 lsli r2, r2, 8 + 1926: 68c9 andn r3, r2 + 1928: 3bad bseti r3, 13 + 192a: 3bae bseti r3, 14 + 192c: 075a br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PA08) + 192e: 395b cmpnei r1, 27 + 1930: 0b2a bt 0x1784 // 1784 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000004; //PA0.8 + 1932: 107b lrw r3, 0x2000004c // 199c + 1934: 310f movi r1, 15 + 1936: 9340 ld.w r2, (r3, 0x0) + 1938: 9261 ld.w r3, (r2, 0x4) + 193a: 68c5 andn r3, r1 + 193c: 3ba2 bseti r3, 2 + 193e: 0738 br 0x17ae // 17ae + else if(EPT_IO_X==EPT_IO_EPI) + 1940: 3847 cmpnei r0, 7 + 1942: 0b21 bt 0x1784 // 1784 + if(IO_Num_X==IO_NUM_PA07) + 1944: 3950 cmpnei r1, 16 + 1946: 0809 bt 0x1958 // 1958 + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X50000000; //PA0.7 EPI0 + 1948: 1075 lrw r3, 0x2000004c // 199c + 194a: 9340 ld.w r2, (r3, 0x0) + 194c: 9260 ld.w r3, (r2, 0x0) + 194e: 4364 lsli r3, r3, 4 + 1950: 4b64 lsri r3, r3, 4 + 1952: 3bbc bseti r3, 28 + 1954: 3bbe bseti r3, 30 + 1956: 0716 br 0x1782 // 1782 + else if(IO_Num_X==IO_NUM_PA013) + 1958: 3320 movi r3, 32 + 195a: 64c6 cmpne r1, r3 + 195c: 0809 bt 0x196e // 196e + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00400000; //PA0.13 EPI1 + 195e: 1070 lrw r3, 0x2000004c // 199c + 1960: 32f0 movi r2, 240 + 1962: 9320 ld.w r1, (r3, 0x0) + 1964: 9161 ld.w r3, (r1, 0x4) + 1966: 4250 lsli r2, r2, 16 + 1968: 68c9 andn r3, r2 + 196a: 3bb6 bseti r3, 22 + 196c: 0717 br 0x179a // 179a + else if(IO_Num_X==IO_NUM_PB03) + 196e: 3953 cmpnei r1, 19 + 1970: 080b bt 0x1986 // 1986 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00007000; //PB0.3 EPI2 + 1972: 106c lrw r3, 0x20000048 // 19a0 + 1974: 32f0 movi r2, 240 + 1976: 9320 ld.w r1, (r3, 0x0) + 1978: 4248 lsli r2, r2, 8 + 197a: 9160 ld.w r3, (r1, 0x0) + 197c: 68c9 andn r3, r2 + 197e: 32e0 movi r2, 224 + 1980: 4247 lsli r2, r2, 7 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3 + 1982: 6cc8 or r3, r2 + 1984: 072e br 0x17e0 // 17e0 + else if(IO_Num_X==IO_NUM_PB02) + 1986: 3956 cmpnei r1, 22 + 1988: 0afe bt 0x1784 // 1784 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3 + 198a: 1066 lrw r3, 0x20000048 // 19a0 + 198c: 32f0 movi r2, 240 + 198e: 9320 ld.w r1, (r3, 0x0) + 1990: 4244 lsli r2, r2, 4 + 1992: 9160 ld.w r3, (r1, 0x0) + 1994: 68c9 andn r3, r2 + 1996: 32e0 movi r2, 224 + 1998: 4243 lsli r2, r2, 3 + 199a: 07f4 br 0x1982 // 1982 + 199c: 2000004c .long 0x2000004c + 19a0: 20000048 .long 0x20000048 + +Disassembly of section .text.EPT_PWM_Config: + +000019a4 : +//ReturnValue:NONE +/*************************************************************/ +//Fclk=Fpclk/(PSC+1) +void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X + , U16_T EPT_PSCR) +{ + 19a4: 14c3 push r4-r6 + 19a6: 6d8b mov r6, r2 + EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6)); + 19a8: 104b lrw r2, 0x20000020 // 19d4 + if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK) + 19aa: 3840 cmpnei r0, 0 + EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6)); + 19ac: 92a0 ld.w r5, (r2, 0x0) + 19ae: 9580 ld.w r4, (r5, 0x0) + 19b0: 32ff movi r2, 255 + 19b2: 6909 andn r4, r2 + 19b4: 3ca0 bseti r4, 0 + 19b6: 3ca1 bseti r4, 1 + 19b8: 6d00 or r4, r0 + 19ba: b580 st.w r4, (r5, 0x0) + if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK) + 19bc: 0802 bt 0x19c0 // 19c0 + { + EPT0->PSCR=EPT_PSCR; + 19be: b562 st.w r3, (r5, 0x8) + } + EPT0->CR=(EPT0->CR&0xfff8ffc0)|EPT_CNTMD_SELECTE_X|(0x1<<2)|(0x0<<3)|(0x0<<4)|EPT_OPM_SELECTE_X|(0X0<<16)|(0x1<<18); + 19c0: 9543 ld.w r2, (r5, 0xc) + 19c2: 1066 lrw r3, 0x7003f // 19d8 + 19c4: 688d andn r2, r3 + 19c6: 6c98 or r2, r6 + 19c8: 3aa2 bseti r2, 2 + 19ca: 3ab2 bseti r2, 18 + 19cc: 6c48 or r1, r2 + 19ce: b523 st.w r1, (r5, 0xc) +} + 19d0: 1483 pop r4-r6 + 19d2: 0000 bkpt + 19d4: 20000020 .long 0x20000020 + 19d8: 0007003f .long 0x0007003f + +Disassembly of section .text.EPT_PWMX_Output_Control: + +000019dc : + EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output , + EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output , + EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output , + EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output + ) +{ + 19dc: 14c4 push r4-r7 + 19de: 1425 subi r14, r14, 20 + 19e0: 9889 ld.w r4, (r14, 0x24) + 19e2: b880 st.w r4, (r14, 0x0) + 19e4: 988a ld.w r4, (r14, 0x28) + 19e6: b881 st.w r4, (r14, 0x4) + 19e8: 988b ld.w r4, (r14, 0x2c) + 19ea: b882 st.w r4, (r14, 0x8) + 19ec: 988c ld.w r4, (r14, 0x30) + 19ee: b883 st.w r4, (r14, 0xc) + if(EPT_PWMX_Selecte==EPT_PWMA) + 19f0: 3840 cmpnei r0, 0 +{ + 19f2: 988d ld.w r4, (r14, 0x34) + 19f4: b884 st.w r4, (r14, 0x10) + 19f6: 98ce ld.w r6, (r14, 0x38) + 19f8: 98ef ld.w r7, (r14, 0x3c) + 19fa: 98b0 ld.w r5, (r14, 0x40) + 19fc: 9891 ld.w r4, (r14, 0x44) + if(EPT_PWMX_Selecte==EPT_PWMA) + 19fe: 0816 bt 0x1a2a // 1a2a + { + EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a00: 6d14 or r4, r5 + 1a02: 6d1c or r4, r7 + 1a04: 98a4 ld.w r5, (r14, 0x10) + 1a06: 6d18 or r4, r6 + 1a08: 6d14 or r4, r5 + 1a0a: 98a3 ld.w r5, (r14, 0xc) + 1a0c: 6d14 or r4, r5 + 1a0e: 98a2 ld.w r5, (r14, 0x8) + 1a10: 6d14 or r4, r5 + 1a12: 98a1 ld.w r5, (r14, 0x4) + 1a14: 6d14 or r4, r5 + 1a16: 98a0 ld.w r5, (r14, 0x0) + 1a18: 6d14 or r4, r5 + 1a1a: 6cd0 or r3, r4 + EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a1c: 1105 lrw r0, 0x20000020 // 1ab0 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a1e: 6c8c or r2, r3 + EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a20: 9000 ld.w r0, (r0, 0x0) + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a22: 6c48 or r1, r2 + EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a24: b032 st.w r1, (r0, 0x48) + { + EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + } + +} + 1a26: 1405 addi r14, r14, 20 + 1a28: 1484 pop r4-r7 + else if(EPT_PWMX_Selecte==EPT_PWMB) + 1a2a: 3841 cmpnei r0, 1 + 1a2c: 0815 bt 0x1a56 // 1a56 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a2e: 6d14 or r4, r5 + 1a30: 6d1c or r4, r7 + 1a32: 98a4 ld.w r5, (r14, 0x10) + 1a34: 6d18 or r4, r6 + 1a36: 6d14 or r4, r5 + 1a38: 98a3 ld.w r5, (r14, 0xc) + 1a3a: 6d14 or r4, r5 + 1a3c: 98a2 ld.w r5, (r14, 0x8) + 1a3e: 6d14 or r4, r5 + 1a40: 98a1 ld.w r5, (r14, 0x4) + 1a42: 6d14 or r4, r5 + 1a44: 98a0 ld.w r5, (r14, 0x0) + 1a46: 6d14 or r4, r5 + 1a48: 6cd0 or r3, r4 + EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a4a: 101a lrw r0, 0x20000020 // 1ab0 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a4c: 6c8c or r2, r3 + EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a4e: 9000 ld.w r0, (r0, 0x0) + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a50: 6c48 or r1, r2 + EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a52: b033 st.w r1, (r0, 0x4c) + 1a54: 07e9 br 0x1a26 // 1a26 + else if(EPT_PWMX_Selecte==EPT_PWMC) + 1a56: 3842 cmpnei r0, 2 + 1a58: 0815 bt 0x1a82 // 1a82 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a5a: 6d14 or r4, r5 + 1a5c: 6d1c or r4, r7 + 1a5e: 98a4 ld.w r5, (r14, 0x10) + 1a60: 6d18 or r4, r6 + 1a62: 6d14 or r4, r5 + 1a64: 98a3 ld.w r5, (r14, 0xc) + 1a66: 6d14 or r4, r5 + 1a68: 98a2 ld.w r5, (r14, 0x8) + 1a6a: 6d14 or r4, r5 + 1a6c: 98a1 ld.w r5, (r14, 0x4) + 1a6e: 6d14 or r4, r5 + 1a70: 98a0 ld.w r5, (r14, 0x0) + 1a72: 6d14 or r4, r5 + 1a74: 6cd0 or r3, r4 + EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a76: 100f lrw r0, 0x20000020 // 1ab0 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a78: 6c8c or r2, r3 + EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a7a: 9000 ld.w r0, (r0, 0x0) + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a7c: 6c48 or r1, r2 + EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1a7e: b034 st.w r1, (r0, 0x50) + 1a80: 07d3 br 0x1a26 // 1a26 + else if(EPT_PWMX_Selecte==EPT_PWMD) + 1a82: 3843 cmpnei r0, 3 + 1a84: 0bd1 bt 0x1a26 // 1a26 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1a86: 6d14 or r4, r5 + 1a88: 6d1c or r4, r7 + 1a8a: 98a4 ld.w r5, (r14, 0x10) + 1a8c: 6d18 or r4, r6 + 1a8e: 6d14 or r4, r5 + 1a90: 98a3 ld.w r5, (r14, 0xc) + 1a92: 6d14 or r4, r5 + 1a94: 98a2 ld.w r5, (r14, 0x8) + 1a96: 6d14 or r4, r5 + 1a98: 98a1 ld.w r5, (r14, 0x4) + 1a9a: 6d14 or r4, r5 + 1a9c: 98a0 ld.w r5, (r14, 0x0) + 1a9e: 6d14 or r4, r5 + 1aa0: 6cd0 or r3, r4 + EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1aa2: 1004 lrw r0, 0x20000020 // 1ab0 + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1aa4: 6c8c or r2, r3 + EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1aa6: 9000 ld.w r0, (r0, 0x0) + EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output; + 1aa8: 6c48 or r1, r2 + EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output| + 1aaa: b035 st.w r1, (r0, 0x54) +} + 1aac: 07bd br 0x1a26 // 1a26 + 1aae: 0000 bkpt + 1ab0: 20000020 .long 0x20000020 + +Disassembly of section .text.EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config: + +00001ab4 : +//EPT_CMPB_Value:0~0xff +//EPT_CMPC_Value:0~0xff +//EPT_CMPD_Value:0~0xff +/*************************************************************/ +void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value) +{ + 1ab4: 14c2 push r4-r5 + EPT0->PRDR=EPT_PRDR_Value; + 1ab6: 1086 lrw r4, 0x20000020 // 1acc +{ + 1ab8: d8ae1004 ld.h r5, (r14, 0x8) + EPT0->PRDR=EPT_PRDR_Value; + 1abc: 9480 ld.w r4, (r4, 0x0) + 1abe: b409 st.w r0, (r4, 0x24) + EPT0->CMPA=EPT_CMPA_Value; + 1ac0: b42b st.w r1, (r4, 0x2c) + EPT0->CMPB=EPT_CMPB_Value; + 1ac2: b44c st.w r2, (r4, 0x30) + EPT0->CMPC=EPT_CMPC_Value; + 1ac4: b46d st.w r3, (r4, 0x34) + EPT0->CMPD=EPT_CMPD_Value; + 1ac6: b4ae st.w r5, (r4, 0x38) +} + 1ac8: 1482 pop r4-r5 + 1aca: 0000 bkpt + 1acc: 20000020 .long 0x20000020 + +Disassembly of section .text.ADC12_RESET_VALUE: + +00001ad0 : +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_RESET_VALUE(void) +{ + ADC0->ECR = ADC_ECR_RST; /**< ECR reset value */ + 1ad0: 1078 lrw r3, 0x20000050 // 1b30 + 1ad2: 3200 movi r2, 0 + 1ad4: 9360 ld.w r3, (r3, 0x0) + 1ad6: b340 st.w r2, (r3, 0x0) + ADC0->DCR = ADC_DCR_RST; /**< DCR reset value */ + 1ad8: b341 st.w r2, (r3, 0x4) + ADC0->PMSR = ADC_PMSR_RST; /**< PMSR reset value */ + 1ada: b342 st.w r2, (r3, 0x8) + //ADC0->CR = ADC_CR_RST; /**< CR reset value */ + ADC0->MR = ADC_MR_RST; /**< MR reset value */ + 1adc: b345 st.w r2, (r3, 0x14) + ADC0->CSR = ADC_CSR_RST; /**< CSR reset value */ + 1ade: b347 st.w r2, (r3, 0x1c) + ADC0->SR = ADC_SR_RST; /**< SR reset value */ + 1ae0: b348 st.w r2, (r3, 0x20) + ADC0->IER = ADC_IER_RST; /**< IER reset value */ + 1ae2: b349 st.w r2, (r3, 0x24) + ADC0->IDR = ADC_IDR_RST; /**< IDR reset value */ + 1ae4: b34a st.w r2, (r3, 0x28) + ADC0->IMR = ADC_IMR_RST; /**< IMR reset value */ + 1ae6: b34b st.w r2, (r3, 0x2c) + ADC0->SEQ[0]= ADC_SEQx_RST; /**< SEQ0 reset value */ + 1ae8: b34c st.w r2, (r3, 0x30) + ADC0->SEQ[1]= ADC_SEQx_RST; /**< SEQ1 reset value */ + 1aea: b34d st.w r2, (r3, 0x34) + ADC0->SEQ[2]= ADC_SEQx_RST; /**< SEQ2 reset value */ + 1aec: b34e st.w r2, (r3, 0x38) + ADC0->SEQ[3]= ADC_SEQx_RST; /**< SEQ3 reset value */ + 1aee: b34f st.w r2, (r3, 0x3c) + ADC0->SEQ[4]= ADC_SEQx_RST; /**< SEQ4 reset value */ + 1af0: b350 st.w r2, (r3, 0x40) + ADC0->SEQ[5]= ADC_SEQx_RST; /**< SEQ5 reset value */ + 1af2: b351 st.w r2, (r3, 0x44) + ADC0->SEQ[6]= ADC_SEQx_RST; /**< SEQ6 reset value */ + 1af4: b352 st.w r2, (r3, 0x48) + ADC0->SEQ[7]= ADC_SEQx_RST; /**< SEQ7 reset value */ + 1af6: b353 st.w r2, (r3, 0x4c) + ADC0->SEQ[8]= ADC_SEQx_RST; /**< SEQ8 reset value */ + 1af8: b354 st.w r2, (r3, 0x50) + ADC0->SEQ[9]= ADC_SEQx_RST; /**< SEQ9 reset value */ + 1afa: b355 st.w r2, (r3, 0x54) + ADC0->SEQ[10]= ADC_SEQx_RST; /**< SEQ10 reset value */ + 1afc: b356 st.w r2, (r3, 0x58) + ADC0->SEQ[11]= ADC_SEQx_RST; /**< SEQ11 reset value */ + 1afe: b357 st.w r2, (r3, 0x5c) + ADC0->SEQ[12]= ADC_SEQx_RST; /**< SEQ12 reset value */ + 1b00: b358 st.w r2, (r3, 0x60) + ADC0->SEQ[13]= ADC_SEQx_RST; /**< SEQ13 reset value */ + 1b02: b359 st.w r2, (r3, 0x64) + ADC0->SEQ[14]= ADC_SEQx_RST; /**< SEQ14 reset value */ + 1b04: b35a st.w r2, (r3, 0x68) + ADC0->SEQ[15]= ADC_SEQx_RST; /**< SEQ15 reset value */ + 1b06: b35b st.w r2, (r3, 0x6c) + ADC0->DR[0] = ADC_DR_RST; /**< DR reset value */ + 1b08: 23ff addi r3, 256 + 1b0a: b340 st.w r2, (r3, 0x0) + ADC0->DR[1] = ADC_DR_RST; /**< DR reset value */ + 1b0c: b341 st.w r2, (r3, 0x4) + ADC0->DR[2] = ADC_DR_RST; /**< DR reset value */ + 1b0e: b342 st.w r2, (r3, 0x8) + ADC0->DR[3] = ADC_DR_RST; /**< DR reset value */ + 1b10: b343 st.w r2, (r3, 0xc) + ADC0->DR[4] = ADC_DR_RST; /**< DR reset value */ + 1b12: b344 st.w r2, (r3, 0x10) + ADC0->DR[5] = ADC_DR_RST; /**< DR reset value */ + 1b14: b345 st.w r2, (r3, 0x14) + ADC0->DR[6] = ADC_DR_RST; /**< DR reset value */ + 1b16: b346 st.w r2, (r3, 0x18) + ADC0->DR[7] = ADC_DR_RST; /**< DR reset value */ + 1b18: b347 st.w r2, (r3, 0x1c) + ADC0->DR[8] = ADC_DR_RST; /**< DR reset value */ + 1b1a: b348 st.w r2, (r3, 0x20) + ADC0->DR[9] = ADC_DR_RST; /**< DR reset value */ + 1b1c: b349 st.w r2, (r3, 0x24) + ADC0->DR[10] = ADC_DR_RST; /**< DR reset value */ + 1b1e: b34a st.w r2, (r3, 0x28) + ADC0->DR[11] = ADC_DR_RST; /**< DR reset value */ + 1b20: b34b st.w r2, (r3, 0x2c) + ADC0->DR[12] = ADC_DR_RST; /**< DR reset value */ + 1b22: b34c st.w r2, (r3, 0x30) + ADC0->DR[13] = ADC_DR_RST; /**< DR reset value */ + 1b24: b34d st.w r2, (r3, 0x34) + ADC0->DR[14] = ADC_DR_RST; /**< DR reset value */ + 1b26: b34e st.w r2, (r3, 0x38) + ADC0->DR[15] = ADC_DR_RST; /**< DR reset value */ + 1b28: b34f st.w r2, (r3, 0x3c) + ADC0->CMP0 = ADC_CMP0_RST; /**< CMP1 reset value */ + 1b2a: b350 st.w r2, (r3, 0x40) + ADC0->CMP1 = ADC_CMP1_RST; /**< CMP2 reset value */ + 1b2c: b351 st.w r2, (r3, 0x44) +} + 1b2e: 783c jmp r15 + 1b30: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_Control: + +00001b34 : +//ReturnValue:NONE +/*************************************************************/ + //control:ADC enable/disable ,start/stop,swrst +void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x ) +{ + ADC0->CR |= ADC12_Control_x; // + 1b34: 1063 lrw r3, 0x20000050 // 1b40 + 1b36: 9340 ld.w r2, (r3, 0x0) + 1b38: 9264 ld.w r3, (r2, 0x10) + 1b3a: 6c0c or r0, r3 + 1b3c: b204 st.w r0, (r2, 0x10) +} + 1b3e: 783c jmp r15 + 1b40: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_CMD.part.0: + +00001b44 : +//ADC12 ENABLE +//EntryParameter:NewState +//NewState:ENABLE , DISABLE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_CMD(FunctionalStatus NewState) + 1b44: 14d0 push r15 +{ + if (NewState != DISABLE) + { + ADC12_Control(ADC12_ADCEN); //ADC12 ENABLE + 1b46: 3002 movi r0, 2 + 1b48: e3fffff6 bsr 0x1b34 // 1b34 + while(!(ADC0->SR &ADC12_ADCENS)); + 1b4c: 1065 lrw r3, 0x20000050 // 1b60 + 1b4e: 3280 movi r2, 128 + 1b50: 9320 ld.w r1, (r3, 0x0) + 1b52: 4241 lsli r2, r2, 1 + 1b54: 9168 ld.w r3, (r1, 0x20) + 1b56: 68c8 and r3, r2 + 1b58: 3b40 cmpnei r3, 0 + 1b5a: 0ffd bf 0x1b54 // 1b54 + else + { + ADC12_Control(ADC12_ADCDIS); //ADC12 DISABLE + while(ADC0->SR&ADC12_ADCENS); + } +} + 1b5c: 1490 pop r15 + 1b5e: 0000 bkpt + 1b60: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_CLK_CMD: + +00001b64 : + if (NewState != DISABLE) + 1b64: 3940 cmpnei r1, 0 + 1b66: 106a lrw r3, 0x20000050 // 1b8c + ADC0->ECR |= ADC_CLK_CMD; //ENABLE + 1b68: 9340 ld.w r2, (r3, 0x0) + if (NewState != DISABLE) + 1b6a: 0c09 bf 0x1b7c // 1b7c + ADC0->ECR |= ADC_CLK_CMD; //ENABLE + 1b6c: 9260 ld.w r3, (r2, 0x0) + 1b6e: 6cc0 or r3, r0 + 1b70: b260 st.w r3, (r2, 0x0) + while(!(ADC0->PMSR&ADC_CLK_CMD)); + 1b72: 9262 ld.w r3, (r2, 0x8) + 1b74: 68c0 and r3, r0 + 1b76: 3b40 cmpnei r3, 0 + 1b78: 0ffd bf 0x1b72 // 1b72 +} + 1b7a: 783c jmp r15 + ADC0->DCR |= ADC_CLK_CMD; //DISABLE + 1b7c: 9261 ld.w r3, (r2, 0x4) + 1b7e: 6cc0 or r3, r0 + 1b80: b261 st.w r3, (r2, 0x4) + while(ADC0->PMSR&ADC_CLK_CMD); + 1b82: 9262 ld.w r3, (r2, 0x8) + 1b84: 68c0 and r3, r0 + 1b86: 3b40 cmpnei r3, 0 + 1b88: 0bfd bt 0x1b82 // 1b82 + 1b8a: 07f8 br 0x1b7a // 1b7a + 1b8c: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_Software_Reset: + +00001b90 : +{ + 1b90: 14d0 push r15 + ADC12_Control(ADC12_SWRST); + 1b92: 3001 movi r0, 1 + 1b94: e3ffffd0 bsr 0x1b34 // 1b34 +} + 1b98: 1490 pop r15 + +Disassembly of section .text.ADC12_CMD: + +00001b9c : +{ + 1b9c: 14d0 push r15 + if (NewState != DISABLE) + 1b9e: 3840 cmpnei r0, 0 + 1ba0: 0c04 bf 0x1ba8 // 1ba8 + 1ba2: e3ffffd1 bsr 0x1b44 // 1b44 +} + 1ba6: 1490 pop r15 + ADC12_Control(ADC12_ADCDIS); //ADC12 DISABLE + 1ba8: 3004 movi r0, 4 + 1baa: e3ffffc5 bsr 0x1b34 // 1b34 + while(ADC0->SR&ADC12_ADCENS); + 1bae: 1065 lrw r3, 0x20000050 // 1bc0 + 1bb0: 3280 movi r2, 128 + 1bb2: 9320 ld.w r1, (r3, 0x0) + 1bb4: 4241 lsli r2, r2, 1 + 1bb6: 9168 ld.w r3, (r1, 0x20) + 1bb8: 68c8 and r3, r2 + 1bba: 3b40 cmpnei r3, 0 + 1bbc: 0bfd bt 0x1bb6 // 1bb6 + 1bbe: 07f4 br 0x1ba6 // 1ba6 + 1bc0: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_ready_wait: + +00001bc4 : +//EntryParameter:NONE +//ReturnValue:ADC12 READ FLAG +/*************************************************************/ +void ADC12_ready_wait(void) +{ + while(!(ADC0->SR&ADC12_READY)); // Waiting for ADC0 Ready + 1bc4: 1064 lrw r3, 0x20000050 // 1bd4 + 1bc6: 3202 movi r2, 2 + 1bc8: 9320 ld.w r1, (r3, 0x0) + 1bca: 9168 ld.w r3, (r1, 0x20) + 1bcc: 68c8 and r3, r2 + 1bce: 3b40 cmpnei r3, 0 + 1bd0: 0ffd bf 0x1bca // 1bca +} + 1bd2: 783c jmp r15 + 1bd4: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_SEQEND_wait: + +00001bd8 : +//EntryParameter:NONE +//ReturnValue:ADC12 EOC +/*************************************************************/ +void ADC12_SEQEND_wait(U8_T val) +{ + while(!(ADC0->SR & (0x01ul << (16+val)))); // EOC wait + 1bd8: 200f addi r0, 16 + 1bda: 1065 lrw r3, 0x20000050 // 1bec + 1bdc: 3201 movi r2, 1 + 1bde: 9320 ld.w r1, (r3, 0x0) + 1be0: 7080 lsl r2, r0 + 1be2: 9168 ld.w r3, (r1, 0x20) + 1be4: 68c8 and r3, r2 + 1be6: 3b40 cmpnei r3, 0 + 1be8: 0ffd bf 0x1be2 // 1be2 +} + 1bea: 783c jmp r15 + 1bec: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_DATA_OUPUT: + +00001bf0 : +//EntryParameter:NONE +//ReturnValue:ADC12 DR +/*************************************************************/ +U16_T ADC12_DATA_OUPUT(U16_T Data_index ) +{ + return(ADC0->DR[Data_index]); + 1bf0: 203f addi r0, 64 + 1bf2: 1064 lrw r3, 0x20000050 // 1c00 + 1bf4: 4002 lsli r0, r0, 2 + 1bf6: 9360 ld.w r3, (r3, 0x0) + 1bf8: 600c addu r0, r3 + 1bfa: 9000 ld.w r0, (r0, 0x0) + 1bfc: 7401 zexth r0, r0 +} + 1bfe: 783c jmp r15 + 1c00: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_Configure_Mode: + +00001c04 : + //10BIT or 12BIT adc ; + //ADC12_BIT_SELECTED:ADC12_12BIT/ADC12_10BIT; + //ADC12_ConverMode:One_shot_mode/Continuous_mode; + //adc date output=last number of Conversions; +void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver ) +{ + 1c04: 14d4 push r4-r7, r15 + 1c06: 1422 subi r14, r14, 8 + 1c08: 1c08 addi r4, r14, 32 + 1c0a: 84a0 ld.b r5, (r4, 0x0) + ADC0->MR=ADC12_DIV|((NumConver-1)<<10); + 1c0c: 2d00 subi r5, 1 +{ + 1c0e: 6dc3 mov r7, r0 + ADC0->MR=ADC12_DIV|((NumConver-1)<<10); + 1c10: 10db lrw r6, 0x20000050 // 1c7c +{ + 1c12: d80e001c ld.b r0, (r14, 0x1c) + ADC0->MR=ADC12_DIV|((NumConver-1)<<10); + 1c16: 45aa lsli r5, r5, 10 + 1c18: 9680 ld.w r4, (r6, 0x0) + 1c1a: 6d40 or r5, r0 + if(ADC12_ConverMode==One_shot_mode) + 1c1c: 3940 cmpnei r1, 0 + ADC0->MR=ADC12_DIV|((NumConver-1)<<10); + 1c1e: b4a5 st.w r5, (r4, 0x14) + if(ADC12_ConverMode==One_shot_mode) + 1c20: 081c bt 0x1c58 // 1c58 + { + ADC0->MR&=~CONTCV; //one short mode + 1c22: 9425 ld.w r1, (r4, 0x14) + 1c24: 4121 lsli r1, r1, 1 + 1c26: 4921 lsri r1, r1, 1 + while(ADC0->SR&ADC12_CTCVS); + 1c28: 3080 movi r0, 128 + ADC0->MR&=~CONTCV; //one short mode + 1c2a: b425 st.w r1, (r4, 0x14) + while(ADC0->SR&ADC12_CTCVS); + 1c2c: 4002 lsli r0, r0, 2 + 1c2e: 9428 ld.w r1, (r4, 0x20) + 1c30: 6840 and r1, r0 + 1c32: 3940 cmpnei r1, 0 + 1c34: 0bfd bt 0x1c2e // 1c2e + 1c36: b861 st.w r3, (r14, 0x4) + 1c38: b840 st.w r2, (r14, 0x0) + 1c3a: e3ffff85 bsr 0x1b44 // 1b44 + { + ADC0->MR|=CONTCV; //Continuous mode + while(!(ADC0->SR&ADC12_CTCVS)); + } + ADC12_CMD(ENABLE); //ADC0 enable + if(ADC12_BIT_SELECTED) + 1c3e: 3f40 cmpnei r7, 0 + 1c40: 9840 ld.w r2, (r14, 0x0) + 1c42: 9861 ld.w r3, (r14, 0x4) + 1c44: 0c16 bf 0x1c70 // 1c70 + { + ADC0->CR|=ADC12_10BITor12BIT; + 1c46: 9600 ld.w r0, (r6, 0x0) + 1c48: 9024 ld.w r1, (r0, 0x10) + 1c4a: 39bf bseti r1, 31 + } + else + { + ADC0->CR&=~ADC12_10BITor12BIT; + 1c4c: b024 st.w r1, (r0, 0x10) + } + //ADC0->CR|=ADC12_VREF_VDD | ADC12_FVR_DIS; + ADC0->PRI=ADC12_PRI; + 1c4e: 9620 ld.w r1, (r6, 0x0) + 1c50: b15c st.w r2, (r1, 0x70) + ADC0->SHR=adc12_SHR; //adc Sampling & Holding cycles + 1c52: b166 st.w r3, (r1, 0x18) +} + 1c54: 1402 addi r14, r14, 8 + 1c56: 1494 pop r4-r7, r15 + else if(ADC12_ConverMode==Continuous_mode) + 1c58: 3941 cmpnei r1, 1 + 1c5a: 0bee bt 0x1c36 // 1c36 + ADC0->MR|=CONTCV; //Continuous mode + 1c5c: 9425 ld.w r1, (r4, 0x14) + 1c5e: 39bf bseti r1, 31 + while(!(ADC0->SR&ADC12_CTCVS)); + 1c60: 3080 movi r0, 128 + ADC0->MR|=CONTCV; //Continuous mode + 1c62: b425 st.w r1, (r4, 0x14) + while(!(ADC0->SR&ADC12_CTCVS)); + 1c64: 4002 lsli r0, r0, 2 + 1c66: 9428 ld.w r1, (r4, 0x20) + 1c68: 6840 and r1, r0 + 1c6a: 3940 cmpnei r1, 0 + 1c6c: 0ffd bf 0x1c66 // 1c66 + 1c6e: 07e4 br 0x1c36 // 1c36 + ADC0->CR&=~ADC12_10BITor12BIT; + 1c70: 9600 ld.w r0, (r6, 0x0) + 1c72: 9024 ld.w r1, (r0, 0x10) + 1c74: 4121 lsli r1, r1, 1 + 1c76: 4921 lsri r1, r1, 1 + 1c78: 07ea br 0x1c4c // 1c4c + 1c7a: 0000 bkpt + 1c7c: 20000050 .long 0x20000050 + +Disassembly of section .text.ADC12_Configure_VREF_Selecte: + +00001c80 : +//EntryParameter:NONE +//ReturnValue:None +/*************************************************************/ +void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X ) +{ + if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_VSS) + 1c80: 3840 cmpnei r0, 0 + 1c82: 0808 bt 0x1c92 // 1c92 + { + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x00<<6); + 1c84: 127c lrw r3, 0x20000050 // 1df4 + 1c86: 123d lrw r1, 0x103c0 // 1df8 + 1c88: 9340 ld.w r2, (r3, 0x0) + 1c8a: 9264 ld.w r3, (r2, 0x10) + 1c8c: 68c5 andn r3, r1 + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0B<<6)|(0X01<<24)|(0X01<<25); + } + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_EXIT) + { + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17); + 1c8e: b264 st.w r3, (r2, 0x10) + } +} + 1c90: 783c jmp r15 + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_VSS) + 1c92: 3841 cmpnei r0, 1 + 1c94: 0810 bt 0x1cb4 // 1cb4 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1c96: 127a lrw r3, 0x2000004c // 1dfc + 1c98: 32f0 movi r2, 240 + 1c9a: 9320 ld.w r1, (r3, 0x0) + 1c9c: 9160 ld.w r3, (r1, 0x0) + 1c9e: 4244 lsli r2, r2, 4 + 1ca0: 68c9 andn r3, r2 + 1ca2: 3bab bseti r3, 11 + 1ca4: b160 st.w r3, (r1, 0x0) + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x01<<6); + 1ca6: 1235 lrw r1, 0x103c0 // 1df8 + 1ca8: 1273 lrw r3, 0x20000050 // 1df4 + 1caa: 9340 ld.w r2, (r3, 0x0) + 1cac: 9264 ld.w r3, (r2, 0x10) + 1cae: 68c5 andn r3, r1 + 1cb0: 3ba6 bseti r3, 6 + 1cb2: 07ee br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_VSS) + 1cb4: 3842 cmpnei r0, 2 + 1cb6: 0811 bt 0x1cd8 // 1cd8 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1cb8: 1271 lrw r3, 0x2000004c // 1dfc + 1cba: 32f0 movi r2, 240 + 1cbc: 9320 ld.w r1, (r3, 0x0) + 1cbe: 9160 ld.w r3, (r1, 0x0) + 1cc0: 4244 lsli r2, r2, 4 + 1cc2: 68c9 andn r3, r2 + 1cc4: 3bab bseti r3, 11 + 1cc6: b160 st.w r3, (r1, 0x0) + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x02<<6)|(0X01<<24)|(0X00<<25); + 1cc8: 122e lrw r1, 0x30103c0 // 1e00 + 1cca: 126b lrw r3, 0x20000050 // 1df4 + 1ccc: 9340 ld.w r2, (r3, 0x0) + 1cce: 9264 ld.w r3, (r2, 0x10) + 1cd0: 68c5 andn r3, r1 + 1cd2: 3ba7 bseti r3, 7 + 1cd4: 3bb8 bseti r3, 24 + 1cd6: 07dc br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_VSS) + 1cd8: 3843 cmpnei r0, 3 + 1cda: 0811 bt 0x1cfc // 1cfc + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1cdc: 1268 lrw r3, 0x2000004c // 1dfc + 1cde: 32f0 movi r2, 240 + 1ce0: 9320 ld.w r1, (r3, 0x0) + 1ce2: 9160 ld.w r3, (r1, 0x0) + 1ce4: 4244 lsli r2, r2, 4 + 1ce6: 68c9 andn r3, r2 + 1ce8: 3bab bseti r3, 11 + 1cea: b160 st.w r3, (r1, 0x0) + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x03<<6)|(0X01<<24)|(0X01<<25); + 1cec: 1225 lrw r1, 0x30103c0 // 1e00 + 1cee: 1262 lrw r3, 0x20000050 // 1df4 + 1cf0: 9340 ld.w r2, (r3, 0x0) + 1cf2: 9264 ld.w r3, (r2, 0x10) + 1cf4: 68c5 andn r3, r1 + 1cf6: 1224 lrw r1, 0x30000c0 // 1e04 + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17); + 1cf8: 6cc4 or r3, r1 + 1cfa: 07ca br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_VSS) + 1cfc: 3845 cmpnei r0, 5 + 1cfe: 0809 bt 0x1d10 // 1d10 + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x04<<6)|(0X00<<16)|(0X02<<17); + 1d00: 117d lrw r3, 0x20000050 // 1df4 + 1d02: 1222 lrw r1, 0x503c0 // 1e08 + 1d04: 9340 ld.w r2, (r3, 0x0) + 1d06: 9264 ld.w r3, (r2, 0x10) + 1d08: 68c5 andn r3, r1 + 1d0a: 3ba8 bseti r3, 8 + 1d0c: 3bb2 bseti r3, 18 + 1d0e: 07c0 br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_EXIT) + 1d10: 3846 cmpnei r0, 6 + 1d12: 0812 bt 0x1d36 // 1d36 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + 1d14: 117a lrw r3, 0x2000004c // 1dfc + 1d16: 32f0 movi r2, 240 + 1d18: 9320 ld.w r1, (r3, 0x0) + 1d1a: 9160 ld.w r3, (r1, 0x0) + 1d1c: 4248 lsli r2, r2, 8 + 1d1e: 68c9 andn r3, r2 + 1d20: 32b0 movi r2, 176 + 1d22: 4248 lsli r2, r2, 8 + 1d24: 6cc8 or r3, r2 + 1d26: b160 st.w r3, (r1, 0x0) + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x08<<6); + 1d28: 1134 lrw r1, 0x103c0 // 1df8 + 1d2a: 1173 lrw r3, 0x20000050 // 1df4 + 1d2c: 9340 ld.w r2, (r3, 0x0) + 1d2e: 9264 ld.w r3, (r2, 0x10) + 1d30: 68c5 andn r3, r1 + 1d32: 3ba9 bseti r3, 9 + 1d34: 07ad br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_EXIT) + 1d36: 3847 cmpnei r0, 7 + 1d38: 0819 bt 0x1d6a // 1d6a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + 1d3a: 1171 lrw r3, 0x2000004c // 1dfc + 1d3c: 31f0 movi r1, 240 + 1d3e: 9340 ld.w r2, (r3, 0x0) + 1d40: 9260 ld.w r3, (r2, 0x0) + 1d42: 4128 lsli r1, r1, 8 + 1d44: 68c5 andn r3, r1 + 1d46: 31b0 movi r1, 176 + 1d48: 4128 lsli r1, r1, 8 + 1d4a: 6cc4 or r3, r1 + 1d4c: b260 st.w r3, (r2, 0x0) + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1d4e: 31f0 movi r1, 240 + 1d50: 9260 ld.w r3, (r2, 0x0) + 1d52: 4124 lsli r1, r1, 4 + 1d54: 68c5 andn r3, r1 + 1d56: 3bab bseti r3, 11 + 1d58: b260 st.w r3, (r2, 0x0) + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x09<<6); + 1d5a: 1128 lrw r1, 0x103c0 // 1df8 + 1d5c: 1166 lrw r3, 0x20000050 // 1df4 + 1d5e: 9340 ld.w r2, (r3, 0x0) + 1d60: 9264 ld.w r3, (r2, 0x10) + 1d62: 68c5 andn r3, r1 + 1d64: 3ba6 bseti r3, 6 + 1d66: 3ba9 bseti r3, 9 + 1d68: 0793 br 0x1c8e // 1c8e + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_EXIT) + 1d6a: 3848 cmpnei r0, 8 + 1d6c: 0818 bt 0x1d9c // 1d9c + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + 1d6e: 1164 lrw r3, 0x2000004c // 1dfc + 1d70: 31f0 movi r1, 240 + 1d72: 9340 ld.w r2, (r3, 0x0) + 1d74: 9260 ld.w r3, (r2, 0x0) + 1d76: 4128 lsli r1, r1, 8 + 1d78: 68c5 andn r3, r1 + 1d7a: 31b0 movi r1, 176 + 1d7c: 4128 lsli r1, r1, 8 + 1d7e: 6cc4 or r3, r1 + 1d80: b260 st.w r3, (r2, 0x0) + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1d82: 31f0 movi r1, 240 + 1d84: 9260 ld.w r3, (r2, 0x0) + 1d86: 4124 lsli r1, r1, 4 + 1d88: 68c5 andn r3, r1 + 1d8a: 3bab bseti r3, 11 + 1d8c: b260 st.w r3, (r2, 0x0) + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0A<<6)|(0X01<<24)|(0X00<<25); + 1d8e: 103d lrw r1, 0x30103c0 // 1e00 + 1d90: 1079 lrw r3, 0x20000050 // 1df4 + 1d92: 9340 ld.w r2, (r3, 0x0) + 1d94: 9264 ld.w r3, (r2, 0x10) + 1d96: 68c5 andn r3, r1 + 1d98: 103d lrw r1, 0x1000280 // 1e0c + 1d9a: 07af br 0x1cf8 // 1cf8 + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_EXIT) + 1d9c: 3849 cmpnei r0, 9 + 1d9e: 0818 bt 0x1dce // 1dce + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + 1da0: 1077 lrw r3, 0x2000004c // 1dfc + 1da2: 31f0 movi r1, 240 + 1da4: 9340 ld.w r2, (r3, 0x0) + 1da6: 9260 ld.w r3, (r2, 0x0) + 1da8: 4128 lsli r1, r1, 8 + 1daa: 68c5 andn r3, r1 + 1dac: 31b0 movi r1, 176 + 1dae: 4128 lsli r1, r1, 8 + 1db0: 6cc4 or r3, r1 + 1db2: b260 st.w r3, (r2, 0x0) + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800; + 1db4: 31f0 movi r1, 240 + 1db6: 9260 ld.w r3, (r2, 0x0) + 1db8: 4124 lsli r1, r1, 4 + 1dba: 68c5 andn r3, r1 + 1dbc: 3bab bseti r3, 11 + 1dbe: b260 st.w r3, (r2, 0x0) + ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0B<<6)|(0X01<<24)|(0X01<<25); + 1dc0: 1030 lrw r1, 0x30103c0 // 1e00 + 1dc2: 106d lrw r3, 0x20000050 // 1df4 + 1dc4: 9340 ld.w r2, (r3, 0x0) + 1dc6: 9264 ld.w r3, (r2, 0x10) + 1dc8: 68c5 andn r3, r1 + 1dca: 1032 lrw r1, 0x30002c0 // 1e10 + 1dcc: 0796 br 0x1cf8 // 1cf8 + else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_EXIT) + 1dce: 384b cmpnei r0, 11 + 1dd0: 0b60 bt 0x1c90 // 1c90 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000; + 1dd2: 106b lrw r3, 0x2000004c // 1dfc + 1dd4: 32f0 movi r2, 240 + 1dd6: 9320 ld.w r1, (r3, 0x0) + 1dd8: 9160 ld.w r3, (r1, 0x0) + 1dda: 4248 lsli r2, r2, 8 + 1ddc: 68c9 andn r3, r2 + 1dde: 32b0 movi r2, 176 + 1de0: 4248 lsli r2, r2, 8 + 1de2: 6cc8 or r3, r2 + 1de4: b160 st.w r3, (r1, 0x0) + ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17); + 1de6: 1029 lrw r1, 0x503c0 // 1e08 + 1de8: 1063 lrw r3, 0x20000050 // 1df4 + 1dea: 9340 ld.w r2, (r3, 0x0) + 1dec: 9264 ld.w r3, (r2, 0x10) + 1dee: 68c5 andn r3, r1 + 1df0: 1029 lrw r1, 0x40300 // 1e14 + 1df2: 0783 br 0x1cf8 // 1cf8 + 1df4: 20000050 .long 0x20000050 + 1df8: 000103c0 .long 0x000103c0 + 1dfc: 2000004c .long 0x2000004c + 1e00: 030103c0 .long 0x030103c0 + 1e04: 030000c0 .long 0x030000c0 + 1e08: 000503c0 .long 0x000503c0 + 1e0c: 01000280 .long 0x01000280 + 1e10: 030002c0 .long 0x030002c0 + 1e14: 00040300 .long 0x00040300 + +Disassembly of section .text.ADC12_ConversionChannel_Config: + +00001e18 : +//ADC12_ADCINX:ADC12_ADCIN0~ADC12_ADCIN17,ADC12_INTVREF,ADC12_DIV4_VDD,ADC12_VSS +//ReturnValue:NONE +/*************************************************************/ +void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX , + ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx) +{ + 1e18: 14d4 push r4-r7, r15 + 1e1a: 1421 subi r14, r14, 4 + 1e1c: b840 st.w r2, (r14, 0x0) + 1e1e: 6d43 mov r5, r0 + U8_T i; + for(i=0;i<15;i++) + { + ADC0->SEQ[i] &=~(0x01<<7); + 1e20: 125b lrw r2, 0x20000050 // 1f8c + 1e22: 92c0 ld.w r6, (r2, 0x0) + 1e24: 3200 movi r2, 0 + 1e26: 4202 lsli r0, r2, 2 + 1e28: 6018 addu r0, r6 + 1e2a: 908c ld.w r4, (r0, 0x30) + 1e2c: 2200 addi r2, 1 + 1e2e: 3c87 bclri r4, 7 + for(i=0;i<15;i++) + 1e30: 3a4f cmpnei r2, 15 + ADC0->SEQ[i] &=~(0x01<<7); + 1e32: b08c st.w r4, (r0, 0x30) + for(i=0;i<15;i++) + 1e34: 0bf9 bt 0x1e26 // 1e26 + } + switch(ADC12_ADCINX) + 1e36: 3d0f cmphsi r5, 16 + 1e38: 0825 bt 0x1e82 // 1e82 + 1e3a: 6c17 mov r0, r5 + 1e3c: 1255 lrw r2, 0x2000004c // 1f90 + 1e3e: 1296 lrw r4, 0x20000048 // 1f94 + 1e40: e3fff1ba bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 1e44: 322c1408 .long 0x322c1408 + 1e48: 4d474039 .long 0x4d474039 + 1e4c: 756d6559 .long 0x756d6559 + 1e50: 9990877e .long 0x9990877e + { + case 0: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC0 PB0.1 + 1e54: 9240 ld.w r2, (r2, 0x0) + 1e56: 9200 ld.w r0, (r2, 0x0) + 1e58: b200 st.w r0, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + 1e5a: 9201 ld.w r0, (r2, 0x4) + 1e5c: b201 st.w r0, (r2, 0x4) + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0x00000010; + 1e5e: 9400 ld.w r0, (r4, 0x0) + 1e60: 9040 ld.w r2, (r0, 0x0) + 1e62: 34f0 movi r4, 240 + 1e64: 6891 andn r2, r4 + 1e66: 3aa4 bseti r2, 4 + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + break; + case 15: + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC15 PB0.0 + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000001; + 1e68: b040 st.w r2, (r0, 0x0) + break; + 1e6a: 040c br 0x1e82 // 1e82 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000001; //ADC1 PA0.0 + 1e6c: 9200 ld.w r0, (r2, 0x0) + 1e6e: 9040 ld.w r2, (r0, 0x0) + 1e70: 370f movi r7, 15 + 1e72: 689d andn r2, r7 + 1e74: 3aa0 bseti r2, 0 + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x10000000; //ADC6 PA0.7 + 1e76: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + 1e78: 9041 ld.w r2, (r0, 0x4) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00100000; + 1e7a: b041 st.w r2, (r0, 0x4) + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000; + 1e7c: 9440 ld.w r2, (r4, 0x0) + 1e7e: 9200 ld.w r0, (r2, 0x0) + 1e80: b200 st.w r0, (r2, 0x0) + 1e82: 4362 lsli r3, r3, 2 + 1e84: 618c addu r6, r3 + //case 27: break; + case 0x1Cul: break; + case 0x1Dul: break; + case 0x1Eul: break; + } + ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0; + 1e86: 966c ld.w r3, (r6, 0x30) + 1e88: 3300 movi r3, 0 + 1e8a: b66c st.w r3, (r6, 0x30) + ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | CV_RepeatTime | AVG_Set; + 1e8c: 9860 ld.w r3, (r14, 0x0) + 1e8e: 6c4c or r1, r3 + 1e90: 964c ld.w r2, (r6, 0x30) + 1e92: 6d44 or r5, r1 + 1e94: 6d48 or r5, r2 + 1e96: b6ac st.w r5, (r6, 0x30) +} + 1e98: 1401 addi r14, r14, 4 + 1e9a: 1494 pop r4-r7, r15 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000010; //ADC2 PA0.1 + 1e9c: 9200 ld.w r0, (r2, 0x0) + 1e9e: 9040 ld.w r2, (r0, 0x0) + 1ea0: 37f0 movi r7, 240 + 1ea2: 689d andn r2, r7 + 1ea4: 3aa4 bseti r2, 4 + 1ea6: 07e8 br 0x1e76 // 1e76 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00001000; //ADC3 PA0.3 + 1ea8: 9200 ld.w r0, (r2, 0x0) + 1eaa: 37f0 movi r7, 240 + 1eac: 9040 ld.w r2, (r0, 0x0) + 1eae: 47e8 lsli r7, r7, 8 + 1eb0: 689d andn r2, r7 + 1eb2: 3aac bseti r2, 12 + 1eb4: 07e1 br 0x1e76 // 1e76 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00100000; //ADC4 PA0.5 + 1eb6: 9200 ld.w r0, (r2, 0x0) + 1eb8: 37f0 movi r7, 240 + 1eba: 9040 ld.w r2, (r0, 0x0) + 1ebc: 47f0 lsli r7, r7, 16 + 1ebe: 689d andn r2, r7 + 1ec0: 3ab4 bseti r2, 20 + 1ec2: 07da br 0x1e76 // 1e76 + GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x01000000; //ADC5 PA0.6 + 1ec4: 9200 ld.w r0, (r2, 0x0) + 1ec6: 37f0 movi r7, 240 + 1ec8: 9040 ld.w r2, (r0, 0x0) + 1eca: 47f4 lsli r7, r7, 20 + 1ecc: 689d andn r2, r7 + 1ece: 3ab8 bseti r2, 24 + 1ed0: 07d3 br 0x1e76 // 1e76 + GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x10000000; //ADC6 PA0.7 + 1ed2: 9200 ld.w r0, (r2, 0x0) + 1ed4: 9040 ld.w r2, (r0, 0x0) + 1ed6: 4244 lsli r2, r2, 4 + 1ed8: 4a44 lsri r2, r2, 4 + 1eda: 3abc bseti r2, 28 + 1edc: 07cd br 0x1e76 // 1e76 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC7 PB0.2 + 1ede: 9240 ld.w r2, (r2, 0x0) + 1ee0: 9200 ld.w r0, (r2, 0x0) + 1ee2: b200 st.w r0, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + 1ee4: 9201 ld.w r0, (r2, 0x4) + 1ee6: b201 st.w r0, (r2, 0x4) + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000100; + 1ee8: 9400 ld.w r0, (r4, 0x0) + 1eea: 34f0 movi r4, 240 + 1eec: 9040 ld.w r2, (r0, 0x0) + 1eee: 4484 lsli r4, r4, 4 + 1ef0: 6891 andn r2, r4 + 1ef2: 3aa8 bseti r2, 8 + 1ef4: 07ba br 0x1e68 // 1e68 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC8 PB0.3 + 1ef6: 9240 ld.w r2, (r2, 0x0) + 1ef8: 9200 ld.w r0, (r2, 0x0) + 1efa: b200 st.w r0, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + 1efc: 9201 ld.w r0, (r2, 0x4) + 1efe: b201 st.w r0, (r2, 0x4) + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0x00001000; + 1f00: 9400 ld.w r0, (r4, 0x0) + 1f02: 34f0 movi r4, 240 + 1f04: 9040 ld.w r2, (r0, 0x0) + 1f06: 4488 lsli r4, r4, 8 + 1f08: 6891 andn r2, r4 + 1f0a: 3aac bseti r2, 12 + 1f0c: 07ae br 0x1e68 // 1e68 + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC9 PA0.8 + 1f0e: 9200 ld.w r0, (r2, 0x0) + 1f10: 9040 ld.w r2, (r0, 0x0) + 1f12: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000001; + 1f14: 9041 ld.w r2, (r0, 0x4) + 1f16: 370f movi r7, 15 + 1f18: 689d andn r2, r7 + 1f1a: 3aa0 bseti r2, 0 + 1f1c: 07af br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC10 PA0.9 + 1f1e: 9200 ld.w r0, (r2, 0x0) + 1f20: 9040 ld.w r2, (r0, 0x0) + 1f22: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0x00000010; + 1f24: 9041 ld.w r2, (r0, 0x4) + 1f26: 37f0 movi r7, 240 + 1f28: 689d andn r2, r7 + 1f2a: 3aa4 bseti r2, 4 + 1f2c: 07a7 br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC11 PA0.10 + 1f2e: 9200 ld.w r0, (r2, 0x0) + 1f30: 9040 ld.w r2, (r0, 0x0) + 1f32: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0x00000100; + 1f34: 37f0 movi r7, 240 + 1f36: 9041 ld.w r2, (r0, 0x4) + 1f38: 47e4 lsli r7, r7, 4 + 1f3a: 689d andn r2, r7 + 1f3c: 3aa8 bseti r2, 8 + 1f3e: 079e br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC12 PA0.11 + 1f40: 9200 ld.w r0, (r2, 0x0) + 1f42: 9040 ld.w r2, (r0, 0x0) + 1f44: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0x00001000; + 1f46: 37f0 movi r7, 240 + 1f48: 9041 ld.w r2, (r0, 0x4) + 1f4a: 47e8 lsli r7, r7, 8 + 1f4c: 689d andn r2, r7 + 1f4e: 3aac bseti r2, 12 + 1f50: 0795 br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC13 PA0.12 + 1f52: 9200 ld.w r0, (r2, 0x0) + 1f54: 9040 ld.w r2, (r0, 0x0) + 1f56: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00010000; + 1f58: 37f0 movi r7, 240 + 1f5a: 9041 ld.w r2, (r0, 0x4) + 1f5c: 47ec lsli r7, r7, 12 + 1f5e: 689d andn r2, r7 + 1f60: 3ab0 bseti r2, 16 + 1f62: 078c br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC14 PA0.13 + 1f64: 9200 ld.w r0, (r2, 0x0) + 1f66: 9040 ld.w r2, (r0, 0x0) + 1f68: b040 st.w r2, (r0, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00100000; + 1f6a: 37f0 movi r7, 240 + 1f6c: 9041 ld.w r2, (r0, 0x4) + 1f6e: 47f0 lsli r7, r7, 16 + 1f70: 689d andn r2, r7 + 1f72: 3ab4 bseti r2, 20 + 1f74: 0783 br 0x1e7a // 1e7a + GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC15 PB0.0 + 1f76: 9240 ld.w r2, (r2, 0x0) + 1f78: 9200 ld.w r0, (r2, 0x0) + 1f7a: b200 st.w r0, (r2, 0x0) + GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000; + 1f7c: 9201 ld.w r0, (r2, 0x4) + 1f7e: b201 st.w r0, (r2, 0x4) + GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000001; + 1f80: 9400 ld.w r0, (r4, 0x0) + 1f82: 9040 ld.w r2, (r0, 0x0) + 1f84: 340f movi r4, 15 + 1f86: 6891 andn r2, r4 + 1f88: 3aa0 bseti r2, 0 + 1f8a: 076f br 0x1e68 // 1e68 + 1f8c: 20000050 .long 0x20000050 + 1f90: 2000004c .long 0x2000004c + 1f94: 20000048 .long 0x20000048 + +Disassembly of section .text.Page_ProgramData: + +00001f98 : + IFC->CR=0X01; //Start Program + } +} +//Normal mode, when the call is completed once, it will delay 4.2ms in the program +void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry) +{ + 1f98: 14c4 push r4-r7 + 1f9a: 1422 subi r14, r14, 8 + int i,DataBuffer; + + //Page cache wipe 1 + SetUserKey; + 1f9c: 1165 lrw r3, 0x20000060 // 2030 + 1f9e: 1186 lrw r4, 0x5a5a5a5a // 2034 + 1fa0: 9360 ld.w r3, (r3, 0x0) + 1fa2: b388 st.w r4, (r3, 0x20) + IFC->CMR=0x07; + 1fa4: 3407 movi r4, 7 + 1fa6: b383 st.w r4, (r3, 0xc) + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + 1fa8: 3401 movi r4, 1 + IFC->FM_ADDR=FlashAdd; + 1faa: b306 st.w r0, (r3, 0x18) + IFC->CR=0X01; //Start Program + 1fac: b384 st.w r4, (r3, 0x10) + while(IFC->CR!=0x0); //Wait for the operation to complete + 1fae: 9384 ld.w r4, (r3, 0x10) + 1fb0: 3c40 cmpnei r4, 0 + 1fb2: 0bfe bt 0x1fae // 1fae + //Write data to the cache 2 + for(i=0;i<((DataSize+3)/4);i++) //sizeof structure + 1fb4: 2102 addi r1, 3 + 1fb6: 4922 lsri r1, r1, 2 + 1fb8: 4122 lsli r1, r1, 2 + 1fba: 6048 addu r1, r2 + 1fbc: b820 st.w r1, (r14, 0x0) + 1fbe: 5829 subu r1, r0, r2 + 1fc0: b821 st.w r1, (r14, 0x4) + 1fc2: 9820 ld.w r1, (r14, 0x0) + 1fc4: 644a cmpne r2, r1 + 1fc6: 0826 bt 0x2012 // 2012 + *(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer; + BufArry +=4; + } + //Pre-programmed operation settings 3 + SetUserKey; + IFC->CMR=0x06; + 1fc8: 3106 movi r1, 6 + SetUserKey; + 1fca: 105b lrw r2, 0x5a5a5a5a // 2034 + 1fcc: b348 st.w r2, (r3, 0x20) + IFC->CMR=0x06; + 1fce: b323 st.w r1, (r3, 0xc) + IFC->FM_ADDR=FlashAdd; + IFC->CR=0X01; //Start Program + 1fd0: 3101 movi r1, 1 + IFC->FM_ADDR=FlashAdd; + 1fd2: b306 st.w r0, (r3, 0x18) + IFC->CR=0X01; //Start Program + 1fd4: b324 st.w r1, (r3, 0x10) + while(IFC->CR!=0x0); //Wait for the operation to complete + 1fd6: 9324 ld.w r1, (r3, 0x10) + 1fd8: 3940 cmpnei r1, 0 + 1fda: 0bfe bt 0x1fd6 // 1fd6 + //Perform pre-programming 4 + SetUserKey; + 1fdc: b348 st.w r2, (r3, 0x20) + IFC->CMR=0x01; + 1fde: 3201 movi r2, 1 + 1fe0: b343 st.w r2, (r3, 0xc) + IFC->FM_ADDR=FlashAdd; // + 1fe2: b306 st.w r0, (r3, 0x18) + IFC->CR=0X01; //Start Program + 1fe4: b344 st.w r2, (r3, 0x10) + while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete + 1fe6: 934a ld.w r2, (r3, 0x28) + 1fe8: 3a44 cmpnei r2, 4 + 1fea: 0bfe bt 0x1fe6 // 1fe6 + //Page erase 5 + SetUserKey; + IFC->CMR=0x02; + 1fec: 3102 movi r1, 2 + SetUserKey; + 1fee: 1052 lrw r2, 0x5a5a5a5a // 2034 + 1ff0: b348 st.w r2, (r3, 0x20) + IFC->CMR=0x02; + 1ff2: b323 st.w r1, (r3, 0xc) + IFC->FM_ADDR=FlashAdd; // + IFC->CR=0X01; //Start Program + 1ff4: 3101 movi r1, 1 + IFC->FM_ADDR=FlashAdd; // + 1ff6: b306 st.w r0, (r3, 0x18) + IFC->CR=0X01; //Start Program + 1ff8: b324 st.w r1, (r3, 0x10) + while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete + 1ffa: 932a ld.w r1, (r3, 0x28) + 1ffc: 3941 cmpnei r1, 1 + 1ffe: 0bfe bt 0x1ffa // 1ffa + //Write page cache data to flash memory 6 + SetUserKey; + 2000: b348 st.w r2, (r3, 0x20) + IFC->CMR=0x01; + 2002: b323 st.w r1, (r3, 0xc) + IFC->FM_ADDR=FlashAdd; // + 2004: b306 st.w r0, (r3, 0x18) + IFC->CR=0X01; //Start Program + 2006: b324 st.w r1, (r3, 0x10) + while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete + 2008: 934a ld.w r2, (r3, 0x28) + 200a: 3a42 cmpnei r2, 2 + 200c: 0bfe bt 0x2008 // 2008 +} + 200e: 1402 addi r14, r14, 8 + 2010: 1484 pop r4-r7 + DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24); + 2012: 82e0 ld.b r7, (r2, 0x0) + 2014: 8281 ld.b r4, (r2, 0x1) + 2016: 4488 lsli r4, r4, 8 + 2018: 8222 ld.b r1, (r2, 0x2) + 201a: 611c addu r4, r7 + 201c: 82a3 ld.b r5, (r2, 0x3) + 201e: 4130 lsli r1, r1, 16 + 2020: 98c1 ld.w r6, (r14, 0x4) + 2022: 6050 addu r1, r4 + 2024: 45b8 lsli r5, r5, 24 + 2026: 6188 addu r6, r2 + 2028: 6054 addu r1, r5 + *(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer; + 202a: b620 st.w r1, (r6, 0x0) + BufArry +=4; + 202c: 2203 addi r2, 4 + 202e: 07ca br 0x1fc2 // 1fc2 + 2030: 20000060 .long 0x20000060 + 2034: 5a5a5a5a .long 0x5a5a5a5a + +Disassembly of section .text.ReadDataArry_U8: + +00002038 : +//ReadFlashData fuction return Data arry save in Flash +//EntryParameter:RdStartAdd、DataLength、*DataArryPoint +//ReturnValue:NONE +*************************************************************/ +void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint) +{ + 2038: 14c3 push r4-r6 + unsigned int i; + for (i=0;i + RdStartAdd +=4; + } + *DataArryPoint=*(U8_T *)(RdStartAdd+ (i%4)); + DataArryPoint++; + } +} + 2044: 1483 pop r4-r6 + if((i!=0)&&(i%4==0)) + 2046: 3b40 cmpnei r3, 0 + 2048: 0c06 bf 0x2054 // 2054 + 204a: 6d0f mov r4, r3 + 204c: 6914 and r4, r5 + 204e: 3c40 cmpnei r4, 0 + 2050: 0802 bt 0x2054 // 2054 + RdStartAdd +=4; + 2052: 2003 addi r0, 4 + *DataArryPoint=*(U8_T *)(RdStartAdd+ (i%4)); + 2054: 6d0f mov r4, r3 + 2056: 6914 and r4, r5 + 2058: 6100 addu r4, r0 + 205a: 8480 ld.b r4, (r4, 0x0) + 205c: a680 st.b r4, (r6, 0x0) + for (i=0;i + +Disassembly of section .text.startup.main: + +00002064
: + +/***************************************************/ +//main +/**************************************************/ +int main(void) +{ + 2064: 14d0 push r15 + //delay_nms(10000); //power on delay if needed + APT32F102_init(); //102 initial + 2066: e00001d5 bsr 0x2410 // 2410 + + PB_Init(); + 206a: e00007cd bsr 0x3004 // 3004 + + PWM_Init(); + 206e: e00016d5 bsr 0x4e18 // 4e18 + + Dbg_Println(DBG_BIT_SYS_STATUS,"MCU Start!"); + 2072: 1026 lrw r1, 0x5a0c // 2088 + 2074: 3000 movi r0, 0 + 2076: e0000799 bsr 0x2fa8 // 2fa8 + + while(1) + { + SYSCON_IWDCNT_Reload(); //IWDT Clear + 207a: e3fff743 bsr 0xf00 // f00 + + UART1_TASK(); + 207e: e0000767 bsr 0x2f4c // 2f4c + + PB_Task(); + 2082: e0001623 bsr 0x4cc8 // 4cc8 + 2086: 07fa br 0x207a // 207a + 2088: 00005a0c .long 0x00005a0c + +Disassembly of section .text.delay_nms: + +0000208c : +//software delay +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void delay_nms(unsigned int t) +{ + 208c: 14d0 push r15 + 208e: 1423 subi r14, r14, 12 + volatile unsigned int i,j ,k=0; + j = 50* t; + 2090: 3232 movi r2, 50 + volatile unsigned int i,j ,k=0; + 2092: 3300 movi r3, 0 + j = 50* t; + 2094: 7c08 mult r0, r2 + volatile unsigned int i,j ,k=0; + 2096: b862 st.w r3, (r14, 0x8) + j = 50* t; + 2098: b801 st.w r0, (r14, 0x4) + for ( i = 0; i < j; i++ ) + 209a: b860 st.w r3, (r14, 0x0) + 209c: 9840 ld.w r2, (r14, 0x0) + 209e: 9861 ld.w r3, (r14, 0x4) + 20a0: 64c8 cmphs r2, r3 + 20a2: 0c03 bf 0x20a8 // 20a8 + { + k++; + SYSCON_IWDCNT_Reload(); + } +} + 20a4: 1403 addi r14, r14, 12 + 20a6: 1490 pop r15 + k++; + 20a8: 9862 ld.w r3, (r14, 0x8) + 20aa: 2300 addi r3, 1 + 20ac: b862 st.w r3, (r14, 0x8) + SYSCON_IWDCNT_Reload(); + 20ae: e3fff729 bsr 0xf00 // f00 + for ( i = 0; i < j; i++ ) + 20b2: 9860 ld.w r3, (r14, 0x0) + 20b4: 2300 addi r3, 1 + 20b6: 07f2 br 0x209a // 209a + +Disassembly of section .text.GPIO_CONFIG: + +000020b8 : +//GPIO Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPIO_CONFIG(void) +{ + 20b8: 14d2 push r4-r5, r15 + //外部中断初始化 + GPIO_IntGroup_Set(PB0,1,Selete_EXI_PIN1); //PB0.0 set as EXI18 + GPIO_Init(GPIOB0,1,1); //PB0.0 set as input + 20ba: 11a4 lrw r5, 0x20000048 // 2148 + GPIO_IntGroup_Set(PB0,1,Selete_EXI_PIN1); //PB0.0 set as EXI18 + 20bc: 3201 movi r2, 1 + 20be: 3101 movi r1, 1 + 20c0: 3002 movi r0, 2 + 20c2: e3fff84d bsr 0x115c // 115c + GPIO_Init(GPIOB0,1,1); //PB0.0 set as input + 20c6: 9500 ld.w r0, (r5, 0x0) + 20c8: 3201 movi r2, 1 + 20ca: 3101 movi r1, 1 + 20cc: e3fff7d0 bsr 0x106c // 106c + EXTI_trigger_CMD(ENABLE,EXI_PIN1,_EXIRT); //ENABLE falling edge + 20d0: 3200 movi r2, 0 + 20d2: 3102 movi r1, 2 + 20d4: 3001 movi r0, 1 + 20d6: e3fff757 bsr 0xf84 // f84 + + EXTI_interrupt_CMD(ENABLE,EXI_PIN1); //enable EXI + 20da: 3102 movi r1, 2 + 20dc: 3001 movi r0, 1 + 20de: e3fff773 bsr 0xfc4 // fc4 + GPIO_EXTI_interrupt(GPIOB0,0b0000000000000010); //enable GPIOB0.0 as EXI + 20e2: 9500 ld.w r0, (r5, 0x0) + 20e4: 3102 movi r1, 2 + 20e6: e3fff789 bsr 0xff8 // ff8 + + Set_INT_Priority(EXI1_IRQ,0); //0:set int priority 1st + 20ea: 3100 movi r1, 0 + 20ec: 3008 movi r0, 8 + 20ee: e3fff7a7 bsr 0x103c // 103c + EXI1_Int_Enable(); //EXI1 / EXI17 INT Vector + 20f2: e3fff785 bsr 0xffc // ffc + + //GPIO初始化 + GPIO_Init(GPIOB0,4,0); //PB0.4 set as output + GPIO_Init(GPIOA0,12,0); //PA0.12 set as output + 20f6: 1096 lrw r4, 0x2000004c // 214c + GPIO_Init(GPIOB0,4,0); //PB0.4 set as output + 20f8: 3200 movi r2, 0 + 20fa: 9500 ld.w r0, (r5, 0x0) + 20fc: 3104 movi r1, 4 + 20fe: e3fff7b7 bsr 0x106c // 106c + GPIO_Init(GPIOA0,12,0); //PA0.12 set as output + 2102: 9400 ld.w r0, (r4, 0x0) + 2104: 3200 movi r2, 0 + 2106: 310c movi r1, 12 + 2108: e3fff7b2 bsr 0x106c // 106c + GPIO_Init(GPIOA0,14,0); //PA0.14 set as output + 210c: 3200 movi r2, 0 + 210e: 9400 ld.w r0, (r4, 0x0) + 2110: 310e movi r1, 14 + 2112: e3fff7ad bsr 0x106c // 106c + + GPIO_DriveStrength_EN(GPIOB0,4); + 2116: 9500 ld.w r0, (r5, 0x0) + 2118: 3104 movi r1, 4 + 211a: e3fff819 bsr 0x114c // 114c + GPIO_DriveStrength_EN(GPIOA0,12); + 211e: 9400 ld.w r0, (r4, 0x0) + 2120: 310c movi r1, 12 + 2122: e3fff815 bsr 0x114c // 114c + GPIO_DriveStrength_EN(GPIOA0,14); + 2126: 9400 ld.w r0, (r4, 0x0) + 2128: 310e movi r1, 14 + 212a: e3fff811 bsr 0x114c // 114c + + GPIO_Write_Low(GPIOB0,4); //上电默认为低电平 + 212e: 9500 ld.w r0, (r5, 0x0) + 2130: 3104 movi r1, 4 + 2132: e3fff89f bsr 0x1270 // 1270 + GPIO_Write_Low(GPIOA0,12); + 2136: 9400 ld.w r0, (r4, 0x0) + 2138: 310c movi r1, 12 + 213a: e3fff89b bsr 0x1270 // 1270 + GPIO_Write_Low(GPIOA0,14); + 213e: 9400 ld.w r0, (r4, 0x0) + 2140: 310e movi r1, 14 + 2142: e3fff897 bsr 0x1270 // 1270 + + +} + 2146: 1492 pop r4-r5, r15 + 2148: 20000048 .long 0x20000048 + 214c: 2000004c .long 0x2000004c + +Disassembly of section .text.EPT0_CONFIG: + +00002150 : +//ETP0 Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT0_CONFIG(void) +{ + 2150: 14d3 push r4-r6, r15 + 2152: 1429 subi r14, r14, 36 + //4路 PWM初始化 + EPT_Software_Prg(); //EPT software reset + 2154: e3fffae8 bsr 0x1724 // 1724 +//------------ EPT GPIO Setting --------------------------------/ + EPT_IO_SET(EPT_IO_CHAX,IO_NUM_PA10); //AX channel selection + 2158: 3111 movi r1, 17 + 215a: 3000 movi r0, 0 + 215c: e3fffb08 bsr 0x176c // 176c + EPT_IO_SET(EPT_IO_CHBX,IO_NUM_PA11); //BX channel selection + 2160: 3117 movi r1, 23 + 2162: 3002 movi r0, 2 + 2164: e3fffb04 bsr 0x176c // 176c + EPT_IO_SET(EPT_IO_CHCX,IO_NUM_PB05); //CX channel selection + 2168: 3114 movi r1, 20 + 216a: 3004 movi r0, 4 + 216c: e3fffb00 bsr 0x176c // 176c + EPT_IO_SET(EPT_IO_CHD,IO_NUM_PA08); //D channel selection + 2170: 311b movi r1, 27 + 2172: 3006 movi r0, 6 +//------------ EPT Control --------------------------------/ + EPT_PWM_Config(EPT_Selecte_PCLK,EPT_CNTMD_increase,EPT_OPM_Continue,0);//PCLK as clock，increasing mode,continuous mode,TCLK=PCLK/(0+1) + + EPT_PWMX_Output_Control(EPT_PWMA,EPT_CA_Selecte_CMPA,EPT_CB_Selecte_CMPA,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 2174: 3400 movi r4, 0 + EPT_IO_SET(EPT_IO_CHD,IO_NUM_PA08); //D channel selection + 2176: e3fffafb bsr 0x176c // 176c + EPT_PWMX_Output_Control(EPT_PWMA,EPT_CA_Selecte_CMPA,EPT_CB_Selecte_CMPA,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 217a: 3680 movi r6, 128 + 217c: 3520 movi r5, 32 + EPT_PWM_Config(EPT_Selecte_PCLK,EPT_CNTMD_increase,EPT_OPM_Continue,0);//PCLK as clock，increasing mode,continuous mode,TCLK=PCLK/(0+1) + 217e: 3300 movi r3, 0 + 2180: 3200 movi r2, 0 + 2182: 3100 movi r1, 0 + 2184: 3000 movi r0, 0 + 2186: e3fffc0f bsr 0x19a4 // 19a4 + EPT_PWMX_Output_Control(EPT_PWMA,EPT_CA_Selecte_CMPA,EPT_CB_Selecte_CMPA,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 218a: b888 st.w r4, (r14, 0x20) + 218c: b887 st.w r4, (r14, 0x1c) + 218e: b886 st.w r4, (r14, 0x18) + 2190: b885 st.w r4, (r14, 0x14) + 2192: b884 st.w r4, (r14, 0x10) + 2194: b883 st.w r4, (r14, 0xc) + 2196: b8c2 st.w r6, (r14, 0x8) + 2198: b8a1 st.w r5, (r14, 0x4) + 219a: b880 st.w r4, (r14, 0x0) + 219c: 3301 movi r3, 1 + 219e: 3200 movi r2, 0 + 21a0: 3100 movi r1, 0 + 21a2: 3000 movi r0, 0 + 21a4: e3fffc1c bsr 0x19dc // 19dc + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMB,EPT_CA_Selecte_CMPB,EPT_CB_Selecte_CMPB,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 21a8: 3280 movi r2, 128 + 21aa: 3180 movi r1, 128 + 21ac: 424f lsli r2, r2, 15 + 21ae: 412d lsli r1, r1, 13 + 21b0: b888 st.w r4, (r14, 0x20) + 21b2: b887 st.w r4, (r14, 0x1c) + 21b4: b886 st.w r4, (r14, 0x18) + 21b6: b885 st.w r4, (r14, 0x14) + 21b8: b884 st.w r4, (r14, 0x10) + 21ba: b883 st.w r4, (r14, 0xc) + 21bc: b8c2 st.w r6, (r14, 0x8) + 21be: b8a1 st.w r5, (r14, 0x4) + 21c0: b880 st.w r4, (r14, 0x0) + 21c2: 3301 movi r3, 1 + 21c4: 3001 movi r0, 1 + 21c6: e3fffc0b bsr 0x19dc // 19dc + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMC,EPT_CA_Selecte_CMPC,EPT_CB_Selecte_CMPC,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 21ca: 3280 movi r2, 128 + 21cc: 3180 movi r1, 128 + 21ce: 4250 lsli r2, r2, 16 + 21d0: 412e lsli r1, r1, 14 + 21d2: b888 st.w r4, (r14, 0x20) + 21d4: b887 st.w r4, (r14, 0x1c) + 21d6: b886 st.w r4, (r14, 0x18) + 21d8: b885 st.w r4, (r14, 0x14) + 21da: b884 st.w r4, (r14, 0x10) + 21dc: b883 st.w r4, (r14, 0xc) + 21de: b8c2 st.w r6, (r14, 0x8) + 21e0: b8a1 st.w r5, (r14, 0x4) + 21e2: b880 st.w r4, (r14, 0x0) + 21e4: 3301 movi r3, 1 + 21e6: 3002 movi r0, 2 + 21e8: e3fffbfa bsr 0x19dc // 19dc + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMD,EPT_CA_Selecte_CMPD,EPT_CB_Selecte_CMPD,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + 21ec: 32c0 movi r2, 192 + 21ee: 31c0 movi r1, 192 + 21f0: 4250 lsli r2, r2, 16 + 21f2: 412e lsli r1, r1, 14 + 21f4: b888 st.w r4, (r14, 0x20) + 21f6: b887 st.w r4, (r14, 0x1c) + 21f8: b886 st.w r4, (r14, 0x18) + 21fa: b885 st.w r4, (r14, 0x14) + 21fc: b884 st.w r4, (r14, 0x10) + 21fe: b883 st.w r4, (r14, 0xc) + 2200: b8c2 st.w r6, (r14, 0x8) + 2202: b8a1 st.w r5, (r14, 0x4) + 2204: b880 st.w r4, (r14, 0x0) + 2206: 3301 movi r3, 1 + 2208: 3003 movi r0, 3 + 220a: e3fffbe9 bsr 0x19dc // 19dc + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + + EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(PWM_OUT_VAL_MAX,0,0,0,0);//PRDR=2400,CMPA=1200,CMPB=600,CMPC=2400,CMPD=0 + 220e: 3300 movi r3, 0 + 2210: 3200 movi r2, 0 + 2212: 3100 movi r1, 0 + 2214: 1004 lrw r0, 0xbb8 // 2224 + 2216: b880 st.w r4, (r14, 0x0) + 2218: e3fffc4e bsr 0x1ab4 // 1ab4 + +//------------ EPT start --------------------------------/ + EPT_Start(); + 221c: e3fffa94 bsr 0x1744 // 1744 + +} + 2220: 1409 addi r14, r14, 36 + 2222: 1493 pop r4-r6, r15 + 2224: 00000bb8 .long 0x00000bb8 + +Disassembly of section .text.BT_CONFIG: + +00002228 : +//BT Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_CONFIG(void) +{ + 2228: 14d3 push r4-r6, r15 + 222a: 1424 subi r14, r14, 16 + //PB 保护电流PWM_CURR_LMT + BT_DeInit(BT0); + 222c: 11a6 lrw r5, 0x2000000c // 22c4 + BT_IO_Init(BT0_PA15); + BT_Configure(BT0,BTCLK_EN,7,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);//TCLK=PCLK/(0+1) + 222e: 3400 movi r4, 0 + BT_DeInit(BT0); + 2230: 9500 ld.w r0, (r5, 0x0) + 2232: e3fff863 bsr 0x12f8 // 12f8 + BT_IO_Init(BT0_PA15); + 2236: 3007 movi r0, 7 + 2238: e3fff86e bsr 0x1314 // 1314 + BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + 223c: 3680 movi r6, 128 + BT_Configure(BT0,BTCLK_EN,7,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);//TCLK=PCLK/(0+1) + 223e: b881 st.w r4, (r14, 0x4) + 2240: b880 st.w r4, (r14, 0x0) + 2242: 9500 ld.w r0, (r5, 0x0) + BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + 2244: 46c3 lsli r6, r6, 3 + BT_Configure(BT0,BTCLK_EN,7,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);//TCLK=PCLK/(0+1) + 2246: 3308 movi r3, 8 + 2248: 3207 movi r2, 7 + 224a: 3101 movi r1, 1 + 224c: e3fff913 bsr 0x1472 // 1472 + BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + 2250: b883 st.w r4, (r14, 0xc) + 2252: b882 st.w r4, (r14, 0x8) + 2254: b8c1 st.w r6, (r14, 0x4) + 2256: b880 st.w r4, (r14, 0x0) + 2258: 3300 movi r3, 0 + 225a: 9500 ld.w r0, (r5, 0x0) + 225c: 3200 movi r2, 0 + 225e: 3180 movi r1, 128 + 2260: e3fff915 bsr 0x148a // 148a + //BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_EN,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + //BT_Trigger_Configure(BT0,BT_TRGSRC_PEND,BT_TRGOE_EN); + BT_Period_CMP_Write(BT0,4095,4000); + 2264: 32fa movi r2, 250 + 2266: 4244 lsli r2, r2, 4 + 2268: 1038 lrw r1, 0xfff // 22c8 + 226a: 9500 ld.w r0, (r5, 0x0) + 226c: e3fff925 bsr 0x14b6 // 14b6 + BT_Start(BT0); + 2270: 9500 ld.w r0, (r5, 0x0) + 2272: e3fff8f7 bsr 0x1460 // 1460 +// BT_ConfigInterrupt_CMD(BT0,ENABLE,BT_PEND); +// BT0_INT_ENABLE(); + + + //100us 定时器初始化 + BT_DeInit(BT1); + 2276: 10b6 lrw r5, 0x20000008 // 22cc + 2278: 9500 ld.w r0, (r5, 0x0) + 227a: e3fff83f bsr 0x12f8 // 12f8 + BT_Configure(BT1,BTCLK_EN,0,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV); + 227e: b881 st.w r4, (r14, 0x4) + 2280: b880 st.w r4, (r14, 0x0) + 2282: 9500 ld.w r0, (r5, 0x0) + 2284: 3308 movi r3, 8 + 2286: 3200 movi r2, 0 + 2288: 3101 movi r1, 1 + 228a: e3fff8f4 bsr 0x1472 // 1472 + BT_ControlSet_Configure(BT1,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + 228e: b883 st.w r4, (r14, 0xc) + 2290: b882 st.w r4, (r14, 0x8) + 2292: b8c1 st.w r6, (r14, 0x4) + 2294: b880 st.w r4, (r14, 0x0) + 2296: 3300 movi r3, 0 + 2298: 9500 ld.w r0, (r5, 0x0) + 229a: 3200 movi r2, 0 + 229c: 3180 movi r1, 128 + 229e: e3fff8f6 bsr 0x148a // 148a + BT_Period_CMP_Write(BT1,4780,1); + 22a2: 3201 movi r2, 1 + 22a4: 102b lrw r1, 0x12ac // 22d0 + 22a6: 9500 ld.w r0, (r5, 0x0) + 22a8: e3fff907 bsr 0x14b6 // 14b6 + BT_Start(BT1); + 22ac: 9500 ld.w r0, (r5, 0x0) + 22ae: e3fff8d9 bsr 0x1460 // 1460 + BT_ConfigInterrupt_CMD(BT1,ENABLE,BT_CMP); + 22b2: 9500 ld.w r0, (r5, 0x0) + 22b4: 3202 movi r2, 2 + 22b6: 3101 movi r1, 1 + 22b8: e3fff902 bsr 0x14bc // 14bc + BT1_INT_ENABLE(); + 22bc: e3fff90a bsr 0x14d0 // 14d0 + +} + 22c0: 1404 addi r14, r14, 16 + 22c2: 1493 pop r4-r6, r15 + 22c4: 2000000c .long 0x2000000c + 22c8: 00000fff .long 0x00000fff + 22cc: 20000008 .long 0x20000008 + 22d0: 000012ac .long 0x000012ac + +Disassembly of section .text.ADC12_CONFIG: + +000022d4 : +//adc config +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_CONFIG(void) +{ + 22d4: 14d0 push r15 + 22d6: 1422 subi r14, r14, 8 + + ADC12_RESET_VALUE(); //ADC所有寄存器复位 + 22d8: e3fffbfc bsr 0x1ad0 // 1ad0 + ADC12_Software_Reset(); //ADC软件复位 + 22dc: e3fffc5a bsr 0x1b90 // 1b90 + ADC12_CLK_CMD(ADC_CLK_CR,ENABLE); //使能ADC CLK + 22e0: 3101 movi r1, 1 + 22e2: 3002 movi r0, 2 + 22e4: e3fffc40 bsr 0x1b64 // 1b64 + + ADC12_Configure_Mode(ADC12_12BIT,Continuous_mode,0,6,2,4); + 22e8: 3304 movi r3, 4 + 22ea: b861 st.w r3, (r14, 0x4) + 22ec: 3302 movi r3, 2 + 22ee: b860 st.w r3, (r14, 0x0) + 22f0: 3200 movi r2, 0 + 22f2: 3306 movi r3, 6 + 22f4: 3101 movi r1, 1 + 22f6: 3001 movi r0, 1 + 22f8: e3fffc86 bsr 0x1c04 // 1c04 + + ADC12_Configure_VREF_Selecte(ADC12_VREFP_VDD_VREFN_VSS); + 22fc: 3000 movi r0, 0 + 22fe: e3fffcc1 bsr 0x1c80 // 1c80 + + ADC12_ConversionChannel_Config(ADC12_ADCIN4,ADC12_CV_RepeatNum1,ADC12_AVGDIS,0); + 2302: 3300 movi r3, 0 + 2304: 3200 movi r2, 0 + 2306: 3100 movi r1, 0 + 2308: 3004 movi r0, 4 + 230a: e3fffd87 bsr 0x1e18 // 1e18 + ADC12_ConversionChannel_Config(ADC12_ADCIN7,ADC12_CV_RepeatNum1,ADC12_AVGDIS,1); + 230e: 3301 movi r3, 1 + 2310: 3200 movi r2, 0 + 2312: 3100 movi r1, 0 + 2314: 3007 movi r0, 7 + 2316: e3fffd81 bsr 0x1e18 // 1e18 + ADC12_ConversionChannel_Config(ADC12_ADCIN8,ADC12_CV_RepeatNum1,ADC12_AVGDIS,2); + 231a: 3302 movi r3, 2 + 231c: 3200 movi r2, 0 + 231e: 3100 movi r1, 0 + 2320: 3008 movi r0, 8 + 2322: e3fffd7b bsr 0x1e18 // 1e18 + ADC12_ConversionChannel_Config(ADC12_ADCIN10,ADC12_CV_RepeatNum1,ADC12_AVGDIS,3); + 2326: 3303 movi r3, 3 + 2328: 3200 movi r2, 0 + 232a: 3100 movi r1, 0 + 232c: 300a movi r0, 10 + 232e: e3fffd75 bsr 0x1e18 // 1e18 + + ADC12_CMD(ENABLE); + 2332: 3001 movi r0, 1 + 2334: e3fffc34 bsr 0x1b9c // 1b9c + + ADC12_ready_wait(); + 2338: e3fffc46 bsr 0x1bc4 // 1bc4 + + ADC12_Control(ADC12_START); + 233c: 3008 movi r0, 8 + 233e: e3fffbfb bsr 0x1b34 // 1b34 +} + 2342: 1402 addi r14, r14, 8 + 2344: 1490 pop r15 + +Disassembly of section .text.GPT0_CONFIG: + +00002348 : +//GPT0 Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT0_CONFIG(void) +{ + 2348: 14d0 push r15 + 234a: 1426 subi r14, r14, 24 + + GPT_Configure(GPTCLK_EN,GPT_PCLK,GPT_IMMEDIATE,1); + 234c: 3301 movi r3, 1 + 234e: 3240 movi r2, 64 + 2350: 3100 movi r1, 0 + 2352: 3001 movi r0, 1 + 2354: e3fff8c6 bsr 0x14e0 // 14e0 + GPT_WaveCtrl_Configure(GPT_INCREASE,GPT_SWSYNDIS,GPT_IDLE_LOW,GPT_PRDLD_PEND,GPT_OPM_CONTINUOUS,GPT_BURST_DIS,GPT_CKS_PCLK,GPT_CG_CHAX,GPT_CGFLT_00,GPT_PRDLD_ZERO); + 2358: 3300 movi r3, 0 + 235a: b865 st.w r3, (r14, 0x14) + 235c: b864 st.w r3, (r14, 0x10) + 235e: b863 st.w r3, (r14, 0xc) + 2360: b862 st.w r3, (r14, 0x8) + 2362: b861 st.w r3, (r14, 0x4) + 2364: b860 st.w r3, (r14, 0x0) + 2366: 3208 movi r2, 8 + 2368: 3100 movi r1, 0 + 236a: 3000 movi r0, 0 + 236c: e3fff8c4 bsr 0x14f4 // 14f4 + GPT_Period_CMP_Write(24000,1,1000); + 2370: 32fa movi r2, 250 + 2372: 4242 lsli r2, r2, 2 + 2374: 3101 movi r1, 1 + 2376: 1008 lrw r0, 0x5dc0 // 2394 + 2378: e3fff8e8 bsr 0x1548 // 1548 + //GPT_WaveLoad_Configure(GPT_WAVEA_IMMEDIATE,GPT_WAVEB_SHADOW,GPT_AQLDA_ZERO,GPT_AQLDB_ZERO); + + //GPT_SyncSet_Configure(GPT_SYNCUSR0_EN,GPT_OST_CONTINUOUS,GPT_TXREARM_DIS,GPT_TRGO0SEL_SR0,GPT_TRG10SEL_SR0,GPT_AREARM_DIS); + //GPT_Trigger_Configure(GPT_SRCSEL_TRGUSR0EN,GPT_BLKINV_DIS,GPT_ALIGNMD_PRD,GPT_CROSSMD_DIS,5,5); + //GPT_EVTRG_Configure(GPT_TRGSRC0_PRD,GPT_TRGSRC1_PRD,GPT_ESYN0OE_EN,GPT_ESYN1OE_EN,GPT_CNT0INIT_EN,GPT_CNT1INIT_EN,3,3,3,3); + GPT_Start(); + 237c: e3fff8de bsr 0x1538 // 1538 + GPT_ConfigInterrupt_CMD(ENABLE,GPT_INT_PEND); + 2380: 3180 movi r1, 128 + 2382: 4129 lsli r1, r1, 9 + 2384: 3001 movi r0, 1 + 2386: e3fff8e9 bsr 0x1558 // 1558 + GPT_INT_ENABLE(); + 238a: e3fff8f5 bsr 0x1574 // 1574 + +} + 238e: 1406 addi r14, r14, 24 + 2390: 1490 pop r15 + 2392: 0000 bkpt + 2394: 00005dc0 .long 0x00005dc0 + +Disassembly of section .text.SYSCON_CONFIG: + +00002398 : +//syscon Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_CONFIG(void) +{ + 2398: 14d0 push r15 + 239a: 1421 subi r14, r14, 4 +//------SYSTEM CLK AND PCLK FUNTION---------------------------/ + SYSCON_RST_VALUE(); //SYSCON all register clr + 239c: e3fff4f8 bsr 0xd8c // d8c + SYSCON_General_CMD(ENABLE,ENDIS_ISOSC); //SYSCON enable/disable clock source + 23a0: 3101 movi r1, 1 + 23a2: 3001 movi r0, 1 + 23a4: e3fff520 bsr 0xde4 // de4 + //EMOSC_OSTR_Config(0XAD,0X1f,EM_LFSEL_EN,EM_FLEN_EN,EM_FLSEL_10ns); //EM_CNT=0X3FF,0xAD(36K),EM_GM=0,Low F modedisable,EM filter disable,if enable,cont set 5ns + //SYSCON_General_CMD(ENABLE,ENDIS_EMOSC); + SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_48M); //HFOSC selected 48MHz + 23a8: 3000 movi r0, 0 + 23aa: e3fff579 bsr 0xe9c // e9c + SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_HFOSC,HCLK_DIV_1,PCLK_DIV_1,HFOSC_48M);//system clock set, Hclk div ,Pclk div set system clock=SystemCLK/Hclk div/Pclk div + 23ae: 3180 movi r1, 128 + 23b0: 3308 movi r3, 8 + 23b2: 3200 movi r2, 0 + 23b4: 4121 lsli r1, r1, 1 + 23b6: 3002 movi r0, 2 + 23b8: e3fff52e bsr 0xe14 // e14 +//------------ WDT FUNTION --------------------------------/ + SYSCON_IWDCNT_Config(IWDT_TIME_4S,IWDT_INTW_DIV_7); //WDT TIME 1s,WDT alarm interrupt time=1s-1s*1/8=0.875S + 23bc: 30c0 movi r0, 192 + 23be: 3118 movi r1, 24 + 23c0: 4003 lsli r0, r0, 3 + 23c2: e3fff5a9 bsr 0xf14 // f14 + SYSCON_WDT_CMD(ENABLE); //enable/disable WDT + 23c6: 3001 movi r0, 1 + 23c8: e3fff57e bsr 0xec4 // ec4 + SYSCON_IWDCNT_Reload(); //reload WDT + 23cc: e3fff59a bsr 0xf00 // f00 + IWDT_Int_Enable(); + 23d0: e3fff5cc bsr 0xf68 // f68 +//------------ WWDT FUNTION --------------------------------/ + WWDT_CNT_Load(0xFF); + 23d4: 30ff movi r0, 255 + 23d6: e3fff76f bsr 0x12b4 // 12b4 + WWDT_CONFIG(PCLK_4096_DIV0,0xFF,WWDT_DBGDIS); + 23da: 3200 movi r2, 0 + 23dc: 31ff movi r1, 255 + 23de: 3000 movi r0, 0 + 23e0: e3fff75e bsr 0x129c // 129c + WWDT_Int_Config(DISABLE); + 23e4: 3000 movi r0, 0 + 23e6: e3fff76f bsr 0x12c4 // 12c4 + //WWDT_CMD(ENABLE); //enable wwdt +//------------ CLO Output --------------------------------/ + //SYSCON_CLO_CONFIG(CLO_PA08); //CLO output setting + //SYSCON_CLO_SRC_SET(CLO_HFCLK,CLO_DIV16); //CLO output clock and div +//------------ LVD FUNTION --------------------------------/ + SYSCON_LVD_Config(ENABLE_LVDEN,INTDET_LVL_3_9V,RSTDET_LVL_1_9V,ENABLE_LVD_INT,INTDET_POL_fall); //LVD LVR Enable/Disable + 23ea: 3340 movi r3, 64 + 23ec: b860 st.w r3, (r14, 0x0) + 23ee: 31c0 movi r1, 192 + 23f0: 3380 movi r3, 128 + 23f2: 4364 lsli r3, r3, 4 + 23f4: 3200 movi r2, 0 + 23f6: 4123 lsli r1, r1, 3 + 23f8: 3000 movi r0, 0 + 23fa: e3fff599 bsr 0xf2c // f2c + LVD_Int_Enable(); + 23fe: e3fff5a7 bsr 0xf4c // f4c +//------------ SYSCON Vector --------------------------------/ + SYSCON_Int_Enable(); //SYSCON VECTOR + 2402: e3fff605 bsr 0x100c // 100c + //SYSCON_WakeUp_Enable(); //Enable WDT wakeup INT +//------------------------------------------------------------/ +//OSC CLOCK Calibration +//------------------------------------------------------------/ + std_clk_calib(CLK_HFOSC_48M); //Select the same clock source as the system + 2406: 3000 movi r0, 0 + 2408: e0001852 bsr 0x54ac // 54ac + +} + 240c: 1401 addi r14, r14, 4 + 240e: 1490 pop r15 + +Disassembly of section .text.APT32F102_init: + +00002410 : +//ReturnValue:NONE / +/*********************************************************************************/ +/*********************************************************************************/ +/*********************************************************************************/ +void APT32F102_init(void) +{ + 2410: 14d0 push r15 +//------------------------------------------------------------/ +//Peripheral clock enable and disable +//EntryParameter:NONE +//ReturnValue:NONE +//------------------------------------------------------------/ + SYSCON->PCER0=0xFFFFFFF; //PCLK Enable + 2412: 107b lrw r3, 0x2000005c // 247c + SYSCON->PCER1=0xFFFFFFF; //PCLK Enable + while(!(SYSCON->PCSR0&0x1)); //Wait PCLK enabled + 2414: 3101 movi r1, 1 + SYSCON->PCER0=0xFFFFFFF; //PCLK Enable + 2416: 9340 ld.w r2, (r3, 0x0) + 2418: 107a lrw r3, 0xfffffff // 2480 + 241a: b26a st.w r3, (r2, 0x28) + SYSCON->PCER1=0xFFFFFFF; //PCLK Enable + 241c: b26d st.w r3, (r2, 0x34) + while(!(SYSCON->PCSR0&0x1)); //Wait PCLK enabled + 241e: 926c ld.w r3, (r2, 0x30) + 2420: 68c4 and r3, r1 + 2422: 3b40 cmpnei r3, 0 + 2424: 0ffd bf 0x241e // 241e +//------------------------------------------------------------/ +//ISOSC/IMOSC/EMOSC/SYSCLK/IWDT/LVD/EM_CMFAIL/EM_CMRCV/CMD_ERR OSC stable interrupt +//EntryParameter:NONE +//ReturnValue:NONE +//------------------------------------------------------------/ + SYSCON_CONFIG(); //syscon initial + 2426: e3ffffb9 bsr 0x2398 // 2398 + CK_CPU_EnAllNormalIrq(); //enable all IRQ + 242a: e0000527 bsr 0x2e78 // 2e78 + SYSCON_INT_Priority(); //initial all Priority=0xC0 + 242e: e3fff5f5 bsr 0x1018 // 1018 + + Set_INT_Priority(EXI1_IRQ,0); + 2432: 3100 movi r1, 0 + 2434: 3008 movi r0, 8 + 2436: e3fff603 bsr 0x103c // 103c + Set_INT_Priority(UART1_IRQ,1); + 243a: 3101 movi r1, 1 + 243c: 300e movi r0, 14 + 243e: e3fff5ff bsr 0x103c // 103c + Set_INT_Priority(BT1_IRQ,1); + 2442: 3101 movi r1, 1 + 2444: 301d movi r0, 29 + 2446: e3fff5fb bsr 0x103c // 103c + Set_INT_Priority(UART0_IRQ,2); + 244a: 3102 movi r1, 2 + 244c: 300d movi r0, 13 + 244e: e3fff5f7 bsr 0x103c // 103c +//------------------------------------------------------------/ +//Other IP config +//------------------------------------------------------------/ + GPIO_CONFIG(); //GPIO initial + 2452: e3fffe33 bsr 0x20b8 // 20b8 + EPT0_CONFIG(); //EPT0 initial + 2456: e3fffe7d bsr 0x2150 // 2150 + + BT_CONFIG(); //BT initial + 245a: e3fffee7 bsr 0x2228 // 2228 + GPT0_CONFIG(); //2024-06-16 修改 单独用于PWM 1ms定时控制 + 245e: e3ffff75 bsr 0x2348 // 2348 + + UARTx_Init(UART_0,NULL); + 2462: 3100 movi r1, 0 + 2464: 3000 movi r0, 0 + 2466: e000050d bsr 0x2e80 // 2e80 + UARTx_Init(UART_1,BLV_PB_Control_Protocol_Processing); + 246a: 1027 lrw r1, 0x4a1c // 2484 + 246c: 3001 movi r0, 1 + 246e: e0000509 bsr 0x2e80 // 2e80 + + EEPROM_Init(); + 2472: e00017fb bsr 0x5468 // 5468 + + ADC12_CONFIG(); //ADC initial + 2476: e3ffff2f bsr 0x22d4 // 22d4 + +} + 247a: 1490 pop r15 + 247c: 2000005c .long 0x2000005c + 2480: 0fffffff .long 0x0fffffff + 2484: 00004a1c .long 0x00004a1c + +Disassembly of section .text.SYSCONIntHandler: + +00002488 : +//SYSCON Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCONIntHandler(void) +{ + 2488: 1460 nie + 248a: 1462 ipush + // ISR content ... + nop; + 248c: 6c03 mov r0, r0 + if((SYSCON->MISR&ISOSC_ST)==ISOSC_ST) //ISOSC stable interrupt + 248e: 117a lrw r3, 0x2000005c // 2574 + 2490: 3280 movi r2, 128 + 2492: 9360 ld.w r3, (r3, 0x0) + 2494: 60c8 addu r3, r2 + 2496: 9323 ld.w r1, (r3, 0xc) + 2498: 3001 movi r0, 1 + 249a: 6840 and r1, r0 + 249c: 3940 cmpnei r1, 0 + 249e: 0c04 bf 0x24a6 // 24a6 + { + SYSCON->ICR = EMOSC_ST; + } + else if((SYSCON->MISR&HFOSC_ST)==HFOSC_ST) //HFOSC stable interrupt + { + SYSCON->ICR = HFOSC_ST; + 24a0: b301 st.w r0, (r3, 0x4) + } + else if((SYSCON->MISR&CMD_ERR_ST)==CMD_ERR_ST) //Command error interrupt + { + SYSCON->ICR = CMD_ERR_ST; + } +} + 24a2: 1463 ipop + 24a4: 1461 nir + else if((SYSCON->MISR&IMOSC_ST)==IMOSC_ST) //IMOSC stable interrupt + 24a6: 9323 ld.w r1, (r3, 0xc) + 24a8: 3002 movi r0, 2 + 24aa: 6840 and r1, r0 + 24ac: 3940 cmpnei r1, 0 + 24ae: 0bf9 bt 0x24a0 // 24a0 + else if((SYSCON->MISR&EMOSC_ST)==EMOSC_ST) //EMOSC stable interrupt + 24b0: 9323 ld.w r1, (r3, 0xc) + 24b2: 3008 movi r0, 8 + 24b4: 6840 and r1, r0 + 24b6: 3940 cmpnei r1, 0 + 24b8: 0bf4 bt 0x24a0 // 24a0 + else if((SYSCON->MISR&HFOSC_ST)==HFOSC_ST) //HFOSC stable interrupt + 24ba: 9323 ld.w r1, (r3, 0xc) + 24bc: 3010 movi r0, 16 + 24be: 6840 and r1, r0 + 24c0: 3940 cmpnei r1, 0 + 24c2: 0bef bt 0x24a0 // 24a0 + else if((SYSCON->MISR&SYSCLK_ST)==SYSCLK_ST) //SYSCLK change end & stable interrupt + 24c4: 9323 ld.w r1, (r3, 0xc) + 24c6: 6848 and r1, r2 + 24c8: 3940 cmpnei r1, 0 + 24ca: 0c03 bf 0x24d0 // 24d0 + SYSCON->ICR = CMD_ERR_ST; + 24cc: b341 st.w r2, (r3, 0x4) +} + 24ce: 07ea br 0x24a2 // 24a2 + else if((SYSCON->MISR&IWDT_INT_ST)==IWDT_INT_ST) //IWDT alarm window interrupt + 24d0: 3280 movi r2, 128 + 24d2: 9323 ld.w r1, (r3, 0xc) + 24d4: 4241 lsli r2, r2, 1 + 24d6: 6848 and r1, r2 + 24d8: 3940 cmpnei r1, 0 + 24da: 0bf9 bt 0x24cc // 24cc + else if((SYSCON->MISR&WKI_INT_ST)==WKI_INT_ST) + 24dc: 3280 movi r2, 128 + 24de: 9323 ld.w r1, (r3, 0xc) + 24e0: 4242 lsli r2, r2, 2 + 24e2: 6848 and r1, r2 + 24e4: 3940 cmpnei r1, 0 + 24e6: 0bf3 bt 0x24cc // 24cc + else if((SYSCON->MISR&RAMERRINT_ST)==RAMERRINT_ST) //SRAM check fail interrupt + 24e8: 3280 movi r2, 128 + 24ea: 9323 ld.w r1, (r3, 0xc) + 24ec: 4243 lsli r2, r2, 3 + 24ee: 6848 and r1, r2 + 24f0: 3940 cmpnei r1, 0 + 24f2: 0bed bt 0x24cc // 24cc + else if((SYSCON->MISR&LVD_INT_ST)==LVD_INT_ST) //LVD threshold interrupt + 24f4: 3280 movi r2, 128 + 24f6: 9323 ld.w r1, (r3, 0xc) + 24f8: 4244 lsli r2, r2, 4 + 24fa: 6848 and r1, r2 + 24fc: 3940 cmpnei r1, 0 + 24fe: 0c03 bf 0x2504 // 2504 + nop; + 2500: 6c03 mov r0, r0 + 2502: 07e5 br 0x24cc // 24cc + else if((SYSCON->MISR&HWD_ERR_ST)==HWD_ERR_ST) //Hardware Divider divisor = 0 interrupt + 2504: 3280 movi r2, 128 + 2506: 9323 ld.w r1, (r3, 0xc) + 2508: 4245 lsli r2, r2, 5 + 250a: 6848 and r1, r2 + 250c: 3940 cmpnei r1, 0 + 250e: 0bdf bt 0x24cc // 24cc + else if((SYSCON->MISR&EFL_ERR_ST)==EFL_ERR_ST) //Flash check fail interrupt + 2510: 3280 movi r2, 128 + 2512: 9323 ld.w r1, (r3, 0xc) + 2514: 4246 lsli r2, r2, 6 + 2516: 6848 and r1, r2 + 2518: 3940 cmpnei r1, 0 + 251a: 0bd9 bt 0x24cc // 24cc + else if((SYSCON->MISR&OPTERR_INT)==OPTERR_INT) //Option load fail interrupt + 251c: 3280 movi r2, 128 + 251e: 9323 ld.w r1, (r3, 0xc) + 2520: 4247 lsli r2, r2, 7 + 2522: 6848 and r1, r2 + 2524: 3940 cmpnei r1, 0 + 2526: 0bd3 bt 0x24cc // 24cc + else if((SYSCON->MISR&EM_CMLST_ST)==EM_CMLST_ST) //EMOSC clock monitor fail interrupt + 2528: 3280 movi r2, 128 + 252a: 9323 ld.w r1, (r3, 0xc) + 252c: 424b lsli r2, r2, 11 + 252e: 6848 and r1, r2 + 2530: 3940 cmpnei r1, 0 + 2532: 0bcd bt 0x24cc // 24cc + else if((SYSCON->MISR&EM_EVTRG0_ST)==EM_EVTRG0_ST) //Event Trigger Channel 0 Interrupt + 2534: 3280 movi r2, 128 + 2536: 9323 ld.w r1, (r3, 0xc) + 2538: 424c lsli r2, r2, 12 + 253a: 6848 and r1, r2 + 253c: 3940 cmpnei r1, 0 + 253e: 0bc7 bt 0x24cc // 24cc + else if((SYSCON->MISR&EM_EVTRG1_ST)==EM_EVTRG1_ST) //Event Trigger Channel 1 Interrupt + 2540: 3280 movi r2, 128 + 2542: 9323 ld.w r1, (r3, 0xc) + 2544: 424d lsli r2, r2, 13 + 2546: 6848 and r1, r2 + 2548: 3940 cmpnei r1, 0 + 254a: 0bc1 bt 0x24cc // 24cc + else if((SYSCON->MISR&EM_EVTRG2_ST)==EM_EVTRG2_ST) //Event Trigger Channel 2 Interrupt + 254c: 3280 movi r2, 128 + 254e: 9323 ld.w r1, (r3, 0xc) + 2550: 424e lsli r2, r2, 14 + 2552: 6848 and r1, r2 + 2554: 3940 cmpnei r1, 0 + 2556: 0bbb bt 0x24cc // 24cc + else if((SYSCON->MISR&EM_EVTRG3_ST)==EM_EVTRG3_ST) //Event Trigger Channel 3 Interrupt + 2558: 3280 movi r2, 128 + 255a: 9323 ld.w r1, (r3, 0xc) + 255c: 424f lsli r2, r2, 15 + 255e: 6848 and r1, r2 + 2560: 3940 cmpnei r1, 0 + 2562: 0bb5 bt 0x24cc // 24cc + else if((SYSCON->MISR&CMD_ERR_ST)==CMD_ERR_ST) //Command error interrupt + 2564: 3280 movi r2, 128 + 2566: 9323 ld.w r1, (r3, 0xc) + 2568: 4256 lsli r2, r2, 22 + 256a: 6848 and r1, r2 + 256c: 3940 cmpnei r1, 0 + 256e: 0baf bt 0x24cc // 24cc + 2570: 0799 br 0x24a2 // 24a2 + 2572: 0000 bkpt + 2574: 2000005c .long 0x2000005c + +Disassembly of section .text.IFCIntHandler: + +00002578 : +//IFC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void IFCIntHandler(void) +{ + 2578: 1460 nie + 257a: 1462 ipush + // ISR content ... + if(IFC->MISR&ERS_END_INT) + 257c: 1078 lrw r3, 0x20000060 // 25dc + 257e: 3101 movi r1, 1 + 2580: 9360 ld.w r3, (r3, 0x0) + 2582: 934b ld.w r2, (r3, 0x2c) + 2584: 6884 and r2, r1 + 2586: 3a40 cmpnei r2, 0 + 2588: 0c04 bf 0x2590 // 2590 + { + IFC->ICR=RGM_END_INT; + } + else if(IFC->MISR&PEP_END_INT) + { + IFC->ICR=PEP_END_INT; + 258a: b32c st.w r1, (r3, 0x30) + } + else if(IFC->MISR&OVW_ERR_INT) + { + IFC->ICR=OVW_ERR_INT; + } +} + 258c: 1463 ipop + 258e: 1461 nir + else if(IFC->MISR&RGM_END_INT) + 2590: 934b ld.w r2, (r3, 0x2c) + 2592: 3102 movi r1, 2 + 2594: 6884 and r2, r1 + 2596: 3a40 cmpnei r2, 0 + 2598: 0bf9 bt 0x258a // 258a + else if(IFC->MISR&PEP_END_INT) + 259a: 934b ld.w r2, (r3, 0x2c) + 259c: 3104 movi r1, 4 + 259e: 6884 and r2, r1 + 25a0: 3a40 cmpnei r2, 0 + 25a2: 0bf4 bt 0x258a // 258a + else if(IFC->MISR&PROT_ERR_INT) + 25a4: 3280 movi r2, 128 + 25a6: 932b ld.w r1, (r3, 0x2c) + 25a8: 4245 lsli r2, r2, 5 + 25aa: 6848 and r1, r2 + 25ac: 3940 cmpnei r1, 0 + 25ae: 0c03 bf 0x25b4 // 25b4 + IFC->ICR=OVW_ERR_INT; + 25b0: b34c st.w r2, (r3, 0x30) +} + 25b2: 07ed br 0x258c // 258c + else if(IFC->MISR&UDEF_ERR_INT) + 25b4: 3280 movi r2, 128 + 25b6: 932b ld.w r1, (r3, 0x2c) + 25b8: 4246 lsli r2, r2, 6 + 25ba: 6848 and r1, r2 + 25bc: 3940 cmpnei r1, 0 + 25be: 0bf9 bt 0x25b0 // 25b0 + else if(IFC->MISR&ADDR_ERR_INT) + 25c0: 3280 movi r2, 128 + 25c2: 932b ld.w r1, (r3, 0x2c) + 25c4: 4247 lsli r2, r2, 7 + 25c6: 6848 and r1, r2 + 25c8: 3940 cmpnei r1, 0 + 25ca: 0bf3 bt 0x25b0 // 25b0 + else if(IFC->MISR&OVW_ERR_INT) + 25cc: 3280 movi r2, 128 + 25ce: 932b ld.w r1, (r3, 0x2c) + 25d0: 4248 lsli r2, r2, 8 + 25d2: 6848 and r1, r2 + 25d4: 3940 cmpnei r1, 0 + 25d6: 0bed bt 0x25b0 // 25b0 + 25d8: 07da br 0x258c // 258c + 25da: 0000 bkpt + 25dc: 20000060 .long 0x20000060 + +Disassembly of section .text.ADCIntHandler: + +000025e0 : +//ADC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADCIntHandler(void) +{ + 25e0: 1460 nie + 25e2: 1462 ipush + // ISR content ... + if((ADC0->SR&ADC12_EOC)==ADC12_EOC) //ADC EOC interrupt + 25e4: 1078 lrw r3, 0x20000050 // 2644 + 25e6: 3101 movi r1, 1 + 25e8: 9360 ld.w r3, (r3, 0x0) + 25ea: 9348 ld.w r2, (r3, 0x20) + 25ec: 6884 and r2, r1 + 25ee: 3a40 cmpnei r2, 0 + 25f0: 0c04 bf 0x25f8 // 25f8 + { + ADC0->CSR = ADC12_CMP1H; + } + else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L) //ADC CMP1L interrupt. + { + ADC0->CSR = ADC12_CMP1L; + 25f2: b327 st.w r1, (r3, 0x1c) + } + else if((ADC0->SR&ADC12_SEQ_END0)==ADC12_SEQ_END0) //ADC SEQ0 interrupt,SEQ1~SEQ15 replace the parameter with ADC12_SEQ_END1~ADC12_SEQ_END15 + { + ADC0->CSR = ADC12_SEQ_END0; + } +} + 25f4: 1463 ipop + 25f6: 1461 nir + else if((ADC0->SR&ADC12_READY)==ADC12_READY) //ADC READY interrupt + 25f8: 9348 ld.w r2, (r3, 0x20) + 25fa: 3102 movi r1, 2 + 25fc: 6884 and r2, r1 + 25fe: 3a40 cmpnei r2, 0 + 2600: 0bf9 bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_OVR)==ADC12_OVR) //ADC OVR interrupt + 2602: 9348 ld.w r2, (r3, 0x20) + 2604: 3104 movi r1, 4 + 2606: 6884 and r2, r1 + 2608: 3a40 cmpnei r2, 0 + 260a: 0bf4 bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_CMP0H)==ADC12_CMP0H) //ADC CMP0H interrupt + 260c: 9348 ld.w r2, (r3, 0x20) + 260e: 3110 movi r1, 16 + 2610: 6884 and r2, r1 + 2612: 3a40 cmpnei r2, 0 + 2614: 0bef bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_CMP0L)==ADC12_CMP0L) //ADC CMP0L interrupt. + 2616: 9348 ld.w r2, (r3, 0x20) + 2618: 3120 movi r1, 32 + 261a: 6884 and r2, r1 + 261c: 3a40 cmpnei r2, 0 + 261e: 0bea bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_CMP1H)==ADC12_CMP1H) //ADC CMP1H interrupt. + 2620: 9348 ld.w r2, (r3, 0x20) + 2622: 3140 movi r1, 64 + 2624: 6884 and r2, r1 + 2626: 3a40 cmpnei r2, 0 + 2628: 0be5 bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L) //ADC CMP1L interrupt. + 262a: 9348 ld.w r2, (r3, 0x20) + 262c: 3180 movi r1, 128 + 262e: 6884 and r2, r1 + 2630: 3a40 cmpnei r2, 0 + 2632: 0be0 bt 0x25f2 // 25f2 + else if((ADC0->SR&ADC12_SEQ_END0)==ADC12_SEQ_END0) //ADC SEQ0 interrupt,SEQ1~SEQ15 replace the parameter with ADC12_SEQ_END1~ADC12_SEQ_END15 + 2634: 3280 movi r2, 128 + 2636: 9328 ld.w r1, (r3, 0x20) + 2638: 4249 lsli r2, r2, 9 + 263a: 6848 and r1, r2 + 263c: 3940 cmpnei r1, 0 + 263e: 0fdb bf 0x25f4 // 25f4 + ADC0->CSR = ADC12_SEQ_END0; + 2640: b347 st.w r2, (r3, 0x1c) +} + 2642: 07d9 br 0x25f4 // 25f4 + 2644: 20000050 .long 0x20000050 + +Disassembly of section .text.EPT0IntHandler: + +00002648 : +//EPT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT0IntHandler(void) +{ + 2648: 1460 nie + 264a: 1462 ipush + 264c: 14d1 push r4, r15 + // ISR content ... + if((EPT0->MISR&EPT_TRGEV0_INT)==EPT_TRGEV0_INT) //TRGEV0 interrupt + 264e: 1386 lrw r4, 0x20000020 // 27e4 + 2650: 3280 movi r2, 128 + 2652: 9460 ld.w r3, (r4, 0x0) + 2654: 60c8 addu r3, r2 + 2656: 9335 ld.w r1, (r3, 0x54) + 2658: 3001 movi r0, 1 + 265a: 6840 and r1, r0 + 265c: 3940 cmpnei r1, 0 + 265e: 0c03 bf 0x2664 // 2664 + EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT); + R_CMPB_BUF=EPT0->CMPB; //Duty counter + } + else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2) //Capture Load to CMPC interrupt + { + EPT0->ICR=EPT_CAP_LD2; + 2660: b317 st.w r0, (r3, 0x5c) + 2662: 0424 br 0x26aa // 26aa + else if((EPT0->MISR&EPT_TRGEV1_INT)==EPT_TRGEV1_INT) //TRGEV1 interrupt + 2664: 9335 ld.w r1, (r3, 0x54) + 2666: 3002 movi r0, 2 + 2668: 6840 and r1, r0 + 266a: 3940 cmpnei r1, 0 + 266c: 0bfa bt 0x2660 // 2660 + else if((EPT0->MISR&EPT_TRGEV2_INT)==EPT_TRGEV2_INT) //TRGEV2 interrupt + 266e: 9335 ld.w r1, (r3, 0x54) + 2670: 3004 movi r0, 4 + 2672: 6840 and r1, r0 + 2674: 3940 cmpnei r1, 0 + 2676: 0bf5 bt 0x2660 // 2660 + else if((EPT0->MISR&EPT_TRGEV3_INT)==EPT_TRGEV3_INT) //TRGEV3 interrupt + 2678: 9335 ld.w r1, (r3, 0x54) + 267a: 3008 movi r0, 8 + 267c: 6840 and r1, r0 + 267e: 3940 cmpnei r1, 0 + 2680: 0bf0 bt 0x2660 // 2660 + else if((EPT0->MISR&EPT_CAP_LD0)==EPT_CAP_LD0) //Capture Load to CMPA interrupt + 2682: 9335 ld.w r1, (r3, 0x54) + 2684: 3010 movi r0, 16 + 2686: 6840 and r1, r0 + 2688: 3940 cmpnei r1, 0 + 268a: 0c1f bf 0x26c8 // 26c8 + EPT0->ICR=EPT_CAP_LD0; + 268c: b317 st.w r0, (r3, 0x5c) + EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIRT); + 268e: 3200 movi r2, 0 + 2690: 3101 movi r1, 1 + 2692: 3000 movi r0, 0 + 2694: e3fff478 bsr 0xf84 // f84 + EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT); + 2698: 3201 movi r2, 1 + 269a: 3101 movi r1, 1 + 269c: 3001 movi r0, 1 + 269e: e3fff473 bsr 0xf84 // f84 + R_CMPA_BUF=EPT0->CMPA; //Low voltage counter + 26a2: 9460 ld.w r3, (r4, 0x0) + 26a4: 934b ld.w r2, (r3, 0x2c) + 26a6: 1271 lrw r3, 0x20000084 // 27e8 + R_CMPB_BUF=EPT0->CMPB; //Duty counter + 26a8: b340 st.w r2, (r3, 0x0) + else if((EPT0->MISR&EPT_PEND)==EPT_PEND) //End of cycle interrupt + { + EPT0->ICR=EPT_PEND; + } + //Emergency interruption + if((EPT0->EMMISR&EPT_EP0_EMINT)==EPT_EP0_EMINT) //interrupt flag of EP0 event + 26aa: 9460 ld.w r3, (r4, 0x0) + 26ac: 3280 movi r2, 128 + 26ae: 60c8 addu r3, r2 + 26b0: 932b ld.w r1, (r3, 0x2c) + 26b2: 3001 movi r0, 1 + 26b4: 6840 and r1, r0 + 26b6: 3940 cmpnei r1, 0 + 26b8: 0c5e bf 0x2774 // 2774 + { + EPT0->EMICR=EPT_EP5_EMINT; + } + else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT) //interrupt flag of EP6 event + { + EPT0->EMICR=EPT_EP6_EMINT; + 26ba: b30d st.w r0, (r3, 0x34) + } + else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT) //interrupt flag of EOM_FAULT event + { + EPT0->EMICR=EPT_EOM_FAULT_EMINT; + } +} + 26bc: d9ee2001 ld.w r15, (r14, 0x4) + 26c0: 9880 ld.w r4, (r14, 0x0) + 26c2: 1402 addi r14, r14, 8 + 26c4: 1463 ipop + 26c6: 1461 nir + else if((EPT0->MISR&EPT_CAP_LD1)==EPT_CAP_LD1) //Capture Load to CMPB interrupt + 26c8: 9335 ld.w r1, (r3, 0x54) + 26ca: 3020 movi r0, 32 + 26cc: 6840 and r1, r0 + 26ce: 3940 cmpnei r1, 0 + 26d0: 0c10 bf 0x26f0 // 26f0 + EPT0->ICR=EPT_CAP_LD1; + 26d2: b317 st.w r0, (r3, 0x5c) + EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIRT); + 26d4: 3200 movi r2, 0 + 26d6: 3101 movi r1, 1 + 26d8: 3001 movi r0, 1 + 26da: e3fff455 bsr 0xf84 // f84 + EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT); + 26de: 3201 movi r2, 1 + 26e0: 3101 movi r1, 1 + 26e2: 3000 movi r0, 0 + 26e4: e3fff450 bsr 0xf84 // f84 + R_CMPB_BUF=EPT0->CMPB; //Duty counter + 26e8: 9460 ld.w r3, (r4, 0x0) + 26ea: 934c ld.w r2, (r3, 0x30) + 26ec: 1260 lrw r3, 0x2000007c // 27ec + 26ee: 07dd br 0x26a8 // 26a8 + else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2) //Capture Load to CMPC interrupt + 26f0: 9335 ld.w r1, (r3, 0x54) + 26f2: 3040 movi r0, 64 + 26f4: 6840 and r1, r0 + 26f6: 3940 cmpnei r1, 0 + 26f8: 0bb4 bt 0x2660 // 2660 + else if((EPT0->MISR&EPT_CAP_LD3)==EPT_CAP_LD3) //Capture Load to CMPD interrupt + 26fa: 9335 ld.w r1, (r3, 0x54) + 26fc: 6848 and r1, r2 + 26fe: 3940 cmpnei r1, 0 + 2700: 0c03 bf 0x2706 // 2706 + EPT0->ICR=EPT_PEND; + 2702: b357 st.w r2, (r3, 0x5c) + 2704: 07d3 br 0x26aa // 26aa + else if((EPT0->MISR&EPT_CAU)==EPT_CAU) //Up-Counting phase CNT = CMPA interrupt + 2706: 3280 movi r2, 128 + 2708: 9335 ld.w r1, (r3, 0x54) + 270a: 4241 lsli r2, r2, 1 + 270c: 6848 and r1, r2 + 270e: 3940 cmpnei r1, 0 + 2710: 0bf9 bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CAD)==EPT_CAD) //Down-Counting phase CNT = CMPA interrupt + 2712: 3280 movi r2, 128 + 2714: 9335 ld.w r1, (r3, 0x54) + 2716: 4242 lsli r2, r2, 2 + 2718: 6848 and r1, r2 + 271a: 3940 cmpnei r1, 0 + 271c: 0bf3 bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CBU)==EPT_CBU) //Up-Counting phase CNT = CMPB interrupt + 271e: 3280 movi r2, 128 + 2720: 9335 ld.w r1, (r3, 0x54) + 2722: 4243 lsli r2, r2, 3 + 2724: 6848 and r1, r2 + 2726: 3940 cmpnei r1, 0 + 2728: 0bed bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CBD)==EPT_CBD) //Down-Counting phase CNT = CMPB interrupt + 272a: 3280 movi r2, 128 + 272c: 9335 ld.w r1, (r3, 0x54) + 272e: 4244 lsli r2, r2, 4 + 2730: 6848 and r1, r2 + 2732: 3940 cmpnei r1, 0 + 2734: 0be7 bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CCU)==EPT_CCU) //Up-Counting phase CNT = CMPC interrupt + 2736: 3280 movi r2, 128 + 2738: 9335 ld.w r1, (r3, 0x54) + 273a: 4245 lsli r2, r2, 5 + 273c: 6848 and r1, r2 + 273e: 3940 cmpnei r1, 0 + 2740: 0be1 bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CCD)==EPT_CCD) //Down-Counting phase CNT = CMPC interrupt + 2742: 3280 movi r2, 128 + 2744: 9335 ld.w r1, (r3, 0x54) + 2746: 4246 lsli r2, r2, 6 + 2748: 6848 and r1, r2 + 274a: 3940 cmpnei r1, 0 + 274c: 0bdb bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CDU)==EPT_CDU) //Up-Counting phase CNT = CMPD interrupt + 274e: 3280 movi r2, 128 + 2750: 9335 ld.w r1, (r3, 0x54) + 2752: 4247 lsli r2, r2, 7 + 2754: 6848 and r1, r2 + 2756: 3940 cmpnei r1, 0 + 2758: 0bd5 bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_CDD)==EPT_CDD) //Down-Counting phase CNT = CMPD interrupt + 275a: 3280 movi r2, 128 + 275c: 9335 ld.w r1, (r3, 0x54) + 275e: 4248 lsli r2, r2, 8 + 2760: 6848 and r1, r2 + 2762: 3940 cmpnei r1, 0 + 2764: 0bcf bt 0x2702 // 2702 + else if((EPT0->MISR&EPT_PEND)==EPT_PEND) //End of cycle interrupt + 2766: 3280 movi r2, 128 + 2768: 9335 ld.w r1, (r3, 0x54) + 276a: 4249 lsli r2, r2, 9 + 276c: 6848 and r1, r2 + 276e: 3940 cmpnei r1, 0 + 2770: 0f9d bf 0x26aa // 26aa + 2772: 07c8 br 0x2702 // 2702 + else if((EPT0->EMMISR&EPT_EP1_EMINT)==EPT_EP1_EMINT) //interrupt flag of EP1 event + 2774: 932b ld.w r1, (r3, 0x2c) + 2776: 3002 movi r0, 2 + 2778: 6840 and r1, r0 + 277a: 3940 cmpnei r1, 0 + 277c: 0b9f bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP2_EMINT)==EPT_EP2_EMINT) //interrupt flag of EP2 event + 277e: 932b ld.w r1, (r3, 0x2c) + 2780: 3004 movi r0, 4 + 2782: 6840 and r1, r0 + 2784: 3940 cmpnei r1, 0 + 2786: 0b9a bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP3_EMINT)==EPT_EP3_EMINT) //interrupt flag of EP3 event + 2788: 932b ld.w r1, (r3, 0x2c) + 278a: 3008 movi r0, 8 + 278c: 6840 and r1, r0 + 278e: 3940 cmpnei r1, 0 + 2790: 0b95 bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP4_EMINT)==EPT_EP4_EMINT) //interrupt flag of EP4 event + 2792: 932b ld.w r1, (r3, 0x2c) + 2794: 3010 movi r0, 16 + 2796: 6840 and r1, r0 + 2798: 3940 cmpnei r1, 0 + 279a: 0b90 bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP5_EMINT)==EPT_EP5_EMINT) //interrupt flag of EP5 event + 279c: 932b ld.w r1, (r3, 0x2c) + 279e: 3020 movi r0, 32 + 27a0: 6840 and r1, r0 + 27a2: 3940 cmpnei r1, 0 + 27a4: 0b8b bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT) //interrupt flag of EP6 event + 27a6: 932b ld.w r1, (r3, 0x2c) + 27a8: 3040 movi r0, 64 + 27aa: 6840 and r1, r0 + 27ac: 3940 cmpnei r1, 0 + 27ae: 0b86 bt 0x26ba // 26ba + else if((EPT0->EMMISR&EPT_EP7_EMINT)==EPT_EP7_EMINT) //interrupt flag of EP7 event + 27b0: 932b ld.w r1, (r3, 0x2c) + 27b2: 6848 and r1, r2 + 27b4: 3940 cmpnei r1, 0 + 27b6: 0c03 bf 0x27bc // 27bc + EPT0->EMICR=EPT_EOM_FAULT_EMINT; + 27b8: b34d st.w r2, (r3, 0x34) +} + 27ba: 0781 br 0x26bc // 26bc + else if((EPT0->EMMISR&EPT_CPU_FAULT_EMINT)==EPT_CPU_FAULT_EMINT) //interrupt flag of CPU_FAULT event + 27bc: 3280 movi r2, 128 + 27be: 932b ld.w r1, (r3, 0x2c) + 27c0: 4241 lsli r2, r2, 1 + 27c2: 6848 and r1, r2 + 27c4: 3940 cmpnei r1, 0 + 27c6: 0bf9 bt 0x27b8 // 27b8 + else if((EPT0->EMMISR&EPT_MEM_FAULT_EMINT)==EPT_MEM_FAULT_EMINT) //interrupt flag of MEM_FAULT event + 27c8: 3280 movi r2, 128 + 27ca: 932b ld.w r1, (r3, 0x2c) + 27cc: 4242 lsli r2, r2, 2 + 27ce: 6848 and r1, r2 + 27d0: 3940 cmpnei r1, 0 + 27d2: 0bf3 bt 0x27b8 // 27b8 + else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT) //interrupt flag of EOM_FAULT event + 27d4: 3280 movi r2, 128 + 27d6: 932b ld.w r1, (r3, 0x2c) + 27d8: 4243 lsli r2, r2, 3 + 27da: 6848 and r1, r2 + 27dc: 3940 cmpnei r1, 0 + 27de: 0bed bt 0x27b8 // 27b8 + 27e0: 076e br 0x26bc // 26bc + 27e2: 0000 bkpt + 27e4: 20000020 .long 0x20000020 + 27e8: 20000084 .long 0x20000084 + 27ec: 2000007c .long 0x2000007c + +Disassembly of section .text.WWDTHandler: + +000027f0 : +//WWDT Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDTHandler(void) +{ + 27f0: 1460 nie + 27f2: 1462 ipush + 27f4: 14d2 push r4-r5, r15 + WWDT->ICR=0X01; + 27f6: 10ab lrw r5, 0x20000010 // 2820 + 27f8: 3401 movi r4, 1 + 27fa: 9560 ld.w r3, (r5, 0x0) + 27fc: b385 st.w r4, (r3, 0x14) + WWDT_CNT_Load(0xFF); + 27fe: 30ff movi r0, 255 + 2800: e3fff55a bsr 0x12b4 // 12b4 + if((WWDT->MISR&WWDT_EVI)==WWDT_EVI) //WWDT EVI interrupt + 2804: 9540 ld.w r2, (r5, 0x0) + 2806: 9263 ld.w r3, (r2, 0xc) + 2808: 68d0 and r3, r4 + 280a: 3b40 cmpnei r3, 0 + 280c: 0c02 bf 0x2810 // 2810 + { + WWDT->ICR = WWDT_EVI; + 280e: b285 st.w r4, (r2, 0x14) + } +} + 2810: d9ee2002 ld.w r15, (r14, 0x8) + 2814: 98a1 ld.w r5, (r14, 0x4) + 2816: 9880 ld.w r4, (r14, 0x0) + 2818: 1403 addi r14, r14, 12 + 281a: 1463 ipop + 281c: 1461 nir + 281e: 0000 bkpt + 2820: 20000010 .long 0x20000010 + +Disassembly of section .text.GPT0IntHandler: + +00002824 : +//GPT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT0IntHandler(void) +{ + 2824: 1460 nie + 2826: 1462 ipush + 2828: 14d0 push r15 + // ISR content ... + if((GPT0->MISR&GPT_INT_TRGEV0)==GPT_INT_TRGEV0) //TRGEV0 interrupt + 282a: 1161 lrw r3, 0x20000024 // 28ac + 282c: 3101 movi r1, 1 + 282e: 9360 ld.w r3, (r3, 0x0) + 2830: 237f addi r3, 128 + 2832: 9355 ld.w r2, (r3, 0x54) + 2834: 6884 and r2, r1 + 2836: 3a40 cmpnei r2, 0 + 2838: 0c07 bf 0x2846 // 2846 + { + GPT0->ICR = GPT_INT_CAPLD0; + } + else if((GPT0->MISR&GPT_INT_CAPLD1)==GPT_INT_CAPLD1) //Capture Load to CMPB interrupt + { + GPT0->ICR = GPT_INT_CAPLD1; + 283a: b337 st.w r1, (r3, 0x5c) + GPT0->ICR = GPT_INT_PEND; + + //2024-06-16 修改 单独用于PWM 1ms定时控制 + PWM_Timer_1ms_Task(); + } +} + 283c: d9ee2000 ld.w r15, (r14, 0x0) + 2840: 1401 addi r14, r14, 4 + 2842: 1463 ipop + 2844: 1461 nir + else if((GPT0->MISR&GPT_INT_TRGEV1)==GPT_INT_TRGEV1) //TRGEV1 interrupt + 2846: 9355 ld.w r2, (r3, 0x54) + 2848: 3102 movi r1, 2 + 284a: 6884 and r2, r1 + 284c: 3a40 cmpnei r2, 0 + 284e: 0bf6 bt 0x283a // 283a + else if((GPT0->MISR&GPT_INT_CAPLD0)==GPT_INT_CAPLD0) //Capture Load to CMPA interrupt + 2850: 9355 ld.w r2, (r3, 0x54) + 2852: 3110 movi r1, 16 + 2854: 6884 and r2, r1 + 2856: 3a40 cmpnei r2, 0 + 2858: 0bf1 bt 0x283a // 283a + else if((GPT0->MISR&GPT_INT_CAPLD1)==GPT_INT_CAPLD1) //Capture Load to CMPB interrupt + 285a: 9355 ld.w r2, (r3, 0x54) + 285c: 3120 movi r1, 32 + 285e: 6884 and r2, r1 + 2860: 3a40 cmpnei r2, 0 + 2862: 0bec bt 0x283a // 283a + else if((GPT0->MISR&GPT_INT_CAU)==GPT_INT_CAU) //Up-Counting phase CNT = CMPA Interrupt + 2864: 3280 movi r2, 128 + 2866: 9335 ld.w r1, (r3, 0x54) + 2868: 4241 lsli r2, r2, 1 + 286a: 6848 and r1, r2 + 286c: 3940 cmpnei r1, 0 + 286e: 0c03 bf 0x2874 // 2874 + GPT0->ICR = GPT_INT_CBD; + 2870: b357 st.w r2, (r3, 0x5c) + 2872: 07e5 br 0x283c // 283c + else if((GPT0->MISR&GPT_INT_CAD)==GPT_INT_CAD) //Down-Counting phase CNT = CMPA Interrupt + 2874: 3280 movi r2, 128 + 2876: 9335 ld.w r1, (r3, 0x54) + 2878: 4242 lsli r2, r2, 2 + 287a: 6848 and r1, r2 + 287c: 3940 cmpnei r1, 0 + 287e: 0bf9 bt 0x2870 // 2870 + else if((GPT0->MISR&GPT_INT_CBU)==GPT_INT_CBU) //Up-Counting phase CNT = CMPB Interrupt + 2880: 3280 movi r2, 128 + 2882: 9335 ld.w r1, (r3, 0x54) + 2884: 4243 lsli r2, r2, 3 + 2886: 6848 and r1, r2 + 2888: 3940 cmpnei r1, 0 + 288a: 0bf3 bt 0x2870 // 2870 + else if((GPT0->MISR&GPT_INT_CBD)==GPT_INT_CBD) //Down-Counting phase CNT = CMPB Interrupt + 288c: 3280 movi r2, 128 + 288e: 9335 ld.w r1, (r3, 0x54) + 2890: 4244 lsli r2, r2, 4 + 2892: 6848 and r1, r2 + 2894: 3940 cmpnei r1, 0 + 2896: 0bed bt 0x2870 // 2870 + else if((GPT0->MISR&GPT_INT_PEND)==GPT_INT_PEND) //End of cycle interrupt + 2898: 3280 movi r2, 128 + 289a: 9335 ld.w r1, (r3, 0x54) + 289c: 4249 lsli r2, r2, 9 + 289e: 6848 and r1, r2 + 28a0: 3940 cmpnei r1, 0 + 28a2: 0fcd bf 0x283c // 283c + GPT0->ICR = GPT_INT_PEND; + 28a4: b357 st.w r2, (r3, 0x5c) + PWM_Timer_1ms_Task(); + 28a6: e0001435 bsr 0x5110 // 5110 +} + 28aa: 07c9 br 0x283c // 283c + 28ac: 20000024 .long 0x20000024 + +Disassembly of section .text.RTCIntHandler: + +000028b0 : +//RTC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTCIntHandler(void) +{ + 28b0: 1460 nie + 28b2: 1462 ipush + // ISR content ... + if((RTC->MISR&ALRA_INT)==ALRA_INT) //Interrupt of alarm A + 28b4: 1079 lrw r3, 0x20000018 // 2918 + 28b6: 3101 movi r1, 1 + 28b8: 9360 ld.w r3, (r3, 0x0) + 28ba: 934a ld.w r2, (r3, 0x28) + 28bc: 6884 and r2, r1 + 28be: 3a40 cmpnei r2, 0 + 28c0: 0c14 bf 0x28e8 // 28e8 + { + RTC->ICR=ALRA_INT; + RTC->KEY=0XCA53; + 28c2: 1057 lrw r2, 0xca53 // 291c + RTC->ICR=ALRA_INT; + 28c4: b32b st.w r1, (r3, 0x2c) + RTC->KEY=0XCA53; + 28c6: b34c st.w r2, (r3, 0x30) + RTC->CR=RTC->CR|0x01; + 28c8: 9342 ld.w r2, (r3, 0x8) + 28ca: 6c84 or r2, r1 + 28cc: b342 st.w r2, (r3, 0x8) + RTC->TIMR=(0x10<<16)|(0x00<<8)|(0x00); //Hour bit6->0:am 1:pm + 28ce: 3280 movi r2, 128 + 28d0: 424d lsli r2, r2, 13 + 28d2: b340 st.w r2, (r3, 0x0) + while(RTC->CR&0x02); //busy TIMR DATR ALRAR ALRBR Update done + 28d4: 3102 movi r1, 2 + 28d6: 9342 ld.w r2, (r3, 0x8) + 28d8: 6884 and r2, r1 + 28da: 3a40 cmpnei r2, 0 + 28dc: 0bfd bt 0x28d6 // 28d6 + RTC->CR &= ~0x1; + 28de: 9342 ld.w r2, (r3, 0x8) + 28e0: 3a80 bclri r2, 0 + 28e2: b342 st.w r2, (r3, 0x8) + } + else if((RTC->MISR&RTC_TRGEV1_INT)==RTC_TRGEV1_INT) //Interrupt of trigger event 1 + { + RTC->ICR=RTC_TRGEV1_INT; + } +} + 28e4: 1463 ipop + 28e6: 1461 nir + else if((RTC->MISR&ALRB_INT)==ALRB_INT) //Interrupt of alarm B + 28e8: 934a ld.w r2, (r3, 0x28) + 28ea: 3102 movi r1, 2 + 28ec: 6884 and r2, r1 + 28ee: 3a40 cmpnei r2, 0 + 28f0: 0c03 bf 0x28f6 // 28f6 + RTC->ICR=RTC_TRGEV1_INT; + 28f2: b32b st.w r1, (r3, 0x2c) +} + 28f4: 07f8 br 0x28e4 // 28e4 + else if((RTC->MISR&CPRD_INT)==CPRD_INT) //Interrupt of alarm CPRD + 28f6: 934a ld.w r2, (r3, 0x28) + 28f8: 3104 movi r1, 4 + 28fa: 6884 and r2, r1 + 28fc: 3a40 cmpnei r2, 0 + 28fe: 0bfa bt 0x28f2 // 28f2 + else if((RTC->MISR&RTC_TRGEV0_INT)==RTC_TRGEV0_INT) //Interrupt of trigger event 0 + 2900: 934a ld.w r2, (r3, 0x28) + 2902: 3108 movi r1, 8 + 2904: 6884 and r2, r1 + 2906: 3a40 cmpnei r2, 0 + 2908: 0bf5 bt 0x28f2 // 28f2 + else if((RTC->MISR&RTC_TRGEV1_INT)==RTC_TRGEV1_INT) //Interrupt of trigger event 1 + 290a: 934a ld.w r2, (r3, 0x28) + 290c: 3110 movi r1, 16 + 290e: 6884 and r2, r1 + 2910: 3a40 cmpnei r2, 0 + 2912: 0bf0 bt 0x28f2 // 28f2 + 2914: 07e8 br 0x28e4 // 28e4 + 2916: 0000 bkpt + 2918: 20000018 .long 0x20000018 + 291c: 0000ca53 .long 0x0000ca53 + +Disassembly of section .text.UART0IntHandler: + +00002920 : +//UART0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0IntHandler(void) +{ + 2920: 1460 nie + 2922: 1462 ipush + 2924: 14d0 push r15 + char inchar = 0; + + // ISR content ... + if ((UART0->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + 2926: 1073 lrw r3, 0x20000040 // 2970 + 2928: 3102 movi r1, 2 + 292a: 9360 ld.w r3, (r3, 0x0) + 292c: 9343 ld.w r2, (r3, 0xc) + 292e: 6884 and r2, r1 + 2930: 3a40 cmpnei r2, 0 + 2932: 0c08 bf 0x2942 // 2942 + { + UART0->ISR=UART_RX_INT_S; + 2934: b323 st.w r1, (r3, 0xc) + inchar = CSP_UART_GET_DATA(UART0); + 2936: 9360 ld.w r3, (r3, 0x0) + } + else if ((UART0->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART0->ISR=UART_TX_IOV_S; + } +} + 2938: d9ee2000 ld.w r15, (r14, 0x0) + 293c: 1401 addi r14, r14, 4 + 293e: 1463 ipop + 2940: 1461 nir + else if( (UART0->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + 2942: 9343 ld.w r2, (r3, 0xc) + 2944: 3101 movi r1, 1 + 2946: 6884 and r2, r1 + 2948: 3a40 cmpnei r2, 0 + 294a: 0c05 bf 0x2954 // 2954 + UART0->ISR=UART_TX_INT_S; + 294c: b323 st.w r1, (r3, 0xc) + PB_Send_String_INT(); + 294e: e0000431 bsr 0x31b0 // 31b0 + 2952: 07f3 br 0x2938 // 2938 + else if ((UART0->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + 2954: 9343 ld.w r2, (r3, 0xc) + 2956: 3108 movi r1, 8 + 2958: 6884 and r2, r1 + 295a: 3a40 cmpnei r2, 0 + 295c: 0c03 bf 0x2962 // 2962 + UART0->ISR=UART_TX_IOV_S; + 295e: b323 st.w r1, (r3, 0xc) +} + 2960: 07ec br 0x2938 // 2938 + else if ((UART0->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + 2962: 9343 ld.w r2, (r3, 0xc) + 2964: 3104 movi r1, 4 + 2966: 6884 and r2, r1 + 2968: 3a40 cmpnei r2, 0 + 296a: 0bfa bt 0x295e // 295e + 296c: 07e6 br 0x2938 // 2938 + 296e: 0000 bkpt + 2970: 20000040 .long 0x20000040 + +Disassembly of section .text.UART1IntHandler: + +00002974 : +//UART1 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1IntHandler(void) +{ + 2974: 1460 nie + 2976: 1462 ipush + 2978: 14d0 push r15 + char inchar = 0; + + // ISR content ... + if ((UART1->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + 297a: 1072 lrw r3, 0x2000003c // 29c0 + 297c: 3102 movi r1, 2 + 297e: 9360 ld.w r3, (r3, 0x0) + 2980: 9343 ld.w r2, (r3, 0xc) + 2982: 6884 and r2, r1 + 2984: 3a40 cmpnei r2, 0 + 2986: 0c0b bf 0x299c // 299c + { + UART1->ISR=UART_RX_INT_S; + 2988: b323 st.w r1, (r3, 0xc) + inchar = CSP_UART_GET_DATA(UART1); + 298a: 9300 ld.w r0, (r3, 0x0) + UART1_RecvINT_Processing(inchar); + 298c: 7400 zextb r0, r0 + 298e: e00002c3 bsr 0x2f14 // 2f14 + } + else if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART1->ISR=UART_TX_IOV_S; + } +} + 2992: d9ee2000 ld.w r15, (r14, 0x0) + 2996: 1401 addi r14, r14, 4 + 2998: 1463 ipop + 299a: 1461 nir + else if( (UART1->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + 299c: 9343 ld.w r2, (r3, 0xc) + 299e: 3101 movi r1, 1 + 29a0: 6884 and r2, r1 + 29a2: 3a40 cmpnei r2, 0 + 29a4: 0c03 bf 0x29aa // 29aa + UART1->ISR=UART_TX_IOV_S; + 29a6: b323 st.w r1, (r3, 0xc) +} + 29a8: 07f5 br 0x2992 // 2992 + else if ((UART1->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + 29aa: 9343 ld.w r2, (r3, 0xc) + 29ac: 3108 movi r1, 8 + 29ae: 6884 and r2, r1 + 29b0: 3a40 cmpnei r2, 0 + 29b2: 0bfa bt 0x29a6 // 29a6 + else if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + 29b4: 9343 ld.w r2, (r3, 0xc) + 29b6: 3104 movi r1, 4 + 29b8: 6884 and r2, r1 + 29ba: 3a40 cmpnei r2, 0 + 29bc: 0bf5 bt 0x29a6 // 29a6 + 29be: 07ea br 0x2992 // 2992 + 29c0: 2000003c .long 0x2000003c + +Disassembly of section .text.UART2IntHandler: + +000029c4 : +//UART2 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2IntHandler(void) +{ + 29c4: 1460 nie + 29c6: 1462 ipush + // ISR content ... + if ((UART2->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + 29c8: 106d lrw r3, 0x20000038 // 29fc + 29ca: 3102 movi r1, 2 + 29cc: 9360 ld.w r3, (r3, 0x0) + 29ce: 9343 ld.w r2, (r3, 0xc) + 29d0: 6884 and r2, r1 + 29d2: 3a40 cmpnei r2, 0 + 29d4: 0c03 bf 0x29da // 29da + { + UART2->ISR=UART_RX_IOV_S; + } + else if ((UART2->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART2->ISR=UART_TX_IOV_S; + 29d6: b323 st.w r1, (r3, 0xc) + } +} + 29d8: 0410 br 0x29f8 // 29f8 + else if( (UART2->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + 29da: 9343 ld.w r2, (r3, 0xc) + 29dc: 3101 movi r1, 1 + 29de: 6884 and r2, r1 + 29e0: 3a40 cmpnei r2, 0 + 29e2: 0bfa bt 0x29d6 // 29d6 + else if ((UART2->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + 29e4: 9343 ld.w r2, (r3, 0xc) + 29e6: 3108 movi r1, 8 + 29e8: 6884 and r2, r1 + 29ea: 3a40 cmpnei r2, 0 + 29ec: 0bf5 bt 0x29d6 // 29d6 + else if ((UART2->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + 29ee: 9343 ld.w r2, (r3, 0xc) + 29f0: 3104 movi r1, 4 + 29f2: 6884 and r2, r1 + 29f4: 3a40 cmpnei r2, 0 + 29f6: 0bf0 bt 0x29d6 // 29d6 +} + 29f8: 1463 ipop + 29fa: 1461 nir + 29fc: 20000038 .long 0x20000038 + +Disassembly of section .text.SPI0IntHandler: + +00002a00 : +//SPI Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI0IntHandler(void) +{ + 2a00: 1460 nie + 2a02: 1462 ipush + // ISR content ... + if((SPI0->MISR&SPI_PORIM)==SPI_PORIM) //Receive Overrun Interrupt + 2a04: 1178 lrw r3, 0x20000034 // 2ae4 + 2a06: 3101 movi r1, 1 + 2a08: 9360 ld.w r3, (r3, 0x0) + 2a0a: 9347 ld.w r2, (r3, 0x1c) + 2a0c: 6884 and r2, r1 + 2a0e: 3a40 cmpnei r2, 0 + 2a10: 0c03 bf 0x2a16 // 2a16 + } + } + } + else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM) //Transmit FIFO Interrupt + { + SPI0->ICR = SPI_TXIM; + 2a12: b328 st.w r1, (r3, 0x20) + } + +} + 2a14: 0407 br 0x2a22 // 2a22 + else if((SPI0->MISR&SPI_RTIM)==SPI_RTIM) //Receive Timeout Interrupt + 2a16: 9347 ld.w r2, (r3, 0x1c) + 2a18: 3002 movi r0, 2 + 2a1a: 6880 and r2, r0 + 2a1c: 3a40 cmpnei r2, 0 + 2a1e: 0c04 bf 0x2a26 // 2a26 + SPI0->ICR = SPI_RTIM; + 2a20: b308 st.w r0, (r3, 0x20) +} + 2a22: 1463 ipop + 2a24: 1461 nir + else if((SPI0->MISR&SPI_RXIM)==SPI_RXIM) //Receive FIFO Interrupt,FIFO can be set 1/8,1/4,1/2 FIFO Interrupt + 2a26: 9347 ld.w r2, (r3, 0x1c) + 2a28: 3004 movi r0, 4 + 2a2a: 6880 and r2, r0 + 2a2c: 3a40 cmpnei r2, 0 + 2a2e: 0c55 bf 0x2ad8 // 2ad8 + SPI0->ICR = SPI_RXIM; + 2a30: b308 st.w r0, (r3, 0x20) + if(SPI0->DR==0xaa) + 2a32: 9302 ld.w r0, (r3, 0x8) + 2a34: 32aa movi r2, 170 + 2a36: 6482 cmpne r0, r2 + 2a38: 083e bt 0x2ab4 // 2ab4 + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + 2a3a: 3102 movi r1, 2 + 2a3c: 9343 ld.w r2, (r3, 0xc) + 2a3e: 6884 and r2, r1 + 2a40: 3a40 cmpnei r2, 0 + 2a42: 0ffd bf 0x2a3c // 2a3c + SPI0->DR = 0x11; + 2a44: 3211 movi r2, 17 + 2a46: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2a48: 3110 movi r1, 16 + 2a4a: 9343 ld.w r2, (r3, 0xc) + 2a4c: 6884 and r2, r1 + 2a4e: 3a40 cmpnei r2, 0 + 2a50: 0bfd bt 0x2a4a // 2a4a + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + 2a52: 3102 movi r1, 2 + 2a54: 9343 ld.w r2, (r3, 0xc) + 2a56: 6884 and r2, r1 + 2a58: 3a40 cmpnei r2, 0 + 2a5a: 0ffd bf 0x2a54 // 2a54 + SPI0->DR = 0x12; + 2a5c: 3212 movi r2, 18 + 2a5e: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2a60: 3110 movi r1, 16 + 2a62: 9343 ld.w r2, (r3, 0xc) + 2a64: 6884 and r2, r1 + 2a66: 3a40 cmpnei r2, 0 + 2a68: 0bfd bt 0x2a62 // 2a62 + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + 2a6a: 3102 movi r1, 2 + 2a6c: 9343 ld.w r2, (r3, 0xc) + 2a6e: 6884 and r2, r1 + 2a70: 3a40 cmpnei r2, 0 + 2a72: 0ffd bf 0x2a6c // 2a6c + SPI0->DR = 0x13; + 2a74: 3213 movi r2, 19 + 2a76: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2a78: 3110 movi r1, 16 + 2a7a: 9343 ld.w r2, (r3, 0xc) + 2a7c: 6884 and r2, r1 + 2a7e: 3a40 cmpnei r2, 0 + 2a80: 0bfd bt 0x2a7a // 2a7a + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + 2a82: 3102 movi r1, 2 + 2a84: 9343 ld.w r2, (r3, 0xc) + 2a86: 6884 and r2, r1 + 2a88: 3a40 cmpnei r2, 0 + 2a8a: 0ffd bf 0x2a84 // 2a84 + SPI0->DR = 0x14; + 2a8c: 3214 movi r2, 20 + 2a8e: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2a90: 3110 movi r1, 16 + 2a92: 9343 ld.w r2, (r3, 0xc) + 2a94: 6884 and r2, r1 + 2a96: 3a40 cmpnei r2, 0 + 2a98: 0bfd bt 0x2a92 // 2a92 + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + 2a9a: 3102 movi r1, 2 + 2a9c: 9343 ld.w r2, (r3, 0xc) + 2a9e: 6884 and r2, r1 + 2aa0: 3a40 cmpnei r2, 0 + 2aa2: 0ffd bf 0x2a9c // 2a9c + SPI0->DR = 0x15; + 2aa4: 3215 movi r2, 21 + 2aa6: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2aa8: 3110 movi r1, 16 + 2aaa: 9343 ld.w r2, (r3, 0xc) + 2aac: 6884 and r2, r1 + 2aae: 3a40 cmpnei r2, 0 + 2ab0: 0bfd bt 0x2aaa // 2aaa + 2ab2: 07b8 br 0x2a22 // 2a22 + if(((SPI0->SR) & SSP_TFE)!=SSP_TFE) + 2ab4: 9343 ld.w r2, (r3, 0xc) + 2ab6: 6884 and r2, r1 + 2ab8: 3a40 cmpnei r2, 0 + 2aba: 0bb4 bt 0x2a22 // 2a22 + SPI0->DR=0x0; //FIFO=0 + 2abc: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2abe: 3110 movi r1, 16 + SPI0->DR=0x0; //FIFO=0 + 2ac0: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2ac2: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2ac4: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2ac6: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2ac8: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2aca: b342 st.w r2, (r3, 0x8) + SPI0->DR=0x0; //FIFO=0 + 2acc: b342 st.w r2, (r3, 0x8) + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + 2ace: 9343 ld.w r2, (r3, 0xc) + 2ad0: 6884 and r2, r1 + 2ad2: 3a40 cmpnei r2, 0 + 2ad4: 0bfd bt 0x2ace // 2ace + 2ad6: 07a6 br 0x2a22 // 2a22 + else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM) //Transmit FIFO Interrupt + 2ad8: 9347 ld.w r2, (r3, 0x1c) + 2ada: 3108 movi r1, 8 + 2adc: 6884 and r2, r1 + 2ade: 3a40 cmpnei r2, 0 + 2ae0: 0b99 bt 0x2a12 // 2a12 + 2ae2: 07a0 br 0x2a22 // 2a22 + 2ae4: 20000034 .long 0x20000034 + +Disassembly of section .text.SIO0IntHandler: + +00002ae8 : +//SIO Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO0IntHandler(void) +{ + 2ae8: 1460 nie + 2aea: 1462 ipush + delay_nms(10); + SIO0->TXBUF=(0x03<<30)|(0x02<<28)|(0x03<<26)|(0x02<<24)|(0x03<<22)|(0x02<<20)|(0x03<<18)|(0x02<<16)| + (0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x00<<4)|(0x01<<2)|(0x0<<0); //0:D0,1:D1,2:DL,3:DH; + }*/ + + if(SIO0->MISR&0X02) //RXDNE + 2aec: 107d lrw r3, 0x2000002c // 2b60 + 2aee: 3102 movi r1, 2 + 2af0: 9360 ld.w r3, (r3, 0x0) + 2af2: 9349 ld.w r2, (r3, 0x24) + 2af4: 6884 and r2, r1 + 2af6: 3a40 cmpnei r2, 0 + 2af8: 0c13 bf 0x2b1e // 2b1e + { + SIO0->ICR=0X02; + 2afa: b32b st.w r1, (r3, 0x2c) + if(R_SIORX_count>=1) + 2afc: 101a lrw r0, 0x20000088 // 2b64 + 2afe: 9040 ld.w r2, (r0, 0x0) + 2b00: 3a20 cmplti r2, 1 + 2b02: 080c bt 0x2b1a // 2b1a + { + R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF&0xff000000; //8bit + 2b04: 9040 ld.w r2, (r0, 0x0) + 2b06: 9327 ld.w r1, (r3, 0x1c) + 2b08: 4938 lsri r1, r1, 24 + 2b0a: 4262 lsli r3, r2, 2 + 2b0c: 1057 lrw r2, 0x2000008c // 2b68 + 2b0e: 4138 lsli r1, r1, 24 + 2b10: 60c8 addu r3, r2 + 2b12: b320 st.w r1, (r3, 0x0) + nop; + 2b14: 6c03 mov r0, r0 + R_SIORX_count=0; + 2b16: 3300 movi r3, 0 + 2b18: b060 st.w r3, (r0, 0x0) + } + else if(SIO0->MISR&0X020) //TIMEOUT + { + SIO0->ICR=0X20; + } +} + 2b1a: 1463 ipop + 2b1c: 1461 nir + else if(SIO0->MISR&0X08) //RXBUFFULL + 2b1e: 9349 ld.w r2, (r3, 0x24) + 2b20: 3108 movi r1, 8 + 2b22: 6884 and r2, r1 + 2b24: 3a40 cmpnei r2, 0 + 2b26: 0c10 bf 0x2b46 // 2b46 + SIO0->ICR=0X08; + 2b28: b32b st.w r1, (r3, 0x2c) + if(R_SIORX_count<1) + 2b2a: 102f lrw r1, 0x20000088 // 2b64 + 2b2c: 9140 ld.w r2, (r1, 0x0) + 2b2e: 3a20 cmplti r2, 1 + 2b30: 0ff5 bf 0x2b1a // 2b1a + R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF; //32bit + 2b32: 9140 ld.w r2, (r1, 0x0) + 2b34: 9307 ld.w r0, (r3, 0x1c) + 2b36: 4262 lsli r3, r2, 2 + 2b38: 104c lrw r2, 0x2000008c // 2b68 + 2b3a: 60c8 addu r3, r2 + 2b3c: b300 st.w r0, (r3, 0x0) + R_SIORX_count++; + 2b3e: 9160 ld.w r3, (r1, 0x0) + 2b40: 2300 addi r3, 1 + 2b42: b160 st.w r3, (r1, 0x0) + 2b44: 07eb br 0x2b1a // 2b1a + else if(SIO0->MISR&0X010) //BREAK + 2b46: 9349 ld.w r2, (r3, 0x24) + 2b48: 3110 movi r1, 16 + 2b4a: 6884 and r2, r1 + 2b4c: 3a40 cmpnei r2, 0 + 2b4e: 0c03 bf 0x2b54 // 2b54 + SIO0->ICR=0X20; + 2b50: b32b st.w r1, (r3, 0x2c) +} + 2b52: 07e4 br 0x2b1a // 2b1a + else if(SIO0->MISR&0X020) //TIMEOUT + 2b54: 9349 ld.w r2, (r3, 0x24) + 2b56: 3120 movi r1, 32 + 2b58: 6884 and r2, r1 + 2b5a: 3a40 cmpnei r2, 0 + 2b5c: 0bfa bt 0x2b50 // 2b50 + 2b5e: 07de br 0x2b1a // 2b1a + 2b60: 2000002c .long 0x2000002c + 2b64: 20000088 .long 0x20000088 + 2b68: 2000008c .long 0x2000008c + +Disassembly of section .text.EXI0IntHandler: + +00002b6c : +//EXT0/16 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0IntHandler(void) +{ + 2b6c: 1460 nie + 2b6e: 1462 ipush + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0) //EXT0 Interrupt + 2b70: 106a lrw r3, 0x2000005c // 2b98 + 2b72: 3101 movi r1, 1 + 2b74: 9360 ld.w r3, (r3, 0x0) + 2b76: 237f addi r3, 128 + 2b78: 934c ld.w r2, (r3, 0x30) + 2b7a: 6884 and r2, r1 + 2b7c: 3a40 cmpnei r2, 0 + 2b7e: 0c04 bf 0x2b86 // 2b86 + { + SYSCON->EXICR = EXI_PIN0; + 2b80: b32b st.w r1, (r3, 0x2c) + } + else if ((SYSCON->EXIRS&EXI_PIN16)==EXI_PIN16) //EXT16 Interrupt + { + SYSCON->EXICR = EXI_PIN16; + } +} + 2b82: 1463 ipop + 2b84: 1461 nir + else if ((SYSCON->EXIRS&EXI_PIN16)==EXI_PIN16) //EXT16 Interrupt + 2b86: 3280 movi r2, 128 + 2b88: 932c ld.w r1, (r3, 0x30) + 2b8a: 4249 lsli r2, r2, 9 + 2b8c: 6848 and r1, r2 + 2b8e: 3940 cmpnei r1, 0 + 2b90: 0ff9 bf 0x2b82 // 2b82 + SYSCON->EXICR = EXI_PIN16; + 2b92: b34b st.w r2, (r3, 0x2c) +} + 2b94: 07f7 br 0x2b82 // 2b82 + 2b96: 0000 bkpt + 2b98: 2000005c .long 0x2000005c + +Disassembly of section .text.EXI1IntHandler: + +00002b9c : +//EXT1/17 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1IntHandler(void) +{ + 2b9c: 1460 nie + 2b9e: 1462 ipush + 2ba0: 14d0 push r15 + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1) //EXT1 Interrupt + 2ba2: 106d lrw r3, 0x2000005c // 2bd4 + 2ba4: 3102 movi r1, 2 + 2ba6: 9360 ld.w r3, (r3, 0x0) + 2ba8: 237f addi r3, 128 + 2baa: 934c ld.w r2, (r3, 0x30) + 2bac: 6884 and r2, r1 + 2bae: 3a40 cmpnei r2, 0 + 2bb0: 0c09 bf 0x2bc2 // 2bc2 + { + SYSCON->EXICR = EXI_PIN1; + 2bb2: b32b st.w r1, (r3, 0x2c) + PB_OVERCURR_PWR_BUS_INT_Processing(); + 2bb4: e0000372 bsr 0x3298 // 3298 + } + else if ((SYSCON->EXIRS&EXI_PIN17)==EXI_PIN17) //EXT17 Interrupt + { + SYSCON->EXICR = EXI_PIN17; + } +} + 2bb8: d9ee2000 ld.w r15, (r14, 0x0) + 2bbc: 1401 addi r14, r14, 4 + 2bbe: 1463 ipop + 2bc0: 1461 nir + else if ((SYSCON->EXIRS&EXI_PIN17)==EXI_PIN17) //EXT17 Interrupt + 2bc2: 3280 movi r2, 128 + 2bc4: 932c ld.w r1, (r3, 0x30) + 2bc6: 424a lsli r2, r2, 10 + 2bc8: 6848 and r1, r2 + 2bca: 3940 cmpnei r1, 0 + 2bcc: 0ff6 bf 0x2bb8 // 2bb8 + SYSCON->EXICR = EXI_PIN17; + 2bce: b34b st.w r2, (r3, 0x2c) +} + 2bd0: 07f4 br 0x2bb8 // 2bb8 + 2bd2: 0000 bkpt + 2bd4: 2000005c .long 0x2000005c + +Disassembly of section .text.EXI2to3IntHandler: + +00002bd8 : +//EXI2~3 18~19Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2to3IntHandler(void) +{ + 2bd8: 1460 nie + 2bda: 1462 ipush + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2) //EXT2 Interrupt + 2bdc: 1070 lrw r3, 0x2000005c // 2c1c + 2bde: 3104 movi r1, 4 + 2be0: 9360 ld.w r3, (r3, 0x0) + 2be2: 237f addi r3, 128 + 2be4: 934c ld.w r2, (r3, 0x30) + 2be6: 6884 and r2, r1 + 2be8: 3a40 cmpnei r2, 0 + 2bea: 0c04 bf 0x2bf2 // 2bf2 + { + SYSCON->EXICR = EXI_PIN2; + } + else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) //EXT3 Interrupt + { + SYSCON->EXICR = EXI_PIN3; + 2bec: b32b st.w r1, (r3, 0x2c) + } + else if ((SYSCON->EXIRS&EXI_PIN19)==EXI_PIN19) //EXT19 Interrupt + { + SYSCON->EXICR = EXI_PIN19; + } +} + 2bee: 1463 ipop + 2bf0: 1461 nir + else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) //EXT3 Interrupt + 2bf2: 934c ld.w r2, (r3, 0x30) + 2bf4: 3108 movi r1, 8 + 2bf6: 6884 and r2, r1 + 2bf8: 3a40 cmpnei r2, 0 + 2bfa: 0bf9 bt 0x2bec // 2bec + else if ((SYSCON->EXIRS&EXI_PIN18)==EXI_PIN18) //EXT18 Interrupt + 2bfc: 3280 movi r2, 128 + 2bfe: 932c ld.w r1, (r3, 0x30) + 2c00: 424b lsli r2, r2, 11 + 2c02: 6848 and r1, r2 + 2c04: 3940 cmpnei r1, 0 + 2c06: 0c03 bf 0x2c0c // 2c0c + SYSCON->EXICR = EXI_PIN19; + 2c08: b34b st.w r2, (r3, 0x2c) +} + 2c0a: 07f2 br 0x2bee // 2bee + else if ((SYSCON->EXIRS&EXI_PIN19)==EXI_PIN19) //EXT19 Interrupt + 2c0c: 3280 movi r2, 128 + 2c0e: 932c ld.w r1, (r3, 0x30) + 2c10: 424c lsli r2, r2, 12 + 2c12: 6848 and r1, r2 + 2c14: 3940 cmpnei r1, 0 + 2c16: 0bf9 bt 0x2c08 // 2c08 + 2c18: 07eb br 0x2bee // 2bee + 2c1a: 0000 bkpt + 2c1c: 2000005c .long 0x2000005c + +Disassembly of section .text.EXI4to9IntHandler: + +00002c20 : +//EXI4~9 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4to9IntHandler(void) +{ + 2c20: 1460 nie + 2c22: 1462 ipush + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4) //EXT4 Interrupt + 2c24: 1075 lrw r3, 0x2000005c // 2c78 + 2c26: 3280 movi r2, 128 + 2c28: 9360 ld.w r3, (r3, 0x0) + 2c2a: 60c8 addu r3, r2 + 2c2c: 932c ld.w r1, (r3, 0x30) + 2c2e: 3010 movi r0, 16 + 2c30: 6840 and r1, r0 + 2c32: 3940 cmpnei r1, 0 + 2c34: 0c04 bf 0x2c3c // 2c3c + { + SYSCON->EXICR = EXI_PIN5; + } + else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) //EXT6 Interrupt + { + SYSCON->EXICR = EXI_PIN6; + 2c36: b30b st.w r0, (r3, 0x2c) + else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) //EXT9 Interrupt + { + SYSCON->EXICR = EXI_PIN9; + } + +} + 2c38: 1463 ipop + 2c3a: 1461 nir + else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5) //EXT5 Interrupt + 2c3c: 932c ld.w r1, (r3, 0x30) + 2c3e: 3020 movi r0, 32 + 2c40: 6840 and r1, r0 + 2c42: 3940 cmpnei r1, 0 + 2c44: 0bf9 bt 0x2c36 // 2c36 + else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) //EXT6 Interrupt + 2c46: 932c ld.w r1, (r3, 0x30) + 2c48: 3040 movi r0, 64 + 2c4a: 6840 and r1, r0 + 2c4c: 3940 cmpnei r1, 0 + 2c4e: 0bf4 bt 0x2c36 // 2c36 + else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7) //EXT7 Interrupt + 2c50: 932c ld.w r1, (r3, 0x30) + 2c52: 6848 and r1, r2 + 2c54: 3940 cmpnei r1, 0 + 2c56: 0c03 bf 0x2c5c // 2c5c + SYSCON->EXICR = EXI_PIN9; + 2c58: b34b st.w r2, (r3, 0x2c) +} + 2c5a: 07ef br 0x2c38 // 2c38 + else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8) //EXT8 Interrupt + 2c5c: 3280 movi r2, 128 + 2c5e: 932c ld.w r1, (r3, 0x30) + 2c60: 4241 lsli r2, r2, 1 + 2c62: 6848 and r1, r2 + 2c64: 3940 cmpnei r1, 0 + 2c66: 0bf9 bt 0x2c58 // 2c58 + else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) //EXT9 Interrupt + 2c68: 3280 movi r2, 128 + 2c6a: 932c ld.w r1, (r3, 0x30) + 2c6c: 4242 lsli r2, r2, 2 + 2c6e: 6848 and r1, r2 + 2c70: 3940 cmpnei r1, 0 + 2c72: 0bf3 bt 0x2c58 // 2c58 + 2c74: 07e2 br 0x2c38 // 2c38 + 2c76: 0000 bkpt + 2c78: 2000005c .long 0x2000005c + +Disassembly of section .text.EXI10to15IntHandler: + +00002c7c : +//EXI4 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI10to15IntHandler(void) +{ + 2c7c: 1460 nie + 2c7e: 1462 ipush + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN10)==EXI_PIN10) //EXT10 Interrupt + 2c80: 1076 lrw r3, 0x2000005c // 2cd8 + 2c82: 3280 movi r2, 128 + 2c84: 9360 ld.w r3, (r3, 0x0) + 2c86: 237f addi r3, 128 + 2c88: 932c ld.w r1, (r3, 0x30) + 2c8a: 4243 lsli r2, r2, 3 + 2c8c: 6848 and r1, r2 + 2c8e: 3940 cmpnei r1, 0 + 2c90: 0c03 bf 0x2c96 // 2c96 + { + SYSCON->EXICR = EXI_PIN14; + } + else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) //EXT15 Interrupt + { + SYSCON->EXICR = EXI_PIN15; + 2c92: b34b st.w r2, (r3, 0x2c) + } +} + 2c94: 041f br 0x2cd2 // 2cd2 + else if ((SYSCON->EXIRS&EXI_PIN11)==EXI_PIN11) //EXT11 Interrupt + 2c96: 3280 movi r2, 128 + 2c98: 932c ld.w r1, (r3, 0x30) + 2c9a: 4244 lsli r2, r2, 4 + 2c9c: 6848 and r1, r2 + 2c9e: 3940 cmpnei r1, 0 + 2ca0: 0bf9 bt 0x2c92 // 2c92 + else if ((SYSCON->EXIRS&EXI_PIN12)==EXI_PIN12) //EXT12 Interrupt + 2ca2: 3280 movi r2, 128 + 2ca4: 932c ld.w r1, (r3, 0x30) + 2ca6: 4245 lsli r2, r2, 5 + 2ca8: 6848 and r1, r2 + 2caa: 3940 cmpnei r1, 0 + 2cac: 0bf3 bt 0x2c92 // 2c92 + else if ((SYSCON->EXIRS&EXI_PIN13)==EXI_PIN13) //EXT13 Interrupt + 2cae: 3280 movi r2, 128 + 2cb0: 932c ld.w r1, (r3, 0x30) + 2cb2: 4246 lsli r2, r2, 6 + 2cb4: 6848 and r1, r2 + 2cb6: 3940 cmpnei r1, 0 + 2cb8: 0bed bt 0x2c92 // 2c92 + else if ((SYSCON->EXIRS&EXI_PIN14)==EXI_PIN14) //EXT14 Interrupt + 2cba: 3280 movi r2, 128 + 2cbc: 932c ld.w r1, (r3, 0x30) + 2cbe: 4247 lsli r2, r2, 7 + 2cc0: 6848 and r1, r2 + 2cc2: 3940 cmpnei r1, 0 + 2cc4: 0be7 bt 0x2c92 // 2c92 + else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) //EXT15 Interrupt + 2cc6: 3280 movi r2, 128 + 2cc8: 932c ld.w r1, (r3, 0x30) + 2cca: 4248 lsli r2, r2, 8 + 2ccc: 6848 and r1, r2 + 2cce: 3940 cmpnei r1, 0 + 2cd0: 0be1 bt 0x2c92 // 2c92 +} + 2cd2: 1463 ipop + 2cd4: 1461 nir + 2cd6: 0000 bkpt + 2cd8: 2000005c .long 0x2000005c + +Disassembly of section .text.LPTIntHandler: + +00002cdc : +//LPT Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPTIntHandler(void) +{ + 2cdc: 1460 nie + 2cde: 1462 ipush + // ISR content ... + if((LPT->MISR&LPT_TRGEV0)==LPT_TRGEV0) //TRGEV0 interrupt + 2ce0: 106b lrw r3, 0x20000014 // 2d0c + 2ce2: 3101 movi r1, 1 + 2ce4: 9360 ld.w r3, (r3, 0x0) + 2ce6: 934e ld.w r2, (r3, 0x38) + 2ce8: 6884 and r2, r1 + 2cea: 3a40 cmpnei r2, 0 + 2cec: 0c03 bf 0x2cf2 // 2cf2 + { + LPT->ICR = LPT_MATCH; + } + else if((LPT->MISR&LPT_PEND)==LPT_PEND) //PEND interrupt + { + LPT->ICR = LPT_PEND; + 2cee: b330 st.w r1, (r3, 0x40) + } +} + 2cf0: 040b br 0x2d06 // 2d06 + else if((LPT->MISR&LPT_MATCH)==LPT_MATCH) //MATCH interrupt + 2cf2: 934e ld.w r2, (r3, 0x38) + 2cf4: 3102 movi r1, 2 + 2cf6: 6884 and r2, r1 + 2cf8: 3a40 cmpnei r2, 0 + 2cfa: 0bfa bt 0x2cee // 2cee + else if((LPT->MISR&LPT_PEND)==LPT_PEND) //PEND interrupt + 2cfc: 934e ld.w r2, (r3, 0x38) + 2cfe: 3104 movi r1, 4 + 2d00: 6884 and r2, r1 + 2d02: 3a40 cmpnei r2, 0 + 2d04: 0bf5 bt 0x2cee // 2cee +} + 2d06: 1463 ipop + 2d08: 1461 nir + 2d0a: 0000 bkpt + 2d0c: 20000014 .long 0x20000014 + +Disassembly of section .text.BT0IntHandler: + +00002d10 : +//BT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT0IntHandler(void) +{ + 2d10: 1460 nie + 2d12: 1462 ipush + // ISR content ... + if((BT0->MISR&BT_PEND)==BT_PEND) //BT0 PEND interrupt + 2d14: 106d lrw r3, 0x2000000c // 2d48 + 2d16: 3101 movi r1, 1 + 2d18: 9360 ld.w r3, (r3, 0x0) + 2d1a: 934c ld.w r2, (r3, 0x30) + 2d1c: 6884 and r2, r1 + 2d1e: 3a40 cmpnei r2, 0 + 2d20: 0c03 bf 0x2d26 // 2d26 + { + BT0->ICR = BT_OVF; + } + else if((BT0->MISR&BT_EVTRG)==BT_EVTRG) //BT0 Event trigger interrupt + { + BT0->ICR = BT_EVTRG; + 2d22: b32d st.w r1, (r3, 0x34) + } +} + 2d24: 0410 br 0x2d44 // 2d44 + else if((BT0->MISR&BT_CMP)==BT_CMP) //BT0 CMP Match interrupt + 2d26: 934c ld.w r2, (r3, 0x30) + 2d28: 3102 movi r1, 2 + 2d2a: 6884 and r2, r1 + 2d2c: 3a40 cmpnei r2, 0 + 2d2e: 0bfa bt 0x2d22 // 2d22 + else if((BT0->MISR&BT_OVF)==BT_OVF) //BT0 OVF interrupt + 2d30: 934c ld.w r2, (r3, 0x30) + 2d32: 3104 movi r1, 4 + 2d34: 6884 and r2, r1 + 2d36: 3a40 cmpnei r2, 0 + 2d38: 0bf5 bt 0x2d22 // 2d22 + else if((BT0->MISR&BT_EVTRG)==BT_EVTRG) //BT0 Event trigger interrupt + 2d3a: 934c ld.w r2, (r3, 0x30) + 2d3c: 3108 movi r1, 8 + 2d3e: 6884 and r2, r1 + 2d40: 3a40 cmpnei r2, 0 + 2d42: 0bf0 bt 0x2d22 // 2d22 +} + 2d44: 1463 ipop + 2d46: 1461 nir + 2d48: 2000000c .long 0x2000000c + +Disassembly of section .text.BT1IntHandler: + +00002d4c : +//BT1 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT1IntHandler(void) +{ + 2d4c: 1460 nie + 2d4e: 1462 ipush + 2d50: 14d0 push r15 + static U8_T NUM = 0; + // ISR content ... + if((BT1->MISR&BT_PEND)==BT_PEND) //BT1 PEND interrupt + 2d52: 1079 lrw r3, 0x20000008 // 2db4 + 2d54: 3101 movi r1, 1 + 2d56: 9360 ld.w r3, (r3, 0x0) + 2d58: 934c ld.w r2, (r3, 0x30) + 2d5a: 6884 and r2, r1 + 2d5c: 3a40 cmpnei r2, 0 + 2d5e: 0c03 bf 0x2d64 // 2d64 + { + BT1->ICR = BT_OVF; + } + else if((BT1->MISR&BT_EVTRG)==BT_EVTRG) //BT1 Event trigger interrupt + { + BT1->ICR = BT_EVTRG; + 2d60: b32d st.w r1, (r3, 0x34) + } +} + 2d62: 0418 br 0x2d92 // 2d92 + else if((BT1->MISR&BT_CMP)==BT_CMP) //BT1 CMP Match interrupt + 2d64: 934c ld.w r2, (r3, 0x30) + 2d66: 3102 movi r1, 2 + 2d68: 6884 and r2, r1 + 2d6a: 3a40 cmpnei r2, 0 + 2d6c: 0c18 bf 0x2d9c // 2d9c + BT1->ICR = BT_CMP; + 2d6e: b32d st.w r1, (r3, 0x34) + NUM++; + 2d70: 1072 lrw r3, 0x20000068 // 2db8 + 2d72: 8340 ld.b r2, (r3, 0x0) + 2d74: 2200 addi r2, 1 + 2d76: 7488 zextb r2, r2 + SysTick_100us++; + 2d78: 9321 ld.w r1, (r3, 0x4) + 2d7a: 2100 addi r1, 1 + if(NUM >= 10){ + 2d7c: 3a09 cmphsi r2, 10 + NUM++; + 2d7e: a340 st.b r2, (r3, 0x0) + SysTick_100us++; + 2d80: b321 st.w r1, (r3, 0x4) + if(NUM >= 10){ + 2d82: 0c08 bf 0x2d92 // 2d92 + NUM = 0; + 2d84: 3200 movi r2, 0 + 2d86: a340 st.b r2, (r3, 0x0) + SysTick_1ms++; + 2d88: 9342 ld.w r2, (r3, 0x8) + 2d8a: 2200 addi r2, 1 + 2d8c: b342 st.w r2, (r3, 0x8) + PB_Scan_State_Task(); + 2d8e: e00002c1 bsr 0x3310 // 3310 +} + 2d92: d9ee2000 ld.w r15, (r14, 0x0) + 2d96: 1401 addi r14, r14, 4 + 2d98: 1463 ipop + 2d9a: 1461 nir + else if((BT1->MISR&BT_OVF)==BT_OVF) //BT1 OVF interrupt + 2d9c: 934c ld.w r2, (r3, 0x30) + 2d9e: 3104 movi r1, 4 + 2da0: 6884 and r2, r1 + 2da2: 3a40 cmpnei r2, 0 + 2da4: 0bde bt 0x2d60 // 2d60 + else if((BT1->MISR&BT_EVTRG)==BT_EVTRG) //BT1 Event trigger interrupt + 2da6: 934c ld.w r2, (r3, 0x30) + 2da8: 3108 movi r1, 8 + 2daa: 6884 and r2, r1 + 2dac: 3a40 cmpnei r2, 0 + 2dae: 0bd9 bt 0x2d60 // 2d60 + 2db0: 07f1 br 0x2d92 // 2d92 + 2db2: 0000 bkpt + 2db4: 20000008 .long 0x20000008 + 2db8: 20000068 .long 0x20000068 + +Disassembly of section .text.PriviledgeVioHandler: + +00002dbc : + 2dbc: 783c jmp r15 + +Disassembly of section .text.PendTrapHandler: + +00002dbe : + // ISR content ... + +} + +void PendTrapHandler(void) +{ + 2dbe: 1460 nie + 2dc0: 1462 ipush + // ISR content ... + +} + 2dc2: 1463 ipop + 2dc4: 1461 nir + +Disassembly of section .text.Trap3Handler: + +00002dc6 : + 2dc6: 1460 nie + 2dc8: 1462 ipush + 2dca: 1463 ipop + 2dcc: 1461 nir + +Disassembly of section .text.Trap2Handler: + +00002dce : + 2dce: 1460 nie + 2dd0: 1462 ipush + 2dd2: 1463 ipop + 2dd4: 1461 nir + +Disassembly of section .text.Trap1Handler: + +00002dd6 : + 2dd6: 1460 nie + 2dd8: 1462 ipush + 2dda: 1463 ipop + 2ddc: 1461 nir + +Disassembly of section .text.Trap0Handler: + +00002dde : + 2dde: 1460 nie + 2de0: 1462 ipush + 2de2: 1463 ipop + 2de4: 1461 nir + +Disassembly of section .text.UnrecExecpHandler: + +00002de6 : + 2de6: 1460 nie + 2de8: 1462 ipush + 2dea: 1463 ipop + 2dec: 1461 nir + +Disassembly of section .text.BreakPointHandler: + +00002dee : + 2dee: 1460 nie + 2df0: 1462 ipush + 2df2: 1463 ipop + 2df4: 1461 nir + +Disassembly of section .text.AccessErrHandler: + +00002df6 : + 2df6: 1460 nie + 2df8: 1462 ipush + 2dfa: 1463 ipop + 2dfc: 1461 nir + +Disassembly of section .text.IllegalInstrHandler: + +00002dfe : + 2dfe: 1460 nie + 2e00: 1462 ipush + 2e02: 1463 ipop + 2e04: 1461 nir + +Disassembly of section .text.MisalignedHandler: + +00002e06 : + 2e06: 1460 nie + 2e08: 1462 ipush + 2e0a: 1463 ipop + 2e0c: 1461 nir + +Disassembly of section .text.TKEYIntHandler: + +00002e0e : + 2e0e: 1460 nie + 2e10: 1462 ipush + 2e12: 1463 ipop + 2e14: 1461 nir + +Disassembly of section .text.CNTAIntHandler: + +00002e16 : + 2e16: 1460 nie + 2e18: 1462 ipush + 2e1a: 1463 ipop + 2e1c: 1461 nir + +Disassembly of section .text.I2CIntHandler: + +00002e1e : + 2e1e: 1460 nie + 2e20: 1462 ipush + 2e22: 1463 ipop + 2e24: 1461 nir + +Disassembly of section .text.CORETHandler: + +00002e26 : + 2e26: 1460 nie + 2e28: 1462 ipush + 2e2a: 1463 ipop + 2e2c: 1461 nir + +Disassembly of section .text.__divsi3: + +00002e30 <__divsi3>: +CSP_BT_T *BT1 = (CSP_BT_T *)APB_BT1Base ; +CSP_CRC_T *CRC = (CSP_CRC_T *)AHB_CRCBase ; +CSP_HWD_T *HWD = (CSP_HWD_T *)APB_HWDBase ; + +int __divsi3 ( int a, int b) +{ + 2e30: 14c1 push r4 + int PSR; + __asm volatile( + 2e32: c0006023 mfcr r3, cr<0, 0> + 2e36: c0807020 psrclr ie + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 0; + 2e3a: 1046 lrw r2, 0x20000000 // 2e50 <__divsi3+0x20> + 2e3c: 3400 movi r4, 0 + 2e3e: 9240 ld.w r2, (r2, 0x0) + 2e40: b284 st.w r4, (r2, 0x10) + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + 2e42: 3bbf bseti r3, 31 + HWD->DIVIDENT = a; + 2e44: b200 st.w r0, (r2, 0x0) + HWD->DIVISOR = b; + 2e46: b221 st.w r1, (r2, 0x4) + __asm volatile( + 2e48: c0036420 mtcr r3, cr<0, 0> + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + + return HWD->QUOTIENT; + 2e4c: 9202 ld.w r0, (r2, 0x8) +} + 2e4e: 1481 pop r4 + 2e50: 20000000 .long 0x20000000 + +Disassembly of section .text.__udivsi3: + +00002e54 <__udivsi3>: + unsigned int __udivsi3 ( unsigned int a, unsigned int b) +{ + 2e54: 14c1 push r4 + int PSR; + __asm volatile( + 2e56: c0006023 mfcr r3, cr<0, 0> + 2e5a: c0807020 psrclr ie + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 1; + 2e5e: 1046 lrw r2, 0x20000000 // 2e74 <__udivsi3+0x20> + 2e60: 3401 movi r4, 1 + 2e62: 9240 ld.w r2, (r2, 0x0) + 2e64: b284 st.w r4, (r2, 0x10) + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + 2e66: 3bbf bseti r3, 31 + HWD->DIVIDENT = a; + 2e68: b200 st.w r0, (r2, 0x0) + HWD->DIVISOR = b; + 2e6a: b221 st.w r1, (r2, 0x4) + __asm volatile( + 2e6c: c0036420 mtcr r3, cr<0, 0> + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + + return HWD->QUOTIENT; + 2e70: 9202 ld.w r0, (r2, 0x8) +} + 2e72: 1481 pop r4 + 2e74: 20000000 .long 0x20000000 + +Disassembly of section .text.CK_CPU_EnAllNormalIrq: + +00002e78 : +} + + +void CK_CPU_EnAllNormalIrq(void) +{ + asm ("psrset ee,ie"); + 2e78: c1807420 psrset ee, ie +} + 2e7c: 783c jmp r15 + +Disassembly of section .text.UARTx_Init: + +00002e80 : + * UART0 用于PB数据发送，没有接收 9600 -> 对应设置 5000 + * */ + +UART_t g_uart; //目前该项目只使用串口1 进行双向通讯 + +void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf) { + 2e80: 14d1 push r4, r15 + switch(uart_id){ + 2e82: 3841 cmpnei r0, 1 +void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf) { + 2e84: 6d07 mov r4, r1 + switch(uart_id){ + 2e86: 0c15 bf 0x2eb0 // 2eb0 + 2e88: 3840 cmpnei r0, 0 + 2e8a: 0c04 bf 0x2e92 // 2e92 + 2e8c: 3842 cmpnei r0, 2 + 2e8e: 0c2a bf 0x2ee2 // 2ee2 + UARTInitRxTxIntEn(UART2,98,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + //UART1_Int_Enable(); + + break; + } +} + 2e90: 1491 pop r4, r15 + UART0_DeInit(); //clear all UART Register + 2e92: e3fff379 bsr 0x1584 // 1584 + UART_IO_Init(IO_UART0,0); //use PA0.1->RXD0, PA0.0->TXD0 + 2e96: 3100 movi r1, 0 + 2e98: 3000 movi r0, 0 + 2e9a: e3fff3b5 bsr 0x1604 // 1604 + UARTInitRxTxIntEn(UART0,10000,UART_PAR_NONE); //baudrate=sysclock 48M/1000=4800,tx rx int enabled + 2e9e: 1078 lrw r3, 0x20000040 // 2efc + 2ea0: 3200 movi r2, 0 + 2ea2: 9300 ld.w r0, (r3, 0x0) + 2ea4: 1037 lrw r1, 0x2710 // 2f00 + 2ea6: e3fff423 bsr 0x16ec // 16ec + UART0_Int_Enable(); + 2eaa: e3fff391 bsr 0x15cc // 15cc + break; + 2eae: 07f1 br 0x2e90 // 2e90 + UART1_DeInit(); //clear all UART Register + 2eb0: e3fff376 bsr 0x159c // 159c + UART_IO_Init(IO_UART1,0); //use PA0.13->RXD1, PB0.0->TXD1 + 2eb4: 3100 movi r1, 0 + 2eb6: 3001 movi r0, 1 + 2eb8: e3fff3a6 bsr 0x1604 // 1604 + UARTInitRxTxIntEn(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + 2ebc: 1072 lrw r3, 0x2000003c // 2f04 + 2ebe: 31d0 movi r1, 208 + 2ec0: 9300 ld.w r0, (r3, 0x0) + 2ec2: 3200 movi r2, 0 + 2ec4: 4121 lsli r1, r1, 1 + 2ec6: e3fff413 bsr 0x16ec // 16ec + UART1_Int_Enable(); + 2eca: e3fff38f bsr 0x15e8 // 15e8 + memset(&g_uart,0,sizeof(UART_t)); + 2ece: 32dc movi r2, 220 + 2ed0: 3100 movi r1, 0 + 2ed2: 100e lrw r0, 0x200000b4 // 2f08 + 2ed4: e3ffee90 bsr 0xbf4 // bf4 <__memset_fast> + g_uart.RecvTimeout = Recv_115200_TimeOut; + 2ed8: 106d lrw r3, 0x20000134 // 2f0c + 2eda: 3203 movi r2, 3 + 2edc: b354 st.w r2, (r3, 0x50) + g_uart.processing_cf = prt_cf; + 2ede: b396 st.w r4, (r3, 0x58) + break; + 2ee0: 07d8 br 0x2e90 // 2e90 + UART2_DeInit(); //clear all UART Register + 2ee2: e3fff369 bsr 0x15b4 // 15b4 + UART_IO_Init(IO_UART2,1); //use PA0.13->RXD1, PB0.0->TXD1 + 2ee6: 3101 movi r1, 1 + 2ee8: 3002 movi r0, 2 + 2eea: e3fff38d bsr 0x1604 // 1604 + UARTInitRxTxIntEn(UART2,98,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + 2eee: 1069 lrw r3, 0x20000038 // 2f10 + 2ef0: 3200 movi r2, 0 + 2ef2: 9300 ld.w r0, (r3, 0x0) + 2ef4: 3162 movi r1, 98 + 2ef6: e3fff3fb bsr 0x16ec // 16ec +} + 2efa: 07cb br 0x2e90 // 2e90 + 2efc: 20000040 .long 0x20000040 + 2f00: 00002710 .long 0x00002710 + 2f04: 2000003c .long 0x2000003c + 2f08: 200000b4 .long 0x200000b4 + 2f0c: 20000134 .long 0x20000134 + 2f10: 20000038 .long 0x20000038 + +Disassembly of section .text.UART1_RecvINT_Processing: + +00002f14 : + +/******************************************************************************* +* Function Name : UART1_RecvINT_Processing +* Description : 串口1 接收中断处理函数 - 接收中断调用 +*******************************************************************************/ +void UART1_RecvINT_Processing(char data){ + 2f14: 14c1 push r4 + if((g_uart.RecvLen + 1) >= USART_BUFFER_SIZE) g_uart.RecvLen = 0; + 2f16: 106b lrw r3, 0x20000174 // 2f40 + 2f18: 8b25 ld.h r1, (r3, 0xa) + 2f1a: 3262 movi r2, 98 + 2f1c: 6449 cmplt r2, r1 + 2f1e: 0c03 bf 0x2f24 // 2f24 + 2f20: 3200 movi r2, 0 + 2f22: ab45 st.h r2, (r3, 0xa) + g_uart.RecvBuffer[g_uart.RecvLen++] = (U8_T)data; + 2f24: 8b25 ld.h r1, (r3, 0xa) + 2f26: 1048 lrw r2, 0x200000b4 // 2f44 + 2f28: 5982 addi r4, r1, 1 + 2f2a: 6048 addu r1, r2 + 2f2c: a100 st.b r0, (r1, 0x0) + + g_uart.RecvIdleTiming = SysTick_1ms; + 2f2e: 227f addi r2, 128 + 2f30: 1026 lrw r1, 0x20000070 // 2f48 + 2f32: 9120 ld.w r1, (r1, 0x0) + 2f34: b235 st.w r1, (r2, 0x54) + g_uart.Receiving = 0x01; + 2f36: 3201 movi r2, 1 + g_uart.RecvBuffer[g_uart.RecvLen++] = (U8_T)data; + 2f38: ab85 st.h r4, (r3, 0xa) + g_uart.Receiving = 0x01; + 2f3a: a348 st.b r2, (r3, 0x8) +} + 2f3c: 1481 pop r4 + 2f3e: 0000 bkpt + 2f40: 20000174 .long 0x20000174 + 2f44: 200000b4 .long 0x200000b4 + 2f48: 20000070 .long 0x20000070 + +Disassembly of section .text.UART1_TASK: + +00002f4c : + + +void UART1_TASK(void){ + 2f4c: 14d2 push r4-r5, r15 + U8_T rev = 0; + if(g_uart.Receiving == 0x01){ + 2f4e: 1092 lrw r4, 0x20000174 // 2f94 + 2f50: 8468 ld.b r3, (r4, 0x8) + 2f52: 3b41 cmpnei r3, 1 + 2f54: 081e bt 0x2f90 // 2f90 + + if(SysTick_1ms - g_uart.RecvIdleTiming > Recv_115200_TimeOut){ + 2f56: 1051 lrw r2, 0x20000070 // 2f98 + 2f58: 10b1 lrw r5, 0x20000134 // 2f9c + 2f5a: 9260 ld.w r3, (r2, 0x0) + 2f5c: 9535 ld.w r1, (r5, 0x54) + 2f5e: 60c6 subu r3, r1 + 2f60: 3b03 cmphsi r3, 4 + 2f62: 0c17 bf 0x2f90 // 2f90 + g_uart.RecvIdleTiming = SysTick_1ms; + 2f64: 9260 ld.w r3, (r2, 0x0) + + memcpy(g_uart.DealBuff,g_uart.RecvBuffer,g_uart.RecvLen); + 2f66: 100f lrw r0, 0x20000118 // 2fa0 + 2f68: 102f lrw r1, 0x200000b4 // 2fa4 + 2f6a: 8c45 ld.h r2, (r4, 0xa) + g_uart.RecvIdleTiming = SysTick_1ms; + 2f6c: b575 st.w r3, (r5, 0x54) + memcpy(g_uart.DealBuff,g_uart.RecvBuffer,g_uart.RecvLen); + 2f6e: e3ffee87 bsr 0xc7c // c7c <__memcpy_fast> + g_uart.DealLen = g_uart.RecvLen; + g_uart.RecvLen = 0; + 2f72: 3300 movi r3, 0 + g_uart.DealLen = g_uart.RecvLen; + 2f74: 8c25 ld.h r1, (r4, 0xa) + g_uart.Receiving = 0; + 2f76: a468 st.b r3, (r4, 0x8) + g_uart.RecvLen = 0; + 2f78: ac65 st.h r3, (r4, 0xa) + + Dbg_Println(DBG_BIT_SYS_STATUS, "UART recv Len %d", g_uart.DealLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"UART buff",g_uart.DealBuff,g_uart.DealLen); + + if(g_uart.processing_cf != NULL){ + 2f7a: 9576 ld.w r3, (r5, 0x58) + 2f7c: 3b40 cmpnei r3, 0 + g_uart.DealLen = g_uart.RecvLen; + 2f7e: ac26 st.h r1, (r4, 0xc) + if(g_uart.processing_cf != NULL){ + 2f80: 0c03 bf 0x2f86 // 2f86 + rev = g_uart.processing_cf(g_uart.DealBuff,g_uart.DealLen); + 2f82: 1008 lrw r0, 0x20000118 // 2fa0 + 2f84: 7bcd jsr r3 + + if(rev == 0x01){ + //Dbg_Print_Buff(DBG_BIT_Debug_STATUS,"error buff ",g_uart.DealBuff,g_uart.DealLen); + } + + memset(g_uart.DealBuff,0,USART_BUFFER_SIZE); + 2f86: 3264 movi r2, 100 + 2f88: 3100 movi r1, 0 + 2f8a: 1006 lrw r0, 0x20000118 // 2fa0 + 2f8c: e3ffee34 bsr 0xbf4 // bf4 <__memset_fast> + } + } +} + 2f90: 1492 pop r4-r5, r15 + 2f92: 0000 bkpt + 2f94: 20000174 .long 0x20000174 + 2f98: 20000070 .long 0x20000070 + 2f9c: 20000134 .long 0x20000134 + 2fa0: 20000118 .long 0x20000118 + 2fa4: 200000b4 .long 0x200000b4 + +Disassembly of section .text.Dbg_Println: + +00002fa8 : + } + +#endif +} + +void Dbg_Println(int DbgOptBit, const char *cmd, ...){ + 2fa8: 1423 subi r14, r14, 12 + 2faa: b862 st.w r3, (r14, 0x8) + 2fac: b841 st.w r2, (r14, 0x4) + 2fae: b820 st.w r1, (r14, 0x0) + + DBG_Printf("\r\n",2); + } + +#endif +} + 2fb0: 1403 addi r14, r14, 12 + 2fb2: 783c jmp r15 + +Disassembly of section .text.Dbg_Print_Buff: + +00002fb4 : + + DBG_Printf("\r\n",2); + } + +#endif +} + 2fb4: 783c jmp r15 + +Disassembly of section .text.PB_Set_Power_State.part.1: + +00002fb8 : + +/********************************************************************* + * @fn PB_Set_Power_State + * @brief PB - 设置PB电源状态 + */ +void PB_Set_Power_State(U8_T state){ + 2fb8: 14d0 push r15 + switch(state){ + case TRUE: + g_PB.enable = TRUE; + break; + case FALSE: + g_PB.enable = FALSE; + 2fba: 3200 movi r2, 0 + 2fbc: 1065 lrw r3, 0x200002f0 // 2fd0 + g_PB.power_status = FALSE; + DRV_PB_DISABLE; + 2fbe: 310c movi r1, 12 + g_PB.enable = FALSE; + 2fc0: a352 st.b r2, (r3, 0x12) + g_PB.power_status = FALSE; + 2fc2: a351 st.b r2, (r3, 0x11) + DRV_PB_DISABLE; + 2fc4: 1064 lrw r3, 0x2000004c // 2fd4 + 2fc6: 9300 ld.w r0, (r3, 0x0) + 2fc8: e3fff154 bsr 0x1270 // 1270 + break; + } +} + 2fcc: 1490 pop r15 + 2fce: 0000 bkpt + 2fd0: 200002f0 .long 0x200002f0 + 2fd4: 2000004c .long 0x2000004c + +Disassembly of section .text.PB_Set_SaveCurrent: + +00002fd8 : +void PB_Set_SaveCurrent(U8_T val){ + 2fd8: 14d0 push r15 + if( (val < PB_SaveCurrent_Min) || (val > PB_SaveCurrent_Max) ) return ; + 2fda: 5863 subi r3, r0, 1 + 2fdc: 74cc zextb r3, r3 + 2fde: 32a4 movi r2, 164 + 2fe0: 64c8 cmphs r2, r3 + 2fe2: 0c0c bf 0x2ffa // 2ffa + curr_val = val*4095/PB_SaveCurrent_Max; + 2fe4: 406c lsli r3, r0, 12 + 2fe6: 5b01 subu r0, r3, r0 + 2fe8: 31a5 movi r1, 165 + 2fea: e3ffff23 bsr 0x2e30 // 2e30 <__divsi3> + BT_Period_CMP_Write(BT0,4095,curr_val); + 2fee: 1064 lrw r3, 0x2000000c // 2ffc + 2ff0: 7481 zexth r2, r0 + 2ff2: 1024 lrw r1, 0xfff // 3000 + 2ff4: 9300 ld.w r0, (r3, 0x0) + 2ff6: e3fff260 bsr 0x14b6 // 14b6 +} + 2ffa: 1490 pop r15 + 2ffc: 2000000c .long 0x2000000c + 3000: 00000fff .long 0x00000fff + +Disassembly of section .text.PB_Init: + +00003004 : +void PB_Init(void){ + 3004: 14d1 push r4, r15 + memset(&g_PB,0,sizeof(PB_INFO_T)); + 3006: 108d lrw r4, 0x200002f0 // 3038 + 3008: 3285 movi r2, 133 + 300a: 4243 lsli r2, r2, 3 + 300c: 3100 movi r1, 0 + 300e: 6c13 mov r0, r4 + 3010: e3ffedf2 bsr 0xbf4 // bf4 <__memset_fast> + memset(&curr_monitoring,0,sizeof(PB_DETECTION_FILTER_INFO)); + 3014: 3100 movi r1, 0 + 3016: 3298 movi r2, 152 + 3018: 1009 lrw r0, 0x20000258 // 303c + 301a: e3ffeded bsr 0xbf4 // bf4 <__memset_fast> + g_PB.enable = g_eeprom.powerbus_enable; + 301e: 1069 lrw r3, 0x200007a4 // 3040 + 3020: 8340 ld.b r2, (r3, 0x0) + g_PB.protect_curr = g_eeprom.save_curr; + 3022: 8301 ld.b r0, (r3, 0x1) + g_PB.protect_time = 5000; //5S + 3024: 3383 movi r3, 131 + 3026: 4363 lsli r3, r3, 3 + g_PB.enable = g_eeprom.powerbus_enable; + 3028: a452 st.b r2, (r4, 0x12) + g_PB.protect_curr = g_eeprom.save_curr; + 302a: a415 st.b r0, (r4, 0x15) + g_PB.protect_time = 5000; //5S + 302c: 610c addu r4, r3 + 302e: 1066 lrw r3, 0x1388 // 3044 + 3030: b460 st.w r3, (r4, 0x0) + PB_Set_SaveCurrent(g_PB.protect_curr); //设置保护电流 + 3032: e3ffffd3 bsr 0x2fd8 // 2fd8 +} + 3036: 1491 pop r4, r15 + 3038: 200002f0 .long 0x200002f0 + 303c: 20000258 .long 0x20000258 + 3040: 200007a4 .long 0x200007a4 + 3044: 00001388 .long 0x00001388 + +Disassembly of section .text.PB_Set_Power_State: + +00003048 : +void PB_Set_Power_State(U8_T state){ + 3048: 14d0 push r15 + switch(state){ + 304a: 3840 cmpnei r0, 0 + 304c: 0c07 bf 0x305a // 305a + 304e: 3841 cmpnei r0, 1 + 3050: 0804 bt 0x3058 // 3058 + g_PB.enable = TRUE; + 3052: 1064 lrw r3, 0x200002f0 // 3060 + 3054: 3201 movi r2, 1 + 3056: a352 st.b r2, (r3, 0x12) +} + 3058: 1490 pop r15 + 305a: e3ffffaf bsr 0x2fb8 // 2fb8 + 305e: 07fd br 0x3058 // 3058 + 3060: 200002f0 .long 0x200002f0 + +Disassembly of section .text.PB_Soft_Boot_Task: + +00003064 : + +/********************************************************************* + * @fn PB_Soft_Boot_Task + * @brief PB - 软启动任务 + */ +void PB_Soft_Boot_Task(void){ + 3064: 14d3 push r4-r6, r15 + + if(g_PB.meas_hv_PB_State != 0x01) return; //PB输出电源未打开 + 3066: 11bf lrw r5, 0x200002f0 // 3160 + 3068: 8566 ld.b r3, (r5, 0x6) + 306a: 3b41 cmpnei r3, 1 + 306c: 6d17 mov r4, r5 + 306e: 080b bt 0x3084 // 3084 + + if(g_PB.enable != TRUE) return ; + 3070: 8572 ld.b r3, (r5, 0x12) + 3072: 3b41 cmpnei r3, 1 + 3074: 0808 bt 0x3084 // 3084 + + switch(g_PB.soft_boot){ + 3076: 8573 ld.b r3, (r5, 0x13) + 3078: 3b41 cmpnei r3, 1 + 307a: 0c25 bf 0x30c4 // 30c4 + 307c: 3b40 cmpnei r3, 0 + 307e: 0c04 bf 0x3086 // 3086 + 3080: 3b42 cmpnei r3, 2 + 3082: 0c37 bf 0x30f0 // 30f0 + + //Dbg_Println(DBG_BIT_SYS_STATUS, "PWM DutyHigh %d",g_PB.soft_boot_high); + } + break; + } +} + 3084: 1493 pop r4-r6, r15 + g_PB.soft_boot_high = 0x01; + 3086: 1178 lrw r3, 0x3ae // 3164 + 3088: 60d4 addu r3, r5 + 308a: 3201 movi r2, 1 + 308c: ab40 st.h r2, (r3, 0x0) + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + 308e: 33ec movi r3, 236 + 3090: 4362 lsli r3, r3, 2 + 3092: 60d4 addu r3, r5 + 3094: 3263 movi r2, 99 + 3096: ab40 st.h r2, (r3, 0x0) + DRV_PB_DISABLE; + 3098: 310c movi r1, 12 + g_PB.soft_boot_tick = SysTick_100us; + 309a: 1174 lrw r3, 0x2000006c // 3168 + 309c: 9340 ld.w r2, (r3, 0x0) + 309e: 1174 lrw r3, 0x41c // 316c + 30a0: 60d4 addu r3, r5 + 30a2: b340 st.w r2, (r3, 0x0) + g_PB.soft_boot_cnt = 0; + 30a4: 33eb movi r3, 235 + 30a6: 4362 lsli r3, r3, 2 + 30a8: 60d4 addu r3, r5 + 30aa: 3200 movi r2, 0 + 30ac: ab40 st.h r2, (r3, 0x0) + DRV_PB_DISABLE; + 30ae: 1171 lrw r3, 0x2000004c // 3170 + 30b0: 9300 ld.w r0, (r3, 0x0) + 30b2: e3fff0df bsr 0x1270 // 1270 + g_PB.soft_boot = 0x01; + 30b6: 3301 movi r3, 1 + 30b8: a573 st.b r3, (r5, 0x13) + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Soft_Boot_Task Start"); + 30ba: 112f lrw r1, 0x5a17 // 3174 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Soft_Boot_Task End"); + 30bc: 3000 movi r0, 0 + 30be: e3ffff75 bsr 0x2fa8 // 2fa8 + 30c2: 07e1 br 0x3084 // 3084 + if(SysTick_100us - g_PB.soft_boot_tick >= g_PB.soft_boot_low){ + 30c4: 114a lrw r2, 0x41c // 316c + 30c6: 1129 lrw r1, 0x2000006c // 3168 + 30c8: 6094 addu r2, r5 + 30ca: 9200 ld.w r0, (r2, 0x0) + 30cc: 9160 ld.w r3, (r1, 0x0) + 30ce: 60c2 subu r3, r0 + 30d0: 30ec movi r0, 236 + 30d2: 4002 lsli r0, r0, 2 + 30d4: 6014 addu r0, r5 + 30d6: 8800 ld.h r0, (r0, 0x0) + 30d8: 640c cmphs r3, r0 + 30da: 0fd5 bf 0x3084 // 3084 + g_PB.soft_boot_tick = SysTick_100us; + 30dc: 9160 ld.w r3, (r1, 0x0) + 30de: b260 st.w r3, (r2, 0x0) + DRV_PB_ENABLE; + 30e0: 310c movi r1, 12 + 30e2: 1164 lrw r3, 0x2000004c // 3170 + 30e4: 9300 ld.w r0, (r3, 0x0) + 30e6: e3fff0c1 bsr 0x1268 // 1268 + g_PB.soft_boot = 0x02; + 30ea: 3302 movi r3, 2 + 30ec: a573 st.b r3, (r5, 0x13) + 30ee: 07cb br 0x3084 // 3084 + if(SysTick_100us - g_PB.soft_boot_tick >= g_PB.soft_boot_high){ + 30f0: 101f lrw r0, 0x41c // 316c + 30f2: 10be lrw r5, 0x2000006c // 3168 + 30f4: 103c lrw r1, 0x3ae // 3164 + 30f6: 6010 addu r0, r4 + 30f8: 9540 ld.w r2, (r5, 0x0) + 30fa: 6050 addu r1, r4 + 30fc: 90c0 ld.w r6, (r0, 0x0) + 30fe: 8960 ld.h r3, (r1, 0x0) + 3100: 609a subu r2, r6 + 3102: 64c8 cmphs r2, r3 + 3104: 0fc0 bf 0x3084 // 3084 + g_PB.soft_boot_tick = SysTick_100us; + 3106: 9540 ld.w r2, (r5, 0x0) + 3108: b040 st.w r2, (r0, 0x0) + g_PB.soft_boot_cnt++; + 310a: 30eb movi r0, 235 + 310c: 4002 lsli r0, r0, 2 + 310e: 6010 addu r0, r4 + 3110: 8840 ld.h r2, (r0, 0x0) + 3112: 2200 addi r2, 1 + 3114: 7489 zexth r2, r2 + if(g_PB.soft_boot_cnt >= 3){ + 3116: 3a02 cmphsi r2, 3 + 3118: 0813 bt 0x313e // 313e + g_PB.soft_boot_cnt++; + 311a: a840 st.h r2, (r0, 0x0) + if(g_PB.soft_boot_high >= PB_SOFTBOOT_PERIOD){ + 311c: 8940 ld.h r2, (r1, 0x0) + 311e: 3363 movi r3, 99 + 3120: 648c cmphs r3, r2 + 3122: 1074 lrw r3, 0x2000004c // 3170 + DRV_PB_ENABLE; + 3124: 310c movi r1, 12 + 3126: 9300 ld.w r0, (r3, 0x0) + if(g_PB.soft_boot_high >= PB_SOFTBOOT_PERIOD){ + 3128: 0817 bt 0x3156 // 3156 + DRV_PB_ENABLE; + 312a: e3fff09f bsr 0x1268 // 1268 + g_PB.enable = FALSE; + 312e: 3300 movi r3, 0 + 3130: a472 st.b r3, (r4, 0x12) + g_PB.power_status = TRUE; + 3132: 3301 movi r3, 1 + 3134: a471 st.b r3, (r4, 0x11) + g_PB.soft_boot = 0x00; + 3136: 3300 movi r3, 0 + 3138: a473 st.b r3, (r4, 0x13) + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Soft_Boot_Task End"); + 313a: 1030 lrw r1, 0x5a2f // 3178 + 313c: 07c0 br 0x30bc // 30bc + g_PB.soft_boot_cnt = 0; + 313e: 3200 movi r2, 0 + 3140: a840 st.h r2, (r0, 0x0) + g_PB.soft_boot_high++; + 3142: 2300 addi r3, 1 + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + 3144: 30ec movi r0, 236 + g_PB.soft_boot_high++; + 3146: 74cd zexth r3, r3 + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + 3148: 4002 lsli r0, r0, 2 + 314a: 3264 movi r2, 100 + g_PB.soft_boot_high++; + 314c: a960 st.h r3, (r1, 0x0) + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + 314e: 6010 addu r0, r4 + 3150: 5a6d subu r3, r2, r3 + 3152: a860 st.h r3, (r0, 0x0) + 3154: 07e4 br 0x311c // 311c + DRV_PB_DISABLE; + 3156: e3fff08d bsr 0x1270 // 1270 + g_PB.soft_boot = 0x01; + 315a: 3301 movi r3, 1 + 315c: a473 st.b r3, (r4, 0x13) + 315e: 0793 br 0x3084 // 3084 + 3160: 200002f0 .long 0x200002f0 + 3164: 000003ae .long 0x000003ae + 3168: 2000006c .long 0x2000006c + 316c: 0000041c .long 0x0000041c + 3170: 2000004c .long 0x2000004c + 3174: 00005a17 .long 0x00005a17 + 3178: 00005a2f .long 0x00005a2f + +Disassembly of section .text.PowerBus_Data_Encoding: + +0000317c : +/********************************************************************* + * @fn PB_Data_Send + * @brief PB - 数据发送函数 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PowerBus_Data_Encoding(U8_T *CodeData,U8_T *Sourdata,U16_T SourLen){ + 317c: 14c4 push r4-r7 + U8_T temp_num = 0; + U8_T i=0; + + for(i=0;i> 4) & 0x0F; + CodeData[i*2] = PowerBus_Code_Comparative[temp_num]; + 3180: 10cb lrw r6, 0x5730 // 31ac + for(i=0;i + } + + //Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Encoding Buff:", CodeData, SourLen*2); + + return 0x00; +} + 3186: 3000 movi r0, 0 + 3188: 1484 pop r4-r7 + temp_num = (Sourdata[i] >> 4) & 0x0F; + 318a: 59ec addu r7, r1, r3 + 318c: 8780 ld.b r4, (r7, 0x0) + CodeData[i*2] = PowerBus_Code_Comparative[temp_num]; + 318e: 4c84 lsri r4, r4, 4 + 3190: 43a1 lsli r5, r3, 1 + 3192: 6118 addu r4, r6 + 3194: 6140 addu r5, r0 + 3196: 8480 ld.b r4, (r4, 0x0) + 3198: a580 st.b r4, (r5, 0x0) + temp_num = (Sourdata[i]) & 0x0F; + 319a: 8780 ld.b r4, (r7, 0x0) + CodeData[i*2 + 1] = PowerBus_Code_Comparative[temp_num]; + 319c: 370f movi r7, 15 + 319e: 691c and r4, r7 + 31a0: 6118 addu r4, r6 + 31a2: 8480 ld.b r4, (r4, 0x0) + for(i=0;i + 31ac: 00005730 .long 0x00005730 + +Disassembly of section .text.PB_Send_String_INT: + +000031b0 : +volatile U8_T UTS_send_Length_temp = 0; +volatile U8_T UTS_send_Length = 0; + +//中断发送 - 串口中断调用 +void PB_Send_String_INT(void){ + if(UTS_send_Complete != 0x00){ + 31b0: 1070 lrw r3, 0x20000074 // 31f0 + 31b2: 8340 ld.b r2, (r3, 0x0) + 31b4: 3a40 cmpnei r2, 0 + 31b6: 0c08 bf 0x31c6 // 31c6 + if(UTS_send_Length_temp >= UTS_send_Length){ + 31b8: 8321 ld.b r1, (r3, 0x1) + 31ba: 8342 ld.b r2, (r3, 0x2) + 31bc: 6484 cmphs r1, r2 + 31be: 0c05 bf 0x31c8 // 31c8 + UTS_send_Complete = 0; + UTS_send_Length_temp = 0; + }else{ + if(UTS_send_Length_temp >= PB_INTP_BUFFER_SIZE){ + UTS_send_Complete = 0; + 31c0: 3200 movi r2, 0 + 31c2: a340 st.b r2, (r3, 0x0) + UTS_send_Length_temp = 0; + 31c4: a341 st.b r2, (r3, 0x1) + + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + } + } + } +} + 31c6: 783c jmp r15 + if(UTS_send_Length_temp >= PB_INTP_BUFFER_SIZE){ + 31c8: 8321 ld.b r1, (r3, 0x1) + 31ca: 32c7 movi r2, 199 + 31cc: 6448 cmphs r2, r1 + 31ce: 0ff9 bf 0x31c0 // 31c0 + CSP_UART_SET_DATA(UART0,Uart_Intp_Send_Buff[UTS_send_Length_temp++]); + 31d0: 1049 lrw r2, 0x20000040 // 31f4 + 31d2: 9200 ld.w r0, (r2, 0x0) + 31d4: 8341 ld.b r2, (r3, 0x1) + 31d6: 7488 zextb r2, r2 + 31d8: 5a22 addi r1, r2, 1 + 31da: 7444 zextb r1, r1 + 31dc: a321 st.b r1, (r3, 0x1) + 31de: 1067 lrw r3, 0x20000190 // 31f8 + 31e0: 608c addu r2, r3 + 31e2: 8260 ld.b r3, (r2, 0x0) + 31e4: b060 st.w r3, (r0, 0x0) + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + 31e6: 1066 lrw r3, 0x20000070 // 31fc + 31e8: 9340 ld.w r2, (r3, 0x0) + 31ea: 1066 lrw r3, 0x20000714 // 3200 + 31ec: b340 st.w r2, (r3, 0x0) +} + 31ee: 07ec br 0x31c6 // 31c6 + 31f0: 20000074 .long 0x20000074 + 31f4: 20000040 .long 0x20000040 + 31f8: 20000190 .long 0x20000190 + 31fc: 20000070 .long 0x20000070 + 3200: 20000714 .long 0x20000714 + +Disassembly of section .text.PowerBus_Data_Send: + +00003204 : +/********************************************************************* + * @fn PowerBus_Data_Send + * @brief PowerBus - 总线数据发送函数 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PowerBus_Data_Send(U8_T *data,U16_T len){ + 3204: 14d4 push r4-r7, r15 + 3206: 173d subi r14, r14, 500 + U8_T send_buff[500]; + memset(send_buff,0,sizeof(send_buff)); + 3208: 32fa movi r2, 250 +U8_T PowerBus_Data_Send(U8_T *data,U16_T len){ + 320a: 6d83 mov r6, r0 + 320c: 6dc7 mov r7, r1 + memset(send_buff,0,sizeof(send_buff)); + 320e: 4241 lsli r2, r2, 1 + 3210: 3100 movi r1, 0 + 3212: 6c3b mov r0, r14 + /*PowerBus - 总线通讯采用新编码格式*/ +// PowerBus_Data_Encoding(send_buff,data,len); +// PowerBus_SendData(send_buff,len*2); + + /*PowerBus - 总线通讯 中断发送*/ + if(UTS_send_Complete == 0x00){ + 3214: 10b6 lrw r5, 0x20000074 // 326c + memset(send_buff,0,sizeof(send_buff)); + 3216: e3ffecef bsr 0xbf4 // bf4 <__memset_fast> + if(UTS_send_Complete == 0x00){ + 321a: 8560 ld.b r3, (r5, 0x0) + 321c: 3b40 cmpnei r3, 0 + 321e: 0824 bt 0x3266 // 3266 + 3220: 3364 movi r3, 100 + 3222: 65cc cmphs r3, r7 + 3224: 6d1f mov r4, r7 + 3226: 0802 bt 0x322a // 322a + 3228: 3464 movi r4, 100 + memset((void *)Uart_Intp_Send_Buff,0,sizeof(PB_INTP_BUFFER_SIZE)); + 322a: 10f2 lrw r7, 0x20000190 // 3270 + 322c: 7511 zexth r4, r4 + 322e: 3204 movi r2, 4 + 3230: 3100 movi r1, 0 + 3232: 6c1f mov r0, r7 + 3234: e3ffece0 bsr 0xbf4 // bf4 <__memset_fast> + PowerBus_Data_Encoding(Uart_Intp_Send_Buff,data,send_len); + 3238: 6c93 mov r2, r4 + 323a: 6c5b mov r1, r6 + 323c: 6c1f mov r0, r7 + UTS_send_Complete = 0x01; + UTS_send_Length = send_len*2; + 323e: 4481 lsli r4, r4, 1 + PowerBus_Data_Encoding(Uart_Intp_Send_Buff,data,send_len); + 3240: e3ffff9e bsr 0x317c // 317c + UTS_send_Length = send_len*2; + 3244: 7510 zextb r4, r4 + UTS_send_Complete = 0x01; + 3246: 3301 movi r3, 1 + 3248: a560 st.b r3, (r5, 0x0) + UTS_send_Length = send_len*2; + 324a: a582 st.b r4, (r5, 0x2) + UTS_send_Length_temp = 0x01; + 324c: a561 st.b r3, (r5, 0x1) + UARTTxByte(UART0,Uart_Intp_Send_Buff[0]); + 324e: 8720 ld.b r1, (r7, 0x0) + 3250: 1069 lrw r3, 0x20000040 // 3274 + 3252: 9300 ld.w r0, (r3, 0x0) + 3254: e3fff251 bsr 0x16f6 // 16f6 + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + 3258: 1068 lrw r3, 0x20000070 // 3278 + //上次发送还未结束 + + return 0xFF; + } + + return 0x00; + 325a: 3000 movi r0, 0 + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + 325c: 9340 ld.w r2, (r3, 0x0) + 325e: 1068 lrw r3, 0x20000714 // 327c + 3260: b340 st.w r2, (r3, 0x0) + } + + return 0x01; +} + 3262: 171d addi r14, r14, 500 + 3264: 1494 pop r4-r7, r15 + return 0xFF; + 3266: 30ff movi r0, 255 + 3268: 07fd br 0x3262 // 3262 + 326a: 0000 bkpt + 326c: 20000074 .long 0x20000074 + 3270: 20000190 .long 0x20000190 + 3274: 20000040 .long 0x20000040 + 3278: 20000070 .long 0x20000070 + 327c: 20000714 .long 0x20000714 + +Disassembly of section .text.PB_CheckSum: + +00003280 : +/********************************************************************* + * @fn PB_CheckSum + * @brief PB - 数据和校验取反 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PB_CheckSum(U8_T *buff,U16_T len){ + 3280: 6040 addu r1, r0 + U8_T sum = 0; + 3282: 3300 movi r3, 0 + + for(U16_T i=0;i + sum+=buff[i]; + } + + return ~(sum); + 3288: 6cce nor r3, r3 + 328a: 740c zextb r0, r3 +} + 328c: 783c jmp r15 + sum+=buff[i]; + 328e: 8040 ld.b r2, (r0, 0x0) + 3290: 60c8 addu r3, r2 + 3292: 74cc zextb r3, r3 + 3294: 2000 addi r0, 1 + 3296: 07f7 br 0x3284 // 3284 + +Disassembly of section .text.PB_OVERCURR_PWR_BUS_INT_Processing: + +00003298 : +/********************************************************************* + * @fn PB_OVERCURR_PWR_BUS_INT_Processing + * @brief PB - 过流保护中断 引脚中断服务函数中调用 + * @return NULL + */ +void PB_OVERCURR_PWR_BUS_INT_Processing(void){ + 3298: 14d0 push r15 + 329a: e3fffe8f bsr 0x2fb8 // 2fb8 + //if(PB_OVERCURR_PWR_BUS == 0x01){ + /*检测OverCurr引脚状态 上升沿中断信号 High:过流保护中，Low:正常工作中*/ + PB_Set_Power_State(FALSE); + g_PB.protect_flag = TRUE; + 329e: 1066 lrw r3, 0x200002f0 // 32b4 + 32a0: 3201 movi r2, 1 + g_PB.protect_tick = SysTick_1ms; + 32a2: 3184 movi r1, 132 + g_PB.protect_flag = TRUE; + 32a4: a354 st.b r2, (r3, 0x14) + g_PB.protect_tick = SysTick_1ms; + 32a6: 4123 lsli r1, r1, 3 + 32a8: 1044 lrw r2, 0x20000070 // 32b8 + 32aa: 60c4 addu r3, r1 + 32ac: 9240 ld.w r2, (r2, 0x0) + 32ae: b340 st.w r2, (r3, 0x0) + //} +} + 32b0: 1490 pop r15 + 32b2: 0000 bkpt + 32b4: 200002f0 .long 0x200002f0 + 32b8: 20000070 .long 0x20000070 + +Disassembly of section .text.PB_Protect_Task: + +000032bc : + +/********************************************************************* + * @fn PB_Protect_Task + * @brief PB - PB保护任务 + */ +void PB_Protect_Task(void){ + 32bc: 14d1 push r4, r15 + if(g_PB.protect_flag == TRUE){ + 32be: 1091 lrw r4, 0x200002f0 // 3300 + 32c0: 8474 ld.b r3, (r4, 0x14) + 32c2: 3b41 cmpnei r3, 1 + 32c4: 081d bt 0x32fe // 32fe + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Protect ...."); + 32c6: 1030 lrw r1, 0x5a45 // 3304 + 32c8: 3000 movi r0, 0 + 32ca: e3fffe6f bsr 0x2fa8 // 2fa8 + if(PB_OVERCURR_PWR_BUS == 0x00){ + 32ce: 106f lrw r3, 0x20000048 // 3308 + 32d0: 3101 movi r1, 1 + 32d2: 9300 ld.w r0, (r3, 0x0) + 32d4: e3ffefd2 bsr 0x1278 // 1278 + 32d8: 3840 cmpnei r0, 0 + 32da: 0812 bt 0x32fe // 32fe + if(SysTick_1ms - g_PB.protect_tick >= g_PB.protect_time){ + 32dc: 3284 movi r2, 132 + 32de: 4243 lsli r2, r2, 3 + 32e0: 106b lrw r3, 0x20000070 // 330c + 32e2: 6090 addu r2, r4 + 32e4: 9240 ld.w r2, (r2, 0x0) + 32e6: 9360 ld.w r3, (r3, 0x0) + 32e8: 60ca subu r3, r2 + 32ea: 3283 movi r2, 131 + 32ec: 4243 lsli r2, r2, 3 + 32ee: 6090 addu r2, r4 + 32f0: 9240 ld.w r2, (r2, 0x0) + 32f2: 648c cmphs r3, r2 + 32f4: 0c05 bf 0x32fe // 32fe + g_PB.protect_flag = FALSE; + 32f6: 3300 movi r3, 0 + 32f8: a474 st.b r3, (r4, 0x14) + g_PB.enable = TRUE; + 32fa: 3301 movi r3, 1 + 32fc: a472 st.b r3, (r4, 0x12) + + //Dbg_Println(DBG_BIT_SYS_STATUS, "重新开启PB电源"); + } + } + } +} + 32fe: 1491 pop r4, r15 + 3300: 200002f0 .long 0x200002f0 + 3304: 00005a45 .long 0x00005a45 + 3308: 20000048 .long 0x20000048 + 330c: 20000070 .long 0x20000070 + +Disassembly of section .text.PB_Scan_State_Task: + +00003310 : + +/********************************************************************* + * @fn PB_Scan_State_Task + * @brief PB - 扫描状态 - 1ms一次，确保状态可以及时更新 + */ +void PB_Scan_State_Task(void){ + 3310: 14d0 push r15 + + /*检测OverCurr引脚状态，High:过流保护中，Low:正常工作中*/ + if(PB_OVERCURR_PWR_BUS == 0x01){ + 3312: 106a lrw r3, 0x20000048 // 3338 + 3314: 3101 movi r1, 1 + 3316: 9300 ld.w r0, (r3, 0x0) + 3318: e3ffefb0 bsr 0x1278 // 1278 + 331c: 3841 cmpnei r0, 1 + 331e: 080c bt 0x3336 // 3336 + 3320: e3fffe4c bsr 0x2fb8 // 2fb8 + PB_Set_Power_State(FALSE); + g_PB.protect_flag = TRUE; + 3324: 1066 lrw r3, 0x200002f0 // 333c + 3326: 3201 movi r2, 1 + g_PB.protect_tick = SysTick_1ms; + 3328: 3184 movi r1, 132 + g_PB.protect_flag = TRUE; + 332a: a354 st.b r2, (r3, 0x14) + g_PB.protect_tick = SysTick_1ms; + 332c: 4123 lsli r1, r1, 3 + 332e: 1045 lrw r2, 0x20000070 // 3340 + 3330: 60c4 addu r3, r1 + 3332: 9240 ld.w r2, (r2, 0x0) + 3334: b340 st.w r2, (r3, 0x0) + + //Dbg_Println(DBG_BIT_SYS_STATUS, "检测到 OverCurr High状态"); + } +} + 3336: 1490 pop r15 + 3338: 20000048 .long 0x20000048 + 333c: 200002f0 .long 0x200002f0 + 3340: 20000070 .long 0x20000070 + +Disassembly of section .text.PowerBus_FillSendBuff: + +00003344 : +/********************************************************************* + * @fn PowerBus_FillSendBuff + * @brief PowerBus - 写入发送缓冲区中 + * @return NULL + */ +void PowerBus_FillSendBuff(U8_T resendNum,U8_T *data,U8_T len){ + 3344: 14d2 push r4-r5, r15 + 3346: 3364 movi r3, 100 + 3348: 648c cmphs r3, r2 + 334a: 6d4b mov r5, r2 + 334c: 0802 bt 0x3350 // 3350 + 334e: 3564 movi r5, 100 + if(len >= PB_BUFFER_SIZE) len = PB_BUFFER_SIZE; + + g_PB.resendNum = resendNum; + 3350: 106d lrw r3, 0x200002f0 // 3384 + 3352: 108e lrw r4, 0x3a9 // 3388 + 3354: 610c addu r4, r3 + 3356: a400 st.b r0, (r4, 0x0) + g_PB.sendbufferlen[g_PB.sendWriteCnt] = len; + 3358: 3480 movi r4, 128 + 335a: 610c addu r4, r3 + 335c: 8400 ld.b r0, (r4, 0x0) + 335e: 60c0 addu r3, r0 + 3360: 2380 addi r3, 129 + 3362: a3a0 st.b r5, (r3, 0x0) + memcpy(g_PB.sendbuffer[g_PB.sendWriteCnt], data, len); + 3364: 3364 movi r3, 100 + 3366: 7c0c mult r0, r3 + 3368: 1069 lrw r3, 0x20000379 // 338c + 336a: 600c addu r0, r3 + 336c: 7494 zextb r2, r5 + 336e: e3ffec87 bsr 0xc7c // c7c <__memcpy_fast> + + g_PB.sendWriteCnt++; + 3372: 8460 ld.b r3, (r4, 0x0) + 3374: 2300 addi r3, 1 + 3376: 74cc zextb r3, r3 + if(g_PB.sendWriteCnt >= PB_BUFFER_NUM){ + 3378: 3b07 cmphsi r3, 8 + 337a: 0803 bt 0x3380 // 3380 + g_PB.sendWriteCnt = 0; + 337c: a460 st.b r3, (r4, 0x0) + } +} + 337e: 1492 pop r4-r5, r15 + g_PB.sendWriteCnt = 0; + 3380: 3300 movi r3, 0 + 3382: 07fd br 0x337c // 337c + 3384: 200002f0 .long 0x200002f0 + 3388: 000003a9 .long 0x000003a9 + 338c: 20000379 .long 0x20000379 + +Disassembly of section .text.PowerBus_PackFillBuff: + +00003390 : +/********************************************************************* + * @fn PowerBus_PackFillBuff + * @brief PowerBus - 数据打包并写入发生缓冲区中 + * @return NULL + */ +void PowerBus_PackFillBuff(U8_T resendNum,U8_T cmd,U8_T *data,U8_T len){ + 3390: 14d4 push r4-r7, r15 + 3392: 1422 subi r14, r14, 8 + + g_PB.sendSN++; + 3394: 11a6 lrw r5, 0x20000350 // 342c +void PowerBus_PackFillBuff(U8_T resendNum,U8_T cmd,U8_T *data,U8_T len){ + 3396: b841 st.w r2, (r14, 0x4) + g_PB.sendSN++; + 3398: 855d ld.b r2, (r5, 0x1d) + 339a: 2200 addi r2, 1 +void PowerBus_PackFillBuff(U8_T resendNum,U8_T cmd,U8_T *data,U8_T len){ + 339c: b820 st.w r1, (r14, 0x0) + g_PB.sendSN++; + 339e: 7488 zextb r2, r2 + if(g_PB.sendSN >= 0xFA) g_PB.sendSN = 0x01; //SN号范围 1~250 + 33a0: 31f9 movi r1, 249 + 33a2: 6484 cmphs r1, r2 + 33a4: 0c3f bf 0x3422 // 3422 + 33a6: a55d st.b r2, (r5, 0x1d) + + g_PB.resendNum = resendNum; + 33a8: 1142 lrw r2, 0x20000699 // 3430 + 33aa: a200 st.b r0, (r2, 0x0) + + if((len + PowerBUS_FMT_PARAM) >= PB_BUFFER_SIZE) len = PB_BUFFER_SIZE - PowerBUS_FMT_PARAM; //参数加上包头长度大于上限 + 33ac: 325f movi r2, 95 + 33ae: 64c9 cmplt r2, r3 + 33b0: 0c02 bf 0x33b4 // 33b4 + 33b2: 3360 movi r3, 96 + + g_PB.sendbufferlen[g_PB.sendWriteCnt] = len + PowerBUS_FMT_PARAM; + 33b4: 1180 lrw r4, 0x200002f0 // 3434 + 33b6: 3680 movi r6, 128 + 33b8: 6190 addu r6, r4 + 33ba: 8600 ld.b r0, (r6, 0x0) + 33bc: 5b4e addi r2, r3, 4 + 33be: 5c20 addu r1, r4, r0 + 33c0: 7488 zextb r2, r2 + 33c2: 2180 addi r1, 129 + 33c4: a140 st.b r2, (r1, 0x0) + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN] = g_PB.sendbufferlen[g_PB.sendWriteCnt]; + 33c6: 3164 movi r1, 100 + 33c8: 7c04 mult r0, r1 + 33ca: 5c20 addu r1, r4, r0 + 33cc: 3789 movi r7, 137 + 33ce: 61c4 addu r7, r1 + 33d0: a740 st.b r2, (r7, 0x0) + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_SN] = g_PB.sendSN; + 33d2: 328a movi r2, 138 + 33d4: 6084 addu r2, r1 + 33d6: 85bd ld.b r5, (r5, 0x1d) + 33d8: a2a0 st.b r5, (r2, 0x0) + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = 0x00; + 33da: 358b movi r5, 139 + 33dc: 5954 addu r2, r1, r5 + 33de: 3700 movi r7, 0 + 33e0: a2e0 st.b r7, (r2, 0x0) + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CMD] = cmd; + 33e2: 218b addi r1, 140 + 33e4: d84e0000 ld.b r2, (r14, 0x0) + 33e8: a140 st.b r2, (r1, 0x0) + + memcpy(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_PARAM], data, len); + 33ea: 1054 lrw r2, 0x2000037d // 3438 + 33ec: 6008 addu r0, r2 + 33ee: 9821 ld.w r1, (r14, 0x4) + 33f0: 6c8f mov r2, r3 + 33f2: e3ffec45 bsr 0xc7c // c7c <__memcpy_fast> + + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = PB_CheckSum(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + 33f6: 86e0 ld.b r7, (r6, 0x0) + 33f8: 5c7c addu r3, r4, r7 + 33fa: 2380 addi r3, 129 + 33fc: 8320 ld.b r1, (r3, 0x0) + 33fe: 3364 movi r3, 100 + 3400: 7cdc mult r3, r7 + 3402: 100f lrw r0, 0x20000379 // 343c + 3404: 600c addu r0, r3 + 3406: b860 st.w r3, (r14, 0x0) + +// Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Data Buff:", data, len); +// Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Send Buff:", g_PB.sendbuffer[g_PB.sendWriteCnt], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + + g_PB.sendWriteCnt++; + 3408: 2700 addi r7, 1 + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = PB_CheckSum(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + 340a: e3ffff3b bsr 0x3280 // 3280 + 340e: 9860 ld.w r3, (r14, 0x0) + 3410: 610c addu r4, r3 + g_PB.sendWriteCnt++; + 3412: 75dc zextb r7, r7 + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = PB_CheckSum(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + 3414: 6150 addu r5, r4 + if(g_PB.sendWriteCnt >= PB_BUFFER_NUM){ + 3416: 3f07 cmphsi r7, 8 + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = PB_CheckSum(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + 3418: a500 st.b r0, (r5, 0x0) + if(g_PB.sendWriteCnt >= PB_BUFFER_NUM){ + 341a: 0806 bt 0x3426 // 3426 + g_PB.sendWriteCnt++; + 341c: a6e0 st.b r7, (r6, 0x0) + g_PB.sendWriteCnt = 0; + } + +} + 341e: 1402 addi r14, r14, 8 + 3420: 1494 pop r4-r7, r15 + if(g_PB.sendSN >= 0xFA) g_PB.sendSN = 0x01; //SN号范围 1~250 + 3422: 3201 movi r2, 1 + 3424: 07c1 br 0x33a6 // 33a6 + g_PB.sendWriteCnt = 0; + 3426: 3300 movi r3, 0 + 3428: a660 st.b r3, (r6, 0x0) +} + 342a: 07fa br 0x341e // 341e + 342c: 20000350 .long 0x20000350 + 3430: 20000699 .long 0x20000699 + 3434: 200002f0 .long 0x200002f0 + 3438: 2000037d .long 0x2000037d + 343c: 20000379 .long 0x20000379 + +Disassembly of section .text.PowerBUS_GetCommState: + +00003440 : + * @brief BLV PowerBus 获取当前PowerBUS总线发送状态 + * @return none + */ +U8_T PowerBUS_GetCommState(void){ + + if(g_PB.sendWriteCnt != g_PB.sendReadCnt){ + 3440: 1066 lrw r3, 0x200002f0 // 3458 + 3442: 3280 movi r2, 128 + 3444: 608c addu r2, r3 + 3446: 235f addi r3, 96 + 3448: 8240 ld.b r2, (r2, 0x0) + 344a: 837f ld.b r3, (r3, 0x1f) + 344c: 64ca cmpne r2, r3 + 344e: 3000 movi r0, 0 + 3450: 6001 addc r0, r0 + 3452: 7400 zextb r0, r0 + return 0x01; + } + + return 0x00; +} + 3454: 783c jmp r15 + 3456: 0000 bkpt + 3458: 200002f0 .long 0x200002f0 + +Disassembly of section .text.PB_FilACkPacket: + +0000345c : +/********************************************************************* + * @fn PB_FilACkPacket + * @brief BLV PB控制协议 - 数据打包函数 + * @return none + */ +void PB_FilACkPacket(U8_T *ackBuff,U8_T ackLen){ + 345c: 14d1 push r4, r15 + ackBuff[PB_FMT_ADDR_TX] = PB_DEV_Addr; + 345e: 3301 movi r3, 1 + 3460: a060 st.b r3, (r0, 0x0) +void PB_FilACkPacket(U8_T *ackBuff,U8_T ackLen){ + 3462: 6d03 mov r4, r0 + ackBuff[PB_FMT_TYPE] = (g_PB.recv_sn & 0x0F); + 3464: 106a lrw r3, 0x200002f0 // 348c + 3466: 8357 ld.b r2, (r3, 0x17) + 3468: 300f movi r0, 15 + 346a: 6880 and r2, r0 + 346c: a441 st.b r2, (r4, 0x1) + ackBuff[PB_FMT_DEV_TYPE] = PB_DEV_TYPE; + 346e: 3230 movi r2, 48 + 3470: a442 st.b r2, (r4, 0x2) + ackBuff[PB_FMT_ADDR_RX] = g_PB.recv_addr; + 3472: 8356 ld.b r2, (r3, 0x16) + 3474: a443 st.b r2, (r4, 0x3) + ackBuff[PB_FMT_LEN] = ackLen; + ackBuff[PB_FMT_CKS] = 0x00; + 3476: 3200 movi r2, 0 + ackBuff[PB_FMT_LEN] = ackLen; + 3478: a424 st.b r1, (r4, 0x4) + ackBuff[PB_FMT_CKS] = 0x00; + 347a: a445 st.b r2, (r4, 0x5) + ackBuff[PB_FMT_CMD] = g_PB.recv_cmd; + 347c: 8378 ld.b r3, (r3, 0x18) + 347e: a466 st.b r3, (r4, 0x6) + + ackBuff[PB_FMT_CKS] = PB_CheckSum(ackBuff, ackLen); + 3480: 7445 zexth r1, r1 + 3482: 6c13 mov r0, r4 + 3484: e3fffefe bsr 0x3280 // 3280 + 3488: a405 st.b r0, (r4, 0x5) +} + 348a: 1491 pop r4, r15 + 348c: 200002f0 .long 0x200002f0 + +Disassembly of section .text.PB_RS485_ReplyAck: + +00003490 : +/********************************************************************* + * @fn PB_RS485_ReplyAck + * @brief BLV PB控制协议 - 应答回复 + * @return none + */ +void PB_RS485_ReplyAck(void){ + 3490: 14d2 push r4-r5, r15 + g_PB.ackLen += PB_FMT_PARA; + 3492: 10ab lrw r5, 0x200002f0 // 34bc + 3494: 108b lrw r4, 0x3aa // 34c0 + 3496: 6114 addu r4, r5 + 3498: 8c60 ld.h r3, (r4, 0x0) + 349a: 2306 addi r3, 7 + 349c: 74cd zexth r3, r3 + + PB_FilACkPacket(g_PB.ackbuff,g_PB.ackLen); + 349e: 2518 addi r5, 25 + 34a0: 744c zextb r1, r3 + 34a2: 6c17 mov r0, r5 + g_PB.ackLen += PB_FMT_PARA; + 34a4: ac60 st.h r3, (r4, 0x0) + PB_FilACkPacket(g_PB.ackbuff,g_PB.ackLen); + 34a6: e3ffffdb bsr 0x345c // 345c + RCU_PB_SendData(g_PB.ackbuff,g_PB.ackLen); + 34aa: 1067 lrw r3, 0x2000003c // 34c4 + 34ac: 8c40 ld.h r2, (r4, 0x0) + 34ae: 9300 ld.w r0, (r3, 0x0) + 34b0: 6c57 mov r1, r5 + 34b2: e3fff129 bsr 0x1704 // 1704 + + g_PB.ackLen = 0; + 34b6: 3300 movi r3, 0 + 34b8: ac60 st.h r3, (r4, 0x0) +} + 34ba: 1492 pop r4-r5, r15 + 34bc: 200002f0 .long 0x200002f0 + 34c0: 000003aa .long 0x000003aa + 34c4: 2000003c .long 0x2000003c + +Disassembly of section .text.PB_Set_CH_SaveBrightnessInfo: + +000034c8 : +/********************************************************************* + * @fn PB_Set_CH_SaveBrightnessInfo + * @brief PB - 设置灯带回路保存灯光参数 + * @return 0x00:处理成功，其他值：处理失败 + */ +U8_T PB_Set_CH_SaveBrightnessInfo(U8_T loop,U8_T brightness,U16_T gradualtime){ + 34c8: 14d1 push r4, r15 + + switch(loop){ + 34ca: 3803 cmphsi r0, 4 +U8_T PB_Set_CH_SaveBrightnessInfo(U8_T loop,U8_T brightness,U16_T gradualtime){ + 34cc: 6d03 mov r4, r0 + switch(loop){ + 34ce: 0814 bt 0x34f6 // 34f6 + 34d0: 106b lrw r3, 0x200007a4 // 34fc + 34d2: e3ffe671 bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 34d6: 0602 .short 0x0602 + 34d8: 0d0a .short 0x0d0a + case PWM_OUT_CH1: + g_eeprom.brightness[PWM_OUT_CH1] = brightness; + 34da: a329 st.b r1, (r3, 0x9) + g_eeprom.gradialTime[PWM_OUT_CH1] = gradualtime; + 34dc: ab47 st.h r2, (r3, 0xe) + return 0x01; + break; + } + + return 0x00; +} + 34de: 6c13 mov r0, r4 + 34e0: 1491 pop r4, r15 + g_eeprom.brightness[PWM_OUT_CH2] = brightness; + 34e2: a32a st.b r1, (r3, 0xa) + g_eeprom.gradialTime[PWM_OUT_CH2] = gradualtime; + 34e4: ab48 st.h r2, (r3, 0x10) + return 0x00; + 34e6: 3400 movi r4, 0 + break; + 34e8: 07fb br 0x34de // 34de + g_eeprom.brightness[PWM_OUT_CH3] = brightness; + 34ea: a32b st.b r1, (r3, 0xb) + g_eeprom.gradialTime[PWM_OUT_CH3] = gradualtime; + 34ec: ab49 st.h r2, (r3, 0x12) + 34ee: 07fc br 0x34e6 // 34e6 + g_eeprom.brightness[PWM_OUT_CH4] = brightness; + 34f0: a32c st.b r1, (r3, 0xc) + g_eeprom.gradialTime[PWM_OUT_CH4] = gradualtime; + 34f2: ab4a st.h r2, (r3, 0x14) + 34f4: 07f9 br 0x34e6 // 34e6 + return 0x01; + 34f6: 3401 movi r4, 1 + 34f8: 07f3 br 0x34de // 34de + 34fa: 0000 bkpt + 34fc: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_Set_CH_SaveSwitchInfo: + +00003500 : +/********************************************************************* + * @fn PB_Set_CH_SaveSwitchInfo + * @brief PB - 设置灯带回路保存开关状态参数 + * @return 0x00:处理成功，其他值：处理失败 + */ +U8_T PB_Set_CH_SaveSwitchInfo(U8_T loop,U8_T switch_state){ + 3500: 14d0 push r15 + + switch(loop){ + 3502: 3803 cmphsi r0, 4 +U8_T PB_Set_CH_SaveSwitchInfo(U8_T loop,U8_T switch_state){ + 3504: 6cc3 mov r3, r0 + switch(loop){ + 3506: 0810 bt 0x3526 // 3526 + 3508: 1049 lrw r2, 0x200007a4 // 352c + 350a: e3ffe655 bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 350e: 0502 .short 0x0502 + 3510: 0a08 .short 0x0a08 + case PWM_OUT_CH1: + g_eeprom.swithcState[PWM_OUT_CH1] = switch_state; + 3512: a225 st.b r1, (r2, 0x5) + return 0x01; + break; + } + + return 0x00; +} + 3514: 6c0f mov r0, r3 + 3516: 1490 pop r15 + g_eeprom.swithcState[PWM_OUT_CH2] = switch_state; + 3518: a226 st.b r1, (r2, 0x6) + return 0x00; + 351a: 3300 movi r3, 0 + break; + 351c: 07fc br 0x3514 // 3514 + g_eeprom.swithcState[PWM_OUT_CH3] = switch_state; + 351e: a227 st.b r1, (r2, 0x7) + 3520: 07fd br 0x351a // 351a + g_eeprom.swithcState[PWM_OUT_CH4] = switch_state; + 3522: a228 st.b r1, (r2, 0x8) + 3524: 07fb br 0x351a // 351a + return 0x01; + 3526: 3301 movi r3, 1 + 3528: 07f6 br 0x3514 // 3514 + 352a: 0000 bkpt + 352c: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_ACK_SET_LED_BRIGHTNESS: + +00003530 : +/********************************************************************* + * @fn PB_ACK_SET_LED_BRIGHTNESS + * @brief BLV PB控制协议 - 设定灯带亮度 + * @return none + */ +void PB_ACK_SET_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3530: 14d4 push r4-r7, r15 + 3532: 1427 subi r14, r14, 28 + U8_T chnMask = para[PB_FMT_PARA]; + 3534: 8067 ld.b r3, (r0, 0x7) + 3536: b862 st.w r3, (r14, 0x8) + U8_T i = 0,save_flag = 0; + 3538: 3300 movi r3, 0 + 353a: 3509 movi r5, 9 + 353c: b861 st.w r3, (r14, 0x4) +void PB_ACK_SET_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 353e: 6dc3 mov r7, r0 + + temp_val = para[PB_FMT_PARA+6+i]*100; + PWM_SetCHGradualTime(i, temp_val); + PWM_SetOutBrightness(i, para[PB_FMT_PARA+2+i]); + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d",i,para[PB_FMT_PARA+2+i],para[PB_FMT_PARA+6]); + 3540: 1160 lrw r3, 0x5a55 // 35c0 + 3542: 6140 addu r5, r0 +void PB_ACK_SET_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3544: b823 st.w r1, (r14, 0xc) + 3546: b844 st.w r2, (r14, 0x10) + U8_T chnMask = para[PB_FMT_PARA]; + 3548: 3400 movi r4, 0 + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d",i,para[PB_FMT_PARA+2+i],para[PB_FMT_PARA+6]); + 354a: b865 st.w r3, (r14, 0x14) + 354c: 74d0 zextb r3, r4 + 354e: b866 st.w r3, (r14, 0x18) + if((chnMask & (0x01 << i)) != 0x00){ + 3550: 9862 ld.w r3, (r14, 0x8) + 3552: 70d2 asr r3, r4 + 3554: 3201 movi r2, 1 + 3556: 68c8 and r3, r2 + 3558: 3b40 cmpnei r3, 0 + 355a: 0c20 bf 0x359a // 359a + temp_val = para[PB_FMT_PARA+6+i]*100; + 355c: 3364 movi r3, 100 + 355e: 85c4 ld.b r6, (r5, 0x4) + 3560: 7d8c mult r6, r3 + 3562: 7599 zexth r6, r6 + PWM_SetCHGradualTime(i, temp_val); + 3564: 6c5b mov r1, r6 + 3566: 7410 zextb r0, r4 + 3568: e0000bd2 bsr 0x4d0c // 4d0c + PWM_SetOutBrightness(i, para[PB_FMT_PARA+2+i]); + 356c: 8520 ld.b r1, (r5, 0x0) + 356e: 7410 zextb r0, r4 + 3570: e0000bd8 bsr 0x4d20 // 4d20 + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d",i,para[PB_FMT_PARA+2+i],para[PB_FMT_PARA+6]); + 3574: 874d ld.b r2, (r7, 0xd) + 3576: 8560 ld.b r3, (r5, 0x0) + 3578: 9825 ld.w r1, (r14, 0x14) + 357a: b840 st.w r2, (r14, 0x0) + 357c: 3000 movi r0, 0 + 357e: 6c93 mov r2, r4 + 3580: e3fffd14 bsr 0x2fa8 // 2fa8 + + //是否保存参数 + if( para[PB_FMT_PARA+1] == 0xF1){ + 3584: 8748 ld.b r2, (r7, 0x8) + 3586: 33f1 movi r3, 241 + 3588: 64ca cmpne r2, r3 + 358a: 0808 bt 0x359a // 359a + PB_Set_CH_SaveBrightnessInfo(i,para[PB_FMT_PARA+2+i],temp_val); + 358c: 8520 ld.b r1, (r5, 0x0) + 358e: 6c9b mov r2, r6 + 3590: 7410 zextb r0, r4 + 3592: e3ffff9b bsr 0x34c8 // 34c8 + save_flag = 0x01; + 3596: 3301 movi r3, 1 + 3598: b861 st.w r3, (r14, 0x4) + 359a: 2400 addi r4, 1 + for(i=0;i +// +// Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d",i,para[PB_FMT_PARA+3+i],temp_val); +// } +// } + + if(save_flag == 0x01){ + 35a2: 9861 ld.w r3, (r14, 0x4) + 35a4: 3b41 cmpnei r3, 1 + 35a6: 0804 bt 0x35ae // 35ae + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + 35a8: 1007 lrw r0, 0x200007a4 // 35c4 + 35aa: e0000ec1 bsr 0x532c // 532c + } + + *ackLen = 1; + 35ae: 9864 ld.w r3, (r14, 0x10) + 35b0: 3201 movi r2, 1 + 35b2: ab40 st.h r2, (r3, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 35b4: 9863 ld.w r3, (r14, 0xc) + 35b6: 3200 movi r2, 0 + 35b8: a340 st.b r2, (r3, 0x0) +} + 35ba: 1407 addi r14, r14, 28 + 35bc: 1494 pop r4-r7, r15 + 35be: 0000 bkpt + 35c0: 00005a55 .long 0x00005a55 + 35c4: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_ACK_SET_STRIP_SWITCH: + +000035c8 : + +void PB_ACK_SET_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 35c8: 14d4 push r4-r7, r15 + 35ca: 1425 subi r14, r14, 20 + U8_T chnMask = para[PB_FMT_PARA]; + 35cc: 8067 ld.b r3, (r0, 0x7) + 35ce: b861 st.w r3, (r14, 0x4) + U8_T i = 0,save_flag = 0;; + 35d0: 3300 movi r3, 0 + 35d2: 3509 movi r5, 9 + 35d4: b860 st.w r3, (r14, 0x0) +void PB_ACK_SET_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 35d6: 6d83 mov r6, r0 + for(i=0;i + 35da: 6140 addu r5, r0 +void PB_ACK_SET_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 35dc: b822 st.w r1, (r14, 0x8) + 35de: b843 st.w r2, (r14, 0xc) + U8_T chnMask = para[PB_FMT_PARA]; + 35e0: 3400 movi r4, 0 + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d ",i,para[PB_FMT_PARA+2+i]); + 35e2: b864 st.w r3, (r14, 0x10) + if((chnMask & (0x01 << i)) != 0x00){ + 35e4: 9861 ld.w r3, (r14, 0x4) + 35e6: 70d2 asr r3, r4 + 35e8: 3201 movi r2, 1 + 35ea: 68c8 and r3, r2 + 35ec: 3b40 cmpnei r3, 0 + 35ee: 75d0 zextb r7, r4 + 35f0: 0c15 bf 0x361a // 361a + Pwm_SetOnOffState(i, para[PB_FMT_PARA+2+i]); + 35f2: 8520 ld.b r1, (r5, 0x0) + 35f4: 6c1f mov r0, r7 + 35f6: e0000d11 bsr 0x5018 // 5018 + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d ",i,para[PB_FMT_PARA+2+i]); + 35fa: 8560 ld.b r3, (r5, 0x0) + 35fc: 6c93 mov r2, r4 + 35fe: 9824 ld.w r1, (r14, 0x10) + 3600: 3000 movi r0, 0 + 3602: e3fffcd3 bsr 0x2fa8 // 2fa8 + + //是否保存参数 + if( para[PB_FMT_PARA+1] == 0xF1){ + 3606: 8648 ld.b r2, (r6, 0x8) + 3608: 33f1 movi r3, 241 + 360a: 64ca cmpne r2, r3 + 360c: 0807 bt 0x361a // 361a + PB_Set_CH_SaveSwitchInfo(i,para[PB_FMT_PARA+2+i]); + 360e: 8520 ld.b r1, (r5, 0x0) + 3610: 6c1f mov r0, r7 + 3612: e3ffff77 bsr 0x3500 // 3500 + save_flag = 0x01; + 3616: 3301 movi r3, 1 + 3618: b860 st.w r3, (r14, 0x0) + 361a: 2400 addi r4, 1 + for(i=0;i + } + } + } + + if(save_flag == 0x01){ + 3622: 9860 ld.w r3, (r14, 0x0) + 3624: 3b41 cmpnei r3, 1 + 3626: 0804 bt 0x362e // 362e + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + 3628: 1007 lrw r0, 0x200007a4 // 3644 + 362a: e0000e81 bsr 0x532c // 532c + } + + *ackLen = 1; + 362e: 9863 ld.w r3, (r14, 0xc) + 3630: 3201 movi r2, 1 + 3632: ab40 st.h r2, (r3, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 3634: 9862 ld.w r3, (r14, 0x8) + 3636: 3200 movi r2, 0 + 3638: a340 st.b r2, (r3, 0x0) +} + 363a: 1405 addi r14, r14, 20 + 363c: 1494 pop r4-r7, r15 + 363e: 0000 bkpt + 3640: 00005a67 .long 0x00005a67 + 3644: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_ACK_SET_STRIP_ADJUST: + +00003648 : + +void PB_ACK_SET_STRIP_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3648: 14d4 push r4-r7, r15 + 364a: 1425 subi r14, r14, 20 + U8_T chnMask = para[PB_FMT_PARA]; + 364c: 8067 ld.b r3, (r0, 0x7) + 364e: b862 st.w r3, (r14, 0x8) +void PB_ACK_SET_STRIP_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3650: b823 st.w r1, (r14, 0xc) + 3652: 6dcb mov r7, r2 + if((chnMask & (0x01 << i)) != 0x00){ + temp_val = para[PB_FMT_PARA+3+i*3]; + temp_val = temp_val * 100; + PWM_SetAutoAdjust(i, para[PB_FMT_PARA+1+i*3],para[PB_FMT_PARA+2+i*3],temp_val); + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d %dms",i,para[PB_FMT_PARA+1+i*3],para[PB_FMT_PARA+2+i*3],temp_val); + 3654: 1074 lrw r3, 0x5a77 // 36a4 + 3656: 589e addi r4, r0, 8 + U8_T chnMask = para[PB_FMT_PARA]; + 3658: 3500 movi r5, 0 + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d %dms",i,para[PB_FMT_PARA+1+i*3],para[PB_FMT_PARA+2+i*3],temp_val); + 365a: b864 st.w r3, (r14, 0x10) + if((chnMask & (0x01 << i)) != 0x00){ + 365c: 9862 ld.w r3, (r14, 0x8) + 365e: 70d6 asr r3, r5 + 3660: 3201 movi r2, 1 + 3662: 68c8 and r3, r2 + 3664: 3b40 cmpnei r3, 0 + 3666: 7414 zextb r0, r5 + 3668: 0c12 bf 0x368c // 368c + temp_val = para[PB_FMT_PARA+3+i*3]; + 366a: 84c2 ld.b r6, (r4, 0x2) + temp_val = temp_val * 100; + 366c: 3364 movi r3, 100 + 366e: 7d8c mult r6, r3 + PWM_SetAutoAdjust(i, para[PB_FMT_PARA+1+i*3],para[PB_FMT_PARA+2+i*3],temp_val); + 3670: 8441 ld.b r2, (r4, 0x1) + 3672: 8420 ld.b r1, (r4, 0x0) + 3674: 6cdb mov r3, r6 + 3676: e0000cf3 bsr 0x505c // 505c + Dbg_Println(DBG_BIT_SYS_STATUS,"Set PWM%d - %d %d %dms",i,para[PB_FMT_PARA+1+i*3],para[PB_FMT_PARA+2+i*3],temp_val); + 367a: 8460 ld.b r3, (r4, 0x0) + 367c: b8c1 st.w r6, (r14, 0x4) + 367e: 8441 ld.b r2, (r4, 0x1) + 3680: b840 st.w r2, (r14, 0x0) + 3682: 9824 ld.w r1, (r14, 0x10) + 3684: 6c97 mov r2, r5 + 3686: 3000 movi r0, 0 + 3688: e3fffc90 bsr 0x2fa8 // 2fa8 + 368c: 2500 addi r5, 1 + for(i=0;i + } + } + + *ackLen = 1; + 3694: 3301 movi r3, 1 + 3696: af60 st.h r3, (r7, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 3698: 3200 movi r2, 0 + 369a: 9863 ld.w r3, (r14, 0xc) + 369c: a340 st.b r2, (r3, 0x0) +} + 369e: 1405 addi r14, r14, 20 + 36a0: 1494 pop r4-r7, r15 + 36a2: 0000 bkpt + 36a4: 00005a77 .long 0x00005a77 + +Disassembly of section .text.PB_ACK_SET_PIRTIGGLE_LED: + +000036a8 : +/********************************************************************* + * @fn PB_ACK_SET_PIRTIGGLE_LED + * @brief BLV PB控制协议 - 设定PB总线 设定LD PIR触发LED + * @return none + */ +void PB_ACK_SET_PIRTIGGLE_LED(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 36a8: 14d2 push r4-r5, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + *ackLen = 1; + 36aa: 3301 movi r3, 1 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 36ac: 8084 ld.b r4, (r0, 0x4) + *ackLen = 1; + 36ae: aa60 st.h r3, (r2, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 36b0: 3300 movi r3, 0 +void PB_ACK_SET_PIRTIGGLE_LED(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 36b2: 6d43 mov r5, r0 + ackPara[0] = PB_CMD_Reply_Succ; + 36b4: a160 st.b r3, (r1, 0x0) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 36b6: 1049 lrw r2, 0x5740 // 36d8 + 36b8: 1029 lrw r1, 0x5a8e // 36dc + 36ba: 3000 movi r0, 0 + 36bc: e3fffc76 bsr 0x2fa8 // 2fa8 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 36c0: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_PIR_ENABLE,¶[PB_FMT_PARA + 1],para_len); + 36c2: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 36c4: 7510 zextb r4, r4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_PIR_ENABLE,¶[PB_FMT_PARA + 1],para_len); + 36c6: 2000 addi r0, 1 + 36c8: 5d5e addi r2, r5, 8 + 36ca: 7400 zextb r0, r0 + 36cc: 6cd3 mov r3, r4 + 36ce: 3109 movi r1, 9 + 36d0: e3fffe60 bsr 0x3390 // 3390 +} + 36d4: 1492 pop r4-r5, r15 + 36d6: 0000 bkpt + 36d8: 00005740 .long 0x00005740 + 36dc: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_SaveCurrInfo: + +000036e0 : +/********************************************************************* + * @fn PB_ACK_SET_SaveCurrInfo + * @brief BLV PB控制协议 - 设定PB总线 保护电流 + * @return none + */ +void PB_ACK_SET_SaveCurrInfo(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 36e0: 14d4 push r4-r7, r15 + + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA; + 36e2: 8064 ld.b r3, (r0, 0x4) + 36e4: 2b06 subi r3, 7 + //*ackLen = 0; + + if(para_len < 0x02) return ; + 36e6: 74cc zextb r3, r3 + 36e8: 3b01 cmphsi r3, 2 +void PB_ACK_SET_SaveCurrInfo(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 36ea: 6dc3 mov r7, r0 + 36ec: 6d47 mov r5, r1 + 36ee: 6d8b mov r6, r2 + if(para_len < 0x02) return ; + 36f0: 0c25 bf 0x373a // 373a + + g_PB.protect_curr = para[PB_FMT_PARA]; + 36f2: 8047 ld.b r2, (r0, 0x7) + 36f4: 1093 lrw r4, 0x200002f0 // 3740 + + Dbg_Println(DBG_BIT_SYS_STATUS,"protect_curr %d",g_PB.protect_curr); + 36f6: 1034 lrw r1, 0x5a91 // 3744 + 36f8: 3000 movi r0, 0 + g_PB.protect_curr = para[PB_FMT_PARA]; + 36fa: a455 st.b r2, (r4, 0x15) + Dbg_Println(DBG_BIT_SYS_STATUS,"protect_curr %d",g_PB.protect_curr); + 36fc: e3fffc56 bsr 0x2fa8 // 2fa8 + + /*不在范围内，设置为默认值10A*/ + if((g_PB.protect_curr < PB_SaveCurrent_Min) || (g_PB.protect_curr > PB_SaveCurrent_Max)){ + 3700: 8475 ld.b r3, (r4, 0x15) + 3702: 2b00 subi r3, 1 + 3704: 74cc zextb r3, r3 + 3706: 32a4 movi r2, 164 + 3708: 64c8 cmphs r2, r3 + 370a: 0819 bt 0x373c // 373c + g_PB.protect_curr = EEPROM_ParaDefault_SaveCurr; + 370c: 3378 movi r3, 120 + 370e: a475 st.b r3, (r4, 0x15) + + ackPara[0] = 0x01; //设置失败 + 3710: 3301 movi r3, 1 + }else{ + + ackPara[0] = 0x00; //设置成功 + 3712: a560 st.b r3, (r5, 0x0) + } + + PB_Set_SaveCurrent(g_PB.protect_curr); + 3714: 8415 ld.b r0, (r4, 0x15) + 3716: e3fffc61 bsr 0x2fd8 // 2fd8 + + if(para[PB_FMT_PARA + 1] == 0xF1){ + 371a: 8748 ld.b r2, (r7, 0x8) + 371c: 33f1 movi r3, 241 + 371e: 64ca cmpne r2, r3 + 3720: 0809 bt 0x3732 // 3732 + if(g_eeprom.save_curr != g_PB.protect_curr){ + 3722: 100a lrw r0, 0x200007a4 // 3748 + 3724: 8475 ld.b r3, (r4, 0x15) + 3726: 8041 ld.b r2, (r0, 0x1) + 3728: 64ca cmpne r2, r3 + 372a: 0c04 bf 0x3732 // 3732 + g_eeprom.save_curr = g_PB.protect_curr; + 372c: a061 st.b r3, (r0, 0x1) + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + 372e: e0000dff bsr 0x532c // 532c + } + } + + *ackLen = 1; + 3732: 3301 movi r3, 1 + 3734: ae60 st.h r3, (r6, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 3736: 3300 movi r3, 0 + 3738: a560 st.b r3, (r5, 0x0) +} + 373a: 1494 pop r4-r7, r15 + ackPara[0] = 0x00; //设置成功 + 373c: 3300 movi r3, 0 + 373e: 07ea br 0x3712 // 3712 + 3740: 200002f0 .long 0x200002f0 + 3744: 00005a91 .long 0x00005a91 + 3748: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_ACK_SET_UniversPara: + +0000374c : +/********************************************************************* + * @fn PB_ACK_SET_UniversPara + * @brief BLV PB控制协议 - 设定整体参数，设定PB整体亮度和PowerBus 总线整体亮度 + * @return none + */ +void PB_ACK_SET_UniversPara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 374c: 14d4 push r4-r7, r15 + 374e: 1422 subi r14, r14, 8 + + S8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3750: 80c4 ld.b r6, (r0, 0x4) + 3752: 2e07 subi r6, 8 + 3754: 7598 zextb r6, r6 + U8_T mask_bit = 0,rev = 0; + U32_T temp_val = 0; + + if( para_len < 5 ) return ; + 3756: 74da sextb r3, r6 + 3758: 3b24 cmplti r3, 5 +void PB_ACK_SET_UniversPara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 375a: 6d03 mov r4, r0 + 375c: b820 st.w r1, (r14, 0x0) + 375e: b841 st.w r2, (r14, 0x4) + if( para_len < 5 ) return ; + 3760: 0853 bt 0x3806 // 3806 + + mask_bit = para[PB_FMT_PARA + 1]; + 3762: 80e8 ld.b r7, (r0, 0x8) + + if((mask_bit & 0x80) != 0x00){ + 3764: 74de sextb r3, r7 + 3766: 3bdf btsti r3, 31 + 3768: 0c53 bf 0x380e // 380e + //设定全局亮度 + if( para[PB_FMT_PARA + 3] <= 100){ + 376a: 800a ld.b r0, (r0, 0xa) + 376c: 3364 movi r3, 100 + 376e: 640c cmphs r3, r0 + 3770: 0c4d bf 0x380a // 380a + g_eeprom.allBrightness = para[PB_FMT_PARA + 3]; //全局亮度 + 3772: 116b lrw r3, 0x200007a4 // 381c + U8_T mask_bit = 0,rev = 0; + 3774: 3500 movi r5, 0 + g_eeprom.allBrightness = para[PB_FMT_PARA + 3]; //全局亮度 + 3776: a302 st.b r0, (r3, 0x2) + Pwm_SetAllBrightness(g_eeprom.allBrightness); + 3778: e0000c5c bsr 0x5030 // 5030 + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightness:%d",g_pwm.allBrightness); + 377c: 1169 lrw r3, 0x20000718 // 3820 + 377e: 8341 ld.b r2, (r3, 0x1) + 3780: 1129 lrw r1, 0x5aa1 // 3824 + 3782: 3000 movi r0, 0 + 3784: e3fffc12 bsr 0x2fa8 // 2fa8 + } + if((mask_bit & 0x40) != 0x00){ + 3788: 3340 movi r3, 64 + 378a: 68dc and r3, r7 + 378c: 3b40 cmpnei r3, 0 + 378e: 0c10 bf 0x37ae // 37ae + //设定全局可调上限 + if( para[PB_FMT_PARA + 4] <= 100){ + 3790: 840b ld.b r0, (r4, 0xb) + 3792: 3364 movi r3, 100 + 3794: 640c cmphs r3, r0 + 3796: 0c3e bf 0x3812 // 3812 + g_eeprom.allBrightnessUpLimit = para[PB_FMT_PARA + 4]; //全局亮度可调上限 + 3798: 1161 lrw r3, 0x200007a4 // 381c + 379a: a303 st.b r0, (r3, 0x3) + PWM_SetUpLimitVal(g_eeprom.allBrightnessUpLimit); + 379c: e0000bfa bsr 0x4f90 // 4f90 + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightnessUpLimit:%d - %d",g_pwm.allBrightnessUpLimit,g_pwm.allPwmUpLimit); + 37a0: 1140 lrw r2, 0x20000718 // 3820 + 37a2: 8a6a ld.h r3, (r2, 0x14) + 37a4: 1121 lrw r1, 0x5ab6 // 3828 + 37a6: 8242 ld.b r2, (r2, 0x2) + 37a8: 3000 movi r0, 0 + 37aa: e3fffbff bsr 0x2fa8 // 2fa8 + } + if((mask_bit & 0x20) != 0x00){ + 37ae: 3320 movi r3, 32 + 37b0: 69cc and r7, r3 + 37b2: 3f40 cmpnei r7, 0 + 37b4: 0c13 bf 0x37da // 37da + //设定全局可调下限 + if( (para[PB_FMT_PARA + 5] <= 100) && (para[PB_FMT_PARA + 5] < g_pwm.allBrightnessUpLimit) ){ + 37b6: 840c ld.b r0, (r4, 0xc) + 37b8: 3364 movi r3, 100 + 37ba: 640c cmphs r3, r0 + 37bc: 10f9 lrw r7, 0x20000718 // 3820 + 37be: 0c2c bf 0x3816 // 3816 + 37c0: 8762 ld.b r3, (r7, 0x2) + 37c2: 64c0 cmphs r0, r3 + 37c4: 0829 bt 0x3816 // 3816 + g_eeprom.allBrightnessDownLimit = para[PB_FMT_PARA + 5]; //全局亮度可调上限 + 37c6: 1076 lrw r3, 0x200007a4 // 381c + 37c8: a304 st.b r0, (r3, 0x4) + PWM_SetDownLimitVal(g_eeprom.allBrightnessDownLimit); + 37ca: e0000c05 bsr 0x4fd4 // 4fd4 + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightnessDownLimit:%d - %d",g_pwm.allBrightnessDownLimit,g_pwm.allPwmDownLimit); + 37ce: 8f6b ld.h r3, (r7, 0x16) + 37d0: 8743 ld.b r2, (r7, 0x3) + 37d2: 1037 lrw r1, 0x5ad7 // 382c + 37d4: 3000 movi r0, 0 + 37d6: e3fffbe9 bsr 0x2fa8 // 2fa8 + } + + if(para[PB_FMT_PARA + 2] == 0xF1){ + 37da: 8449 ld.b r2, (r4, 0x9) + 37dc: 33f1 movi r3, 241 + 37de: 64ca cmpne r2, r3 + 37e0: 0804 bt 0x37e8 // 37e8 + /*保存参数*/ + + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + 37e2: 100f lrw r0, 0x200007a4 // 381c + 37e4: e0000da4 bsr 0x532c // 532c + } + + /*同时下发PowerBus*/ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_UniversPara"); + 37e8: 1032 lrw r1, 0x5afa // 3830 + 37ea: 3000 movi r0, 0 + 37ec: e3fffbde bsr 0x2fa8 // 2fa8 + PowerBus_PackFillBuff(0x03,PowerBUS_CMD_SET_UniversPara,¶[PB_FMT_PARA + 1],para_len); + 37f0: 5c5e addi r2, r4, 8 + 37f2: 6cdb mov r3, r6 + 37f4: 31f0 movi r1, 240 + 37f6: 3003 movi r0, 3 + 37f8: e3fffdcc bsr 0x3390 // 3390 + + *ackLen = 1; + 37fc: 9861 ld.w r3, (r14, 0x4) + 37fe: 3201 movi r2, 1 + 3800: ab40 st.h r2, (r3, 0x0) + + ackPara[0] = rev; + 3802: 9860 ld.w r3, (r14, 0x0) + 3804: a3a0 st.b r5, (r3, 0x0) +} + 3806: 1402 addi r14, r14, 8 + 3808: 1494 pop r4-r7, r15 + rev = 0x01; //参数错误 + 380a: 3501 movi r5, 1 + 380c: 07b8 br 0x377c // 377c + U8_T mask_bit = 0,rev = 0; + 380e: 3500 movi r5, 0 + 3810: 07bc br 0x3788 // 3788 + rev = 0x01; //参数错误 + 3812: 3501 movi r5, 1 + 3814: 07c6 br 0x37a0 // 37a0 + rev = 0x01; //参数错误 + 3816: 3501 movi r5, 1 + 3818: 07db br 0x37ce // 37ce + 381a: 0000 bkpt + 381c: 200007a4 .long 0x200007a4 + 3820: 20000718 .long 0x20000718 + 3824: 00005aa1 .long 0x00005aa1 + 3828: 00005ab6 .long 0x00005ab6 + 382c: 00005ad7 .long 0x00005ad7 + 3830: 00005afa .long 0x00005afa + +Disassembly of section .text.PB_ACK_SET_PowerBus_EnablePara: + +00003834 : +/********************************************************************* + * @fn PB_ACK_SET_PowerBus_EnablePara + * @brief BLV PB控制协议 - PB使能状态控制 + * @return none + */ +void PB_ACK_SET_PowerBus_EnablePara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3834: 14d3 push r4-r6, r15 + + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA; + 3836: 8064 ld.b r3, (r0, 0x4) + 3838: 2b06 subi r3, 7 + //*ackLen = 0; + + if(para_len < 0x02) return ; + 383a: 74cc zextb r3, r3 + 383c: 3b01 cmphsi r3, 2 +void PB_ACK_SET_PowerBus_EnablePara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 383e: 6d83 mov r6, r0 + 3840: 6d07 mov r4, r1 + 3842: 6d4b mov r5, r2 + if(para_len < 0x02) return ; + 3844: 0c1a bf 0x3878 // 3878 + + PB_Set_Power_State(para[PB_FMT_PARA]); + 3846: 8007 ld.b r0, (r0, 0x7) + 3848: e3fffc00 bsr 0x3048 // 3048 + Dbg_Println(DBG_BIT_SYS_STATUS, "Power Enable %d",para[PB_FMT_PARA]); + 384c: 8647 ld.b r2, (r6, 0x7) + 384e: 102c lrw r1, 0x5b11 // 387c + 3850: 3000 movi r0, 0 + 3852: e3fffbab bsr 0x2fa8 // 2fa8 + + if(para[PB_FMT_PARA + 1] == 0xF1){ + 3856: 8648 ld.b r2, (r6, 0x8) + 3858: 33f1 movi r3, 241 + 385a: 64ca cmpne r2, r3 + 385c: 080a bt 0x3870 // 3870 + + if(g_PB.enable != g_eeprom.powerbus_enable){ + 385e: 1069 lrw r3, 0x200002f0 // 3880 + 3860: 1009 lrw r0, 0x200007a4 // 3884 + 3862: 8372 ld.b r3, (r3, 0x12) + 3864: 8040 ld.b r2, (r0, 0x0) + 3866: 64ca cmpne r2, r3 + 3868: 0c04 bf 0x3870 // 3870 + g_eeprom.powerbus_enable = g_PB.enable; + 386a: a060 st.b r3, (r0, 0x0) + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + 386c: e0000d60 bsr 0x532c // 532c + } + } + + *ackLen = 1; + 3870: 3301 movi r3, 1 + 3872: ad60 st.h r3, (r5, 0x0) + ackPara[0] = PB_CMD_Reply_Succ; + 3874: 3300 movi r3, 0 + 3876: a460 st.b r3, (r4, 0x0) +} + 3878: 1493 pop r4-r6, r15 + 387a: 0000 bkpt + 387c: 00005b11 .long 0x00005b11 + 3880: 200002f0 .long 0x200002f0 + 3884: 200007a4 .long 0x200007a4 + +Disassembly of section .text.PB_ACK_PassThroug_Data: + +00003888 : +/********************************************************************* + * @fn PB_ACK_PassThroug_Data + * @brief BLV PB控制协议 - PB透传命令 + * @return none + */ +void PB_ACK_PassThroug_Data(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3888: 14d3 push r4-r6, r15 + 388a: 6d03 mov r4, r0 + 388c: 6d47 mov r5, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_PassThroug_Data"); + 388e: 3000 movi r0, 0 + 3890: 102c lrw r1, 0x5b21 // 38c0 +void PB_ACK_PassThroug_Data(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3892: 6d8b mov r6, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_PassThroug_Data"); + 3894: e3fffb8a bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3898: e3fffdd4 bsr 0x3440 // 3440 + 389c: 3840 cmpnei r0, 0 + + *ackLen = 1; + 389e: 3301 movi r3, 1 + 38a0: ae60 st.h r3, (r6, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 38a2: 080c bt 0x38ba // 38ba + ackPara[0] = PB_CMD_Reply_Succ; + 38a4: 3300 movi r3, 0 + 38a6: a560 st.b r3, (r5, 0x0) + + PowerBus_FillSendBuff(para[PB_FMT_PARA] + 0x01,¶[PB_FMT_PARA + 2],para[PB_FMT_PARA + 1]); + 38a8: 8407 ld.b r0, (r4, 0x7) + 38aa: 3109 movi r1, 9 + 38ac: 2000 addi r0, 1 + 38ae: 8448 ld.b r2, (r4, 0x8) + 38b0: 6050 addu r1, r4 + 38b2: 7400 zextb r0, r0 + 38b4: e3fffd48 bsr 0x3344 // 3344 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + 38b8: 1493 pop r4-r6, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 38ba: a560 st.b r3, (r5, 0x0) +} + 38bc: 07fe br 0x38b8 // 38b8 + 38be: 0000 bkpt + 38c0: 00005b21 .long 0x00005b21 + +Disassembly of section .text.PB_ACK_SET_PB_LEDS_BRIGHTNESS: + +000038c4 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 LED亮度 --按照地址段控制 每个回路可单独设定亮度 + * @return none + */ +void PB_ACK_SET_PB_LEDS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 38c4: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 38c6: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LEDS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 38c8: 6d43 mov r5, r0 + 38ca: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHTNESS"); + 38cc: 3000 movi r0, 0 + 38ce: 102d lrw r1, 0x5b38 // 3900 +void PB_ACK_SET_PB_LEDS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 38d0: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHTNESS"); + 38d2: e3fffb6b bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 38d6: e3fffdb5 bsr 0x3440 // 3440 + 38da: 3840 cmpnei r0, 0 + *ackLen = 1; + 38dc: 3301 movi r3, 1 + 38de: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 38e0: 080d bt 0x38fa // 38fa + ackPara[0] = PB_CMD_Reply_Succ; + 38e2: 3300 movi r3, 0 + 38e4: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 38e6: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 38e8: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 38ea: 2000 addi r0, 1 + 38ec: 74d0 zextb r3, r4 + 38ee: 5d5e addi r2, r5, 8 + 38f0: 7400 zextb r0, r0 + 38f2: 3104 movi r1, 4 + 38f4: e3fffd4e bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 38f8: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 38fa: a660 st.b r3, (r6, 0x0) +} + 38fc: 07fe br 0x38f8 // 38f8 + 38fe: 0000 bkpt + 3900: 00005b38 .long 0x00005b38 + +Disassembly of section .text.PB_ACK_SET_PB_LEDS_ADJUST: + +00003904 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LED亮度递增递减调节 --按照地址段控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3904: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3906: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LEDS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3908: 6d43 mov r5, r0 + 390a: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_ADJUST"); + 390c: 3000 movi r0, 0 + 390e: 102d lrw r1, 0x5b56 // 3940 +void PB_ACK_SET_PB_LEDS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3910: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_ADJUST"); + 3912: e3fffb4b bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3916: e3fffd95 bsr 0x3440 // 3440 + 391a: 3840 cmpnei r0, 0 + *ackLen = 1; + 391c: 3301 movi r3, 1 + 391e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3920: 080d bt 0x393a // 393a + ackPara[0] = PB_CMD_Reply_Succ; + 3922: 3300 movi r3, 0 + 3924: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 3926: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3928: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 392a: 2000 addi r0, 1 + 392c: 74d0 zextb r3, r4 + 392e: 5d5e addi r2, r5, 8 + 3930: 7400 zextb r0, r0 + 3932: 3106 movi r1, 6 + 3934: e3fffd2e bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 3938: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 393a: a660 st.b r3, (r6, 0x0) +} + 393c: 07fe br 0x3938 // 3938 + 393e: 0000 bkpt + 3940: 00005b56 .long 0x00005b56 + +Disassembly of section .text.PB_ACK_SET_PB_LEDS_SWITCH: + +00003944 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 LED单开关状态 --按照单个回路控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3944: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3946: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LEDS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3948: 6d43 mov r5, r0 + 394a: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_SWITCH"); + 394c: 3000 movi r0, 0 + 394e: 102d lrw r1, 0x5b70 // 3980 +void PB_ACK_SET_PB_LEDS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3950: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_SWITCH"); + 3952: e3fffb2b bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3956: e3fffd75 bsr 0x3440 // 3440 + 395a: 3840 cmpnei r0, 0 + *ackLen = 1; + 395c: 3301 movi r3, 1 + 395e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3960: 080d bt 0x397a // 397a + ackPara[0] = PB_CMD_Reply_Succ; + 3962: 3300 movi r3, 0 + 3964: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3966: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3968: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 396a: 2000 addi r0, 1 + 396c: 74d0 zextb r3, r4 + 396e: 5d5e addi r2, r5, 8 + 3970: 7400 zextb r0, r0 + 3972: 3105 movi r1, 5 + 3974: e3fffd0e bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 3978: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 397a: a660 st.b r3, (r6, 0x0) +} + 397c: 07fe br 0x3978 // 3978 + 397e: 0000 bkpt + 3980: 00005b70 .long 0x00005b70 + +Disassembly of section .text.PB_ACK_SET_PB_LEDS_BRIGHT: + +00003984 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_BRIGHT + * @brief BLV PB控制协议 - 设定PB总线 LED亮度 --按照地址段控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_BRIGHT(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3984: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3986: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LEDS_BRIGHT(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3988: 6d43 mov r5, r0 + 398a: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHT"); + 398c: 3000 movi r0, 0 + 398e: 102d lrw r1, 0x5b8a // 39c0 +void PB_ACK_SET_PB_LEDS_BRIGHT(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3990: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHT"); + 3992: e3fffb0b bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3996: e3fffd55 bsr 0x3440 // 3440 + 399a: 3840 cmpnei r0, 0 + *ackLen = 1; + 399c: 3301 movi r3, 1 + 399e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 39a0: 080d bt 0x39ba // 39ba + ackPara[0] = PB_CMD_Reply_Succ; + 39a2: 3300 movi r3, 0 + 39a4: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHT,¶[PB_FMT_PARA + 1],para_len); + 39a6: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 39a8: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHT,¶[PB_FMT_PARA + 1],para_len); + 39aa: 2000 addi r0, 1 + 39ac: 74d0 zextb r3, r4 + 39ae: 5d5e addi r2, r5, 8 + 39b0: 7400 zextb r0, r0 + 39b2: 3107 movi r1, 7 + 39b4: e3fffcee bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 39b8: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 39ba: a660 st.b r3, (r6, 0x0) +} + 39bc: 07fe br 0x39b8 // 39b8 + 39be: 0000 bkpt + 39c0: 00005b8a .long 0x00005b8a + +Disassembly of section .text.PB_ACK_SET_PB_LED_BRIGHTNESS: + +000039c4 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 LED单回路亮度 --按照单个回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 39c4: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 39c6: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 39c8: 6d43 mov r5, r0 + 39ca: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_BRIGHTNESS"); + 39cc: 3000 movi r0, 0 + 39ce: 102d lrw r1, 0x5ba4 // 3a00 +void PB_ACK_SET_PB_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 39d0: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_BRIGHTNESS"); + 39d2: e3fffaeb bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 39d6: e3fffd35 bsr 0x3440 // 3440 + 39da: 3840 cmpnei r0, 0 + *ackLen = 1; + 39dc: 3301 movi r3, 1 + 39de: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 39e0: 080d bt 0x39fa // 39fa + ackPara[0] = PB_CMD_Reply_Succ; + 39e2: 3300 movi r3, 0 + 39e4: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 39e6: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 39e8: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 39ea: 2000 addi r0, 1 + 39ec: 74d0 zextb r3, r4 + 39ee: 5d5e addi r2, r5, 8 + 39f0: 7400 zextb r0, r0 + 39f2: 3101 movi r1, 1 + 39f4: e3fffcce bsr 0x3390 // 3390 + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + + } + +} + 39f8: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 39fa: a660 st.b r3, (r6, 0x0) +} + 39fc: 07fe br 0x39f8 // 39f8 + 39fe: 0000 bkpt + 3a00: 00005ba4 .long 0x00005ba4 + +Disassembly of section .text.PB_ACK_SET_PB_LED_Adjust: + +00003a04 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_Adjust + * @brief BLV PB控制协议 - 设定PB总线 LED单回路亮度调节 --按照单独回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a04: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3a06: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LED_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a08: 6d43 mov r5, r0 + 3a0a: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_Adjust"); + 3a0c: 3000 movi r0, 0 + 3a0e: 102d lrw r1, 0x5bc1 // 3a40 +void PB_ACK_SET_PB_LED_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a10: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_Adjust"); + 3a12: e3fffacb bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3a16: e3fffd15 bsr 0x3440 // 3440 + 3a1a: 3840 cmpnei r0, 0 + *ackLen = 1; + 3a1c: 3301 movi r3, 1 + 3a1e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3a20: 080d bt 0x3a3a // 3a3a + ackPara[0] = PB_CMD_Reply_Succ; + 3a22: 3300 movi r3, 0 + 3a24: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 3a26: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3a28: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 3a2a: 2000 addi r0, 1 + 3a2c: 74d0 zextb r3, r4 + 3a2e: 5d5e addi r2, r5, 8 + 3a30: 7400 zextb r0, r0 + 3a32: 3103 movi r1, 3 + 3a34: e3fffcae bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + + } +} + 3a38: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 3a3a: a660 st.b r3, (r6, 0x0) +} + 3a3c: 07fe br 0x3a38 // 3a38 + 3a3e: 0000 bkpt + 3a40: 00005bc1 .long 0x00005bc1 + +Disassembly of section .text.PB_ACK_SET_PB_LED_SWITCH: + +00003a44 : +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 LED单回路开关状态 --按照单独回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a44: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3a46: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_LED_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a48: 6d43 mov r5, r0 + 3a4a: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_SWITCH"); + 3a4c: 3000 movi r0, 0 + 3a4e: 102d lrw r1, 0x5bda // 3a80 +void PB_ACK_SET_PB_LED_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a50: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_SWITCH"); + 3a52: e3fffaab bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3a56: e3fffcf5 bsr 0x3440 // 3440 + 3a5a: 3840 cmpnei r0, 0 + *ackLen = 1; + 3a5c: 3301 movi r3, 1 + 3a5e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3a60: 080d bt 0x3a7a // 3a7a + ackPara[0] = PB_CMD_Reply_Succ; + 3a62: 3300 movi r3, 0 + 3a64: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3a66: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3a68: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3a6a: 2000 addi r0, 1 + 3a6c: 74d0 zextb r3, r4 + 3a6e: 5d5e addi r2, r5, 8 + 3a70: 7400 zextb r0, r0 + 3a72: 3102 movi r1, 2 + 3a74: e3fffc8e bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 3a78: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 3a7a: a660 st.b r3, (r6, 0x0) +} + 3a7c: 07fe br 0x3a78 // 3a78 + 3a7e: 0000 bkpt + 3a80: 00005bda .long 0x00005bda + +Disassembly of section .text.PB_ACK_SET_PB_ALLLED_Switch: + +00003a84 : +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLLED_Switch + * @brief BLV PB控制协议 - 设定PB总线 LED全部设备开关状态 + * @return none + */ +void PB_ACK_SET_PB_ALLLED_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a84: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3a86: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_ALLLED_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a88: 6d43 mov r5, r0 + 3a8a: 6d87 mov r6, r1 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_ALLLED_Switch"); + 3a8c: 3000 movi r0, 0 + 3a8e: 102d lrw r1, 0x5bf3 // 3ac0 +void PB_ACK_SET_PB_ALLLED_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3a90: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_ALLLED_Switch"); + 3a92: e3fffa8b bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3a96: e3fffcd5 bsr 0x3440 // 3440 + 3a9a: 3840 cmpnei r0, 0 + *ackLen = 1; + 3a9c: 3301 movi r3, 1 + 3a9e: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3aa0: 080d bt 0x3aba // 3aba + ackPara[0] = PB_CMD_Reply_Succ; + 3aa2: 3300 movi r3, 0 + 3aa4: a660 st.b r3, (r6, 0x0) + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLLED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3aa6: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3aa8: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLLED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3aaa: 2000 addi r0, 1 + 3aac: 74d0 zextb r3, r4 + 3aae: 5d5e addi r2, r5, 8 + 3ab0: 7400 zextb r0, r0 + 3ab2: 3108 movi r1, 8 + 3ab4: e3fffc6e bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 3ab8: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 3aba: a660 st.b r3, (r6, 0x0) +} + 3abc: 07fe br 0x3ab8 // 3ab8 + 3abe: 0000 bkpt + 3ac0: 00005bf3 .long 0x00005bf3 + +Disassembly of section .text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS: + +00003ac4 : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3ac4: 14d4 push r4-r7, r15 + 3ac6: 1430 subi r14, r14, 64 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3ac8: 80a4 ld.b r5, (r0, 0x4) + 3aca: 2d07 subi r5, 8 + 3acc: 7554 zextb r5, r5 + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %d",__func__,para_len); + 3ace: 6cd7 mov r3, r5 +void PB_ACK_SET_PB_STRIPS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3ad0: 6d03 mov r4, r0 + 3ad2: 6d87 mov r6, r1 + 3ad4: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %d",__func__,para_len); + 3ad6: 1233 lrw r1, 0x5c0f // 3c20 + 3ad8: 1253 lrw r2, 0x5759 // 3c24 + 3ada: 3000 movi r0, 0 + 3adc: e3fffa66 bsr 0x2fa8 // 2fa8 + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 0x4B){ + 3ae0: 334b movi r3, 75 + 3ae2: 64d6 cmpne r5, r3 + 3ae4: 0899 bt 0x3c16 // 3c16 + + if(PowerBUS_GetCommState() == 0x00){ + 3ae6: e3fffcad bsr 0x3440 // 3440 + 3aea: 3840 cmpnei r0, 0 + 3aec: 0892 bt 0x3c10 // 3c10 + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + 3aee: 320b movi r2, 11 + 3af0: 6090 addu r2, r4 + 3af2: 8261 ld.b r3, (r2, 0x1) + 3af4: 8220 ld.b r1, (r2, 0x0) + 3af6: 4368 lsli r3, r3, 8 + 3af8: 6cc4 or r3, r1 + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + 3afa: 844a ld.b r2, (r4, 0xa) + ch_mask <<= 8; + 3afc: 4368 lsli r3, r3, 8 + ch_mask |= para[PB_FMT_PARA + 3]; + 3afe: 6cc8 or r3, r2 + ch_mask <<= 8; + 3b00: 4368 lsli r3, r3, 8 + ch_mask |= para[PB_FMT_PARA + 2]; + 3b02: 8449 ld.b r2, (r4, 0x9) + 3b04: 6cc8 or r3, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + 3b06: 6c8f mov r2, r3 + 3b08: 1228 lrw r1, 0x5c15 // 3c28 + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + 3b0a: 84a8 ld.b r5, (r4, 0x8) + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + 3b0c: b860 st.w r3, (r14, 0x0) + 3b0e: e3fffa4d bsr 0x2fa8 // 2fa8 + if(ch_mask != 0x00){ + 3b12: 9860 ld.w r3, (r14, 0x0) + 3b14: 3b40 cmpnei r3, 0 + 3b16: 0c31 bf 0x3b78 // 3b78 + //判断前32回路是否有控制状态 + + //Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + + memset(pack_buff, 0, sizeof(pack_buff)); + 3b18: 323c movi r2, 60 + 3b1a: 3100 movi r1, 0 + 3b1c: 1801 addi r0, r14, 4 + 3b1e: e3ffe86b bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + 3b22: 4561 lsli r3, r5, 1 + 3b24: dc6e0004 st.b r3, (r14, 0x4) + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + 3b28: 8469 ld.b r3, (r4, 0x9) + 3b2a: dc6e0005 st.b r3, (r14, 0x5) + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + 3b2e: 846a ld.b r3, (r4, 0xa) + 3b30: dc6e0006 st.b r3, (r14, 0x6) + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + 3b34: 846b ld.b r3, (r4, 0xb) + 3b36: dc6e0007 st.b r3, (r14, 0x7) + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + 3b3a: 846c ld.b r3, (r4, 0xc) + 3b3c: dc6e0008 st.b r3, (r14, 0x8) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3b40: 8471 ld.b r3, (r4, 0x11) + 3b42: dc6e0009 st.b r3, (r14, 0x9) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //渐变时间 + 3b46: 8472 ld.b r3, (r4, 0x12) + 3b48: dc6e000a st.b r3, (r14, 0xa) + + memcpy(&pack_buff[pack_len], ¶[PB_FMT_PARA + 12], 32); //拷贝32回路的控制亮度 + 3b4c: 3007 movi r0, 7 + 3b4e: 1b01 addi r3, r14, 4 + 3b50: 3113 movi r1, 19 + 3b52: 600c addu r0, r3 + 3b54: 3220 movi r2, 32 + 3b56: 6050 addu r1, r4 + 3b58: e3ffe892 bsr 0xc7c // c7c <__memcpy_fast> + pack_len+=32; + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3b5c: 3327 movi r3, 39 + 3b5e: 1a01 addi r2, r14, 4 + 3b60: 1133 lrw r1, 0x5c25 // 3c2c + 3b62: 3000 movi r0, 0 + 3b64: e3fffa28 bsr 0x2fb4 // 2fb4 + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_BRIGHTNESS,pack_buff,pack_len); + 3b68: 8407 ld.b r0, (r4, 0x7) + 3b6a: 2000 addi r0, 1 + 3b6c: 7400 zextb r0, r0 + 3b6e: 3327 movi r3, 39 + 3b70: 1a01 addi r2, r14, 4 + 3b72: 3114 movi r1, 20 + 3b74: e3fffc0e bsr 0x3390 // 3390 + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + 3b78: 320f movi r2, 15 + 3b7a: 6090 addu r2, r4 + 3b7c: 8261 ld.b r3, (r2, 0x1) + 3b7e: 8220 ld.b r1, (r2, 0x0) + 3b80: 4368 lsli r3, r3, 8 + 3b82: 6cc4 or r3, r1 + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + 3b84: 844e ld.b r2, (r4, 0xe) + ch_mask <<= 8; + 3b86: 4368 lsli r3, r3, 8 + ch_mask |= para[PB_FMT_PARA + 7]; + 3b88: 6cc8 or r3, r2 + ch_mask <<= 8; + 3b8a: 4368 lsli r3, r3, 8 + ch_mask |= para[PB_FMT_PARA + 6]; + 3b8c: 844d ld.b r2, (r4, 0xd) + 3b8e: 6cc8 or r3, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + 3b90: 6c8f mov r2, r3 + 3b92: 1126 lrw r1, 0x5c15 // 3c28 + 3b94: 3000 movi r0, 0 + 3b96: b860 st.w r3, (r14, 0x0) + 3b98: e3fffa08 bsr 0x2fa8 // 2fa8 + if(ch_mask != 0x00){ + 3b9c: 9860 ld.w r3, (r14, 0x0) + 3b9e: 3b40 cmpnei r3, 0 + 3ba0: 0c32 bf 0x3c04 // 3c04 + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + 3ba2: 323c movi r2, 60 + 3ba4: 3100 movi r1, 0 + 3ba6: 1801 addi r0, r14, 4 + 3ba8: e3ffe826 bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + //Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + 3bac: 846d ld.b r3, (r4, 0xd) + 3bae: dc6e0005 st.b r3, (r14, 0x5) + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + 3bb2: 846e ld.b r3, (r4, 0xe) + 3bb4: dc6e0006 st.b r3, (r14, 0x6) + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + 3bb8: 846f ld.b r3, (r4, 0xf) + 3bba: dc6e0007 st.b r3, (r14, 0x7) + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + 3bbe: 8470 ld.b r3, (r4, 0x10) + 3bc0: dc6e0008 st.b r3, (r14, 0x8) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3bc4: 8471 ld.b r3, (r4, 0x11) + 3bc6: dc6e0009 st.b r3, (r14, 0x9) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //渐变时间 + 3bca: 8472 ld.b r3, (r4, 0x12) + 3bcc: dc6e000a st.b r3, (r14, 0xa) + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3bd0: 45a1 lsli r5, r5, 1 + + memcpy(&pack_buff[pack_len], ¶[PB_FMT_PARA + 44], 32); //拷贝32回路的控制亮度 + 3bd2: 1b01 addi r3, r14, 4 + 3bd4: 3007 movi r0, 7 + 3bd6: 3133 movi r1, 51 + 3bd8: 600c addu r0, r3 + 3bda: 6050 addu r1, r4 + 3bdc: 3220 movi r2, 32 + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3bde: 2500 addi r5, 1 + 3be0: dcae0004 st.b r5, (r14, 0x4) + memcpy(&pack_buff[pack_len], ¶[PB_FMT_PARA + 44], 32); //拷贝32回路的控制亮度 + 3be4: e3ffe84c bsr 0xc7c // c7c <__memcpy_fast> + pack_len+=32; + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3be8: 3327 movi r3, 39 + 3bea: 1a01 addi r2, r14, 4 + 3bec: 1030 lrw r1, 0x5c25 // 3c2c + 3bee: 3000 movi r0, 0 + 3bf0: e3fff9e2 bsr 0x2fb4 // 2fb4 + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_BRIGHTNESS,pack_buff,pack_len); + 3bf4: 8407 ld.b r0, (r4, 0x7) + 3bf6: 2000 addi r0, 1 + 3bf8: 7400 zextb r0, r0 + 3bfa: 3327 movi r3, 39 + 3bfc: 1a01 addi r2, r14, 4 + 3bfe: 3114 movi r1, 20 + 3c00: e3fffbc8 bsr 0x3390 // 3390 + } + + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + 3c04: 3301 movi r3, 1 + 3c06: af60 st.h r3, (r7, 0x0) + + ackPara[0] = PB_CMD_Reply_Succ; + 3c08: 3300 movi r3, 0 + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + 3c0a: a660 st.b r3, (r6, 0x0) + } + +} + 3c0c: 1410 addi r14, r14, 64 + 3c0e: 1494 pop r4-r7, r15 + *ackLen = 1; + 3c10: 3301 movi r3, 1 + 3c12: af60 st.h r3, (r7, 0x0) + 3c14: 07fb br 0x3c0a // 3c0a + *ackLen = 1; + 3c16: 3301 movi r3, 1 + 3c18: af60 st.h r3, (r7, 0x0) + ackPara[0] = PB_CMD_Reply_ParaError; + 3c1a: 3302 movi r3, 2 + 3c1c: 07f7 br 0x3c0a // 3c0a + 3c1e: 0000 bkpt + 3c20: 00005c0f .long 0x00005c0f + 3c24: 00005759 .long 0x00005759 + 3c28: 00005c15 .long 0x00005c15 + 3c2c: 00005c25 .long 0x00005c25 + +Disassembly of section .text.PB_ACK_SET_PB_STRIPS_ADJUST: + +00003c30 : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3c30: 14d4 push r4-r7, r15 + 3c32: 1433 subi r14, r14, 76 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3c34: 80e4 ld.b r7, (r0, 0x4) +void PB_ACK_SET_PB_STRIPS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3c36: 6d03 mov r4, r0 + 3c38: 6d47 mov r5, r1 + 3c3a: 6d8b mov r6, r2 + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 3c3c: 122d lrw r1, 0x5a8e // 3d70 + 3c3e: 124e lrw r2, 0x5779 // 3d74 + 3c40: 3000 movi r0, 0 + 3c42: e3fff9b3 bsr 0x2fa8 // 2fa8 + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 12){ + 3c46: 3f54 cmpnei r7, 20 + 3c48: 088f bt 0x3d66 // 3d66 + + if(PowerBUS_GetCommState() == 0x00){ + 3c4a: e3fffbfb bsr 0x3440 // 3440 + 3c4e: 3840 cmpnei r0, 0 + 3c50: 0888 bt 0x3d60 // 3d60 + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + 3c52: 8468 ld.b r3, (r4, 0x8) + 3c54: b860 st.w r3, (r14, 0x0) + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + 3c56: 330b movi r3, 11 + 3c58: 60d0 addu r3, r4 + 3c5a: 8341 ld.b r2, (r3, 0x1) + 3c5c: 8320 ld.b r1, (r3, 0x0) + 3c5e: 4248 lsli r2, r2, 8 + 3c60: 6c84 or r2, r1 + ch_mask <<= 8; + 3c62: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 3]; + 3c64: 84ea ld.b r7, (r4, 0xa) + ch_mask = para[PB_FMT_PARA + 5]; + 3c66: 846c ld.b r3, (r4, 0xc) + ch_mask |= para[PB_FMT_PARA + 3]; + 3c68: 6c9c or r2, r7 + ch_mask = para[PB_FMT_PARA + 5]; + 3c6a: b861 st.w r3, (r14, 0x4) + ch_mask <<= 8; + 3c6c: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 2]; + 3c6e: 8469 ld.b r3, (r4, 0x9) + 3c70: 6c8c or r2, r3 + if(ch_mask != 0x00){ + 3c72: 3a40 cmpnei r2, 0 + ch_mask |= para[PB_FMT_PARA + 4]; + 3c74: b822 st.w r1, (r14, 0x8) + if(ch_mask != 0x00){ + 3c76: 0c2f bf 0x3cd4 // 3cd4 + //判断前32回路是否有控制状态 + + memset(pack_buff, 0, sizeof(pack_buff)); + 3c78: 323c movi r2, 60 + 3c7a: 3100 movi r1, 0 + 3c7c: 1804 addi r0, r14, 16 + 3c7e: b863 st.w r3, (r14, 0xc) + 3c80: e3ffe7ba bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + 3c84: 9860 ld.w r3, (r14, 0x0) + 3c86: 4341 lsli r2, r3, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + 3c88: 9863 ld.w r3, (r14, 0xc) + 3c8a: dc6e0011 st.b r3, (r14, 0x11) + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + 3c8e: d86e0008 ld.b r3, (r14, 0x8) + 3c92: dc6e0013 st.b r3, (r14, 0x13) + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + 3c96: d86e0004 ld.b r3, (r14, 0x4) + 3c9a: dc6e0014 st.b r3, (r14, 0x14) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + 3c9e: 8471 ld.b r3, (r4, 0x11) + 3ca0: dc6e0015 st.b r3, (r14, 0x15) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //调节方向 + 3ca4: 8472 ld.b r3, (r4, 0x12) + 3ca6: dc6e0016 st.b r3, (r14, 0x16) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + 3caa: 8473 ld.b r3, (r4, 0x13) + pack_buff[pack_len++] = addr_field*2; //组地址 + 3cac: dc4e0010 st.b r2, (r14, 0x10) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + 3cb0: dc6e0017 st.b r3, (r14, 0x17) + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3cb4: 1a04 addi r2, r14, 16 + 3cb6: 3308 movi r3, 8 + 3cb8: 1130 lrw r1, 0x5c25 // 3d78 + 3cba: 3000 movi r0, 0 + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + 3cbc: dcee0012 st.b r7, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3cc0: e3fff97a bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_SWITCH,pack_buff,pack_len); + 3cc4: 8407 ld.b r0, (r4, 0x7) + 3cc6: 2000 addi r0, 1 + 3cc8: 7400 zextb r0, r0 + 3cca: 3308 movi r3, 8 + 3ccc: 1a04 addi r2, r14, 16 + 3cce: 3115 movi r1, 21 + 3cd0: e3fffb60 bsr 0x3390 // 3390 + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + 3cd4: 330f movi r3, 15 + 3cd6: 60d0 addu r3, r4 + 3cd8: 8341 ld.b r2, (r3, 0x1) + 3cda: 8320 ld.b r1, (r3, 0x0) + 3cdc: 4248 lsli r2, r2, 8 + 3cde: 6c84 or r2, r1 + ch_mask <<= 8; + 3ce0: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 7]; + 3ce2: 84ee ld.b r7, (r4, 0xe) + ch_mask = para[PB_FMT_PARA + 9]; + 3ce4: 8470 ld.b r3, (r4, 0x10) + ch_mask |= para[PB_FMT_PARA + 7]; + 3ce6: 6c9c or r2, r7 + ch_mask = para[PB_FMT_PARA + 9]; + 3ce8: b861 st.w r3, (r14, 0x4) + ch_mask <<= 8; + 3cea: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 6]; + 3cec: 846d ld.b r3, (r4, 0xd) + 3cee: 6c8c or r2, r3 + if(ch_mask != 0x00){ + 3cf0: 3a40 cmpnei r2, 0 + ch_mask |= para[PB_FMT_PARA + 8]; + 3cf2: b822 st.w r1, (r14, 0x8) + if(ch_mask != 0x00){ + 3cf4: 0c30 bf 0x3d54 // 3d54 + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + 3cf6: 323c movi r2, 60 + 3cf8: 3100 movi r1, 0 + 3cfa: 1804 addi r0, r14, 16 + 3cfc: b863 st.w r3, (r14, 0xc) + 3cfe: e3ffe77b bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3d02: 9860 ld.w r3, (r14, 0x0) + 3d04: 4341 lsli r2, r3, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + 3d06: 9863 ld.w r3, (r14, 0xc) + 3d08: dc6e0011 st.b r3, (r14, 0x11) + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + 3d0c: d86e0008 ld.b r3, (r14, 0x8) + 3d10: dc6e0013 st.b r3, (r14, 0x13) + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + 3d14: d86e0004 ld.b r3, (r14, 0x4) + 3d18: dc6e0014 st.b r3, (r14, 0x14) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + 3d1c: 8471 ld.b r3, (r4, 0x11) + 3d1e: dc6e0015 st.b r3, (r14, 0x15) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //调节方向 + 3d22: 8472 ld.b r3, (r4, 0x12) + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3d24: 2200 addi r2, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //调节方向 + 3d26: dc6e0016 st.b r3, (r14, 0x16) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + 3d2a: 8473 ld.b r3, (r4, 0x13) + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3d2c: dc4e0010 st.b r2, (r14, 0x10) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + 3d30: dc6e0017 st.b r3, (r14, 0x17) + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3d34: 1a04 addi r2, r14, 16 + 3d36: 3308 movi r3, 8 + 3d38: 1030 lrw r1, 0x5c25 // 3d78 + 3d3a: 3000 movi r0, 0 + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + 3d3c: dcee0012 st.b r7, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3d40: e3fff93a bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_SWITCH,pack_buff,pack_len); + 3d44: 8407 ld.b r0, (r4, 0x7) + 3d46: 2000 addi r0, 1 + 3d48: 7400 zextb r0, r0 + 3d4a: 3308 movi r3, 8 + 3d4c: 1a04 addi r2, r14, 16 + 3d4e: 3115 movi r1, 21 + 3d50: e3fffb20 bsr 0x3390 // 3390 + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + 3d54: 3301 movi r3, 1 + 3d56: ae60 st.h r3, (r6, 0x0) + + ackPara[0] = PB_CMD_Reply_Succ; + 3d58: 3300 movi r3, 0 + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + 3d5a: a560 st.b r3, (r5, 0x0) + } + +} + 3d5c: 1413 addi r14, r14, 76 + 3d5e: 1494 pop r4-r7, r15 + *ackLen = 1; + 3d60: 3301 movi r3, 1 + 3d62: ae60 st.h r3, (r6, 0x0) + 3d64: 07fb br 0x3d5a // 3d5a + *ackLen = 1; + 3d66: 3301 movi r3, 1 + 3d68: ae60 st.h r3, (r6, 0x0) + ackPara[0] = PB_CMD_Reply_ParaError; + 3d6a: 3302 movi r3, 2 + 3d6c: 07f7 br 0x3d5a // 3d5a + 3d6e: 0000 bkpt + 3d70: 00005a8e .long 0x00005a8e + 3d74: 00005779 .long 0x00005779 + 3d78: 00005c25 .long 0x00005c25 + +Disassembly of section .text.PB_ACK_SET_PB_STRIPS_SWITCH: + +00003d7c : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3d7c: 14d4 push r4-r7, r15 + 3d7e: 1432 subi r14, r14, 72 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3d80: 80a4 ld.b r5, (r0, 0x4) + 3d82: 2d07 subi r5, 8 + 3d84: 7554 zextb r5, r5 +void PB_ACK_SET_PB_STRIPS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3d86: b821 st.w r1, (r14, 0x4) + 3d88: b842 st.w r2, (r14, 0x8) + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0,off_mask = 0,on_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %02x",__func__,para_len); + 3d8a: 6cd7 mov r3, r5 +void PB_ACK_SET_PB_STRIPS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3d8c: 6d03 mov r4, r0 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %02x",__func__,para_len); + 3d8e: 0354 lrw r2, 0x5795 // 3fb8 + 3d90: 0334 lrw r1, 0x5c2f // 3fbc + 3d92: 3000 movi r0, 0 + 3d94: e3fff90a bsr 0x2fa8 // 2fa8 + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 0x4A){ + 3d98: 334a movi r3, 74 + 3d9a: 64d6 cmpne r5, r3 + 3d9c: 0908 bt 0x3fac // 3fac + if(PowerBUS_GetCommState() == 0x00){ + 3d9e: e3fffb51 bsr 0x3440 // 3440 + 3da2: 3840 cmpnei r0, 0 + 3da4: 08ff bt 0x3fa2 // 3fa2 + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + 3da6: 8468 ld.b r3, (r4, 0x8) + 3da8: b860 st.w r3, (r14, 0x0) + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + 3daa: 330b movi r3, 11 + 3dac: 60d0 addu r3, r4 + 3dae: 83e1 ld.b r7, (r3, 0x1) + 3db0: 8340 ld.b r2, (r3, 0x0) + 3db2: 47e8 lsli r7, r7, 8 + 3db4: 6dc8 or r7, r2 + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + 3db6: 846a ld.b r3, (r4, 0xa) + ch_mask <<= 8; + 3db8: 47e8 lsli r7, r7, 8 + ch_mask |= para[PB_FMT_PARA + 3]; + 3dba: 6dcc or r7, r3 + ch_mask <<= 8; + 3dbc: 47e8 lsli r7, r7, 8 + ch_mask |= para[PB_FMT_PARA + 2]; + 3dbe: 8469 ld.b r3, (r4, 0x9) + 3dc0: 6dcc or r7, r3 + + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + 3dc2: 6c9f mov r2, r7 + 3dc4: 133f lrw r1, 0x5c15 // 3fc0 + 3dc6: e3fff8f1 bsr 0x2fa8 // 2fa8 + if(ch_mask != 0x00){ + 3dca: 3f40 cmpnei r7, 0 + 3dcc: 0c66 bf 0x3e98 // 3e98 + 3dce: 3212 movi r2, 18 + 3dd0: 6090 addu r2, r4 + 3dd2: 3300 movi r3, 0 + 3dd4: 3500 movi r5, 0 + 3dd6: 3600 movi r6, 0 + //判断前32回路是否有控制状态 + + for(U8_T ch = 0;ch<32;ch++){ + if( (ch_mask & (0x01< + //有控制状态 - 检查控制 + if(para[PB_FMT_PARA + 11 + ch] == 0x01){ + 3de4: 8200 ld.b r0, (r2, 0x0) + 3de6: 3841 cmpnei r0, 1 + 3de8: 08d5 bt 0x3f92 // 3f92 + + on_mask |= 0x01 << ch; + 3dea: 6d84 or r6, r1 + 3dec: 2300 addi r3, 1 + for(U8_T ch = 0;ch<32;ch++){ + 3dee: 3120 movi r1, 32 + 3df0: 644e cmpne r3, r1 + 3df2: 2200 addi r2, 1 + 3df4: 0bf2 bt 0x3dd8 // 3dd8 + off_mask |= 0x01 << ch; + } + } + } + + if(on_mask != 0x00){ + 3df6: 3e40 cmpnei r6, 0 + 3df8: 0c29 bf 0x3e4a // 3e4a + memset(pack_buff, 0, sizeof(pack_buff)); + 3dfa: 323c movi r2, 60 + 3dfc: 3100 movi r1, 0 + 3dfe: 1803 addi r0, r14, 12 + 3e00: e3ffe6fa bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + 3e04: 9860 ld.w r3, (r14, 0x0) + 3e06: 4361 lsli r3, r3, 1 + 3e08: dc6e000c st.b r3, (r14, 0xc) + + pack_buff[pack_len++] = (on_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>8) & 0xFF); //回路Mask + 3e0c: 4e68 lsri r3, r6, 8 + 3e0e: dc6e000e st.b r3, (r14, 0xe) + pack_buff[pack_len++] = ((on_mask>>16) & 0xFF); //回路Mask + 3e12: 4e70 lsri r3, r6, 16 + 3e14: dc6e000f st.b r3, (r14, 0xf) + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3e18: 8471 ld.b r3, (r4, 0x11) + 3e1a: dc6e0011 st.b r3, (r14, 0x11) + + pack_buff[pack_len++] = 0x01; //开 + 3e1e: 3301 movi r3, 1 + pack_buff[pack_len++] = (on_mask & 0xFF); //回路Mask + 3e20: dcce000d st.b r6, (r14, 0xd) + pack_buff[pack_len++] = 0x01; //开 + 3e24: dc6e0012 st.b r3, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3e28: 1a03 addi r2, r14, 12 + 3e2a: 3307 movi r3, 7 + 3e2c: 1326 lrw r1, 0x5c25 // 3fc4 + 3e2e: 3000 movi r0, 0 + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + 3e30: 4ed8 lsri r6, r6, 24 + 3e32: dcce0010 st.b r6, (r14, 0x10) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3e36: e3fff8bf bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + 3e3a: 8407 ld.b r0, (r4, 0x7) + 3e3c: 2000 addi r0, 1 + 3e3e: 7400 zextb r0, r0 + 3e40: 3307 movi r3, 7 + 3e42: 1a03 addi r2, r14, 12 + 3e44: 3116 movi r1, 22 + 3e46: e3fffaa5 bsr 0x3390 // 3390 + } + + if(off_mask != 0x00){ + 3e4a: 3d40 cmpnei r5, 0 + 3e4c: 0c26 bf 0x3e98 // 3e98 + memset(pack_buff, 0, sizeof(pack_buff)); + 3e4e: 323c movi r2, 60 + 3e50: 3100 movi r1, 0 + 3e52: 1803 addi r0, r14, 12 + 3e54: e3ffe6d0 bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + 3e58: 9860 ld.w r3, (r14, 0x0) + 3e5a: 4361 lsli r3, r3, 1 + 3e5c: dc6e000c st.b r3, (r14, 0xc) + + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>8) & 0xFF); //回路Mask + 3e60: 4d68 lsri r3, r5, 8 + 3e62: dc6e000e st.b r3, (r14, 0xe) + pack_buff[pack_len++] = ((off_mask>>16) & 0xFF); //回路Mask + 3e66: 4d70 lsri r3, r5, 16 + 3e68: dc6e000f st.b r3, (r14, 0xf) + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3e6c: 8471 ld.b r3, (r4, 0x11) + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + 3e6e: dcae000d st.b r5, (r14, 0xd) + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3e72: dc6e0011 st.b r3, (r14, 0x11) + + pack_buff[pack_len++] = 0x00; //关 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3e76: 1a03 addi r2, r14, 12 + 3e78: 3307 movi r3, 7 + 3e7a: 1233 lrw r1, 0x5c25 // 3fc4 + 3e7c: 3000 movi r0, 0 + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + 3e7e: 4db8 lsri r5, r5, 24 + 3e80: dcae0010 st.b r5, (r14, 0x10) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3e84: e3fff898 bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + 3e88: 8407 ld.b r0, (r4, 0x7) + 3e8a: 2000 addi r0, 1 + 3e8c: 7400 zextb r0, r0 + 3e8e: 3307 movi r3, 7 + 3e90: 1a03 addi r2, r14, 12 + 3e92: 3116 movi r1, 22 + 3e94: e3fffa7e bsr 0x3390 // 3390 + on_mask = 0x00000000; + off_mask = 0x00000000; + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + 3e98: 330f movi r3, 15 + 3e9a: 60d0 addu r3, r4 + 3e9c: 8341 ld.b r2, (r3, 0x1) + 3e9e: 8320 ld.b r1, (r3, 0x0) + 3ea0: 4248 lsli r2, r2, 8 + 3ea2: 6c84 or r2, r1 + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + 3ea4: 846e ld.b r3, (r4, 0xe) + ch_mask <<= 8; + 3ea6: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 7]; + 3ea8: 6c8c or r2, r3 + ch_mask <<= 8; + 3eaa: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 6]; + 3eac: 846d ld.b r3, (r4, 0xd) + 3eae: 6c8c or r2, r3 + if(ch_mask != 0x00){ + 3eb0: 3a40 cmpnei r2, 0 + 3eb2: 0c68 bf 0x3f82 // 3f82 + 3eb4: 3132 movi r1, 50 + 3eb6: 6050 addu r1, r4 + 3eb8: 3300 movi r3, 0 + 3eba: 3500 movi r5, 0 + 3ebc: 3600 movi r6, 0 + //判断后32回路是否有控制状态 + for(U8_T ch = 0;ch<32;ch++){ + if( (ch_mask & (0x01< + //有控制状态 - 检查控制 + if(para[PB_FMT_PARA + 43 + ch] == 0x01){ + 3eca: 81e0 ld.b r7, (r1, 0x0) + 3ecc: 3f41 cmpnei r7, 1 + 3ece: 0866 bt 0x3f9a // 3f9a + + on_mask |= 0x01 << ch; + 3ed0: 6d80 or r6, r0 + 3ed2: 2300 addi r3, 1 + for(U8_T ch = 0;ch<32;ch++){ + 3ed4: 3020 movi r0, 32 + 3ed6: 640e cmpne r3, r0 + 3ed8: 2100 addi r1, 1 + 3eda: 0bf2 bt 0x3ebe // 3ebe + off_mask |= 0x01 << ch; + } + } + } + + if(on_mask != 0x00){ + 3edc: 3e40 cmpnei r6, 0 + 3ede: 0c2a bf 0x3f32 // 3f32 + memset(pack_buff, 0, sizeof(pack_buff)); + 3ee0: 323c movi r2, 60 + 3ee2: 3100 movi r1, 0 + 3ee4: 1803 addi r0, r14, 12 + 3ee6: e3ffe687 bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3eea: 9860 ld.w r3, (r14, 0x0) + 3eec: 4361 lsli r3, r3, 1 + 3eee: 2300 addi r3, 1 + 3ef0: dc6e000c st.b r3, (r14, 0xc) + + pack_buff[pack_len++] = (on_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>8) & 0xFF); //回路Mask + 3ef4: 4e68 lsri r3, r6, 8 + 3ef6: dc6e000e st.b r3, (r14, 0xe) + pack_buff[pack_len++] = ((on_mask>>16) & 0xFF); //回路Mask + 3efa: 4e70 lsri r3, r6, 16 + 3efc: dc6e000f st.b r3, (r14, 0xf) + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3f00: 8471 ld.b r3, (r4, 0x11) + 3f02: dc6e0011 st.b r3, (r14, 0x11) + + pack_buff[pack_len++] = 0x01; //开 + 3f06: 3301 movi r3, 1 + pack_buff[pack_len++] = (on_mask & 0xFF); //回路Mask + 3f08: dcce000d st.b r6, (r14, 0xd) + pack_buff[pack_len++] = 0x01; //开 + 3f0c: dc6e0012 st.b r3, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3f10: 1a03 addi r2, r14, 12 + 3f12: 3307 movi r3, 7 + 3f14: 112c lrw r1, 0x5c25 // 3fc4 + 3f16: 3000 movi r0, 0 + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + 3f18: 4ed8 lsri r6, r6, 24 + 3f1a: dcce0010 st.b r6, (r14, 0x10) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3f1e: e3fff84b bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + 3f22: 8407 ld.b r0, (r4, 0x7) + 3f24: 2000 addi r0, 1 + 3f26: 7400 zextb r0, r0 + 3f28: 3307 movi r3, 7 + 3f2a: 1a03 addi r2, r14, 12 + 3f2c: 3116 movi r1, 22 + 3f2e: e3fffa31 bsr 0x3390 // 3390 + } + + if(off_mask != 0x00){ + 3f32: 3d40 cmpnei r5, 0 + 3f34: 0c27 bf 0x3f82 // 3f82 + memset(pack_buff, 0, sizeof(pack_buff)); + 3f36: 323c movi r2, 60 + 3f38: 3100 movi r1, 0 + 3f3a: 1803 addi r0, r14, 12 + 3f3c: e3ffe65c bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 3f40: 9860 ld.w r3, (r14, 0x0) + 3f42: 4361 lsli r3, r3, 1 + 3f44: 2300 addi r3, 1 + 3f46: dc6e000c st.b r3, (r14, 0xc) + + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>8) & 0xFF); //回路Mask + 3f4a: 4d68 lsri r3, r5, 8 + 3f4c: dc6e000e st.b r3, (r14, 0xe) + pack_buff[pack_len++] = ((off_mask>>16) & 0xFF); //回路Mask + 3f50: 4d70 lsri r3, r5, 16 + 3f52: dc6e000f st.b r3, (r14, 0xf) + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3f56: 8471 ld.b r3, (r4, 0x11) + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + 3f58: dcae000d st.b r5, (r14, 0xd) + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + 3f5c: dc6e0011 st.b r3, (r14, 0x11) + + pack_buff[pack_len++] = 0x00; //关 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3f60: 1a03 addi r2, r14, 12 + 3f62: 3307 movi r3, 7 + 3f64: 1038 lrw r1, 0x5c25 // 3fc4 + 3f66: 3000 movi r0, 0 + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + 3f68: 4db8 lsri r5, r5, 24 + 3f6a: dcae0010 st.b r5, (r14, 0x10) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 3f6e: e3fff823 bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + 3f72: 8407 ld.b r0, (r4, 0x7) + 3f74: 2000 addi r0, 1 + 3f76: 7400 zextb r0, r0 + 3f78: 3307 movi r3, 7 + 3f7a: 1a03 addi r2, r14, 12 + 3f7c: 3116 movi r1, 22 + 3f7e: e3fffa09 bsr 0x3390 // 3390 + } + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + 3f82: 9862 ld.w r3, (r14, 0x8) + 3f84: 3201 movi r2, 1 + 3f86: ab40 st.h r2, (r3, 0x0) + + ackPara[0] = PB_CMD_Reply_Succ; + 3f88: 9861 ld.w r3, (r14, 0x4) + 3f8a: 3200 movi r2, 0 + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + 3f8c: a340 st.b r2, (r3, 0x0) + } +} + 3f8e: 1412 addi r14, r14, 72 + 3f90: 1494 pop r4-r7, r15 + }else if(para[PB_FMT_PARA + 11 + ch] == 0x02){ + 3f92: 3842 cmpnei r0, 2 + 3f94: 0b2c bt 0x3dec // 3dec + off_mask |= 0x01 << ch; + 3f96: 6d44 or r5, r1 + 3f98: 072a br 0x3dec // 3dec + }else if(para[PB_FMT_PARA + 43 + ch] == 0x02){ + 3f9a: 3f42 cmpnei r7, 2 + 3f9c: 0b9b bt 0x3ed2 // 3ed2 + off_mask |= 0x01 << ch; + 3f9e: 6d40 or r5, r0 + 3fa0: 0799 br 0x3ed2 // 3ed2 + *ackLen = 1; + 3fa2: 9862 ld.w r3, (r14, 0x8) + 3fa4: 3201 movi r2, 1 + 3fa6: ab40 st.h r2, (r3, 0x0) + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 3fa8: 9861 ld.w r3, (r14, 0x4) + 3faa: 07f1 br 0x3f8c // 3f8c + *ackLen = 1; + 3fac: 9862 ld.w r3, (r14, 0x8) + 3fae: 3201 movi r2, 1 + 3fb0: ab40 st.h r2, (r3, 0x0) + ackPara[0] = PB_CMD_Reply_ParaError; + 3fb2: 9861 ld.w r3, (r14, 0x4) + 3fb4: 3202 movi r2, 2 + 3fb6: 07eb br 0x3f8c // 3f8c + 3fb8: 00005795 .long 0x00005795 + 3fbc: 00005c2f .long 0x00005c2f + 3fc0: 00005c15 .long 0x00005c15 + 3fc4: 00005c25 .long 0x00005c25 + +Disassembly of section .text.PB_ACK_SET_PB_STRIP_SWITCH: + +00003fc8 : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3fc8: 14d4 push r4-r7, r15 + 3fca: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3fcc: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 3fce: 104e lrw r2, 0x57b1 // 4004 +void PB_ACK_SET_PB_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 3fd0: 6d43 mov r5, r0 + 3fd2: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 3fd4: 3000 movi r0, 0 + 3fd6: 102d lrw r1, 0x5a8e // 4008 + 3fd8: e3fff7e8 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 3fdc: e3fffa32 bsr 0x3440 // 3440 + 3fe0: 3840 cmpnei r0, 0 + *ackLen = 1; + 3fe2: 3301 movi r3, 1 + 3fe4: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 3fe6: 080d bt 0x4000 // 4000 + + ackPara[0] = PB_CMD_Reply_Succ; + 3fe8: 3300 movi r3, 0 + 3fea: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3fec: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 3fee: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 3ff0: 2000 addi r0, 1 + 3ff2: 74d0 zextb r3, r4 + 3ff4: 5d5e addi r2, r5, 8 + 3ff6: 7400 zextb r0, r0 + 3ff8: 3112 movi r1, 18 + 3ffa: e3fff9cb bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 3ffe: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4000: a660 st.b r3, (r6, 0x0) +} + 4002: 07fe br 0x3ffe // 3ffe + 4004: 000057b1 .long 0x000057b1 + 4008: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_STRIP_BRIGHTNESS: + +0000400c : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIP_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 400c: 14d4 push r4-r7, r15 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 400e: 8084 ld.b r4, (r0, 0x4) +void PB_ACK_SET_PB_STRIP_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4010: 6d43 mov r5, r0 + 4012: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4014: 3000 movi r0, 0 + 4016: 102c lrw r1, 0x5a8e // 4044 +void PB_ACK_SET_PB_STRIP_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4018: 6dcb mov r7, r2 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 401a: 104c lrw r2, 0x57cc // 4048 + 401c: e3fff7c6 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4020: e3fffa10 bsr 0x3440 // 3440 + 4024: 3840 cmpnei r0, 0 + 4026: 080e bt 0x4042 // 4042 + *ackLen = 1; + 4028: 3301 movi r3, 1 + 402a: af60 st.h r3, (r7, 0x0) + + ackPara[0] = PB_CMD_Reply_Succ; + 402c: 3300 movi r3, 0 + 402e: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 4030: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4032: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + 4034: 2000 addi r0, 1 + 4036: 74d0 zextb r3, r4 + 4038: 5d5e addi r2, r5, 8 + 403a: 7400 zextb r0, r0 + 403c: 3111 movi r1, 17 + 403e: e3fff9a9 bsr 0x3390 // 3390 + }else{ + + } + +} + 4042: 1494 pop r4-r7, r15 + 4044: 00005a8e .long 0x00005a8e + 4048: 000057cc .long 0x000057cc + +Disassembly of section .text.PB_ACK_SET_PB_STRIP_Adjust: + +0000404c : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_Adjust + * @brief BLV PB控制协议 - 设定PB总线 LS 递增、递减 - 指定回路控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 404c: 14d4 push r4-r7, r15 + 404e: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4050: 8084 ld.b r4, (r0, 0x4) + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4052: 104e lrw r2, 0x57eb // 4088 +void PB_ACK_SET_PB_STRIP_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4054: 6d43 mov r5, r0 + 4056: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4058: 3000 movi r0, 0 + 405a: 102d lrw r1, 0x5a8e // 408c + 405c: e3fff7a6 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4060: e3fff9f0 bsr 0x3440 // 3440 + 4064: 3840 cmpnei r0, 0 + *ackLen = 1; + 4066: 3301 movi r3, 1 + 4068: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 406a: 080d bt 0x4084 // 4084 + + ackPara[0] = PB_CMD_Reply_Succ; + 406c: 3300 movi r3, 0 + 406e: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 4070: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4072: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 4074: 2000 addi r0, 1 + 4076: 74d0 zextb r3, r4 + 4078: 5d5e addi r2, r5, 8 + 407a: 7400 zextb r0, r0 + 407c: 3113 movi r1, 19 + 407e: e3fff989 bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 4082: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4084: a660 st.b r3, (r6, 0x0) +} + 4086: 07fe br 0x4082 // 4082 + 4088: 000057eb .long 0x000057eb + 408c: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST: + +00004090 : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LS 相对亮度调节 - 组地址控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4090: 14d4 push r4-r7, r15 + 4092: 1433 subi r14, r14, 76 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4094: 80e4 ld.b r7, (r0, 0x4) +void PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4096: 6d03 mov r4, r0 + 4098: 6d47 mov r5, r1 + 409a: 6d8b mov r6, r2 + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 409c: 122d lrw r1, 0x5a8e // 41d0 + 409e: 124e lrw r2, 0x5806 // 41d4 + 40a0: 3000 movi r0, 0 + 40a2: e3fff783 bsr 0x2fa8 // 2fa8 + + /*2024-07-02 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 12){ + 40a6: 3f54 cmpnei r7, 20 + 40a8: 088f bt 0x41c6 // 41c6 + + if(PowerBUS_GetCommState() == 0x00){ + 40aa: e3fff9cb bsr 0x3440 // 3440 + 40ae: 3840 cmpnei r0, 0 + 40b0: 0888 bt 0x41c0 // 41c0 + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + 40b2: 8468 ld.b r3, (r4, 0x8) + 40b4: b860 st.w r3, (r14, 0x0) + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + 40b6: 330b movi r3, 11 + 40b8: 60d0 addu r3, r4 + 40ba: 8341 ld.b r2, (r3, 0x1) + 40bc: 8320 ld.b r1, (r3, 0x0) + 40be: 4248 lsli r2, r2, 8 + 40c0: 6c84 or r2, r1 + ch_mask <<= 8; + 40c2: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 3]; + 40c4: 84ea ld.b r7, (r4, 0xa) + ch_mask = para[PB_FMT_PARA + 5]; + 40c6: 846c ld.b r3, (r4, 0xc) + ch_mask |= para[PB_FMT_PARA + 3]; + 40c8: 6c9c or r2, r7 + ch_mask = para[PB_FMT_PARA + 5]; + 40ca: b861 st.w r3, (r14, 0x4) + ch_mask <<= 8; + 40cc: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 2]; + 40ce: 8469 ld.b r3, (r4, 0x9) + 40d0: 6c8c or r2, r3 + if(ch_mask != 0x00){ + 40d2: 3a40 cmpnei r2, 0 + ch_mask |= para[PB_FMT_PARA + 4]; + 40d4: b822 st.w r1, (r14, 0x8) + if(ch_mask != 0x00){ + 40d6: 0c2f bf 0x4134 // 4134 + //判断前32回路是否有控制状态 + + memset(pack_buff, 0, sizeof(pack_buff)); + 40d8: 323c movi r2, 60 + 40da: 3100 movi r1, 0 + 40dc: 1804 addi r0, r14, 16 + 40de: b863 st.w r3, (r14, 0xc) + 40e0: e3ffe58a bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + 40e4: 9860 ld.w r3, (r14, 0x0) + 40e6: 4341 lsli r2, r3, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + 40e8: 9863 ld.w r3, (r14, 0xc) + 40ea: dc6e0011 st.b r3, (r14, 0x11) + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + 40ee: d86e0008 ld.b r3, (r14, 0x8) + 40f2: dc6e0013 st.b r3, (r14, 0x13) + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + 40f6: d86e0004 ld.b r3, (r14, 0x4) + 40fa: dc6e0014 st.b r3, (r14, 0x14) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + 40fe: 8471 ld.b r3, (r4, 0x11) + 4100: dc6e0015 st.b r3, (r14, 0x15) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //相对调节亮度值 + 4104: 8472 ld.b r3, (r4, 0x12) + 4106: dc6e0016 st.b r3, (r14, 0x16) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + 410a: 8473 ld.b r3, (r4, 0x13) + pack_buff[pack_len++] = addr_field*2; //组地址 + 410c: dc4e0010 st.b r2, (r14, 0x10) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + 4110: dc6e0017 st.b r3, (r14, 0x17) + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 4114: 1a04 addi r2, r14, 16 + 4116: 3308 movi r3, 8 + 4118: 1130 lrw r1, 0x5c25 // 41d8 + 411a: 3000 movi r0, 0 + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + 411c: dcee0012 st.b r7, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 4120: e3fff74a bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_GROUP_ADJUST,pack_buff,pack_len); + 4124: 8407 ld.b r0, (r4, 0x7) + 4126: 2000 addi r0, 1 + 4128: 7400 zextb r0, r0 + 412a: 3308 movi r3, 8 + 412c: 1a04 addi r2, r14, 16 + 412e: 3118 movi r1, 24 + 4130: e3fff930 bsr 0x3390 // 3390 + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + 4134: 330f movi r3, 15 + 4136: 60d0 addu r3, r4 + 4138: 8341 ld.b r2, (r3, 0x1) + 413a: 8320 ld.b r1, (r3, 0x0) + 413c: 4248 lsli r2, r2, 8 + 413e: 6c84 or r2, r1 + ch_mask <<= 8; + 4140: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 7]; + 4142: 84ee ld.b r7, (r4, 0xe) + ch_mask = para[PB_FMT_PARA + 9]; + 4144: 8470 ld.b r3, (r4, 0x10) + ch_mask |= para[PB_FMT_PARA + 7]; + 4146: 6c9c or r2, r7 + ch_mask = para[PB_FMT_PARA + 9]; + 4148: b861 st.w r3, (r14, 0x4) + ch_mask <<= 8; + 414a: 4248 lsli r2, r2, 8 + ch_mask |= para[PB_FMT_PARA + 6]; + 414c: 846d ld.b r3, (r4, 0xd) + 414e: 6c8c or r2, r3 + if(ch_mask != 0x00){ + 4150: 3a40 cmpnei r2, 0 + ch_mask |= para[PB_FMT_PARA + 8]; + 4152: b822 st.w r1, (r14, 0x8) + if(ch_mask != 0x00){ + 4154: 0c30 bf 0x41b4 // 41b4 + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + 4156: 323c movi r2, 60 + 4158: 3100 movi r1, 0 + 415a: 1804 addi r0, r14, 16 + 415c: b863 st.w r3, (r14, 0xc) + 415e: e3ffe54b bsr 0xbf4 // bf4 <__memset_fast> + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 4162: 9860 ld.w r3, (r14, 0x0) + 4164: 4341 lsli r2, r3, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + 4166: 9863 ld.w r3, (r14, 0xc) + 4168: dc6e0011 st.b r3, (r14, 0x11) + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + 416c: d86e0008 ld.b r3, (r14, 0x8) + 4170: dc6e0013 st.b r3, (r14, 0x13) + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + 4174: d86e0004 ld.b r3, (r14, 0x4) + 4178: dc6e0014 st.b r3, (r14, 0x14) + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + 417c: 8471 ld.b r3, (r4, 0x11) + 417e: dc6e0015 st.b r3, (r14, 0x15) + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //相对调节亮度值 + 4182: 8472 ld.b r3, (r4, 0x12) + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 4184: 2200 addi r2, 1 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //相对调节亮度值 + 4186: dc6e0016 st.b r3, (r14, 0x16) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + 418a: 8473 ld.b r3, (r4, 0x13) + pack_buff[pack_len++] = addr_field*2+1; //组地址 + 418c: dc4e0010 st.b r2, (r14, 0x10) + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + 4190: dc6e0017 st.b r3, (r14, 0x17) + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 4194: 1a04 addi r2, r14, 16 + 4196: 3308 movi r3, 8 + 4198: 1030 lrw r1, 0x5c25 // 41d8 + 419a: 3000 movi r0, 0 + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + 419c: dcee0012 st.b r7, (r14, 0x12) + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + 41a0: e3fff70a bsr 0x2fb4 // 2fb4 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_GROUP_ADJUST,pack_buff,pack_len); + 41a4: 8407 ld.b r0, (r4, 0x7) + 41a6: 2000 addi r0, 1 + 41a8: 7400 zextb r0, r0 + 41aa: 3308 movi r3, 8 + 41ac: 1a04 addi r2, r14, 16 + 41ae: 3118 movi r1, 24 + 41b0: e3fff8f0 bsr 0x3390 // 3390 + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + 41b4: 3301 movi r3, 1 + 41b6: ae60 st.h r3, (r6, 0x0) + + ackPara[0] = PB_CMD_Reply_Succ; + 41b8: 3300 movi r3, 0 + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + 41ba: a560 st.b r3, (r5, 0x0) + } +} + 41bc: 1413 addi r14, r14, 76 + 41be: 1494 pop r4-r7, r15 + *ackLen = 1; + 41c0: 3301 movi r3, 1 + 41c2: ae60 st.h r3, (r6, 0x0) + 41c4: 07fb br 0x41ba // 41ba + *ackLen = 1; + 41c6: 3301 movi r3, 1 + 41c8: ae60 st.h r3, (r6, 0x0) + ackPara[0] = PB_CMD_Reply_ParaError; + 41ca: 3302 movi r3, 2 + 41cc: 07f7 br 0x41ba // 41ba + 41ce: 0000 bkpt + 41d0: 00005a8e .long 0x00005a8e + 41d4: 00005806 .long 0x00005806 + 41d8: 00005c25 .long 0x00005c25 + +Disassembly of section .text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST: + +000041dc : +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LS 相对亮度调节 - 指定回路控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 41dc: 14d4 push r4-r7, r15 + 41de: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 41e0: 8084 ld.b r4, (r0, 0x4) + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 41e2: 104e lrw r2, 0x5830 // 4218 +void PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 41e4: 6d43 mov r5, r0 + 41e6: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 41e8: 3000 movi r0, 0 + 41ea: 102d lrw r1, 0x5a8e // 421c + 41ec: e3fff6de bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 41f0: e3fff928 bsr 0x3440 // 3440 + 41f4: 3840 cmpnei r0, 0 + *ackLen = 1; + 41f6: 3301 movi r3, 1 + 41f8: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 41fa: 080d bt 0x4214 // 4214 + + ackPara[0] = PB_CMD_Reply_Succ; + 41fc: 3300 movi r3, 0 + 41fe: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 4200: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4202: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_ADJUST,¶[PB_FMT_PARA + 1],para_len); + 4204: 2000 addi r0, 1 + 4206: 74d0 zextb r3, r4 + 4208: 5d5e addi r2, r5, 8 + 420a: 7400 zextb r0, r0 + 420c: 3119 movi r1, 25 + 420e: e3fff8c1 bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + 4212: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4214: a660 st.b r3, (r6, 0x0) +} + 4216: 07fe br 0x4212 // 4212 + 4218: 00005830 .long 0x00005830 + 421c: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_ALLSTRIP_Switch: + +00004220 : +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLSTRIP_Switch + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_ALLSTRIP_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4220: 14d4 push r4-r7, r15 + 4222: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4224: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4226: 104e lrw r2, 0x5854 // 425c +void PB_ACK_SET_PB_ALLSTRIP_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4228: 6d43 mov r5, r0 + 422a: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 422c: 3000 movi r0, 0 + 422e: 102d lrw r1, 0x5a8e // 4260 + 4230: e3fff6bc bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4234: e3fff906 bsr 0x3440 // 3440 + 4238: 3840 cmpnei r0, 0 + *ackLen = 1; + 423a: 3301 movi r3, 1 + 423c: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 423e: 080d bt 0x4258 // 4258 + + ackPara[0] = PB_CMD_Reply_Succ; + 4240: 3300 movi r3, 0 + 4242: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLSTRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4244: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4246: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLSTRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4248: 2000 addi r0, 1 + 424a: 74d0 zextb r3, r4 + 424c: 5d5e addi r2, r5, 8 + 424e: 7400 zextb r0, r0 + 4250: 3117 movi r1, 23 + 4252: e3fff89f bsr 0x3390 // 3390 + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + 4256: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4258: a660 st.b r3, (r6, 0x0) +} + 425a: 07fe br 0x4256 // 4256 + 425c: 00005854 .long 0x00005854 + 4260: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_RELAYS_SWITCH: + +00004264 : +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAYS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAYS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4264: 14d4 push r4-r7, r15 + 4266: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4268: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 426a: 104e lrw r2, 0x5872 // 42a0 +void PB_ACK_SET_PB_RELAYS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 426c: 6d43 mov r5, r0 + 426e: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4270: 3000 movi r0, 0 + 4272: 102d lrw r1, 0x5a8e // 42a4 + 4274: e3fff69a bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4278: e3fff8e4 bsr 0x3440 // 3440 + 427c: 3840 cmpnei r0, 0 + *ackLen = 1; + 427e: 3301 movi r3, 1 + 4280: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 4282: 080d bt 0x429c // 429c + + ackPara[0] = PB_CMD_Reply_Succ; + 4284: 3300 movi r3, 0 + 4286: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAYS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4288: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 428a: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAYS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 428c: 2000 addi r0, 1 + 428e: 74d0 zextb r3, r4 + 4290: 5d5e addi r2, r5, 8 + 4292: 7400 zextb r0, r0 + 4294: 3121 movi r1, 33 + 4296: e3fff87d bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 429a: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 429c: a660 st.b r3, (r6, 0x0) +} + 429e: 07fe br 0x429a // 429a + 42a0: 00005872 .long 0x00005872 + 42a4: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_ALLRELAY_SWITCH: + +000042a8 : +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLRELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_ALLRELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 42a8: 14d4 push r4-r7, r15 + 42aa: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 42ac: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 42ae: 104e lrw r2, 0x588e // 42e4 +void PB_ACK_SET_PB_ALLRELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 42b0: 6d43 mov r5, r0 + 42b2: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 42b4: 3000 movi r0, 0 + 42b6: 102d lrw r1, 0x5a8e // 42e8 + 42b8: e3fff678 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 42bc: e3fff8c2 bsr 0x3440 // 3440 + 42c0: 3840 cmpnei r0, 0 + *ackLen = 1; + 42c2: 3301 movi r3, 1 + 42c4: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 42c6: 080d bt 0x42e0 // 42e0 + + ackPara[0] = PB_CMD_Reply_Succ; + 42c8: 3300 movi r3, 0 + 42ca: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLRELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 42cc: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 42ce: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLRELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 42d0: 2000 addi r0, 1 + 42d2: 74d0 zextb r3, r4 + 42d4: 5d5e addi r2, r5, 8 + 42d6: 7400 zextb r0, r0 + 42d8: 3122 movi r1, 34 + 42da: e3fff85b bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 42de: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 42e0: a660 st.b r3, (r6, 0x0) +} + 42e2: 07fe br 0x42de // 42de + 42e4: 0000588e .long 0x0000588e + 42e8: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_RELAY_SWITCH: + +000042ec : +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 42ec: 14d4 push r4-r7, r15 + 42ee: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 42f0: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 42f2: 104e lrw r2, 0x58ac // 4328 +void PB_ACK_SET_PB_RELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 42f4: 6d43 mov r5, r0 + 42f6: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 42f8: 3000 movi r0, 0 + 42fa: 102d lrw r1, 0x5a8e // 432c + 42fc: e3fff656 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4300: e3fff8a0 bsr 0x3440 // 3440 + 4304: 3840 cmpnei r0, 0 + *ackLen = 1; + 4306: 3301 movi r3, 1 + 4308: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 430a: 080d bt 0x4324 // 4324 + + ackPara[0] = PB_CMD_Reply_Succ; + 430c: 3300 movi r3, 0 + 430e: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4310: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4312: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4314: 2000 addi r0, 1 + 4316: 74d0 zextb r3, r4 + 4318: 5d5e addi r2, r5, 8 + 431a: 7400 zextb r0, r0 + 431c: 3123 movi r1, 35 + 431e: e3fff839 bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 4322: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4324: a660 st.b r3, (r6, 0x0) +} + 4326: 07fe br 0x4322 // 4322 + 4328: 000058ac .long 0x000058ac + 432c: 00005a8e .long 0x00005a8e + +Disassembly of section .text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH: + +00004330 : +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAY_DELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAY_DELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4330: 14d4 push r4-r7, r15 + 4332: 6dcb mov r7, r2 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4334: 8084 ld.b r4, (r0, 0x4) + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 4336: 104e lrw r2, 0x58c7 // 436c +void PB_ACK_SET_PB_RELAY_DELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 4338: 6d43 mov r5, r0 + 433a: 6d87 mov r6, r1 + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + 433c: 3000 movi r0, 0 + 433e: 102d lrw r1, 0x5a8e // 4370 + 4340: e3fff634 bsr 0x2fa8 // 2fa8 + + if(PowerBUS_GetCommState() == 0x00){ + 4344: e3fff87e bsr 0x3440 // 3440 + 4348: 3840 cmpnei r0, 0 + *ackLen = 1; + 434a: 3301 movi r3, 1 + 434c: af60 st.h r3, (r7, 0x0) + if(PowerBUS_GetCommState() == 0x00){ + 434e: 080d bt 0x4368 // 4368 + + ackPara[0] = PB_CMD_Reply_Succ; + 4350: 3300 movi r3, 0 + 4352: a660 st.b r3, (r6, 0x0) + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_DELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4354: 8507 ld.b r0, (r5, 0x7) + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + 4356: 2c07 subi r4, 8 + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_DELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + 4358: 2000 addi r0, 1 + 435a: 74d0 zextb r3, r4 + 435c: 5d5e addi r2, r5, 8 + 435e: 7400 zextb r0, r0 + 4360: 3124 movi r1, 36 + 4362: e3fff817 bsr 0x3390 // 3390 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + 4366: 1494 pop r4-r7, r15 + ackPara[0] = PB_CMD_Reply_CommStateBusy; + 4368: a660 st.b r3, (r6, 0x0) +} + 436a: 07fe br 0x4366 // 4366 + 436c: 000058c7 .long 0x000058c7 + 4370: 00005a8e .long 0x00005a8e + +Disassembly of section .text.Get_ADC_Val_Filter: + +00004374 : + +/********************************************************************* + * @fn Get_ADC_Val_Filter + * @brief 获取ADC平滑滤波后的值 + */ +U32_T Get_ADC_Val_Filter(U16_T *data,U8_T data_len){ + 4374: 14d1 push r4, r15 + 4376: 6d07 mov r4, r1 + 4378: 6c83 mov r2, r0 + U32_T sum_val = 0; + U16_T age_val = 0; + U8_T sum_cnt = 0; + + for(sum_cnt = 0;sum_cnt < data_len;sum_cnt++){ + 437a: 3100 movi r1, 0 + U32_T sum_val = 0; + 437c: 3000 movi r0, 0 + for(sum_cnt = 0;sum_cnt < data_len;sum_cnt++){ + 437e: 6506 cmpne r1, r4 + 4380: 0805 bt 0x438a // 438a + sum_val += data[sum_cnt]; + } + + age_val = (sum_val / data_len) & 0xFFFF; + 4382: e3fff569 bsr 0x2e54 // 2e54 <__udivsi3> + + return age_val; + 4386: 7401 zexth r0, r0 +} + 4388: 1491 pop r4, r15 + sum_val += data[sum_cnt]; + 438a: 8a60 ld.h r3, (r2, 0x0) + 438c: 600c addu r0, r3 + for(sum_cnt = 0;sum_cnt < data_len;sum_cnt++){ + 438e: 5962 addi r3, r1, 1 + 4390: 744c zextb r1, r3 + 4392: 2201 addi r2, 2 + 4394: 07f5 br 0x437e // 437e + +Disassembly of section .text.Get_PB_CURR_VAL: + +00004398 : + +/*获取电流值*/ +U16_T Get_PB_CURR_VAL(void){ + 4398: 14d0 push r15 + + U16_T Temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_CURRPWR_Buff,MEAS_Debounce_Num); + 439a: 3105 movi r1, 5 + 439c: 1006 lrw r0, 0x200006fc // 43b4 + 439e: e3ffffeb bsr 0x4374 // 4374 + g_PB.meas_powerbus_curr = (Temp_val * 16500 ) / 4096; + 43a2: 7401 zexth r0, r0 + 43a4: 1065 lrw r3, 0x4074 // 43b8 + 43a6: 7c0c mult r0, r3 + 43a8: 500c asri r0, r0, 12 + 43aa: 7401 zexth r0, r0 + 43ac: 1064 lrw r3, 0x200006a6 // 43bc + 43ae: ab00 st.h r0, (r3, 0x0) + return g_PB.meas_powerbus_curr; +} + 43b0: 1490 pop r15 + 43b2: 0000 bkpt + 43b4: 200006fc .long 0x200006fc + 43b8: 00004074 .long 0x00004074 + 43bc: 200006a6 .long 0x200006a6 + +Disassembly of section .text.PB_ACK_GET_STATE: + +000043c0 : +void PB_ACK_GET_STATE(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 43c0: 14d4 push r4-r7, r15 + 43c2: 1424 subi r14, r14, 16 + 43c4: 6d07 mov r4, r1 + 43c6: b841 st.w r2, (r14, 0x4) + U16_T temp_val = Get_PB_CURR_VAL(); + 43c8: e3ffffe8 bsr 0x4398 // 4398 + ackPara[i++] = g_pwm.allBrightness; //全局亮度 + 43cc: 1171 lrw r3, 0x20000718 // 4490 + 43ce: 8341 ld.b r2, (r3, 0x1) + 43d0: a440 st.b r2, (r4, 0x0) + ackPara[i++] = g_pwm.allBrightnessUpLimit; //全局亮度可调上限 + 43d2: 8342 ld.b r2, (r3, 0x2) + 43d4: a441 st.b r2, (r4, 0x1) + ackPara[i++] = g_pwm.allBrightnessDownLimit; //全局亮度可调下限 + 43d6: 8343 ld.b r2, (r3, 0x3) + 43d8: a442 st.b r2, (r4, 0x2) + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH1]; //灯亮度 - CH4 + 43da: 8344 ld.b r2, (r3, 0x4) + 43dc: a443 st.b r2, (r4, 0x3) + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH2]; //灯亮度 - CH3 + 43de: 8345 ld.b r2, (r3, 0x5) + 43e0: a444 st.b r2, (r4, 0x4) + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH3]; //灯亮度 - CH2 + 43e2: 8346 ld.b r2, (r3, 0x6) + 43e4: a445 st.b r2, (r4, 0x5) + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH4]; //灯亮度 - CH1 + 43e6: 8367 ld.b r3, (r3, 0x7) + ackPara[i++] = (g_PB.meas_powerstrip_volt >> 8) & 0xFF; //当前灯带电压 H + 43e8: 32ed movi r2, 237 + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH4]; //灯亮度 - CH1 + 43ea: a466 st.b r3, (r4, 0x6) + ackPara[i++] = (g_PB.meas_powerstrip_volt >> 8) & 0xFF; //当前灯带电压 H + 43ec: 4242 lsli r2, r2, 2 + 43ee: 116a lrw r3, 0x200002f0 // 4494 + 43f0: 608c addu r2, r3 + 43f2: 8a20 ld.h r1, (r2, 0x0) + 43f4: 4928 lsri r1, r1, 8 + 43f6: a427 st.b r1, (r4, 0x7) + ackPara[i++] = (g_PB.meas_powerstrip_volt) & 0xFF;; //当前灯带电压 L + 43f8: 8220 ld.b r1, (r2, 0x0) + 43fa: b843 st.w r2, (r14, 0xc) + ackPara[i++] = (g_PB.meas_powerbus_volt >> 8) & 0xFF; //当前PB BUS电压 H + 43fc: 11e7 lrw r7, 0x3b2 // 4498 + ackPara[i++] = 0x00; //当前灯带CH1 电流 H + 43fe: 3200 movi r2, 0 + 4400: a449 st.b r2, (r4, 0x9) + ackPara[i++] = 0x00; //当前灯带CH1 电流 L + 4402: a44a st.b r2, (r4, 0xa) + ackPara[i++] = 0x00; //当前灯带CH2 电流 H + 4404: a44b st.b r2, (r4, 0xb) + ackPara[i++] = 0x00; //当前灯带CH2 电流 L + 4406: a44c st.b r2, (r4, 0xc) + ackPara[i++] = 0x00; //当前灯带CH3 电流 H + 4408: a44d st.b r2, (r4, 0xd) + ackPara[i++] = 0x00; //当前灯带CH3 电流 L + 440a: a44e st.b r2, (r4, 0xe) + ackPara[i++] = 0x00; //当前灯带CH4 电流 H + 440c: a44f st.b r2, (r4, 0xf) + ackPara[i++] = 0x00; //当前灯带CH4 电流 L + 440e: a450 st.b r2, (r4, 0x10) + ackPara[i++] = 0x00; //g_PB.switchState[group]; //Bit7~Bit4:灯带开关状态MASK ,Bit3~Bit0:灯带故障状态 + 4410: a451 st.b r2, (r4, 0x11) + ackPara[i++] = (g_PB.meas_powerbus_volt >> 8) & 0xFF; //当前PB BUS电压 H + 4412: 61cc addu r7, r3 + ackPara[i++] = (g_PB.meas_powerstrip_volt) & 0xFF;; //当前灯带电压 L + 4414: a428 st.b r1, (r4, 0x8) + ackPara[i++] = (g_PB.meas_powerbus_volt >> 8) & 0xFF; //当前PB BUS电压 H + 4416: 8f20 ld.h r1, (r7, 0x0) + 4418: 4928 lsri r1, r1, 8 + 441a: a432 st.b r1, (r4, 0x12) + 441c: b862 st.w r3, (r14, 0x8) + ackPara[i++] = (temp_val >> 8) & 0xFF; //当前PB BUS电流 H + 441e: 4828 lsri r1, r0, 8 + ackPara[i++] = (g_PB.meas_powerbus_volt) & 0xFF; //当前PB BUS电压 L + 4420: 8760 ld.b r3, (r7, 0x0) + 4422: a473 st.b r3, (r4, 0x13) + ackPara[i++] = (temp_val >> 8) & 0xFF; //当前PB BUS电流 H + 4424: a434 st.b r1, (r4, 0x14) + ackPara[i++] = (temp_val) & 0xFF; //当前PB BUS电流 L + 4426: a415 st.b r0, (r4, 0x15) + U16_T temp_val = Get_PB_CURR_VAL(); + 4428: 6d83 mov r6, r0 + temp_power = temp_val * g_PB.meas_powerbus_volt / 1000; + 442a: 31fa movi r1, 250 + 442c: 8f00 ld.h r0, (r7, 0x0) + 442e: 7c18 mult r0, r6 + 4430: 4122 lsli r1, r1, 2 + 4432: e3fff4ff bsr 0x2e30 // 2e30 <__divsi3> + ackPara[i++] = g_PB.protect_flag; //PB BUS故障状态MASK + 4436: 9862 ld.w r3, (r14, 0x8) + 4438: 8354 ld.b r2, (r3, 0x14) + ackPara[i++] = (temp_power >> 24) & 0xFF; //当前PB BUS功率 H + 443a: 4838 lsri r1, r0, 24 + ackPara[i++] = g_PB.enable; //PB 输出使能状态 + 443c: 8372 ld.b r3, (r3, 0x12) + ackPara[i++] = (temp_power >> 24) & 0xFF; //当前PB BUS功率 H + 443e: a436 st.b r1, (r4, 0x16) + ackPara[i++] = g_PB.enable; //PB 输出使能状态 + 4440: a47b st.b r3, (r4, 0x1b) + ackPara[i++] = (temp_power >> 16) & 0xFF; //当前PB BUS功率 L + 4442: 4830 lsri r1, r0, 16 + ackPara[i++] = Project_Software_Ver; //PB 软件版本 + 4444: 3307 movi r3, 7 + ackPara[i++] = (temp_power >> 16) & 0xFF; //当前PB BUS功率 L + 4446: a437 st.b r1, (r4, 0x17) + ackPara[i++] = Project_Software_Ver; //PB 软件版本 + 4448: a47c st.b r3, (r4, 0x1c) + ackPara[i++] = (temp_power >> 8) & 0xFF; //当前PB BUS功率 H + 444a: 4828 lsri r1, r0, 8 + ackPara[i++] = Project_Hardware_Ver; //PB 硬件版本 + 444c: 3304 movi r3, 4 + 444e: a47d st.b r3, (r4, 0x1d) + ackPara[i++] = (temp_power >> 8) & 0xFF; //当前PB BUS功率 H + 4450: a438 st.b r1, (r4, 0x18) + ackPara[i++] = g_PB.protect_flag; //PB BUS故障状态MASK + 4452: a45a st.b r2, (r4, 0x1a) + ackPara[i++] = temp_power & 0xFF; //当前PB BUS功率 L + 4454: a419 st.b r0, (r4, 0x19) + temp_power = temp_val * g_PB.meas_powerbus_volt / 1000; + 4456: 6d43 mov r5, r0 + ackPara[i++] = PowerBUS_GetCommState(); //PowerBus 当前通讯状态 + 4458: e3fff7f4 bsr 0x3440 // 3440 + 445c: a41e st.b r0, (r4, 0x1e) + Dbg_Println(DBG_BIT_SYS_STATUS, "PS Voltage:%dmV",g_PB.meas_powerstrip_volt); + 445e: 9843 ld.w r2, (r14, 0xc) + 4460: 8a40 ld.h r2, (r2, 0x0) + 4462: 102f lrw r1, 0x5c37 // 449c + 4464: 3000 movi r0, 0 + 4466: e3fff5a1 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB CURR:%dmA Voltage:%dmV %dmW",temp_val,g_PB.meas_powerbus_volt,temp_power); + 446a: 8f60 ld.h r3, (r7, 0x0) + 446c: 6c9b mov r2, r6 + 446e: b8a0 st.w r5, (r14, 0x0) + 4470: 3000 movi r0, 0 + 4472: 102c lrw r1, 0x5c47 // 44a0 + 4474: e3fff59a bsr 0x2fa8 // 2fa8 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "ACK Buff:", ackPara, i); + 4478: 6c93 mov r2, r4 + 447a: 331f movi r3, 31 + 447c: 102a lrw r1, 0x5c66 // 44a4 + 447e: 3000 movi r0, 0 + 4480: e3fff59a bsr 0x2fb4 // 2fb4 + *ackLen = i; + 4484: 9861 ld.w r3, (r14, 0x4) + 4486: 321f movi r2, 31 + 4488: ab40 st.h r2, (r3, 0x0) +} + 448a: 1404 addi r14, r14, 16 + 448c: 1494 pop r4-r7, r15 + 448e: 0000 bkpt + 4490: 20000718 .long 0x20000718 + 4494: 200002f0 .long 0x200002f0 + 4498: 000003b2 .long 0x000003b2 + 449c: 00005c37 .long 0x00005c37 + 44a0: 00005c47 .long 0x00005c47 + 44a4: 00005c66 .long 0x00005c66 + +Disassembly of section .text.Current_Coarse_Filter: + +000044a8 : + } + +} + +//检测电流突变功能 +U16_T Current_Coarse_Filter(U16_T vsens){ + 44a8: 14d0 push r15 + U8_T i=0; + U16_T rev = 0; + U32_T filter_sum = 0; + curr_monitoring.coarse_filter_buff[Filter_Coarse_Size] = vsens; + 44aa: 1069 lrw r3, 0x20000258 // 44cc + for(i=0;i + } + rev = (U16_T)(filter_sum / Filter_Coarse_Size); + 44c2: 3105 movi r1, 5 + 44c4: e3fff4c8 bsr 0x2e54 // 2e54 <__udivsi3> + return rev; + 44c8: 7401 zexth r0, r0 +} + 44ca: 1490 pop r15 + 44cc: 20000258 .long 0x20000258 + +Disassembly of section .text.Current_Fine_Filter: + +000044d0 : + +U16_T Current_Fine_Filter(U16_T vsens){ + 44d0: 14d1 push r4, r15 + U8_T i=0; + U16_T rev = 0; + U32_T filter_sum = 0; + curr_monitoring.fine_filter_buff[Filter_Fine_Size] = vsens; + 44d2: 106a lrw r3, 0x200002d8 // 44f8 + 44d4: ab04 st.h r0, (r3, 0x8) + for(i=0;i + U32_T filter_sum = 0; + 44da: 3000 movi r0, 0 + for(i=0;i + } + rev = (U16_T)(filter_sum / Filter_Fine_Size); + 44ee: 3132 movi r1, 50 + 44f0: e3fff4b2 bsr 0x2e54 // 2e54 <__udivsi3> + return rev; + 44f4: 7401 zexth r0, r0 +} + 44f6: 1491 pop r4, r15 + 44f8: 200002d8 .long 0x200002d8 + 44fc: 20000258 .long 0x20000258 + +Disassembly of section .text.PB_Current_Monitoring_Meas: + +00004500 : + +void PB_Current_Monitoring_Meas(void){ + 4500: 14d3 push r4-r6, r15 + 4502: 1422 subi r14, r14, 8 + U16_T coarse_val = 0,fine_val = 0; + int temp_diff_val = 0,temp_power = 0; + + if(curr_monitoring.fun_enable != 0x01) return ; + 4504: 1285 lrw r4, 0x20000258 // 4618 + 4506: 8463 ld.b r3, (r4, 0x3) + 4508: 3b41 cmpnei r3, 1 + 450a: 0832 bt 0x456e // 456e + + coarse_val = Current_Coarse_Filter(g_PB.meas_powerbus_curr); + 450c: 12c4 lrw r6, 0x200006a6 // 461c + 450e: 8e00 ld.h r0, (r6, 0x0) + 4510: e3ffffcc bsr 0x44a8 // 44a8 + 4514: 6d43 mov r5, r0 + fine_val = Current_Fine_Filter(g_PB.meas_powerbus_curr); + 4516: 8e00 ld.h r0, (r6, 0x0) + 4518: e3ffffdc bsr 0x44d0 // 44d0 + + curr_monitoring.curr_diff_val = coarse_val - fine_val; + 451c: 5d41 subu r2, r5, r0 + 451e: 3680 movi r6, 128 + 4520: 6190 addu r6, r4 + temp_diff_val = abs(curr_monitoring.curr_diff_val); + 4522: 3adf btsti r2, 31 + curr_monitoring.curr_diff_val = coarse_val - fine_val; + 4524: b645 st.w r2, (r6, 0x14) + temp_diff_val = abs(curr_monitoring.curr_diff_val); + 4526: 0c03 bf 0x452c // 452c + 4528: 3300 movi r3, 0 + 452a: 5b49 subu r2, r3, r2 + temp_power = temp_diff_val * g_PB.meas_powerbus_volt / 1000; + 452c: 117d lrw r3, 0x200006a2 // 4620 + 452e: 8b00 ld.h r0, (r3, 0x0) + 4530: 31fa movi r1, 250 + 4532: 7c08 mult r0, r2 + 4534: 4122 lsli r1, r1, 2 + 4536: b841 st.w r2, (r14, 0x4) + 4538: e3fff47c bsr 0x2e30 // 2e30 <__divsi3> + + if(curr_monitoring.dead_switch != 0x00){ + 453c: 8462 ld.b r3, (r4, 0x2) + 453e: 3b40 cmpnei r3, 0 + temp_power = temp_diff_val * g_PB.meas_powerbus_volt / 1000; + 4540: 6d43 mov r5, r0 + if(curr_monitoring.dead_switch != 0x00){ + 4542: 9841 ld.w r2, (r14, 0x4) + 4544: 0c19 bf 0x4576 // 4576 +// curr_monitoring.dead_tick = SysTick_1ms; +// } + + //根据当前是否处于稳定范围 + + if(temp_power <= 1000){ + 4546: 33fa movi r3, 250 + 4548: 4362 lsli r3, r3, 2 + 454a: 640d cmplt r3, r0 + 454c: 0813 bt 0x4572 // 4572 + + curr_monitoring.release_debounce_cnt++; + 454e: 846e ld.b r3, (r4, 0xe) + 4550: 2300 addi r3, 1 + 4552: 74cc zextb r3, r3 + if(curr_monitoring.release_debounce_cnt >= 20){ + 4554: 3b13 cmphsi r3, 20 + curr_monitoring.release_debounce_cnt++; + 4556: a46e st.b r3, (r4, 0xe) + if(curr_monitoring.release_debounce_cnt >= 20){ + 4558: 0c04 bf 0x4560 // 4560 + curr_monitoring.dead_switch = 0x00; + 455a: 3300 movi r3, 0 + 455c: a462 st.b r3, (r4, 0x2) + curr_monitoring.release_debounce_cnt = 0; + } + }else{ + curr_monitoring.release_debounce_cnt = 0; + 455e: a46e st.b r3, (r4, 0xe) + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Curr Monit: %d - %dmW JUMP %d",temp_diff_val,temp_power,curr_monitoring.release_debounce_cnt); + 4560: 846e ld.b r3, (r4, 0xe) + 4562: b860 st.w r3, (r14, 0x0) + 4564: 3000 movi r0, 0 + 4566: 6cd7 mov r3, r5 + 4568: 112f lrw r1, 0x5c70 // 4624 + 456a: e3fff51f bsr 0x2fa8 // 2fa8 + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.release_strip_bright[PWM_OUT_CH4]); + } + } + + //Dbg_NoTick_Println(DBG_BIT_Debug_STATUS,"%d,%d,%d,%d",coarse_val,fine_val,curr_monitoring.curr_diff_val,curr_monitoring.pb_state); +} + 456e: 1402 addi r14, r14, 8 + 4570: 1493 pop r4-r6, r15 + curr_monitoring.release_debounce_cnt = 0; + 4572: 3300 movi r3, 0 + 4574: 07f5 br 0x455e // 455e + Dbg_Println(DBG_BIT_SYS_STATUS,"Curr Monit: %d - %dmW",temp_diff_val,temp_power); + 4576: 6cc3 mov r3, r0 + 4578: 112c lrw r1, 0x5c8f // 4628 + 457a: 3000 movi r0, 0 + 457c: e3fff516 bsr 0x2fa8 // 2fa8 + if(curr_monitoring.curr_diff_val >= 0){ + 4580: 9665 ld.w r3, (r6, 0x14) + 4582: 3bdf btsti r3, 31 + 4584: 082c bt 0x45dc // 45dc + if(temp_power >= curr_monitoring.trigger_threshold){ + 4586: 8c6a ld.h r3, (r4, 0x14) + 4588: 64d5 cmplt r5, r3 + 458a: 080a bt 0x459e // 459e + curr_monitoring.trigger_debounce_cnt++; + 458c: 846d ld.b r3, (r4, 0xd) + 458e: 2300 addi r3, 1 + 4590: 74cc zextb r3, r3 + if(curr_monitoring.trigger_debounce_cnt >= curr_monitoring.trigger_debounce_num){ + 4592: 844f ld.b r2, (r4, 0xf) + 4594: 648c cmphs r3, r2 + curr_monitoring.trigger_debounce_cnt++; + 4596: a46d st.b r3, (r4, 0xd) + if(curr_monitoring.trigger_debounce_cnt >= curr_monitoring.trigger_debounce_num){ + 4598: 0c05 bf 0x45a2 // 45a2 + curr_monitoring.pb_state = 0x01; + 459a: 3301 movi r3, 1 + 459c: a460 st.b r3, (r4, 0x0) + curr_monitoring.trigger_debounce_cnt = 0; + 459e: 3300 movi r3, 0 + 45a0: a46d st.b r3, (r4, 0xd) + if(curr_monitoring.pb_state != curr_monitoring.last_pb_state){ + 45a2: 8440 ld.b r2, (r4, 0x0) + 45a4: 8461 ld.b r3, (r4, 0x1) + 45a6: 648e cmpne r3, r2 + 45a8: 0fe3 bf 0x456e // 456e + Dbg_Println(DBG_BIT_SYS_STATUS,"curr_monitoring state: %d",curr_monitoring.pb_state); + 45aa: 1121 lrw r1, 0x5ca5 // 462c + 45ac: 3000 movi r0, 0 + curr_monitoring.last_pb_state = curr_monitoring.pb_state; + 45ae: a441 st.b r2, (r4, 0x1) + Dbg_Println(DBG_BIT_SYS_STATUS,"curr_monitoring state: %d",curr_monitoring.pb_state); + 45b0: e3fff4fc bsr 0x2fa8 // 2fa8 + if(curr_monitoring.pb_state == 0x01){ + 45b4: 8460 ld.b r3, (r4, 0x0) + 45b6: 3b41 cmpnei r3, 1 + 45b8: 0822 bt 0x45fc // 45fc + PWM_SetOutBrightness(PWM_OUT_CH1,curr_monitoring.triggle_strip_bright[PWM_OUT_CH1]); + 45ba: 8425 ld.b r1, (r4, 0x5) + 45bc: 3000 movi r0, 0 + 45be: e00003b1 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2,curr_monitoring.triggle_strip_bright[PWM_OUT_CH2]); + 45c2: 8426 ld.b r1, (r4, 0x6) + 45c4: 3001 movi r0, 1 + 45c6: e00003ad bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3,curr_monitoring.triggle_strip_bright[PWM_OUT_CH3]); + 45ca: 8427 ld.b r1, (r4, 0x7) + 45cc: 3002 movi r0, 2 + 45ce: e00003a9 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.triggle_strip_bright[PWM_OUT_CH4]); + 45d2: 8428 ld.b r1, (r4, 0x8) + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.release_strip_bright[PWM_OUT_CH4]); + 45d4: 3003 movi r0, 3 + 45d6: e00003a5 bsr 0x4d20 // 4d20 + 45da: 07ca br 0x456e // 456e + if(temp_power >= curr_monitoring.release_threshold){ + 45dc: 8c6b ld.h r3, (r4, 0x16) + 45de: 64d5 cmplt r5, r3 + 45e0: 080c bt 0x45f8 // 45f8 + curr_monitoring.release_debounce_cnt++; + 45e2: 846e ld.b r3, (r4, 0xe) + 45e4: 2300 addi r3, 1 + 45e6: 74cc zextb r3, r3 + if(curr_monitoring.release_debounce_cnt >= curr_monitoring.release_debounce_num){ + 45e8: 8450 ld.b r2, (r4, 0x10) + 45ea: 648c cmphs r3, r2 + curr_monitoring.release_debounce_cnt++; + 45ec: a46e st.b r3, (r4, 0xe) + if(curr_monitoring.release_debounce_cnt >= curr_monitoring.release_debounce_num){ + 45ee: 0fda bf 0x45a2 // 45a2 + curr_monitoring.pb_state = 0x00; + 45f0: 3300 movi r3, 0 + 45f2: a460 st.b r3, (r4, 0x0) + curr_monitoring.release_debounce_cnt = 0; + 45f4: a46e st.b r3, (r4, 0xe) + 45f6: 07d6 br 0x45a2 // 45a2 + 45f8: 3300 movi r3, 0 + 45fa: 07fd br 0x45f4 // 45f4 + PWM_SetOutBrightness(PWM_OUT_CH1,curr_monitoring.release_strip_bright[PWM_OUT_CH1]); + 45fc: 8429 ld.b r1, (r4, 0x9) + 45fe: 3000 movi r0, 0 + 4600: e0000390 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2,curr_monitoring.release_strip_bright[PWM_OUT_CH2]); + 4604: 842a ld.b r1, (r4, 0xa) + 4606: 3001 movi r0, 1 + 4608: e000038c bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3,curr_monitoring.release_strip_bright[PWM_OUT_CH3]); + 460c: 842b ld.b r1, (r4, 0xb) + 460e: 3002 movi r0, 2 + 4610: e0000388 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.release_strip_bright[PWM_OUT_CH4]); + 4614: 842c ld.b r1, (r4, 0xc) + 4616: 07df br 0x45d4 // 45d4 + 4618: 20000258 .long 0x20000258 + 461c: 200006a6 .long 0x200006a6 + 4620: 200006a2 .long 0x200006a2 + 4624: 00005c70 .long 0x00005c70 + 4628: 00005c8f .long 0x00005c8f + 462c: 00005ca5 .long 0x00005ca5 + +Disassembly of section .text.PMU_MEAS_Task: + +00004630 : +void PMU_MEAS_Task(void){ + 4630: 14d2 push r4-r5, r15 + if(SysTick_1ms - meas_tick >= 30){ + 4632: 132c lrw r1, 0x20000070 // 47e0 + 4634: 134c lrw r2, 0x20000074 // 47e4 + 4636: 138d lrw r4, 0x200002f0 // 47e8 + 4638: 9201 ld.w r0, (r2, 0x4) + 463a: 9160 ld.w r3, (r1, 0x0) + 463c: 60c2 subu r3, r0 + 463e: 3b1d cmphsi r3, 30 + 4640: 0c9a bf 0x4774 // 4774 + meas_tick = SysTick_1ms; + 4642: 9160 ld.w r3, (r1, 0x0) + 4644: b261 st.w r3, (r2, 0x4) + if(g_PB.meas_cnt >= MEAS_BUFFER_SIZE) { + 4646: 8460 ld.b r3, (r4, 0x0) + 4648: 3b13 cmphsi r3, 20 + 464a: 0c05 bf 0x4654 // 4654 + g_PB.meas_fill_flag = 0x01; + 464c: 3301 movi r3, 1 + 464e: a461 st.b r3, (r4, 0x1) + g_PB.meas_cnt = 0; + 4650: 3300 movi r3, 0 + 4652: a460 st.b r3, (r4, 0x0) + ADC12_SEQEND_wait(0); + 4654: 3000 movi r0, 0 + 4656: e3ffeac1 bsr 0x1bd8 // 1bd8 + g_PB.meas_hv_PB_val[g_PB.meas_cnt] = ADC12_DATA_OUPUT(0); + 465a: 3000 movi r0, 0 + 465c: 84a0 ld.b r5, (r4, 0x0) + 465e: e3ffeac9 bsr 0x1bf0 // 1bf0 + 4662: 33ee movi r3, 238 + 4664: 4361 lsli r3, r3, 1 + 4666: 614c addu r5, r3 + 4668: 45a1 lsli r5, r5, 1 + 466a: 6150 addu r5, r4 + 466c: ad00 st.h r0, (r5, 0x0) + ADC12_SEQEND_wait(1); + 466e: 3001 movi r0, 1 + 4670: e3ffeab4 bsr 0x1bd8 // 1bd8 + g_PB.meas_hv_PS_val[g_PB.meas_cnt] = ADC12_DATA_OUPUT(1); + 4674: 3001 movi r0, 1 + 4676: 84a0 ld.b r5, (r4, 0x0) + 4678: e3ffeabc bsr 0x1bf0 // 1bf0 + 467c: 33f8 movi r3, 248 + 467e: 4361 lsli r3, r3, 1 + 4680: 614c addu r5, r3 + 4682: 45a1 lsli r5, r5, 1 + 4684: 6150 addu r5, r4 + 4686: ad00 st.h r0, (r5, 0x0) + ADC12_SEQEND_wait(2); + 4688: 3002 movi r0, 2 + 468a: e3ffeaa7 bsr 0x1bd8 // 1bd8 + g_PB.meas_hv_CURRPWRx5_val = ADC12_DATA_OUPUT(2); + 468e: 3002 movi r0, 2 + 4690: e3ffeab0 bsr 0x1bf0 // 1bf0 + 4694: 12b6 lrw r5, 0x200006f8 // 47ec + 4696: ad00 st.h r0, (r5, 0x0) + ADC12_SEQEND_wait(3); + 4698: 3003 movi r0, 3 + 469a: e3ffea9f bsr 0x1bd8 // 1bd8 + g_PB.meas_hv_CURRPWRx50_val = ADC12_DATA_OUPUT(3); + 469e: 3003 movi r0, 3 + 46a0: e3ffeaa8 bsr 0x1bf0 // 1bf0 + if(g_PB.meas_hv_curr_cnt >= MEAS_Debounce_Num){ + 46a4: 846c ld.b r3, (r4, 0xc) + 46a6: 3b04 cmphsi r3, 5 + g_PB.meas_hv_CURRPWRx50_val = ADC12_DATA_OUPUT(3); + 46a8: ad01 st.h r0, (r5, 0x2) + if(g_PB.meas_hv_curr_cnt >= MEAS_Debounce_Num){ + 46aa: 0c03 bf 0x46b0 // 46b0 + g_PB.meas_hv_curr_cnt = 0; + 46ac: 3300 movi r3, 0 + 46ae: a46c st.b r3, (r4, 0xc) + g_PB.meas_hv_CURRPWR_Buff[g_PB.meas_hv_curr_cnt++] = g_PB.meas_hv_CURRPWRx5_val; + 46b0: 846c ld.b r3, (r4, 0xc) + 46b2: 5b42 addi r2, r3, 1 + 46b4: a44c st.b r2, (r4, 0xc) + 46b6: 124f lrw r2, 0x206 // 47f0 + 46b8: 60c8 addu r3, r2 + 46ba: 4361 lsli r3, r3, 1 + 46bc: 60d0 addu r3, r4 + 46be: 8d40 ld.h r2, (r5, 0x0) + 46c0: ab40 st.h r2, (r3, 0x0) + Get_PB_CURR_VAL(); + 46c2: e3fffe6b bsr 0x4398 // 4398 + PB_Current_Monitoring_Meas(); + 46c6: e3ffff1d bsr 0x4500 // 4500 + g_PB.meas_cnt++; + 46ca: 8460 ld.b r3, (r4, 0x0) + 46cc: 2300 addi r3, 1 + 46ce: a460 st.b r3, (r4, 0x0) + if(g_PB.meas_fill_flag != 0x01) return ; //检测BUFF未满,直接退出 + 46d0: 8461 ld.b r3, (r4, 0x1) + 46d2: 3b41 cmpnei r3, 1 + 46d4: 0876 bt 0x47c0 // 47c0 + g_PB.meas_fill_flag = 0x00; //重新开始计数 + 46d6: 3300 movi r3, 0 + temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_PB_val,MEAS_BUFFER_SIZE); + 46d8: 3114 movi r1, 20 + 46da: 1207 lrw r0, 0x200006a8 // 47f4 + g_PB.meas_fill_flag = 0x00; //重新开始计数 + 46dc: a461 st.b r3, (r4, 0x1) + temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_PB_val,MEAS_BUFFER_SIZE); + 46de: e3fffe4b bsr 0x4374 // 4374 + g_PB.meas_powerbus_volt = (temp_val * 3300 * 16) / 4096; //输入电压 = 检测电压 * 16 + 46e2: 1266 lrw r3, 0xce40 // 47f8 + 46e4: 7c0c mult r0, r3 + 46e6: 480c lsri r0, r0, 12 + 46e8: 7401 zexth r0, r0 + 46ea: 1265 lrw r3, 0x200006a2 // 47fc + 46ec: ab00 st.h r0, (r3, 0x0) + if( (g_PB.meas_powerbus_volt >= MEAS_InputVoltage_Min) && (g_PB.meas_powerbus_volt <= MEAS_InputVoltage_Max) ){ + 46ee: 1265 lrw r3, 0xffffd8f0 // 4800 + 46f0: 600c addu r0, r3 + 46f2: 7401 zexth r0, r0 + 46f4: 1264 lrw r3, 0x6d60 // 4804 + 46f6: 640c cmphs r3, r0 + 46f8: 0c0e bf 0x4714 // 4714 + g_PB.meas_hv_PB_ONcnt++; + 46fa: 8462 ld.b r3, (r4, 0x2) + 46fc: 2300 addi r3, 1 + 46fe: 74cc zextb r3, r3 + g_PB.meas_hv_PB_OFFcnt = 0x00; + 4700: 3200 movi r2, 0 + if(g_PB.meas_hv_PB_ONcnt >= MEAS_Debounce_Num){ + 4702: 3b04 cmphsi r3, 5 + g_PB.meas_hv_PB_ONcnt++; + 4704: a462 st.b r3, (r4, 0x2) + g_PB.meas_hv_PB_OFFcnt = 0x00; + 4706: a444 st.b r2, (r4, 0x4) + if(g_PB.meas_hv_PB_ONcnt >= MEAS_Debounce_Num){ + 4708: 0c0e bf 0x4724 // 4724 + g_PB.meas_hv_PB_ONcnt = 0x00; + 470a: 3300 movi r3, 0 + 470c: a462 st.b r3, (r4, 0x2) + g_PB.meas_hv_PB_State = 0x01; + 470e: 3301 movi r3, 1 + g_PB.meas_hv_PB_State = 0x00; + 4710: a466 st.b r3, (r4, 0x6) + 4712: 0409 br 0x4724 // 4724 + g_PB.meas_hv_PB_ONcnt = 0x00; + 4714: 3300 movi r3, 0 + 4716: a462 st.b r3, (r4, 0x2) + g_PB.meas_hv_PB_OFFcnt++; + 4718: 8464 ld.b r3, (r4, 0x4) + 471a: 2300 addi r3, 1 + 471c: 74cc zextb r3, r3 + if(g_PB.meas_hv_PB_OFFcnt >= MEAS_Debounce_Num){ + 471e: 3b04 cmphsi r3, 5 + 4720: 081f bt 0x475e // 475e + g_PB.meas_hv_PB_OFFcnt++; + 4722: a464 st.b r3, (r4, 0x4) + temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_PS_val,MEAS_BUFFER_SIZE); + 4724: 3114 movi r1, 20 + 4726: 1119 lrw r0, 0x200006d0 // 4808 + 4728: e3fffe26 bsr 0x4374 // 4374 + g_PB.meas_powerstrip_volt = (temp_val * 3300 * 16) / 4096; + 472c: 1173 lrw r3, 0xce40 // 47f8 + 472e: 7c0c mult r0, r3 + 4730: 480c lsri r0, r0, 12 + 4732: 7401 zexth r0, r0 + 4734: 1176 lrw r3, 0x200006a4 // 480c + 4736: ab00 st.h r0, (r3, 0x0) + if( (g_PB.meas_powerstrip_volt >= MEAS_InputVoltage_Min) && (g_PB.meas_powerstrip_volt <= MEAS_InputVoltage_Max)){ + 4738: 1172 lrw r3, 0xffffd8f0 // 4800 + 473a: 600c addu r0, r3 + 473c: 7401 zexth r0, r0 + 473e: 1172 lrw r3, 0x6d60 // 4804 + 4740: 640c cmphs r3, r0 + 4742: 0c11 bf 0x4764 // 4764 + g_PB.meas_hv_PS_ONcnt++; + 4744: 8463 ld.b r3, (r4, 0x3) + 4746: 2300 addi r3, 1 + 4748: 74cc zextb r3, r3 + g_PB.meas_hv_PS_OFFcnt = 0x00; + 474a: 3200 movi r2, 0 + if(g_PB.meas_hv_PS_ONcnt >= MEAS_Debounce_Num){ + 474c: 3b04 cmphsi r3, 5 + g_PB.meas_hv_PS_ONcnt++; + 474e: a463 st.b r3, (r4, 0x3) + g_PB.meas_hv_PS_OFFcnt = 0x00; + 4750: a445 st.b r2, (r4, 0x5) + if(g_PB.meas_hv_PS_ONcnt >= MEAS_Debounce_Num){ + 4752: 0c11 bf 0x4774 // 4774 + g_PB.meas_hv_PS_ONcnt = 0x00; + 4754: 3300 movi r3, 0 + 4756: a463 st.b r3, (r4, 0x3) + g_PB.meas_hv_PS_State = 0x01; + 4758: 3301 movi r3, 1 + g_PB.meas_hv_PS_State = 0x00; + 475a: a467 st.b r3, (r4, 0x7) + 475c: 040c br 0x4774 // 4774 + g_PB.meas_hv_PB_OFFcnt = 0x00; + 475e: 3300 movi r3, 0 + 4760: a464 st.b r3, (r4, 0x4) + 4762: 07d7 br 0x4710 // 4710 + g_PB.meas_hv_PS_ONcnt = 0x00; + 4764: 3300 movi r3, 0 + 4766: a463 st.b r3, (r4, 0x3) + g_PB.meas_hv_PS_OFFcnt++; + 4768: 8465 ld.b r3, (r4, 0x5) + 476a: 2300 addi r3, 1 + 476c: 74cc zextb r3, r3 + if(g_PB.meas_hv_PS_OFFcnt >= MEAS_Debounce_Num){ + 476e: 3b04 cmphsi r3, 5 + 4770: 0829 bt 0x47c2 // 47c2 + g_PB.meas_hv_PS_OFFcnt++; + 4772: a465 st.b r3, (r4, 0x5) + if(g_PB.meas_hv_PB_State != g_PB.last_meas_hv_PB_State) { + 4774: 8446 ld.b r2, (r4, 0x6) + 4776: 8468 ld.b r3, (r4, 0x8) + 4778: 648e cmpne r3, r2 + 477a: 0c10 bf 0x479a // 479a + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PB State Change : %d",g_PB.last_meas_hv_PB_State); + 477c: 1125 lrw r1, 0x5cbf // 4810 + 477e: 3000 movi r0, 0 + g_PB.last_meas_hv_PB_State = g_PB.meas_hv_PB_State; + 4780: a448 st.b r2, (r4, 0x8) + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PB State Change : %d",g_PB.last_meas_hv_PB_State); + 4782: e3fff413 bsr 0x2fa8 // 2fa8 + switch(g_PB.last_meas_hv_PB_State) { + 4786: 8468 ld.b r3, (r4, 0x8) + 4788: 3b40 cmpnei r3, 0 + 478a: 0c1f bf 0x47c8 // 47c8 + 478c: 3b41 cmpnei r3, 1 + 478e: 0806 bt 0x479a // 479a + DRV_PB36V_ON; + 4790: 1161 lrw r3, 0x20000048 // 4814 + 4792: 3104 movi r1, 4 + 4794: 9300 ld.w r0, (r3, 0x0) + 4796: e3ffe569 bsr 0x1268 // 1268 + if(g_PB.meas_hv_PS_State != g_PB.last_meas_hv_PS_State){ + 479a: 8447 ld.b r2, (r4, 0x7) + 479c: 8469 ld.b r3, (r4, 0x9) + 479e: 648e cmpne r3, r2 + 47a0: 0c10 bf 0x47c0 // 47c0 + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PS State Change : %d",g_PB.last_meas_hv_PS_State); + 47a2: 103e lrw r1, 0x5cd7 // 4818 + 47a4: 3000 movi r0, 0 + g_PB.last_meas_hv_PS_State = g_PB.meas_hv_PS_State; + 47a6: a449 st.b r2, (r4, 0x9) + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PS State Change : %d",g_PB.last_meas_hv_PS_State); + 47a8: e3fff400 bsr 0x2fa8 // 2fa8 + switch(g_PB.last_meas_hv_PS_State) { + 47ac: 8469 ld.b r3, (r4, 0x9) + 47ae: 3b40 cmpnei r3, 0 + 47b0: 0c12 bf 0x47d4 // 47d4 + 47b2: 3b41 cmpnei r3, 1 + 47b4: 0806 bt 0x47c0 // 47c0 + DRV_PS36V_ON; + 47b6: 107a lrw r3, 0x2000004c // 481c + 47b8: 310e movi r1, 14 + 47ba: 9300 ld.w r0, (r3, 0x0) + 47bc: e3ffe556 bsr 0x1268 // 1268 +} + 47c0: 1492 pop r4-r5, r15 + g_PB.meas_hv_PS_OFFcnt = 0x00; + 47c2: 3300 movi r3, 0 + 47c4: a465 st.b r3, (r4, 0x5) + 47c6: 07ca br 0x475a // 475a + DRV_PB36V_OFF; + 47c8: 1073 lrw r3, 0x20000048 // 4814 + 47ca: 3104 movi r1, 4 + 47cc: 9300 ld.w r0, (r3, 0x0) + 47ce: e3ffe551 bsr 0x1270 // 1270 + break; + 47d2: 07e4 br 0x479a // 479a + DRV_PS36V_OFF; + 47d4: 1072 lrw r3, 0x2000004c // 481c + 47d6: 310e movi r1, 14 + 47d8: 9300 ld.w r0, (r3, 0x0) + 47da: e3ffe54b bsr 0x1270 // 1270 + break; + 47de: 07f1 br 0x47c0 // 47c0 + 47e0: 20000070 .long 0x20000070 + 47e4: 20000074 .long 0x20000074 + 47e8: 200002f0 .long 0x200002f0 + 47ec: 200006f8 .long 0x200006f8 + 47f0: 00000206 .long 0x00000206 + 47f4: 200006a8 .long 0x200006a8 + 47f8: 0000ce40 .long 0x0000ce40 + 47fc: 200006a2 .long 0x200006a2 + 4800: ffffd8f0 .long 0xffffd8f0 + 4804: 00006d60 .long 0x00006d60 + 4808: 200006d0 .long 0x200006d0 + 480c: 200006a4 .long 0x200006a4 + 4810: 00005cbf .long 0x00005cbf + 4814: 20000048 .long 0x20000048 + 4818: 00005cd7 .long 0x00005cd7 + 481c: 2000004c .long 0x2000004c + +Disassembly of section .text.Set_PB_CurrMonitoring_Dead: + +00004820 : + +/*让PB触发电流失效一段时间*/ +void Set_PB_CurrMonitoring_Dead(void){ + curr_monitoring.dead_switch = 0x01; + 4820: 1063 lrw r3, 0x20000258 // 482c + 4822: 3201 movi r2, 1 + 4824: a342 st.b r2, (r3, 0x2) + //根据时间 +// curr_monitoring.dead_time = time; +// curr_monitoring.dead_tick = SysTick_1ms; + + //根据稳定 + curr_monitoring.release_debounce_cnt = 0; + 4826: 3200 movi r2, 0 + 4828: a34e st.b r2, (r3, 0xe) +} + 482a: 783c jmp r15 + 482c: 20000258 .long 0x20000258 + +Disassembly of section .text.PowerBus_SendBuffer_Task: + +00004830 : +void PowerBus_SendBuffer_Task(void){ + 4830: 14d1 push r4, r15 + if(g_PB.sendWriteCnt != g_PB.sendReadCnt){ + 4832: 107b lrw r3, 0x200002f0 // 489c + 4834: 3460 movi r4, 96 + 4836: 3280 movi r2, 128 + 4838: 610c addu r4, r3 + 483a: 608c addu r2, r3 + 483c: 841f ld.b r0, (r4, 0x1f) + 483e: 8240 ld.b r2, (r2, 0x0) + 4840: 640a cmpne r2, r0 + 4842: 0c21 bf 0x4884 // 4884 + if(SysTick_1ms - g_PB.send_tick >= POWERBUS_SEND_DELAY){ + 4844: 1037 lrw r1, 0x424 // 48a0 + 4846: 1058 lrw r2, 0x20000070 // 48a4 + 4848: 604c addu r1, r3 + 484a: 9120 ld.w r1, (r1, 0x0) + 484c: 9240 ld.w r2, (r2, 0x0) + 484e: 6086 subu r2, r1 + 4850: 3131 movi r1, 49 + 4852: 6484 cmphs r1, r2 + 4854: 0818 bt 0x4884 // 4884 + if(g_PB.sendCnt < g_PB.resendNum){ + 4856: 1055 lrw r2, 0x3a9 // 48a8 + 4858: 608c addu r2, r3 + 485a: 843e ld.b r1, (r4, 0x1e) + 485c: 8240 ld.b r2, (r2, 0x0) + 485e: 6484 cmphs r1, r2 + 4860: 0813 bt 0x4886 // 4886 + send_rev = PowerBus_Data_Send(g_PB.sendbuffer[g_PB.sendReadCnt], g_PB.sendbufferlen[g_PB.sendReadCnt]); + 4862: 60c0 addu r3, r0 + 4864: 2380 addi r3, 129 + 4866: 8320 ld.b r1, (r3, 0x0) + 4868: 3364 movi r3, 100 + 486a: 7c0c mult r0, r3 + 486c: 1070 lrw r3, 0x20000379 // 48ac + 486e: 600c addu r0, r3 + 4870: e3fff4ca bsr 0x3204 // 3204 + if(send_rev != 0xFF){ + 4874: 33ff movi r3, 255 + 4876: 64c2 cmpne r0, r3 + 4878: 0c06 bf 0x4884 // 4884 + Set_PB_CurrMonitoring_Dead(); + 487a: e3ffffd3 bsr 0x4820 // 4820 + g_PB.sendCnt++; + 487e: 847e ld.b r3, (r4, 0x1e) + 4880: 2300 addi r3, 1 + 4882: a47e st.b r3, (r4, 0x1e) +} + 4884: 1491 pop r4, r15 + g_PB.sendReadCnt++; + 4886: 2000 addi r0, 1 + 4888: 7400 zextb r0, r0 + g_PB.sendCnt = 0; + 488a: 3300 movi r3, 0 + if(g_PB.sendReadCnt >= PB_BUFFER_NUM){ + 488c: 3807 cmphsi r0, 8 + g_PB.sendCnt = 0; + 488e: a47e st.b r3, (r4, 0x1e) + if(g_PB.sendReadCnt >= PB_BUFFER_NUM){ + 4890: 0803 bt 0x4896 // 4896 + g_PB.sendReadCnt++; + 4892: a41f st.b r0, (r4, 0x1f) + 4894: 07f8 br 0x4884 // 4884 + g_PB.sendReadCnt = 0; + 4896: 3300 movi r3, 0 + 4898: a47f st.b r3, (r4, 0x1f) + 489a: 07f5 br 0x4884 // 4884 + 489c: 200002f0 .long 0x200002f0 + 48a0: 00000424 .long 0x00000424 + 48a4: 20000070 .long 0x20000070 + 48a8: 000003a9 .long 0x000003a9 + 48ac: 20000379 .long 0x20000379 + +Disassembly of section .text.PB_ACK_SET_CurrTiggleStrip: + +000048b0 : +void PB_ACK_SET_CurrTiggleStrip(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 48b0: 14d4 push r4-r7, r15 + 48b2: 1421 subi r14, r14, 4 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA; + 48b4: 8064 ld.b r3, (r0, 0x4) + 48b6: 2b06 subi r3, 7 +void PB_ACK_SET_CurrTiggleStrip(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + 48b8: 6d43 mov r5, r0 + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA; + 48ba: 74cc zextb r3, r3 + *ackLen = 1; + 48bc: 3001 movi r0, 1 + 48be: aa00 st.h r0, (r2, 0x0) + if(para_len < 15) return ; + 48c0: 3b0e cmphsi r3, 15 + ackPara[0] = PB_CMD_Reply_Succ; + 48c2: 3200 movi r2, 0 + 48c4: a140 st.b r2, (r1, 0x0) + if(para_len < 15) return ; + 48c6: 0c86 bf 0x49d2 // 49d2 + if((curr_monitoring.fun_enable == 0x00) && (para[PB_FMT_PARA] == 0x01)){ + 48c8: 1284 lrw r4, 0x20000258 // 49d8 + 48ca: 8463 ld.b r3, (r4, 0x3) + 48cc: 3b40 cmpnei r3, 0 + 48ce: 0806 bt 0x48da // 48da + 48d0: 8567 ld.b r3, (r5, 0x7) + 48d2: 3b41 cmpnei r3, 1 + 48d4: 0803 bt 0x48da // 48da + Set_PB_CurrMonitoring_Dead(); + 48d6: e3ffffa5 bsr 0x4820 // 4820 + temp_para = temp_para * 10 * g_PB.meas_powerbus_volt / 1000; + 48da: 1261 lrw r3, 0x200006a2 // 49dc + 48dc: 8508 ld.b r0, (r5, 0x8) + 48de: 8be0 ld.h r7, (r3, 0x0) + 48e0: 330a movi r3, 10 + curr_monitoring.fun_enable = para[PB_FMT_PARA]; //使能状态 + 48e2: 85c7 ld.b r6, (r5, 0x7) + temp_para = temp_para * 10 * g_PB.meas_powerbus_volt / 1000; + 48e4: 7c0c mult r0, r3 + 48e6: 31fa movi r1, 250 + 48e8: 4122 lsli r1, r1, 2 + curr_monitoring.fun_enable = para[PB_FMT_PARA]; //使能状态 + 48ea: a4c3 st.b r6, (r4, 0x3) + temp_para = temp_para * 10 * g_PB.meas_powerbus_volt / 1000; + 48ec: 7c1c mult r0, r7 + 48ee: b860 st.w r3, (r14, 0x0) + 48f0: e3fff2a0 bsr 0x2e30 // 2e30 <__divsi3> + 48f4: ac0a st.h r0, (r4, 0x14) + curr_monitoring.trigger_debounce_num = para[PB_FMT_PARA + 2]; //触发消抖次数 + 48f6: 8569 ld.b r3, (r5, 0x9) + 48f8: a46f st.b r3, (r4, 0xf) + temp_para = temp_para * 10 * g_PB.meas_powerbus_volt / 1000; + 48fa: 850a ld.b r0, (r5, 0xa) + 48fc: 9860 ld.w r3, (r14, 0x0) + 48fe: 7c0c mult r0, r3 + 4900: 31fa movi r1, 250 + 4902: 4122 lsli r1, r1, 2 + 4904: 7c1c mult r0, r7 + 4906: e3fff295 bsr 0x2e30 // 2e30 <__divsi3> + 490a: ac0b st.h r0, (r4, 0x16) + curr_monitoring.release_debounce_num = para[PB_FMT_PARA + 4]; //释放消抖次数 + 490c: 856b ld.b r3, (r5, 0xb) + 490e: a470 st.b r3, (r4, 0x10) + curr_monitoring.strip_relation = para[PB_FMT_PARA + 5]; + 4910: 856c ld.b r3, (r5, 0xc) + 4912: a464 st.b r3, (r4, 0x4) + curr_monitoring.strip_gradient_time = curr_monitoring.strip_gradient_time * 100; + 4914: 3264 movi r2, 100 + curr_monitoring.strip_gradient_time = para[PB_FMT_PARA + 6]; + 4916: 856d ld.b r3, (r5, 0xd) + curr_monitoring.strip_gradient_time = curr_monitoring.strip_gradient_time * 100; + 4918: 7cc8 mult r3, r2 + 491a: ac69 st.h r3, (r4, 0x12) + curr_monitoring.triggle_strip_bright[PWM_OUT_CH1] = para[PB_FMT_PARA + 7]; + 491c: 856e ld.b r3, (r5, 0xe) + 491e: a465 st.b r3, (r4, 0x5) + curr_monitoring.triggle_strip_bright[PWM_OUT_CH2] = para[PB_FMT_PARA + 8]; + 4920: 856f ld.b r3, (r5, 0xf) + 4922: a466 st.b r3, (r4, 0x6) + curr_monitoring.triggle_strip_bright[PWM_OUT_CH3] = para[PB_FMT_PARA + 9]; + 4924: 8570 ld.b r3, (r5, 0x10) + 4926: a467 st.b r3, (r4, 0x7) + curr_monitoring.triggle_strip_bright[PWM_OUT_CH4] = para[PB_FMT_PARA + 10]; + 4928: 8571 ld.b r3, (r5, 0x11) + 492a: a468 st.b r3, (r4, 0x8) + curr_monitoring.release_strip_bright[PWM_OUT_CH1] = para[PB_FMT_PARA + 11]; + 492c: 8572 ld.b r3, (r5, 0x12) + 492e: a469 st.b r3, (r4, 0x9) + curr_monitoring.release_strip_bright[PWM_OUT_CH2] = para[PB_FMT_PARA + 12]; + 4930: 8573 ld.b r3, (r5, 0x13) + 4932: a46a st.b r3, (r4, 0xa) + curr_monitoring.release_strip_bright[PWM_OUT_CH3] = para[PB_FMT_PARA + 13]; + 4934: 8574 ld.b r3, (r5, 0x14) + 4936: a46b st.b r3, (r4, 0xb) + Dbg_Println(DBG_BIT_SYS_STATUS,"fun_enable %d",curr_monitoring.fun_enable); + 4938: 6c9b mov r2, r6 + curr_monitoring.release_strip_bright[PWM_OUT_CH4] = para[PB_FMT_PARA + 14]; + 493a: 8575 ld.b r3, (r5, 0x15) + Dbg_Println(DBG_BIT_SYS_STATUS,"fun_enable %d",curr_monitoring.fun_enable); + 493c: 1129 lrw r1, 0x5cef // 49e0 + 493e: 3000 movi r0, 0 + curr_monitoring.release_strip_bright[PWM_OUT_CH4] = para[PB_FMT_PARA + 14]; + 4940: a46c st.b r3, (r4, 0xc) + Dbg_Println(DBG_BIT_SYS_STATUS,"fun_enable %d",curr_monitoring.fun_enable); + 4942: e3fff333 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"trigger_threshold %dmW",curr_monitoring.trigger_threshold); + 4946: 8c4a ld.h r2, (r4, 0x14) + 4948: 1127 lrw r1, 0x5cfd // 49e4 + 494a: 3000 movi r0, 0 + 494c: e3fff32e bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"trigger_debounce_num %d",curr_monitoring.trigger_debounce_num); + 4950: 844f ld.b r2, (r4, 0xf) + 4952: 1126 lrw r1, 0x5d14 // 49e8 + 4954: 3000 movi r0, 0 + 4956: e3fff329 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_threshold %dmW",curr_monitoring.release_threshold); + 495a: 8c4b ld.h r2, (r4, 0x16) + 495c: 1124 lrw r1, 0x5d2c // 49ec + 495e: 3000 movi r0, 0 + 4960: e3fff324 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_debounce_num %d",curr_monitoring.release_debounce_num); + 4964: 8450 ld.b r2, (r4, 0x10) + 4966: 1123 lrw r1, 0x5d43 // 49f0 + 4968: 3000 movi r0, 0 + 496a: e3fff31f bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"strip_relation %d",curr_monitoring.strip_relation); + 496e: 8444 ld.b r2, (r4, 0x4) + 4970: 1121 lrw r1, 0x5d5b // 49f4 + 4972: 3000 movi r0, 0 + 4974: e3fff31a bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"strip_gradient_time %d",curr_monitoring.strip_gradient_time); + 4978: 8c49 ld.h r2, (r4, 0x12) + 497a: 1120 lrw r1, 0x5d6d // 49f8 + 497c: 3000 movi r0, 0 + 497e: e3fff315 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"triggle_strip_bright CH1 %d",curr_monitoring.triggle_strip_bright[PWM_OUT_CH1]); + 4982: 8445 ld.b r2, (r4, 0x5) + 4984: 103e lrw r1, 0x5d84 // 49fc + 4986: 3000 movi r0, 0 + 4988: e3fff310 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"triggle_strip_bright CH2 %d",curr_monitoring.triggle_strip_bright[PWM_OUT_CH2]); + 498c: 8446 ld.b r2, (r4, 0x6) + 498e: 103d lrw r1, 0x5da0 // 4a00 + 4990: 3000 movi r0, 0 + 4992: e3fff30b bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"triggle_strip_bright CH3 %d",curr_monitoring.triggle_strip_bright[PWM_OUT_CH3]); + 4996: 8447 ld.b r2, (r4, 0x7) + 4998: 103b lrw r1, 0x5dbc // 4a04 + 499a: 3000 movi r0, 0 + 499c: e3fff306 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"triggle_strip_bright CH4 %d",curr_monitoring.triggle_strip_bright[PWM_OUT_CH4]); + 49a0: 8448 ld.b r2, (r4, 0x8) + 49a2: 103a lrw r1, 0x5dd8 // 4a08 + 49a4: 3000 movi r0, 0 + 49a6: e3fff301 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_strip_bright CH1 %d",curr_monitoring.release_strip_bright[PWM_OUT_CH1]); + 49aa: 8449 ld.b r2, (r4, 0x9) + 49ac: 1038 lrw r1, 0x5df4 // 4a0c + 49ae: 3000 movi r0, 0 + 49b0: e3fff2fc bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_strip_bright CH2 %d",curr_monitoring.release_strip_bright[PWM_OUT_CH2]); + 49b4: 844a ld.b r2, (r4, 0xa) + 49b6: 1037 lrw r1, 0x5e10 // 4a10 + 49b8: 3000 movi r0, 0 + 49ba: e3fff2f7 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_strip_bright CH3 %d",curr_monitoring.release_strip_bright[PWM_OUT_CH3]); + 49be: 844b ld.b r2, (r4, 0xb) + 49c0: 1035 lrw r1, 0x5e2c // 4a14 + 49c2: 3000 movi r0, 0 + 49c4: e3fff2f2 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"release_strip_bright CH4 %d",curr_monitoring.release_strip_bright[PWM_OUT_CH4]); + 49c8: 844c ld.b r2, (r4, 0xc) + 49ca: 1034 lrw r1, 0x5e48 // 4a18 + 49cc: 3000 movi r0, 0 + 49ce: e3fff2ed bsr 0x2fa8 // 2fa8 +} + 49d2: 1401 addi r14, r14, 4 + 49d4: 1494 pop r4-r7, r15 + 49d6: 0000 bkpt + 49d8: 20000258 .long 0x20000258 + 49dc: 200006a2 .long 0x200006a2 + 49e0: 00005cef .long 0x00005cef + 49e4: 00005cfd .long 0x00005cfd + 49e8: 00005d14 .long 0x00005d14 + 49ec: 00005d2c .long 0x00005d2c + 49f0: 00005d43 .long 0x00005d43 + 49f4: 00005d5b .long 0x00005d5b + 49f8: 00005d6d .long 0x00005d6d + 49fc: 00005d84 .long 0x00005d84 + 4a00: 00005da0 .long 0x00005da0 + 4a04: 00005dbc .long 0x00005dbc + 4a08: 00005dd8 .long 0x00005dd8 + 4a0c: 00005df4 .long 0x00005df4 + 4a10: 00005e10 .long 0x00005e10 + 4a14: 00005e2c .long 0x00005e2c + 4a18: 00005e48 .long 0x00005e48 + +Disassembly of section .text.BLV_PB_Control_Protocol_Processing: + +00004a1c : +U8_T BLV_PB_Control_Protocol_Processing(U8_T *data,U16_T len){ + 4a1c: 14d3 push r4-r6, r15 + if(data[PB_FMT_ADDR_TX] != 0x00){ + 4a1e: 8060 ld.b r3, (r0, 0x0) + 4a20: 3b40 cmpnei r3, 0 +U8_T BLV_PB_Control_Protocol_Processing(U8_T *data,U16_T len){ + 4a22: 6d03 mov r4, r0 + 4a24: 6d87 mov r6, r1 + if(data[PB_FMT_ADDR_TX] != 0x00){ + 4a26: 0c08 bf 0x4a36 // 4a36 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Tx Addr Error!"); + 4a28: 0320 lrw r1, 0x5e64 // 4ca4 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Rx Addr Error!"); + 4a2a: 3000 movi r0, 0 + 4a2c: e3fff2be bsr 0x2fa8 // 2fa8 + return 0x01; + 4a30: 3501 movi r5, 1 +} + 4a32: 6c17 mov r0, r5 + 4a34: 1493 pop r4-r6, r15 + if(data[PB_FMT_ADDR_RX] != 0x01){ + 4a36: 8063 ld.b r3, (r0, 0x3) + 4a38: 3b41 cmpnei r3, 1 + 4a3a: 0c03 bf 0x4a40 // 4a40 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Rx Addr Error!"); + 4a3c: 0324 lrw r1, 0x5e76 // 4ca8 + 4a3e: 07f6 br 0x4a2a // 4a2a + if(PB_CheckSum(data,len) != 0x00){ + 4a40: e3fff420 bsr 0x3280 // 3280 + 4a44: 3840 cmpnei r0, 0 + 4a46: 6d43 mov r5, r0 + 4a48: 0c03 bf 0x4a4e // 4a4e + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Check Fail!!!!"); + 4a4a: 0326 lrw r1, 0x5e88 // 4cac + 4a4c: 07ef br 0x4a2a // 4a2a + if(data[PB_FMT_LEN] != len){ + 4a4e: 8444 ld.b r2, (r4, 0x4) + 4a50: 649a cmpne r6, r2 + 4a52: 0c07 bf 0x4a60 // 4a60 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Len Fail %d - %d!!!!",data[PB_FMT_LEN],len); + 4a54: 6cdb mov r3, r6 + 4a56: 0328 lrw r1, 0x5e9a // 4cb0 + 4a58: 3000 movi r0, 0 + 4a5a: e3fff2a7 bsr 0x2fa8 // 2fa8 + 4a5e: 07e9 br 0x4a30 // 4a30 + if(data[PB_FMT_DEV_TYPE] != PB_DEV_TYPE){ + 4a60: 8442 ld.b r2, (r4, 0x2) + 4a62: 3330 movi r3, 48 + 4a64: 64ca cmpne r2, r3 + 4a66: 0c07 bf 0x4a74 // 4a74 + Dbg_Println(DBG_BIT_SYS_STATUS, "PB TYPE Fail %d - %d!!!!",data[PB_FMT_DEV_TYPE],PB_DEV_TYPE); + 4a68: 032c lrw r1, 0x5eb2 // 4cb4 + 4a6a: 3000 movi r0, 0 + 4a6c: e3fff29e bsr 0x2fa8 // 2fa8 + return 0x02; + 4a70: 3502 movi r5, 2 + 4a72: 07e0 br 0x4a32 // 4a32 + g_PB.recv_cmd = data[PB_FMT_CMD]; + 4a74: 032e lrw r1, 0x200002f0 // 4cb8 + 4a76: 8466 ld.b r3, (r4, 0x6) + 4a78: a178 st.b r3, (r1, 0x18) + if((data[PB_FMT_TYPE] & 0x0F) != g_PB.recv_sn){ + 4a7a: 8461 ld.b r3, (r4, 0x1) + 4a7c: 300f movi r0, 15 + 4a7e: 8157 ld.b r2, (r1, 0x17) + 4a80: 680c and r0, r3 + 4a82: 640a cmpne r2, r0 + 4a84: 6c87 mov r2, r1 + 4a86: 0d02 bf 0x4c8a // 4c8a + g_PB.recv_sn = data[PB_FMT_TYPE] & 0x0F; + 4a88: a117 st.b r0, (r1, 0x17) + g_PB.recv_addr = data[PB_FMT_ADDR_TX]; + 4a8a: 8460 ld.b r3, (r4, 0x0) + 4a8c: a176 st.b r3, (r1, 0x16) + switch(data[PB_FMT_CMD]){ + 4a8e: 8406 ld.b r0, (r4, 0x6) + 4a90: 281f subi r0, 32 + 4a92: 3333 movi r3, 51 + 4a94: 640c cmphs r3, r0 + 4a96: 0fce bf 0x4a32 // 4a32 + 4a98: e3ffdb98 bsr 0x1c8 // 1c8 <___gnu_csky_case_shi> + 4a9c: 003a0034 .long 0x003a0034 + 4aa0: 00480042 .long 0x00480042 + 4aa4: 0054004e .long 0x0054004e + 4aa8: 0060005a .long 0x0060005a + 4aac: 006d0067 .long 0x006d0067 + 4ab0: ffcb0073 .long 0xffcb0073 + 4ab4: ffcbffcb .long 0xffcbffcb + 4ab8: ffcbffcb .long 0xffcbffcb + 4abc: 007f0079 .long 0x007f0079 + 4ac0: 008b0085 .long 0x008b0085 + 4ac4: 00970091 .long 0x00970091 + 4ac8: 00a3009d .long 0x00a3009d + 4acc: ffcbffcb .long 0xffcbffcb + 4ad0: ffcbffcb .long 0xffcbffcb + 4ad4: ffcbffcb .long 0xffcbffcb + 4ad8: ffcbffcb .long 0xffcbffcb + 4adc: 00af00a9 .long 0x00af00a9 + 4ae0: 00bb00b5 .long 0x00bb00b5 + 4ae4: 00c700c1 .long 0x00c700c1 + 4ae8: 00d300cd .long 0x00d300cd + 4aec: ffcb00d9 .long 0xffcb00d9 + 4af0: ffcbffcb .long 0xffcbffcb + 4af4: ffcbffcb .long 0xffcbffcb + 4af8: ffcbffcb .long 0xffcbffcb + 4afc: 00e500df .long 0x00e500df + 4b00: 00f100eb .long 0x00f100eb + PB_ACK_GET_STATE(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b04: 134e lrw r2, 0x2000069a // 4cbc + 4b06: 132f lrw r1, 0x20000310 // 4cc0 + PB_ACK_GET_STATE(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b08: 6c13 mov r0, r4 + 4b0a: e3fffc5b bsr 0x43c0 // 43c0 + break; + 4b0e: 0406 br 0x4b1a // 4b1a + PB_ACK_SET_LED_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b10: 134b lrw r2, 0x2000069a // 4cbc + 4b12: 132c lrw r1, 0x20000310 // 4cc0 + 4b14: 6c13 mov r0, r4 + 4b16: e3fff50d bsr 0x3530 // 3530 + PB_RS485_ReplyAck(); + 4b1a: e3fff4bb bsr 0x3490 // 3490 + 4b1e: 078a br 0x4a32 // 4a32 + PB_ACK_SET_STRIP_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b20: 1347 lrw r2, 0x2000069a // 4cbc + 4b22: 1328 lrw r1, 0x20000310 // 4cc0 + 4b24: 6c13 mov r0, r4 + 4b26: e3fff551 bsr 0x35c8 // 35c8 + break; + 4b2a: 07f8 br 0x4b1a // 4b1a + PB_ACK_SET_STRIP_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b2c: 1344 lrw r2, 0x2000069a // 4cbc + 4b2e: 1325 lrw r1, 0x20000310 // 4cc0 + 4b30: 6c13 mov r0, r4 + 4b32: e3fff58b bsr 0x3648 // 3648 + break; + 4b36: 07f2 br 0x4b1a // 4b1a + PB_ACK_SET_PIRTIGGLE_LED(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b38: 1341 lrw r2, 0x2000069a // 4cbc + 4b3a: 1322 lrw r1, 0x20000310 // 4cc0 + 4b3c: 6c13 mov r0, r4 + 4b3e: e3fff5b5 bsr 0x36a8 // 36a8 + break; + 4b42: 07ec br 0x4b1a // 4b1a + PB_ACK_SET_CurrTiggleStrip(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b44: 125e lrw r2, 0x2000069a // 4cbc + 4b46: 123f lrw r1, 0x20000310 // 4cc0 + 4b48: 6c13 mov r0, r4 + 4b4a: e3fffeb3 bsr 0x48b0 // 48b0 + break; + 4b4e: 07e6 br 0x4b1a // 4b1a + PB_ACK_SET_SaveCurrInfo(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b50: 125b lrw r2, 0x2000069a // 4cbc + 4b52: 123c lrw r1, 0x20000310 // 4cc0 + 4b54: 6c13 mov r0, r4 + 4b56: e3fff5c5 bsr 0x36e0 // 36e0 + break; + 4b5a: 07e0 br 0x4b1a // 4b1a + *ackLen = 1; + 4b5c: 1278 lrw r3, 0x2000069a // 4cbc + 4b5e: 3101 movi r1, 1 + 4b60: ab20 st.h r1, (r3, 0x0) + ackPara[0] = g_PB.protect_curr; + 4b62: 8255 ld.b r2, (r2, 0x15) + 4b64: 1277 lrw r3, 0x20000310 // 4cc0 + 4b66: a340 st.b r2, (r3, 0x0) + break; + 4b68: 07d9 br 0x4b1a // 4b1a + PB_ACK_SET_UniversPara(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b6a: 1255 lrw r2, 0x2000069a // 4cbc + 4b6c: 1235 lrw r1, 0x20000310 // 4cc0 + 4b6e: 6c13 mov r0, r4 + 4b70: e3fff5ee bsr 0x374c // 374c + break; + 4b74: 07d3 br 0x4b1a // 4b1a + PB_ACK_SET_PowerBus_EnablePara(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b76: 1252 lrw r2, 0x2000069a // 4cbc + 4b78: 1232 lrw r1, 0x20000310 // 4cc0 + 4b7a: 6c13 mov r0, r4 + 4b7c: e3fff65c bsr 0x3834 // 3834 + break; + 4b80: 07cd br 0x4b1a // 4b1a + PB_ACK_PassThroug_Data(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b82: 124f lrw r2, 0x2000069a // 4cbc + 4b84: 122f lrw r1, 0x20000310 // 4cc0 + 4b86: 6c13 mov r0, r4 + 4b88: e3fff680 bsr 0x3888 // 3888 + break; + 4b8c: 07c7 br 0x4b1a // 4b1a + PB_ACK_SET_PB_LEDS_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b8e: 124c lrw r2, 0x2000069a // 4cbc + 4b90: 122c lrw r1, 0x20000310 // 4cc0 + 4b92: 6c13 mov r0, r4 + 4b94: e3fff698 bsr 0x38c4 // 38c4 + break; + 4b98: 07c1 br 0x4b1a // 4b1a + PB_ACK_SET_PB_LEDS_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4b9a: 1249 lrw r2, 0x2000069a // 4cbc + 4b9c: 1229 lrw r1, 0x20000310 // 4cc0 + 4b9e: 6c13 mov r0, r4 + 4ba0: e3fff6b2 bsr 0x3904 // 3904 + break; + 4ba4: 07bb br 0x4b1a // 4b1a + PB_ACK_SET_PB_LEDS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4ba6: 1246 lrw r2, 0x2000069a // 4cbc + 4ba8: 1226 lrw r1, 0x20000310 // 4cc0 + 4baa: 6c13 mov r0, r4 + 4bac: e3fff6cc bsr 0x3944 // 3944 + break; + 4bb0: 07b5 br 0x4b1a // 4b1a + PB_ACK_SET_PB_LEDS_BRIGHT(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bb2: 1243 lrw r2, 0x2000069a // 4cbc + 4bb4: 1223 lrw r1, 0x20000310 // 4cc0 + 4bb6: 6c13 mov r0, r4 + 4bb8: e3fff6e6 bsr 0x3984 // 3984 + break; + 4bbc: 07af br 0x4b1a // 4b1a + PB_ACK_SET_PB_LED_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bbe: 1240 lrw r2, 0x2000069a // 4cbc + 4bc0: 1220 lrw r1, 0x20000310 // 4cc0 + 4bc2: 6c13 mov r0, r4 + 4bc4: e3fff740 bsr 0x3a44 // 3a44 + break; + 4bc8: 07a9 br 0x4b1a // 4b1a + PB_ACK_SET_PB_LED_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bca: 115d lrw r2, 0x2000069a // 4cbc + 4bcc: 113d lrw r1, 0x20000310 // 4cc0 + 4bce: 6c13 mov r0, r4 + 4bd0: e3fff6fa bsr 0x39c4 // 39c4 + break; + 4bd4: 07a3 br 0x4b1a // 4b1a + PB_ACK_SET_PB_LED_Adjust(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bd6: 115a lrw r2, 0x2000069a // 4cbc + 4bd8: 113a lrw r1, 0x20000310 // 4cc0 + 4bda: 6c13 mov r0, r4 + 4bdc: e3fff714 bsr 0x3a04 // 3a04 + break; + 4be0: 079d br 0x4b1a // 4b1a + PB_ACK_SET_PB_ALLLED_Switch(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4be2: 1157 lrw r2, 0x2000069a // 4cbc + 4be4: 1137 lrw r1, 0x20000310 // 4cc0 + 4be6: 6c13 mov r0, r4 + 4be8: e3fff74e bsr 0x3a84 // 3a84 + break; + 4bec: 0797 br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIPS_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bee: 1154 lrw r2, 0x2000069a // 4cbc + 4bf0: 1134 lrw r1, 0x20000310 // 4cc0 + 4bf2: 6c13 mov r0, r4 + 4bf4: e3fff768 bsr 0x3ac4 // 3ac4 + break; + 4bf8: 0791 br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIPS_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4bfa: 1151 lrw r2, 0x2000069a // 4cbc + 4bfc: 1131 lrw r1, 0x20000310 // 4cc0 + 4bfe: 6c13 mov r0, r4 + 4c00: e3fff818 bsr 0x3c30 // 3c30 + break; + 4c04: 078b br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIPS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c06: 114e lrw r2, 0x2000069a // 4cbc + 4c08: 112e lrw r1, 0x20000310 // 4cc0 + 4c0a: 6c13 mov r0, r4 + 4c0c: e3fff8b8 bsr 0x3d7c // 3d7c + break; + 4c10: 0785 br 0x4b1a // 4b1a + PB_ACK_SET_PB_ALLSTRIP_Switch(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c12: 114b lrw r2, 0x2000069a // 4cbc + 4c14: 112b lrw r1, 0x20000310 // 4cc0 + 4c16: 6c13 mov r0, r4 + 4c18: e3fffb04 bsr 0x4220 // 4220 + break; + 4c1c: 077f br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIP_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c1e: 1148 lrw r2, 0x2000069a // 4cbc + 4c20: 1128 lrw r1, 0x20000310 // 4cc0 + 4c22: 6c13 mov r0, r4 + 4c24: e3fff9d2 bsr 0x3fc8 // 3fc8 + break; + 4c28: 0779 br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIP_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c2a: 1145 lrw r2, 0x2000069a // 4cbc + 4c2c: 1125 lrw r1, 0x20000310 // 4cc0 + 4c2e: 6c13 mov r0, r4 + 4c30: e3fff9ee bsr 0x400c // 400c + break; + 4c34: 0773 br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIP_Adjust(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c36: 1142 lrw r2, 0x2000069a // 4cbc + 4c38: 1122 lrw r1, 0x20000310 // 4cc0 + 4c3a: 6c13 mov r0, r4 + 4c3c: e3fffa08 bsr 0x404c // 404c + break; + 4c40: 076d br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c42: 105f lrw r2, 0x2000069a // 4cbc + 4c44: 103f lrw r1, 0x20000310 // 4cc0 + 4c46: 6c13 mov r0, r4 + 4c48: e3fffa24 bsr 0x4090 // 4090 + break; + 4c4c: 0767 br 0x4b1a // 4b1a + PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c4e: 105c lrw r2, 0x2000069a // 4cbc + 4c50: 103c lrw r1, 0x20000310 // 4cc0 + 4c52: 6c13 mov r0, r4 + 4c54: e3fffac4 bsr 0x41dc // 41dc + break; + 4c58: 0761 br 0x4b1a // 4b1a + PB_ACK_SET_PB_RELAYS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c5a: 1059 lrw r2, 0x2000069a // 4cbc + 4c5c: 1039 lrw r1, 0x20000310 // 4cc0 + 4c5e: 6c13 mov r0, r4 + 4c60: e3fffb02 bsr 0x4264 // 4264 + break; + 4c64: 075b br 0x4b1a // 4b1a + PB_ACK_SET_PB_ALLRELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c66: 1056 lrw r2, 0x2000069a // 4cbc + 4c68: 1036 lrw r1, 0x20000310 // 4cc0 + 4c6a: 6c13 mov r0, r4 + 4c6c: e3fffb1e bsr 0x42a8 // 42a8 + break; + 4c70: 0755 br 0x4b1a // 4b1a + PB_ACK_SET_PB_RELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c72: 1053 lrw r2, 0x2000069a // 4cbc + 4c74: 1033 lrw r1, 0x20000310 // 4cc0 + 4c76: 6c13 mov r0, r4 + 4c78: e3fffb3a bsr 0x42ec // 42ec + break; + 4c7c: 074f br 0x4b1a // 4b1a + PB_ACK_SET_PB_RELAY_DELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c7e: 1050 lrw r2, 0x2000069a // 4cbc + 4c80: 1030 lrw r1, 0x20000310 // 4cc0 + 4c82: 6c13 mov r0, r4 + 4c84: e3fffb56 bsr 0x4330 // 4330 + break; + 4c88: 0749 br 0x4b1a // 4b1a + }else if((data[PB_FMT_TYPE] & 0x40) == 0x40){ + 4c8a: 3240 movi r2, 64 + 4c8c: 68c8 and r3, r2 + 4c8e: 3b40 cmpnei r3, 0 + 4c90: 0ed1 bf 0x4a32 // 4a32 + switch(data[PB_FMT_CMD]){ + 4c92: 8446 ld.b r2, (r4, 0x6) + 4c94: 3320 movi r3, 32 + 4c96: 64ca cmpne r2, r3 + 4c98: 0b41 bt 0x4b1a // 4b1a + PB_ACK_GET_STATE(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + 4c9a: 104b lrw r2, 0x3aa // 4cc4 + 4c9c: 6084 addu r2, r1 + 4c9e: 211f addi r1, 32 + 4ca0: 0734 br 0x4b08 // 4b08 + 4ca2: 0000 bkpt + 4ca4: 00005e64 .long 0x00005e64 + 4ca8: 00005e76 .long 0x00005e76 + 4cac: 00005e88 .long 0x00005e88 + 4cb0: 00005e9a .long 0x00005e9a + 4cb4: 00005eb2 .long 0x00005eb2 + 4cb8: 200002f0 .long 0x200002f0 + 4cbc: 2000069a .long 0x2000069a + 4cc0: 20000310 .long 0x20000310 + 4cc4: 000003aa .long 0x000003aa + +Disassembly of section .text.PB_Task: + +00004cc8 : + +void PB_Task(void){ + 4cc8: 14d0 push r15 + PB_Soft_Boot_Task(); + 4cca: e3fff1cd bsr 0x3064 // 3064 + + PB_Protect_Task(); + 4cce: e3fff2f7 bsr 0x32bc // 32bc + + PowerBus_SendBuffer_Task(); + 4cd2: e3fffdaf bsr 0x4830 // 4830 + + PMU_MEAS_Task(); + 4cd6: e3fffcad bsr 0x4630 // 4630 +} + 4cda: 1490 pop r15 + +Disassembly of section .text.PWM_SetOutDuty: + +00004cdc : + * @brief 设置PWM通道输出亮度 + * @para + * index: 设置通道 0~3 + * val: 输出值 PWM_OUT_VAL_MIN ~ PWM_OUT_VAL_MAX + */ +void PWM_SetOutDuty(U8_T index,U16_T val){ + 4cdc: 14d0 push r15 + U16_T temp_val = 0; + if(val > PWM_OUT_VAL_MAX) return; + 4cde: 106a lrw r3, 0xbb8 // 4d04 + 4ce0: 644c cmphs r3, r1 + 4ce2: 0c0a bf 0x4cf6 // 4cf6 + + //temp_val = PWM_OUT_VAL_MAX - val; + temp_val = val; + switch(index){ + 4ce4: 3803 cmphsi r0, 4 + 4ce6: 0808 bt 0x4cf6 // 4cf6 + 4ce8: 1068 lrw r3, 0x20000020 // 4d08 + break; + case PWM_OUT_CH3: + EPT0->CMPC=temp_val; + break; + case PWM_OUT_CH4: + EPT0->CMPD=temp_val; + 4cea: 9360 ld.w r3, (r3, 0x0) + switch(index){ + 4cec: e3ffda64 bsr 0x1b4 // 1b4 <___gnu_csky_case_uqi> + 4cf0: 08060402 .long 0x08060402 + EPT0->CMPA=temp_val; + 4cf4: b32b st.w r1, (r3, 0x2c) + break; + } +} + 4cf6: 1490 pop r15 + EPT0->CMPB=temp_val; + 4cf8: b32c st.w r1, (r3, 0x30) + 4cfa: 07fe br 0x4cf6 // 4cf6 + EPT0->CMPC=temp_val; + 4cfc: b32d st.w r1, (r3, 0x34) + 4cfe: 07fc br 0x4cf6 // 4cf6 + EPT0->CMPD=temp_val; + 4d00: b32e st.w r1, (r3, 0x38) + 4d02: 07fa br 0x4cf6 // 4cf6 + 4d04: 00000bb8 .long 0x00000bb8 + 4d08: 20000020 .long 0x20000020 + +Disassembly of section .text.PWM_SetCHGradualTime: + +00004d0c : + * @para + * index: 设置通道 0~3 + * val: 渐变时间 单位：ms + */ +void PWM_SetCHGradualTime(U8_T index, U16_T val){ + if(index >= PWM_OUT_CH_MAX) return ; + 4d0c: 3803 cmphsi r0, 4 + 4d0e: 0805 bt 0x4d18 // 4d18 + + g_pwm.gradualTime[index] = val; + 4d10: 4001 lsli r0, r0, 1 + 4d12: 1063 lrw r3, 0x20000740 // 4d1c + 4d14: 600c addu r0, r3 + 4d16: a820 st.h r1, (r0, 0x0) +} + 4d18: 783c jmp r15 + 4d1a: 0000 bkpt + 4d1c: 20000740 .long 0x20000740 + +Disassembly of section .text.PWM_SetOutBrightness: + +00004d20 : + * @brief 设置PWM 通道输出亮度 + * @para + * index: 设置通道 0~3 + * brightness：设置亮度 0~100 + */ +void PWM_SetOutBrightness(U8_T index, U8_T brightness){ + 4d20: 14d4 push r4-r7, r15 + 4d22: 1421 subi r14, r14, 4 + U32_T tempPwmVal = 0; + + if(brightness != 0x00){ + 4d24: 3940 cmpnei r1, 0 +void PWM_SetOutBrightness(U8_T index, U8_T brightness){ + 4d26: 6d03 mov r4, r0 + 4d28: 11b8 lrw r5, 0x20000718 // 4e08 + if(brightness != 0x00){ + 4d2a: 0c0a bf 0x4d3e // 4d3e + if(brightness >= g_pwm.allBrightnessUpLimit) { + 4d2c: 8562 ld.b r3, (r5, 0x2) + 4d2e: 64c4 cmphs r1, r3 + 4d30: 082d bt 0x4d8a // 4d8a + 4d32: 8543 ld.b r2, (r5, 0x3) + 4d34: 6448 cmphs r2, r1 + 4d36: 6ccb mov r3, r2 + 4d38: 0802 bt 0x4d3c // 4d3c + 4d3a: 6cc7 mov r3, r1 + 4d3c: 744c zextb r1, r3 + }else if(brightness <= g_pwm.allBrightnessDownLimit){ + brightness = g_pwm.allBrightnessDownLimit; + } + } + + g_pwm.irqEnable = FALSE; + 4d3e: 3300 movi r3, 0 + 4d40: a560 st.b r3, (r5, 0x0) + + g_pwmAutoAdj.enable[index] = FALSE; + 4d42: 3200 movi r2, 0 + 4d44: 1172 lrw r3, 0x20000768 // 4e0c + 4d46: 60d0 addu r3, r4 + 4d48: a340 st.b r2, (r3, 0x0) + g_pwm.controlFlag[index] = TRUE; + 4d4a: 5dd0 addu r6, r5, r4 + 4d4c: 3301 movi r3, 1 + 4d4e: a66c st.b r3, (r6, 0xc) + g_pwm.brightnessCurr[index] = brightness; + //当前PWM值 = PWM调节最大值 * 全局亮度百分比 * 当前亮度百分比 * 开关状态 + tempPwmVal = ((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.brightnessCurr[index]) * g_pwm.switchState[index])/10000; + 4d50: 8501 ld.b r0, (r5, 0x1) + 4d52: 1170 lrw r3, 0xbb8 // 4e10 + 4d54: 7c0c mult r0, r3 + g_pwm.brightnessCurr[index] = brightness; + 4d56: a624 st.b r1, (r6, 0x4) + tempPwmVal = ((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.brightnessCurr[index]) * g_pwm.switchState[index])/10000; + 4d58: 7c40 mult r1, r0 + 4d5a: 8608 ld.b r0, (r6, 0x8) + 4d5c: 7c04 mult r0, r1 + 4d5e: 112e lrw r1, 0x2710 // 4e14 + 4d60: e3fff068 bsr 0x2e30 // 2e30 <__divsi3> + g_pwm.pwmValTarget[index] = tempPwmVal; + 4d64: 3310 movi r3, 16 + 4d66: 60d0 addu r3, r4 + 4d68: 4361 lsli r3, r3, 1 + + if(g_pwm.pwmValTarget[index] == g_pwm.pwmValCurr[index]){ + 4d6a: 310c movi r1, 12 + g_pwm.pwmValTarget[index] = tempPwmVal; + 4d6c: 75c1 zexth r7, r0 + 4d6e: 60d4 addu r3, r5 + if(g_pwm.pwmValTarget[index] == g_pwm.pwmValCurr[index]){ + 4d70: 6050 addu r1, r4 + g_pwm.pwmValTarget[index] = tempPwmVal; + 4d72: abe0 st.h r7, (r3, 0x0) + if(g_pwm.pwmValTarget[index] == g_pwm.pwmValCurr[index]){ + 4d74: 4161 lsli r3, r1, 1 + 4d76: 60d4 addu r3, r5 + 4d78: 8b40 ld.h r2, (r3, 0x0) + 4d7a: 649e cmpne r7, r2 + 4d7c: 0809 bt 0x4d8e // 4d8e + g_pwm.addOrDecFlag[index] = PWMA_Nochange; + 4d7e: 3302 movi r3, 2 + 4d80: a670 st.b r3, (r6, 0x10) + g_pwm.pwmStep[index] = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + } + } + //Dbg_Println(DBG_BIT_SYS_STATUS,"PWM%d Step - %f",index,g_pwm.pwmStep[index]); + + g_pwm.irqEnable = TRUE; + 4d82: 3301 movi r3, 1 + 4d84: a560 st.b r3, (r5, 0x0) +} + 4d86: 1401 addi r14, r14, 4 + 4d88: 1494 pop r4-r7, r15 + 4d8a: 6c4f mov r1, r3 + 4d8c: 07d9 br 0x4d3e // 4d3e + }else if(g_pwm.pwmValTarget[index] > g_pwm.pwmValCurr[index]){ + 4d8e: 65c8 cmphs r2, r7 + 4d90: 0823 bt 0x4dd6 // 4dd6 + if(g_pwm.gradualTime[index] != 0x00){ + 4d92: 2413 addi r4, 20 + 4d94: 4481 lsli r4, r4, 1 + g_pwm.addOrDecFlag[index] = PWMA_Ascending; + 4d96: 3301 movi r3, 1 + if(g_pwm.gradualTime[index] != 0x00){ + 4d98: 6114 addu r4, r5 + g_pwm.addOrDecFlag[index] = PWMA_Ascending; + 4d9a: a670 st.b r3, (r6, 0x10) + 4d9c: 4010 lsli r0, r0, 16 + if(g_pwm.gradualTime[index] != 0x00){ + 4d9e: 8c60 ld.h r3, (r4, 0x0) + tempPwmVal = g_pwm.pwmValTarget[index] - g_pwm.pwmValCurr[index]; + 4da0: 4810 lsri r0, r0, 16 + 4da2: 4182 lsli r4, r1, 2 + if(g_pwm.gradualTime[index] != 0x00){ + 4da4: 3b40 cmpnei r3, 0 + 4da6: b860 st.w r3, (r14, 0x0) + g_pwm.pwmStep[index] = ((float)tempPwmVal*1.0 / g_pwm.gradualTime[index]); + 4da8: 6114 addu r4, r5 + tempPwmVal = g_pwm.pwmValTarget[index] - g_pwm.pwmValCurr[index]; + 4daa: 600a subu r0, r2 + if(g_pwm.gradualTime[index] != 0x00){ + 4dac: 0c2a bf 0x4e00 // 4e00 + g_pwm.pwmStep[index] = ((float)tempPwmVal*1.0 / g_pwm.gradualTime[index]); + 4dae: e3ffdbaf bsr 0x50c // 50c <__floatunsisf> + 4db2: e3ffdb9b bsr 0x4e8 // 4e8 <__extendsfdf2> + 4db6: 9860 ld.w r3, (r14, 0x0) + 4db8: 6dc3 mov r7, r0 + 4dba: 6c0f mov r0, r3 + 4dbc: 6d87 mov r6, r1 + 4dbe: e3ffdc81 bsr 0x6c0 // 6c0 <__floatsidf> + 4dc2: 6c83 mov r2, r0 + 4dc4: 6cc7 mov r3, r1 + 4dc6: 6c1f mov r0, r7 + 4dc8: 6c5b mov r1, r6 + 4dca: e3ffdbd1 bsr 0x56c // 56c <__divdf3> + 4dce: e3ffdcc5 bsr 0x758 // 758 <__truncdfsf2> + g_pwm.pwmStep[index] = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + 4dd2: b400 st.w r0, (r4, 0x0) + 4dd4: 07d7 br 0x4d82 // 4d82 + }else if(g_pwm.pwmValTarget[index] < g_pwm.pwmValCurr[index]){ + 4dd6: 649c cmphs r7, r2 + 4dd8: 0bd5 bt 0x4d82 // 4d82 + g_pwm.addOrDecFlag[index] = PWMA_Decreasing; + 4dda: 3300 movi r3, 0 + 4ddc: a670 st.b r3, (r6, 0x10) + if(g_pwm.gradualTime[index] != 0x00){ + 4dde: 6cd3 mov r3, r4 + 4de0: 2313 addi r3, 20 + 4de2: 4361 lsli r3, r3, 1 + 4de4: 60d4 addu r3, r5 + 4de6: 8b60 ld.h r3, (r3, 0x0) + 4de8: 3b40 cmpnei r3, 0 + 4dea: 4182 lsli r4, r1, 2 + 4dec: 4010 lsli r0, r0, 16 + 4dee: 0c06 bf 0x4dfa // 4dfa + tempPwmVal = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + 4df0: 4810 lsri r0, r0, 16 + 4df2: b860 st.w r3, (r14, 0x0) + g_pwm.pwmStep[index] = ((float)tempPwmVal*1.0 / g_pwm.gradualTime[index]); + 4df4: 6114 addu r4, r5 + tempPwmVal = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + 4df6: 5a01 subu r0, r2, r0 + 4df8: 07db br 0x4dae // 4dae + g_pwm.pwmStep[index] = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + 4dfa: 4810 lsri r0, r0, 16 + 4dfc: 6114 addu r4, r5 + 4dfe: 5a01 subu r0, r2, r0 + 4e00: e3ffdb18 bsr 0x430 // 430 <__floatsisf> + 4e04: 07e7 br 0x4dd2 // 4dd2 + 4e06: 0000 bkpt + 4e08: 20000718 .long 0x20000718 + 4e0c: 20000768 .long 0x20000768 + 4e10: 00000bb8 .long 0x00000bb8 + 4e14: 00002710 .long 0x00002710 + +Disassembly of section .text.PWM_Init: + +00004e18 : +void PWM_Init(void){ + 4e18: 14d4 push r4-r7, r15 + memset(&g_pwm,0,sizeof(PWM_CONTROL_T)); + 4e1a: 128a lrw r4, 0x20000718 // 4f40 + 4e1c: 3250 movi r2, 80 + 4e1e: 3100 movi r1, 0 + 4e20: 6c13 mov r0, r4 + 4e22: e3ffdee9 bsr 0xbf4 // bf4 <__memset_fast> + g_pwm.allBrightness = g_eeprom.allBrightness; + 4e26: 12a8 lrw r5, 0x200007a4 // 4f44 + memset(&g_pwmAutoAdj,0,sizeof(PWM_AUTO_ADJUST_T)); + 4e28: 323c movi r2, 60 + 4e2a: 3100 movi r1, 0 + 4e2c: 1207 lrw r0, 0x20000768 // 4f48 + 4e2e: e3ffdee3 bsr 0xbf4 // bf4 <__memset_fast> + g_pwm.switchState[PWM_OUT_CH1] = g_eeprom.swithcState[PWM_OUT_CH1]; + 4e32: 8565 ld.b r3, (r5, 0x5) + 4e34: a468 st.b r3, (r4, 0x8) + g_pwm.switchState[PWM_OUT_CH2] = g_eeprom.swithcState[PWM_OUT_CH2]; + 4e36: 8566 ld.b r3, (r5, 0x6) + 4e38: a469 st.b r3, (r4, 0x9) + g_pwm.switchState[PWM_OUT_CH3] = g_eeprom.swithcState[PWM_OUT_CH3]; + 4e3a: 8567 ld.b r3, (r5, 0x7) + 4e3c: a46a st.b r3, (r4, 0xa) + g_pwm.switchState[PWM_OUT_CH4] = g_eeprom.swithcState[PWM_OUT_CH4]; + 4e3e: 8568 ld.b r3, (r5, 0x8) + 4e40: a46b st.b r3, (r4, 0xb) + g_pwm.gradualTime[PWM_OUT_CH1] = g_eeprom.gradialTime[PWM_OUT_CH1]; + 4e42: 8d67 ld.h r3, (r5, 0xe) + 4e44: ac74 st.h r3, (r4, 0x28) + g_pwm.gradualTime[PWM_OUT_CH2] = g_eeprom.gradialTime[PWM_OUT_CH2]; + 4e46: 8d68 ld.h r3, (r5, 0x10) + 4e48: ac75 st.h r3, (r4, 0x2a) + g_pwm.gradualTime[PWM_OUT_CH3] = g_eeprom.gradialTime[PWM_OUT_CH3]; + 4e4a: 8d69 ld.h r3, (r5, 0x12) + 4e4c: ac76 st.h r3, (r4, 0x2c) + g_pwm.gradualTime[PWM_OUT_CH4] = g_eeprom.gradialTime[PWM_OUT_CH4]; + 4e4e: 8d6a ld.h r3, (r5, 0x14) + 4e50: ac77 st.h r3, (r4, 0x2e) + g_pwm.irqEnable = TRUE; + 4e52: 3301 movi r3, 1 + g_pwm.allBrightness = g_eeprom.allBrightness; + 4e54: 85c2 ld.b r6, (r5, 0x2) + g_pwm.irqEnable = TRUE; + 4e56: a460 st.b r3, (r4, 0x0) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + 4e58: 117d lrw r3, 0xbb8 // 4f4c + g_pwm.allBrightnessUpLimit = g_eeprom.allBrightnessUpLimit; + 4e5a: 8503 ld.b r0, (r5, 0x3) + g_pwm.allBrightnessDownLimit = g_eeprom.allBrightnessDownLimit; + 4e5c: 85e4 ld.b r7, (r5, 0x4) + g_pwm.allBrightness = g_eeprom.allBrightness; + 4e5e: a4c1 st.b r6, (r4, 0x1) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + 4e60: 7d8c mult r6, r3 + g_pwm.allBrightnessUpLimit = g_eeprom.allBrightnessUpLimit; + 4e62: a402 st.b r0, (r4, 0x2) + g_pwm.allBrightnessDownLimit = g_eeprom.allBrightnessDownLimit; + 4e64: a4e3 st.b r7, (r4, 0x3) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + 4e66: 7c18 mult r0, r6 + 4e68: 113a lrw r1, 0x2710 // 4f50 + 4e6a: e3ffeff5 bsr 0x2e54 // 2e54 <__udivsi3> + g_pwm.allPwmUpLimit = temp_val; + 4e6e: ac0a st.h r0, (r4, 0x14) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessDownLimit))/10000; + 4e70: 6c1f mov r0, r7 + 4e72: 7c18 mult r0, r6 + 4e74: 1137 lrw r1, 0x2710 // 4f50 + 4e76: e3ffefef bsr 0x2e54 // 2e54 <__udivsi3> + g_pwm.allPwmDownLimit = temp_val; + 4e7a: ac0b st.h r0, (r4, 0x16) + PWM_SetOutBrightness(PWM_OUT_CH1,g_eeprom.brightness[PWM_OUT_CH1]); + 4e7c: 8529 ld.b r1, (r5, 0x9) + 4e7e: 3000 movi r0, 0 + 4e80: e3ffff50 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2,g_eeprom.brightness[PWM_OUT_CH2]); + 4e84: 852a ld.b r1, (r5, 0xa) + 4e86: 3001 movi r0, 1 + 4e88: e3ffff4c bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3,g_eeprom.brightness[PWM_OUT_CH3]); + 4e8c: 852b ld.b r1, (r5, 0xb) + 4e8e: 3002 movi r0, 2 + 4e90: e3ffff48 bsr 0x4d20 // 4d20 + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightness %d",g_pwm.allBrightness); + 4e94: 11d0 lrw r6, 0x6055 // 4f54 + PWM_SetOutBrightness(PWM_OUT_CH4,g_eeprom.brightness[PWM_OUT_CH4]); + 4e96: 852c ld.b r1, (r5, 0xc) + 4e98: 3003 movi r0, 3 + 4e9a: e3ffff43 bsr 0x4d20 // 4d20 + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightness %d",g_pwm.allBrightness); + 4e9e: 8441 ld.b r2, (r4, 0x1) + 4ea0: 6c5b mov r1, r6 + 4ea2: 3000 movi r0, 0 + 4ea4: e3fff082 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightnessUpLimit %d",g_pwm.allBrightnessUpLimit); + 4ea8: 8442 ld.b r2, (r4, 0x2) + 4eaa: 112c lrw r1, 0x6070 // 4f58 + 4eac: 3000 movi r0, 0 + 4eae: e3fff07d bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightnessDownLimit %d",g_pwm.allBrightnessDownLimit); + 4eb2: 8443 ld.b r2, (r4, 0x3) + 4eb4: 112a lrw r1, 0x6092 // 4f5c + 4eb6: 3000 movi r0, 0 + 4eb8: e3fff078 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightness %d",g_pwm.allBrightness); + 4ebc: 8441 ld.b r2, (r4, 0x1) + 4ebe: 6c5b mov r1, r6 + 4ec0: 3000 movi r0, 0 + 4ec2: e3fff073 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH1] %d",g_pwm.switchState[PWM_OUT_CH1]); + 4ec6: 8448 ld.b r2, (r4, 0x8) + 4ec8: 1126 lrw r1, 0x5ecb // 4f60 + 4eca: 3000 movi r0, 0 + 4ecc: e3fff06e bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH2] %d",g_pwm.switchState[PWM_OUT_CH2]); + 4ed0: 8449 ld.b r2, (r4, 0x9) + 4ed2: 1125 lrw r1, 0x5ee7 // 4f64 + 4ed4: 3000 movi r0, 0 + 4ed6: e3fff069 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH3] %d",g_pwm.switchState[PWM_OUT_CH3]); + 4eda: 844a ld.b r2, (r4, 0xa) + 4edc: 1123 lrw r1, 0x5f03 // 4f68 + 4ede: 3000 movi r0, 0 + 4ee0: e3fff064 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH4] %d",g_pwm.switchState[PWM_OUT_CH4]); + 4ee4: 844b ld.b r2, (r4, 0xb) + 4ee6: 1122 lrw r1, 0x5f1f // 4f6c + 4ee8: 3000 movi r0, 0 + 4eea: e3fff05f bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH1] %d",g_pwm.gradualTime[PWM_OUT_CH1]); + 4eee: 8c54 ld.h r2, (r4, 0x28) + 4ef0: 1120 lrw r1, 0x5f3b // 4f70 + 4ef2: 3000 movi r0, 0 + 4ef4: e3fff05a bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH2] %d",g_pwm.gradualTime[PWM_OUT_CH2]); + 4ef8: 8c55 ld.h r2, (r4, 0x2a) + 4efa: 103f lrw r1, 0x5f57 // 4f74 + 4efc: 3000 movi r0, 0 + 4efe: e3fff055 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH3] %d",g_pwm.gradualTime[PWM_OUT_CH3]); + 4f02: 8c56 ld.h r2, (r4, 0x2c) + 4f04: 103d lrw r1, 0x5f73 // 4f78 + 4f06: 3000 movi r0, 0 + 4f08: e3fff050 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH4] %d",g_pwm.gradualTime[PWM_OUT_CH4]); + 4f0c: 8c57 ld.h r2, (r4, 0x2e) + 4f0e: 103c lrw r1, 0x5f8f // 4f7c + 4f10: 3000 movi r0, 0 + 4f12: e3fff04b bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH1] %d",g_eeprom.brightness[PWM_OUT_CH1]); + 4f16: 8549 ld.b r2, (r5, 0x9) + 4f18: 103a lrw r1, 0x5fab // 4f80 + 4f1a: 3000 movi r0, 0 + 4f1c: e3fff046 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH2] %d",g_eeprom.brightness[PWM_OUT_CH2]); + 4f20: 854a ld.b r2, (r5, 0xa) + 4f22: 1039 lrw r1, 0x5fc6 // 4f84 + 4f24: 3000 movi r0, 0 + 4f26: e3fff041 bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH3] %d",g_eeprom.brightness[PWM_OUT_CH3]); + 4f2a: 854b ld.b r2, (r5, 0xb) + 4f2c: 1037 lrw r1, 0x5fe1 // 4f88 + 4f2e: 3000 movi r0, 0 + 4f30: e3fff03c bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH4] %d",g_eeprom.brightness[PWM_OUT_CH4]); + 4f34: 854c ld.b r2, (r5, 0xc) + 4f36: 1036 lrw r1, 0x5ffc // 4f8c + 4f38: 3000 movi r0, 0 + 4f3a: e3fff037 bsr 0x2fa8 // 2fa8 +} + 4f3e: 1494 pop r4-r7, r15 + 4f40: 20000718 .long 0x20000718 + 4f44: 200007a4 .long 0x200007a4 + 4f48: 20000768 .long 0x20000768 + 4f4c: 00000bb8 .long 0x00000bb8 + 4f50: 00002710 .long 0x00002710 + 4f54: 00006055 .long 0x00006055 + 4f58: 00006070 .long 0x00006070 + 4f5c: 00006092 .long 0x00006092 + 4f60: 00005ecb .long 0x00005ecb + 4f64: 00005ee7 .long 0x00005ee7 + 4f68: 00005f03 .long 0x00005f03 + 4f6c: 00005f1f .long 0x00005f1f + 4f70: 00005f3b .long 0x00005f3b + 4f74: 00005f57 .long 0x00005f57 + 4f78: 00005f73 .long 0x00005f73 + 4f7c: 00005f8f .long 0x00005f8f + 4f80: 00005fab .long 0x00005fab + 4f84: 00005fc6 .long 0x00005fc6 + 4f88: 00005fe1 .long 0x00005fe1 + 4f8c: 00005ffc .long 0x00005ffc + +Disassembly of section .text.PWM_SetUpLimitVal: + +00004f90 : +{ + 4f90: 14d1 push r4, r15 + g_pwm.allBrightnessUpLimit = val; + 4f92: 108e lrw r4, 0x20000718 // 4fc8 + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + 4f94: 104e lrw r2, 0xbb8 // 4fcc + 4f96: 8461 ld.b r3, (r4, 0x1) + 4f98: 7cc8 mult r3, r2 + g_pwm.allBrightnessUpLimit = val; + 4f9a: a402 st.b r0, (r4, 0x2) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + 4f9c: 102d lrw r1, 0x2710 // 4fd0 + 4f9e: 7c0c mult r0, r3 + 4fa0: e3ffef5a bsr 0x2e54 // 2e54 <__udivsi3> + g_pwm.allPwmUpLimit = temp_val; + 4fa4: ac0a st.h r0, (r4, 0x14) + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + 4fa6: 8424 ld.b r1, (r4, 0x4) + 4fa8: 3000 movi r0, 0 + 4faa: e3fffebb bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + 4fae: 8425 ld.b r1, (r4, 0x5) + 4fb0: 3001 movi r0, 1 + 4fb2: e3fffeb7 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + 4fb6: 8426 ld.b r1, (r4, 0x6) + 4fb8: 3002 movi r0, 2 + 4fba: e3fffeb3 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); + 4fbe: 8427 ld.b r1, (r4, 0x7) + 4fc0: 3003 movi r0, 3 + 4fc2: e3fffeaf bsr 0x4d20 // 4d20 +} + 4fc6: 1491 pop r4, r15 + 4fc8: 20000718 .long 0x20000718 + 4fcc: 00000bb8 .long 0x00000bb8 + 4fd0: 00002710 .long 0x00002710 + +Disassembly of section .text.PWM_SetDownLimitVal: + +00004fd4 : +{ + 4fd4: 14d1 push r4, r15 + g_pwm.allBrightnessDownLimit = val; + 4fd6: 108e lrw r4, 0x20000718 // 500c + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessDownLimit))/10000; + 4fd8: 104e lrw r2, 0xbb8 // 5010 + 4fda: 8461 ld.b r3, (r4, 0x1) + 4fdc: 7cc8 mult r3, r2 + g_pwm.allBrightnessDownLimit = val; + 4fde: a403 st.b r0, (r4, 0x3) + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessDownLimit))/10000; + 4fe0: 102d lrw r1, 0x2710 // 5014 + 4fe2: 7c0c mult r0, r3 + 4fe4: e3ffef38 bsr 0x2e54 // 2e54 <__udivsi3> + g_pwm.allPwmDownLimit = temp_val; + 4fe8: ac0b st.h r0, (r4, 0x16) + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + 4fea: 8424 ld.b r1, (r4, 0x4) + 4fec: 3000 movi r0, 0 + 4fee: e3fffe99 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + 4ff2: 8425 ld.b r1, (r4, 0x5) + 4ff4: 3001 movi r0, 1 + 4ff6: e3fffe95 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + 4ffa: 8426 ld.b r1, (r4, 0x6) + 4ffc: 3002 movi r0, 2 + 4ffe: e3fffe91 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); + 5002: 8427 ld.b r1, (r4, 0x7) + 5004: 3003 movi r0, 3 + 5006: e3fffe8d bsr 0x4d20 // 4d20 +} + 500a: 1491 pop r4, r15 + 500c: 20000718 .long 0x20000718 + 5010: 00000bb8 .long 0x00000bb8 + 5014: 00002710 .long 0x00002710 + +Disassembly of section .text.Pwm_SetOnOffState: + +00005018 : +{ + 5018: 14d0 push r15 + if(index >= PWM_OUT_CH_MAX) return ; + 501a: 3803 cmphsi r0, 4 + 501c: 0807 bt 0x502a // 502a + g_pwm.switchState[index] = state; + 501e: 1064 lrw r3, 0x20000718 // 502c + 5020: 60c0 addu r3, r0 + 5022: a328 st.b r1, (r3, 0x8) + PWM_SetOutBrightness(index, g_pwm.brightnessCurr[index]); + 5024: 8324 ld.b r1, (r3, 0x4) + 5026: e3fffe7d bsr 0x4d20 // 4d20 +} + 502a: 1490 pop r15 + 502c: 20000718 .long 0x20000718 + +Disassembly of section .text.Pwm_SetAllBrightness: + +00005030 : +{ + 5030: 14d1 push r4, r15 + g_pwm.allBrightness = val; + 5032: 108a lrw r4, 0x20000718 // 5058 + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + 5034: 8424 ld.b r1, (r4, 0x4) + g_pwm.allBrightness = val; + 5036: a401 st.b r0, (r4, 0x1) + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + 5038: 3000 movi r0, 0 + 503a: e3fffe73 bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + 503e: 8425 ld.b r1, (r4, 0x5) + 5040: 3001 movi r0, 1 + 5042: e3fffe6f bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + 5046: 8426 ld.b r1, (r4, 0x6) + 5048: 3002 movi r0, 2 + 504a: e3fffe6b bsr 0x4d20 // 4d20 + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); + 504e: 8427 ld.b r1, (r4, 0x7) + 5050: 3003 movi r0, 3 + 5052: e3fffe67 bsr 0x4d20 // 4d20 +} + 5056: 1491 pop r4, r15 + 5058: 20000718 .long 0x20000718 + +Disassembly of section .text.PWM_SetAutoAdjust: + +0000505c : + * index: 设置通道 0~3 + * mode： 自动调光模式 0x00:调节到顶端停止 0x01:循环调节 0x02:停止调节 + * adj： 调节方向 0x00:递减 0x01:递增 0x02:与上次命令相反 + * adj_time：调节时间 亮度0~100的调节时间，单位：ms + */ +void PWM_SetAutoAdjust(U8_T index,U8_T mode,U8_T adj,U16_T adj_time){ + 505c: 14d4 push r4-r7, r15 + 505e: 1423 subi r14, r14, 12 + 5060: 6d03 mov r4, r0 + g_pwm.irqEnable = FALSE; + 5062: 11a8 lrw r5, 0x20000718 // 5100 + 5064: 3000 movi r0, 0 + 5066: a500 st.b r0, (r5, 0x0) + g_pwmAutoAdj.enable[index] = TRUE; + 5068: 3701 movi r7, 1 + 506a: 1107 lrw r0, 0x20000768 // 5104 + 506c: 58d0 addu r6, r0, r4 + + if(mode == 0x02){ + 506e: 3942 cmpnei r1, 2 + g_pwmAutoAdj.enable[index] = TRUE; + 5070: a6e0 st.b r7, (r6, 0x0) + 5072: b800 st.w r0, (r14, 0x0) + if(mode == 0x02){ + 5074: 0839 bt 0x50e6 // 50e6 + g_pwmAutoAdj.enable[index] = FALSE; //停止自动调节 + + g_pwm.brightnessCurr[index] = (g_pwm.pwmValCurr[index] * 100) / PWM_OUT_VAL_MAX; //同步一下当前亮度 + 5076: 370c movi r7, 12 + 5078: 61d0 addu r7, r4 + 507a: 47e1 lsli r7, r7, 1 + 507c: b862 st.w r3, (r14, 0x8) + 507e: 61d4 addu r7, r5 + g_pwmAutoAdj.enable[index] = FALSE; //停止自动调节 + 5080: 3300 movi r3, 0 + 5082: a660 st.b r3, (r6, 0x0) + g_pwm.brightnessCurr[index] = (g_pwm.pwmValCurr[index] * 100) / PWM_OUT_VAL_MAX; //同步一下当前亮度 + 5084: 311e movi r1, 30 + 5086: 8f00 ld.h r0, (r7, 0x0) + 5088: b841 st.w r2, (r14, 0x4) + 508a: e3ffeed3 bsr 0x2e30 // 2e30 <__divsi3> + 508e: 5d30 addu r1, r5, r4 + 5090: a104 st.b r0, (r1, 0x4) + + if(g_pwm.switchState[index] == 0x00){ + 5092: 8108 ld.b r0, (r1, 0x8) + 5094: 3840 cmpnei r0, 0 + 5096: 9841 ld.w r2, (r14, 0x4) + 5098: 9862 ld.w r3, (r14, 0x8) + 509a: 0808 bt 0x50aa // 50aa + //如果当前回路状态为关，当前输出PWM也应为0 + g_pwm.pwmValCurr[index] = 0; + 509c: 3100 movi r1, 0 + 509e: af20 st.h r1, (r7, 0x0) + g_pwm.pwmFloatValCurr[index] = 0; + 50a0: 3110 movi r1, 16 + 50a2: 6050 addu r1, r4 + 50a4: 4122 lsli r1, r1, 2 + 50a6: 6054 addu r1, r5 + 50a8: b100 st.w r0, (r1, 0x0) + } + }else{ + g_pwmAutoAdj.adjMode[index] = mode; + } + + if(adj == 0x02){ + 50aa: 3a42 cmpnei r2, 2 + 50ac: 081f bt 0x50ea // 50ea + if(g_pwmAutoAdj.adjDir[index] == 0x01){ + 50ae: 8648 ld.b r2, (r6, 0x8) + g_pwmAutoAdj.adjDir[index] = 0x00; + 50b0: 3a41 cmpnei r2, 1 + 50b2: 3200 movi r2, 0 + 50b4: 6089 addc r2, r2 + 50b6: 2402 addi r4, 3 + g_pwmAutoAdj.adjDir[index] = adj; + }else{ + g_pwmAutoAdj.adjDir[index] = 0x00; + } + + if(adj_time != 0x00){ + 50b8: 3b40 cmpnei r3, 0 + g_pwmAutoAdj.adjDir[index] = 0x00; + 50ba: a648 st.b r2, (r6, 0x8) + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / adj_time); + 50bc: 4482 lsli r4, r4, 2 + if(adj_time != 0x00){ + 50be: 0c1a bf 0x50f2 // 50f2 + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / adj_time); + 50c0: 9840 ld.w r2, (r14, 0x0) + 50c2: 6090 addu r2, r4 + 50c4: 6c0f mov r0, r3 + 50c6: 6d0b mov r4, r2 + 50c8: e3ffdafc bsr 0x6c0 // 6c0 <__floatsidf> + 50cc: 6c83 mov r2, r0 + 50ce: 6cc7 mov r3, r1 + 50d0: 3000 movi r0, 0 + 50d2: 102e lrw r1, 0x40a77000 // 5108 + 50d4: e3ffda4c bsr 0x56c // 56c <__divdf3> + 50d8: e3ffdb40 bsr 0x758 // 758 <__truncdfsf2> + 50dc: b400 st.w r0, (r4, 0x0) + //循环调光时间最短为100ms + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / 100); + } + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Adjust PWM%d Step - %f",index,g_pwmAutoAdj.pwmStep[index]); + g_pwm.irqEnable = TRUE; + 50de: 3301 movi r3, 1 + 50e0: a560 st.b r3, (r5, 0x0) +} + 50e2: 1403 addi r14, r14, 12 + 50e4: 1494 pop r4-r7, r15 + g_pwmAutoAdj.adjMode[index] = mode; + 50e6: a624 st.b r1, (r6, 0x4) + 50e8: 07e1 br 0x50aa // 50aa + }else if(adj < 0x02){ + 50ea: 3a01 cmphsi r2, 2 + 50ec: 0fe5 bf 0x50b6 // 50b6 + g_pwmAutoAdj.adjDir[index] = 0x00; + 50ee: 3200 movi r2, 0 + 50f0: 07e3 br 0x50b6 // 50b6 + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / 100); + 50f2: 9860 ld.w r3, (r14, 0x0) + 50f4: 60d0 addu r3, r4 + 50f6: 6d0f mov r4, r3 + 50f8: 1065 lrw r3, 0x41f00000 // 510c + 50fa: b460 st.w r3, (r4, 0x0) + 50fc: 07f1 br 0x50de // 50de + 50fe: 0000 bkpt + 5100: 20000718 .long 0x20000718 + 5104: 20000768 .long 0x20000768 + 5108: 40a77000 .long 0x40a77000 + 510c: 41f00000 .long 0x41f00000 + +Disassembly of section .text.PWM_Timer_1ms_Task: + +00005110 : + +void PWM_Timer_Disable(void){ + g_pwm.irqEnable = FALSE; +} + +void PWM_Timer_1ms_Task(void){ + 5110: 14d4 push r4-r7, r15 + 5112: 1426 subi r14, r14, 24 + U8_T index = 0; + float temp_float_val = 0; + + if(g_pwm.irqEnable == TRUE){ + 5114: 1366 lrw r3, 0x20000718 // 52ac + 5116: 8340 ld.b r2, (r3, 0x0) + 5118: 3a41 cmpnei r2, 1 + 511a: b861 st.w r3, (r14, 0x4) + 511c: 088b bt 0x5232 // 5232 + 511e: 1365 lrw r3, 0x20000768 // 52b0 + 5120: b863 st.w r3, (r14, 0xc) + 5122: 98a1 ld.w r5, (r14, 0x4) + 5124: b860 st.w r3, (r14, 0x0) + 5126: 3300 movi r3, 0 + 5128: 6dd7 mov r7, r5 + 512a: 6d17 mov r4, r5 + 512c: b862 st.w r3, (r14, 0x8) + for(index = 0;index < PWM_OUT_CH_MAX; index++){ + if(g_pwmAutoAdj.enable[index] == FALSE){ + 512e: 9860 ld.w r3, (r14, 0x0) + 5130: 8360 ld.b r3, (r3, 0x0) + 5132: 3b40 cmpnei r3, 0 + 5134: 084a bt 0x51c8 // 51c8 + + //调节至指定亮度 + if(g_pwm.controlFlag[index] == TRUE){ + 5136: 876c ld.b r3, (r7, 0xc) + 5138: 3b41 cmpnei r3, 1 + 513a: 086c bt 0x5212 // 5212 + //当前PWM输出通道，需要进行调节 + if(g_pwm.gradualTime[index] != 0x00){ + 513c: 8d74 ld.h r3, (r5, 0x28) + 513e: 3b40 cmpnei r3, 0 + 5140: 0c42 bf 0x51c4 // 51c4 + if(g_pwm.addOrDecFlag[index] == PWMA_Ascending){ + 5142: 87d0 ld.b r6, (r7, 0x10) + 5144: 3e41 cmpnei r6, 1 + 5146: 0822 bt 0x518a // 518a + + //PWM递增 - 防止溢出 + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwm.pwmStep[index]; + 5148: 942c ld.w r1, (r4, 0x30) + 514a: 9410 ld.w r0, (r4, 0x40) + 514c: e3ffd90a bsr 0x360 // 360 <__addsf3> + if(temp_float_val <= PWM_OUT_VAL_MAX){ + 5150: 1239 lrw r1, 0x453b8000 // 52b4 + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwm.pwmStep[index]; + 5152: 6d83 mov r6, r0 + if(temp_float_val <= PWM_OUT_VAL_MAX){ + 5154: e3ffd952 bsr 0x3f8 // 3f8 <__lesf2> + 5158: 3820 cmplti r0, 1 + 515a: 0c15 bf 0x5184 // 5184 + g_pwm.pwmFloatValCurr[index] = temp_float_val; + 515c: b4d0 st.w r6, (r4, 0x40) + }else{ + g_pwm.pwmFloatValCurr[index] = PWM_OUT_VAL_MAX; + } + + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + 515e: 9410 ld.w r0, (r4, 0x40) + 5160: e3ffd842 bsr 0x1e4 // 1e4 <__fixunssfsi> + 5164: 74c1 zexth r3, r0 + //调节至目标值，便停止调节 + if(g_pwm.pwmValCurr[index] >= g_pwm.pwmValTarget[index]){ + 5166: 8d10 ld.h r0, (r5, 0x20) + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + 5168: ad6c st.h r3, (r5, 0x18) + if(g_pwm.pwmValCurr[index] >= g_pwm.pwmValTarget[index]){ + 516a: 640c cmphs r3, r0 + g_pwm.pwmFloatValCurr[index] = 0x00; + } + + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + //调节至目标值，便停止调节 + if(g_pwm.pwmValCurr[index] <= g_pwm.pwmValTarget[index]){ + 516c: 0c07 bf 0x517a // 517a + g_pwm.controlFlag[index] = FALSE; + //Dbg_Println(DBG_BIT_Debug_STATUS,"controlFlag 3 %d ",index); + } + }else { + //渐变时间为0，直接设置当前通道的PWM值 + g_pwm.pwmValCurr[index] = g_pwm.pwmValTarget[index]; + 516e: ad0c st.h r0, (r5, 0x18) + g_pwm.pwmFloatValCurr[index] = g_pwm.pwmValCurr[index]; + 5170: e3ffd9ce bsr 0x50c // 50c <__floatunsisf> + 5174: b410 st.w r0, (r4, 0x40) + g_pwm.controlFlag[index] = FALSE; + 5176: 3300 movi r3, 0 + 5178: a76c st.b r3, (r7, 0xc) + } + + //Dbg_Println(DBG_BIT_SYS_STATUS,"PWM%d %d %f %f",index,g_pwm.pwmValCurr[index],g_pwm.pwmStep[index],g_pwm.pwmFloatValCurr[index]); + //设置通道的PWM输出的值 + PWM_SetOutDuty(index,g_pwm.pwmValCurr[index]); + 517a: 8d2c ld.h r1, (r5, 0x18) + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + + //设置通道的PWM输出的值 + if(g_pwm.switchState[index] != 0x00){ + + PWM_SetOutDuty(index,g_pwm.pwmValCurr[index]); + 517c: 9802 ld.w r0, (r14, 0x8) + 517e: e3fffdaf bsr 0x4cdc // 4cdc + 5182: 0448 br 0x5212 // 5212 + g_pwm.pwmFloatValCurr[index] = PWM_OUT_VAL_MAX; + 5184: 126c lrw r3, 0x453b8000 // 52b4 + 5186: b470 st.w r3, (r4, 0x40) + 5188: 07eb br 0x515e // 515e + }else if(g_pwm.addOrDecFlag[index] == PWMA_Decreasing){ + 518a: 3e40 cmpnei r6, 0 + 518c: 0bf5 bt 0x5176 // 5176 + if(g_pwm.pwmFloatValCurr[index] >= g_pwm.pwmStep[index]){ + 518e: 9450 ld.w r2, (r4, 0x40) + 5190: 946c ld.w r3, (r4, 0x30) + 5192: 6c4f mov r1, r3 + 5194: 6c0b mov r0, r2 + 5196: b865 st.w r3, (r14, 0x14) + 5198: b844 st.w r2, (r14, 0x10) + 519a: e3ffd913 bsr 0x3c0 // 3c0 <__gesf2> + 519e: 38df btsti r0, 31 + 51a0: 0810 bt 0x51c0 // 51c0 + g_pwm.pwmFloatValCurr[index] -= g_pwm.pwmStep[index]; + 51a2: 9865 ld.w r3, (r14, 0x14) + 51a4: 9844 ld.w r2, (r14, 0x10) + 51a6: 6c4f mov r1, r3 + 51a8: 6c0b mov r0, r2 + 51aa: e3ffd8f1 bsr 0x38c // 38c <__subsf3> + 51ae: b410 st.w r0, (r4, 0x40) + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + 51b0: 9410 ld.w r0, (r4, 0x40) + 51b2: e3ffd819 bsr 0x1e4 // 1e4 <__fixunssfsi> + 51b6: 74c1 zexth r3, r0 + if(g_pwm.pwmValCurr[index] <= g_pwm.pwmValTarget[index]){ + 51b8: 8d10 ld.h r0, (r5, 0x20) + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + 51ba: ad6c st.h r3, (r5, 0x18) + if(g_pwm.pwmValCurr[index] <= g_pwm.pwmValTarget[index]){ + 51bc: 64c0 cmphs r0, r3 + 51be: 07d7 br 0x516c // 516c + g_pwm.pwmFloatValCurr[index] = 0x00; + 51c0: b4d0 st.w r6, (r4, 0x40) + 51c2: 07f7 br 0x51b0 // 51b0 + g_pwm.pwmValCurr[index] = g_pwm.pwmValTarget[index]; + 51c4: 8d10 ld.h r0, (r5, 0x20) + 51c6: 07d4 br 0x516e // 516e + if(g_pwmAutoAdj.adjDir[index] == 0x00){ + 51c8: 9860 ld.w r3, (r14, 0x0) + 51ca: 8368 ld.b r3, (r3, 0x8) + 51cc: 3b40 cmpnei r3, 0 + 51ce: 0846 bt 0x525a // 525a + if((g_pwm.pwmFloatValCurr[index] >= g_pwmAutoAdj.pwmStep[index]) && (g_pwm.pwmFloatValCurr[index] >= (float)g_pwm.allPwmDownLimit) ){ + 51d0: 9863 ld.w r3, (r14, 0xc) + 51d2: 9363 ld.w r3, (r3, 0xc) + 51d4: 94d0 ld.w r6, (r4, 0x40) + 51d6: 6c4f mov r1, r3 + 51d8: 6c1b mov r0, r6 + 51da: b864 st.w r3, (r14, 0x10) + 51dc: e3ffd8f2 bsr 0x3c0 // 3c0 <__gesf2> + 51e0: 38df btsti r0, 31 + 51e2: 082a bt 0x5236 // 5236 + 51e4: 9861 ld.w r3, (r14, 0x4) + 51e6: 8b0b ld.h r0, (r3, 0x16) + 51e8: e3ffd992 bsr 0x50c // 50c <__floatunsisf> + 51ec: 6c43 mov r1, r0 + 51ee: 6c1b mov r0, r6 + 51f0: e3ffd8e8 bsr 0x3c0 // 3c0 <__gesf2> + 51f4: 38df btsti r0, 31 + 51f6: 0820 bt 0x5236 // 5236 + g_pwm.pwmFloatValCurr[index] -= g_pwmAutoAdj.pwmStep[index]; + 51f8: 9824 ld.w r1, (r14, 0x10) + 51fa: 6c1b mov r0, r6 + 51fc: e3ffd8c8 bsr 0x38c // 38c <__subsf3> + 5200: b410 st.w r0, (r4, 0x40) + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + 5202: 9410 ld.w r0, (r4, 0x40) + 5204: e3ffd7f0 bsr 0x1e4 // 1e4 <__fixunssfsi> + 5208: 7441 zexth r1, r0 + 520a: ad2c st.h r1, (r5, 0x18) + if(g_pwm.switchState[index] != 0x00){ + 520c: 8768 ld.b r3, (r7, 0x8) + 520e: 3b40 cmpnei r3, 0 + 5210: 0bb6 bt 0x517c // 517c + for(index = 0;index < PWM_OUT_CH_MAX; index++){ + 5212: 9862 ld.w r3, (r14, 0x8) + 5214: 2300 addi r3, 1 + 5216: 74cc zextb r3, r3 + 5218: b862 st.w r3, (r14, 0x8) + 521a: 9860 ld.w r3, (r14, 0x0) + 521c: 2300 addi r3, 1 + 521e: b860 st.w r3, (r14, 0x0) + 5220: 9863 ld.w r3, (r14, 0xc) + 5222: 2303 addi r3, 4 + 5224: b863 st.w r3, (r14, 0xc) + 5226: 9862 ld.w r3, (r14, 0x8) + 5228: 3b44 cmpnei r3, 4 + 522a: 2501 addi r5, 2 + 522c: 2403 addi r4, 4 + 522e: 2700 addi r7, 1 + 5230: 0b7f bt 0x512e // 512e + + } + + } + } +} + 5232: 1406 addi r14, r14, 24 + 5234: 1494 pop r4-r7, r15 + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmDownLimit; + 5236: 9861 ld.w r3, (r14, 0x4) + 5238: 8bcb ld.h r6, (r3, 0x16) + 523a: 6c1b mov r0, r6 + 523c: e3ffd968 bsr 0x50c // 50c <__floatunsisf> + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + 5240: 9860 ld.w r3, (r14, 0x0) + 5242: 8364 ld.b r3, (r3, 0x4) + 5244: 3b41 cmpnei r3, 1 + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmDownLimit; + 5246: b410 st.w r0, (r4, 0x40) + g_pwmAutoAdj.adjDir[index] = 0x01; + 5248: 9860 ld.w r3, (r14, 0x0) + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + 524a: 0804 bt 0x5252 // 5252 + g_pwmAutoAdj.adjDir[index] = 0x01; + 524c: 3201 movi r2, 1 + g_pwmAutoAdj.adjDir[index] = 0x00; + 524e: a348 st.b r2, (r3, 0x8) + 5250: 07d9 br 0x5202 // 5202 + g_pwmAutoAdj.enable[index] = FALSE; //自动调节完毕 + 5252: 3200 movi r2, 0 + g_pwmAutoAdj.enable[index] = FALSE; //自动调节完毕 + 5254: a340 st.b r2, (r3, 0x0) + g_pwm.brightnessCurr[index] = g_pwm.allPwmUpLimit; //同步一下当前亮度 + 5256: a7c4 st.b r6, (r7, 0x4) + 5258: 07d5 br 0x5202 // 5202 + }else if(g_pwmAutoAdj.adjDir[index] == 0x01){ + 525a: 3b41 cmpnei r3, 1 + 525c: 0bd3 bt 0x5202 // 5202 + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwmAutoAdj.pwmStep[index]; + 525e: 9470 ld.w r3, (r4, 0x40) + 5260: b864 st.w r3, (r14, 0x10) + 5262: 9863 ld.w r3, (r14, 0xc) + 5264: 9323 ld.w r1, (r3, 0xc) + 5266: 9804 ld.w r0, (r14, 0x10) + 5268: e3ffd87c bsr 0x360 // 360 <__addsf3> + if( (temp_float_val <= PWM_OUT_VAL_MAX) && (g_pwm.pwmFloatValCurr[index] <= (float)g_pwm.allPwmUpLimit) ){ + 526c: 1032 lrw r1, 0x453b8000 // 52b4 + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwmAutoAdj.pwmStep[index]; + 526e: 6d83 mov r6, r0 + if( (temp_float_val <= PWM_OUT_VAL_MAX) && (g_pwm.pwmFloatValCurr[index] <= (float)g_pwm.allPwmUpLimit) ){ + 5270: e3ffd8c4 bsr 0x3f8 // 3f8 <__lesf2> + 5274: 3820 cmplti r0, 1 + 5276: 0c0d bf 0x5290 // 5290 + 5278: 9861 ld.w r3, (r14, 0x4) + 527a: 8b0a ld.h r0, (r3, 0x14) + 527c: e3ffd948 bsr 0x50c // 50c <__floatunsisf> + 5280: 6c43 mov r1, r0 + 5282: 9804 ld.w r0, (r14, 0x10) + 5284: e3ffd8ba bsr 0x3f8 // 3f8 <__lesf2> + 5288: 3820 cmplti r0, 1 + 528a: 0c03 bf 0x5290 // 5290 + g_pwm.pwmFloatValCurr[index] = temp_float_val; + 528c: b4d0 st.w r6, (r4, 0x40) + 528e: 07ba br 0x5202 // 5202 + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmUpLimit; + 5290: 9861 ld.w r3, (r14, 0x4) + 5292: 8bca ld.h r6, (r3, 0x14) + 5294: 6c1b mov r0, r6 + 5296: e3ffd93b bsr 0x50c // 50c <__floatunsisf> + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + 529a: 9860 ld.w r3, (r14, 0x0) + 529c: 8364 ld.b r3, (r3, 0x4) + 529e: 3b41 cmpnei r3, 1 + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmUpLimit; + 52a0: b410 st.w r0, (r4, 0x40) + g_pwmAutoAdj.adjDir[index] = 0x00; + 52a2: 9860 ld.w r3, (r14, 0x0) + 52a4: 3200 movi r2, 0 + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + 52a6: 0bd7 bt 0x5254 // 5254 + 52a8: 07d3 br 0x524e // 524e + 52aa: 0000 bkpt + 52ac: 20000718 .long 0x20000718 + 52b0: 20000768 .long 0x20000768 + 52b4: 453b8000 .long 0x453b8000 + +Disassembly of section .text.EEPROM_ReadParaInfo: + +000052b8 : + + EEPROM_Validate_ParaInfo(&g_eeprom); +} + + +U8_T EEPROM_ReadParaInfo(E_PARA_INFO *info){ + 52b8: 14d1 push r4, r15 + 52ba: 143b subi r14, r14, 108 + 52bc: 6d03 mov r4, r0 + U8_T read_info[6]; + U8_T para_data[EEPROM_DATA_Size_Max]; + U16_T read_len = 0; + + memset(read_info,0,sizeof(read_info)); + 52be: 3300 movi r3, 0 + memset(para_data,0,sizeof(para_data)); + 52c0: 3264 movi r2, 100 + 52c2: 3100 movi r1, 0 + 52c4: 1802 addi r0, r14, 8 + memset(read_info,0,sizeof(read_info)); + 52c6: b860 st.w r3, (r14, 0x0) + 52c8: dc6e1002 st.h r3, (r14, 0x4) + memset(para_data,0,sizeof(para_data)); + 52cc: e3ffdc94 bsr 0xbf4 // bf4 <__memset_fast> + + ReadDataArry_U8(EEPROM_ParaInfo_Address,4,read_info); + 52d0: 6cbb mov r2, r14 + 52d2: 3104 movi r1, 4 + 52d4: 1014 lrw r0, 0x10000020 // 5324 + 52d6: e3ffe6b1 bsr 0x2038 // 2038 + + if(read_info[0] == EEPROM_SVAE_FLAG){ + 52da: d84e0000 ld.b r2, (r14, 0x0) + 52de: 33a6 movi r3, 166 + 52e0: 64ca cmpne r2, r3 + 52e2: 0c04 bf 0x52ea // 52ea + return 0x00; + } + } + } + + return 0x01; + 52e4: 3001 movi r0, 1 +} + 52e6: 141b addi r14, r14, 108 + 52e8: 1491 pop r4, r15 + read_len |= read_info[1]; + 52ea: d82e0002 ld.b r1, (r14, 0x2) + 52ee: d86e0001 ld.b r3, (r14, 0x1) + 52f2: 4128 lsli r1, r1, 8 + 52f4: 6c4c or r1, r3 + if(read_len <= EEPROM_DATA_Size_Max){ + 52f6: 3364 movi r3, 100 + 52f8: 644c cmphs r3, r1 + 52fa: 0ff5 bf 0x52e4 // 52e4 + ReadDataArry_U8(EEPROM_ParaInfo_Address+4,read_len,para_data); + 52fc: 1a02 addi r2, r14, 8 + 52fe: 100b lrw r0, 0x10000024 // 5328 + 5300: e3ffe69c bsr 0x2038 // 2038 + if(PB_CheckSum(para_data,sizeof(E_PARA_INFO)) == read_info[3]){ + 5304: 3116 movi r1, 22 + 5306: 1802 addi r0, r14, 8 + 5308: e3ffefbc bsr 0x3280 // 3280 + 530c: d86e0003 ld.b r3, (r14, 0x3) + 5310: 640e cmpne r3, r0 + 5312: 0be9 bt 0x52e4 // 52e4 + memcpy((uint8_t *)info,para_data,sizeof(E_PARA_INFO)); + 5314: 3216 movi r2, 22 + 5316: 1902 addi r1, r14, 8 + 5318: 6c13 mov r0, r4 + 531a: e3ffdcb1 bsr 0xc7c // c7c <__memcpy_fast> + return 0x00; + 531e: 3000 movi r0, 0 + 5320: 07e3 br 0x52e6 // 52e6 + 5322: 0000 bkpt + 5324: 10000020 .long 0x10000020 + 5328: 10000024 .long 0x10000024 + +Disassembly of section .text.EEPROM_WriteParaInfo: + +0000532c : + +U8_T EEPROM_WriteParaInfo(E_PARA_INFO *info){ + 532c: 14d0 push r15 + 532e: 143b subi r14, r14, 108 + U8_T save_data[EEPROM_DATA_Size_Max + 6]; + U16_T save_len = sizeof(E_PARA_INFO); + + if(save_len >= EEPROM_DATA_Size_Max) save_len = EEPROM_DATA_Size_Max; + + save_data[0] = EEPROM_SVAE_FLAG; + 5330: 3300 movi r3, 0 + 5332: 2b59 subi r3, 90 + 5334: dc6e0000 st.b r3, (r14, 0x0) + save_data[1] = save_len & 0xFF; + 5338: 3316 movi r3, 22 + 533a: dc6e0001 st.b r3, (r14, 0x1) + save_data[2] = (save_len >> 8) & 0xFF; + 533e: 3300 movi r3, 0 + 5340: dc6e0002 st.b r3, (r14, 0x2) + + memcpy(&save_data[4],(uint8_t *)info,save_len); + 5344: 1b01 addi r3, r14, 4 +U8_T EEPROM_WriteParaInfo(E_PARA_INFO *info){ + 5346: 6c43 mov r1, r0 + memcpy(&save_data[4],(uint8_t *)info,save_len); + 5348: 3216 movi r2, 22 + 534a: 6c0f mov r0, r3 + 534c: e3ffdc98 bsr 0xc7c // c7c <__memcpy_fast> + + save_data[3] = PB_CheckSum(&save_data[4],save_len); + 5350: 3116 movi r1, 22 + 5352: e3ffef97 bsr 0x3280 // 3280 + 5356: dc0e0003 st.b r0, (r14, 0x3) + + save_len+=4; + + Page_ProgramData(EEPROM_ParaInfo_Address,save_len,save_data); + 535a: 6cbb mov r2, r14 + 535c: 311a movi r1, 26 + 535e: 1004 lrw r0, 0x10000020 // 536c + 5360: e3ffe61c bsr 0x1f98 // 1f98 + + return 0; +} + 5364: 3000 movi r0, 0 + 5366: 141b addi r14, r14, 108 + 5368: 1490 pop r15 + 536a: 0000 bkpt + 536c: 10000020 .long 0x10000020 + +Disassembly of section .text.EEPROM_Validate_ParaInfo: + +00005370 : + Page_ProgramData(EEPROM_ParaInfo_Address,save_len,save_data); + + return 0; +} + +U8_T EEPROM_Validate_ParaInfo(E_PARA_INFO *info){ + 5370: 14d3 push r4-r6, r15 + 5372: 1421 subi r14, r14, 4 + U8_T i=0; + + //以下为本地参数 + + //PowerBus 总线开关 0x01:开启，0x02:关闭 + if((info->powerbus_enable < 0x01) || (info->powerbus_enable > 0x01) ){ + 5374: 8060 ld.b r3, (r0, 0x0) + 5376: 3b41 cmpnei r3, 1 +U8_T EEPROM_Validate_ParaInfo(E_PARA_INFO *info){ + 5378: 6d03 mov r4, r0 + if((info->powerbus_enable < 0x01) || (info->powerbus_enable > 0x01) ){ + 537a: 0c03 bf 0x5380 // 5380 + info->powerbus_enable = EEPROM_ParaDefault_PowerBusEnable; //默认开启 + 537c: 3301 movi r3, 1 + 537e: a060 st.b r3, (r0, 0x0) + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info powerbus_enable %d",info->powerbus_enable); + 5380: 8440 ld.b r2, (r4, 0x0) + 5382: 1127 lrw r1, 0x6017 // 541c + 5384: 3000 movi r0, 0 + 5386: e3ffee11 bsr 0x2fa8 // 2fa8 + + //PowerBus 总线保护电流范围：1~165 单位：0.1A 1V = 5A + //因为 BLV_C8_V05 硬件版本目前芯片供电为3.3V,提供给保护阈值电压最高为3.3V,所以保护电流最高为16.5A + if((info->save_curr < PB_SaveCurrent_Min) || (info->save_curr > PB_SaveCurrent_Max)){ + 538a: 8461 ld.b r3, (r4, 0x1) + 538c: 2b00 subi r3, 1 + 538e: 74cc zextb r3, r3 + 5390: 32a4 movi r2, 164 + 5392: 64c8 cmphs r2, r3 + 5394: 0803 bt 0x539a // 539a + info->save_curr = EEPROM_ParaDefault_SaveCurr; //默认保护电流为10A + 5396: 3378 movi r3, 120 + 5398: a461 st.b r3, (r4, 0x1) + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info save_curr %d",info->save_curr); + 539a: 8441 ld.b r2, (r4, 0x1) + 539c: 1121 lrw r1, 0x6034 // 5420 + 539e: 3000 movi r0, 0 + 53a0: e3ffee04 bsr 0x2fa8 // 2fa8 + + + //以下为灯光参数校验 + + //全局亮度有效范围：0~100 + if(info->allBrightness > BRIGHTNESS_MAX){ + 53a4: 8442 ld.b r2, (r4, 0x2) + 53a6: 3364 movi r3, 100 + 53a8: 648c cmphs r3, r2 + 53aa: 0802 bt 0x53ae // 53ae + info->allBrightness = BRIGHTNESS_MAX; //全局亮度默认：100 + 53ac: a462 st.b r3, (r4, 0x2) + } + + //全局亮度可调上限有效范围：0~100 + if(info->allBrightnessUpLimit > BRIGHTNESS_MAX){ + 53ae: 8443 ld.b r2, (r4, 0x3) + 53b0: 3364 movi r3, 100 + 53b2: 648c cmphs r3, r2 + 53b4: 0802 bt 0x53b8 // 53b8 + info->allBrightnessUpLimit = BRIGHTNESS_MAX; //全局亮度可调上限默认：100 + 53b6: a463 st.b r3, (r4, 0x3) + } + + //全局亮度可调下限有效范围：0~100 + if(info->allBrightnessDownLimit > BRIGHTNESS_MAX){ + 53b8: 8444 ld.b r2, (r4, 0x4) + 53ba: 3364 movi r3, 100 + 53bc: 648c cmphs r3, r2 + 53be: 0803 bt 0x53c4 // 53c4 + info->allBrightnessDownLimit = BRIGHTNESS_MIN; //全局亮度可调下限默认：0 + 53c0: 3300 movi r3, 0 + 53c2: a464 st.b r3, (r4, 0x4) + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightness %d",info->allBrightness); + 53c4: 8442 ld.b r2, (r4, 0x2) + 53c6: 1038 lrw r1, 0x604b // 5424 + 53c8: 3000 movi r0, 0 + 53ca: e3ffedef bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightnessUpLimit %d",info->allBrightnessUpLimit); + 53ce: 8443 ld.b r2, (r4, 0x3) + 53d0: 1036 lrw r1, 0x6066 // 5428 + 53d2: 3000 movi r0, 0 + 53d4: e3ffedea bsr 0x2fa8 // 2fa8 + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightnessDownLimit %d",info->allBrightnessDownLimit); + 53d8: 8444 ld.b r2, (r4, 0x4) + 53da: 1035 lrw r1, 0x6088 // 542c + 53dc: 3000 movi r0, 0 + 53de: e3ffede5 bsr 0x2fa8 // 2fa8 + 53e2: 2404 addi r4, 5 + 53e4: 3500 movi r5, 0 + //回路亮度：0~100 + if(info->brightness[i] > BRIGHTNESS_MAX){ + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Light Loop%d %d-%d",i,info->swithcState[i],info->brightness[i]); + 53e6: 10d3 lrw r6, 0x60ac // 5430 + if(info->swithcState[i] > 0x01){ + 53e8: 8460 ld.b r3, (r4, 0x0) + 53ea: 3b01 cmphsi r3, 2 + 53ec: 0c03 bf 0x53f2 // 53f2 + info->swithcState[i] = 0x01; //回路开关状态默认：0x01 + 53ee: 3301 movi r3, 1 + 53f0: a460 st.b r3, (r4, 0x0) + if(info->brightness[i] > BRIGHTNESS_MAX){ + 53f2: 8444 ld.b r2, (r4, 0x4) + 53f4: 3364 movi r3, 100 + 53f6: 648c cmphs r3, r2 + 53f8: 0803 bt 0x53fe // 53fe + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + 53fa: 3300 movi r3, 0 + 53fc: a464 st.b r3, (r4, 0x4) + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Light Loop%d %d-%d",i,info->swithcState[i],info->brightness[i]); + 53fe: 8444 ld.b r2, (r4, 0x4) + 5400: 8460 ld.b r3, (r4, 0x0) + 5402: 6c5b mov r1, r6 + 5404: b840 st.w r2, (r14, 0x0) + 5406: 3000 movi r0, 0 + 5408: 6c97 mov r2, r5 + 540a: 2500 addi r5, 1 + 540c: e3ffedce bsr 0x2fa8 // 2fa8 + for(i=0;i + } + + return 0; +} + 5416: 3000 movi r0, 0 + 5418: 1401 addi r14, r14, 4 + 541a: 1493 pop r4-r6, r15 + 541c: 00006017 .long 0x00006017 + 5420: 00006034 .long 0x00006034 + 5424: 0000604b .long 0x0000604b + 5428: 00006066 .long 0x00006066 + 542c: 00006088 .long 0x00006088 + 5430: 000060ac .long 0x000060ac + +Disassembly of section .text.EEPROM_Default_ParaInfo: + +00005434 : + +/*恢复默认值*/ +void EEPROM_Default_ParaInfo(E_PARA_INFO *info){ + 5434: 14c1 push r4 + info->powerbus_enable = EEPROM_ParaDefault_PowerBusEnable; + 5436: 3301 movi r3, 1 + 5438: a060 st.b r3, (r0, 0x0) + info->save_curr = EEPROM_ParaDefault_SaveCurr; + 543a: 3378 movi r3, 120 + 543c: a061 st.b r3, (r0, 0x1) + info->allBrightness = BRIGHTNESS_MAX; //全局亮度默认：100 + 543e: 3364 movi r3, 100 + 5440: a062 st.b r3, (r0, 0x2) + info->allBrightnessUpLimit = BRIGHTNESS_MAX; //全局亮度可调上限默认：100 + 5442: a063 st.b r3, (r0, 0x3) + 5444: 310e movi r1, 14 + info->allBrightnessDownLimit = BRIGHTNESS_MIN; //全局亮度可调下限默认：0 + 5446: 3300 movi r3, 0 + + for(U8_T i=0;iswithcState[i] = 0x01; //回路开关状态默认：0x01 + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + info->gradialTime[i] = 1000; //回路渐变时间默认：1000 + 5448: 32fa movi r2, 250 + info->allBrightnessDownLimit = BRIGHTNESS_MIN; //全局亮度可调下限默认：0 + 544a: a064 st.b r3, (r0, 0x4) + 544c: 6040 addu r1, r0 + 544e: 5872 addi r3, r0, 5 + info->gradialTime[i] = 1000; //回路渐变时间默认：1000 + 5450: 4242 lsli r2, r2, 2 + 5452: 2008 addi r0, 9 + info->swithcState[i] = 0x01; //回路开关状态默认：0x01 + 5454: 3401 movi r4, 1 + 5456: a380 st.b r4, (r3, 0x0) + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + 5458: 3400 movi r4, 0 + 545a: a384 st.b r4, (r3, 0x4) + 545c: 2300 addi r3, 1 + for(U8_T i=0;igradialTime[i] = 1000; //回路渐变时间默认：1000 + 5460: a940 st.h r2, (r1, 0x0) + 5462: 2101 addi r1, 2 + for(U8_T i=0;i + } +} + 5466: 1481 pop r4 + +Disassembly of section .text.EEPROM_Init: + +00005468 : +void EEPROM_Init(void){ + 5468: 14d0 push r15 + EnIFCClk; //使能 IFC 时钟 + 546a: 106e lrw r3, 0x20000060 // 54a0 + 546c: 3201 movi r2, 1 + 546e: 9360 ld.w r3, (r3, 0x0) + 5470: b341 st.w r2, (r3, 0x4) + IFC->MR |= 0x10002; //高速模式，延迟 2 个周期 + 5472: 9345 ld.w r2, (r3, 0x14) + 5474: 3aa1 bseti r2, 1 + 5476: 3ab0 bseti r2, 16 + 5478: b345 st.w r2, (r3, 0x14) + delay_nms(10); + 547a: 300a movi r0, 10 + 547c: e3ffe608 bsr 0x208c // 208c + rev = EEPROM_ReadParaInfo(&g_eeprom); + 5480: 1009 lrw r0, 0x200007a4 // 54a4 + 5482: e3ffff1b bsr 0x52b8 // 52b8 + if(rev != 0x00){ + 5486: 3840 cmpnei r0, 0 + 5488: 0c08 bf 0x5498 // 5498 + EEPROM_Default_ParaInfo(&g_eeprom); + 548a: 1007 lrw r0, 0x200007a4 // 54a4 + 548c: e3ffffd4 bsr 0x5434 // 5434 + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info Use Default"); + 5490: 1026 lrw r1, 0x60c4 // 54a8 + 5492: 3000 movi r0, 0 + 5494: e3ffed8a bsr 0x2fa8 // 2fa8 + EEPROM_Validate_ParaInfo(&g_eeprom); + 5498: 1003 lrw r0, 0x200007a4 // 54a4 + 549a: e3ffff6b bsr 0x5370 // 5370 +} + 549e: 1490 pop r15 + 54a0: 20000060 .long 0x20000060 + 54a4: 200007a4 .long 0x200007a4 + 54a8: 000060c4 .long 0x000060c4 + +Disassembly of section .text.std_clk_calib: + +000054ac : + 54ac: 14d4 push r4-r7, r15 + 54ae: 142d subi r14, r14, 52 + 54b0: 3201 movi r2, 1 + 54b2: 03ce lrw r6, 0x2000005c // 56f4 + 54b4: 6cc3 mov r3, r0 + 54b6: dc4e000a st.b r2, (r14, 0xa) + 54ba: 9640 ld.w r2, (r6, 0x0) + 54bc: 9247 ld.w r2, (r2, 0x1c) + 54be: 7488 zextb r2, r2 + 54c0: dc4e0009 st.b r2, (r14, 0x9) + 54c4: d84e0009 ld.b r2, (r14, 0x9) + 54c8: 3a40 cmpnei r2, 0 + 54ca: 0c08 bf 0x54da // 54da + 54cc: d84e0009 ld.b r2, (r14, 0x9) + 54d0: 3a42 cmpnei r2, 2 + 54d2: 0c04 bf 0x54da // 54da + 54d4: 3000 movi r0, 0 + 54d6: 140d addi r14, r14, 52 + 54d8: 1494 pop r4-r7, r15 + 54da: 0397 lrw r4, 0x2000000c // 56f8 + 54dc: 3209 movi r2, 9 + 54de: 9400 ld.w r0, (r4, 0x0) + 54e0: 3b40 cmpnei r3, 0 + 54e2: b041 st.w r2, (r0, 0x4) + 54e4: 0857 bt 0x5592 // 5592 + 54e6: 3307 movi r3, 7 + 54e8: dc6e000b st.b r3, (r14, 0xb) + 54ec: 037b lrw r3, 0x2dc6c00 // 56fc + 54ee: b863 st.w r3, (r14, 0xc) + 54f0: 3380 movi r3, 128 + 54f2: 4362 lsli r3, r3, 2 + 54f4: b867 st.w r3, (r14, 0x1c) + 54f6: d86e000b ld.b r3, (r14, 0xb) + 54fa: 74cc zextb r3, r3 + 54fc: b062 st.w r3, (r0, 0x8) + 54fe: 037e lrw r3, 0xffff // 5700 + 5500: b063 st.w r3, (r0, 0xc) + 5502: 3201 movi r2, 1 + 5504: 3101 movi r1, 1 + 5506: 03bf lrw r5, 0x20000014 // 5704 + 5508: e3ffdfda bsr 0x14bc // 14bc + 550c: 95e0 ld.w r7, (r5, 0x0) + 550e: 137f lrw r3, 0xbe9c0005 // 5708 + 5510: b760 st.w r3, (r7, 0x0) + 5512: 135f lrw r2, 0x30010 // 570c + 5514: 3300 movi r3, 0 + 5516: b762 st.w r3, (r7, 0x8) + 5518: b743 st.w r2, (r7, 0xc) + 551a: 32d8 movi r2, 216 + 551c: b745 st.w r2, (r7, 0x14) + 551e: 974f ld.w r2, (r7, 0x3c) + 5520: 3aa2 bseti r2, 2 + 5522: b74f st.w r2, (r7, 0x3c) + 5524: 9803 ld.w r0, (r14, 0xc) + 5526: d82e000b ld.b r1, (r14, 0xb) + 552a: 327d movi r2, 125 + 552c: 2100 addi r1, 1 + 552e: 7c48 mult r1, r2 + 5530: b861 st.w r3, (r14, 0x4) + 5532: e3ffec91 bsr 0x2e54 // 2e54 <__udivsi3> + 5536: b804 st.w r0, (r14, 0x10) + 5538: 32fa movi r2, 250 + 553a: 9824 ld.w r1, (r14, 0x10) + 553c: 4242 lsli r2, r2, 2 + 553e: 6448 cmphs r2, r1 + 5540: 0bca bt 0x54d4 // 54d4 + 5542: 9844 ld.w r2, (r14, 0x10) + 5544: 3178 movi r1, 120 + 5546: 9804 ld.w r0, (r14, 0x10) + 5548: b840 st.w r2, (r14, 0x0) + 554a: e3ffec85 bsr 0x2e54 // 2e54 <__udivsi3> + 554e: 9840 ld.w r2, (r14, 0x0) + 5550: 6082 subu r2, r0 + 5552: b845 st.w r2, (r14, 0x14) + 5554: 9804 ld.w r0, (r14, 0x10) + 5556: 3178 movi r1, 120 + 5558: 9844 ld.w r2, (r14, 0x10) + 555a: b840 st.w r2, (r14, 0x0) + 555c: e3ffec7c bsr 0x2e54 // 2e54 <__udivsi3> + 5560: 9840 ld.w r2, (r14, 0x0) + 5562: 6008 addu r0, r2 + 5564: b806 st.w r0, (r14, 0x18) + 5566: c0807020 psrclr ie + 556a: 9640 ld.w r2, (r6, 0x0) + 556c: 9254 ld.w r2, (r2, 0x50) + 556e: b848 st.w r2, (r14, 0x20) + 5570: 9861 ld.w r3, (r14, 0x4) + 5572: 9440 ld.w r2, (r4, 0x0) + 5574: b260 st.w r3, (r2, 0x0) + 5576: b761 st.w r3, (r7, 0x4) + 5578: d86e000a ld.b r3, (r14, 0xa) + 557c: 3b40 cmpnei r3, 0 + 557e: 083e bt 0x55fa // 55fa + 5580: e3ffde84 bsr 0x1288 // 1288 + 5584: 9400 ld.w r0, (r4, 0x0) + 5586: e3ffdf71 bsr 0x1468 // 1468 + 558a: c1807420 psrset ee, ie + 558e: 3001 movi r0, 1 + 5590: 07a3 br 0x54d6 // 54d6 + 5592: 3b41 cmpnei r3, 1 + 5594: 0806 bt 0x55a0 // 55a0 + 5596: 3303 movi r3, 3 + 5598: dc6e000b st.b r3, (r14, 0xb) + 559c: 127d lrw r3, 0x16e3600 // 5710 + 559e: 07a8 br 0x54ee // 54ee + 55a0: 3b42 cmpnei r3, 2 + 55a2: 0806 bt 0x55ae // 55ae + 55a4: 3301 movi r3, 1 + 55a6: dc6e000b st.b r3, (r14, 0xb) + 55aa: 127b lrw r3, 0xb71b00 // 5714 + 55ac: 07a1 br 0x54ee // 54ee + 55ae: 3b43 cmpnei r3, 3 + 55b0: 0806 bt 0x55bc // 55bc + 55b2: 3300 movi r3, 0 + 55b4: dc6e000b st.b r3, (r14, 0xb) + 55b8: 1278 lrw r3, 0x5b8d80 // 5718 + 55ba: 079a br 0x54ee // 54ee + 55bc: 3b44 cmpnei r3, 4 + 55be: 0809 bt 0x55d0 // 55d0 + 55c0: 3300 movi r3, 0 + 55c2: dc6e000b st.b r3, (r14, 0xb) + 55c6: 1276 lrw r3, 0x54c720 // 571c + 55c8: b863 st.w r3, (r14, 0xc) + 55ca: 3380 movi r3, 128 + 55cc: 4369 lsli r3, r3, 9 + 55ce: 0793 br 0x54f4 // 54f4 + 55d0: 3b45 cmpnei r3, 5 + 55d2: 0806 bt 0x55de // 55de + 55d4: 3300 movi r3, 0 + 55d6: dc6e000b st.b r3, (r14, 0xb) + 55da: 1272 lrw r3, 0x3ffed0 // 5720 + 55dc: 07f6 br 0x55c8 // 55c8 + 55de: 3b46 cmpnei r3, 6 + 55e0: 0806 bt 0x55ec // 55ec + 55e2: 3300 movi r3, 0 + 55e4: dc6e000b st.b r3, (r14, 0xb) + 55e8: 126f lrw r3, 0x1fff68 // 5724 + 55ea: 07ef br 0x55c8 // 55c8 + 55ec: 3b47 cmpnei r3, 7 + 55ee: 0b84 bt 0x54f6 // 54f6 + 55f0: 3300 movi r3, 0 + 55f2: dc6e000b st.b r3, (r14, 0xb) + 55f6: 126d lrw r3, 0x1ffb8 // 5728 + 55f8: 07e8 br 0x55c8 // 55c8 + 55fa: 9560 ld.w r3, (r5, 0x0) + 55fc: 3101 movi r1, 1 + 55fe: 9440 ld.w r2, (r4, 0x0) + 5600: b321 st.w r1, (r3, 0x4) + 5602: b220 st.w r1, (r2, 0x0) + 5604: 3100 movi r1, 0 + 5606: b327 st.w r1, (r3, 0x1c) + 5608: 3004 movi r0, 4 + 560a: b225 st.w r1, (r2, 0x14) + 560c: 932e ld.w r1, (r3, 0x38) + 560e: 6840 and r1, r0 + 5610: 3940 cmpnei r1, 0 + 5612: 0ffd bf 0x560c // 560c + 5614: 9225 ld.w r1, (r2, 0x14) + 5616: b82a st.w r1, (r14, 0x28) + 5618: 3100 movi r1, 0 + 561a: b310 st.w r0, (r3, 0x40) + 561c: b327 st.w r1, (r3, 0x1c) + 561e: 3004 movi r0, 4 + 5620: b225 st.w r1, (r2, 0x14) + 5622: 932e ld.w r1, (r3, 0x38) + 5624: 6840 and r1, r0 + 5626: 3940 cmpnei r1, 0 + 5628: 0ffd bf 0x5622 // 5622 + 562a: 9225 ld.w r1, (r2, 0x14) + 562c: b82b st.w r1, (r14, 0x2c) + 562e: 3100 movi r1, 0 + 5630: b310 st.w r0, (r3, 0x40) + 5632: b327 st.w r1, (r3, 0x1c) + 5634: 3004 movi r0, 4 + 5636: b225 st.w r1, (r2, 0x14) + 5638: 932e ld.w r1, (r3, 0x38) + 563a: 6840 and r1, r0 + 563c: 3940 cmpnei r1, 0 + 563e: 0ffd bf 0x5638 // 5638 + 5640: 9225 ld.w r1, (r2, 0x14) + 5642: b82c st.w r1, (r14, 0x30) + 5644: b310 st.w r0, (r3, 0x40) + 5646: 982b ld.w r1, (r14, 0x2c) + 5648: 980c ld.w r0, (r14, 0x30) + 564a: 6040 addu r1, r0 + 564c: b829 st.w r1, (r14, 0x24) + 564e: 9829 ld.w r1, (r14, 0x24) + 5650: 4921 lsri r1, r1, 1 + 5652: b829 st.w r1, (r14, 0x24) + 5654: 3100 movi r1, 0 + 5656: b321 st.w r1, (r3, 0x4) + 5658: b220 st.w r1, (r2, 0x0) + 565a: b327 st.w r1, (r3, 0x1c) + 565c: b225 st.w r1, (r2, 0x14) + 565e: d86e0009 ld.b r3, (r14, 0x9) + 5662: 3b42 cmpnei r3, 2 + 5664: 9849 ld.w r2, (r14, 0x24) + 5666: 082c bt 0x56be // 56be + 5668: 1171 lrw r3, 0x7ff // 572c + 566a: 648c cmphs r3, r2 + 566c: 0c03 bf 0x5672 // 5672 + 566e: 3300 movi r3, 0 + 5670: 040f br 0x568e // 568e + 5672: 9849 ld.w r2, (r14, 0x24) + 5674: 9866 ld.w r3, (r14, 0x18) + 5676: 648c cmphs r3, r2 + 5678: 080e bt 0x5694 // 5694 + 567a: 9868 ld.w r3, (r14, 0x20) + 567c: 9847 ld.w r2, (r14, 0x1c) + 567e: 60ca subu r3, r2 + 5680: b868 st.w r3, (r14, 0x20) + 5682: 32fe movi r2, 254 + 5684: 9868 ld.w r3, (r14, 0x20) + 5686: 4248 lsli r2, r2, 8 + 5688: 68c8 and r3, r2 + 568a: 3b40 cmpnei r3, 0 + 568c: 0812 bt 0x56b0 // 56b0 + 568e: dc6e000a st.b r3, (r14, 0xa) + 5692: 0721 br 0x54d4 // 54d4 + 5694: 9849 ld.w r2, (r14, 0x24) + 5696: 9865 ld.w r3, (r14, 0x14) + 5698: 64c8 cmphs r2, r3 + 569a: 0829 bt 0x56ec // 56ec + 569c: 9868 ld.w r3, (r14, 0x20) + 569e: 9847 ld.w r2, (r14, 0x1c) + 56a0: 60c8 addu r3, r2 + 56a2: b868 st.w r3, (r14, 0x20) + 56a4: 33fe movi r3, 254 + 56a6: 9848 ld.w r2, (r14, 0x20) + 56a8: 4368 lsli r3, r3, 8 + 56aa: 688c and r2, r3 + 56ac: 64ca cmpne r2, r3 + 56ae: 0fe0 bf 0x566e // 566e + 56b0: 9660 ld.w r3, (r6, 0x0) + 56b2: 9848 ld.w r2, (r14, 0x20) + 56b4: b354 st.w r2, (r3, 0x50) + 56b6: 3001 movi r0, 1 + 56b8: e3ffe4ea bsr 0x208c // 208c + 56bc: 075e br 0x5578 // 5578 + 56be: 9866 ld.w r3, (r14, 0x18) + 56c0: 648c cmphs r3, r2 + 56c2: 0809 bt 0x56d4 // 56d4 + 56c4: 9868 ld.w r3, (r14, 0x20) + 56c6: 9847 ld.w r2, (r14, 0x1c) + 56c8: 60ca subu r3, r2 + 56ca: b868 st.w r3, (r14, 0x20) + 56cc: 32ff movi r2, 255 + 56ce: 9868 ld.w r3, (r14, 0x20) + 56d0: 4250 lsli r2, r2, 16 + 56d2: 07db br 0x5688 // 5688 + 56d4: 9849 ld.w r2, (r14, 0x24) + 56d6: 9865 ld.w r3, (r14, 0x14) + 56d8: 64c8 cmphs r2, r3 + 56da: 0809 bt 0x56ec // 56ec + 56dc: 9868 ld.w r3, (r14, 0x20) + 56de: 9847 ld.w r2, (r14, 0x1c) + 56e0: 60c8 addu r3, r2 + 56e2: b868 st.w r3, (r14, 0x20) + 56e4: 33ff movi r3, 255 + 56e6: 9848 ld.w r2, (r14, 0x20) + 56e8: 4370 lsli r3, r3, 16 + 56ea: 07e0 br 0x56aa // 56aa + 56ec: 3300 movi r3, 0 + 56ee: dc6e000a st.b r3, (r14, 0xa) + 56f2: 07e2 br 0x56b6 // 56b6 + 56f4: 2000005c .long 0x2000005c + 56f8: 2000000c .long 0x2000000c + 56fc: 02dc6c00 .long 0x02dc6c00 + 5700: 0000ffff .long 0x0000ffff + 5704: 20000014 .long 0x20000014 + 5708: be9c0005 .long 0xbe9c0005 + 570c: 00030010 .long 0x00030010 + 5710: 016e3600 .long 0x016e3600 + 5714: 00b71b00 .long 0x00b71b00 + 5718: 005b8d80 .long 0x005b8d80 + 571c: 0054c720 .long 0x0054c720 + 5720: 003ffed0 .long 0x003ffed0 + 5724: 001fff68 .long 0x001fff68 + 5728: 0001ffb8 .long 0x0001ffb8 + 572c: 000007ff .long 0x000007ff diff --git a/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.map b/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.map new file mode 100644 index 0000000..2714ead --- /dev/null +++ b/Source/Lst/BLV_C8_PLC_MASTER_V07_20260117.map @@ -0,0 +1,2564 @@ +ELF Header: + Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 + Class: ELF32 + Data: 2's complement, little endian + Version: 1 (current) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: EXEC (Executable file) + Machine: CSKY + Version: 0x1 + Entry point address: 0x10c + Start of program headers: 52 (bytes into file) + Start of section headers: 357224 (bytes into file) + Flags: 0x21000000 + Size of this header: 52 (bytes) + Size of program headers: 32 (bytes) + Number of program headers: 2 + Size of section headers: 40 (bytes) + Number of section headers: 221 + Section header string table index: 218 + +Section Headers: + [Nr] Name Type Addr Off Size ES Flg Lk Inf Al + [ 0] NULL 00000000 000000 000000 00 0 0 0 + [ 1] .text PROGBITS 00000000 001000 000ce0 00 AX 0 0 1024 + [ 2] .text.__main PROGBITS 00000ce0 001ce0 000038 00 AX 0 0 4 + [ 3] .text.SYSCON_Gene PROGBITS 00000d18 001d18 000074 00 AX 0 0 4 + [ 4] .text.SYSCON_RST_ PROGBITS 00000d8c 001d8c 000058 00 AX 0 0 4 + [ 5] .text.SYSCON_Gene PROGBITS 00000de4 001de4 000030 00 AX 0 0 4 + [ 6] .text.SystemCLK_H PROGBITS 00000e14 001e14 000088 00 AX 0 0 4 + [ 7] .text.SYSCON_HFOS PROGBITS 00000e9c 001e9c 000028 00 AX 0 0 4 + [ 8] .text.SYSCON_WDT_ PROGBITS 00000ec4 001ec4 00003c 00 AX 0 0 4 + [ 9] .text.SYSCON_IWDC PROGBITS 00000f00 001f00 000014 00 AX 0 0 4 + [10] .text.SYSCON_IWDC PROGBITS 00000f14 001f14 000018 00 AX 0 0 4 + [11] .text.SYSCON_LVD_ PROGBITS 00000f2c 001f2c 000020 00 AX 0 0 4 + [12] .text.LVD_Int_Ena PROGBITS 00000f4c 001f4c 00001c 00 AX 0 0 4 + [13] .text.IWDT_Int_En PROGBITS 00000f68 001f68 00001c 00 AX 0 0 4 + [14] .text.EXTI_trigge PROGBITS 00000f84 001f84 000040 00 AX 0 0 4 + [15] .text.EXTI_interr PROGBITS 00000fc4 001fc4 000034 00 AX 0 0 4 + [16] .text.GPIO_EXTI_i PROGBITS 00000ff8 001ff8 000004 00 AX 0 0 2 + [17] .text.EXI1_Int_En PROGBITS 00000ffc 001ffc 000010 00 AX 0 0 4 + [18] .text.SYSCON_Int_ PROGBITS 0000100c 00200c 00000c 00 AX 0 0 4 + [19] .text.SYSCON_INT_ PROGBITS 00001018 002018 000024 00 AX 0 0 4 + [20] .text.Set_INT_Pri PROGBITS 0000103c 00203c 000030 00 AX 0 0 4 + [21] .text.GPIO_Init PROGBITS 0000106c 00206c 0000e0 00 AX 0 0 4 + [22] .text.GPIO_DriveS PROGBITS 0000114c 00214c 00000e 00 AX 0 0 2 + [23] .text.GPIO_IntGro PROGBITS 0000115c 00215c 00010c 00 AX 0 0 4 + [24] .text.GPIO_Write_ PROGBITS 00001268 002268 000008 00 AX 0 0 2 + [25] .text.GPIO_Write_ PROGBITS 00001270 002270 000008 00 AX 0 0 2 + [26] .text.GPIO_Read_S PROGBITS 00001278 002278 000010 00 AX 0 0 2 + [27] .text.LPT_Soft_Re PROGBITS 00001288 002288 000014 00 AX 0 0 4 + [28] .text.WWDT_CONFIG PROGBITS 0000129c 00229c 000018 00 AX 0 0 4 + [29] .text.WWDT_CNT_Lo PROGBITS 000012b4 0022b4 000010 00 AX 0 0 4 + [30] .text.WWDT_Int_Co PROGBITS 000012c4 0022c4 000034 00 AX 0 0 4 + [31] .text.BT_DeInit PROGBITS 000012f8 0022f8 00001c 00 AX 0 0 2 + [32] .text.BT_IO_Init PROGBITS 00001314 002314 00014c 00 AX 0 0 4 + [33] .text.BT_Start PROGBITS 00001460 002460 000008 00 AX 0 0 2 + [34] .text.BT_Soft_Res PROGBITS 00001468 002468 00000a 00 AX 0 0 2 + [35] .text.BT_Configur PROGBITS 00001472 002472 000018 00 AX 0 0 2 + [36] .text.BT_ControlS PROGBITS 0000148a 00248a 00002c 00 AX 0 0 2 + [37] .text.BT_Period_C PROGBITS 000014b6 0024b6 000006 00 AX 0 0 2 + [38] .text.BT_ConfigIn PROGBITS 000014bc 0024bc 000012 00 AX 0 0 2 + [39] .text.BT1_INT_ENA PROGBITS 000014d0 0024d0 000010 00 AX 0 0 4 + [40] .text.GPT_Configu PROGBITS 000014e0 0024e0 000014 00 AX 0 0 4 + [41] .text.GPT_WaveCtr PROGBITS 000014f4 0024f4 000044 00 AX 0 0 4 + [42] .text.GPT_Start PROGBITS 00001538 002538 000010 00 AX 0 0 4 + [43] .text.GPT_Period_ PROGBITS 00001548 002548 000010 00 AX 0 0 4 + [44] .text.GPT_ConfigI PROGBITS 00001558 002558 00001c 00 AX 0 0 4 + [45] .text.GPT_INT_ENA PROGBITS 00001574 002574 000010 00 AX 0 0 4 + [46] .text.UART0_DeIni PROGBITS 00001584 002584 000018 00 AX 0 0 4 + [47] .text.UART1_DeIni PROGBITS 0000159c 00259c 000018 00 AX 0 0 4 + [48] .text.UART2_DeIni PROGBITS 000015b4 0025b4 000018 00 AX 0 0 4 + [49] .text.UART0_Int_E PROGBITS 000015cc 0025cc 00001c 00 AX 0 0 4 + [50] .text.UART1_Int_E PROGBITS 000015e8 0025e8 00001c 00 AX 0 0 4 + [51] .text.UART_IO_Ini PROGBITS 00001604 002604 0000e8 00 AX 0 0 4 + [52] .text.UARTInitRxT PROGBITS 000016ec 0026ec 00000a 00 AX 0 0 2 + [53] .text.UARTTxByte PROGBITS 000016f6 0026f6 00000e 00 AX 0 0 2 + [54] .text.UARTTransmi PROGBITS 00001704 002704 00001e 00 AX 0 0 2 + [55] .text.EPT_Softwar PROGBITS 00001724 002724 000020 00 AX 0 0 4 + [56] .text.EPT_Start PROGBITS 00001744 002744 000028 00 AX 0 0 4 + [57] .text.EPT_IO_SET PROGBITS 0000176c 00276c 000238 00 AX 0 0 4 + [58] .text.EPT_PWM_Con PROGBITS 000019a4 0029a4 000038 00 AX 0 0 4 + [59] .text.EPT_PWMX_Ou PROGBITS 000019dc 0029dc 0000d8 00 AX 0 0 4 + [60] .text.EPT_PRDR_CM PROGBITS 00001ab4 002ab4 00001c 00 AX 0 0 4 + [61] .text.ADC12_RESET PROGBITS 00001ad0 002ad0 000064 00 AX 0 0 4 + [62] .text.ADC12_Contr PROGBITS 00001b34 002b34 000010 00 AX 0 0 4 + [63] .text.ADC12_CMD.p PROGBITS 00001b44 002b44 000020 00 AX 0 0 4 + [64] .text.ADC12_CLK_C PROGBITS 00001b64 002b64 00002c 00 AX 0 0 4 + [65] .text.ADC12_Softw PROGBITS 00001b90 002b90 00000a 00 AX 0 0 2 + [66] .text.ADC12_CMD PROGBITS 00001b9c 002b9c 000028 00 AX 0 0 4 + [67] .text.ADC12_ready PROGBITS 00001bc4 002bc4 000014 00 AX 0 0 4 + [68] .text.ADC12_SEQEN PROGBITS 00001bd8 002bd8 000018 00 AX 0 0 4 + [69] .text.ADC12_DATA_ PROGBITS 00001bf0 002bf0 000014 00 AX 0 0 4 + [70] .text.ADC12_Confi PROGBITS 00001c04 002c04 00007c 00 AX 0 0 4 + [71] .text.ADC12_Confi PROGBITS 00001c80 002c80 000198 00 AX 0 0 4 + [72] .text.ADC12_Conve PROGBITS 00001e18 002e18 000180 00 AX 0 0 4 + [73] .text.Page_Progra PROGBITS 00001f98 002f98 0000a0 00 AX 0 0 4 + [74] .text.ReadDataArr PROGBITS 00002038 003038 00002a 00 AX 0 0 2 + [75] .text.startup.mai PROGBITS 00002064 003064 000028 00 AX 0 0 4 + [76] .text.delay_nms PROGBITS 0000208c 00308c 00002c 00 AX 0 0 2 + [77] .text.GPIO_CONFIG PROGBITS 000020b8 0030b8 000098 00 AX 0 0 4 + [78] .text.EPT0_CONFIG PROGBITS 00002150 003150 0000d8 00 AX 0 0 4 + [79] .text.BT_CONFIG PROGBITS 00002228 003228 0000ac 00 AX 0 0 4 + [80] .text.ADC12_CONFI PROGBITS 000022d4 0032d4 000072 00 AX 0 0 2 + [81] .text.GPT0_CONFIG PROGBITS 00002348 003348 000050 00 AX 0 0 4 + [82] .text.SYSCON_CONF PROGBITS 00002398 003398 000078 00 AX 0 0 2 + [83] .text.APT32F102_i PROGBITS 00002410 003410 000078 00 AX 0 0 4 + [84] .text.SYSCONIntHa PROGBITS 00002488 003488 0000f0 00 AX 0 0 4 + [85] .text.IFCIntHandl PROGBITS 00002578 003578 000068 00 AX 0 0 4 + [86] .text.ADCIntHandl PROGBITS 000025e0 0035e0 000068 00 AX 0 0 4 + [87] .text.EPT0IntHand PROGBITS 00002648 003648 0001a8 00 AX 0 0 4 + [88] .text.WWDTHandler PROGBITS 000027f0 0037f0 000034 00 AX 0 0 4 + [89] .text.GPT0IntHand PROGBITS 00002824 003824 00008c 00 AX 0 0 4 + [90] .text.RTCIntHandl PROGBITS 000028b0 0038b0 000070 00 AX 0 0 4 + [91] .text.UART0IntHan PROGBITS 00002920 003920 000054 00 AX 0 0 4 + [92] .text.UART1IntHan PROGBITS 00002974 003974 000050 00 AX 0 0 4 + [93] .text.UART2IntHan PROGBITS 000029c4 0039c4 00003c 00 AX 0 0 4 + [94] .text.SPI0IntHand PROGBITS 00002a00 003a00 0000e8 00 AX 0 0 4 + [95] .text.SIO0IntHand PROGBITS 00002ae8 003ae8 000084 00 AX 0 0 4 + [96] .text.EXI0IntHand PROGBITS 00002b6c 003b6c 000030 00 AX 0 0 4 + [97] .text.EXI1IntHand PROGBITS 00002b9c 003b9c 00003c 00 AX 0 0 4 + [98] .text.EXI2to3IntH PROGBITS 00002bd8 003bd8 000048 00 AX 0 0 4 + [99] .text.EXI4to9IntH PROGBITS 00002c20 003c20 00005c 00 AX 0 0 4 + [100] .text.EXI10to15In PROGBITS 00002c7c 003c7c 000060 00 AX 0 0 4 + [101] .text.LPTIntHandl PROGBITS 00002cdc 003cdc 000034 00 AX 0 0 4 + [102] .text.BT0IntHandl PROGBITS 00002d10 003d10 00003c 00 AX 0 0 4 + [103] .text.BT1IntHandl PROGBITS 00002d4c 003d4c 000070 00 AX 0 0 4 + [104] .text.PriviledgeV PROGBITS 00002dbc 003dbc 000002 00 AX 0 0 2 + [105] .text.PendTrapHan PROGBITS 00002dbe 003dbe 000008 00 AX 0 0 2 + [106] .text.Trap3Handle PROGBITS 00002dc6 003dc6 000008 00 AX 0 0 2 + [107] .text.Trap2Handle PROGBITS 00002dce 003dce 000008 00 AX 0 0 2 + [108] .text.Trap1Handle PROGBITS 00002dd6 003dd6 000008 00 AX 0 0 2 + [109] .text.Trap0Handle PROGBITS 00002dde 003dde 000008 00 AX 0 0 2 + [110] .text.UnrecExecpH PROGBITS 00002de6 003de6 000008 00 AX 0 0 2 + [111] .text.BreakPointH PROGBITS 00002dee 003dee 000008 00 AX 0 0 2 + [112] .text.AccessErrHa PROGBITS 00002df6 003df6 000008 00 AX 0 0 2 + [113] .text.IllegalInst PROGBITS 00002dfe 003dfe 000008 00 AX 0 0 2 + [114] .text.MisalignedH PROGBITS 00002e06 003e06 000008 00 AX 0 0 2 + [115] .text.TKEYIntHand PROGBITS 00002e0e 003e0e 000008 00 AX 0 0 2 + [116] .text.CNTAIntHand PROGBITS 00002e16 003e16 000008 00 AX 0 0 2 + [117] .text.I2CIntHandl PROGBITS 00002e1e 003e1e 000008 00 AX 0 0 2 + [118] .text.CORETHandle PROGBITS 00002e26 003e26 000008 00 AX 0 0 2 + [119] .text.__divsi3 PROGBITS 00002e30 003e30 000024 00 AX 0 0 4 + [120] .text.__udivsi3 PROGBITS 00002e54 003e54 000024 00 AX 0 0 4 + [121] .text.CK_CPU_EnAl PROGBITS 00002e78 003e78 000006 00 AX 0 0 2 + [122] .text.UARTx_Init PROGBITS 00002e80 003e80 000094 00 AX 0 0 4 + [123] .text.UART1_RecvI PROGBITS 00002f14 003f14 000038 00 AX 0 0 4 + [124] .text.UART1_TASK PROGBITS 00002f4c 003f4c 00005c 00 AX 0 0 4 + [125] .text.Dbg_Println PROGBITS 00002fa8 003fa8 00000c 00 AX 0 0 2 + [126] .text.Dbg_Print_B PROGBITS 00002fb4 003fb4 000002 00 AX 0 0 2 + [127] .text.PB_Set_Powe PROGBITS 00002fb8 003fb8 000020 00 AX 0 0 4 + [128] .text.PB_Set_Save PROGBITS 00002fd8 003fd8 00002c 00 AX 0 0 4 + [129] .text.PB_Init PROGBITS 00003004 004004 000044 00 AX 0 0 4 + [130] .text.PB_Set_Powe PROGBITS 00003048 004048 00001c 00 AX 0 0 4 + [131] .text.PB_Soft_Boo PROGBITS 00003064 004064 000118 00 AX 0 0 4 + [132] .text.PowerBus_Da PROGBITS 0000317c 00417c 000034 00 AX 0 0 4 + [133] .text.PB_Send_Str PROGBITS 000031b0 0041b0 000054 00 AX 0 0 4 + [134] .text.PowerBus_Da PROGBITS 00003204 004204 00007c 00 AX 0 0 4 + [135] .text.PB_CheckSum PROGBITS 00003280 004280 000018 00 AX 0 0 2 + [136] .text.PB_OVERCURR PROGBITS 00003298 004298 000024 00 AX 0 0 4 + [137] .text.PB_Protect_ PROGBITS 000032bc 0042bc 000054 00 AX 0 0 4 + [138] .text.PB_Scan_Sta PROGBITS 00003310 004310 000034 00 AX 0 0 4 + [139] .text.PowerBus_Fi PROGBITS 00003344 004344 00004c 00 AX 0 0 4 + [140] .text.PowerBus_Pa PROGBITS 00003390 004390 0000b0 00 AX 0 0 4 + [141] .text.PowerBUS_Ge PROGBITS 00003440 004440 00001c 00 AX 0 0 4 + [142] .text.PB_FilACkPa PROGBITS 0000345c 00445c 000034 00 AX 0 0 4 + [143] .text.PB_RS485_Re PROGBITS 00003490 004490 000038 00 AX 0 0 4 + [144] .text.PB_Set_CH_S PROGBITS 000034c8 0044c8 000038 00 AX 0 0 4 + [145] .text.PB_Set_CH_S PROGBITS 00003500 004500 000030 00 AX 0 0 4 + [146] .text.PB_ACK_SET_ PROGBITS 00003530 004530 000098 00 AX 0 0 4 + [147] .text.PB_ACK_SET_ PROGBITS 000035c8 0045c8 000080 00 AX 0 0 4 + [148] .text.PB_ACK_SET_ PROGBITS 00003648 004648 000060 00 AX 0 0 4 + [149] .text.PB_ACK_SET_ PROGBITS 000036a8 0046a8 000038 00 AX 0 0 4 + [150] .text.PB_ACK_SET_ PROGBITS 000036e0 0046e0 00006c 00 AX 0 0 4 + [151] .text.PB_ACK_SET_ PROGBITS 0000374c 00474c 0000e8 00 AX 0 0 4 + [152] .text.PB_ACK_SET_ PROGBITS 00003834 004834 000054 00 AX 0 0 4 + [153] .text.PB_ACK_Pass PROGBITS 00003888 004888 00003c 00 AX 0 0 4 + [154] .text.PB_ACK_SET_ PROGBITS 000038c4 0048c4 000040 00 AX 0 0 4 + [155] .text.PB_ACK_SET_ PROGBITS 00003904 004904 000040 00 AX 0 0 4 + [156] .text.PB_ACK_SET_ PROGBITS 00003944 004944 000040 00 AX 0 0 4 + [157] .text.PB_ACK_SET_ PROGBITS 00003984 004984 000040 00 AX 0 0 4 + [158] .text.PB_ACK_SET_ PROGBITS 000039c4 0049c4 000040 00 AX 0 0 4 + [159] .text.PB_ACK_SET_ PROGBITS 00003a04 004a04 000040 00 AX 0 0 4 + [160] .text.PB_ACK_SET_ PROGBITS 00003a44 004a44 000040 00 AX 0 0 4 + [161] .text.PB_ACK_SET_ PROGBITS 00003a84 004a84 000040 00 AX 0 0 4 + [162] .text.PB_ACK_SET_ PROGBITS 00003ac4 004ac4 00016c 00 AX 0 0 4 + [163] .text.PB_ACK_SET_ PROGBITS 00003c30 004c30 00014c 00 AX 0 0 4 + [164] .text.PB_ACK_SET_ PROGBITS 00003d7c 004d7c 00024c 00 AX 0 0 4 + [165] .text.PB_ACK_SET_ PROGBITS 00003fc8 004fc8 000044 00 AX 0 0 4 + [166] .text.PB_ACK_SET_ PROGBITS 0000400c 00500c 000040 00 AX 0 0 4 + [167] .text.PB_ACK_SET_ PROGBITS 0000404c 00504c 000044 00 AX 0 0 4 + [168] .text.PB_ACK_SET_ PROGBITS 00004090 005090 00014c 00 AX 0 0 4 + [169] .text.PB_ACK_SET_ PROGBITS 000041dc 0051dc 000044 00 AX 0 0 4 + [170] .text.PB_ACK_SET_ PROGBITS 00004220 005220 000044 00 AX 0 0 4 + [171] .text.PB_ACK_SET_ PROGBITS 00004264 005264 000044 00 AX 0 0 4 + [172] .text.PB_ACK_SET_ PROGBITS 000042a8 0052a8 000044 00 AX 0 0 4 + [173] .text.PB_ACK_SET_ PROGBITS 000042ec 0052ec 000044 00 AX 0 0 4 + [174] .text.PB_ACK_SET_ PROGBITS 00004330 005330 000044 00 AX 0 0 4 + [175] .text.Get_ADC_Val PROGBITS 00004374 005374 000022 00 AX 0 0 2 + [176] .text.Get_PB_CURR PROGBITS 00004398 005398 000028 00 AX 0 0 4 + [177] .text.PB_ACK_GET_ PROGBITS 000043c0 0053c0 0000e8 00 AX 0 0 4 + [178] .text.Current_Coa PROGBITS 000044a8 0054a8 000028 00 AX 0 0 4 + [179] .text.Current_Fin PROGBITS 000044d0 0054d0 000030 00 AX 0 0 4 + [180] .text.PB_Current_ PROGBITS 00004500 005500 000130 00 AX 0 0 4 + [181] .text.PMU_MEAS_Ta PROGBITS 00004630 005630 0001f0 00 AX 0 0 4 + [182] .text.Set_PB_Curr PROGBITS 00004820 005820 000010 00 AX 0 0 4 + [183] .text.PowerBus_Se PROGBITS 00004830 005830 000080 00 AX 0 0 4 + [184] .text.PB_ACK_SET_ PROGBITS 000048b0 0058b0 00016c 00 AX 0 0 4 + [185] .text.BLV_PB_Cont PROGBITS 00004a1c 005a1c 0002ac 00 AX 0 0 4 + [186] .text.PB_Task PROGBITS 00004cc8 005cc8 000014 00 AX 0 0 2 + [187] .text.PWM_SetOutD PROGBITS 00004cdc 005cdc 000030 00 AX 0 0 4 + [188] .text.PWM_SetCHGr PROGBITS 00004d0c 005d0c 000014 00 AX 0 0 4 + [189] .text.PWM_SetOutB PROGBITS 00004d20 005d20 0000f8 00 AX 0 0 4 + [190] .text.PWM_Init PROGBITS 00004e18 005e18 000178 00 AX 0 0 4 + [191] .text.PWM_SetUpLi PROGBITS 00004f90 005f90 000044 00 AX 0 0 4 + [192] .text.PWM_SetDown PROGBITS 00004fd4 005fd4 000044 00 AX 0 0 4 + [193] .text.Pwm_SetOnOf PROGBITS 00005018 006018 000018 00 AX 0 0 4 + [194] .text.Pwm_SetAllB PROGBITS 00005030 006030 00002c 00 AX 0 0 4 + [195] .text.PWM_SetAuto PROGBITS 0000505c 00605c 0000b4 00 AX 0 0 4 + [196] .text.PWM_Timer_1 PROGBITS 00005110 006110 0001a8 00 AX 0 0 4 + [197] .text.EEPROM_Read PROGBITS 000052b8 0062b8 000074 00 AX 0 0 4 + [198] .text.EEPROM_Writ PROGBITS 0000532c 00632c 000044 00 AX 0 0 4 + [199] .text.EEPROM_Vali PROGBITS 00005370 006370 0000c4 00 AX 0 0 4 + [200] .text.EEPROM_Defa PROGBITS 00005434 006434 000034 00 AX 0 0 2 + [201] .text.EEPROM_Init PROGBITS 00005468 006468 000044 00 AX 0 0 4 + [202] .text.std_clk_cal PROGBITS 000054ac 0064ac 000284 00 AX 0 0 4 + [203] .RomCode PROGBITS 00005730 008068 000000 00 W 0 0 1 + [204] .rodata PROGBITS 00005730 006730 0009ac 00 A 0 0 4 + [205] .data PROGBITS 20000000 008000 000068 00 WA 0 0 4 + [206] .bss NOBITS 20000068 008068 000754 00 WA 0 0 4 + [207] .csky.attributes CSKY_ATTRIBUTES 00000000 008068 000022 00 0 0 1 + [208] .comment PROGBITS 00000000 00808a 000042 01 MS 0 0 1 + [209] .csky_stack_size PROGBITS 00000000 0080d0 00089c 00 0 0 16 + [210] .debug_line PROGBITS 00000000 00896c 003f76 00 0 0 1 + [211] .debug_info PROGBITS 00000000 00c8e2 02f1fa 00 0 0 1 + [212] .debug_abbrev PROGBITS 00000000 03badc 0029e3 00 0 0 1 + [213] .debug_aranges PROGBITS 00000000 03e4c0 000e00 00 0 0 8 + [214] .debug_ranges PROGBITS 00000000 03f2c0 000d68 00 0 0 1 + [215] .debug_str PROGBITS 00000000 040028 009e1e 01 MS 0 0 1 + [216] .debug_frame PROGBITS 00000000 049e48 002218 00 0 0 4 + [217] .debug_loc PROGBITS 00000000 04c060 003d54 00 0 0 1 + [218] .shstrtab STRTAB 00000000 055f1e 00144a 00 0 0 1 + [219] .symtab SYMTAB 00000000 04fdb4 004b40 10 220 920 4 + [220] .strtab STRTAB 00000000 0548f4 00162a 00 0 0 1 +Key to Flags: + W (write), A (alloc), X (execute), M (merge), S (strings), I (info), + L (link order), O (extra OS processing required), G (group), T (TLS), + C (compressed), x (unknown), o (OS specific), E (exclude), + p (processor specific) + +Program Headers: + Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align + LOAD 0x001000 0x00000000 0x00000000 0x060dc 0x060dc R E 0x1000 + LOAD 0x008000 0x20000000 0x000060dc 0x00068 0x007bc RW 0x1000 + + Section to Segment mapping: + Segment Sections... + 00 .text .text.__main .text.SYSCON_General_CMD.part.0 .text.SYSCON_RST_VALUE .text.SYSCON_General_CMD .text.SystemCLK_HCLKDIV_PCLKDIV_Config .text.SYSCON_HFOSC_SELECTE .text.SYSCON_WDT_CMD .text.SYSCON_IWDCNT_Reload .text.SYSCON_IWDCNT_Config .text.SYSCON_LVD_Config .text.LVD_Int_Enable .text.IWDT_Int_Enable .text.EXTI_trigger_CMD .text.EXTI_interrupt_CMD .text.GPIO_EXTI_interrupt .text.EXI1_Int_Enable .text.SYSCON_Int_Enable .text.SYSCON_INT_Priority .text.Set_INT_Priority .text.GPIO_Init .text.GPIO_DriveStrength_EN .text.GPIO_IntGroup_Set .text.GPIO_Write_High .text.GPIO_Write_Low .text.GPIO_Read_Status .text.LPT_Soft_Reset .text.WWDT_CONFIG .text.WWDT_CNT_Load .text.WWDT_Int_Config .text.BT_DeInit .text.BT_IO_Init .text.BT_Start .text.BT_Soft_Reset .text.BT_Configure .text.BT_ControlSet_Configure .text.BT_Period_CMP_Write .text.BT_ConfigInterrupt_CMD .text.BT1_INT_ENABLE .text.GPT_Configure .text.GPT_WaveCtrl_Configure .text.GPT_Start .text.GPT_Period_CMP_Write .text.GPT_ConfigInterrupt_CMD .text.GPT_INT_ENABLE .text.UART0_DeInit .text.UART1_DeInit .text.UART2_DeInit .text.UART0_Int_Enable .text.UART1_Int_Enable .text.UART_IO_Init .text.UARTInitRxTxIntEn .text.UARTTxByte .text.UARTTransmit .text.EPT_Software_Prg .text.EPT_Start .text.EPT_IO_SET .text.EPT_PWM_Config .text.EPT_PWMX_Output_Control .text.EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config .text.ADC12_RESET_VALUE .text.ADC12_Control .text.ADC12_CMD.part.0 .text.ADC12_CLK_CMD .text.ADC12_Software_Reset .text.ADC12_CMD .text.ADC12_ready_wait .text.ADC12_SEQEND_wait .text.ADC12_DATA_OUPUT .text.ADC12_Configure_Mode .text.ADC12_Configure_VREF_Selecte .text.ADC12_ConversionChannel_Config .text.Page_ProgramData .text.ReadDataArry_U8 .text.startup.main .text.delay_nms .text.GPIO_CONFIG .text.EPT0_CONFIG .text.BT_CONFIG .text.ADC12_CONFIG .text.GPT0_CONFIG .text.SYSCON_CONFIG .text.APT32F102_init .text.SYSCONIntHandler .text.IFCIntHandler .text.ADCIntHandler .text.EPT0IntHandler .text.WWDTHandler .text.GPT0IntHandler .text.RTCIntHandler .text.UART0IntHandler .text.UART1IntHandler .text.UART2IntHandler .text.SPI0IntHandler .text.SIO0IntHandler .text.EXI0IntHandler .text.EXI1IntHandler .text.EXI2to3IntHandler .text.EXI4to9IntHandler .text.EXI10to15IntHandler .text.LPTIntHandler .text.BT0IntHandler .text.BT1IntHandler .text.PriviledgeVioHandler .text.PendTrapHandler .text.Trap3Handler .text.Trap2Handler .text.Trap1Handler .text.Trap0Handler .text.UnrecExecpHandler .text.BreakPointHandler .text.AccessErrHandler .text.IllegalInstrHandler .text.MisalignedHandler .text.TKEYIntHandler .text.CNTAIntHandler .text.I2CIntHandler .text.CORETHandler .text.__divsi3 .text.__udivsi3 .text.CK_CPU_EnAllNormalIrq .text.UARTx_Init .text.UART1_RecvINT_Processing .text.UART1_TASK .text.Dbg_Println .text.Dbg_Print_Buff .text.PB_Set_Power_State.part.1 .text.PB_Set_SaveCurrent .text.PB_Init .text.PB_Set_Power_State .text.PB_Soft_Boot_Task .text.PowerBus_Data_Encoding .text.PB_Send_String_INT .text.PowerBus_Data_Send .text.PB_CheckSum .text.PB_OVERCURR_PWR_BUS_INT_Processing .text.PB_Protect_Task .text.PB_Scan_State_Task .text.PowerBus_FillSendBuff .text.PowerBus_PackFillBuff .text.PowerBUS_GetCommState .text.PB_FilACkPacket .text.PB_RS485_ReplyAck .text.PB_Set_CH_SaveBrightnessInfo .text.PB_Set_CH_SaveSwitchInfo .text.PB_ACK_SET_LED_BRIGHTNESS .text.PB_ACK_SET_STRIP_SWITCH .text.PB_ACK_SET_STRIP_ADJUST .text.PB_ACK_SET_PIRTIGGLE_LED .text.PB_ACK_SET_SaveCurrInfo .text.PB_ACK_SET_UniversPara .text.PB_ACK_SET_PowerBus_EnablePara .text.PB_ACK_PassThroug_Data .text.PB_ACK_SET_PB_LEDS_BRIGHTNESS .text.PB_ACK_SET_PB_LEDS_ADJUST .text.PB_ACK_SET_PB_LEDS_SWITCH .text.PB_ACK_SET_PB_LEDS_BRIGHT .text.PB_ACK_SET_PB_LED_BRIGHTNESS .text.PB_ACK_SET_PB_LED_Adjust .text.PB_ACK_SET_PB_LED_SWITCH .text.PB_ACK_SET_PB_ALLLED_Switch .text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS .text.PB_ACK_SET_PB_STRIPS_ADJUST .text.PB_ACK_SET_PB_STRIPS_SWITCH .text.PB_ACK_SET_PB_STRIP_SWITCH .text.PB_ACK_SET_PB_STRIP_BRIGHTNESS .text.PB_ACK_SET_PB_STRIP_Adjust .text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST .text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST .text.PB_ACK_SET_PB_ALLSTRIP_Switch .text.PB_ACK_SET_PB_RELAYS_SWITCH .text.PB_ACK_SET_PB_ALLRELAY_SWITCH .text.PB_ACK_SET_PB_RELAY_SWITCH .text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH .text.Get_ADC_Val_Filter .text.Get_PB_CURR_VAL .text.PB_ACK_GET_STATE .text.Current_Coarse_Filter .text.Current_Fine_Filter .text.PB_Current_Monitoring_Meas .text.PMU_MEAS_Task .text.Set_PB_CurrMonitoring_Dead .text.PowerBus_SendBuffer_Task .text.PB_ACK_SET_CurrTiggleStrip .text.BLV_PB_Control_Protocol_Processing .text.PB_Task .text.PWM_SetOutDuty .text.PWM_SetCHGradualTime .text.PWM_SetOutBrightness .text.PWM_Init .text.PWM_SetUpLimitVal .text.PWM_SetDownLimitVal .text.Pwm_SetOnOffState .text.Pwm_SetAllBrightness .text.PWM_SetAutoAdjust .text.PWM_Timer_1ms_Task .text.EEPROM_ReadParaInfo .text.EEPROM_WriteParaInfo .text.EEPROM_Validate_ParaInfo .text.EEPROM_Default_ParaInfo .text.EEPROM_Init .text.std_clk_calib .rodata + 01 .data .bss +====================================================================== +Csky GNU Linker + +====================================================================== + +Section Cross References + + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.EXTI_interrupt_CMD) for EXTI_interrupt_CMD + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.GPIO_EXTI_interrupt) for GPIO_EXTI_interrupt + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.EXI1_Int_Enable) for EXI1_Int_Enable + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_RST_VALUE) for SYSCON_RST_VALUE + Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_HFOSC_SELECTE) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_General_CMD) for SYSCON_General_CMD + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_General_CMD) for SYSCON_General_CMD + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SystemCLK_HCLKDIV_PCLKDIV_Config) for SystemCLK_HCLKDIV_PCLKDIV_Config + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_HFOSC_SELECTE) for SYSCON_HFOSC_SELECTE + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_WDT_CMD) for SYSCON_WDT_CMD + Obj/main.o(.text.startup.main) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_IWDCNT_Reload) for SYSCON_IWDCNT_Reload + Obj/mcu_initial.o(.text.delay_nms) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_IWDCNT_Reload) for SYSCON_IWDCNT_Reload + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_IWDCNT_Reload) for SYSCON_IWDCNT_Reload + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_IWDCNT_Config) for SYSCON_IWDCNT_Config + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_LVD_Config) for SYSCON_LVD_Config + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.LVD_Int_Enable) for LVD_Int_Enable + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.IWDT_Int_Enable) for IWDT_Int_Enable + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.EXTI_trigger_CMD) for EXTI_trigger_CMD + Obj/mcu_interrupt.o(.text.EPT0IntHandler) refers to Obj/FWlib_apt32f102_syscon.o(.text.EXTI_trigger_CMD) for EXTI_trigger_CMD + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_Int_Enable) for SYSCON_Int_Enable + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/FWlib_apt32f102_syscon.o(.text.SYSCON_INT_Priority) for SYSCON_INT_Priority + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_syscon.o(.text.Set_INT_Priority) for Set_INT_Priority + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/FWlib_apt32f102_syscon.o(.text.Set_INT_Priority) for Set_INT_Priority + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_Low) for GPIO_Write_Low + Obj/SYSTEM_pb_fun.o(.text.PB_Set_Power_State.part.1) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_Low) for GPIO_Write_Low + Obj/SYSTEM_pb_fun.o(.text.PB_Soft_Boot_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_Low) for GPIO_Write_Low + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_Low) for GPIO_Write_Low + Obj/SYSTEM_pb_fun.o(.text.PB_Protect_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Read_Status) for GPIO_Read_Status + Obj/SYSTEM_pb_fun.o(.text.PB_Scan_State_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Read_Status) for GPIO_Read_Status + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Init) for GPIO_Init + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_DriveStrength_EN) for GPIO_DriveStrength_EN + Obj/mcu_initial.o(.text.GPIO_CONFIG) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_IntGroup_Set) for GPIO_IntGroup_Set + Obj/SYSTEM_pb_fun.o(.text.PB_Soft_Boot_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_High) for GPIO_Write_High + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Write_High) for GPIO_Write_High + FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) refers to Obj/FWlib_apt32f102_lpt.o(.text.LPT_Soft_Reset) for LPT_Soft_Reset + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_wwdt.o(.text.WWDT_CONFIG) for WWDT_CONFIG + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_wwdt.o(.text.WWDT_CNT_Load) for WWDT_CNT_Load + Obj/mcu_interrupt.o(.text.WWDTHandler) refers to Obj/FWlib_apt32f102_wwdt.o(.text.WWDT_CNT_Load) for WWDT_CNT_Load + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to Obj/FWlib_apt32f102_wwdt.o(.text.WWDT_Int_Config) for WWDT_Int_Config + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT1_INT_ENABLE) for BT1_INT_ENABLE + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_DeInit) for BT_DeInit + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_IO_Init) for BT_IO_Init + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_Start) for BT_Start + FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_Soft_Reset) for BT_Soft_Reset + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_Configure) for BT_Configure + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_ControlSet_Configure) for BT_ControlSet_Configure + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_Period_CMP_Write) for BT_Period_CMP_Write + Obj/SYSTEM_pb_fun.o(.text.PB_Set_SaveCurrent) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_Period_CMP_Write) for BT_Period_CMP_Write + Obj/mcu_initial.o(.text.BT_CONFIG) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_ConfigInterrupt_CMD) for BT_ConfigInterrupt_CMD + FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) refers to Obj/FWlib_apt32f102_bt.o(.text.BT_ConfigInterrupt_CMD) for BT_ConfigInterrupt_CMD + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_Configure) for GPT_Configure + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_WaveCtrl_Configure) for GPT_WaveCtrl_Configure + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_Start) for GPT_Start + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_Period_CMP_Write) for GPT_Period_CMP_Write + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_ConfigInterrupt_CMD) for GPT_ConfigInterrupt_CMD + Obj/mcu_initial.o(.text.GPT0_CONFIG) refers to Obj/FWlib_apt32f102_gpt.o(.text.GPT_INT_ENABLE) for GPT_INT_ENABLE + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART0_DeInit) for UART0_DeInit + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART1_DeInit) for UART1_DeInit + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART2_DeInit) for UART2_DeInit + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART0_Int_Enable) for UART0_Int_Enable + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART1_Int_Enable) for UART1_Int_Enable + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UART_IO_Init) for UART_IO_Init + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to Obj/FWlib_apt32f102_uart.o(.text.UARTInitRxTxIntEn) for UARTInitRxTxIntEn + Obj/SYSTEM_pb_fun.o(.text.PowerBus_Data_Send) refers to Obj/FWlib_apt32f102_uart.o(.text.UARTTxByte) for UARTTxByte + Obj/SYSTEM_pb_fun.o(.text.PB_RS485_ReplyAck) refers to Obj/FWlib_apt32f102_uart.o(.text.UARTTransmit) for UARTTransmit + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_Software_Prg) for EPT_Software_Prg + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_Start) for EPT_Start + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_IO_SET) for EPT_IO_SET + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_PWM_Config) for EPT_PWM_Config + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_PWMX_Output_Control) for EPT_PWMX_Output_Control + Obj/mcu_initial.o(.text.EPT0_CONFIG) refers to Obj/FWlib_apt32f102_ept.o(.text.EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config) for EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_RESET_VALUE) for ADC12_RESET_VALUE + Obj/FWlib_apt32f102_adc.o(.text.ADC12_CMD.part.0) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Control) for ADC12_Control + Obj/FWlib_apt32f102_adc.o(.text.ADC12_Software_Reset) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Control) for ADC12_Control + Obj/FWlib_apt32f102_adc.o(.text.ADC12_CMD) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Control) for ADC12_Control + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Control) for ADC12_Control + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_CLK_CMD) for ADC12_CLK_CMD + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Software_Reset) for ADC12_Software_Reset + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_CMD) for ADC12_CMD + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_ready_wait) for ADC12_ready_wait + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_SEQEND_wait) for ADC12_SEQEND_wait + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_DATA_OUPUT) for ADC12_DATA_OUPUT + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Configure_Mode) for ADC12_Configure_Mode + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_Configure_VREF_Selecte) for ADC12_Configure_VREF_Selecte + Obj/mcu_initial.o(.text.ADC12_CONFIG) refers to Obj/FWlib_apt32f102_adc.o(.text.ADC12_ConversionChannel_Config) for ADC12_ConversionChannel_Config + Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) refers to Obj/FWlib_apt32f102_ifc.o(.text.Page_ProgramData) for Page_ProgramData + Obj/SYSTEM_eeprom.o(.text.EEPROM_ReadParaInfo) refers to Obj/FWlib_apt32f102_ifc.o(.text.ReadDataArry_U8) for ReadDataArry_U8 + Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) refers to Obj/mcu_initial.o(.text.delay_nms) for delay_nms + FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) refers to Obj/mcu_initial.o(.text.delay_nms) for delay_nms + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.GPIO_CONFIG) for GPIO_CONFIG + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.EPT0_CONFIG) for EPT0_CONFIG + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.BT_CONFIG) for BT_CONFIG + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.ADC12_CONFIG) for ADC12_CONFIG + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.GPT0_CONFIG) for GPT0_CONFIG + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/mcu_initial.o(.text.SYSCON_CONFIG) for SYSCON_CONFIG + Obj/main.o(.text.startup.main) refers to Obj/mcu_initial.o(.text.APT32F102_init) for APT32F102_init + Obj/SYSTEM_pb_fun.o(.text.PB_Set_SaveCurrent) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_CurrTiggleStrip) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pwm.o(.text.PWM_SetAutoAdjust) refers to Obj/drivers_apt32f102.o(.text.__divsi3) for __divsi3 + Obj/SYSTEM_pb_fun.o(.text.Get_ADC_Val_Filter) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/SYSTEM_pb_fun.o(.text.Current_Coarse_Filter) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/SYSTEM_pb_fun.o(.text.Current_Fine_Filter) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/SYSTEM_pwm.o(.text.PWM_Init) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/SYSTEM_pwm.o(.text.PWM_SetUpLimitVal) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/SYSTEM_pwm.o(.text.PWM_SetDownLimitVal) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) refers to Obj/drivers_apt32f102.o(.text.__udivsi3) for __udivsi3 + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/drivers_apt32f102_ck801.o(.text.CK_CPU_EnAllNormalIrq) for CK_CPU_EnAllNormalIrq + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/SYSTEM_uart.o(.text.UARTx_Init) for UARTx_Init + Obj/mcu_interrupt.o(.text.UART1IntHandler) refers to Obj/SYSTEM_uart.o(.text.UART1_RecvINT_Processing) for UART1_RecvINT_Processing + Obj/main.o(.text.startup.main) refers to Obj/SYSTEM_uart.o(.text.UART1_TASK) for UART1_TASK + Obj/main.o(.text.startup.main) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_Soft_Boot_Task) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_Protect_Task) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PIRTIGGLE_LED) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_SaveCurrInfo) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PowerBus_EnablePara) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_PassThroug_Data) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHT) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_Adjust) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLLED_Switch) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_Adjust) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLSTRIP_Switch) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAYS_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLRELAY_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_CurrTiggleStrip) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pwm.o(.text.PWM_Init) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_eeprom.o(.text.EEPROM_Validate_ParaInfo) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) refers to Obj/SYSTEM_uart.o(.text.Dbg_Println) for Dbg_Println + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to Obj/SYSTEM_uart.o(.text.Dbg_Print_Buff) for Dbg_Print_Buff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Print_Buff) for Dbg_Print_Buff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) refers to Obj/SYSTEM_uart.o(.text.Dbg_Print_Buff) for Dbg_Print_Buff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) refers to Obj/SYSTEM_uart.o(.text.Dbg_Print_Buff) for Dbg_Print_Buff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) refers to Obj/SYSTEM_uart.o(.text.Dbg_Print_Buff) for Dbg_Print_Buff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Set_CH_SaveSwitchInfo) for PB_Set_CH_SaveSwitchInfo + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) for PB_ACK_SET_LED_BRIGHTNESS + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_SWITCH) for PB_ACK_SET_STRIP_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_ADJUST) for PB_ACK_SET_STRIP_ADJUST + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PIRTIGGLE_LED) for PB_ACK_SET_PIRTIGGLE_LED + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_SaveCurrInfo) for PB_ACK_SET_SaveCurrInfo + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) for PB_ACK_SET_UniversPara + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PowerBus_EnablePara) for PB_ACK_SET_PowerBus_EnablePara + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_PassThroug_Data) for PB_ACK_PassThroug_Data + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHTNESS) for PB_ACK_SET_PB_LEDS_BRIGHTNESS + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_ADJUST) for PB_ACK_SET_PB_LEDS_ADJUST + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_SWITCH) for PB_ACK_SET_PB_LEDS_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHT) for PB_ACK_SET_PB_LEDS_BRIGHT + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_BRIGHTNESS) for PB_ACK_SET_PB_LED_BRIGHTNESS + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_Adjust) for PB_ACK_SET_PB_LED_Adjust + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_SWITCH) for PB_ACK_SET_PB_LED_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLLED_Switch) for PB_ACK_SET_PB_ALLLED_Switch + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) for PB_ACK_SET_PB_STRIPS_BRIGHTNESS + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) for PB_ACK_SET_PB_STRIPS_ADJUST + Obj/SYSTEM_pb_fun.o(.text.PB_Init) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Set_SaveCurrent) for PB_Set_SaveCurrent + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_SaveCurrInfo) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Set_SaveCurrent) for PB_Set_SaveCurrent + Obj/main.o(.text.startup.main) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Init) for PB_Init + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PowerBus_EnablePara) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Set_Power_State) for PB_Set_Power_State + Obj/SYSTEM_pb_fun.o(.text.PB_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Soft_Boot_Task) for PB_Soft_Boot_Task + Obj/SYSTEM_pb_fun.o(.text.PowerBus_Data_Send) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_Data_Encoding) for PowerBus_Data_Encoding + Obj/mcu_interrupt.o(.text.UART0IntHandler) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Send_String_INT) for PB_Send_String_INT + Obj/SYSTEM_pb_fun.o(.text.PowerBus_SendBuffer_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_Data_Send) for PowerBus_Data_Send + Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) refers to Obj/SYSTEM_pb_fun.o(.text.PB_CheckSum) for PB_CheckSum + Obj/SYSTEM_pb_fun.o(.text.PB_FilACkPacket) refers to Obj/SYSTEM_pb_fun.o(.text.PB_CheckSum) for PB_CheckSum + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_CheckSum) for PB_CheckSum + Obj/SYSTEM_eeprom.o(.text.EEPROM_ReadParaInfo) refers to Obj/SYSTEM_pb_fun.o(.text.PB_CheckSum) for PB_CheckSum + Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) refers to Obj/SYSTEM_pb_fun.o(.text.PB_CheckSum) for PB_CheckSum + Obj/mcu_interrupt.o(.text.EXI1IntHandler) refers to Obj/SYSTEM_pb_fun.o(.text.PB_OVERCURR_PWR_BUS_INT_Processing) for PB_OVERCURR_PWR_BUS_INT_Processing + Obj/SYSTEM_pb_fun.o(.text.PB_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Protect_Task) for PB_Protect_Task + Obj/mcu_interrupt.o(.text.BT1IntHandler) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Scan_State_Task) for PB_Scan_State_Task + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_PassThroug_Data) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_FillSendBuff) for PowerBus_FillSendBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PIRTIGGLE_LED) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHT) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_Adjust) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLLED_Switch) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_Adjust) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLSTRIP_Switch) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAYS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLRELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) for PowerBus_PackFillBuff + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_PassThroug_Data) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LEDS_BRIGHT) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_Adjust) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_LED_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLLED_Switch) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_Adjust) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLSTRIP_Switch) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAYS_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLRELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBUS_GetCommState) for PowerBUS_GetCommState + Obj/SYSTEM_pb_fun.o(.text.PB_RS485_ReplyAck) refers to Obj/SYSTEM_pb_fun.o(.text.PB_FilACkPacket) for PB_FilACkPacket + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_RS485_ReplyAck) for PB_RS485_ReplyAck + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Set_CH_SaveBrightnessInfo) for PB_Set_CH_SaveBrightnessInfo + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) for PB_ACK_SET_PB_STRIPS_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_SWITCH) for PB_ACK_SET_PB_STRIP_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_BRIGHTNESS) for PB_ACK_SET_PB_STRIP_BRIGHTNESS + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_Adjust) for PB_ACK_SET_PB_STRIP_Adjust + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) for PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST) for PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLSTRIP_Switch) for PB_ACK_SET_PB_ALLSTRIP_Switch + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAYS_SWITCH) for PB_ACK_SET_PB_RELAYS_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_ALLRELAY_SWITCH) for PB_ACK_SET_PB_ALLRELAY_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_SWITCH) for PB_ACK_SET_PB_RELAY_SWITCH + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH) for PB_ACK_SET_PB_RELAY_DELAY_SWITCH + Obj/SYSTEM_pb_fun.o(.text.Get_PB_CURR_VAL) refers to Obj/SYSTEM_pb_fun.o(.text.Get_ADC_Val_Filter) for Get_ADC_Val_Filter + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/SYSTEM_pb_fun.o(.text.Get_ADC_Val_Filter) for Get_ADC_Val_Filter + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) refers to Obj/SYSTEM_pb_fun.o(.text.Get_PB_CURR_VAL) for Get_PB_CURR_VAL + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/SYSTEM_pb_fun.o(.text.Get_PB_CURR_VAL) for Get_PB_CURR_VAL + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_GET_STATE) for PB_ACK_GET_STATE + Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) refers to Obj/SYSTEM_pb_fun.o(.text.Current_Coarse_Filter) for Current_Coarse_Filter + Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) refers to Obj/SYSTEM_pb_fun.o(.text.Current_Fine_Filter) for Current_Fine_Filter + Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) for PB_Current_Monitoring_Meas + Obj/SYSTEM_pb_fun.o(.text.PB_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PMU_MEAS_Task) for PMU_MEAS_Task + Obj/SYSTEM_pb_fun.o(.text.PowerBus_SendBuffer_Task) refers to Obj/SYSTEM_pb_fun.o(.text.Set_PB_CurrMonitoring_Dead) for Set_PB_CurrMonitoring_Dead + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_CurrTiggleStrip) refers to Obj/SYSTEM_pb_fun.o(.text.Set_PB_CurrMonitoring_Dead) for Set_PB_CurrMonitoring_Dead + Obj/SYSTEM_pb_fun.o(.text.PB_Task) refers to Obj/SYSTEM_pb_fun.o(.text.PowerBus_SendBuffer_Task) for PowerBus_SendBuffer_Task + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_CurrTiggleStrip) for PB_ACK_SET_CurrTiggleStrip + Obj/main.o(.text.startup.main) refers to Obj/SYSTEM_pb_fun.o(.text.PB_Task) for PB_Task + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutDuty) for PWM_SetOutDuty + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetCHGradualTime) for PWM_SetCHGradualTime + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pb_fun.o(.text.PB_Current_Monitoring_Meas) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pwm.o(.text.PWM_Init) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pwm.o(.text.PWM_SetUpLimitVal) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pwm.o(.text.PWM_SetDownLimitVal) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pwm.o(.text.Pwm_SetOnOffState) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/SYSTEM_pwm.o(.text.Pwm_SetAllBrightness) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) for PWM_SetOutBrightness + Obj/main.o(.text.startup.main) refers to Obj/SYSTEM_pwm.o(.text.PWM_Init) for PWM_Init + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetUpLimitVal) for PWM_SetUpLimitVal + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetDownLimitVal) for PWM_SetDownLimitVal + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_SWITCH) refers to Obj/SYSTEM_pwm.o(.text.Pwm_SetOnOffState) for Pwm_SetOnOffState + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_pwm.o(.text.Pwm_SetAllBrightness) for Pwm_SetAllBrightness + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_ADJUST) refers to Obj/SYSTEM_pwm.o(.text.PWM_SetAutoAdjust) for PWM_SetAutoAdjust + Obj/mcu_interrupt.o(.text.GPT0IntHandler) refers to Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) for PWM_Timer_1ms_Task + Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_ReadParaInfo) for EEPROM_ReadParaInfo + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_LED_BRIGHTNESS) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) for EEPROM_WriteParaInfo + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_STRIP_SWITCH) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) for EEPROM_WriteParaInfo + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_SaveCurrInfo) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) for EEPROM_WriteParaInfo + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_UniversPara) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) for EEPROM_WriteParaInfo + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PowerBus_EnablePara) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) for EEPROM_WriteParaInfo + Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_Validate_ParaInfo) for EEPROM_Validate_ParaInfo + Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_Default_ParaInfo) for EEPROM_Default_ParaInfo + Obj/mcu_initial.o(.text.APT32F102_init) refers to Obj/SYSTEM_eeprom.o(.text.EEPROM_Init) for EEPROM_Init + Obj/mcu_initial.o(.text.SYSCON_CONFIG) refers to FWlib_apt32f102_clkcalib.o(.text.std_clk_calib) for std_clk_calib + Obj/FWlib_apt32f102_gpio.o(.text.GPIO_Init) refers to _csky_case_uqi.o(.text) for ___gnu_csky_case_uqi + Obj/FWlib_apt32f102_adc.o(.text.ADC12_ConversionChannel_Config) refers to _csky_case_uqi.o(.text) for ___gnu_csky_case_uqi + Obj/SYSTEM_pb_fun.o(.text.PB_Set_CH_SaveBrightnessInfo) refers to _csky_case_uqi.o(.text) for ___gnu_csky_case_uqi + Obj/SYSTEM_pb_fun.o(.text.PB_Set_CH_SaveSwitchInfo) refers to _csky_case_uqi.o(.text) for ___gnu_csky_case_uqi + Obj/SYSTEM_pwm.o(.text.PWM_SetOutDuty) refers to _csky_case_uqi.o(.text) for ___gnu_csky_case_uqi + Obj/SYSTEM_pb_fun.o(.text.BLV_PB_Control_Protocol_Processing) refers to _csky_case_shi.o(.text) for ___gnu_csky_case_shi + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _fixunssfsi.o(.text) for __fixunssfsi + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _addsub_sf.o(.text) for __addsf3 + _fixunssfsi.o(.text) refers to _addsub_sf.o(.text) for __subsf3 + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _addsub_sf.o(.text) for __subsf3 + _fixunssfsi.o(.text) refers to _ge_sf.o(.text) for __gesf2 + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _ge_sf.o(.text) for __gesf2 + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _le_sf.o(.text) for __lesf2 + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _si_to_sf.o(.text) for __floatsisf + _fixunssfsi.o(.text) refers to _sf_to_si.o(.text) for __fixsfsi + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _sf_to_df.o(.text) for __extendsfdf2 + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _usi_to_sf.o(.text) for __floatunsisf + Obj/SYSTEM_pwm.o(.text.PWM_Timer_1ms_Task) refers to _usi_to_sf.o(.text) for __floatunsisf + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _div_df.o(.text) for __divdf3 + Obj/SYSTEM_pwm.o(.text.PWM_SetAutoAdjust) refers to _div_df.o(.text) for __divdf3 + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _si_to_df.o(.text) for __floatsidf + Obj/SYSTEM_pwm.o(.text.PWM_SetAutoAdjust) refers to _si_to_df.o(.text) for __floatsidf + _sf_to_df.o(.text) refers to _make_df.o(.text) for __make_dp + Obj/SYSTEM_pwm.o(.text.PWM_SetOutBrightness) refers to _df_to_sf.o(.text) for __truncdfsf2 + Obj/SYSTEM_pwm.o(.text.PWM_SetAutoAdjust) refers to _df_to_sf.o(.text) for __truncdfsf2 + _si_to_sf.o(.text) refers to _clzsi2.o(.text) for __clzsi2 + _usi_to_sf.o(.text) refers to _clzsi2.o(.text) for __clzsi2 + _si_to_df.o(.text) refers to _clzsi2.o(.text) for __clzsi2 + _addsub_sf.o(.text) refers to _pack_sf.o(.text) for __pack_f + _addsub_sf.o(.text) refers to _pack_sf.o(.text) for __pack_f + _si_to_sf.o(.text) refers to _pack_sf.o(.text) for __pack_f + _usi_to_sf.o(.text) refers to _pack_sf.o(.text) for __pack_f + _make_sf.o(.text) refers to _pack_sf.o(.text) for __pack_f + _addsub_sf.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _addsub_sf.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _ge_sf.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _le_sf.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _sf_to_si.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _sf_to_df.o(.text) refers to _unpack_sf.o(.text) for __unpack_f + _ge_sf.o(.text) refers to _fpcmp_parts_sf.o(.text) for __fpcmp_parts_f + _le_sf.o(.text) refers to _fpcmp_parts_sf.o(.text) for __fpcmp_parts_f + _df_to_sf.o(.text) refers to _make_sf.o(.text) for __make_fp + _div_df.o(.text) refers to _pack_df.o(.text) for __pack_d + _si_to_df.o(.text) refers to _pack_df.o(.text) for __pack_d + _make_df.o(.text) refers to _pack_df.o(.text) for __pack_d + _div_df.o(.text) refers to _unpack_df.o(.text) for __unpack_d + _df_to_sf.o(.text) refers to _unpack_df.o(.text) for __unpack_d + Obj/arch_mem_init.o(.text.__main) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_uart.o(.text.UARTx_Init) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_uart.o(.text.UART1_TASK) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PB_Init) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PowerBus_Data_Send) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_ADJUST) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_SWITCH) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_pwm.o(.text.PWM_Init) refers to memset_fast.o(.text) for memset + Obj/SYSTEM_eeprom.o(.text.EEPROM_ReadParaInfo) refers to memset_fast.o(.text) for memset + Obj/arch_mem_init.o(.text.__main) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_uart.o(.text.UART1_TASK) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_pb_fun.o(.text.PowerBus_FillSendBuff) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_pb_fun.o(.text.PowerBus_PackFillBuff) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_pb_fun.o(.text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_eeprom.o(.text.EEPROM_ReadParaInfo) refers to memcpy_fast.o(.text) for memcpy + Obj/SYSTEM_eeprom.o(.text.EEPROM_WriteParaInfo) refers to memcpy_fast.o(.text) for memcpy + + +====================================================================== + +Removing Unused input sections from the image. + + Removing .data(Obj/arch_crt0.o), (4 bytes). + Removing .bss(Obj/arch_crt0.o), (0 bytes). + Removing .text(Obj/arch_mem_init.o), (0 bytes). + Removing .data(Obj/arch_mem_init.o), (0 bytes). + Removing .bss(Obj/arch_mem_init.o), (0 bytes). + Removing .text(Obj/arch_apt32f102_iostring.o), (0 bytes). + Removing .data(Obj/arch_apt32f102_iostring.o), (0 bytes). + Removing .bss(Obj/arch_apt32f102_iostring.o), (0 bytes). + Removing .text.__putchar__(Obj/arch_apt32f102_iostring.o), (16 bytes). + Removing .text.myitoa(Obj/arch_apt32f102_iostring.o), (140 bytes). + Removing .text.my_printf(Obj/arch_apt32f102_iostring.o), (198 bytes). + Removing .debug_info(Obj/arch_apt32f102_iostring.o), (7541 bytes). + Removing .debug_abbrev(Obj/arch_apt32f102_iostring.o), (485 bytes). + Removing .debug_loc(Obj/arch_apt32f102_iostring.o), (653 bytes). + Removing .debug_aranges(Obj/arch_apt32f102_iostring.o), (48 bytes). + Removing .debug_ranges(Obj/arch_apt32f102_iostring.o), (32 bytes). + Removing .debug_line(Obj/arch_apt32f102_iostring.o), (491 bytes). + Removing .debug_str(Obj/arch_apt32f102_iostring.o), (2892 bytes). + Removing .comment(Obj/arch_apt32f102_iostring.o), (67 bytes). + Removing .debug_frame(Obj/arch_apt32f102_iostring.o), (120 bytes). + Removing .csky.attributes(Obj/arch_apt32f102_iostring.o), (32 bytes). + Removing .text(Obj/FWlib_apt32f102_syscon.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_syscon.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_syscon.o), (0 bytes). + Removing .text.EMOSC_OSTR_Config(Obj/FWlib_apt32f102_syscon.o), (28 bytes). + Removing .text.SystemCLK_Clear(Obj/FWlib_apt32f102_syscon.o), (24 bytes). + Removing .text.SYSCON_IMOSC_SELECTE(Obj/FWlib_apt32f102_syscon.o), (20 bytes). + Removing .text.LVD_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.IWDT_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.Read_Reset_Status(Obj/FWlib_apt32f102_syscon.o), (24 bytes). + Removing .text.PCLK_goto_idle_mode(Obj/FWlib_apt32f102_syscon.o), (6 bytes). + Removing .text.PCLK_goto_deepsleep_mode(Obj/FWlib_apt32f102_syscon.o), (20 bytes). + Removing .text.EXI0_Int_Enable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.EXI0_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.EXI1_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI2_Int_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI2_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI3_Int_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI3_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI4_Int_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI4_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI0_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.EXI0_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.EXI1_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI1_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI2_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI2_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI3_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI3_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI4_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.EXI4_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.SYSCON_Int_Disable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.SYSCON_WakeUp_Enable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.SYSCON_CLO_CONFIG(Obj/FWlib_apt32f102_syscon.o), (52 bytes). + Removing .text.SYSCON_CLO_SRC_SET(Obj/FWlib_apt32f102_syscon.o), (32 bytes). + Removing .text.SYSCON_WakeUp_Disable(Obj/FWlib_apt32f102_syscon.o), (12 bytes). + Removing .text.SYSCON_Read_CINF0(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.SYSCON_Read_CINF1(Obj/FWlib_apt32f102_syscon.o), (16 bytes). + Removing .text.SYSCON_Software_Reset(Obj/FWlib_apt32f102_syscon.o), (20 bytes). + Removing .text.GPIO_Remap(Obj/FWlib_apt32f102_syscon.o), (652 bytes). + Removing .text(Obj/FWlib_apt32f102_gpio.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_gpio.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_gpio.o), (0 bytes). + Removing .text.GPIO_DeInit(Obj/FWlib_apt32f102_gpio.o), (100 bytes). + Removing .text.GPIO_Init2(Obj/FWlib_apt32f102_gpio.o), (16 bytes). + Removing .text.GPIO_InPutOutPut_Disable(Obj/FWlib_apt32f102_gpio.o), (164 bytes). + Removing .text.GPIO_MODE_Init(Obj/FWlib_apt32f102_gpio.o), (34 bytes). + Removing .text.GPIO_PullHigh_Init(Obj/FWlib_apt32f102_gpio.o), (20 bytes). + Removing .text.GPIO_PullLow_Init(Obj/FWlib_apt32f102_gpio.o), (20 bytes). + Removing .text.GPIO_PullHighLow_DIS(Obj/FWlib_apt32f102_gpio.o), (14 bytes). + Removing .text.GPIO_OpenDrain_EN(Obj/FWlib_apt32f102_gpio.o), (12 bytes). + Removing .text.GPIO_OpenDrain_DIS(Obj/FWlib_apt32f102_gpio.o), (14 bytes). + Removing .text.GPIO_TTL_COSM_Selecte(Obj/FWlib_apt32f102_gpio.o), (72 bytes). + Removing .text.GPIO_DriveStrength_DIS(Obj/FWlib_apt32f102_gpio.o), (16 bytes). + Removing .text.GPIOA0_EXI_Init(Obj/FWlib_apt32f102_gpio.o), (252 bytes). + Removing .text.GPIOB0_EXI_Init(Obj/FWlib_apt32f102_gpio.o), (108 bytes). + Removing .text.GPIO_EXI_EN(Obj/FWlib_apt32f102_gpio.o), (12 bytes). + Removing .text.GPIO_Set_Value(Obj/FWlib_apt32f102_gpio.o), (22 bytes). + Removing .text.GPIO_Reverse(Obj/FWlib_apt32f102_gpio.o), (22 bytes). + Removing .text.GPIO_Read_Output(Obj/FWlib_apt32f102_gpio.o), (16 bytes). + Removing .text(Obj/FWlib_apt32f102_lpt.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_lpt.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_lpt.o), (0 bytes). + Removing .text.LPT_DeInit(Obj/FWlib_apt32f102_lpt.o), (60 bytes). + Removing .text.LPT_IO_Init(Obj/FWlib_apt32f102_lpt.o), (72 bytes). + Removing .text.LPT_Configure(Obj/FWlib_apt32f102_lpt.o), (44 bytes). + Removing .text.LPT_Debug_Mode(Obj/FWlib_apt32f102_lpt.o), (24 bytes). + Removing .text.LPT_Period_CMP_Write(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_CNT_Write(Obj/FWlib_apt32f102_lpt.o), (12 bytes). + Removing .text.LPT_PRDR_Read(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_CMP_Read(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_CNT_Read(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_ControlSet_Configure(Obj/FWlib_apt32f102_lpt.o), (40 bytes). + Removing .text.LPT_SyncSet_Configure(Obj/FWlib_apt32f102_lpt.o), (24 bytes). + Removing .text.LPT_Trigger_Configure(Obj/FWlib_apt32f102_lpt.o), (72 bytes). + Removing .text.LPT_Trigger_EVPS(Obj/FWlib_apt32f102_lpt.o), (20 bytes). + Removing .text.LPT_Trigger_Cnt(Obj/FWlib_apt32f102_lpt.o), (20 bytes). + Removing .text.LPT_Soft_Trigger(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_Start(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_Stop(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_REARM_Write(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_REARM_Read(Obj/FWlib_apt32f102_lpt.o), (20 bytes). + Removing .text.LPT_ConfigInterrupt_CMD(Obj/FWlib_apt32f102_lpt.o), (28 bytes). + Removing .text.LPT_INT_ENABLE(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text.LPT_INT_DISABLE(Obj/FWlib_apt32f102_lpt.o), (16 bytes). + Removing .text(Obj/FWlib_apt32f102_crc.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_crc.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_crc.o), (0 bytes). + Removing .text.CRC_CMD(Obj/FWlib_apt32f102_crc.o), (24 bytes). + Removing .text.CRC_Soft_Reset(Obj/FWlib_apt32f102_crc.o), (16 bytes). + Removing .text.CRC_Configure(Obj/FWlib_apt32f102_crc.o), (36 bytes). + Removing .text.CRC_Seed_Write(Obj/FWlib_apt32f102_crc.o), (12 bytes). + Removing .text.CRC_Seed_Read(Obj/FWlib_apt32f102_crc.o), (12 bytes). + Removing .text.CRC_Datain(Obj/FWlib_apt32f102_crc.o), (12 bytes). + Removing .text.CRC_Result_Read(Obj/FWlib_apt32f102_crc.o), (12 bytes). + Removing .text.Chip_CRC_CRC32(Obj/FWlib_apt32f102_crc.o), (28 bytes). + Removing .text.Chip_CRC_CRC16(Obj/FWlib_apt32f102_crc.o), (52 bytes). + Removing .text.Chip_CRC_CRC8(Obj/FWlib_apt32f102_crc.o), (44 bytes). + Removing .debug_info(Obj/FWlib_apt32f102_crc.o), (7732 bytes). + Removing .debug_abbrev(Obj/FWlib_apt32f102_crc.o), (592 bytes). + Removing .debug_loc(Obj/FWlib_apt32f102_crc.o), (358 bytes). + Removing .debug_aranges(Obj/FWlib_apt32f102_crc.o), (104 bytes). + Removing .debug_ranges(Obj/FWlib_apt32f102_crc.o), (112 bytes). + Removing .debug_line(Obj/FWlib_apt32f102_crc.o), (350 bytes). + Removing .debug_str(Obj/FWlib_apt32f102_crc.o), (3086 bytes). + Removing .comment(Obj/FWlib_apt32f102_crc.o), (67 bytes). + Removing .debug_frame(Obj/FWlib_apt32f102_crc.o), (204 bytes). + Removing .csky.attributes(Obj/FWlib_apt32f102_crc.o), (32 bytes). + Removing .text(Obj/FWlib_apt32f102_wwdt.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_wwdt.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_wwdt.o), (0 bytes). + Removing .text.WWDT_DeInit(Obj/FWlib_apt32f102_wwdt.o), (28 bytes). + Removing .text.WWDT_CMD(Obj/FWlib_apt32f102_wwdt.o), (24 bytes). + Removing .text(Obj/FWlib_apt32f102_countera.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_countera.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_countera.o), (0 bytes). + Removing .text.COUNT_DeInit(Obj/FWlib_apt32f102_countera.o), (20 bytes). + Removing .text.COUNTA_Int_Enable(Obj/FWlib_apt32f102_countera.o), (16 bytes). + Removing .text.COUNTA_Int_Disable(Obj/FWlib_apt32f102_countera.o), (16 bytes). + Removing .text.COUNTA_Wakeup_Enable(Obj/FWlib_apt32f102_countera.o), (16 bytes). + Removing .text.COUNTA_Wakeup_Disable(Obj/FWlib_apt32f102_countera.o), (16 bytes). + Removing .text.COUNTA_Init(Obj/FWlib_apt32f102_countera.o), (60 bytes). + Removing .text.COUNTA_Config(Obj/FWlib_apt32f102_countera.o), (32 bytes). + Removing .text.COUNTA_Start(Obj/FWlib_apt32f102_countera.o), (20 bytes). + Removing .text.COUNTA_Stop(Obj/FWlib_apt32f102_countera.o), (16 bytes). + Removing .text.COUNTA_Data_Update(Obj/FWlib_apt32f102_countera.o), (20 bytes). + Removing .text.COUNTA_IO_Init(Obj/FWlib_apt32f102_countera.o), (80 bytes). + Removing .debug_info(Obj/FWlib_apt32f102_countera.o), (7799 bytes). + Removing .debug_abbrev(Obj/FWlib_apt32f102_countera.o), (381 bytes). + Removing .debug_loc(Obj/FWlib_apt32f102_countera.o), (336 bytes). + Removing .debug_aranges(Obj/FWlib_apt32f102_countera.o), (112 bytes). + Removing .debug_ranges(Obj/FWlib_apt32f102_countera.o), (96 bytes). + Removing .debug_line(Obj/FWlib_apt32f102_countera.o), (350 bytes). + Removing .debug_str(Obj/FWlib_apt32f102_countera.o), (3403 bytes). + Removing .comment(Obj/FWlib_apt32f102_countera.o), (67 bytes). + Removing .debug_frame(Obj/FWlib_apt32f102_countera.o), (224 bytes). + Removing .csky.attributes(Obj/FWlib_apt32f102_countera.o), (32 bytes). + Removing .text(Obj/FWlib_apt32f102_et.o), (0 bytes). + Removing .data(Obj/FWlib_apt32f102_et.o), (0 bytes). + Removing .bss(Obj/FWlib_apt32f102_et.o), (0 bytes). + Removing .text.ET_DeInit(Obj/FWlib_apt32f102_et.o), (40 bytes). + Removing .text.ET_ENABLE(Obj/FWlib_apt32f102_et.o), (16 bytes). + Removing .text.ET_DISABLE(Obj/FWlib_apt32f102_et.o), (16 bytes). + Removing .text.ET_SWTRG_CMD(Obj/FWlib_apt32f102_et.o), (28 bytes). + Removing .text.ET_CH0_SRCSEL(Obj/FWlib_apt32f102_et.o), (108 bytes). + Removing .text.ET_CH0_CONTROL(Obj/FWlib_apt32f102_et.o), (40 bytes). + Removing .text.ET_CH1_SRCSEL(Obj/FWlib_apt32f102_et.o), (108 bytes). + Removing .text.ET_CH1_CONTROL(Obj/FWlib_apt32f102_et.o), (40 bytes). + Removing .text.ET_CH2_SRCSEL(Obj/FWlib_apt32f102_et.o), (108 bytes). + Removing .text.ET_CH2_CONTROL(Obj/FWlib_apt32f102_et.o), (40 bytes). + Removing .text.ET_CHx_CONTROL(Obj/FWlib_apt32f102_et.o), (276 bytes). + Removing .debug_info(Obj/FWlib_apt32f102_et.o), (7781 bytes). + Removing .debug_abbrev(Obj/FWlib_apt32f102_et.o), (410 bytes). + Removing .debug_loc(Obj/FWlib_apt32f102_et.o), (1318 bytes). + Removing .debug_aranges(Obj/FWlib_apt32f102_et.o), (112 bytes). + Removing .debug_ranges(Obj/FWlib_apt32f102_et.o), (96 bytes). + Removing .debug_line(Obj/FWlib_apt32f102_et.o), (463 bytes). + Removing .debug_str(Obj/FWlib_apt32f102_et.o), (3148 bytes). + Removing .comment(Obj/FWlib_apt32f102_et.o), (67 bytes). + Removing .debug_frame(Obj/FWlib_apt32f102_et.o), (204 bytes). + Removing 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.text.GPT_CmpLoad_Configure(Obj/FWlib_apt32f102_gpt.o), (20 bytes). + Removing .text.GPT_Debug_Mode(Obj/FWlib_apt32f102_gpt.o), (24 bytes). + Removing .text.GPT_Stop(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_Soft_Reset(Obj/FWlib_apt32f102_gpt.o), (20 bytes). + Removing .text.GPT_Cap_Rearm(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_Mode_CMD(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_REARM_Write(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_REARM_Read(Obj/FWlib_apt32f102_gpt.o), (20 bytes). + Removing .text.GPT_PRDR_Read(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_CMPA_Read(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_CMPB_Read(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_CNT_Read(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text.GPT_INT_DISABLE(Obj/FWlib_apt32f102_gpt.o), (16 bytes). + Removing .text(Obj/FWlib_apt32f102_sio.o), (0 bytes). + Removing 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.text.Get_ADC_Val_Filter + $t 0x00004374 0 .text.Get_ADC_Val_Filter + $d 0x00004398 0 .text.Get_PB_CURR_VAL + $t 0x00004398 0 .text.Get_PB_CURR_VAL + $d 0x000043b4 0 .text.Get_PB_CURR_VAL + $d 0x000043c0 0 .text.PB_ACK_GET_STATE + $t 0x000043c0 0 .text.PB_ACK_GET_STATE + $d 0x00004490 0 .text.PB_ACK_GET_STATE + $d 0x000044a8 0 .text.Current_Coarse_Filter + $t 0x000044a8 0 .text.Current_Coarse_Filter + $d 0x000044cc 0 .text.Current_Coarse_Filter + $d 0x000044d0 0 .text.Current_Fine_Filter + $t 0x000044d0 0 .text.Current_Fine_Filter + $d 0x000044f8 0 .text.Current_Fine_Filter + $d 0x00004500 0 .text.PB_Current_Monitoring_Meas + $t 0x00004500 0 .text.PB_Current_Monitoring_Meas + $d 0x00004618 0 .text.PB_Current_Monitoring_Meas + $d 0x00004630 0 .text.PMU_MEAS_Task + $t 0x00004630 0 .text.PMU_MEAS_Task + $d 0x000047e0 0 .text.PMU_MEAS_Task + $d 0x00004820 0 .text.Set_PB_CurrMonitoring_Dead + $t 0x00004820 0 .text.Set_PB_CurrMonitoring_Dead + $d 0x0000482c 0 .text.Set_PB_CurrMonitoring_Dead + $d 0x00004830 0 .text.PowerBus_SendBuffer_Task + $t 0x00004830 0 .text.PowerBus_SendBuffer_Task + $d 0x0000489c 0 .text.PowerBus_SendBuffer_Task + $d 0x000048b0 0 .text.PB_ACK_SET_CurrTiggleStrip + $t 0x000048b0 0 .text.PB_ACK_SET_CurrTiggleStrip + $d 0x000049d8 0 .text.PB_ACK_SET_CurrTiggleStrip + $d 0x00004a1c 0 .text.BLV_PB_Control_Protocol_Processing + $t 0x00004a1c 0 .text.BLV_PB_Control_Protocol_Processing + $d 0x00004a9c 0 .text.BLV_PB_Control_Protocol_Processing + $t 0x00004b04 0 .text.BLV_PB_Control_Protocol_Processing + $d 0x00004ca4 0 .text.BLV_PB_Control_Protocol_Processing + $d 0x00004cc8 0 .text.PB_Task + $t 0x00004cc8 0 .text.PB_Task + $d 0x00004cdc 0 .text.PWM_SetOutDuty + $t 0x00004cdc 0 .text.PWM_SetOutDuty + $d 0x00004cf0 0 .text.PWM_SetOutDuty + $t 0x00004cf4 0 .text.PWM_SetOutDuty + $d 0x00004d04 0 .text.PWM_SetOutDuty + $d 0x00004d0c 0 .text.PWM_SetCHGradualTime + $t 0x00004d0c 0 .text.PWM_SetCHGradualTime + $d 0x00004d1c 0 .text.PWM_SetCHGradualTime + $d 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__func__.6280 0x000057eb O 27 .rodata + __func__.6291 0x00005806 O 42 .rodata + __func__.6298 0x00005830 O 36 .rodata + __func__.6305 0x00005854 O 30 .rodata + __func__.6312 0x00005872 O 28 .rodata + __func__.6319 0x0000588e O 30 .rodata + __func__.6326 0x000058ac O 27 .rodata + __func__.6333 0x000058c7 O 33 .rodata + NUM.5984 0x20000068 O 1 .bss + meas_tick.6391 0x20000078 O 4 .bss + + Global Symbols + + Symbol Name Value Type Size Section + vector_table 0x00000000 0 .text + __start 0x0000010c 0 .text + __exit 0x00000160 0 .text + __fail 0x00000176 0 .text + DummyHandler 0x00000184 0 .text + ___gnu_csky_case_uqi 0x000001b4 F 20 .text + ___gnu_csky_case_shi 0x000001c8 F 28 .text + __fixunssfsi 0x000001e4 F 46 .text + __addsf3 0x00000360 F 42 .text + __subsf3 0x0000038c F 50 .text + __gesf2 0x000003c0 F 56 .text + __lesf2 0x000003f8 F 54 .text + __floatsisf 0x00000430 F 100 .text + __fixsfsi 0x00000494 F 84 .text + __extendsfdf2 0x000004e8 F 36 .text + __floatunsisf 0x0000050c F 96 .text + __divdf3 0x0000056c F 340 .text + __floatsidf 0x000006c0 F 112 .text + __make_dp 0x00000730 F 40 .text + __truncdfsf2 0x00000758 F 48 .text + __clzsi2 0x00000788 F 64 .text + __pack_f 0x000007c8 F 184 .text + __unpack_f 0x00000880 F 132 .text + __fpcmp_parts_f 0x00000904 F 120 .text + __make_fp 0x0000097c F 22 .text + __pack_d 0x00000994 F 412 .text + __unpack_d 0x00000b30 F 196 .text + __memset_fast 0x00000bf4 w F 136 .text + memset 0x00000bf4 w F 136 .text + __memcpy_fast 0x00000c7c w F 100 .text + memcpy 0x00000c7c w F 100 .text + __main 0x00000ce0 F 56 .text.__main + SYSCON_RST_VALUE 0x00000d8c F 88 .text.SYSCON_RST_VALUE + SYSCON_General_CMD 0x00000de4 F 48 .text.SYSCON_General_CMD + SystemCLK_HCLKDIV_PCLKDIV_Config 0x00000e14 F 136 .text.SystemCLK_HCLKDIV_PCLKDIV_Config + SYSCON_HFOSC_SELECTE 0x00000e9c F 40 .text.SYSCON_HFOSC_SELECTE + SYSCON_WDT_CMD 0x00000ec4 F 60 .text.SYSCON_WDT_CMD + SYSCON_IWDCNT_Reload 0x00000f00 F 20 .text.SYSCON_IWDCNT_Reload + SYSCON_IWDCNT_Config 0x00000f14 F 24 .text.SYSCON_IWDCNT_Config + SYSCON_LVD_Config 0x00000f2c F 32 .text.SYSCON_LVD_Config + LVD_Int_Enable 0x00000f4c F 28 .text.LVD_Int_Enable + IWDT_Int_Enable 0x00000f68 F 28 .text.IWDT_Int_Enable + EXTI_trigger_CMD 0x00000f84 F 64 .text.EXTI_trigger_CMD + EXTI_interrupt_CMD 0x00000fc4 F 52 .text.EXTI_interrupt_CMD + GPIO_EXTI_interrupt 0x00000ff8 F 4 .text.GPIO_EXTI_interrupt + EXI1_Int_Enable 0x00000ffc F 16 .text.EXI1_Int_Enable + SYSCON_Int_Enable 0x0000100c F 12 .text.SYSCON_Int_Enable + SYSCON_INT_Priority 0x00001018 F 36 .text.SYSCON_INT_Priority + Set_INT_Priority 0x0000103c F 48 .text.Set_INT_Priority + GPIO_Init 0x0000106c F 224 .text.GPIO_Init + GPIO_DriveStrength_EN 0x0000114c F 14 .text.GPIO_DriveStrength_EN + GPIO_IntGroup_Set 0x0000115c F 268 .text.GPIO_IntGroup_Set + GPIO_Write_High 0x00001268 F 8 .text.GPIO_Write_High + GPIO_Write_Low 0x00001270 F 8 .text.GPIO_Write_Low + GPIO_Read_Status 0x00001278 F 16 .text.GPIO_Read_Status + LPT_Soft_Reset 0x00001288 F 20 .text.LPT_Soft_Reset + WWDT_CONFIG 0x0000129c F 24 .text.WWDT_CONFIG + WWDT_CNT_Load 0x000012b4 F 16 .text.WWDT_CNT_Load + WWDT_Int_Config 0x000012c4 F 52 .text.WWDT_Int_Config + BT_DeInit 0x000012f8 F 28 .text.BT_DeInit + BT_IO_Init 0x00001314 F 332 .text.BT_IO_Init + BT_Start 0x00001460 F 8 .text.BT_Start + BT_Soft_Reset 0x00001468 F 10 .text.BT_Soft_Reset + BT_Configure 0x00001472 F 24 .text.BT_Configure + BT_ControlSet_Configure 0x0000148a F 44 .text.BT_ControlSet_Configure + BT_Period_CMP_Write 0x000014b6 F 6 .text.BT_Period_CMP_Write + BT_ConfigInterrupt_CMD 0x000014bc F 18 .text.BT_ConfigInterrupt_CMD + BT1_INT_ENABLE 0x000014d0 F 16 .text.BT1_INT_ENABLE + GPT_Configure 0x000014e0 F 20 .text.GPT_Configure + GPT_WaveCtrl_Configure 0x000014f4 F 68 .text.GPT_WaveCtrl_Configure + GPT_Start 0x00001538 F 16 .text.GPT_Start + GPT_Period_CMP_Write 0x00001548 F 16 .text.GPT_Period_CMP_Write + GPT_ConfigInterrupt_CMD 0x00001558 F 28 .text.GPT_ConfigInterrupt_CMD + GPT_INT_ENABLE 0x00001574 F 16 .text.GPT_INT_ENABLE + UART0_DeInit 0x00001584 F 24 .text.UART0_DeInit + UART1_DeInit 0x0000159c F 24 .text.UART1_DeInit + UART2_DeInit 0x000015b4 F 24 .text.UART2_DeInit + UART0_Int_Enable 0x000015cc F 28 .text.UART0_Int_Enable + UART1_Int_Enable 0x000015e8 F 28 .text.UART1_Int_Enable + UART_IO_Init 0x00001604 F 232 .text.UART_IO_Init + UARTInitRxTxIntEn 0x000016ec F 10 .text.UARTInitRxTxIntEn + UARTTxByte 0x000016f6 F 14 .text.UARTTxByte + UARTTransmit 0x00001704 F 30 .text.UARTTransmit + EPT_Software_Prg 0x00001724 F 32 .text.EPT_Software_Prg + EPT_Start 0x00001744 F 40 .text.EPT_Start + EPT_IO_SET 0x0000176c F 568 .text.EPT_IO_SET + EPT_PWM_Config 0x000019a4 F 56 .text.EPT_PWM_Config + EPT_PWMX_Output_Control 0x000019dc F 216 .text.EPT_PWMX_Output_Control + EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config0x00001ab4 F 28 .text.EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config + ADC12_RESET_VALUE 0x00001ad0 F 100 .text.ADC12_RESET_VALUE + ADC12_Control 0x00001b34 F 16 .text.ADC12_Control + ADC12_CLK_CMD 0x00001b64 F 44 .text.ADC12_CLK_CMD + ADC12_Software_Reset 0x00001b90 F 10 .text.ADC12_Software_Reset + ADC12_CMD 0x00001b9c F 40 .text.ADC12_CMD + ADC12_ready_wait 0x00001bc4 F 20 .text.ADC12_ready_wait + ADC12_SEQEND_wait 0x00001bd8 F 24 .text.ADC12_SEQEND_wait + ADC12_DATA_OUPUT 0x00001bf0 F 20 .text.ADC12_DATA_OUPUT + ADC12_Configure_Mode 0x00001c04 F 124 .text.ADC12_Configure_Mode + ADC12_Configure_VREF_Selecte 0x00001c80 F 408 .text.ADC12_Configure_VREF_Selecte + ADC12_ConversionChannel_Config 0x00001e18 F 384 .text.ADC12_ConversionChannel_Config + Page_ProgramData 0x00001f98 F 160 .text.Page_ProgramData + ReadDataArry_U8 0x00002038 F 42 .text.ReadDataArry_U8 + main 0x00002064 F 40 .text.startup.main + delay_nms 0x0000208c F 44 .text.delay_nms + GPIO_CONFIG 0x000020b8 F 152 .text.GPIO_CONFIG + EPT0_CONFIG 0x00002150 F 216 .text.EPT0_CONFIG + BT_CONFIG 0x00002228 F 172 .text.BT_CONFIG + ADC12_CONFIG 0x000022d4 F 114 .text.ADC12_CONFIG + GPT0_CONFIG 0x00002348 F 80 .text.GPT0_CONFIG + SYSCON_CONFIG 0x00002398 F 120 .text.SYSCON_CONFIG + APT32F102_init 0x00002410 F 120 .text.APT32F102_init + SYSCONIntHandler 0x00002488 F 240 .text.SYSCONIntHandler + IFCIntHandler 0x00002578 F 104 .text.IFCIntHandler + ADCIntHandler 0x000025e0 F 104 .text.ADCIntHandler + EPT0IntHandler 0x00002648 F 424 .text.EPT0IntHandler + WWDTHandler 0x000027f0 F 52 .text.WWDTHandler + GPT0IntHandler 0x00002824 F 140 .text.GPT0IntHandler + RTCIntHandler 0x000028b0 F 112 .text.RTCIntHandler + UART0IntHandler 0x00002920 F 84 .text.UART0IntHandler + UART1IntHandler 0x00002974 F 80 .text.UART1IntHandler + UART2IntHandler 0x000029c4 F 60 .text.UART2IntHandler + SPI0IntHandler 0x00002a00 F 232 .text.SPI0IntHandler + SIO0IntHandler 0x00002ae8 F 132 .text.SIO0IntHandler + EXI0IntHandler 0x00002b6c F 48 .text.EXI0IntHandler + EXI1IntHandler 0x00002b9c F 60 .text.EXI1IntHandler + EXI2to3IntHandler 0x00002bd8 F 72 .text.EXI2to3IntHandler + EXI4to9IntHandler 0x00002c20 F 92 .text.EXI4to9IntHandler + EXI10to15IntHandler 0x00002c7c F 96 .text.EXI10to15IntHandler + LPTIntHandler 0x00002cdc F 52 .text.LPTIntHandler + BT0IntHandler 0x00002d10 F 60 .text.BT0IntHandler + BT1IntHandler 0x00002d4c F 112 .text.BT1IntHandler + PriviledgeVioHandler 0x00002dbc F 2 .text.PriviledgeVioHandler + PendTrapHandler 0x00002dbe F 8 .text.PendTrapHandler + Trap3Handler 0x00002dc6 F 8 .text.Trap3Handler + Trap2Handler 0x00002dce F 8 .text.Trap2Handler + Trap1Handler 0x00002dd6 F 8 .text.Trap1Handler + Trap0Handler 0x00002dde F 8 .text.Trap0Handler + UnrecExecpHandler 0x00002de6 F 8 .text.UnrecExecpHandler + BreakPointHandler 0x00002dee F 8 .text.BreakPointHandler + AccessErrHandler 0x00002df6 F 8 .text.AccessErrHandler + IllegalInstrHandler 0x00002dfe F 8 .text.IllegalInstrHandler + MisalignedHandler 0x00002e06 F 8 .text.MisalignedHandler + TKEYIntHandler 0x00002e0e F 8 .text.TKEYIntHandler + CNTAIntHandler 0x00002e16 F 8 .text.CNTAIntHandler + I2CIntHandler 0x00002e1e F 8 .text.I2CIntHandler + CORETHandler 0x00002e26 F 8 .text.CORETHandler + __divsi3 0x00002e30 F 36 .text.__divsi3 + __udivsi3 0x00002e54 F 36 .text.__udivsi3 + CK_CPU_EnAllNormalIrq 0x00002e78 F 6 .text.CK_CPU_EnAllNormalIrq + UARTx_Init 0x00002e80 F 148 .text.UARTx_Init + UART1_RecvINT_Processing 0x00002f14 F 56 .text.UART1_RecvINT_Processing + UART1_TASK 0x00002f4c F 92 .text.UART1_TASK + Dbg_Println 0x00002fa8 F 12 .text.Dbg_Println + Dbg_Print_Buff 0x00002fb4 F 2 .text.Dbg_Print_Buff + PB_Set_SaveCurrent 0x00002fd8 F 44 .text.PB_Set_SaveCurrent + PB_Init 0x00003004 F 68 .text.PB_Init + PB_Set_Power_State 0x00003048 F 28 .text.PB_Set_Power_State + PB_Soft_Boot_Task 0x00003064 F 280 .text.PB_Soft_Boot_Task + PowerBus_Data_Encoding 0x0000317c F 52 .text.PowerBus_Data_Encoding + PB_Send_String_INT 0x000031b0 F 84 .text.PB_Send_String_INT + PowerBus_Data_Send 0x00003204 F 124 .text.PowerBus_Data_Send + PB_CheckSum 0x00003280 F 24 .text.PB_CheckSum + PB_OVERCURR_PWR_BUS_INT_Processing 0x00003298 F 36 .text.PB_OVERCURR_PWR_BUS_INT_Processing + PB_Protect_Task 0x000032bc F 84 .text.PB_Protect_Task + PB_Scan_State_Task 0x00003310 F 52 .text.PB_Scan_State_Task + PowerBus_FillSendBuff 0x00003344 F 76 .text.PowerBus_FillSendBuff + PowerBus_PackFillBuff 0x00003390 F 176 .text.PowerBus_PackFillBuff + PowerBUS_GetCommState 0x00003440 F 28 .text.PowerBUS_GetCommState + PB_FilACkPacket 0x0000345c F 52 .text.PB_FilACkPacket + PB_RS485_ReplyAck 0x00003490 F 56 .text.PB_RS485_ReplyAck + PB_Set_CH_SaveBrightnessInfo 0x000034c8 F 56 .text.PB_Set_CH_SaveBrightnessInfo + PB_Set_CH_SaveSwitchInfo 0x00003500 F 48 .text.PB_Set_CH_SaveSwitchInfo + PB_ACK_SET_LED_BRIGHTNESS 0x00003530 F 152 .text.PB_ACK_SET_LED_BRIGHTNESS + PB_ACK_SET_STRIP_SWITCH 0x000035c8 F 128 .text.PB_ACK_SET_STRIP_SWITCH + PB_ACK_SET_STRIP_ADJUST 0x00003648 F 96 .text.PB_ACK_SET_STRIP_ADJUST + PB_ACK_SET_PIRTIGGLE_LED 0x000036a8 F 56 .text.PB_ACK_SET_PIRTIGGLE_LED + PB_ACK_SET_SaveCurrInfo 0x000036e0 F 108 .text.PB_ACK_SET_SaveCurrInfo + PB_ACK_SET_UniversPara 0x0000374c F 232 .text.PB_ACK_SET_UniversPara + PB_ACK_SET_PowerBus_EnablePara 0x00003834 F 84 .text.PB_ACK_SET_PowerBus_EnablePara + PB_ACK_PassThroug_Data 0x00003888 F 60 .text.PB_ACK_PassThroug_Data + PB_ACK_SET_PB_LEDS_BRIGHTNESS 0x000038c4 F 64 .text.PB_ACK_SET_PB_LEDS_BRIGHTNESS + PB_ACK_SET_PB_LEDS_ADJUST 0x00003904 F 64 .text.PB_ACK_SET_PB_LEDS_ADJUST + PB_ACK_SET_PB_LEDS_SWITCH 0x00003944 F 64 .text.PB_ACK_SET_PB_LEDS_SWITCH + PB_ACK_SET_PB_LEDS_BRIGHT 0x00003984 F 64 .text.PB_ACK_SET_PB_LEDS_BRIGHT + PB_ACK_SET_PB_LED_BRIGHTNESS 0x000039c4 F 64 .text.PB_ACK_SET_PB_LED_BRIGHTNESS + PB_ACK_SET_PB_LED_Adjust 0x00003a04 F 64 .text.PB_ACK_SET_PB_LED_Adjust + PB_ACK_SET_PB_LED_SWITCH 0x00003a44 F 64 .text.PB_ACK_SET_PB_LED_SWITCH + PB_ACK_SET_PB_ALLLED_Switch 0x00003a84 F 64 .text.PB_ACK_SET_PB_ALLLED_Switch + PB_ACK_SET_PB_STRIPS_BRIGHTNESS 0x00003ac4 F 364 .text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS + PB_ACK_SET_PB_STRIPS_ADJUST 0x00003c30 F 332 .text.PB_ACK_SET_PB_STRIPS_ADJUST + PB_ACK_SET_PB_STRIPS_SWITCH 0x00003d7c F 588 .text.PB_ACK_SET_PB_STRIPS_SWITCH + PB_ACK_SET_PB_STRIP_SWITCH 0x00003fc8 F 68 .text.PB_ACK_SET_PB_STRIP_SWITCH + PB_ACK_SET_PB_STRIP_BRIGHTNESS 0x0000400c F 64 .text.PB_ACK_SET_PB_STRIP_BRIGHTNESS + PB_ACK_SET_PB_STRIP_Adjust 0x0000404c F 68 .text.PB_ACK_SET_PB_STRIP_Adjust + PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST0x00004090 F 332 .text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST + PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST0x000041dc F 68 .text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST + PB_ACK_SET_PB_ALLSTRIP_Switch 0x00004220 F 68 .text.PB_ACK_SET_PB_ALLSTRIP_Switch + PB_ACK_SET_PB_RELAYS_SWITCH 0x00004264 F 68 .text.PB_ACK_SET_PB_RELAYS_SWITCH + PB_ACK_SET_PB_ALLRELAY_SWITCH 0x000042a8 F 68 .text.PB_ACK_SET_PB_ALLRELAY_SWITCH + PB_ACK_SET_PB_RELAY_SWITCH 0x000042ec F 68 .text.PB_ACK_SET_PB_RELAY_SWITCH + PB_ACK_SET_PB_RELAY_DELAY_SWITCH 0x00004330 F 68 .text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH + Get_ADC_Val_Filter 0x00004374 F 34 .text.Get_ADC_Val_Filter + Get_PB_CURR_VAL 0x00004398 F 40 .text.Get_PB_CURR_VAL + PB_ACK_GET_STATE 0x000043c0 F 232 .text.PB_ACK_GET_STATE + Current_Coarse_Filter 0x000044a8 F 40 .text.Current_Coarse_Filter + Current_Fine_Filter 0x000044d0 F 48 .text.Current_Fine_Filter + PB_Current_Monitoring_Meas 0x00004500 F 304 .text.PB_Current_Monitoring_Meas + PMU_MEAS_Task 0x00004630 F 496 .text.PMU_MEAS_Task + Set_PB_CurrMonitoring_Dead 0x00004820 F 16 .text.Set_PB_CurrMonitoring_Dead + PowerBus_SendBuffer_Task 0x00004830 F 128 .text.PowerBus_SendBuffer_Task + PB_ACK_SET_CurrTiggleStrip 0x000048b0 F 364 .text.PB_ACK_SET_CurrTiggleStrip + BLV_PB_Control_Protocol_Processing 0x00004a1c F 684 .text.BLV_PB_Control_Protocol_Processing + PB_Task 0x00004cc8 F 20 .text.PB_Task + PWM_SetOutDuty 0x00004cdc F 48 .text.PWM_SetOutDuty + PWM_SetCHGradualTime 0x00004d0c F 20 .text.PWM_SetCHGradualTime + PWM_SetOutBrightness 0x00004d20 F 248 .text.PWM_SetOutBrightness + PWM_Init 0x00004e18 F 376 .text.PWM_Init + PWM_SetUpLimitVal 0x00004f90 F 68 .text.PWM_SetUpLimitVal + PWM_SetDownLimitVal 0x00004fd4 F 68 .text.PWM_SetDownLimitVal + Pwm_SetOnOffState 0x00005018 F 24 .text.Pwm_SetOnOffState + Pwm_SetAllBrightness 0x00005030 F 44 .text.Pwm_SetAllBrightness + PWM_SetAutoAdjust 0x0000505c F 180 .text.PWM_SetAutoAdjust + PWM_Timer_1ms_Task 0x00005110 F 424 .text.PWM_Timer_1ms_Task + EEPROM_ReadParaInfo 0x000052b8 F 116 .text.EEPROM_ReadParaInfo + EEPROM_WriteParaInfo 0x0000532c F 68 .text.EEPROM_WriteParaInfo + EEPROM_Validate_ParaInfo 0x00005370 F 196 .text.EEPROM_Validate_ParaInfo + EEPROM_Default_ParaInfo 0x00005434 F 52 .text.EEPROM_Default_ParaInfo + EEPROM_Init 0x00005468 F 68 .text.EEPROM_Init + std_clk_calib 0x000054ac F 644 .text.std_clk_calib + PowerBus_Code_Comparative 0x00005730 O 16 .rodata + __thenan_sf 0x000058e8 O 16 .rodata + __thenan_df 0x000058f8 O 20 .rodata + __clz_tab 0x0000590c O 256 .rodata + _end_rodata 0x000060dc 0 .rodata + HWD 0x20000000 O 4 .data + _start_data 0x20000000 0 .data + CRC 0x20000004 O 4 .data + BT1 0x20000008 O 4 .data + BT0 0x2000000c O 4 .data + WWDT 0x20000010 O 4 .data + LPT 0x20000014 O 4 .data + RTC 0x20000018 O 4 .data + ETCB 0x2000001c O 4 .data + EPT0 0x20000020 O 4 .data + GPT0 0x20000024 O 4 .data + CA0 0x20000028 O 4 .data + SIO0 0x2000002c O 4 .data + I2C0 0x20000030 O 4 .data + SPI0 0x20000034 O 4 .data + UART2 0x20000038 O 4 .data + UART1 0x2000003c O 4 .data + UART0 0x20000040 O 4 .data + GPIOGRP 0x20000044 O 4 .data + GPIOB0 0x20000048 O 4 .data + GPIOA0 0x2000004c O 4 .data + ADC0 0x20000050 O 4 .data + TKEYBUF 0x20000054 O 4 .data + TKEY 0x20000058 O 4 .data + SYSCON 0x2000005c O 4 .data + IFC 0x20000060 O 4 .data + CK801 0x20000064 O 4 .data + _end_data 0x20000068 0 .data + _bss_start 0x20000068 0 .bss + SysTick_100us 0x2000006c O 4 .bss + SysTick_1ms 0x20000070 O 4 .bss + UTS_send_Complete 0x20000074 O 1 .bss + UTS_send_Length_temp 0x20000075 O 1 .bss + UTS_send_Length 0x20000076 O 1 .bss + R_CMPB_BUF 0x2000007c O 4 .bss + R_SIOTX_count 0x20000080 O 4 .bss + R_CMPA_BUF 0x20000084 O 4 .bss + R_SIORX_count 0x20000088 O 4 .bss + R_SIORX_buf 0x2000008c O 40 .bss + g_uart 0x200000b4 O 220 .bss + Uart_Intp_Send_Buff 0x20000190 O 200 .bss + curr_monitoring 0x20000258 O 152 .bss + g_PB 0x200002f0 O 1064 .bss + g_pwm 0x20000718 O 80 .bss + g_pwmAutoAdj 0x20000768 O 60 .bss + g_eeprom 0x200007a4 O 22 .bss + _ebss 0x200007bc 0 .bss + _end 0x200007bc 0 .bss + end 0x200007bc 0 .bss + __kernel_stack 0x20000ff8 0 .text + + (w:Weak d:Deubg F:Function f:File name O:Zero) + + +====================================================================== + +Memory Map of the image + + Image Entry point : 0x0000010c + + Region ROM (Base: 0x00000000, Size: 0x000060dc, Max: 0x00010000) + + Base Addr Size Type Attr Idx Section Name Object + 0x00000000 0x000001b4 Code RO 16 .text Obj/arch_crt0.o + 0x000001b4 0x00000014 Code RO 1008 .text _csky_case_uqi.o + 0x000001c8 0x0000001c Code RO 1013 .text _csky_case_shi.o + 0x000001e4 0x0000002e Code RO 1018 .text _fixunssfsi.o + 0x00000212 0x00000002 PAD + 0x00000214 0x000001aa Code RO 1025 .text _addsub_sf.o + 0x000003be 0x00000002 PAD + 0x000003c0 0x00000038 Code RO 1032 .text _ge_sf.o + 0x000003f8 0x00000036 Code RO 1039 .text _le_sf.o + 0x0000042e 0x00000002 PAD + 0x00000430 0x00000064 Code RO 1046 .text _si_to_sf.o + 0x00000494 0x00000054 Code RO 1053 .text _sf_to_si.o + 0x000004e8 0x00000024 Code RO 1060 .text _sf_to_df.o + 0x0000050c 0x00000060 Code RO 1074 .text _usi_to_sf.o + 0x0000056c 0x00000154 Code RO 1081 .text _div_df.o + 0x000006c0 0x00000070 Code RO 1088 .text _si_to_df.o + 0x00000730 0x00000028 Code RO 1095 .text _make_df.o + 0x00000758 0x00000030 Code RO 1102 .text _df_to_sf.o + 0x00000788 0x00000040 Code RO 1116 .text _clzsi2.o + 0x000007c8 0x000000b8 Code RO 1122 .text _pack_sf.o + 0x00000880 0x00000084 Code RO 1129 .text _unpack_sf.o + 0x00000904 0x00000078 Code RO 1136 .text _fpcmp_parts_sf.o + 0x0000097c 0x00000016 Code RO 1143 .text _make_sf.o + 0x00000992 0x00000002 PAD + 0x00000994 0x0000019c Code RO 1150 .text _pack_df.o + 0x00000b30 0x000000c4 Code RO 1157 .text _unpack_df.o + 0x00000bf4 0x00000088 Code RO 1178 .text memset_fast.o + 0x00000c7c 0x00000064 Code RO 1183 .text memcpy_fast.o + 0x00000ce0 0x00000038 Code RO 28 .text.__main Obj/arch_mem_init.o + 0x00000d18 0x00000074 Code RO 61 .text.SYSCON_General_CMD.part.0 Obj/FWlib_apt32f102_syscon.o + 0x00000d8c 0x00000058 Code RO 62 .text.SYSCON_RST_VALUE Obj/FWlib_apt32f102_syscon.o + 0x00000de4 0x00000030 Code RO 64 .text.SYSCON_General_CMD Obj/FWlib_apt32f102_syscon.o + 0x00000e14 0x00000088 Code RO 65 .text.SystemCLK_HCLKDIV_PCLKDIV_Config Obj/FWlib_apt32f102_syscon.o + 0x00000e9c 0x00000028 Code RO 68 .text.SYSCON_HFOSC_SELECTE Obj/FWlib_apt32f102_syscon.o + 0x00000ec4 0x0000003c Code RO 69 .text.SYSCON_WDT_CMD Obj/FWlib_apt32f102_syscon.o + 0x00000f00 0x00000014 Code RO 70 .text.SYSCON_IWDCNT_Reload Obj/FWlib_apt32f102_syscon.o + 0x00000f14 0x00000018 Code RO 71 .text.SYSCON_IWDCNT_Config Obj/FWlib_apt32f102_syscon.o + 0x00000f2c 0x00000020 Code RO 72 .text.SYSCON_LVD_Config Obj/FWlib_apt32f102_syscon.o + 0x00000f4c 0x0000001c Code RO 73 .text.LVD_Int_Enable Obj/FWlib_apt32f102_syscon.o + 0x00000f68 0x0000001c Code RO 75 .text.IWDT_Int_Enable Obj/FWlib_apt32f102_syscon.o + 0x00000f84 0x00000040 Code RO 78 .text.EXTI_trigger_CMD Obj/FWlib_apt32f102_syscon.o + 0x00000fc4 0x00000034 Code RO 79 .text.EXTI_interrupt_CMD Obj/FWlib_apt32f102_syscon.o + 0x00000ff8 0x00000004 Code RO 80 .text.GPIO_EXTI_interrupt Obj/FWlib_apt32f102_syscon.o + 0x00000ffc 0x00000010 Code RO 85 .text.EXI1_Int_Enable Obj/FWlib_apt32f102_syscon.o + 0x0000100c 0x0000000c Code RO 103 .text.SYSCON_Int_Enable Obj/FWlib_apt32f102_syscon.o + 0x00001018 0x00000024 Code RO 112 .text.SYSCON_INT_Priority Obj/FWlib_apt32f102_syscon.o + 0x0000103c 0x00000030 Code RO 113 .text.Set_INT_Priority Obj/FWlib_apt32f102_syscon.o + 0x0000106c 0x000000e0 Code RO 132 .text.GPIO_Init Obj/FWlib_apt32f102_gpio.o + 0x0000114c 0x0000000e Code RO 141 .text.GPIO_DriveStrength_EN Obj/FWlib_apt32f102_gpio.o + 0x0000115c 0x0000010c Code RO 143 .text.GPIO_IntGroup_Set Obj/FWlib_apt32f102_gpio.o + 0x00001268 0x00000008 Code RO 147 .text.GPIO_Write_High Obj/FWlib_apt32f102_gpio.o + 0x00001270 0x00000008 Code RO 148 .text.GPIO_Write_Low Obj/FWlib_apt32f102_gpio.o + 0x00001278 0x00000010 Code RO 151 .text.GPIO_Read_Status Obj/FWlib_apt32f102_gpio.o + 0x00001288 0x00000014 Code RO 185 .text.LPT_Soft_Reset Obj/FWlib_apt32f102_lpt.o + 0x0000129c 0x00000018 Code RO 232 .text.WWDT_CONFIG Obj/FWlib_apt32f102_wwdt.o + 0x000012b4 0x00000010 Code RO 234 .text.WWDT_CNT_Load Obj/FWlib_apt32f102_wwdt.o + 0x000012c4 0x00000034 Code RO 235 .text.WWDT_Int_Config Obj/FWlib_apt32f102_wwdt.o + 0x000012f8 0x0000001c Code RO 303 .text.BT_DeInit Obj/FWlib_apt32f102_bt.o + 0x00001314 0x0000014c Code RO 304 .text.BT_IO_Init Obj/FWlib_apt32f102_bt.o + 0x00001460 0x00000008 Code RO 305 .text.BT_Start Obj/FWlib_apt32f102_bt.o + 0x00001468 0x0000000a Code RO 309 .text.BT_Soft_Reset Obj/FWlib_apt32f102_bt.o + 0x00001472 0x00000018 Code RO 310 .text.BT_Configure Obj/FWlib_apt32f102_bt.o + 0x0000148a 0x0000002c Code RO 311 .text.BT_ControlSet_Configure Obj/FWlib_apt32f102_bt.o + 0x000014b6 0x00000006 Code RO 312 .text.BT_Period_CMP_Write Obj/FWlib_apt32f102_bt.o + 0x000014bc 0x00000012 Code RO 319 .text.BT_ConfigInterrupt_CMD Obj/FWlib_apt32f102_bt.o + 0x000014d0 0x00000010 Code RO 322 .text.BT1_INT_ENABLE Obj/FWlib_apt32f102_bt.o + 0x000014e0 0x00000014 Code RO 341 .text.GPT_Configure Obj/FWlib_apt32f102_gpt.o + 0x000014f4 0x00000044 Code RO 342 .text.GPT_WaveCtrl_Configure Obj/FWlib_apt32f102_gpt.o + 0x00001538 0x00000010 Code RO 353 .text.GPT_Start Obj/FWlib_apt32f102_gpt.o + 0x00001548 0x00000010 Code RO 360 .text.GPT_Period_CMP_Write Obj/FWlib_apt32f102_gpt.o + 0x00001558 0x0000001c Code RO 365 .text.GPT_ConfigInterrupt_CMD Obj/FWlib_apt32f102_gpt.o + 0x00001574 0x00000010 Code RO 366 .text.GPT_INT_ENABLE Obj/FWlib_apt32f102_gpt.o + 0x00001584 0x00000018 Code RO 435 .text.UART0_DeInit Obj/FWlib_apt32f102_uart.o + 0x0000159c 0x00000018 Code RO 436 .text.UART1_DeInit Obj/FWlib_apt32f102_uart.o + 0x000015b4 0x00000018 Code RO 437 .text.UART2_DeInit Obj/FWlib_apt32f102_uart.o + 0x000015cc 0x0000001c Code RO 438 .text.UART0_Int_Enable Obj/FWlib_apt32f102_uart.o + 0x000015e8 0x0000001c Code RO 440 .text.UART1_Int_Enable Obj/FWlib_apt32f102_uart.o + 0x00001604 0x000000e8 Code RO 450 .text.UART_IO_Init Obj/FWlib_apt32f102_uart.o + 0x000016ec 0x0000000a Code RO 452 .text.UARTInitRxTxIntEn Obj/FWlib_apt32f102_uart.o + 0x000016f6 0x0000000e Code RO 455 .text.UARTTxByte Obj/FWlib_apt32f102_uart.o + 0x00001704 0x0000001e Code RO 456 .text.UARTTransmit Obj/FWlib_apt32f102_uart.o + 0x00001724 0x00000020 Code RO 514 .text.EPT_Software_Prg Obj/FWlib_apt32f102_ept.o + 0x00001744 0x00000028 Code RO 515 .text.EPT_Start Obj/FWlib_apt32f102_ept.o + 0x0000176c 0x00000238 Code RO 517 .text.EPT_IO_SET Obj/FWlib_apt32f102_ept.o + 0x000019a4 0x00000038 Code RO 518 .text.EPT_PWM_Config Obj/FWlib_apt32f102_ept.o + 0x000019dc 0x000000d8 Code RO 525 .text.EPT_PWMX_Output_Control Obj/FWlib_apt32f102_ept.o + 0x00001ab4 0x0000001c Code RO 528 .text.EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config Obj/FWlib_apt32f102_ept.o + 0x00001ad0 0x00000064 Code RO 604 .text.ADC12_RESET_VALUE Obj/FWlib_apt32f102_adc.o + 0x00001b34 0x00000010 Code RO 605 .text.ADC12_Control Obj/FWlib_apt32f102_adc.o + 0x00001b44 0x00000020 Code RO 606 .text.ADC12_CMD.part.0 Obj/FWlib_apt32f102_adc.o + 0x00001b64 0x0000002c Code RO 609 .text.ADC12_CLK_CMD Obj/FWlib_apt32f102_adc.o + 0x00001b90 0x0000000a Code RO 610 .text.ADC12_Software_Reset Obj/FWlib_apt32f102_adc.o + 0x00001b9c 0x00000028 Code RO 611 .text.ADC12_CMD Obj/FWlib_apt32f102_adc.o + 0x00001bc4 0x00000014 Code RO 612 .text.ADC12_ready_wait Obj/FWlib_apt32f102_adc.o + 0x00001bd8 0x00000018 Code RO 614 .text.ADC12_SEQEND_wait Obj/FWlib_apt32f102_adc.o + 0x00001bf0 0x00000014 Code RO 615 .text.ADC12_DATA_OUPUT Obj/FWlib_apt32f102_adc.o + 0x00001c04 0x0000007c Code RO 616 .text.ADC12_Configure_Mode Obj/FWlib_apt32f102_adc.o + 0x00001c80 0x00000198 Code RO 617 .text.ADC12_Configure_VREF_Selecte Obj/FWlib_apt32f102_adc.o + 0x00001e18 0x00000180 Code RO 619 .text.ADC12_ConversionChannel_Config Obj/FWlib_apt32f102_adc.o + 0x00001f98 0x000000a0 Code RO 641 .text.Page_ProgramData Obj/FWlib_apt32f102_ifc.o + 0x00002038 0x0000002a Code RO 644 .text.ReadDataArry_U8 Obj/FWlib_apt32f102_ifc.o + 0x00002064 0x00000028 Code RO 690 .text.startup.main Obj/main.o + 0x0000208c 0x0000002c Code RO 706 .text.delay_nms Obj/mcu_initial.o + 0x000020b8 0x00000098 Code RO 708 .text.GPIO_CONFIG Obj/mcu_initial.o + 0x00002150 0x000000d8 Code RO 709 .text.EPT0_CONFIG Obj/mcu_initial.o + 0x00002228 0x000000ac Code RO 710 .text.BT_CONFIG Obj/mcu_initial.o + 0x000022d4 0x00000072 Code RO 714 .text.ADC12_CONFIG Obj/mcu_initial.o + 0x00002348 0x00000050 Code RO 715 .text.GPT0_CONFIG Obj/mcu_initial.o + 0x00002398 0x00000078 Code RO 716 .text.SYSCON_CONFIG Obj/mcu_initial.o + 0x00002410 0x00000078 Code RO 717 .text.APT32F102_init Obj/mcu_initial.o + 0x00002488 0x000000f0 Code RO 733 .text.SYSCONIntHandler Obj/mcu_interrupt.o + 0x00002578 0x00000068 Code RO 734 .text.IFCIntHandler Obj/mcu_interrupt.o + 0x000025e0 0x00000068 Code RO 735 .text.ADCIntHandler Obj/mcu_interrupt.o + 0x00002648 0x000001a8 Code RO 736 .text.EPT0IntHandler Obj/mcu_interrupt.o + 0x000027f0 0x00000034 Code RO 737 .text.WWDTHandler Obj/mcu_interrupt.o + 0x00002824 0x0000008c Code RO 738 .text.GPT0IntHandler Obj/mcu_interrupt.o + 0x000028b0 0x00000070 Code RO 739 .text.RTCIntHandler Obj/mcu_interrupt.o + 0x00002920 0x00000054 Code RO 740 .text.UART0IntHandler Obj/mcu_interrupt.o + 0x00002974 0x00000050 Code RO 741 .text.UART1IntHandler Obj/mcu_interrupt.o + 0x000029c4 0x0000003c Code RO 742 .text.UART2IntHandler Obj/mcu_interrupt.o + 0x00002a00 0x000000e8 Code RO 743 .text.SPI0IntHandler Obj/mcu_interrupt.o + 0x00002ae8 0x00000084 Code RO 744 .text.SIO0IntHandler Obj/mcu_interrupt.o + 0x00002b6c 0x00000030 Code RO 745 .text.EXI0IntHandler Obj/mcu_interrupt.o + 0x00002b9c 0x0000003c Code RO 746 .text.EXI1IntHandler Obj/mcu_interrupt.o + 0x00002bd8 0x00000048 Code RO 747 .text.EXI2to3IntHandler Obj/mcu_interrupt.o + 0x00002c20 0x0000005c Code RO 748 .text.EXI4to9IntHandler Obj/mcu_interrupt.o + 0x00002c7c 0x00000060 Code RO 749 .text.EXI10to15IntHandler Obj/mcu_interrupt.o + 0x00002cdc 0x00000034 Code RO 750 .text.LPTIntHandler Obj/mcu_interrupt.o + 0x00002d10 0x0000003c Code RO 751 .text.BT0IntHandler Obj/mcu_interrupt.o + 0x00002d4c 0x00000070 Code RO 752 .text.BT1IntHandler Obj/mcu_interrupt.o + 0x00002dbc 0x00000002 Code RO 753 .text.PriviledgeVioHandler Obj/mcu_interrupt.o + 0x00002dbe 0x00000008 Code RO 755 .text.PendTrapHandler Obj/mcu_interrupt.o + 0x00002dc6 0x00000008 Code RO 756 .text.Trap3Handler Obj/mcu_interrupt.o + 0x00002dce 0x00000008 Code RO 757 .text.Trap2Handler Obj/mcu_interrupt.o + 0x00002dd6 0x00000008 Code RO 758 .text.Trap1Handler Obj/mcu_interrupt.o + 0x00002dde 0x00000008 Code RO 759 .text.Trap0Handler Obj/mcu_interrupt.o + 0x00002de6 0x00000008 Code RO 760 .text.UnrecExecpHandler Obj/mcu_interrupt.o + 0x00002dee 0x00000008 Code RO 761 .text.BreakPointHandler Obj/mcu_interrupt.o + 0x00002df6 0x00000008 Code RO 762 .text.AccessErrHandler Obj/mcu_interrupt.o + 0x00002dfe 0x00000008 Code RO 763 .text.IllegalInstrHandler Obj/mcu_interrupt.o + 0x00002e06 0x00000008 Code RO 764 .text.MisalignedHandler Obj/mcu_interrupt.o + 0x00002e0e 0x00000008 Code RO 765 .text.TKEYIntHandler Obj/mcu_interrupt.o + 0x00002e16 0x00000008 Code RO 766 .text.CNTAIntHandler Obj/mcu_interrupt.o + 0x00002e1e 0x00000008 Code RO 767 .text.I2CIntHandler Obj/mcu_interrupt.o + 0x00002e26 0x00000008 Code RO 768 .text.CORETHandler Obj/mcu_interrupt.o + 0x00002e30 0x00000024 Code RO 785 .text.__divsi3 Obj/drivers_apt32f102.o + 0x00002e54 0x00000024 Code RO 786 .text.__udivsi3 Obj/drivers_apt32f102.o + 0x00002e78 0x00000006 Code RO 806 .text.CK_CPU_EnAllNormalIrq Obj/drivers_apt32f102_ck801.o + 0x00002e80 0x00000094 Code RO 821 .text.UARTx_Init Obj/SYSTEM_uart.o + 0x00002f14 0x00000038 Code RO 822 .text.UART1_RecvINT_Processing Obj/SYSTEM_uart.o + 0x00002f4c 0x0000005c Code RO 823 .text.UART1_TASK Obj/SYSTEM_uart.o + 0x00002fa8 0x0000000c Code RO 826 .text.Dbg_Println Obj/SYSTEM_uart.o + 0x00002fb4 0x00000002 Code RO 827 .text.Dbg_Print_Buff Obj/SYSTEM_uart.o + 0x00002fb8 0x00000020 Code RO 844 .text.PB_Set_Power_State.part.1 Obj/SYSTEM_pb_fun.o + 0x00002fd8 0x0000002c Code RO 845 .text.PB_Set_SaveCurrent Obj/SYSTEM_pb_fun.o + 0x00003004 0x00000044 Code RO 846 .text.PB_Init Obj/SYSTEM_pb_fun.o + 0x00003048 0x0000001c Code RO 847 .text.PB_Set_Power_State Obj/SYSTEM_pb_fun.o + 0x00003064 0x00000118 Code RO 848 .text.PB_Soft_Boot_Task Obj/SYSTEM_pb_fun.o + 0x0000317c 0x00000034 Code RO 849 .text.PowerBus_Data_Encoding Obj/SYSTEM_pb_fun.o + 0x000031b0 0x00000054 Code RO 850 .text.PB_Send_String_INT Obj/SYSTEM_pb_fun.o + 0x00003204 0x0000007c Code RO 851 .text.PowerBus_Data_Send Obj/SYSTEM_pb_fun.o + 0x00003280 0x00000018 Code RO 852 .text.PB_CheckSum Obj/SYSTEM_pb_fun.o + 0x00003298 0x00000024 Code RO 853 .text.PB_OVERCURR_PWR_BUS_INT_Processing Obj/SYSTEM_pb_fun.o + 0x000032bc 0x00000054 Code RO 854 .text.PB_Protect_Task Obj/SYSTEM_pb_fun.o + 0x00003310 0x00000034 Code RO 855 .text.PB_Scan_State_Task Obj/SYSTEM_pb_fun.o + 0x00003344 0x0000004c Code RO 856 .text.PowerBus_FillSendBuff Obj/SYSTEM_pb_fun.o + 0x00003390 0x000000b0 Code RO 857 .text.PowerBus_PackFillBuff Obj/SYSTEM_pb_fun.o + 0x00003440 0x0000001c Code RO 858 .text.PowerBUS_GetCommState Obj/SYSTEM_pb_fun.o + 0x0000345c 0x00000034 Code RO 859 .text.PB_FilACkPacket Obj/SYSTEM_pb_fun.o + 0x00003490 0x00000038 Code RO 860 .text.PB_RS485_ReplyAck Obj/SYSTEM_pb_fun.o + 0x000034c8 0x00000038 Code RO 861 .text.PB_Set_CH_SaveBrightnessInfo Obj/SYSTEM_pb_fun.o + 0x00003500 0x00000030 Code RO 862 .text.PB_Set_CH_SaveSwitchInfo Obj/SYSTEM_pb_fun.o + 0x00003530 0x00000098 Code RO 863 .text.PB_ACK_SET_LED_BRIGHTNESS Obj/SYSTEM_pb_fun.o + 0x000035c8 0x00000080 Code RO 864 .text.PB_ACK_SET_STRIP_SWITCH Obj/SYSTEM_pb_fun.o + 0x00003648 0x00000060 Code RO 865 .text.PB_ACK_SET_STRIP_ADJUST Obj/SYSTEM_pb_fun.o + 0x000036a8 0x00000038 Code RO 866 .text.PB_ACK_SET_PIRTIGGLE_LED Obj/SYSTEM_pb_fun.o + 0x000036e0 0x0000006c Code RO 867 .text.PB_ACK_SET_SaveCurrInfo Obj/SYSTEM_pb_fun.o + 0x0000374c 0x000000e8 Code RO 869 .text.PB_ACK_SET_UniversPara Obj/SYSTEM_pb_fun.o + 0x00003834 0x00000054 Code RO 870 .text.PB_ACK_SET_PowerBus_EnablePara Obj/SYSTEM_pb_fun.o + 0x00003888 0x0000003c Code RO 871 .text.PB_ACK_PassThroug_Data Obj/SYSTEM_pb_fun.o + 0x000038c4 0x00000040 Code RO 872 .text.PB_ACK_SET_PB_LEDS_BRIGHTNESS Obj/SYSTEM_pb_fun.o + 0x00003904 0x00000040 Code RO 873 .text.PB_ACK_SET_PB_LEDS_ADJUST Obj/SYSTEM_pb_fun.o + 0x00003944 0x00000040 Code RO 874 .text.PB_ACK_SET_PB_LEDS_SWITCH Obj/SYSTEM_pb_fun.o + 0x00003984 0x00000040 Code RO 875 .text.PB_ACK_SET_PB_LEDS_BRIGHT Obj/SYSTEM_pb_fun.o + 0x000039c4 0x00000040 Code RO 876 .text.PB_ACK_SET_PB_LED_BRIGHTNESS Obj/SYSTEM_pb_fun.o + 0x00003a04 0x00000040 Code RO 877 .text.PB_ACK_SET_PB_LED_Adjust Obj/SYSTEM_pb_fun.o + 0x00003a44 0x00000040 Code RO 878 .text.PB_ACK_SET_PB_LED_SWITCH Obj/SYSTEM_pb_fun.o + 0x00003a84 0x00000040 Code RO 879 .text.PB_ACK_SET_PB_ALLLED_Switch Obj/SYSTEM_pb_fun.o + 0x00003ac4 0x0000016c Code RO 880 .text.PB_ACK_SET_PB_STRIPS_BRIGHTNESS Obj/SYSTEM_pb_fun.o + 0x00003c30 0x0000014c Code RO 881 .text.PB_ACK_SET_PB_STRIPS_ADJUST Obj/SYSTEM_pb_fun.o + 0x00003d7c 0x0000024c Code RO 882 .text.PB_ACK_SET_PB_STRIPS_SWITCH Obj/SYSTEM_pb_fun.o + 0x00003fc8 0x00000044 Code RO 883 .text.PB_ACK_SET_PB_STRIP_SWITCH Obj/SYSTEM_pb_fun.o + 0x0000400c 0x00000040 Code RO 884 .text.PB_ACK_SET_PB_STRIP_BRIGHTNESS Obj/SYSTEM_pb_fun.o + 0x0000404c 0x00000044 Code RO 885 .text.PB_ACK_SET_PB_STRIP_Adjust Obj/SYSTEM_pb_fun.o + 0x00004090 0x0000014c Code RO 886 .text.PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST Obj/SYSTEM_pb_fun.o + 0x000041dc 0x00000044 Code RO 887 .text.PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST Obj/SYSTEM_pb_fun.o + 0x00004220 0x00000044 Code RO 888 .text.PB_ACK_SET_PB_ALLSTRIP_Switch Obj/SYSTEM_pb_fun.o + 0x00004264 0x00000044 Code RO 889 .text.PB_ACK_SET_PB_RELAYS_SWITCH Obj/SYSTEM_pb_fun.o + 0x000042a8 0x00000044 Code RO 890 .text.PB_ACK_SET_PB_ALLRELAY_SWITCH Obj/SYSTEM_pb_fun.o + 0x000042ec 0x00000044 Code RO 891 .text.PB_ACK_SET_PB_RELAY_SWITCH Obj/SYSTEM_pb_fun.o + 0x00004330 0x00000044 Code RO 892 .text.PB_ACK_SET_PB_RELAY_DELAY_SWITCH Obj/SYSTEM_pb_fun.o + 0x00004374 0x00000022 Code RO 893 .text.Get_ADC_Val_Filter Obj/SYSTEM_pb_fun.o + 0x00004398 0x00000028 Code RO 894 .text.Get_PB_CURR_VAL Obj/SYSTEM_pb_fun.o + 0x000043c0 0x000000e8 Code RO 895 .text.PB_ACK_GET_STATE Obj/SYSTEM_pb_fun.o + 0x000044a8 0x00000028 Code RO 896 .text.Current_Coarse_Filter Obj/SYSTEM_pb_fun.o + 0x000044d0 0x00000030 Code RO 897 .text.Current_Fine_Filter Obj/SYSTEM_pb_fun.o + 0x00004500 0x00000130 Code RO 898 .text.PB_Current_Monitoring_Meas Obj/SYSTEM_pb_fun.o + 0x00004630 0x000001f0 Code RO 899 .text.PMU_MEAS_Task Obj/SYSTEM_pb_fun.o + 0x00004820 0x00000010 Code RO 900 .text.Set_PB_CurrMonitoring_Dead Obj/SYSTEM_pb_fun.o + 0x00004830 0x00000080 Code RO 901 .text.PowerBus_SendBuffer_Task Obj/SYSTEM_pb_fun.o + 0x000048b0 0x0000016c Code RO 902 .text.PB_ACK_SET_CurrTiggleStrip Obj/SYSTEM_pb_fun.o + 0x00004a1c 0x000002ac Code RO 903 .text.BLV_PB_Control_Protocol_Processing Obj/SYSTEM_pb_fun.o + 0x00004cc8 0x00000014 Code RO 904 .text.PB_Task Obj/SYSTEM_pb_fun.o + 0x00004cdc 0x00000030 Code RO 923 .text.PWM_SetOutDuty Obj/SYSTEM_pwm.o + 0x00004d0c 0x00000014 Code RO 924 .text.PWM_SetCHGradualTime Obj/SYSTEM_pwm.o + 0x00004d20 0x000000f8 Code RO 925 .text.PWM_SetOutBrightness Obj/SYSTEM_pwm.o + 0x00004e18 0x00000178 Code RO 926 .text.PWM_Init Obj/SYSTEM_pwm.o + 0x00004f90 0x00000044 Code RO 927 .text.PWM_SetUpLimitVal Obj/SYSTEM_pwm.o + 0x00004fd4 0x00000044 Code RO 928 .text.PWM_SetDownLimitVal Obj/SYSTEM_pwm.o + 0x00005018 0x00000018 Code RO 929 .text.Pwm_SetOnOffState Obj/SYSTEM_pwm.o + 0x00005030 0x0000002c Code RO 930 .text.Pwm_SetAllBrightness Obj/SYSTEM_pwm.o + 0x0000505c 0x000000b4 Code RO 931 .text.PWM_SetAutoAdjust Obj/SYSTEM_pwm.o + 0x00005110 0x000001a8 Code RO 934 .text.PWM_Timer_1ms_Task Obj/SYSTEM_pwm.o + 0x000052b8 0x00000074 Code RO 952 .text.EEPROM_ReadParaInfo Obj/SYSTEM_eeprom.o + 0x0000532c 0x00000044 Code RO 953 .text.EEPROM_WriteParaInfo Obj/SYSTEM_eeprom.o + 0x00005370 0x000000c4 Code RO 955 .text.EEPROM_Validate_ParaInfo Obj/SYSTEM_eeprom.o + 0x00005434 0x00000034 Code RO 956 .text.EEPROM_Default_ParaInfo Obj/SYSTEM_eeprom.o + 0x00005468 0x00000044 Code RO 957 .text.EEPROM_Init Obj/SYSTEM_eeprom.o + 0x000054ac 0x00000284 Code RO 984 .text.std_clk_calib FWlib_apt32f102_clkcalib.o + 0x00005730 0x000001b8 Data RO 905 .rodata Obj/SYSTEM_pb_fun.o + 0x000058e8 0x00000010 Data RO 1070 .rodata _thenan_sf.o + 0x000058f8 0x00000014 Data RO 1112 .rodata _thenan_df.o + 0x0000590c 0x00000100 Data RO 1167 .rodata _clz.o + 0x00005a0c 0x0000000b Data RO 691 .rodata.str1.1 Obj/main.o + 0x00005a17 0x000004b4 Data RO 906 .rodata.str1.1 Obj/SYSTEM_pb_fun.o + 0x00005ecb 0x0000014c Data RO 935 .rodata.str1.1 Obj/SYSTEM_pwm.o + 0x00006017 0x000000c3 Data RO 958 .rodata.str1.1 Obj/SYSTEM_eeprom.o + 0x000060da 0x00000002 PAD + + Region RAM (Base: 0x20000000, Size: 0x000007bc, Max: 0x00001000) + + Base Addr Size Type Attr Idx Section Name Object + 0x20000000 0x00000068 Data RW 783 .data Obj/drivers_apt32f102.o + 0x20000068 0x0000000c Zero RW 732 .bss Obj/mcu_interrupt.o + 0x20000074 0x00000008 Zero RW 843 .bss Obj/SYSTEM_pb_fun.o + 0x2000007c 0x00000038 Zero RW 781 COMMON Obj/mcu_interrupt.o + 0x200000b4 0x000000dc Zero RW 840 COMMON Obj/SYSTEM_uart.o + 0x20000190 0x00000588 Zero RW 919 COMMON Obj/SYSTEM_pb_fun.o + 0x20000718 0x0000008c Zero RW 948 COMMON Obj/SYSTEM_pwm.o + 0x200007a4 0x00000016 Zero RW 971 COMMON Obj/SYSTEM_eeprom.o + 0x200007ba 0x00000002 PAD + + Region *default* (Base: 0x00000000, Size: 0x00000000, Max: 0xffffffff) + + +====================================================================== + +Image component sizes + + Code RO Data RW Data ZI Data Debug Object Name + + 0 0 0 0 0 linker stubs + 436 0 0 0 267 Obj/arch_crt0.o + 56 0 0 0 803 Obj/arch_mem_init.o + 0 0 0 0 0 Obj/arch_apt32f102_iostring.o + 852 0 0 0 21147 Obj/FWlib_apt32f102_syscon.o + 538 0 0 0 13094 Obj/FWlib_apt32f102_gpio.o + 20 0 0 0 13494 Obj/FWlib_apt32f102_lpt.o + 0 0 0 0 0 Obj/FWlib_apt32f102_crc.o + 92 0 0 0 8327 Obj/FWlib_apt32f102_wwdt.o + 0 0 0 0 0 Obj/FWlib_apt32f102_countera.o + 0 0 0 0 0 Obj/FWlib_apt32f102_et.o + 486 0 0 0 11840 Obj/FWlib_apt32f102_bt.o + 164 0 0 0 21406 Obj/FWlib_apt32f102_gpt.o + 0 0 0 0 0 Obj/FWlib_apt32f102_sio.o + 0 0 0 0 0 Obj/FWlib_apt32f102_spi.o + 414 0 0 0 11721 Obj/FWlib_apt32f102_uart.o + 0 0 0 0 0 Obj/FWlib_apt32f102_i2c.o + 940 0 0 0 28174 Obj/FWlib_apt32f102_ept.o + 0 0 0 0 0 Obj/FWlib_apt32f102_rtc.o + 1222 0 0 0 13987 Obj/FWlib_apt32f102_adc.o + 202 0 0 0 16689 Obj/FWlib_apt32f102_ifc.o + 0 0 0 0 0 Obj/FWlib_apt32f102_coret.o + 40 11 0 0 11184 Obj/main.o + 1018 0 0 0 14854 Obj/mcu_initial.o + 2470 0 0 68 14126 Obj/mcu_interrupt.o + 72 0 104 0 8379 Obj/drivers_apt32f102.o + 6 0 0 0 8319 Obj/drivers_apt32f102_ck801.o + 310 0 0 220 11572 Obj/SYSTEM_uart.o + 7458 1644 0 1424 30327 Obj/SYSTEM_pb_fun.o + 1500 332 0 140 12478 Obj/SYSTEM_pwm.o + 500 195 0 22 11046 Obj/SYSTEM_eeprom.o + 0 0 0 0 0 Obj/__rt_entry.o + ------------------------------------------------------------ + 18796 2182 104 1874 283234 Object Totals + 8 2 0 2 0 Pad + 0 0 0 0 0 LD_GEN + + ------------------------------------------------------------ + [Library Name]: .\lib_102ClkCalib_1_03.a + ------------------------------------------------------------ + Code RO Data RW Data ZI Data Debug Library Member Name + + 644 0 0 0 8675 FWlib_apt32f102_clkcalib.o + ------------------------------------------------------------ + 644 0 0 0 8675 Library Totals + 0 0 0 0 0 Pad + 0 0 0 0 0 LD_GEN + + ------------------------------------------------------------ + [Library Name]: d:/c-sky/cdkrepo/toolchain/ckv2elfminilib/v3.10.29/r/bin/../lib/gcc/csky-elfabiv2/6.3.0/ck801\libgcc.a + ------------------------------------------------------------ + Code RO Data RW Data ZI Data Debug Library Member Name + + 20 0 0 0 0 _csky_case_uqi.o + 28 0 0 0 0 _csky_case_shi.o + 46 0 0 0 0 _fixunssfsi.o + 426 0 0 0 0 _addsub_sf.o + 56 0 0 0 0 _ge_sf.o + 54 0 0 0 0 _le_sf.o + 100 0 0 0 0 _si_to_sf.o + 84 0 0 0 0 _sf_to_si.o + 36 0 0 0 0 _sf_to_df.o + 0 16 0 0 0 _thenan_sf.o + 96 0 0 0 0 _usi_to_sf.o + 340 0 0 0 0 _div_df.o + 112 0 0 0 0 _si_to_df.o + 40 0 0 0 0 _make_df.o + 48 0 0 0 0 _df_to_sf.o + 0 20 0 0 0 _thenan_df.o + 64 0 0 0 0 _clzsi2.o + 184 0 0 0 0 _pack_sf.o + 132 0 0 0 0 _unpack_sf.o + 120 0 0 0 0 _fpcmp_parts_sf.o + 22 0 0 0 0 _make_sf.o + 412 0 0 0 0 _pack_df.o + 196 0 0 0 0 _unpack_df.o + 0 256 0 0 0 _clz.o + ------------------------------------------------------------ + 2616 292 0 0 0 Library Totals + 0 0 0 0 0 Pad + 0 0 0 0 0 LD_GEN + + ------------------------------------------------------------ + [Library Name]: d:/c-sky/cdkrepo/toolchain/ckv2elfminilib/v3.10.29/r/bin/../lib/gcc/csky-elfabiv2/6.3.0/../../../../csky-elfabiv2/lib/ck801\libc.a + ------------------------------------------------------------ + Code RO Data RW Data ZI Data Debug Library Member Name + + 136 0 0 0 0 memset_fast.o + 100 0 0 0 0 memcpy_fast.o + ------------------------------------------------------------ + 236 0 0 0 0 Library Totals + 0 0 0 0 0 Pad + 0 0 0 0 0 LD_GEN + + ------------------------------------------------------------ + +====================================================================== + + + Code RO Data RW Data ZI Data Debug + 22300 2476 104 1876 291909 Grand Totals + 22300 2476 104 1876 291909 Elf Image Totals + 22300 2476 104 0 0 ROM Totals + +====================================================================== + +Total RO Size (Code + RO Data) 24776 ( 24.20kB) +Total RW Size (RW Data + ZI Data) 1980 ( 1.93kB) +Total ROM Size (Code + RO Data + RW Data) 24880 ( 24.30kB) + +====================================================================== diff --git a/Source/MD203F8P.mk b/Source/MD203F8P.mk new file mode 100644 index 0000000..d65c0dd --- /dev/null +++ b/Source/MD203F8P.mk @@ -0,0 +1,263 @@ +## +## Auto Generated makefile by CDK +## Do not modify this file, and any manual changes will be erased!!! +## +## BuildSet +ProjectName :=MD203F8P +ConfigurationName :=BuildSet +WorkspacePath :=./ +ProjectPath :=./ +IntermediateDirectory :=Obj +OutDir :=$(IntermediateDirectory) +User :=Administrator +Date :=19/01/2026 +CDKPath :=../../../../C-Sky/CDK +ToolchainPath :=D:/C-Sky/CDKRepo/Toolchain/CKV2ElfMinilib/V3.10.29/R/ +LinkerName :=csky-elfabiv2-gcc +LinkerNameoption := +SIZE :=csky-elfabiv2-size +READELF :=csky-elfabiv2-readelf +CHECKSUM :=crc32 +SharedObjectLinkerName := +ObjectSuffix :=.o +DependSuffix :=.d +PreprocessSuffix :=.i +DisassemSuffix :=.asm +IHexSuffix :=.ihex +BinSuffix :=.bin +ExeSuffix :=.elf +LibSuffix :=.a +DebugSwitch :=-g +IncludeSwitch :=-I +LibrarySwitch :=-l +OutputSwitch :=-o +ElfInfoSwitch :=-hlS +LibraryPathSwitch :=-L +PreprocessorSwitch :=-D +UnPreprocessorSwitch :=-U +SourceSwitch :=-c +ObjdumpSwitch :=-S +ObjcopySwitch :=-O ihex +ObjcopyBinSwitch :=-O binary +OutputFile :=BLV_C8_PLC_MASTER_V07_20260117 +ObjectSwitch :=-o +ArchiveOutputSwitch := +PreprocessOnlySwitch :=-E +PreprocessOnlyDisableLineSwitch :=-P +ObjectsFileList :=$(IntermediateDirectory)/MD203F8P.txt +MakeDirCommand :=mkdir +LinkOptions := -mcpu=ck801 -nostartfiles -Wl,--gc-sections -T"$(ProjectPath)/ckcpu.ld" -pipe +LinkOtherFlagsOption := -Wl,--ckmap=$(ProjectPath)/Lst/$(OutputFile).map +IncludePackagePath := +IncludeCPath := $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/ $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_core/include/ $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/ $(IncludeSwitch). $(IncludeSwitch)SYSTEM/inc $(IncludeSwitch)include +IncludeAPath := $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_core/csi_cdk/ $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_core/include/ $(IncludeSwitch)../../../../C-Sky/CDK/CSKY/csi/csi_driver/include/ $(IncludeSwitch). $(IncludeSwitch)SYSTEM $(IncludeSwitch)SYSTEM/inc +Libs := -Wl,--start-group -Wl,--end-group $(LibrarySwitch)_102ClkCalib_1_03 $(LibrarySwitch)m +ArLibs := "lib_102ClkCalib_1_03" "libm" +PackagesLibPath := +LibPath :=$(LibraryPathSwitch). $(PackagesLibPath) + +## +## Common variables +## AR, CXX, CC, AS, CXXFLAGS and CFLAGS can be overriden using an environment variables +## +AR :=csky-elfabiv2-ar rcu +CXX :=csky-elfabiv2-g++ +CC :=csky-elfabiv2-gcc +AS :=csky-elfabiv2-gcc +OBJDUMP :=csky-elfabiv2-objdump +OBJCOPY :=csky-elfabiv2-objcopy +CXXFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe +CFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe +ASFLAGS :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CKCPU_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Wa,-gdwarf-2 -pipe +PreprocessFlags :=-mcpu=ck801 $(PreprocessorSwitch)CONFIG_CSKY_MMU=0 $(UnPreprocessorSwitch)__CSKY_ABIV2__ -Os -g -ffunction-sections -mistack -pipe + + +Objects0=$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) $(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) $(IntermediateDirectory)/arch_apt32f102_iostring$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_syscon$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_gpio$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_lpt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_crc$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_wwdt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_countera$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_et$(ObjectSuffix) \ + $(IntermediateDirectory)/FWlib_apt32f102_bt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_gpt$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_sio$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_spi$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_uart$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_i2c$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_ept$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_rtc$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_adc$(ObjectSuffix) $(IntermediateDirectory)/FWlib_apt32f102_ifc$(ObjectSuffix) \ + $(IntermediateDirectory)/FWlib_apt32f102_coret$(ObjectSuffix) $(IntermediateDirectory)/main$(ObjectSuffix) $(IntermediateDirectory)/mcu_initial$(ObjectSuffix) $(IntermediateDirectory)/mcu_interrupt$(ObjectSuffix) $(IntermediateDirectory)/drivers_apt32f102$(ObjectSuffix) $(IntermediateDirectory)/drivers_apt32f102_ck801$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_uart$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_pb_fun$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_pwm$(ObjectSuffix) $(IntermediateDirectory)/SYSTEM_eeprom$(ObjectSuffix) \ + $(IntermediateDirectory)/__rt_entry$(ObjectSuffix) + + + +Objects=$(Objects0) + +## +## Main Build Targets +## +.PHONY: all +all: $(IntermediateDirectory)/$(OutputFile) + +$(IntermediateDirectory)/$(OutputFile): $(Objects) Always_Link + $(LinkerName) $(OutputSwitch) $(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) $(LinkerNameoption) -Wl,--ckmap=$(ProjectPath)/Lst/$(OutputFile).map @$(ObjectsFileList) $(LinkOptions) $(LibPath) $(Libs) $(LinkOtherFlagsOption) + -@mv $(ProjectPath)/Lst/$(OutputFile).map $(ProjectPath)/Lst/$(OutputFile).temp && $(READELF) $(ElfInfoSwitch) $(ProjectPath)/Obj/$(OutputFile)$(ExeSuffix) > $(ProjectPath)/Lst/$(OutputFile).map && echo ====================================================================== >> $(ProjectPath)/Lst/$(OutputFile).map && cat $(ProjectPath)/Lst/$(OutputFile).temp >> $(ProjectPath)/Lst/$(OutputFile).map && rm -rf $(ProjectPath)/Lst/$(OutputFile).temp + $(OBJCOPY) $(ObjcopySwitch) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) $(ProjectPath)/Obj/$(OutputFile)$(IHexSuffix) + $(OBJDUMP) $(ObjdumpSwitch) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) > $(ProjectPath)/Lst/$(OutputFile)$(DisassemSuffix) + @echo size of target: + @$(SIZE) $(ProjectPath)$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) + @echo -n checksum value of target: + @$(CHECKSUM) $(ProjectPath)/$(IntermediateDirectory)/$(OutputFile)$(ExeSuffix) + @MD203F8P.modify.bat $(IntermediateDirectory) $(OutputFile)$(ExeSuffix) + +Always_Link: + + +## +## Objects +## +$(IntermediateDirectory)/arch_crt0$(ObjectSuffix): arch/crt0.S + $(AS) $(SourceSwitch) arch/crt0.S $(ASFLAGS) -MMD -MP -MT$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) -MF$(IntermediateDirectory)/arch_crt0$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/arch_crt0$(ObjectSuffix) $(IncludeAPath) $(IncludePackagePath) +Lst/arch_crt0$(PreprocessSuffix): arch/crt0.S + $(CC) $(CFLAGS)$(IncludeAPath) $(PreprocessOnlySwitch) $(OutputSwitch) Lst/arch_crt0$(PreprocessSuffix) arch/crt0.S + +$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix): arch/mem_init.c + $(CC) $(SourceSwitch) arch/mem_init.c $(CFLAGS) -MMD -MP -MT$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) -MF$(IntermediateDirectory)/arch_mem_init$(DependSuffix) $(ObjectSwitch)$(IntermediateDirectory)/arch_mem_init$(ObjectSuffix) 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$(ASFLAGS) $(ObjectSwitch)$(IntermediateDirectory)/__rt_entry$(ObjectSuffix) $(IncludeAPath) +$(IntermediateDirectory)/__rt_entry$(DependSuffix): + @$(CC) $(CFLAGS) $(IncludeAPath) -MG -MP -MT$(IntermediateDirectory)/__rt_entry$(ObjectSuffix) -MF$(IntermediateDirectory)/__rt_entry$(DependSuffix) -MM $(ProjectPath)/$(IntermediateDirectory)/__rt_entry.S + +-include $(IntermediateDirectory)/*$(DependSuffix) diff --git a/Source/MD203F8P.modify.bat b/Source/MD203F8P.modify.bat new file mode 100644 index 0000000..fc3c788 --- /dev/null +++ b/Source/MD203F8P.modify.bat @@ -0,0 +1,3 @@ +@echo off +SET PATH=%Systemroot%\System32;%PATH% +forfiles.exe -P "%1" -M %2 -C "cmd /c echo %1/%2 is modified at: @fdate @ftime" | findstr modified diff --git a/Source/Makefile b/Source/Makefile new file mode 100644 index 0000000..dc3cb84 --- /dev/null +++ b/Source/Makefile @@ -0,0 +1,8 @@ +.PHONY: clean All + +All: + @echo "----------Building project:[ apt32f102 - BuildSet ]----------" + @cd "C:\Users\yupp.APT-HZ\Desktop\APT32F102_Release_V0_50_20190715\Source" && make -f "apt32f102.mk" +clean: + @echo "----------Cleaning project:[ apt32f102 - BuildSet ]----------" + @cd "C:\Users\yupp.APT-HZ\Desktop\APT32F102_Release_V0_50_20190715\Source" && make -f "apt32f102.mk" clean diff --git a/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.elf b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.elf new file mode 100644 index 0000000..8d0b41d Binary files /dev/null and b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.elf differ diff --git a/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.ihex b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.ihex new file mode 100644 index 0000000..7fdd515 --- /dev/null +++ b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117.ihex @@ -0,0 +1,1639 @@ +:100000000C010000062E0000F62D00008401000007 +:10001000FE2D0000BC2D000084010000EE2D00002C +:10002000E62D00008401000084010000840100002E +:1000300084010000840100008401000084010000AC +:10004000DE2D0000D62D0000CE2D0000C62D0000B4 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+:10611C000000084000F000600020006000000060FB +:10612C00000003400010024000000240001001403B +:08613C000000014000E000E05A +:040000050000010CEA +:00000001FF diff --git a/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117_0x0.bin b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117_0x0.bin new file mode 100644 index 0000000..2ec6eb0 Binary files /dev/null and b/Source/Obj/BLV_C8_PLC_MASTER_V07_20260117_0x0.bin differ diff --git a/Source/Obj/FWlib_apt32f102_adc.d b/Source/Obj/FWlib_apt32f102_adc.d new file mode 100644 index 0000000..1b0fd65 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_adc.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_adc.o: FWlib/apt32f102_adc.c include/apt32f102_adc.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_adc.o b/Source/Obj/FWlib_apt32f102_adc.o new file mode 100644 index 0000000..942de74 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_adc.o differ diff --git a/Source/Obj/FWlib_apt32f102_bt.d b/Source/Obj/FWlib_apt32f102_bt.d new file mode 100644 index 0000000..d3afe77 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_bt.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_bt.o: FWlib/apt32f102_bt.c include/apt32f102_bt.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_bt.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_bt.o b/Source/Obj/FWlib_apt32f102_bt.o new file mode 100644 index 0000000..1d55956 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_bt.o differ diff --git a/Source/Obj/FWlib_apt32f102_coret.d b/Source/Obj/FWlib_apt32f102_coret.d new file mode 100644 index 0000000..c348c18 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_coret.d @@ -0,0 +1,14 @@ +Obj/FWlib_apt32f102_coret.o: FWlib/apt32f102_coret.c \ + include/apt32f102_coret.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_syscon.h + +include/apt32f102_coret.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_syscon.h: diff --git a/Source/Obj/FWlib_apt32f102_coret.o b/Source/Obj/FWlib_apt32f102_coret.o new file mode 100644 index 0000000..96b24f8 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_coret.o differ diff --git a/Source/Obj/FWlib_apt32f102_countera.d b/Source/Obj/FWlib_apt32f102_countera.d new file mode 100644 index 0000000..7e6968f --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_countera.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_countera.o: FWlib/apt32f102_countera.c \ + include/apt32f102_countera.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102_countera.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_countera.o b/Source/Obj/FWlib_apt32f102_countera.o new file mode 100644 index 0000000..a897c2c Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_countera.o differ diff --git a/Source/Obj/FWlib_apt32f102_crc.d b/Source/Obj/FWlib_apt32f102_crc.d new file mode 100644 index 0000000..20a9e11 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_crc.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_crc.o: FWlib/apt32f102_crc.c include/apt32f102_crc.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_crc.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_crc.o b/Source/Obj/FWlib_apt32f102_crc.o new file mode 100644 index 0000000..609a5ad Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_crc.o differ diff --git a/Source/Obj/FWlib_apt32f102_ept.d b/Source/Obj/FWlib_apt32f102_ept.d new file mode 100644 index 0000000..b340f6c --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_ept.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_ept.o: FWlib/apt32f102_ept.c include/apt32f102_ept.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_ept.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_ept.o b/Source/Obj/FWlib_apt32f102_ept.o new file mode 100644 index 0000000..4422c7e Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_ept.o differ diff --git a/Source/Obj/FWlib_apt32f102_et.d b/Source/Obj/FWlib_apt32f102_et.d new file mode 100644 index 0000000..53a2f02 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_et.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_et.o: FWlib/apt32f102_et.c include/apt32f102_et.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_et.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_et.o b/Source/Obj/FWlib_apt32f102_et.o new file mode 100644 index 0000000..3f9f119 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_et.o differ diff --git a/Source/Obj/FWlib_apt32f102_gpio.d b/Source/Obj/FWlib_apt32f102_gpio.d new file mode 100644 index 0000000..86af067 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_gpio.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_gpio.o: FWlib/apt32f102_gpio.c \ + include/apt32f102_gpio.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102_gpio.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_gpio.o b/Source/Obj/FWlib_apt32f102_gpio.o new file mode 100644 index 0000000..cb2f3a4 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_gpio.o differ diff --git a/Source/Obj/FWlib_apt32f102_gpt.d b/Source/Obj/FWlib_apt32f102_gpt.d new file mode 100644 index 0000000..fd9e95c --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_gpt.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_gpt.o: FWlib/apt32f102_gpt.c include/apt32f102_gpt.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_gpt.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_gpt.o b/Source/Obj/FWlib_apt32f102_gpt.o new file mode 100644 index 0000000..dd14341 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_gpt.o differ diff --git a/Source/Obj/FWlib_apt32f102_i2c.d b/Source/Obj/FWlib_apt32f102_i2c.d new file mode 100644 index 0000000..d3e7f34 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_i2c.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_i2c.o: FWlib/apt32f102_i2c.c include/apt32f102_i2c.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_i2c.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_i2c.o b/Source/Obj/FWlib_apt32f102_i2c.o new file mode 100644 index 0000000..3d1ef49 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_i2c.o differ diff --git a/Source/Obj/FWlib_apt32f102_ifc.d b/Source/Obj/FWlib_apt32f102_ifc.d new file mode 100644 index 0000000..1913cf8 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_ifc.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_ifc.o: FWlib/apt32f102_ifc.c include/apt32f102_ifc.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_ifc.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_ifc.o b/Source/Obj/FWlib_apt32f102_ifc.o new file mode 100644 index 0000000..04344bb Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_ifc.o differ diff --git a/Source/Obj/FWlib_apt32f102_lpt.d b/Source/Obj/FWlib_apt32f102_lpt.d new file mode 100644 index 0000000..deda227 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_lpt.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_lpt.o: FWlib/apt32f102_lpt.c include/apt32f102_lpt.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_lpt.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_lpt.o b/Source/Obj/FWlib_apt32f102_lpt.o new file mode 100644 index 0000000..db34eb2 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_lpt.o differ diff --git a/Source/Obj/FWlib_apt32f102_rtc.d b/Source/Obj/FWlib_apt32f102_rtc.d new file mode 100644 index 0000000..615321c --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_rtc.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_rtc.o: FWlib/apt32f102_rtc.c include/apt32f102_rtc.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_rtc.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_rtc.o b/Source/Obj/FWlib_apt32f102_rtc.o new file mode 100644 index 0000000..7b424b4 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_rtc.o differ diff --git a/Source/Obj/FWlib_apt32f102_sio.d b/Source/Obj/FWlib_apt32f102_sio.d new file mode 100644 index 0000000..a96733c --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_sio.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_sio.o: FWlib/apt32f102_sio.c include/apt32f102_sio.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_sio.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_sio.o b/Source/Obj/FWlib_apt32f102_sio.o new file mode 100644 index 0000000..eadcf1a Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_sio.o differ diff --git a/Source/Obj/FWlib_apt32f102_spi.d b/Source/Obj/FWlib_apt32f102_spi.d new file mode 100644 index 0000000..097eac5 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_spi.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_spi.o: FWlib/apt32f102_spi.c include/apt32f102_spi.h \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h + +include/apt32f102_spi.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_spi.o b/Source/Obj/FWlib_apt32f102_spi.o new file mode 100644 index 0000000..e835fed Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_spi.o differ diff --git a/Source/Obj/FWlib_apt32f102_syscon.d b/Source/Obj/FWlib_apt32f102_syscon.d new file mode 100644 index 0000000..622babc --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_syscon.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_syscon.o: FWlib/apt32f102_syscon.c \ + include/apt32f102_syscon.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102_syscon.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_syscon.o b/Source/Obj/FWlib_apt32f102_syscon.o new file mode 100644 index 0000000..c221132 Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_syscon.o differ diff --git a/Source/Obj/FWlib_apt32f102_uart.d b/Source/Obj/FWlib_apt32f102_uart.d new file mode 100644 index 0000000..cb50615 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_uart.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_uart.o: FWlib/apt32f102_uart.c \ + include/apt32f102_uart.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102_uart.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_uart.o b/Source/Obj/FWlib_apt32f102_uart.o new file mode 100644 index 0000000..190cf7c Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_uart.o differ diff --git a/Source/Obj/FWlib_apt32f102_wwdt.d b/Source/Obj/FWlib_apt32f102_wwdt.d new file mode 100644 index 0000000..671e7e6 --- /dev/null +++ b/Source/Obj/FWlib_apt32f102_wwdt.d @@ -0,0 +1,11 @@ +Obj/FWlib_apt32f102_wwdt.o: FWlib/apt32f102_wwdt.c \ + include/apt32f102_wwdt.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102_wwdt.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/FWlib_apt32f102_wwdt.o b/Source/Obj/FWlib_apt32f102_wwdt.o new file mode 100644 index 0000000..60b934e Binary files /dev/null and b/Source/Obj/FWlib_apt32f102_wwdt.o differ diff --git a/Source/Obj/MD203F8P.txt b/Source/Obj/MD203F8P.txt new file mode 100644 index 0000000..e213602 --- /dev/null +++ b/Source/Obj/MD203F8P.txt @@ -0,0 +1 @@ +Obj/arch_crt0.o Obj/arch_mem_init.o Obj/arch_apt32f102_iostring.o Obj/FWlib_apt32f102_syscon.o Obj/FWlib_apt32f102_gpio.o Obj/FWlib_apt32f102_lpt.o Obj/FWlib_apt32f102_crc.o Obj/FWlib_apt32f102_wwdt.o Obj/FWlib_apt32f102_countera.o Obj/FWlib_apt32f102_et.o Obj/FWlib_apt32f102_bt.o Obj/FWlib_apt32f102_gpt.o Obj/FWlib_apt32f102_sio.o Obj/FWlib_apt32f102_spi.o Obj/FWlib_apt32f102_uart.o Obj/FWlib_apt32f102_i2c.o Obj/FWlib_apt32f102_ept.o Obj/FWlib_apt32f102_rtc.o Obj/FWlib_apt32f102_adc.o Obj/FWlib_apt32f102_ifc.o Obj/FWlib_apt32f102_coret.o Obj/main.o Obj/mcu_initial.o Obj/mcu_interrupt.o Obj/drivers_apt32f102.o Obj/drivers_apt32f102_ck801.o Obj/SYSTEM_uart.o Obj/SYSTEM_pb_fun.o Obj/SYSTEM_pwm.o Obj/SYSTEM_eeprom.o Obj/__rt_entry.o \ No newline at end of file diff --git a/Source/Obj/SYSTEM_eeprom.d b/Source/Obj/SYSTEM_eeprom.d new file mode 100644 index 0000000..58954a5 --- /dev/null +++ b/Source/Obj/SYSTEM_eeprom.d @@ -0,0 +1,72 @@ +Obj/SYSTEM_eeprom.o: SYSTEM/eeprom.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/SYSTEM_eeprom.o b/Source/Obj/SYSTEM_eeprom.o new file mode 100644 index 0000000..b529516 Binary files /dev/null and b/Source/Obj/SYSTEM_eeprom.o differ diff --git a/Source/Obj/SYSTEM_pb_fun.d b/Source/Obj/SYSTEM_pb_fun.d new file mode 100644 index 0000000..9c1b7e6 --- /dev/null +++ b/Source/Obj/SYSTEM_pb_fun.d @@ -0,0 +1,72 @@ +Obj/SYSTEM_pb_fun.o: SYSTEM/pb_fun.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/SYSTEM_pb_fun.o b/Source/Obj/SYSTEM_pb_fun.o new file mode 100644 index 0000000..d08d644 Binary files /dev/null and b/Source/Obj/SYSTEM_pb_fun.o differ diff --git a/Source/Obj/SYSTEM_pwm.d b/Source/Obj/SYSTEM_pwm.d new file mode 100644 index 0000000..3af3bb6 --- /dev/null +++ b/Source/Obj/SYSTEM_pwm.d @@ -0,0 +1,72 @@ +Obj/SYSTEM_pwm.o: SYSTEM/pwm.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/SYSTEM_pwm.o b/Source/Obj/SYSTEM_pwm.o new file mode 100644 index 0000000..09c4972 Binary files /dev/null and b/Source/Obj/SYSTEM_pwm.o differ diff --git a/Source/Obj/SYSTEM_uart.d b/Source/Obj/SYSTEM_uart.d new file mode 100644 index 0000000..7d59944 --- /dev/null +++ b/Source/Obj/SYSTEM_uart.d @@ -0,0 +1,72 @@ +Obj/SYSTEM_uart.o: SYSTEM/uart.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/SYSTEM_uart.o b/Source/Obj/SYSTEM_uart.o new file mode 100644 index 0000000..35c5f78 Binary files /dev/null and b/Source/Obj/SYSTEM_uart.o differ diff --git a/Source/Obj/__rt_entry.S b/Source/Obj/__rt_entry.S new file mode 100644 index 0000000..8b9bb64 --- /dev/null +++ b/Source/Obj/__rt_entry.S @@ -0,0 +1,139 @@ + + .global __main + .weak __main + .global __e_rom + .weak __e_rom + .global __s_ram_data_1 + .weak __s_ram_data_1 + .global __e_ram_data_1 + .weak __e_ram_data_1 + .global __s_ram_bss_1 + .weak __s_ram_bss_1 + .global __e_ram_bss_1 + .weak __e_ram_bss_1 + .global __s_ram_data_2 + .weak __s_ram_data_2 + .global __e_ram_data_2 + .weak __e_ram_data_2 + .global __s_ram_bss_2 + .weak __s_ram_bss_2 + .global __e_ram_bss_2 + .weak __e_ram_bss_2 + .global __s_ram_data_3 + .weak __s_ram_data_3 + .global __e_ram_data_3 + .weak __e_ram_data_3 + .global __s_ram_bss_3 + .weak __s_ram_bss_3 + .global __e_ram_bss_3 + .weak __e_ram_bss_3 + .global __s_ram_data_4 + .weak __s_ram_data_4 + .global __e_ram_data_4 + .weak __e_ram_data_4 + .global __s_ram_bss_4 + .weak __s_ram_bss_4 + .global __e_ram_bss_4 + .weak __e_ram_bss_4 + .global __s_ram_data_5 + .weak __s_ram_data_5 + .global __e_ram_data_5 + .weak __e_ram_data_5 + .global __s_ram_bss_5 + .weak __s_ram_bss_5 + .global __e_ram_bss_5 + .weak __e_ram_bss_5 + .global __ChipInitHandler + .weak __ChipInitHandler + + .text + .align 3 + __bss_initialization: + subu a2, a3 + lsri a2, 2 + cmpnei a2, 0 + bf 2f + movi a1, 0 + 1: + stw a1, (a3) + addi a3, 4 + subi a2, 1 + cmpnei a2, 0 + bt 1b + 2: + jmp r15 + + __rom_decompression: + cmphs a1, a2 + bt 4f + 3: + ld.w a3, (a0, 0) + st.w a3, (a1, 0) + addi a0, 4 + addi a1, 4 + cmphs a1, a2 + bf 3b + 4: + jmp r15 + + __main: + mov r6, r15 + lrw a3, __s_ram_bss_1 + lrw a2, __e_ram_bss_1 + bsr __bss_initialization + lrw a3, __s_ram_bss_2 + lrw a2, __e_ram_bss_2 + bsr __bss_initialization + lrw a3, __s_ram_bss_3 + lrw a2, __e_ram_bss_3 + bsr __bss_initialization + lrw a3, __s_ram_bss_4 + lrw a2, __e_ram_bss_4 + bsr __bss_initialization + lrw a3, __s_ram_bss_5 + lrw a2, __e_ram_bss_5 + bsr __bss_initialization + lrw a0, __e_rom + lrw a1, __s_ram_data_1 + lrw a2, __e_ram_data_1 + bsr __rom_decompression + lrw a1, __s_ram_data_2 + lrw a2, __e_ram_data_2 + bsr __rom_decompression + lrw a1, __s_ram_data_3 + lrw a2, __e_ram_data_3 + bsr __rom_decompression + lrw a1, __s_ram_data_4 + lrw a2, __e_ram_data_4 + bsr __rom_decompression + lrw a1, __s_ram_data_5 + lrw a2, __e_ram_data_5 + bsr __rom_decompression + #ifdef __CSKYABIV2__ + subi sp, 4 + stw r6, (sp, 0) + lrw a0, __ChipInitHandler + cmpnei a0, 0 + bf 1f + jsr a0 + 1: + lrw a0, main + jsr a0 + #else + subi sp, 8 + stw r6, (sp, 0) + lrw a0, __ChipInitHandler + cmpnei a0, 0 + bf 1f + jsri __ChipInitHandler + 1: + jsri main + #endif + ldw r15, (sp, 0) + #ifdef __CSKYABIV2__ + addi sp, 4 + #else + addi sp, 8 + #endif + jmp r15 + \ No newline at end of file diff --git a/Source/Obj/__rt_entry.d b/Source/Obj/__rt_entry.d new file mode 100644 index 0000000..21afacb --- /dev/null +++ b/Source/Obj/__rt_entry.d @@ -0,0 +1 @@ +Obj/__rt_entry.o: Obj/__rt_entry.S diff --git a/Source/Obj/__rt_entry.o b/Source/Obj/__rt_entry.o new file mode 100644 index 0000000..678005f Binary files /dev/null and b/Source/Obj/__rt_entry.o differ diff --git a/Source/Obj/arch_apt32f102_iostring.d b/Source/Obj/arch_apt32f102_iostring.d new file mode 100644 index 0000000..8aea0fc --- /dev/null +++ b/Source/Obj/arch_apt32f102_iostring.d @@ -0,0 +1,13 @@ +Obj/arch_apt32f102_iostring.o: arch/apt32f102_iostring.c \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h include/apt32f102_uart.h include/apt32f102.h + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_uart.h: + +include/apt32f102.h: diff --git a/Source/Obj/arch_apt32f102_iostring.o b/Source/Obj/arch_apt32f102_iostring.o new file mode 100644 index 0000000..4ba42a4 Binary files /dev/null and b/Source/Obj/arch_apt32f102_iostring.o differ diff --git a/Source/Obj/arch_crt0.d b/Source/Obj/arch_crt0.d new file mode 100644 index 0000000..430c939 --- /dev/null +++ b/Source/Obj/arch_crt0.d @@ -0,0 +1 @@ +Obj/arch_crt0.o: arch/crt0.S diff --git a/Source/Obj/arch_crt0.o b/Source/Obj/arch_crt0.o new file mode 100644 index 0000000..1733c69 Binary files /dev/null and b/Source/Obj/arch_crt0.o differ diff --git a/Source/Obj/arch_mem_init.d b/Source/Obj/arch_mem_init.d new file mode 100644 index 0000000..c3cd9c6 --- /dev/null +++ b/Source/Obj/arch_mem_init.d @@ -0,0 +1 @@ +Obj/arch_mem_init.o: arch/mem_init.c diff --git a/Source/Obj/arch_mem_init.o b/Source/Obj/arch_mem_init.o new file mode 100644 index 0000000..0fb53a5 Binary files /dev/null and b/Source/Obj/arch_mem_init.o differ diff --git a/Source/Obj/drivers_apt32f102.d b/Source/Obj/drivers_apt32f102.d new file mode 100644 index 0000000..9d7f972 --- /dev/null +++ b/Source/Obj/drivers_apt32f102.d @@ -0,0 +1,8 @@ +Obj/drivers_apt32f102.o: drivers/apt32f102.c include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/drivers_apt32f102.o b/Source/Obj/drivers_apt32f102.o new file mode 100644 index 0000000..84d14e6 Binary files /dev/null and b/Source/Obj/drivers_apt32f102.o differ diff --git a/Source/Obj/drivers_apt32f102_ck801.d b/Source/Obj/drivers_apt32f102_ck801.d new file mode 100644 index 0000000..8d9ab1a --- /dev/null +++ b/Source/Obj/drivers_apt32f102_ck801.d @@ -0,0 +1,11 @@ +Obj/drivers_apt32f102_ck801.o: drivers/apt32f102_ck801.c \ + include/apt32f102.h include/apt32f102_types_local.h \ + include/apt32f102_ck801.h include/apt32f102_ck801.h + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_ck801.h: diff --git a/Source/Obj/drivers_apt32f102_ck801.o b/Source/Obj/drivers_apt32f102_ck801.o new file mode 100644 index 0000000..221be6c Binary files /dev/null and b/Source/Obj/drivers_apt32f102_ck801.o differ diff --git a/Source/Obj/main.d b/Source/Obj/main.d new file mode 100644 index 0000000..68c978b --- /dev/null +++ b/Source/Obj/main.d @@ -0,0 +1,72 @@ +Obj/main.o: main.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/main.o b/Source/Obj/main.o new file mode 100644 index 0000000..90ab505 Binary files /dev/null and b/Source/Obj/main.o differ diff --git a/Source/Obj/mcu_initial.d b/Source/Obj/mcu_initial.d new file mode 100644 index 0000000..dc15363 --- /dev/null +++ b/Source/Obj/mcu_initial.d @@ -0,0 +1,72 @@ +Obj/mcu_initial.o: mcu_initial.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/mcu_initial.o b/Source/Obj/mcu_initial.o new file mode 100644 index 0000000..d1265d2 Binary files /dev/null and b/Source/Obj/mcu_initial.o differ diff --git a/Source/Obj/mcu_interrupt.d b/Source/Obj/mcu_interrupt.d new file mode 100644 index 0000000..fca7ec2 --- /dev/null +++ b/Source/Obj/mcu_interrupt.d @@ -0,0 +1,72 @@ +Obj/mcu_interrupt.o: mcu_interrupt.c includes.h include/apt32f102.h \ + include/apt32f102_types_local.h include/apt32f102_ck801.h \ + include/apt32f102_adc.h include/apt32f102.h include/apt32f102_bt.h \ + include/apt32f102_coret.h include/apt32f102_countera.h \ + include/apt32f102_crc.h include/apt32f102_ept.h include/apt32f102_et.h \ + include/apt32f102_gpio.h include/apt32f102_gpt.h include/apt32f102_i2c.h \ + include/apt32f102_ifc.h include/apt32f102_lpt.h include/apt32f102_rtc.h \ + include/apt32f102_sio.h include/apt32f102_spi.h \ + include/apt32f102_syscon.h include/apt32f102_uart.h \ + include/apt32f102_wwdt.h include/apt32f102_types_local.h \ + include/apt32f102_clkcalib.h SYSTEM/inc/uart.h SYSTEM/inc/pb_fun.h \ + SYSTEM/inc/pwm.h SYSTEM/inc/pwm.h SYSTEM/inc/eeprom.h + +includes.h: + +include/apt32f102.h: + +include/apt32f102_types_local.h: + +include/apt32f102_ck801.h: + +include/apt32f102_adc.h: + +include/apt32f102.h: + +include/apt32f102_bt.h: + +include/apt32f102_coret.h: + +include/apt32f102_countera.h: + +include/apt32f102_crc.h: + +include/apt32f102_ept.h: + +include/apt32f102_et.h: + +include/apt32f102_gpio.h: + +include/apt32f102_gpt.h: + +include/apt32f102_i2c.h: + +include/apt32f102_ifc.h: + +include/apt32f102_lpt.h: + +include/apt32f102_rtc.h: + +include/apt32f102_sio.h: + +include/apt32f102_spi.h: + +include/apt32f102_syscon.h: + +include/apt32f102_uart.h: + +include/apt32f102_wwdt.h: + +include/apt32f102_types_local.h: + +include/apt32f102_clkcalib.h: + +SYSTEM/inc/uart.h: + +SYSTEM/inc/pb_fun.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/pwm.h: + +SYSTEM/inc/eeprom.h: diff --git a/Source/Obj/mcu_interrupt.o b/Source/Obj/mcu_interrupt.o new file mode 100644 index 0000000..fb06f2e Binary files /dev/null and b/Source/Obj/mcu_interrupt.o differ diff --git a/Source/Project.cdkproj b/Source/Project.cdkproj new file mode 100644 index 0000000..4b4926c --- /dev/null +++ b/Source/Project.cdkproj @@ -0,0 +1,457 @@ + + + + + + yes + + + + + 104 + 90 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NULL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CKV2ElfMinilib + latest + + + + CK801:1;i_temp:1;j_temp:1;k_temp:1;GPIOB0:1;GPIOA0:1;SYSCON:1;test_d:1;LPT:1;BT0:1;Key_Map:1;DFLASH_rdata:1;TKEYBUF:1;g_uart.DealBuff:1 + 0x00080140;;; + ;;32;;MHZ; + + SYSCON + + 1 + 0 + layout2|name=Project View;caption=Project View;state=31459324;dir=4;layer=1;row=0;pos=0;prop=68571;bestw=456;besth=277;minw=10;minh=5;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Debugger;caption=Debugger;state=14682108;dir=3;layer=1;row=0;pos=0;prop=86169;bestw=341;besth=315;minw=10;minh=5;maxw=-1;maxh=-1;floatx=60;floaty=707;floatw=418;floath=340|name=Frame Info;caption=Frame Info;state=14698492;dir=3;layer=1;row=0;pos=1;prop=106705;bestw=400;besth=300;minw=10;minh=5;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Peripherals;caption=Peripherals;state=31459326;dir=3;layer=1;row=0;pos=4;prop=100000;bestw=11;besth=43;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Serial Pane;caption=Serial Pane;state=14682110;dir=3;layer=1;row=0;pos=4;prop=100000;bestw=400;besth=300;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Editor;caption=;state=256;dir=5;layer=0;row=0;pos=0;prop=100000;bestw=20;besth=20;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Output View;caption=Output View;state=31459326;dir=3;layer=1;row=0;pos=1;prop=100000;bestw=958;besth=244;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=-1;floaty=-1;floatw=-1;floath=-1|name=Disassemble;caption=Disassemble;state=2099198;dir=3;layer=1;row=0;pos=2;prop=158373;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=1746;floaty=812;floatw=216;floath=236|name=Register;caption=Register;state=2099198;dir=4;layer=1;row=0;pos=1;prop=100000;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=83;floaty=444;floatw=218;floath=240|name=Outline;caption=Outline;state=2099198;dir=2;layer=0;row=2;pos=0;prop=100000;bestw=200;besth=200;minw=-1;minh=-1;maxw=-1;maxh=-1;floatx=1823;floaty=285;floatw=216;floath=236|dock_size(4,1,0)=210|dock_size(5,0,0)=20|dock_size(3,1,0)=335| + 100:4;100:8;100:8;100:8; + + + + + + + + yes + 0x00000000 + 0x00010000 + + + no + + + + + no + + + + + no + + + + + no + + + + + + + yes + 0x20000000 + 0x20001000 + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + ck801 + yes + little + no + no + no + no + + + BLV_C8_PLC_MASTER_V07_20260117 + Executable + yes + yes + no + yes + no + yes + + + + no + + no + + + no + + no + + + no + + no + + + + + CONFIG_CSKY_MMU=0 + __CSKY_ABIV2__ + Optimize size (-Os) + Default (-g) + $(CDKPath)/CSKY/csi/csi_core/csi_cdk/;$(CDKPath)/CSKY/csi/csi_core/include/;$(CDKPath)/CSKY/csi/csi_driver/include/;$(ProjectPath);$(ProjectPath)/SYSTEM/inc;$(ProjectPath)/include + -mistack + no + no + no + no + no + no + no + no + yes + no + no + + + CONFIG_CKCPU_MMU=0 + __CSKY_ABIV2__ + $(CDKPath)/CSKY/csi/csi_core/csi_cdk/;$(CDKPath)/CSKY/csi/csi_core/include/;$(CDKPath)/CSKY/csi/csi_driver/include/;$(ProjectPath);$(ProjectPath)//SYSTEM;$(ProjectPath)/SYSTEM/inc + + gdwarf2 + + + yes + yes + $(ProjectPath)/ckcpu.ld + lib_102ClkCalib_1_03;libm + $(ProjectPath) + + no + + no + none + no + + + yes + ICE + yes + main + + + + yes + Soft Reset + abcd1234 + no + + no + $(ProjectPath)/$(ProjectName).cdkcore + + + localhost + 1025 + 0 + 1500 + 10 + 100 + 50 + yes + no + no + yes + Normal + Soft Reset + abcd1234 + Bare Metal + yes + yes + + Local + + yes + 1000 + yes + 1026 + latest + no + + + soccfg/cskyv2/smart_card_802_cfg.xml + + yes + no + no + latest + + + + yes + no + 4444 + no + 6666 + + 5000 + localhost + 3333 + openocd-sifive + latest + + + + + + Erase Full Chip + APT32F102_FLASHDOWN.elf + yes + yes + yes + Soft Reset + abcd1234 + no + 0 + no + + + + + + diff --git a/Source/Project.cdkws b/Source/Project.cdkws new file mode 100644 index 0000000..2dd9677 --- /dev/null +++ b/Source/Project.cdkws @@ -0,0 +1,11 @@ + + + $(CDKWS)\__workspace_pack__ + + + + + + + + diff --git a/Source/Project.tags b/Source/Project.tags new file mode 100644 index 0000000..66596bb Binary files /dev/null and b/Source/Project.tags differ diff --git a/Source/SYSTEM/eeprom.c b/Source/SYSTEM/eeprom.c new file mode 100644 index 0000000..2c5c4f5 --- /dev/null +++ b/Source/SYSTEM/eeprom.c @@ -0,0 +1,159 @@ +#include "includes.h" + +E_PARA_INFO g_eeprom; + +void EEPROM_Init(void){ + U8_T rev = 0; + EnIFCClk; //使能 IFC 时钟 + IFC->MR |= 0x10002; //高速模式，延迟 2 个周期 + + delay_nms(10); + + rev = EEPROM_ReadParaInfo(&g_eeprom); + if(rev != 0x00){ + //读取失败，恢复默认参数 + EEPROM_Default_ParaInfo(&g_eeprom); + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info Use Default"); + } + + EEPROM_Validate_ParaInfo(&g_eeprom); +} + + +U8_T EEPROM_ReadParaInfo(E_PARA_INFO *info){ + U8_T read_info[6]; + U8_T para_data[EEPROM_DATA_Size_Max]; + U16_T read_len = 0; + + memset(read_info,0,sizeof(read_info)); + memset(para_data,0,sizeof(para_data)); + + ReadDataArry_U8(EEPROM_ParaInfo_Address,4,read_info); + + if(read_info[0] == EEPROM_SVAE_FLAG){ + read_len = read_info[2]; + read_len <<= 8; + read_len |= read_info[1]; + + if(read_len <= EEPROM_DATA_Size_Max){ + + ReadDataArry_U8(EEPROM_ParaInfo_Address+4,read_len,para_data); + if(PB_CheckSum(para_data,sizeof(E_PARA_INFO)) == read_info[3]){ + //校验成功 + memcpy((uint8_t *)info,para_data,sizeof(E_PARA_INFO)); + + return 0x00; + } + } + } + + return 0x01; +} + +U8_T EEPROM_WriteParaInfo(E_PARA_INFO *info){ + U8_T save_data[EEPROM_DATA_Size_Max + 6]; + U16_T save_len = sizeof(E_PARA_INFO); + + if(save_len >= EEPROM_DATA_Size_Max) save_len = EEPROM_DATA_Size_Max; + + save_data[0] = EEPROM_SVAE_FLAG; + save_data[1] = save_len & 0xFF; + save_data[2] = (save_len >> 8) & 0xFF; + + memcpy(&save_data[4],(uint8_t *)info,save_len); + + save_data[3] = PB_CheckSum(&save_data[4],save_len); + + save_len+=4; + + Page_ProgramData(EEPROM_ParaInfo_Address,save_len,save_data); + + return 0; +} + +U8_T EEPROM_ClearParaInfo(void){ + U8_T save_data[EEPROM_DATA_Size_Max+10]; + UINT16 save_len = sizeof(E_PARA_INFO); + + if(save_len >= EEPROM_DATA_Size_Max) save_len = EEPROM_DATA_Size_Max; + + save_len += 4; + memset(save_data,0xFF,save_len); + + Page_ProgramData(EEPROM_ParaInfo_Address,save_len,save_data); + + return 0; +} + +U8_T EEPROM_Validate_ParaInfo(E_PARA_INFO *info){ + U8_T i=0; + + //以下为本地参数 + + //PowerBus 总线开关 0x01:开启，0x02:关闭 + if((info->powerbus_enable < 0x01) || (info->powerbus_enable > 0x01) ){ + info->powerbus_enable = EEPROM_ParaDefault_PowerBusEnable; //默认开启 + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info powerbus_enable %d",info->powerbus_enable); + + //PowerBus 总线保护电流范围：1~165 单位：0.1A 1V = 5A + //因为 BLV_C8_V05 硬件版本目前芯片供电为3.3V,提供给保护阈值电压最高为3.3V,所以保护电流最高为16.5A + if((info->save_curr < PB_SaveCurrent_Min) || (info->save_curr > PB_SaveCurrent_Max)){ + info->save_curr = EEPROM_ParaDefault_SaveCurr; //默认保护电流为10A + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info save_curr %d",info->save_curr); + + + //以下为灯光参数校验 + + //全局亮度有效范围：0~100 + if(info->allBrightness > BRIGHTNESS_MAX){ + info->allBrightness = BRIGHTNESS_MAX; //全局亮度默认：100 + } + + //全局亮度可调上限有效范围：0~100 + if(info->allBrightnessUpLimit > BRIGHTNESS_MAX){ + info->allBrightnessUpLimit = BRIGHTNESS_MAX; //全局亮度可调上限默认：100 + } + + //全局亮度可调下限有效范围：0~100 + if(info->allBrightnessDownLimit > BRIGHTNESS_MAX){ + info->allBrightnessDownLimit = BRIGHTNESS_MIN; //全局亮度可调下限默认：0 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightness %d",info->allBrightness); + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightnessUpLimit %d",info->allBrightnessUpLimit); + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Info allBrightnessDownLimit %d",info->allBrightnessDownLimit); + + for(i=0;iswithcState[i] > 0x01){ + info->swithcState[i] = 0x01; //回路开关状态默认：0x01 + } + + //回路亮度：0~100 + if(info->brightness[i] > BRIGHTNESS_MAX){ + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Para Light Loop%d %d-%d",i,info->swithcState[i],info->brightness[i]); + } + + return 0; +} + +/*恢复默认值*/ +void EEPROM_Default_ParaInfo(E_PARA_INFO *info){ + info->powerbus_enable = EEPROM_ParaDefault_PowerBusEnable; + info->save_curr = EEPROM_ParaDefault_SaveCurr; + info->allBrightness = BRIGHTNESS_MAX; //全局亮度默认：100 + info->allBrightnessUpLimit = BRIGHTNESS_MAX; //全局亮度可调上限默认：100 + info->allBrightnessDownLimit = BRIGHTNESS_MIN; //全局亮度可调下限默认：0 + + for(U8_T i=0;iswithcState[i] = 0x01; //回路开关状态默认：0x01 + info->brightness[i] = BRIGHTNESS_MIN; //回路亮度默认：100 + info->gradialTime[i] = 1000; //回路渐变时间默认：1000 + } +} + diff --git a/Source/SYSTEM/inc/eeprom.h b/Source/SYSTEM/inc/eeprom.h new file mode 100644 index 0000000..e0bf23e --- /dev/null +++ b/Source/SYSTEM/inc/eeprom.h @@ -0,0 +1,52 @@ +#ifndef _EEPROM_H_ +#define _EEPROM_H_ + +#include "apt32f102.h" + +#define EEPROM_ParaInfo_Address 0x10000020 + +/* EEPROM 保存数据格式： + * FLAG - 1Byte 保存标志位 + * LEN - 2Byte 保存数据长度 + * CHECK - 1Byte 保存数据校验 + * DATA - nByte 保存数据内容 + * + * */ +#define EEPROM_Offset_SaveFlag 0x00 +#define EEPROM_Offset_Datalen 0x01 +#define EEPROM_Offset_Check 0x03 +#define EEPROM_Offset_Data 0x04 + +#define EEPROM_SVAE_FLAG 0xA6 +#define EEPROM_DATA_Size_Max 100 //目前保存数据内容最长为100Byte + +#define EEPROM_ParaDefault_PowerBusEnable 0x01 +#define EEPROM_ParaDefault_SaveCurr 120 //默认保护电流为12A,单位:0.1A + + +typedef struct{ + + U8_T powerbus_enable; //PB电源使能状态 0x01:开启，0x02:关闭 + U8_T save_curr; //保护电流 + + /*调光参数*/ + U8_T allBrightness; //全局调光 0~100 + U8_T allBrightnessUpLimit; //全局调光上限百分比 + U8_T allBrightnessDownLimit; //全局调光下限百分比 + + U8_T swithcState[PWM_OUT_CH_MAX]; //开关状态 0x01:开，0x00:关 + U8_T brightness[PWM_OUT_CH_MAX]; //亮度 0~100 + U16_T gradialTime[PWM_OUT_CH_MAX]; //渐变时间 单位：ms + +}E_PARA_INFO; + +extern E_PARA_INFO g_eeprom; + +void EEPROM_Init(void); +U8_T EEPROM_ReadParaInfo(E_PARA_INFO *info); +U8_T EEPROM_WriteParaInfo(E_PARA_INFO *info); +U8_T EEPROM_ClearParaInfo(void); +U8_T EEPROM_Validate_ParaInfo(E_PARA_INFO *info); +void EEPROM_Default_ParaInfo(E_PARA_INFO *info); + +#endif diff --git a/Source/SYSTEM/inc/pb_fun.h b/Source/SYSTEM/inc/pb_fun.h new file mode 100644 index 0000000..69d2ab1 --- /dev/null +++ b/Source/SYSTEM/inc/pb_fun.h @@ -0,0 +1,263 @@ +#ifndef _PB_FUN_H_ +#define _PB_FUN_H_ + +#include "apt32f102_gpio.h" +#include "pwm.h" + +#define PB_SOFTBOOT_PERIOD 100 //PB软启动一个周期的时间 + +//PB输出控制使能 +#define DRV_PB_ENABLE GPIO_Write_High(GPIOA0,12) +#define DRV_PB_DISABLE GPIO_Write_Low(GPIOA0,12) + +#define DRV_PB36V_ON GPIO_Write_High(GPIOB0,4) +#define DRV_PB36V_OFF GPIO_Write_Low(GPIOB0,4) + +#define DRV_PS36V_ON GPIO_Write_High(GPIOA0,14) +#define DRV_PS36V_OFF GPIO_Write_Low(GPIOA0,14) + +//过流保护中断引脚 +#define PB_OVERCURR_PWR_BUS GPIO_Read_Status(GPIOB0,1) + +//PowerBus 保护电流 +#define PB_SaveCurrent_Min 1 +#define PB_SaveCurrent_Max 165 + +/*PB通讯 RS485协议相关内容 - 开始*/ +/*PB通讯 RS485协议 - 格式*/ +typedef enum{ + PB_FMT_ADDR_TX = 0, + PB_FMT_TYPE, + PB_FMT_DEV_TYPE, + PB_FMT_ADDR_RX, + PB_FMT_LEN, + PB_FMT_CKS, + PB_FMT_CMD, + PB_FMT_PARA, +}PB_FMT_E; + +#define PB_DEV_Addr 0x01 //PB设备地址默认0x01 主机地址默认为0x00 +//#define PB_DEV_StripAddr 0x01 //PB灯带地址默认0x01 +#define PB_DEV_TYPE 0x30 //PB设备类型 +#define PB_BUFFER_SIZE 100 //PB缓冲区数据大小 +#define PB_BUFFER_NUM 8 //PB缓冲区数据个数 +#define PB_INTP_BUFFER_SIZE 200 //PB中断发送 缓冲区数据大小 + +/*PB20 通讯协议命令*/ +#define PB_CMD_GET_STATE 0x20 //查询当前状态 +#define PB_CMD_SET_STRIP_BRIGHTNESS 0x21 //设定灯带亮度 +#define PB_CMD_SET_STRIP_SWITCH 0x22 //设定灯带开关状态 +#define PB_CMD_SET_STRIP_ADJUST 0x23 //设定灯带亮度递增、递减 +#define PB_CMD_SET_PIRTIGGLE_LED 0x24 //设定LD PIR触发LED +#define PB_CMD_SET_CurrTiggleStrip 0x25 //PB总线电流触发灯带调光 +#define PB_CMD_SET_SaveCurrInfo 0x26 //设定PB总线保护电流 +#define PB_CMD_GET_SaveCurrInfo 0x27 //获取PB总线保护电流信息 +#define PB_CMD_SET_UniversPara 0x28 //设定整体参数 +#define PB_CMD_SET_PowerBus_Enable 0x29 //设定PB 总线输出使能 +#define PB_CMD_PassThroug_Data 0x2A //PB透传命令 + +#define PB_CMD_SET_PB_LEDS_BRIGHTNESS 0x30 //设定PB总线 LED亮度 --按照地址段控制 每个回路可单独设定亮度 +#define PB_CMD_SET_PB_LEDS_ADJUST 0x31 //设定PB总线 LED亮度递增递减调节 --按照地址段控制 +#define PB_CMD_SET_PB_LEDS_SWITCH 0x32 //设定PB总线 LED开关状态 --按照地址段控制 +#define PB_CMD_SET_PB_LEDS_BRIGHT 0x33 //设定PB总线 LED亮度 --按照地址段控制 +#define PB_CMD_SET_PB_LED_SWITCH 0x34 //设定PB总线 LED单开关状态 --按照单独回路控制 +#define PB_CMD_SET_PB_LED_BRIGHTNESS 0x35 //设定PB总线 LED单回路亮度 --按照单独回路控制 +#define PB_CMD_SET_PB_LED_Adjust 0x36 //设定PB总线 LED单回路亮度调节 --按照单独回路控制 +#define PB_CMD_SET_PB_ALLLED_Switch 0x37 //设定PB总线 LED全部设备开关状态 + +#define PB_CMD_SET_PB_STRIPS_BRIGHTNESS 0x40 //设定PB总线 Strip亮度 --按照地址段控制 每个回路可单独设定亮度 +#define PB_CMD_SET_PB_STRIPS_ADJUST 0x41 //设定PB总线 Strip亮度递增递减调节 --按照地址段控制 +#define PB_CMD_SET_PB_STRIPS_SWITCH 0x42 //设定PB总线 Strip开关状态 --按照地址段控制 +#define PB_CMD_SET_PB_ALLSTRIP_Switch 0x43 //设定PB总线 Strip全部设备开关状态 +#define PB_CMD_SET_PB_STRIP_SWITCH 0x44 //设定PB总线 Strip单开关状态 --按照单独回路控制 +#define PB_CMD_SET_PB_STRIP_BRIGHTNESS 0x45 //设定PB总线 Strip单回路亮度 --按照单独回路控制 +#define PB_CMD_SET_PB_STRIP_Adjust 0x46 //设定PB总线 Strip单回路亮度 --按照单独回路控制 +#define PB_CMD_SET_PB_STRIP_RELATIVE_GROUP_ADJUST 0x47 //设定PB总线 Strip相对调节 --按照32回路/组 +#define PB_CMD_SET_PB_STRIP_RELATIVE_ADJUST 0x48 //设定PB总线 Strip相对调节 --指定回路 + + +#define PB_CMD_SET_PB_RELAYS_SWITCH 0x50 //设定PB总线 继电器开关状态 --按照地址段控制 +#define PB_CMD_SET_PB_ALLRELAY_SWITCH 0x51 //设定PB总线 全部继电器开关状态 --按照地址段控制 +#define PB_CMD_SET_PB_RELAY_SWITCH 0x52 //设定PB总线 继电器开关状态 +#define PB_CMD_SET_PB_RELAY_DELAY_SWITCH 0x53 //设定PB总线 继电器延时开关状态 + +#define PB_CMD_Reply_Succ 0x00 //PowerBus总线通讯空闲 +#define PB_CMD_Reply_CommStateBusy 0x01 //PowerBus总线通讯繁忙 +#define PB_CMD_Reply_ParaError 0x02 //参数错误 + +/*PB通讯 RS485协议相关内容 - 结束*/ + +/*PB 总线通讯协议 相关内容 - 开始*/ + +#define POWERBUS_SEND_DELAY 50 //PowerBus 发送延时 50ms + +typedef enum +{ + PowerBUS_FMT_LEN, + PowerBUS_FMT_SN, + PowerBUS_FMT_CKS, + PowerBUS_FMT_CMD, + PowerBUS_FMT_PARAM, +}PowerBUS_FMT_e; + + +#define PowerBUS_CMD_SET_LED_BRIGHTNESS 0x01 //设置亮度 +#define PowerBUS_CMD_SET_LED_SWITCH 0x02 //设置开关状态 +#define PowerBUS_CMD_SET_LED_ADJUST 0x03 //设定调光 +#define PowerBUS_CMD_SET_LEDS_BRIGHTNESS 0x04 +#define PowerBUS_CMD_SET_LEDS_SWITCH 0x05 +#define PowerBUS_CMD_SET_LEDS_ADJUST 0x06 +#define PowerBUS_CMD_SET_LEDS_BRIGHT 0x07 +#define PowerBUS_CMD_SET_ALLLED_SWITCH 0x08 +#define PowerBUS_CMD_SET_PIR_ENABLE 0x09 //设定PIR使能 + +#define PowerBUS_CMD_SET_STRIP_BRIGHTNESS 0x11 //设置亮度 --指定回路 +#define PowerBUS_CMD_SET_STRIP_SWITCH 0x12 //设置开关状态 --指定回路 +#define PowerBUS_CMD_SET_STRIP_ADJUST 0x13 //设定调光 --指定回路 +#define PowerBUS_CMD_SET_STRIPS_BRIGHTNESS 0x14 //设定亮度 按照组地址控制 +#define PowerBUS_CMD_SET_STRIPS_SWITCH 0x15 //设定开关状态 按照组地址控制 +#define PowerBUS_CMD_SET_STRIPS_ADJUST 0x16 //设定调光 按照组地址控制 +#define PowerBUS_CMD_SET_ALLSTRIP_SWITCH 0x17 //设置LED开关状态 --全部开关状态可单独设置 +#define PowerBUS_CMD_SET_STRIP_RELATIVE_GROUP_ADJUST 0x18 //设置灯带相对调节 --按照32回路/组 +#define PowerBUS_CMD_SET_STRIP_RELATIVE_ADJUST 0x19 //设置灯带相对调节 --指定回路 + + +#define PowerBUS_CMD_SET_RELAYS_SWITCH 0x21 //设定继电器开关状态 - 组地址控制 +#define PowerBUS_CMD_SET_ALLRELAY_SWITCH 0x22 //设定继电器全部开关状态 +#define PowerBUS_CMD_SET_RELAY_SWITCH 0x23 //设定继电器开关状态 +#define PowerBUS_CMD_SET_RELAY_DELAY_SWITCH 0x24 //设定继电器延时开关控制 + +#define PowerBUS_CMD_SET_UniversPara 0xF0 //设定整体参数信息 - 调光上下限设定，全局亮度设定 + +/*PB 总线通讯协议 相关内容 - 结束*/ + +#define PB_GROUP_NUM 32 +#define MEAS_BUFFER_SIZE 20 +#define MEAS_Debounce_Num 5 + +#define MEAS_InputVoltage_Min 10000 //输入电压最低为10V,单位：mV +#define MEAS_InputVoltage_Max 38000 //输入电压最高为38V,单位：mV + +typedef struct{ + //输入电源检测与输出电源开关 相关定义 + U8_T meas_cnt; //检测BUFF 当前下标 + U8_T meas_fill_flag; //检测BUFF 已满标志位 + U8_T meas_hv_PB_ONcnt; // + U8_T meas_hv_PS_ONcnt; // + U8_T meas_hv_PB_OFFcnt; // + U8_T meas_hv_PS_OFFcnt; // + U8_T meas_hv_PB_State; + U8_T meas_hv_PS_State; + U8_T last_meas_hv_PB_State; + U8_T last_meas_hv_PS_State; + U8_T meas_hv_curr_ward; //PB负载电流检测 挡位 0x00:低挡位，0x01:高挡位 + U8_T meas_hv_curr_toggle; + U8_T meas_hv_curr_cnt; + U8_T meas_hv_curr_filter; + + U8_T meas_load_current_ONcnt; //PB负载电流 触发灯带计数 + U8_T meas_load_current_OFFcnt; //PB负载电流 触发灯带计数 + U8_T meas_load_current_state; //PB负载电流 触发状态 + + //PB 状态变量相关定义 + U8_T power_status; //PB 开关状态 + U8_T enable; //PB 使能状态 + U8_T soft_boot; //PB 软启动 + U8_T protect_flag; //PB 电源保护标志位 + U8_T protect_curr; //PB 保护电流值 + + U8_T recv_addr; //接收数据地址 + U8_T recv_sn; //接收SN号 + U8_T recv_cmd; //接收命令 + U8_T ackbuff[PB_BUFFER_SIZE]; //应答数据 + + U8_T sendSN; + U8_T sendCnt; + U8_T sendReadCnt; + U8_T sendWriteCnt; + U8_T sendbufferlen[PB_BUFFER_NUM]; + U8_T sendbuffer[PB_BUFFER_NUM][PB_BUFFER_SIZE]; + +// U8_T brightnessCurr[PB_GROUP_NUM][8]; +// U8_T switchState[PB_GROUP_NUM]; + + U8_T resendNum; //下发PB数据 - 重发次数 + + U16_T ackLen; //应答数据长度 + U16_T soft_boot_cnt; //软启动占空比 + U16_T soft_boot_high; //软启动 - 高电平时间 + U16_T soft_boot_low; //软启动 - 低电平时间 + U16_T meas_powerbus_volt; //PB电压 + U16_T meas_powerstrip_volt; //PS电压 + U16_T meas_powerbus_curr; //PB电流 + + U16_T meas_hv_PB_val[MEAS_BUFFER_SIZE]; + U16_T meas_hv_PS_val[MEAS_BUFFER_SIZE]; + U16_T meas_hv_CURRPWRx5_val; + U16_T meas_hv_CURRPWRx50_val; + U16_T meas_hv_CURRPWR_Buff[MEAS_Debounce_Num]; + //U16_T meas_hv_CURRPWR_FilterBuff[5]; + + U32_T protect_time; //PB 保护电流过载时间 + U32_T soft_boot_tick; //软启动 时间戳 + U32_T protect_tick; //电流过载 时间戳 + U32_T send_tick; //发送时间戳 +}PB_INFO_T; + +/*PB 检测电流变化相关变量*/ + +#define Filter_Coarse_Size 5 +#define Filter_Fine_Size 50 + +typedef struct{ + U8_T pb_state; //状态 0x00:未触发；0x01:触发；0x02:释放 + U8_T last_pb_state; + U8_T dead_switch; //功能失效开关 - RCU下发控制时，在一定时间内会失效 + + U8_T fun_enable; //功能使能状态 + U8_T strip_relation; //灯带关联 + + U8_T triggle_strip_bright[PWM_OUT_CH_MAX]; //触发后灯带亮度 + U8_T release_strip_bright[PWM_OUT_CH_MAX]; //释放后灯带亮度 + + U8_T trigger_debounce_cnt; //触发消抖计数 + U8_T release_debounce_cnt; //释放消抖计数 + U8_T trigger_debounce_num; //触发消抖次数 + U8_T release_debounce_num; //释放消抖次数 + + U16_T strip_gradient_time; //灯带渐变时间,单位：ms + + U16_T trigger_threshold; //触发阈值 - 单位：mW + U16_T release_threshold; //释放阈值 - 单位：mW + + U16_T coarse_filter_buff[Filter_Coarse_Size+1]; + U16_T fine_filter_buff[Filter_Fine_Size+1]; + + U32_T dead_time; //失效时间 + U32_T dead_tick; //失效时间戳 + + int curr_diff_val; //电流差值 + +}PB_DETECTION_FILTER_INFO; + + + +extern PB_INFO_T g_PB; + +void PB_Init(void); +void PB_Set_SaveCurrent(U8_T val); +U8_T PB_CheckSum(U8_T *buff,U16_T len); +void PB_Send_String_INT(void); +void PB_OVERCURR_PWR_BUS_INT_Processing(void); +void PB_Scan_State_Task(void); +U16_T Get_PB_CURR_VAL(void); +U8_T BLV_PB_Control_Protocol_Processing(U8_T *data,U16_T len); +void PowerBus_FillSendBuff(U8_T resendNum,U8_T *data,U8_T len); +U8_T PowerBUS_GetCommState(void); + +void PB_Current_Monitoring_Meas(void); +void Set_PB_CurrMonitoring_Dead(void); + +void PB_Task(void); + +#endif diff --git a/Source/SYSTEM/inc/pwm.h b/Source/SYSTEM/inc/pwm.h new file mode 100644 index 0000000..6a16a51 --- /dev/null +++ b/Source/SYSTEM/inc/pwm.h @@ -0,0 +1,79 @@ +#ifndef _PWM_H_ +#define _PWM_H_ + +#include "apt32f102.h" +#include "apt32f102_ept.h" + +#define PWM_OUT_VAL_MAX 3000 +#define PWM_OUT_VAL_MIN 0 +#define BRIGHTNESS_MAX 100 +#define BRIGHTNESS_MIN 0 + +#define BRIGHTNESS_UP_LIMIT 100 +#define BRIGHTNESS_DOWN_LIMIT 0 + +typedef enum +{ + PWM_OUT_CH1 = 0x00, + PWM_OUT_CH2, + PWM_OUT_CH3, + PWM_OUT_CH4, + PWM_OUT_CH_MAX, +}PWM_CHN_e; + +typedef enum{ + PWMA_Decreasing = 0, //PWM调节方向 - 递减 + PWMA_Ascending, //PWM调节方向 - 递增 + PWMA_Nochange, //PWM调节方向 - 不调节 +}PWM_ADJUST_ORIENTATION; + +typedef struct{ + U8_T irqEnable; //PWM控制中断使能状态 + U8_T allBrightness; //全局调光 + U8_T allBrightnessUpLimit; //全局调光上限百分比 + U8_T allBrightnessDownLimit; //全局调光下限百分比 + + U8_T brightnessCurr[PWM_OUT_CH_MAX]; //当前PWM 百分比亮度 + U8_T switchState[PWM_OUT_CH_MAX]; + U8_T controlFlag[PWM_OUT_CH_MAX]; + U8_T addOrDecFlag[PWM_OUT_CH_MAX]; + + U16_T allPwmUpLimit; //全局可调上限 + U16_T allPwmDownLimit; //全局可调下限 + U16_T pwmValCurr[PWM_OUT_CH_MAX]; //当前PWM + U16_T pwmValTarget[PWM_OUT_CH_MAX]; //目标PWM + U16_T gradualTime[PWM_OUT_CH_MAX]; //调节时间 , 单位：ms + + float pwmStep[PWM_OUT_CH_MAX]; //步进值 + float pwmFloatValCurr[PWM_OUT_CH_MAX]; //当前PWM - 浮点类型 + +}PWM_CONTROL_T; + +typedef struct{ + U8_T enable[PWM_OUT_CH_MAX]; //自动调节使能状态 0x01:使能，0x00:未使能 + U8_T adjMode[PWM_OUT_CH_MAX]; //0x00:调节到顶端停止 0x01:循环调节 0x02:停止调节 + U8_T adjDir[PWM_OUT_CH_MAX]; //0x00:递减 0x01:递增 0x02:与上次命令相反 + float pwmStep[PWM_OUT_CH_MAX]; //PWM步进值 + U32_T pwmStepTime[PWM_OUT_CH_MAX]; //步进时间 ， 单位：ms + U32_T pwmStepTick[PWM_OUT_CH_MAX]; //步进时间戳 ， 单位：ms +}PWM_AUTO_ADJUST_T; + +extern PWM_CONTROL_T g_pwm; +extern PWM_AUTO_ADJUST_T g_pwmAutoAdj; + +void PWM_Init(void); + +void PWM_SetUpLimitVal(U8_T val); +void PWM_SetDownLimitVal(U8_T val); +void Pwm_SetAllBrightness(U8_T val); + +void PWM_SetOutDuty(U8_T index,U16_T val); +void PWM_SetCHGradualTime(U8_T index, U16_T val); +void Pwm_SetOnOffState(U8_T index, U8_T state); +void PWM_SetOutBrightness(U8_T index, U8_T brightness); +void PWM_SetAutoAdjust(U8_T index,U8_T mode,U8_T adj,U16_T adj_time); +void PWM_Timer_Enable(void); +void PWM_Timer_Disable(void); +void PWM_Timer_1ms_Task(void); + +#endif diff --git a/Source/SYSTEM/inc/uart.h b/Source/SYSTEM/inc/uart.h new file mode 100644 index 0000000..c3e2c29 --- /dev/null +++ b/Source/SYSTEM/inc/uart.h @@ -0,0 +1,75 @@ +#ifndef _UART_H_ +#define _UART_H_ + +#include "apt32f102.h" +#include "apt32f102_uart.h" + +#define Recv_2400_TimeOut 20 //ms +#define Recv_9600_TimeOut 10 //ms +#define Recv_115200_TimeOut 3 //ms + +#define USART_BUFFER_NUM 3 +#define USART_BUFFER_SIZE 100 + +#define UART_SEND_BUFFER_NUM 10 +#define UART_SEND_BUFFER_SIZE 20 + +/*调试信息相关定义*/ +#ifndef DBG_LOG_EN +#define DBG_LOG_EN 0 //DEBUG LOG 输出总开关 +#endif + +/*调试信息初始状态*/ +#define DBG_OPT_Debug_STATUS 0 //临时调试信息打印开关 +#define DBG_OPT_DEVICE_STATUS 0 //设备驱动层打印调试信息打印开关 +#define DBG_OPT_SYS_STATUS 0 //系统调试信息打印开关 + +/*调试信息输出控制位*/ +#define DBG_BIT_Debug_STATUS 2 +#define DBG_BIT_DEVICE_STATUS 1 +#define DBG_BIT_SYS_STATUS 0 + +#if DBG_LOG_EN +#define DBG_Printf(data,len) UARTTransmit(UART1,data,len) +#else +#define DBG_Printf +#endif + +typedef U8_T (*Uart_prt)(U8_T *,U16_T); + +typedef enum +{ + UART_0, + UART_1, + UART_2, + UART_3, + UART_MAX, +}UART_IDX; + +typedef struct{ + U8_T RecvBuffer[USART_BUFFER_SIZE]; + U8_T DealBuff[USART_BUFFER_SIZE]; + U8_T Receiving; + + U16_T RecvLen; + U16_T DealLen; + + U32_T RecvTimeout; + U32_T RecvIdleTiming; + + Uart_prt processing_cf; //处理函数指针 +}UART_t; + +extern U32_T Dbg_Switch; + +void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf); +void UART1_RecvINT_Processing(char data); +void UART1_TASK(void); + +void Dbg_NoTick_Println(int DbgOptBit, const char *cmd, ...); +void Dbg_Print(int DbgOptBit, const char *cmd, ...); +void Dbg_Println(int DbgOptBit, const char *cmd, ...); +void Dbg_Print_Buff(int DbgOptBit, const char *cmd, U8_T *buff,U16_T len); + + +#endif diff --git a/Source/SYSTEM/pb_fun.c b/Source/SYSTEM/pb_fun.c new file mode 100644 index 0000000..3d32095 --- /dev/null +++ b/Source/SYSTEM/pb_fun.c @@ -0,0 +1,2196 @@ +#include "includes.h" +#include +#include + +#define PowerBus_SendData(data,len) UARTTransmit(UART0,data,len) //PowerBus总线控制 数据发送 +#define RCU_PB_SendData(data,len) UARTTransmit(UART1,data,len) //RCU与PB通讯 数据发送 + +PB_INFO_T g_PB; +PB_DETECTION_FILTER_INFO curr_monitoring; //电流监视 + +void PB_Init(void){ + + memset(&g_PB,0,sizeof(PB_INFO_T)); + memset(&curr_monitoring,0,sizeof(PB_DETECTION_FILTER_INFO)); + + + //PB 功能 + g_PB.enable = g_eeprom.powerbus_enable; + g_PB.protect_curr = g_eeprom.save_curr; + g_PB.protect_time = 5000; //5S + + PB_Set_SaveCurrent(g_PB.protect_curr); //设置保护电流 +} + +/********************************************************************* + * @fn PB_Set_SaveCurrent + * @brief PB - 设置PB 保护电流 + * @para val:1~165 + */ +void PB_Set_SaveCurrent(U8_T val){ + + U32_T curr_val = 0; + + if( (val < PB_SaveCurrent_Min) || (val > PB_SaveCurrent_Max) ) return ; + + curr_val = val*4095/PB_SaveCurrent_Max; + + BT_Period_CMP_Write(BT0,4095,curr_val); +} + +/********************************************************************* + * @fn PB_Set_Power_State + * @brief PB - 设置PB电源状态 + */ +void PB_Set_Power_State(U8_T state){ + switch(state){ + case TRUE: + g_PB.enable = TRUE; + break; + case FALSE: + g_PB.enable = FALSE; + g_PB.power_status = FALSE; + DRV_PB_DISABLE; + break; + } +} + +/********************************************************************* + * @fn PB_Soft_Boot_Task + * @brief PB - 软启动任务 + */ +void PB_Soft_Boot_Task(void){ + + if(g_PB.meas_hv_PB_State != 0x01) return; //PB输出电源未打开 + + if(g_PB.enable != TRUE) return ; + + switch(g_PB.soft_boot){ + case 0x00: //开启启动 + g_PB.soft_boot_high = 0x01; + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + g_PB.soft_boot_tick = SysTick_100us; + g_PB.soft_boot_cnt = 0; + DRV_PB_DISABLE; + g_PB.soft_boot = 0x01; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Soft_Boot_Task Start"); + break; + case 0x01: //软启动中 - 低电平输出时间 + if(SysTick_100us - g_PB.soft_boot_tick >= g_PB.soft_boot_low){ + g_PB.soft_boot_tick = SysTick_100us; + + DRV_PB_ENABLE; + g_PB.soft_boot = 0x02; + //Dbg_Println(DBG_BIT_SYS_STATUS, "PWM DutyLow %d",g_PB.soft_boot_low); + } + break; + case 0x02: //软启动中 - 高电平输出时间 + if(SysTick_100us - g_PB.soft_boot_tick >= g_PB.soft_boot_high){ + g_PB.soft_boot_tick = SysTick_100us; + + g_PB.soft_boot_cnt++; + + if(g_PB.soft_boot_cnt >= 3){ + g_PB.soft_boot_cnt = 0; + + g_PB.soft_boot_high++; + g_PB.soft_boot_low = PB_SOFTBOOT_PERIOD - g_PB.soft_boot_high; + } + + if(g_PB.soft_boot_high >= PB_SOFTBOOT_PERIOD){ + DRV_PB_ENABLE; + g_PB.enable = FALSE; + g_PB.power_status = TRUE; + g_PB.soft_boot = 0x00; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Soft_Boot_Task End"); + + }else { + DRV_PB_DISABLE; + g_PB.soft_boot = 0x01; + } + + //Dbg_Println(DBG_BIT_SYS_STATUS, "PWM DutyHigh %d",g_PB.soft_boot_high); + } + break; + } +} + +/*PB 编码对照表*/ +const U8_T PowerBus_Code_Comparative[16] = {0xEF,0xEE,0xED,0xB7,0xEB,0x77,0xD7,0x7D,0xE7,0xBB,0x7B,0xDB,0xBD,0xDD,0xDE,0xFF}; +/********************************************************************* + * @fn PB_Data_Send + * @brief PB - 数据发送函数 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PowerBus_Data_Encoding(U8_T *CodeData,U8_T *Sourdata,U16_T SourLen){ + U8_T temp_num = 0; + U8_T i=0; + + for(i=0;i> 4) & 0x0F; + CodeData[i*2] = PowerBus_Code_Comparative[temp_num]; + + temp_num = (Sourdata[i]) & 0x0F; + CodeData[i*2 + 1] = PowerBus_Code_Comparative[temp_num]; + } + + //Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Encoding Buff:", CodeData, SourLen*2); + + return 0x00; +} + +U8_T Uart_Intp_Send_Buff[PB_INTP_BUFFER_SIZE]; //中断发送buff +volatile U8_T UTS_send_Complete = 0; +volatile U8_T UTS_send_Length_temp = 0; +volatile U8_T UTS_send_Length = 0; + +//中断发送 - 串口中断调用 +void PB_Send_String_INT(void){ + if(UTS_send_Complete != 0x00){ + if(UTS_send_Length_temp >= UTS_send_Length){ + UTS_send_Complete = 0; + UTS_send_Length_temp = 0; + }else{ + if(UTS_send_Length_temp >= PB_INTP_BUFFER_SIZE){ + UTS_send_Complete = 0; + UTS_send_Length_temp = 0; + }else{ + //UARTTxByte(UART0,Uart_Intp_Send_Buff[UTS_send_Length_temp++]); + CSP_UART_SET_DATA(UART0,Uart_Intp_Send_Buff[UTS_send_Length_temp++]); + + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + } + } + } +} + +/********************************************************************* + * @fn PowerBus_Data_Send + * @brief PowerBus - 总线数据发送函数 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PowerBus_Data_Send(U8_T *data,U16_T len){ + U8_T send_buff[500]; + memset(send_buff,0,sizeof(send_buff)); + U16_T send_len = len; + + if(send_len >= PB_BUFFER_SIZE) send_len = PB_BUFFER_SIZE; + + //if(g_PB.power_status == 0x01) + { +// Dbg_Println(DBG_BIT_SYS_STATUS, "PB_Data_Send %d",len); +// Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "PB_Data_Send Buff:", data, len); + + /*PowerBus - 总线通讯采用新编码格式*/ +// PowerBus_Data_Encoding(send_buff,data,len); +// PowerBus_SendData(send_buff,len*2); + + /*PowerBus - 总线通讯 中断发送*/ + if(UTS_send_Complete == 0x00){ + memset((void *)Uart_Intp_Send_Buff,0,sizeof(PB_INTP_BUFFER_SIZE)); + PowerBus_Data_Encoding(Uart_Intp_Send_Buff,data,send_len); + UTS_send_Complete = 0x01; + UTS_send_Length = send_len*2; + UTS_send_Length_temp = 0x01; + UARTTxByte(UART0,Uart_Intp_Send_Buff[0]); + g_PB.send_tick = SysTick_1ms; //更新发送时间戳 + }else{ + //上次发送还未结束 + + return 0xFF; + } + + return 0x00; + } + + return 0x01; +} + +/********************************************************************* + * @fn PB_CheckSum + * @brief PB - 数据和校验取反 + * @return 0x00:发送没问题，0x01:发送失败 + */ +U8_T PB_CheckSum(U8_T *buff,U16_T len){ + U8_T sum = 0; + + for(U16_T i=0;i= g_PB.protect_time){ + g_PB.protect_flag = FALSE; + + PB_Set_Power_State(TRUE); + + //Dbg_Println(DBG_BIT_SYS_STATUS, "重新开启PB电源"); + } + } + } +} + +/********************************************************************* + * @fn PB_Scan_State_Task + * @brief PB - 扫描状态 - 1ms一次，确保状态可以及时更新 + */ +void PB_Scan_State_Task(void){ + + /*检测OverCurr引脚状态，High:过流保护中，Low:正常工作中*/ + if(PB_OVERCURR_PWR_BUS == 0x01){ + PB_Set_Power_State(FALSE); + g_PB.protect_flag = TRUE; + g_PB.protect_tick = SysTick_1ms; + + //Dbg_Println(DBG_BIT_SYS_STATUS, "检测到 OverCurr High状态"); + } +} + +/********************************************************************* + * @fn PowerBus_FillSendBuff + * @brief PowerBus - 写入发送缓冲区中 + * @return NULL + */ +void PowerBus_FillSendBuff(U8_T resendNum,U8_T *data,U8_T len){ + if(len >= PB_BUFFER_SIZE) len = PB_BUFFER_SIZE; + + g_PB.resendNum = resendNum; + g_PB.sendbufferlen[g_PB.sendWriteCnt] = len; + memcpy(g_PB.sendbuffer[g_PB.sendWriteCnt], data, len); + + g_PB.sendWriteCnt++; + if(g_PB.sendWriteCnt >= PB_BUFFER_NUM){ + g_PB.sendWriteCnt = 0; + } +} + +/********************************************************************* + * @fn PowerBus_PackFillBuff + * @brief PowerBus - 数据打包并写入发生缓冲区中 + * @return NULL + */ +void PowerBus_PackFillBuff(U8_T resendNum,U8_T cmd,U8_T *data,U8_T len){ + + g_PB.sendSN++; + if(g_PB.sendSN >= 0xFA) g_PB.sendSN = 0x01; //SN号范围 1~250 + + g_PB.resendNum = resendNum; + + if((len + PowerBUS_FMT_PARAM) >= PB_BUFFER_SIZE) len = PB_BUFFER_SIZE - PowerBUS_FMT_PARAM; //参数加上包头长度大于上限 + + g_PB.sendbufferlen[g_PB.sendWriteCnt] = len + PowerBUS_FMT_PARAM; + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN] = g_PB.sendbufferlen[g_PB.sendWriteCnt]; + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_SN] = g_PB.sendSN; + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = 0x00; + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CMD] = cmd; + + memcpy(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_PARAM], data, len); + + g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_CKS] = PB_CheckSum(&g_PB.sendbuffer[g_PB.sendWriteCnt][PowerBUS_FMT_LEN], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + +// Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Data Buff:", data, len); +// Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Send Buff:", g_PB.sendbuffer[g_PB.sendWriteCnt], g_PB.sendbufferlen[g_PB.sendWriteCnt]); + + g_PB.sendWriteCnt++; + if(g_PB.sendWriteCnt >= PB_BUFFER_NUM){ + g_PB.sendWriteCnt = 0; + } + +} + +/********************************************************************* + * @fn PowerBus_SendBuffer_Task + * @brief BLV PowerBus通讯协议发送任务 + * @return none + */ +void PowerBus_SendBuffer_Task(void){ + U8_T send_rev = 0; + if(g_PB.sendWriteCnt != g_PB.sendReadCnt){ + if(SysTick_1ms - g_PB.send_tick >= POWERBUS_SEND_DELAY){ + + if(g_PB.sendCnt < g_PB.resendNum){ + //Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "PowerBus_Data_Send",g_PB.sendbuffer[g_PB.sendReadCnt],g_PB.sendbufferlen[g_PB.sendReadCnt]); + + send_rev = PowerBus_Data_Send(g_PB.sendbuffer[g_PB.sendReadCnt], g_PB.sendbufferlen[g_PB.sendReadCnt]); + if(send_rev != 0xFF){ + Set_PB_CurrMonitoring_Dead(); + g_PB.sendCnt++; + } + + }else { + g_PB.sendCnt = 0; + + g_PB.sendReadCnt++; + if(g_PB.sendReadCnt >= PB_BUFFER_NUM){ + g_PB.sendReadCnt = 0; + } + + return ; //直接退出不更新时间 + } + + //g_PB.send_tick = SysTick_1ms; + } + } +} + +/********************************************************************* + * @fn PowerBUS_GetCommState + * @brief BLV PowerBus 获取当前PowerBUS总线发送状态 + * @return none + */ +U8_T PowerBUS_GetCommState(void){ + + if(g_PB.sendWriteCnt != g_PB.sendReadCnt){ + return 0x01; + } + + return 0x00; +} + +/********************************************************************* + * @fn PB_FilACkPacket + * @brief BLV PB控制协议 - 数据打包函数 + * @return none + */ +void PB_FilACkPacket(U8_T *ackBuff,U8_T ackLen){ + ackBuff[PB_FMT_ADDR_TX] = PB_DEV_Addr; + ackBuff[PB_FMT_TYPE] = (g_PB.recv_sn & 0x0F); + ackBuff[PB_FMT_DEV_TYPE] = PB_DEV_TYPE; + ackBuff[PB_FMT_ADDR_RX] = g_PB.recv_addr; + ackBuff[PB_FMT_LEN] = ackLen; + ackBuff[PB_FMT_CKS] = 0x00; + ackBuff[PB_FMT_CMD] = g_PB.recv_cmd; + + ackBuff[PB_FMT_CKS] = PB_CheckSum(ackBuff, ackLen); +} + +/********************************************************************* + * @fn PB_RS485_ReplyAck + * @brief BLV PB控制协议 - 应答回复 + * @return none + */ +void PB_RS485_ReplyAck(void){ + g_PB.ackLen += PB_FMT_PARA; + + PB_FilACkPacket(g_PB.ackbuff,g_PB.ackLen); + RCU_PB_SendData(g_PB.ackbuff,g_PB.ackLen); + + g_PB.ackLen = 0; +} + +/********************************************************************* + * @fn PB_Set_CH_SaveBrightnessInfo + * @brief PB - 设置灯带回路保存灯光参数 + * @return 0x00:处理成功，其他值：处理失败 + */ +U8_T PB_Set_CH_SaveBrightnessInfo(U8_T loop,U8_T brightness,U16_T gradualtime){ + + switch(loop){ + case PWM_OUT_CH1: + g_eeprom.brightness[PWM_OUT_CH1] = brightness; + g_eeprom.gradialTime[PWM_OUT_CH1] = gradualtime; + break; + case PWM_OUT_CH2: + g_eeprom.brightness[PWM_OUT_CH2] = brightness; + g_eeprom.gradialTime[PWM_OUT_CH2] = gradualtime; + break; + case PWM_OUT_CH3: + g_eeprom.brightness[PWM_OUT_CH3] = brightness; + g_eeprom.gradialTime[PWM_OUT_CH3] = gradualtime; + break; + case PWM_OUT_CH4: + g_eeprom.brightness[PWM_OUT_CH4] = brightness; + g_eeprom.gradialTime[PWM_OUT_CH4] = gradualtime; + break; + default: + return 0x01; + break; + } + + return 0x00; +} + +/********************************************************************* + * @fn PB_Set_CH_SaveSwitchInfo + * @brief PB - 设置灯带回路保存开关状态参数 + * @return 0x00:处理成功，其他值：处理失败 + */ +U8_T PB_Set_CH_SaveSwitchInfo(U8_T loop,U8_T switch_state){ + + switch(loop){ + case PWM_OUT_CH1: + g_eeprom.swithcState[PWM_OUT_CH1] = switch_state; + break; + case PWM_OUT_CH2: + g_eeprom.swithcState[PWM_OUT_CH2] = switch_state; + break; + case PWM_OUT_CH3: + g_eeprom.swithcState[PWM_OUT_CH3] = switch_state; + break; + case PWM_OUT_CH4: + g_eeprom.swithcState[PWM_OUT_CH4] = switch_state; + break; + default: + return 0x01; + break; + } + + return 0x00; +} + +/********************************************************************* + * @fn PB_ACK_GET_STATE + * @brief BLV PB控制协议 - 查询当前状态 因为目前无法获取PB状态，只能回复0x00 + * @return none + */ +void PB_ACK_GET_STATE(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T i=0; + + U16_T temp_val = Get_PB_CURR_VAL(); + U32_T temp_power = 0; + + //g_PB.recv_cmd = para[PB_FMT_CMD]; + + ackPara[i++] = g_pwm.allBrightness; //全局亮度 + ackPara[i++] = g_pwm.allBrightnessUpLimit; //全局亮度可调上限 + ackPara[i++] = g_pwm.allBrightnessDownLimit; //全局亮度可调下限 + + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH1]; //灯亮度 - CH4 + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH2]; //灯亮度 - CH3 + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH3]; //灯亮度 - CH2 + ackPara[i++] = g_pwm.brightnessCurr[PWM_OUT_CH4]; //灯亮度 - CH1 + ackPara[i++] = (g_PB.meas_powerstrip_volt >> 8) & 0xFF; //当前灯带电压 H + ackPara[i++] = (g_PB.meas_powerstrip_volt) & 0xFF;; //当前灯带电压 L + ackPara[i++] = 0x00; //当前灯带CH1 电流 H + ackPara[i++] = 0x00; //当前灯带CH1 电流 L + ackPara[i++] = 0x00; //当前灯带CH2 电流 H + ackPara[i++] = 0x00; //当前灯带CH2 电流 L + ackPara[i++] = 0x00; //当前灯带CH3 电流 H + ackPara[i++] = 0x00; //当前灯带CH3 电流 L + ackPara[i++] = 0x00; //当前灯带CH4 电流 H + ackPara[i++] = 0x00; //当前灯带CH4 电流 L + ackPara[i++] = 0x00; //g_PB.switchState[group]; //Bit7~Bit4:灯带开关状态MASK ,Bit3~Bit0:灯带故障状态 + ackPara[i++] = (g_PB.meas_powerbus_volt >> 8) & 0xFF; //当前PB BUS电压 H + ackPara[i++] = (g_PB.meas_powerbus_volt) & 0xFF; //当前PB BUS电压 L + ackPara[i++] = (temp_val >> 8) & 0xFF; //当前PB BUS电流 H + ackPara[i++] = (temp_val) & 0xFF; //当前PB BUS电流 L + temp_power = temp_val * g_PB.meas_powerbus_volt / 1000; + ackPara[i++] = (temp_power >> 24) & 0xFF; //当前PB BUS功率 H + ackPara[i++] = (temp_power >> 16) & 0xFF; //当前PB BUS功率 L + ackPara[i++] = (temp_power >> 8) & 0xFF; //当前PB BUS功率 H + ackPara[i++] = temp_power & 0xFF; //当前PB BUS功率 L + ackPara[i++] = g_PB.protect_flag; //PB BUS故障状态MASK + + ackPara[i++] = g_PB.enable; //PB 输出使能状态 + + ackPara[i++] = Project_Software_Ver; //PB 软件版本 + ackPara[i++] = Project_Hardware_Ver; //PB 硬件版本 + ackPara[i++] = PowerBUS_GetCommState(); //PowerBus 当前通讯状态 + + Dbg_Println(DBG_BIT_SYS_STATUS, "PS Voltage:%dmV",g_PB.meas_powerstrip_volt); + Dbg_Println(DBG_BIT_SYS_STATUS, "PB CURR:%dmA Voltage:%dmV %dmW",temp_val,g_PB.meas_powerbus_volt,temp_power); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "ACK Buff:", ackPara, i); + + *ackLen = i; +} + +/********************************************************************* + * @fn PB_ACK_SET_LED_BRIGHTNESS + * @brief BLV PB控制协议 - 设定灯带亮度 + * @return none + */ +void PB_ACK_SET_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T chnMask = para[PB_FMT_PARA]; + U8_T i = 0,save_flag = 0; + U16_T temp_val = 0x00; + + //修改后的协议控制内容 + for(i=0;i PB_SaveCurrent_Max)){ + g_PB.protect_curr = EEPROM_ParaDefault_SaveCurr; + + ackPara[0] = 0x01; //设置失败 + }else{ + + ackPara[0] = 0x00; //设置成功 + } + + PB_Set_SaveCurrent(g_PB.protect_curr); + + if(para[PB_FMT_PARA + 1] == 0xF1){ + if(g_eeprom.save_curr != g_PB.protect_curr){ + g_eeprom.save_curr = g_PB.protect_curr; + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + } + } + + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; +} + +/********************************************************************* + * @fn PB_ACK_GET_SaveCurrInfo + * @brief BLV PB控制协议 - 获取PB总线 保护电流信息 + * @return none + */ +void PB_ACK_GET_SaveCurrInfo(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + *ackLen = 1; + + ackPara[0] = g_PB.protect_curr; +} + +/********************************************************************* + * @fn PB_ACK_SET_UniversPara + * @brief BLV PB控制协议 - 设定整体参数，设定PB整体亮度和PowerBus 总线整体亮度 + * @return none + */ +void PB_ACK_SET_UniversPara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + + S8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + U8_T mask_bit = 0,rev = 0; + U32_T temp_val = 0; + + if( para_len < 5 ) return ; + + mask_bit = para[PB_FMT_PARA + 1]; + + if((mask_bit & 0x80) != 0x00){ + //设定全局亮度 + if( para[PB_FMT_PARA + 3] <= 100){ + g_eeprom.allBrightness = para[PB_FMT_PARA + 3]; //全局亮度 + Pwm_SetAllBrightness(g_eeprom.allBrightness); + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightness:%d",g_pwm.allBrightness); + } + if((mask_bit & 0x40) != 0x00){ + //设定全局可调上限 + if( para[PB_FMT_PARA + 4] <= 100){ + g_eeprom.allBrightnessUpLimit = para[PB_FMT_PARA + 4]; //全局亮度可调上限 + PWM_SetUpLimitVal(g_eeprom.allBrightnessUpLimit); + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightnessUpLimit:%d - %d",g_pwm.allBrightnessUpLimit,g_pwm.allPwmUpLimit); + } + if((mask_bit & 0x20) != 0x00){ + //设定全局可调下限 + if( (para[PB_FMT_PARA + 5] <= 100) && (para[PB_FMT_PARA + 5] < g_pwm.allBrightnessUpLimit) ){ + g_eeprom.allBrightnessDownLimit = para[PB_FMT_PARA + 5]; //全局亮度可调上限 + PWM_SetDownLimitVal(g_eeprom.allBrightnessDownLimit); + }else{ + rev = 0x01; //参数错误 + } + + Dbg_Println(DBG_BIT_SYS_STATUS,"Set allBrightnessDownLimit:%d - %d",g_pwm.allBrightnessDownLimit,g_pwm.allPwmDownLimit); + } + + if(para[PB_FMT_PARA + 2] == 0xF1){ + /*保存参数*/ + + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + } + + /*同时下发PowerBus*/ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_UniversPara"); + PowerBus_PackFillBuff(0x03,PowerBUS_CMD_SET_UniversPara,¶[PB_FMT_PARA + 1],para_len); + + *ackLen = 1; + + ackPara[0] = rev; +} + +/********************************************************************* + * @fn PB_ACK_SET_PowerBus_EnablePara + * @brief BLV PB控制协议 - PB使能状态控制 + * @return none + */ +void PB_ACK_SET_PowerBus_EnablePara(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA; + //*ackLen = 0; + + if(para_len < 0x02) return ; + + PB_Set_Power_State(para[PB_FMT_PARA]); + Dbg_Println(DBG_BIT_SYS_STATUS, "Power Enable %d",para[PB_FMT_PARA]); + + if(para[PB_FMT_PARA + 1] == 0xF1){ + + if(g_PB.enable != g_eeprom.powerbus_enable){ + g_eeprom.powerbus_enable = g_PB.enable; + EEPROM_WriteParaInfo(&g_eeprom); //保存参数 + } + } + + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; +} + +/********************************************************************* + * @fn PB_ACK_PassThroug_Data + * @brief BLV PB控制协议 - PB透传命令 + * @return none + */ +void PB_ACK_PassThroug_Data(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_PassThroug_Data"); + + if(PowerBUS_GetCommState() == 0x00){ + + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_FillSendBuff(para[PB_FMT_PARA] + 0x01,¶[PB_FMT_PARA + 2],para[PB_FMT_PARA + 1]); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + + +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 LED亮度 --按照地址段控制 每个回路可单独设定亮度 + * @return none + */ +void PB_ACK_SET_PB_LEDS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHTNESS"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LED亮度递增递减调节 --按照地址段控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_ADJUST"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_ADJUST,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 LED单开关状态 --按照单个回路控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_SWITCH"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LEDS_BRIGHT + * @brief BLV PB控制协议 - 设定PB总线 LED亮度 --按照地址段控制 + * @return none + */ +void PB_ACK_SET_PB_LEDS_BRIGHT(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LEDS_BRIGHT"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LEDS_BRIGHT,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 LED单回路亮度 --按照单个回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_BRIGHTNESS"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_Adjust + * @brief BLV PB控制协议 - 设定PB总线 LED单回路亮度调节 --按照单独回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_Adjust"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_ADJUST,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + + } +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_LED_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 LED单回路开关状态 --按照单独回路控制 + * @return none + */ +void PB_ACK_SET_PB_LED_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_LED_SWITCH"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_LED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLLED_Switch + * @brief BLV PB控制协议 - 设定PB总线 LED全部设备开关状态 + * @return none + */ +void PB_ACK_SET_PB_ALLLED_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "PB_ACK_SET_PB_ALLLED_Switch"); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_Succ; + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLLED_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %d",__func__,para_len); + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 0x4B){ + + if(PowerBUS_GetCommState() == 0x00){ + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 2]; + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + if(ch_mask != 0x00){ + //判断前32回路是否有控制状态 + + //Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //渐变时间 + + memcpy(&pack_buff[pack_len], ¶[PB_FMT_PARA + 12], 32); //拷贝32回路的控制亮度 + pack_len+=32; + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_BRIGHTNESS,pack_buff,pack_len); + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 6]; + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + if(ch_mask != 0x00){ + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + //Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //渐变时间 + + memcpy(&pack_buff[pack_len], ¶[PB_FMT_PARA + 44], 32); //拷贝32回路的控制亮度 + pack_len+=32; + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_BRIGHTNESS,pack_buff,pack_len); + } + + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + }else{ + //回复当前PowerBus 通讯状态繁忙 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 12){ + + if(PowerBUS_GetCommState() == 0x00){ + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 2]; + if(ch_mask != 0x00){ + //判断前32回路是否有控制状态 + + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //调节方向 + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_SWITCH,pack_buff,pack_len); + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 6]; + if(ch_mask != 0x00){ + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //调节方向 + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //调节时间 + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_SWITCH,pack_buff,pack_len); + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + + }else{ + //回复当前PowerBus 通讯状态繁忙 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIPS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIPS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0,off_mask = 0,on_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s %02x",__func__,para_len); + + /*2024-06-20 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 0x4A){ + if(PowerBUS_GetCommState() == 0x00){ + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 2]; + + Dbg_Println(DBG_BIT_SYS_STATUS, "L ch_mask :%08x",ch_mask); + if(ch_mask != 0x00){ + //判断前32回路是否有控制状态 + + for(U8_T ch = 0;ch<32;ch++){ + if( (ch_mask & (0x01<>8) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>16) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + + pack_buff[pack_len++] = 0x01; //开 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + } + + if(off_mask != 0x00){ + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>8) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>16) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + + pack_buff[pack_len++] = 0x00; //关 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + } + + } + + //前32个回路发送完成后，清除当前开关状态数据，然后进行后32个回路开关状态数据的装填 + on_mask = 0x00000000; + off_mask = 0x00000000; + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 6]; + if(ch_mask != 0x00){ + //判断后32回路是否有控制状态 + for(U8_T ch = 0;ch<32;ch++){ + if( (ch_mask & (0x01<>8) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>16) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((on_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + + pack_buff[pack_len++] = 0x01; //开 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + } + + if(off_mask != 0x00){ + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + + pack_buff[pack_len++] = (off_mask & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>8) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>16) & 0xFF); //回路Mask + pack_buff[pack_len++] = ((off_mask>>24) & 0xFF); //回路Mask + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //是否保存 + + pack_buff[pack_len++] = 0x00; //关 + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIPS_ADJUST,pack_buff,pack_len); + } + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + }else{ + //回复当前PowerBus 通讯状态繁忙 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + } +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIP_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_BRIGHTNESS + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_STRIP_BRIGHTNESS(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_BRIGHTNESS,¶[PB_FMT_PARA + 1],para_len); + }else{ + + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_Adjust + * @brief BLV PB控制协议 - 设定PB总线 LS 递增、递减 - 指定回路控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_Adjust(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_ADJUST,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LS 相对亮度调节 - 组地址控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + U8_T addr_field = 0; + U8_T pack_buff[60]; + U8_T pack_len = 0; + U32_T ch_mask = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + /*2024-07-02 修改主机这边组地址 按照64回路地址下发，而PowerBus还是按照32回路一组控制，因此需要手动分包*/ + if(para_len == 12){ + + if(PowerBUS_GetCommState() == 0x00){ + addr_field = para[PB_FMT_PARA + 1]; //地址段 0~3：正常地址段范围 ，大于4：属于群控地址 + ch_mask = para[PB_FMT_PARA + 5]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 4]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 3]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 2]; + if(ch_mask != 0x00){ + //判断前32回路是否有控制状态 + + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 2]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 3]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 4]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 5]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //相对调节亮度值 + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_GROUP_ADJUST,pack_buff,pack_len); + } + + ch_mask = para[PB_FMT_PARA + 9]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 8]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 7]; + ch_mask <<= 8; + ch_mask |= para[PB_FMT_PARA + 6]; + if(ch_mask != 0x00){ + //判断后32回路是否有控制状态 + memset(pack_buff, 0, sizeof(pack_buff)); + pack_len = 0; + + pack_buff[pack_len++] = addr_field*2+1; //组地址 + pack_buff[pack_len++] = para[PB_FMT_PARA + 6]; //回路Mask + pack_buff[pack_len++] = para[PB_FMT_PARA + 7]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 8]; + pack_buff[pack_len++] = para[PB_FMT_PARA + 9]; + + pack_buff[pack_len++] = para[PB_FMT_PARA + 10]; //模式 + pack_buff[pack_len++] = para[PB_FMT_PARA + 11]; //相对调节亮度值 + pack_buff[pack_len++] = para[PB_FMT_PARA + 12]; //只调亮的回路 + + Dbg_Print_Buff(DBG_BIT_SYS_STATUS, "Pack BUFF",pack_buff,pack_len); + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_GROUP_ADJUST,pack_buff,pack_len); + } + //回复当前PowerBus 通讯状态空闲，处理成功 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + + }else{ + //回复当前PowerBus 通讯状态繁忙 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + }else{ + //回复当前PowerBus 参数错误 + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_ParaError; + } +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST + * @brief BLV PB控制协议 - 设定PB总线 LS 相对亮度调节 - 指定回路控制 + * @return none + */ +void PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_STRIP_RELATIVE_ADJUST,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLSTRIP_Switch + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_ALLSTRIP_Switch(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLSTRIP_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAYS_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAYS_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAYS_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_ALLRELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_ALLRELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_ALLRELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn PB_ACK_SET_PB_RELAY_DELAY_SWITCH + * @brief BLV PB控制协议 - 设定PB总线 + * @return none + */ +void PB_ACK_SET_PB_RELAY_DELAY_SWITCH(U8_T *para,U8_T *ackPara,U16_T *ackLen){ + U8_T para_len = para[PB_FMT_LEN] - PB_FMT_PARA - 1; + + Dbg_Println(DBG_BIT_SYS_STATUS, "%s",__func__); + + if(PowerBUS_GetCommState() == 0x00){ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_Succ; + PowerBus_PackFillBuff(para[PB_FMT_PARA]+1,PowerBUS_CMD_SET_RELAY_DELAY_SWITCH,¶[PB_FMT_PARA + 1],para_len); + }else{ + *ackLen = 1; + + ackPara[0] = PB_CMD_Reply_CommStateBusy; + } + +} + +/********************************************************************* + * @fn BLV_PB_Control_Protocol_Processing + * @brief BLV PB控制协议处理函数(BLV_A8 PB控制协议) + * @return none + */ +U8_T BLV_PB_Control_Protocol_Processing(U8_T *data,U16_T len){ + + U8_T ack_flag = 0; + + //目前RCU地址为0x00 + if(data[PB_FMT_ADDR_TX] != 0x00){ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Tx Addr Error!"); + return 0x01; + } + + //目前PB地址为0x01 + if(data[PB_FMT_ADDR_RX] != 0x01){ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Rx Addr Error!"); + return 0x01; + } + + if(PB_CheckSum(data,len) != 0x00){ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Check Fail!!!!"); + return 0x01; + } + + if(data[PB_FMT_LEN] != len){ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB Len Fail %d - %d!!!!",data[PB_FMT_LEN],len); + return 0x01; + } + + if(data[PB_FMT_DEV_TYPE] != PB_DEV_TYPE){ + Dbg_Println(DBG_BIT_SYS_STATUS, "PB TYPE Fail %d - %d!!!!",data[PB_FMT_DEV_TYPE],PB_DEV_TYPE); + return 0x02; + } + + g_PB.recv_cmd = data[PB_FMT_CMD]; + if((data[PB_FMT_TYPE] & 0x0F) != g_PB.recv_sn){ + g_PB.recv_sn = data[PB_FMT_TYPE] & 0x0F; + g_PB.recv_addr = data[PB_FMT_ADDR_TX]; + + switch(data[PB_FMT_CMD]){ + case PB_CMD_GET_STATE: //查询当前状态 + PB_ACK_GET_STATE(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_STRIP_BRIGHTNESS: //设定灯带亮度 + PB_ACK_SET_LED_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_STRIP_SWITCH: //设定灯带开关状态 + PB_ACK_SET_STRIP_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_STRIP_ADJUST: + PB_ACK_SET_STRIP_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PIRTIGGLE_LED: + PB_ACK_SET_PIRTIGGLE_LED(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_CurrTiggleStrip: + PB_ACK_SET_CurrTiggleStrip(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_SaveCurrInfo: + PB_ACK_SET_SaveCurrInfo(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_GET_SaveCurrInfo: + PB_ACK_GET_SaveCurrInfo(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_UniversPara: + PB_ACK_SET_UniversPara(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PowerBus_Enable: + PB_ACK_SET_PowerBus_EnablePara(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_PassThroug_Data: + PB_ACK_PassThroug_Data(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LEDS_BRIGHTNESS: //设定PB总线 LED亮度 --按照地址段控制 单独控制回路亮度 + PB_ACK_SET_PB_LEDS_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LEDS_ADJUST: //设定PB总线 LED亮度递增递减调节 --按照地址段控制 + PB_ACK_SET_PB_LEDS_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LEDS_SWITCH: //设定PB总线 LED开关状态 --按照地址段控制 + PB_ACK_SET_PB_LEDS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LEDS_BRIGHT: //设定PB总线 LED亮度 --按照地址段控制 + PB_ACK_SET_PB_LEDS_BRIGHT(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LED_SWITCH: //设定PB总线 LED单开关状态 --按照单个回路控制 + PB_ACK_SET_PB_LED_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LED_BRIGHTNESS: //设定PB总线 LED单回路亮度 --按照单个回路控制 + PB_ACK_SET_PB_LED_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_LED_Adjust: //设定PB总线 LED单回路亮度 --按照单个回路控制 + PB_ACK_SET_PB_LED_Adjust(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_ALLLED_Switch: //设定PB总线 LED单回路亮度 --按照单个回路控制 + PB_ACK_SET_PB_ALLLED_Switch(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIPS_BRIGHTNESS: //PB 恒压调光 设定灯带亮度 --按照地址段控制 + PB_ACK_SET_PB_STRIPS_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIPS_ADJUST: //PB 恒压调光 设定灯带递增、递减 --按照地址段控制 + PB_ACK_SET_PB_STRIPS_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIPS_SWITCH: //PB 恒压调光 设定灯带开关状态 --按照地址段控制 + PB_ACK_SET_PB_STRIPS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_ALLSTRIP_Switch: //PB 恒压调光 设定灯带全部开关状态 + PB_ACK_SET_PB_ALLSTRIP_Switch(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIP_SWITCH: //PB 恒压调光 设定灯带开关状态 --按照指定回路 + PB_ACK_SET_PB_STRIP_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIP_BRIGHTNESS: //PB 恒压调光 设定灯带亮度 --按照指定回路 + PB_ACK_SET_PB_STRIP_BRIGHTNESS(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIP_Adjust: //PB 恒压调光 设定灯带递增、递减 --按照指定回路 + PB_ACK_SET_PB_STRIP_Adjust(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIP_RELATIVE_GROUP_ADJUST: //PB 恒压调光 设定灯带相对亮度 --按照地址段控制 + PB_ACK_SET_PB_STRIP_RELATIVE_GROUP_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_STRIP_RELATIVE_ADJUST: //PB 恒压调光 设定灯带相对亮度 --按照指定回路 + PB_ACK_SET_PB_STRIP_RELATIVE_ADJUST(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + + case PB_CMD_SET_PB_RELAYS_SWITCH: + PB_ACK_SET_PB_RELAYS_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_ALLRELAY_SWITCH: + PB_ACK_SET_PB_ALLRELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_RELAY_SWITCH: + PB_ACK_SET_PB_RELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + case PB_CMD_SET_PB_RELAY_DELAY_SWITCH: + PB_ACK_SET_PB_RELAY_DELAY_SWITCH(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + ack_flag = 0x01; + break; + + } + }else if((data[PB_FMT_TYPE] & 0x40) == 0x40){ + //重发标志位置位 - 回复应答数据，但是不处理 + switch(data[PB_FMT_CMD]){ + case PB_CMD_GET_STATE: + PB_ACK_GET_STATE(data,&g_PB.ackbuff[PB_FMT_PARA],&g_PB.ackLen); + break; + } + PB_RS485_ReplyAck(); + } + + if(ack_flag == 0x01){ + PB_RS485_ReplyAck(); + } + + return 0x00; +} + +/********************************************************************* + * @fn Get_ADC_Val_Filter + * @brief 获取ADC平滑滤波后的值 + */ +U32_T Get_ADC_Val_Filter(U16_T *data,U8_T data_len){ + U32_T sum_val = 0; + U16_T age_val = 0; + U8_T sum_cnt = 0; + + for(sum_cnt = 0;sum_cnt < data_len;sum_cnt++){ + sum_val += data[sum_cnt]; + } + + age_val = (sum_val / data_len) & 0xFFFF; + + return age_val; +} + +/*获取电流值*/ +U16_T Get_PB_CURR_VAL(void){ + + U16_T Temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_CURRPWR_Buff,MEAS_Debounce_Num); + g_PB.meas_powerbus_curr = (Temp_val * 16500 ) / 4096; + return g_PB.meas_powerbus_curr; +} + +/********************************************************************* + * @fn PMU_MEAS_Task + * @brief PB - 检测输入电压与负载任务，通过4路ADC检测 + */ +void PMU_MEAS_Task(void){ + + static U32_T meas_tick = 0; + U32_T temp_val = 0,convert_val = 0; + + if(SysTick_1ms - meas_tick >= 30){ + meas_tick = SysTick_1ms; + + if(g_PB.meas_cnt >= MEAS_BUFFER_SIZE) { + g_PB.meas_fill_flag = 0x01; + g_PB.meas_cnt = 0; + } + + ADC12_SEQEND_wait(0); + g_PB.meas_hv_PB_val[g_PB.meas_cnt] = ADC12_DATA_OUPUT(0); + + ADC12_SEQEND_wait(1); + g_PB.meas_hv_PS_val[g_PB.meas_cnt] = ADC12_DATA_OUPUT(1); + + ADC12_SEQEND_wait(2); + g_PB.meas_hv_CURRPWRx5_val = ADC12_DATA_OUPUT(2); + + ADC12_SEQEND_wait(3); + g_PB.meas_hv_CURRPWRx50_val = ADC12_DATA_OUPUT(3); + + /* 检测PB输出 - 负载电流 + * 2023 - 10 - 21 目前只使用X5挡位的检测 精度可达标 可以不使用x50挡位 + * + * */ +// if(g_PB.meas_hv_curr_ward == 0x01){ +// if(g_PB.meas_hv_CURRPWRx5_val <= 500){ +// g_PB.meas_hv_curr_toggle++; +// if(g_PB.meas_hv_curr_toggle >= 3){ +// g_PB.meas_hv_curr_toggle = 0; +// g_PB.meas_hv_curr_ward = 0x00; //切换至低挡位 +// } +// }else{ +// g_PB.meas_hv_curr_toggle = 0; +// } +// +// g_PB.meas_hv_CURRPWR_Buff[g_PB.meas_hv_curr_cnt] = g_PB.meas_hv_CURRPWRx5_val; +// +// }else { +// if(g_PB.meas_hv_CURRPWRx50_val >= 3500){ +// g_PB.meas_hv_curr_toggle++; +// if(g_PB.meas_hv_curr_toggle >= 3){ +// g_PB.meas_hv_curr_toggle = 0; +// g_PB.meas_hv_curr_ward = 0x01; //切换至高挡位 +// } +// }else{ +// g_PB.meas_hv_curr_toggle = 0; +// } +// +// g_PB.meas_hv_CURRPWR_Buff[g_PB.meas_hv_curr_cnt] = g_PB.meas_hv_CURRPWRx50_val; +// } + + if(g_PB.meas_hv_curr_cnt >= MEAS_Debounce_Num){ + g_PB.meas_hv_curr_cnt = 0; + } + g_PB.meas_hv_CURRPWR_Buff[g_PB.meas_hv_curr_cnt++] = g_PB.meas_hv_CURRPWRx5_val; + Get_PB_CURR_VAL(); + PB_Current_Monitoring_Meas(); + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PB Curr %dmA",Get_PB_CURR_VAL()); + + //以下内容为输出电源检测 + g_PB.meas_cnt++; + if(g_PB.meas_fill_flag != 0x01) return ; //检测BUFF未满,直接退出 + g_PB.meas_fill_flag = 0x00; //重新开始计数 + + /*Meas PB Voltage 检测OK后，才打开PB输出电源*/ + temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_PB_val,MEAS_BUFFER_SIZE); + g_PB.meas_powerbus_volt = (temp_val * 3300 * 16) / 4096; //输入电压 = 检测电压 * 16 +// Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PB Voltage:%dmv",g_PB.meas_powerbus_volt); + + if( (g_PB.meas_powerbus_volt >= MEAS_InputVoltage_Min) && (g_PB.meas_powerbus_volt <= MEAS_InputVoltage_Max) ){ + g_PB.meas_hv_PB_ONcnt++; + g_PB.meas_hv_PB_OFFcnt = 0x00; + + if(g_PB.meas_hv_PB_ONcnt >= MEAS_Debounce_Num){ + g_PB.meas_hv_PB_ONcnt = 0x00; + g_PB.meas_hv_PB_State = 0x01; + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PB Voltage ON %dmV",g_PB.meas_powerbus_volt); + } + }else { + g_PB.meas_hv_PB_ONcnt = 0x00; + g_PB.meas_hv_PB_OFFcnt++; + + if(g_PB.meas_hv_PB_OFFcnt >= MEAS_Debounce_Num){ + g_PB.meas_hv_PB_OFFcnt = 0x00; + g_PB.meas_hv_PB_State = 0x00; + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PB Voltage OFF %dmV",g_PB.meas_powerbus_volt); + } + } + + /*Meas PS Voltage 检测输入OK后，才打开PB输出电源*/ + temp_val = Get_ADC_Val_Filter(g_PB.meas_hv_PS_val,MEAS_BUFFER_SIZE); + g_PB.meas_powerstrip_volt = (temp_val * 3300 * 16) / 4096; +// Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PS Voltage:%dmv",g_PB.meas_powerstrip_volt); + + if( (g_PB.meas_powerstrip_volt >= MEAS_InputVoltage_Min) && (g_PB.meas_powerstrip_volt <= MEAS_InputVoltage_Max)){ + g_PB.meas_hv_PS_ONcnt++; + g_PB.meas_hv_PS_OFFcnt = 0x00; + + if(g_PB.meas_hv_PS_ONcnt >= MEAS_Debounce_Num){ + g_PB.meas_hv_PS_ONcnt = 0x00; + g_PB.meas_hv_PS_State = 0x01; + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PS Voltage ON %dmV",g_PB.meas_powerstrip_volt); + } + }else { + g_PB.meas_hv_PS_ONcnt = 0x00; + g_PB.meas_hv_PS_OFFcnt++; + + if(g_PB.meas_hv_PS_OFFcnt >= MEAS_Debounce_Num){ + g_PB.meas_hv_PS_OFFcnt = 0x00; + g_PB.meas_hv_PS_State = 0x00; + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Meas PS Voltage OFF %dmV",g_PB.meas_powerstrip_volt); + } + } + + } + + if(g_PB.meas_hv_PB_State != g_PB.last_meas_hv_PB_State) { + g_PB.last_meas_hv_PB_State = g_PB.meas_hv_PB_State; + + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PB State Change : %d",g_PB.last_meas_hv_PB_State); + switch(g_PB.last_meas_hv_PB_State) { + case 0x01: //开启PB输出 + DRV_PB36V_ON; + break; + case 0x00: //关闭PB输出 + DRV_PB36V_OFF; + break; + } + } + + if(g_PB.meas_hv_PS_State != g_PB.last_meas_hv_PS_State){ + g_PB.last_meas_hv_PS_State = g_PB.meas_hv_PS_State; + + Dbg_Println(DBG_BIT_SYS_STATUS,"HV PS State Change : %d",g_PB.last_meas_hv_PS_State); + + switch(g_PB.last_meas_hv_PS_State) { + case 0x01: //开启PS输出 + DRV_PS36V_ON; + break; + case 0x00: //关闭PS输出 + DRV_PS36V_OFF; + break; + } + } + +} + +//检测电流突变功能 +U16_T Current_Coarse_Filter(U16_T vsens){ + U8_T i=0; + U16_T rev = 0; + U32_T filter_sum = 0; + curr_monitoring.coarse_filter_buff[Filter_Coarse_Size] = vsens; + for(i=0;i= 20){ + curr_monitoring.dead_switch = 0x00; + curr_monitoring.release_debounce_cnt = 0; + } + }else{ + curr_monitoring.release_debounce_cnt = 0; + } + Dbg_Println(DBG_BIT_SYS_STATUS,"Curr Monit: %d - %dmW JUMP %d",temp_diff_val,temp_power,curr_monitoring.release_debounce_cnt); + return ; + } + + + Dbg_Println(DBG_BIT_SYS_STATUS,"Curr Monit: %d - %dmW",temp_diff_val,temp_power); + /*触发/消抖阈值是以功率为标准，所以需要转化一下*/ + if(curr_monitoring.curr_diff_val >= 0){ + if(temp_power >= curr_monitoring.trigger_threshold){ + curr_monitoring.trigger_debounce_cnt++; + if(curr_monitoring.trigger_debounce_cnt >= curr_monitoring.trigger_debounce_num){ + curr_monitoring.pb_state = 0x01; + curr_monitoring.trigger_debounce_cnt = 0; + } + }else{ + curr_monitoring.trigger_debounce_cnt = 0; + } + + }else if(curr_monitoring.curr_diff_val < 0){ + if(temp_power >= curr_monitoring.release_threshold){ + curr_monitoring.release_debounce_cnt++; + if(curr_monitoring.release_debounce_cnt >= curr_monitoring.release_debounce_num){ + curr_monitoring.pb_state = 0x00; + curr_monitoring.release_debounce_cnt = 0; + } + }else{ + curr_monitoring.release_debounce_cnt = 0; + } + } + + if(curr_monitoring.pb_state != curr_monitoring.last_pb_state){ + + curr_monitoring.last_pb_state = curr_monitoring.pb_state; + + Dbg_Println(DBG_BIT_SYS_STATUS,"curr_monitoring state: %d",curr_monitoring.pb_state); + + if(curr_monitoring.pb_state == 0x01){ + PWM_SetOutBrightness(PWM_OUT_CH1,curr_monitoring.triggle_strip_bright[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2,curr_monitoring.triggle_strip_bright[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3,curr_monitoring.triggle_strip_bright[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.triggle_strip_bright[PWM_OUT_CH4]); + }else{ + PWM_SetOutBrightness(PWM_OUT_CH1,curr_monitoring.release_strip_bright[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2,curr_monitoring.release_strip_bright[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3,curr_monitoring.release_strip_bright[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4,curr_monitoring.release_strip_bright[PWM_OUT_CH4]); + } + } + + //Dbg_NoTick_Println(DBG_BIT_Debug_STATUS,"%d,%d,%d,%d",coarse_val,fine_val,curr_monitoring.curr_diff_val,curr_monitoring.pb_state); +} + +/*让PB触发电流失效一段时间*/ +void Set_PB_CurrMonitoring_Dead(void){ + curr_monitoring.dead_switch = 0x01; + + //根据时间 +// curr_monitoring.dead_time = time; +// curr_monitoring.dead_tick = SysTick_1ms; + + //根据稳定 + curr_monitoring.release_debounce_cnt = 0; +} + +void PB_Task(void){ + PB_Soft_Boot_Task(); + + PB_Protect_Task(); + + PowerBus_SendBuffer_Task(); + + PMU_MEAS_Task(); +} + + + + + diff --git a/Source/SYSTEM/pwm.c b/Source/SYSTEM/pwm.c new file mode 100644 index 0000000..3059d89 --- /dev/null +++ b/Source/SYSTEM/pwm.c @@ -0,0 +1,416 @@ +#include "includes.h" + +PWM_CONTROL_T g_pwm; +PWM_AUTO_ADJUST_T g_pwmAutoAdj; + +void PWM_Init(void){ + U32_T temp_val = 0; + memset(&g_pwm,0,sizeof(PWM_CONTROL_T)); + memset(&g_pwmAutoAdj,0,sizeof(PWM_AUTO_ADJUST_T)); + + g_pwm.allBrightness = g_eeprom.allBrightness; + g_pwm.switchState[PWM_OUT_CH1] = g_eeprom.swithcState[PWM_OUT_CH1]; + g_pwm.switchState[PWM_OUT_CH2] = g_eeprom.swithcState[PWM_OUT_CH2]; + g_pwm.switchState[PWM_OUT_CH3] = g_eeprom.swithcState[PWM_OUT_CH3]; + g_pwm.switchState[PWM_OUT_CH4] = g_eeprom.swithcState[PWM_OUT_CH4]; + + g_pwm.gradualTime[PWM_OUT_CH1] = g_eeprom.gradialTime[PWM_OUT_CH1]; + g_pwm.gradualTime[PWM_OUT_CH2] = g_eeprom.gradialTime[PWM_OUT_CH2]; + g_pwm.gradualTime[PWM_OUT_CH3] = g_eeprom.gradialTime[PWM_OUT_CH3]; + g_pwm.gradualTime[PWM_OUT_CH4] = g_eeprom.gradialTime[PWM_OUT_CH4]; + + g_pwm.irqEnable = TRUE; + g_pwm.allBrightnessUpLimit = g_eeprom.allBrightnessUpLimit; + g_pwm.allBrightnessDownLimit = g_eeprom.allBrightnessDownLimit; + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + g_pwm.allPwmUpLimit = temp_val; + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessDownLimit))/10000; + g_pwm.allPwmDownLimit = temp_val; + + PWM_SetOutBrightness(PWM_OUT_CH1,g_eeprom.brightness[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2,g_eeprom.brightness[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3,g_eeprom.brightness[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4,g_eeprom.brightness[PWM_OUT_CH4]); + + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightness %d",g_pwm.allBrightness); + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightnessUpLimit %d",g_pwm.allBrightnessUpLimit); + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightnessDownLimit %d",g_pwm.allBrightnessDownLimit); + Dbg_Println(DBG_BIT_SYS_STATUS,"allBrightness %d",g_pwm.allBrightness); + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH1] %d",g_pwm.switchState[PWM_OUT_CH1]); + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH2] %d",g_pwm.switchState[PWM_OUT_CH2]); + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH3] %d",g_pwm.switchState[PWM_OUT_CH3]); + Dbg_Println(DBG_BIT_SYS_STATUS,"switchState[PWM_OUT_CH4] %d",g_pwm.switchState[PWM_OUT_CH4]); + + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH1] %d",g_pwm.gradualTime[PWM_OUT_CH1]); + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH2] %d",g_pwm.gradualTime[PWM_OUT_CH2]); + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH3] %d",g_pwm.gradualTime[PWM_OUT_CH3]); + Dbg_Println(DBG_BIT_SYS_STATUS,"gradualTime[PWM_OUT_CH4] %d",g_pwm.gradualTime[PWM_OUT_CH4]); + + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH1] %d",g_eeprom.brightness[PWM_OUT_CH1]); + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH2] %d",g_eeprom.brightness[PWM_OUT_CH2]); + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH3] %d",g_eeprom.brightness[PWM_OUT_CH3]); + Dbg_Println(DBG_BIT_SYS_STATUS,"brightness[PWM_OUT_CH4] %d",g_eeprom.brightness[PWM_OUT_CH4]); + + //设置指定亮度 +// g_pwm.pwmValCurr[PWM_OUT_CH1] = 0; +// g_pwm.pwmValCurr[PWM_OUT_CH2] = 550; +// g_pwm.pwmValCurr[PWM_OUT_CH3] = 600; +// g_pwm.pwmValCurr[PWM_OUT_CH4] = 650; +// +// PWM_SetOutDuty(PWM_OUT_CH1,g_pwm.pwmValCurr[PWM_OUT_CH1]); +// PWM_SetOutDuty(PWM_OUT_CH2,g_pwm.pwmValCurr[PWM_OUT_CH2]); +// PWM_SetOutDuty(PWM_OUT_CH3,g_pwm.pwmValCurr[PWM_OUT_CH3]); +// PWM_SetOutDuty(PWM_OUT_CH4,g_pwm.pwmValCurr[PWM_OUT_CH4]); + + //循环调光测试 +// PWM_SetAutoAdjust(PWM_OUT_CH1,0x01,0x01,2000); +// PWM_SetAutoAdjust(PWM_OUT_CH2,0x01,0x01,4000); +// PWM_SetAutoAdjust(PWM_OUT_CH3,0x01,0x01,8000); +// PWM_SetAutoAdjust(PWM_OUT_CH4,0x01,0x01,12000); +} + +/********************************************************************* + * @fn PWM_SetOutDuty + * @brief 设置PWM通道输出亮度 + * @para + * index: 设置通道 0~3 + * val: 输出值 PWM_OUT_VAL_MIN ~ PWM_OUT_VAL_MAX + */ +void PWM_SetOutDuty(U8_T index,U16_T val){ + U16_T temp_val = 0; + if(val > PWM_OUT_VAL_MAX) return; + + //temp_val = PWM_OUT_VAL_MAX - val; + temp_val = val; + switch(index){ + case PWM_OUT_CH1: + EPT0->CMPA=temp_val; + break; + case PWM_OUT_CH2: + EPT0->CMPB=temp_val; + break; + case PWM_OUT_CH3: + EPT0->CMPC=temp_val; + break; + case PWM_OUT_CH4: + EPT0->CMPD=temp_val; + break; + } +} + +/********************************************************************* + * @fn PWM_SetCHGradualTime + * @brief 设置PWM通道渐变时间 + * @para + * index: 设置通道 0~3 + * val: 渐变时间 单位：ms + */ +void PWM_SetCHGradualTime(U8_T index, U16_T val){ + if(index >= PWM_OUT_CH_MAX) return ; + + g_pwm.gradualTime[index] = val; +} + +/********************************************************************* + * @fn PWM_SetDownLimitVal + * @brief 设置PWM调光上限 + * @para + * val: 上限百分比 0~100 + */ +void PWM_SetUpLimitVal(U8_T val) +{ + U32_T temp_val = 0; + + g_pwm.allBrightnessUpLimit = val; + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessUpLimit))/10000; + g_pwm.allPwmUpLimit = temp_val; + + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); +} + +/********************************************************************* + * @fn PWM_SetDownLimitVal + * @brief 设置PWM调光下限 + * @para + * val: 下限百分比 0~100 + */ +void PWM_SetDownLimitVal(U8_T val) +{ + U32_T temp_val = 0; + + g_pwm.allBrightnessDownLimit = val; + temp_val = (U32_T)((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.allBrightnessDownLimit))/10000; + g_pwm.allPwmDownLimit = temp_val; + + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); +} + +/********************************************************************* + * @fn Pwm_SetOnOffState + * @brief 设置PWM通道开关状态 + * @para + * index: 设置通道 0~3 + * state: 设置开关状态 0x00:关；0x01:开 + */ +void Pwm_SetOnOffState(U8_T index, U8_T state) +{ + if(index >= PWM_OUT_CH_MAX) return ; + + g_pwm.switchState[index] = state; + PWM_SetOutBrightness(index, g_pwm.brightnessCurr[index]); +} + +/********************************************************************* + * @fn Pwm_SetAllBrightness + * @brief 设置PWM全局亮度 + * @para + * val: 设置全局亮度 0~100 + */ +void Pwm_SetAllBrightness(U8_T val) +{ + g_pwm.allBrightness = val; + PWM_SetOutBrightness(PWM_OUT_CH1, g_pwm.brightnessCurr[PWM_OUT_CH1]); + PWM_SetOutBrightness(PWM_OUT_CH2, g_pwm.brightnessCurr[PWM_OUT_CH2]); + PWM_SetOutBrightness(PWM_OUT_CH3, g_pwm.brightnessCurr[PWM_OUT_CH3]); + PWM_SetOutBrightness(PWM_OUT_CH4, g_pwm.brightnessCurr[PWM_OUT_CH4]); +} + +/********************************************************************* + * @fn PWM_SetOutBrightness + * @brief 设置PWM 通道输出亮度 + * @para + * index: 设置通道 0~3 + * brightness：设置亮度 0~100 + */ +void PWM_SetOutBrightness(U8_T index, U8_T brightness){ + U32_T tempPwmVal = 0; + + if(brightness != 0x00){ + if(brightness >= g_pwm.allBrightnessUpLimit) { + brightness = g_pwm.allBrightnessUpLimit; + }else if(brightness <= g_pwm.allBrightnessDownLimit){ + brightness = g_pwm.allBrightnessDownLimit; + } + } + + g_pwm.irqEnable = FALSE; + + g_pwmAutoAdj.enable[index] = FALSE; + g_pwm.controlFlag[index] = TRUE; + g_pwm.brightnessCurr[index] = brightness; + //当前PWM值 = PWM调节最大值 * 全局亮度百分比 * 当前亮度百分比 * 开关状态 + tempPwmVal = ((PWM_OUT_VAL_MAX * g_pwm.allBrightness * g_pwm.brightnessCurr[index]) * g_pwm.switchState[index])/10000; + g_pwm.pwmValTarget[index] = tempPwmVal; + + if(g_pwm.pwmValTarget[index] == g_pwm.pwmValCurr[index]){ + g_pwm.addOrDecFlag[index] = PWMA_Nochange; + }else if(g_pwm.pwmValTarget[index] > g_pwm.pwmValCurr[index]){ + g_pwm.addOrDecFlag[index] = PWMA_Ascending; + + if(g_pwm.gradualTime[index] != 0x00){ + tempPwmVal = g_pwm.pwmValTarget[index] - g_pwm.pwmValCurr[index]; + + g_pwm.pwmStep[index] = ((float)tempPwmVal*1.0 / g_pwm.gradualTime[index]); + + }else{ + g_pwm.pwmStep[index] = g_pwm.pwmValTarget[index] - g_pwm.pwmValCurr[index]; + } + + }else if(g_pwm.pwmValTarget[index] < g_pwm.pwmValCurr[index]){ + g_pwm.addOrDecFlag[index] = PWMA_Decreasing; + + if(g_pwm.gradualTime[index] != 0x00){ + + tempPwmVal = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + + g_pwm.pwmStep[index] = ((float)tempPwmVal*1.0 / g_pwm.gradualTime[index]); + + }else { + g_pwm.pwmStep[index] = g_pwm.pwmValCurr[index] - g_pwm.pwmValTarget[index]; + } + } + //Dbg_Println(DBG_BIT_SYS_STATUS,"PWM%d Step - %f",index,g_pwm.pwmStep[index]); + + g_pwm.irqEnable = TRUE; +} + +/********************************************************************* + * @fn PWM_SetAutoAdjust + * @brief 设置PWM自动调光 + * @para + * index: 设置通道 0~3 + * mode： 自动调光模式 0x00:调节到顶端停止 0x01:循环调节 0x02:停止调节 + * adj： 调节方向 0x00:递减 0x01:递增 0x02:与上次命令相反 + * adj_time：调节时间 亮度0~100的调节时间，单位：ms + */ +void PWM_SetAutoAdjust(U8_T index,U8_T mode,U8_T adj,U16_T adj_time){ + g_pwm.irqEnable = FALSE; + g_pwmAutoAdj.enable[index] = TRUE; + + if(mode == 0x02){ + g_pwmAutoAdj.enable[index] = FALSE; //停止自动调节 + + g_pwm.brightnessCurr[index] = (g_pwm.pwmValCurr[index] * 100) / PWM_OUT_VAL_MAX; //同步一下当前亮度 + + if(g_pwm.switchState[index] == 0x00){ + //如果当前回路状态为关，当前输出PWM也应为0 + g_pwm.pwmValCurr[index] = 0; + g_pwm.pwmFloatValCurr[index] = 0; + } + }else{ + g_pwmAutoAdj.adjMode[index] = mode; + } + + if(adj == 0x02){ + if(g_pwmAutoAdj.adjDir[index] == 0x01){ + g_pwmAutoAdj.adjDir[index] = 0x00; + }else{ + g_pwmAutoAdj.adjDir[index] = 0x01; + } + }else if(adj < 0x02){ + g_pwmAutoAdj.adjDir[index] = adj; + }else{ + g_pwmAutoAdj.adjDir[index] = 0x00; + } + + if(adj_time != 0x00){ + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / adj_time); + }else{ + //循环调光时间最短为100ms + g_pwmAutoAdj.pwmStep[index] = (float)(PWM_OUT_VAL_MAX*1.0 / 100); + } + + //Dbg_Println(DBG_BIT_SYS_STATUS,"Adjust PWM%d Step - %f",index,g_pwmAutoAdj.pwmStep[index]); + g_pwm.irqEnable = TRUE; +} + +void PWM_Timer_Enable(void){ + g_pwm.irqEnable = TRUE; +} + +void PWM_Timer_Disable(void){ + g_pwm.irqEnable = FALSE; +} + +void PWM_Timer_1ms_Task(void){ + U8_T index = 0; + float temp_float_val = 0; + + if(g_pwm.irqEnable == TRUE){ + for(index = 0;index < PWM_OUT_CH_MAX; index++){ + if(g_pwmAutoAdj.enable[index] == FALSE){ + + //调节至指定亮度 + if(g_pwm.controlFlag[index] == TRUE){ + //当前PWM输出通道，需要进行调节 + if(g_pwm.gradualTime[index] != 0x00){ + if(g_pwm.addOrDecFlag[index] == PWMA_Ascending){ + + //PWM递增 - 防止溢出 + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwm.pwmStep[index]; + if(temp_float_val <= PWM_OUT_VAL_MAX){ + g_pwm.pwmFloatValCurr[index] = temp_float_val; + }else{ + g_pwm.pwmFloatValCurr[index] = PWM_OUT_VAL_MAX; + } + + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + //调节至目标值，便停止调节 + if(g_pwm.pwmValCurr[index] >= g_pwm.pwmValTarget[index]){ + g_pwm.pwmValCurr[index] = g_pwm.pwmValTarget[index]; + g_pwm.pwmFloatValCurr[index] = g_pwm.pwmValCurr[index]; + g_pwm.controlFlag[index] = FALSE; + } + + }else if(g_pwm.addOrDecFlag[index] == PWMA_Decreasing){ + + //PWM递减 - 防止溢出 + if(g_pwm.pwmFloatValCurr[index] >= g_pwm.pwmStep[index]){ + g_pwm.pwmFloatValCurr[index] -= g_pwm.pwmStep[index]; + }else{ + g_pwm.pwmFloatValCurr[index] = 0x00; + } + + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + //调节至目标值，便停止调节 + if(g_pwm.pwmValCurr[index] <= g_pwm.pwmValTarget[index]){ + g_pwm.pwmValCurr[index] = g_pwm.pwmValTarget[index]; + g_pwm.pwmFloatValCurr[index] = g_pwm.pwmValCurr[index]; + g_pwm.controlFlag[index] = FALSE; + } + }else{ + g_pwm.controlFlag[index] = FALSE; + //Dbg_Println(DBG_BIT_Debug_STATUS,"controlFlag 3 %d ",index); + } + }else { + //渐变时间为0，直接设置当前通道的PWM值 + g_pwm.pwmValCurr[index] = g_pwm.pwmValTarget[index]; + g_pwm.pwmFloatValCurr[index] = g_pwm.pwmValCurr[index]; + g_pwm.controlFlag[index] = FALSE; + } + + //Dbg_Println(DBG_BIT_SYS_STATUS,"PWM%d %d %f %f",index,g_pwm.pwmValCurr[index],g_pwm.pwmStep[index],g_pwm.pwmFloatValCurr[index]); + //设置通道的PWM输出的值 + PWM_SetOutDuty(index,g_pwm.pwmValCurr[index]); + } + }else { + + //自动调光 - 在设置的全局亮度上下限中进行调光 + if(g_pwmAutoAdj.adjDir[index] == 0x00){ + //调节方向 - 递减 + if((g_pwm.pwmFloatValCurr[index] >= g_pwmAutoAdj.pwmStep[index]) && (g_pwm.pwmFloatValCurr[index] >= (float)g_pwm.allPwmDownLimit) ){ + g_pwm.pwmFloatValCurr[index] -= g_pwmAutoAdj.pwmStep[index]; + }else{ + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmDownLimit; + + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + //循环调节 + g_pwmAutoAdj.adjDir[index] = 0x01; + }else { + g_pwmAutoAdj.enable[index] = FALSE; //自动调节完毕 + g_pwm.brightnessCurr[index] = g_pwm.allPwmDownLimit; //同步一下当前亮度 + } + } + }else if(g_pwmAutoAdj.adjDir[index] == 0x01){ + temp_float_val = g_pwm.pwmFloatValCurr[index] + g_pwmAutoAdj.pwmStep[index]; + + if( (temp_float_val <= PWM_OUT_VAL_MAX) && (g_pwm.pwmFloatValCurr[index] <= (float)g_pwm.allPwmUpLimit) ){ + g_pwm.pwmFloatValCurr[index] = temp_float_val; + }else{ + g_pwm.pwmFloatValCurr[index] = (float)g_pwm.allPwmUpLimit; + if(g_pwmAutoAdj.adjMode[index] == 0x01){ + //循环调节 + g_pwmAutoAdj.adjDir[index] = 0x00; + }else { + g_pwmAutoAdj.enable[index] = FALSE; //自动调节完毕 + g_pwm.brightnessCurr[index] = g_pwm.allPwmUpLimit; //同步一下当前亮度 + } + } + } + + g_pwm.pwmValCurr[index] = (U16_T)g_pwm.pwmFloatValCurr[index]; + + //设置通道的PWM输出的值 + if(g_pwm.switchState[index] != 0x00){ + + PWM_SetOutDuty(index,g_pwm.pwmValCurr[index]); + }else{ + /*在回路状态为关的情况下，不进行输出控制*/ + + } + + //Dbg_Println(DBG_BIT_SYS_STATUS,"PWM%d Adjust %d %f %f %d %d",index,g_pwm.pwmValCurr[index],g_pwm.pwmFloatValCurr[index],g_pwmAutoAdj.pwmStep[index],g_pwm.allPwmUpLimit,g_pwm.allPwmDownLimit); + + } + + } + } +} + + diff --git a/Source/SYSTEM/uart.c b/Source/SYSTEM/uart.c new file mode 100644 index 0000000..514728a --- /dev/null +++ b/Source/SYSTEM/uart.c @@ -0,0 +1,196 @@ +#include "includes.h" +#include +#include + +/** + * BLV_C8_PB 串口使用情况 + * UART1 用与RCU进行双向通讯 115200 -> 对应设置 416 + * UART0 用于PB数据发送，没有接收 9600 -> 对应设置 5000 + * */ + +UART_t g_uart; //目前该项目只使用串口1 进行双向通讯 + +void UARTx_Init(UART_IDX uart_id, Uart_prt prt_cf) { + switch(uart_id){ + case UART_0: + UART0_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART0,0); //use PA0.1->RXD0, PA0.0->TXD0 + + UARTInitRxTxIntEn(UART0,10000,UART_PAR_NONE); //baudrate=sysclock 48M/1000=4800,tx rx int enabled + UART0_Int_Enable(); + break; + case UART_1: + UART1_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART1,0); //use PA0.13->RXD1, PB0.0->TXD1 + + UARTInitRxTxIntEn(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + UART1_Int_Enable(); + + memset(&g_uart,0,sizeof(UART_t)); + + g_uart.RecvTimeout = Recv_115200_TimeOut; + g_uart.processing_cf = prt_cf; + + break; + case UART_2: + UART2_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART2,1); //use PA0.13->RXD1, PB0.0->TXD1 + + UARTInitRxTxIntEn(UART2,98,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + //UART1_Int_Enable(); + + break; + } +} + +/******************************************************************************* +* Function Name : UART1_RecvINT_Processing +* Description : 串口1 接收中断处理函数 - 接收中断调用 +*******************************************************************************/ +void UART1_RecvINT_Processing(char data){ + if((g_uart.RecvLen + 1) >= USART_BUFFER_SIZE) g_uart.RecvLen = 0; + g_uart.RecvBuffer[g_uart.RecvLen++] = (U8_T)data; + + g_uart.RecvIdleTiming = SysTick_1ms; + g_uart.Receiving = 0x01; +} + + +void UART1_TASK(void){ + U8_T rev = 0; + if(g_uart.Receiving == 0x01){ + + if(SysTick_1ms - g_uart.RecvIdleTiming > Recv_115200_TimeOut){ + g_uart.RecvIdleTiming = SysTick_1ms; + + memcpy(g_uart.DealBuff,g_uart.RecvBuffer,g_uart.RecvLen); + g_uart.DealLen = g_uart.RecvLen; + g_uart.RecvLen = 0; + g_uart.Receiving = 0; + + Dbg_Println(DBG_BIT_SYS_STATUS, "UART recv Len %d", g_uart.DealLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"UART buff",g_uart.DealBuff,g_uart.DealLen); + + if(g_uart.processing_cf != NULL){ + rev = g_uart.processing_cf(g_uart.DealBuff,g_uart.DealLen); + } + + if(rev == 0x01){ + //Dbg_Print_Buff(DBG_BIT_Debug_STATUS,"error buff ",g_uart.DealBuff,g_uart.DealLen); + } + + memset(g_uart.DealBuff,0,USART_BUFFER_SIZE); + } + } +} + + +/*调试信息输出接口*/ +U32_T Dbg_Switch = (DBG_OPT_Debug_STATUS << DBG_BIT_Debug_STATUS) + + (DBG_OPT_DEVICE_STATUS << DBG_BIT_DEVICE_STATUS) + + (DBG_OPT_SYS_STATUS << DBG_BIT_SYS_STATUS); + +#if DBG_LOG_EN + +char Dbg_Buffer[256] = {0}; +U32_T SysTick_Now = 0, SysTick_Last = 0, SysTick_Diff = 0; + +#endif + +void Dbg_NoTick_Println(int DbgOptBit, const char *cmd, ...){ +#if DBG_LOG_EN + U16_T str_offset = 0; + + if (Dbg_Switch & (1 << DbgOptBit)) { + + va_list args; //定义一个va_list类型的变量，用来储存单个参数 + va_start(args, cmd); //使args指向可变参数的第一个参数 + str_offset = vsnprintf(Dbg_Buffer, sizeof(Dbg_Buffer) ,cmd, args); //必须用vprintf等带V的 + va_end(args); //结束可变参数的获取 + + DBG_Printf(Dbg_Buffer,str_offset); + + DBG_Printf("\r\n",2); + } + +#endif +} + +void Dbg_Print(int DbgOptBit, const char *cmd, ...){ + +#if DBG_LOG_EN + U16_T str_offset = 0; + + if (Dbg_Switch & (1 << DbgOptBit)) { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差 + SysTick_Last = SysTick_Now; + str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer),"%8d [%6d]: ", SysTick_Now, SysTick_Diff); + DBG_Printf(Dbg_Buffer,str_offset); + + va_list args; //定义一个va_list类型的变量，用来储存单个参数 + va_start(args, cmd); //使args指向可变参数的第一个参数 + str_offset = vsnprintf(Dbg_Buffer, sizeof(Dbg_Buffer) ,cmd, args); //必须用vprintf等带V的 + va_end(args); //结束可变参数的获取 + + DBG_Printf(Dbg_Buffer,str_offset); + } + +#endif +} + +void Dbg_Println(int DbgOptBit, const char *cmd, ...){ + +#if DBG_LOG_EN + U16_T str_offset = 0; + + if (Dbg_Switch & (1 << DbgOptBit)) { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差 + SysTick_Last = SysTick_Now; + str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%8ld [%6ld]: ", SysTick_Now, SysTick_Diff); + DBG_Printf(Dbg_Buffer,str_offset); + + va_list args; //定义一个va_list类型的变量，用来储存单个参数 + va_start(args, cmd); //使args指向可变参数的第一个参数 + str_offset = vsnprintf(Dbg_Buffer, sizeof(Dbg_Buffer) ,cmd, args); //必须用vprintf等带V的 + va_end(args); //结束可变参数的获取 + + DBG_Printf(Dbg_Buffer,str_offset); + + DBG_Printf("\r\n",2); + } + +#endif +} + + +void Dbg_Print_Buff(int DbgOptBit, const char *cmd, U8_T *buff,U16_T len){ +#if DBG_LOG_EN + U16_T str_offset = 0; + + if (Dbg_Switch & (1 << DbgOptBit)) { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //上一次打印时间差 + SysTick_Last = SysTick_Now; + str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%8ld [%6ld]: %s", SysTick_Now, SysTick_Diff,cmd); + DBG_Printf(Dbg_Buffer,str_offset); + + for (uint32_t i = 0; i < len; i++) { + str_offset = snprintf(Dbg_Buffer, sizeof(Dbg_Buffer) , "%02X ", buff[i]); + DBG_Printf(Dbg_Buffer,str_offset); + } + + DBG_Printf("\r\n",2); + } + +#endif +} + + + + + + + + diff --git a/Source/arch/apt32f102_iostring.c b/Source/arch/apt32f102_iostring.c new file mode 100644 index 0000000..71147a1 --- /dev/null +++ b/Source/arch/apt32f102_iostring.c @@ -0,0 +1,143 @@ +/* + ****************************************************************************** + * @file apt32f102_iostring.c + * @author APT AE Team + * @version V1.00 + * @date 2020/05/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ +/****************************************************************************** +* Include Files +******************************************************************************/ +#include "apt32f102.h" +#include "apt32f102_uart.h" +#include "stdarg.h" +#include "stddef.h" +#include "stdio.h" +#define LDCC_DATA_P 0xe001105c /* LDCC Register. */ +#define LDCC_BIT_STATUS 0x80000000 /* LDCC Status bit. */ +//#define _debug_uart_io +/****************************************************************************** +* Main code +******************************************************************************/ +void __putchar__ (char ch) +{ +#ifdef _debug_uart_io + //UARTTxByte(UART0,s); //uart 0 + UARTTxByte(UART1,s); //uart 1 +#else + //select debug serial Pane + volatile unsigned int *pdata = (unsigned int *)LDCC_DATA_P; + while (*pdata & LDCC_BIT_STATUS); //Waiting for data read. + *pdata = ch; +#endif +} + +int *myitoa(int value, int* string, int radix) +{ + + int tmp[33]; + int* tp = tmp; + int i; + unsigned v; + int sign; + int* sp; + + if (radix > 36 || radix <= 1) + { + return 0; + } + + sign = (radix == 10 && value < 0); + if (sign) + v = -value; + else + v = (unsigned)value; + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) { + *tp++ = i+'0'; + + } else { + *tp++ = i + 'a' - 10; + + } + + } + + sp = string; + + if (sign) + *sp++ = '-'; + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + return string; +} + + +void my_printf(const char *fmt, ...) +{ + +// const char *s; + const int *s; + int d; + //char ch, *pbuf, buf[16]; + char ch, *pbuf; + int buf[16]; + va_list ap; + va_start(ap, fmt); + while (*fmt) { + if (*fmt != '%') { + __putchar__(*fmt++); + continue; + } + switch (*++fmt) { + case 's': + s = va_arg(ap, const int *); + for ( ; *s; s++) { + __putchar__(*s); + } + break; + case 'd': + d = va_arg(ap, int); + myitoa(d, buf, 10); + for (s = buf; *s; s++) { + __putchar__(*s); + } + break; + + case 'x': + case 'X': + d = va_arg(ap, int); + myitoa(d, buf, 16); + for (s = buf; *s; s++) { + __putchar__(*s); + } + break; + // Add other specifiers here... + case 'c': + case 'C': + ch = (unsigned char)va_arg(ap, int); + pbuf = &ch; + __putchar__(*pbuf); + break; + default: + __putchar__(*fmt); + break; + } + fmt++; + } + va_end(ap); +} + diff --git a/Source/arch/apt32f102a.svc b/Source/arch/apt32f102a.svc new file mode 100644 index 0000000..e6d8764 --- /dev/null +++ b/Source/arch/apt32f102a.svc @@ -0,0 +1,3453 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Source/arch/crt0.S b/Source/arch/crt0.S new file mode 100644 index 0000000..cc28c85 --- /dev/null +++ b/Source/arch/crt0.S @@ -0,0 +1,213 @@ +//start from __start, +//(0)initialize vector table +//(1)initialize all registers +//(2)prepare initial reg values for user process +//(3)initialize supervisor mode stack pointer +//(4)construct ASID Table +//(5)prepare PTE entry for user process start virtual address +//(6)creat a mapping between VPN:0 and PFN:0 for kernel +//(7)set VBR register +//(8)enable EE and MMU +//(9)jump to the main procedure using jsri main + + +#define UserOption 0x55aa0005 +.export vector_table +//.import VecTable +.align 10 +vector_table: //totally 256 entries +// .long __start +// .rept 128 +// .long __dummy +// .endr + +.long __start +.long MisalignedHandler +.long AccessErrHandler +.long DummyHandler +.long IllegalInstrHandler +.long PriviledgeVioHandler +.long DummyHandler +.long BreakPointHandler +.long UnrecExecpHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long Trap0Handler +.long Trap1Handler +.long Trap2Handler +.long Trap3Handler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long DummyHandler +.long PendTrapHandler +.long CORETHandler +.long SYSCONIntHandler +.long IFCIntHandler +.long ADCIntHandler +.long EPT0IntHandler +.long DummyHandler//EPT0EMIntHandler +.long WWDTHandler +.long EXI0IntHandler +.long EXI1IntHandler +.long GPT0IntHandler +.long DummyHandler//GPT1IntHandler +.long DummyHandler +.long RTCIntHandler +.long UART0IntHandler +.long UART1IntHandler +.long UART2IntHandler//USARTIntHandler +.long DummyHandler +.long I2CIntHandler +.long DummyHandler +.long SPI0IntHandler +.long SIO0IntHandler +.long EXI2to3IntHandler +.long EXI4to9IntHandler +.long EXI10to15IntHandler +.long CNTAIntHandler +.long TKEYIntHandler +.long LPTIntHandler +.long DummyHandler//LEDIntHandler +.long BT0IntHandler +.long BT1IntHandler +.long DummyHandler//BT2IntHandler +.long DummyHandler//BT3IntHandler +.long UserOption + +.text +.export __start +.long 0x00000000 +.long 0x00000000 +// .long __start +__start: + + + //initialize all registers + movi r0, 0 + movi r1, 0 + movi r2, 0 + movi r3, 0 + movi r4, 0 + movi r5, 0 + movi r6, 0 + movi r7, 0 + //movi r8, 0 + //movi r9, 0 + //movi r10, 0 + //movi r11, 0 + //movi r12, 0 + //movi r13, 0 + //movi r14, 0 + //movi r15, 0 + +//set VBR + lrw r2, vector_table + mtcr r2, cr<1,0> + +//enable EE bit of psr + mfcr r2, cr<0,0> + bseti r2, r2, 8 + mtcr r2, cr<0,0> + +////set rom access delay +// lrw r1, 0xe00000 +// lrw r2, 0x7 +// st.w r2, (r1,0x0) + +////enable cache +// lrw r1, 0xe000f000 +// movi r2, 0x2 +// st.w r2, (r1,0x0) +// lrw r2, 0x29 +// st.w r2, (r1,0x4) +// movi r2, 0x1 +// st.w r2, (r1,0x0) + +//disable power peak + lrw r1, 0xe000ef90 + movi r2, 0x0 + st.w r2, (r1, 0x0) + + + +//initialize kernel stack + lrw r7, __kernel_stack + mov r14,r7 + subi r6,r7,0x4 + + //lrw r3, 0x40 + lrw r3, 0x04 + + subu r4, r7, r3 + lrw r5, 0x0 +INIT_KERLE_STACK: + addi r4, 0x4 + st.w r5, (r4) + //cmphs r7, r4 + cmphs r6, r4 + bt INIT_KERLE_STACK + +__to_main: + lrw r0,__main + jsr r0 + mov r0, r0 + mov r0, r0 + + + + lrw r15, __exit + lrw r0,main + jmp r0 + mov r0, r0 + mov r0, r0 + mov r0, r0 + mov r0, r0 + mov r0, r0 + +.export __exit +__exit: + + lrw r4, 0x20003000 + //lrw r5, 0x0 + mov r5, r0 + st.w r5, (r4) + + mfcr r1, cr<0,0> + lrw r1, 0xFFFF + mtcr r1, cr<11,0> + lrw r1, 0xFFF + movi r0, 0x0 + st r1, (r0) + +.export __fail +__fail: + lrw r1, 0xEEEE + mtcr r1, cr<11,0> + lrw r1, 0xEEE + movi r0, 0x0 + st r1, (r0) + +__dummy: + br __fail + +.export DummyHandler +DummyHandler: + br __fail + + +.data +.align 10 +.long __start diff --git a/Source/arch/mem_init.c b/Source/arch/mem_init.c new file mode 100644 index 0000000..d9d8c00 --- /dev/null +++ b/Source/arch/mem_init.c @@ -0,0 +1,44 @@ +/* + * Filename : mem_init.c + * + * Memory Initialization + * + * Copyrights 2015 @ APTCHIP + * + * + */ +#include "string.h" + +extern char _end_rodata[]; +extern char _start_data[]; +extern char _end_data[]; + +extern char _bss_start[]; +extern char _ebss[]; + + +void __main( void ) +{ + + char *dst = _start_data; + char *src = _end_rodata; + + /* if the start of data (dst) + is not equal to end of text (src) then + copy it, else it's already in the right place + */ + if( _start_data != _end_rodata ) { +// __memcpy_fast( dst, src, (_end_data - _start_data)); + memcpy( dst, src, (_end_data - _start_data)); + } + + /* zero the bss + */ + if( _ebss - _bss_start ) { +// __memset_fast( _bss_start, 0x00, ( _ebss - _bss_start )); + memset( _bss_start, 0x00, ( _ebss - _bss_start )); + } + + +} + diff --git a/Source/cdkws.mk b/Source/cdkws.mk new file mode 100644 index 0000000..c897709 --- /dev/null +++ b/Source/cdkws.mk @@ -0,0 +1,14 @@ +.PHONY: clean All Project_Title Project_Build + +All: Project_Title Project_Build + +Project_Title: + @echo "----------Building project:[ MD203F8P - BuildSet ]----------" + +Project_Build: + @make -r -f MD203F8P.mk -j 8 -C ./ + + +clean: + @echo "----------Cleaning project:[ MD203F8P - BuildSet ]----------" + diff --git a/Source/ckcpu.ld b/Source/ckcpu.ld new file mode 100644 index 0000000..69c30de --- /dev/null +++ b/Source/ckcpu.ld @@ -0,0 +1,58 @@ +MEMORY +{ +ROM(RX) : ORIGIN = 0x00000000, LENGTH = 64K +RAM(RWX) : ORIGIN = 0x20000000, LENGTH = 4K +} +__kernel_stack = ORIGIN(RAM) + LENGTH(RAM) -8 ; +ENTRY(__start) + +SECTIONS { + .text : + { + . = ALIGN(0x4) ; + *crt0.o (.text) + *(.text) + } >ROM + + .RomCode : + { + . = ALIGN(0x4) ; + *(.text) + } >ROM + + .rodata : + { + . = ALIGN(0x4) ; + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4) ; + _end_rodata = .; + } >ROM + + .data : AT(_end_rodata) + { + . = ALIGN(0x4) ; + _start_data = .; + *( .data ); + . = ALIGN(0x4) ; + _end_data = .; + } >RAM + + .bss : + { + . = ALIGN(0x4) ; + _bss_start = . ; + *(.sbss) + *(.sbss.*) + *(.scommon) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(0x4) ; + _ebss = . ; + _end = . ; + end = . ; + } >RAM + +} + diff --git a/Source/doc/APT32F102_Lib_Fix_Log.md b/Source/doc/APT32F102_Lib_Fix_Log.md new file mode 100644 index 0000000..f4df6c0 --- /dev/null +++ b/Source/doc/APT32F102_Lib_Fix_Log.md @@ -0,0 +1,84 @@ +#20180129 V1.00 初版 + +#20180131 V1.02： + 1.apt32f102_i2c.h，修改I2C_Slave_CONFIG(); PA0.1定义错误 + 2.apt32f102_i2c.c，修改void I2C_Slave_Receive(void) + 3.apt32f102_interrupt.c，修改LPTIntHandler(); + 4.syscon.h，修改“SYSCON_SCLKCR_RST ((CSP_REGISTER_T)0xD22Dul<<16)” + 5.syscon.C， SYSCON_RST_VALUE(void) ； + 5.EPT.C &EPT.H 修改 + 6.syscon.h，修改 INTDET_POL_X_TypeDef枚举; + 7.apt32f102_initial.c ，修改EPT0_Config()； + 8.apt32f102_interrupt.c，修改EPT0IntHandler(); + 9.修改了CRC输入函数，分32/16/8bit数据输入 + 10.增加了GPT同步及触发事件函数 + 11.增加了WWDT初始化函数 +#20201124 V1.02： + 1.修改UART_IO_Init(); PA0.15 PA0.14初始化 + 2.删除SYSCON_CONFIG()；"EVTRG function 程序屏蔽" + 3.删除了tkey相关残留的程序 +#20201124 V1.03： + 1.增加了touch key库文件 +#20201202 V1.04： + 1.修改了SYSCON_General_CMD();函数，fix 使用外部晶振后调试口被占用的问题 + 2.修改了BT PB0.0配置错误的问题 + 3.修改了外部中断向量EXI9错误的问题 + 4.修改了外部中断向量EXI4to9IntHandle，EXI10to15IntHandler + 5.修改了GPT.h中PB0.1定义错误的问题 + 6.增加了IFC读ReadDataArry_U8函数，读数据时字节长度可不按4的倍数 + 7.修改了spi.c中PA0.8配置错误的问题 +#20200121 V1.05： + 1.修改了ADC初始化中的错误 + 2.修改了apt32f102_interrupt.c中EXI15的错误 + 3.修改了BT.c中BT0和BT1混淆的问题 + 4.修复了使用触摸FVR参考时，调用ADC造成触摸失灵的问题 + 5.增加了tkey的睡眠睡醒功能 + 6.修改了1.04 .s文件中外部中断定义错误的问题 +#20210601 V1.06： + 1.修改了COUNTERA IO配置错误 + 2.修改了BT中IO配置错误 + 3.修改了EPT PB0.5 CHAY配置错误 + 4.修改了EPT 外部触发端口使能配置相反的错误 + 5.增加了I2C做从机时配置i2c中断优先级为最高的配置 + 6.修改了调用GPIO_DeInit后调试口被修改的问题 + 7.修复了TK在FVR模式以外开启TCH3后触摸初始化卡死的问题 + 8.修改了TK参数配置中，使能TK的方式，采用更直观的方式 + 9.修改了TK参数配置中，EC默认电压为3V，FVR参考默认2.048V，防止客户使用3.3V工作电压时一开始TK无法工作的问题 +#20210621 V1.08： + 1.解决了触摸长时间睡眠后，唤醒失败的问题（功耗增加10uA） + 2.修改了注释为英文 + 3.修改了不同版本的触摸库文件方便不同应用 +#20210801 V1.09： + 1.修改了syscon.c，解决了系统主频在切换时偶尔遇到的时钟卡死问题 + 2.增加了IO remap功能函数 + 3.修正1_09和1_09M这两个版本.a库，多键模式按键误清零的问题 + 4.删除之前版本initial.c中对EVTRG function的配置，以解决因此产生的某些情况下睡眠后功耗异常的问题 +#20210825 V1.10： + 1.修改了SPI做从机时，PA0.14/PA0.15配置错误的问题 + 2.修改了RTC中参数的定义为volatile，解决某些意外情况下进位时小时位出现错误值的问题 + 3.增加了BT中控制波形stop时输出高/低电平函数 + 4.修改gpio.c中配置外部组扩展配置时PB0组IO无法配置的问题,增加了EXI16~19的中断函数 + 5.syscon中加入clo输出配置函数 + 6.在syscon.c中增加Set_INT_Priority();函数，可直接配置中断优先级 + 7.在fwlib文件夹增加了iostring.c文件 + 8.修改库文件包名称为APT32F102x_StdPeriph_Lib +#20211101 V1.11： + 1.修改了SIO做RX时，配置错误的问题 + 2.增加了debug print功能 + 3.增加了芯片svc文件，方便查看芯片register内容 + 4.解决了TK和ADC选择不同参考源时造成的互相影响的问题，修改了ADC.c和TK库文件 + 5.修改了EPT中EVTRG配置移位错误 +#20211122 V1.12： + 1.修改了GPT 同步触发模式的配置定义错误 + 2.增加了频率校准函数std_clk_calib();支持HFOSC IMOSC频率软件校准； + 3.lib_102ClkCalib_1_03，修改了1.02的校准库在与触摸低功耗共同使用时，会造成睡眠功耗偏大到1.2mA的问题 +#20211213 V1.13： + 1.修改了在使用ADC时，因为配置ADC序列和序列个数不一致而可能引起的ADC卡死问题 + 2.修改了UART初始化使能函数，解决了因配置顺序导致INT_TX_DONE中断无法进入的问题 + 3.修改了IFC_MR中不同时钟频率下WAIT和SPEED默认值 + 4.解除了TK使用FVR模式参考电压固定选择4.096V的限制，可选择2.048V"抗干扰能力低于4.096V" +#20220825 V1.15： + 1.修改去除部分编译中出现的警告 + 2.修改触摸库函数，增加因异常情况overflow后造成的按键扫描卡住问题 + 3.修改部分代码中注释的书写问题 + 4.修改了uart初始化中奇偶校验错误的问题 \ No newline at end of file diff --git a/Source/doc/APT32F102_TKLib_Version.md b/Source/doc/APT32F102_TKLib_Version.md new file mode 100644 index 0000000..0c108e4 --- /dev/null +++ b/Source/doc/APT32F102_TKLib_Version.md @@ -0,0 +1,16 @@ +#Touch Key库最新版本V1.15 +#Touch Key中断扫描版本 +lib_102TKey_1_15.a 触摸库文件完整版(默认库文件) +lib_102TKey_1_15C.a 触摸库文件精简版，程序占用空间更小，扫描速度更快，抗干扰性能降低，睡眠功耗更低 +#Touch Key主循环扫描版本 +lib_102TKey_1_15M.a 触摸库文件主循环扫描完整版，不支持睡眠唤醒 +lib_102TKey_1_15MC.a 触摸库文件主循环扫描精简版，程序占用空间更小，扫描速度更快，抗干扰性能降低，去除coret占用，没有长按强制更新功能，不支持睡眠唤醒 +#说明： +C---Compression +M---Main Loop +#注意： +1. 使用Touch Key主循环扫描版本，需要在主循环中添加tk_prgm();函数，每次执行时间在1~1.8ms之间 +2. 未使用coret功能的版本，需要在apt32f102_interrupt.c中重新打开CORETHandler()入口 +3. 中断扫描版本：每一轮的按键扫描时间可控，触摸体验良好；会占用中断资源，如果有高时序要求的中断，没有配置中断好中断优先级的话会影响高时序要求的中断 +4. 主循环版本：不会占用中断资源，对别的中断不会有影响；每一轮的按键扫描时间不可控，如果主循环一次循环里有函数占用大量时间，会影响按键的触摸体验 +5. 使用1.15版本，必须在linker中包含libm数学库 diff --git a/Source/drivers/apt32f102.c b/Source/drivers/apt32f102.c new file mode 100644 index 0000000..0eb4720 --- /dev/null +++ b/Source/drivers/apt32f102.c @@ -0,0 +1,146 @@ +/* + ****************************************************************************** + * @file apt32f102.c + * @author APT AE Team + * @version V1.01 + * @date 2019/04/05 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +/** + * @addtogroup Struct pointer assignment Functions + * @{ + */ +CSP_CK801_T *CK801 = (CSP_CK801_T *)CK801_BASEADDR ; + +CSP_IFC_T *IFC = (CSP_IFC_T *)APB_IFCBase ; +CSP_SYSCON_T *SYSCON = (CSP_SYSCON_T *)APB_SYSCONBase ; + +CSP_TKEY_T *TKEY = (CSP_TKEY_T *)APB_TKEYBase ; +CSP_TKEYBUF_T *TKEYBUF = (CSP_TKEYBUF_T *)APB_TKEYBUFBase; +CSP_ADC12_T *ADC0 = (CSP_ADC12_T *)APB_ADC0Base ; + +CSP_GPIO_T *GPIOA0 = (CSP_GPIO_T *)APB_GPIOA0Base ; // A0 +CSP_GPIO_T *GPIOB0 = (CSP_GPIO_T *)APB_GPIOB0Base ; // B0 +CSP_IGRP_T *GPIOGRP = (CSP_IGRP_T *)APB_IGRPBase; + +CSP_UART_T *UART0 = (CSP_UART_T *)APB_UART0Base ; +CSP_UART_T *UART1 = (CSP_UART_T *)APB_UART1Base ; +CSP_UART_T *UART2 = (CSP_UART_T *)APB_UART2Base ; +CSP_SSP_T *SPI0 = (CSP_SSP_T *)APB_SPI0Base ; +CSP_I2C_T *I2C0 = (CSP_I2C_T *)APB_I2C0Base ; +CSP_SIO_T *SIO0 = (CSP_SIO_T *)APB_SIO0Base ; +CSP_CA_T *CA0 = (CSP_CA_T *)APB_CNTABase ; + +CSP_GPT_T *GPT0 = (CSP_GPT_T *)APB_GPT0Base; +CSP_EPT_T *EPT0 = (CSP_EPT_T *)APB_EPT0Base ; +CSP_ETCB_T *ETCB = (CSP_ETCB_T *)APB_ETCBBase ; +CSP_RTC_T *RTC = (CSP_RTC_T *)APB_RTCBase ; +CSP_LPT_T *LPT = (CSP_LPT_T *)APB_LPTBase ; +CSP_WWDT_T *WWDT = (CSP_WWDT_T *)APB_WWDTBase ; +CSP_BT_T *BT0 = (CSP_BT_T *)APB_BT0Base ; +CSP_BT_T *BT1 = (CSP_BT_T *)APB_BT1Base ; +CSP_CRC_T *CRC = (CSP_CRC_T *)AHB_CRCBase ; +CSP_HWD_T *HWD = (CSP_HWD_T *)APB_HWDBase ; + +int __divsi3 ( int a, int b) +{ + int PSR; + __asm volatile( + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 0; + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + __asm volatile( + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + + return HWD->QUOTIENT; +} + unsigned int __udivsi3 ( unsigned int a, unsigned int b) +{ + int PSR; + __asm volatile( + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 1; + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + __asm volatile( + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + + return HWD->QUOTIENT; +} + +int __modsi3 ( int a, int b) +{ + int PSR; + __asm volatile( + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 0; + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + __asm volatile( + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + return HWD->REMAIN; +} + +unsigned int __umodsi3 ( unsigned int a, unsigned int b) +{ + int PSR; + __asm volatile( + "mfcr %0 , psr \n\r" + "psrclr ie \n\r" + : "=r"(PSR) + ); + + HWD->CR = 1; + HWD->DIVIDENT = a; + HWD->DIVISOR = b; + + PSR |= 0x80000000; + __asm volatile( + "mtcr %0 , psr \n\r" + : + :"r"(PSR) + ); + return HWD->REMAIN; +} +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/drivers/apt32f102_ck801.c b/Source/drivers/apt32f102_ck801.c new file mode 100644 index 0000000..3cf5be2 --- /dev/null +++ b/Source/drivers/apt32f102_ck801.c @@ -0,0 +1,275 @@ +/* + ****************************************************************************** + * @file apt32f102_ck801.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" +#include "apt32f102_ck801.h" + +void CK801_Init(void) +{ + /* Initial the Interrupt source priority level registers */ + CK801->IPR[0] = 0xC0804000; + CK801->IPR[1] = 0xC0004000; + CK801->IPR[2] = 0xC0804000; + CK801->IPR[3] = 0xC0804000; + CK801->IPR[4] = 0xC0804000; + CK801->IPR[5] = 0xC0804000; + CK801->IPR[6] = 0xC0804000; + CK801->IPR[7] = 0xC0804000; + + CK801->IPTR = 0x00000000;//disable threshold +} + +void force_interrupt(IRQn_Type IRQn) +{ + CK801->ISPR = (1 << (uint32_t)(IRQn)); +} + + +void CK_CPU_EnAllNormalIrq(void) +{ + asm ("psrset ee,ie"); +} + +void CK_CPU_DisAllNormalIrq(void) +{ + asm ("psrclr ie"); +} + +/* ########################## NVIC functions #################################### */ + + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +__INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + + CK801->ISER = 1 << (uint32_t)(IRQn); +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +__INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + CK801->ICER = 1 << (uint32_t)(IRQn); +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return always 0 + */ +__INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return (uint32_t)(CK801->ISPR); +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * No effect. + */ +__INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + CK801->ISPR = (1 << (uint32_t)(IRQn)); +} +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * No effect. + */ +__INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + CK801->ICPR = (1 << (uint32_t)(IRQn)); +} + +/** + * @brief Read the active bit for an external interrupt + * + * @return always 0 + * + */ +__INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return (CK801->IABR & (1 << IRQn)); +} + +__INLINE uint32_t NVIC_GetActiveVector(void) +{ + unsigned int vectactive = 0; + //isr low 8bits gives the active vector + vectactive = (CK801 ->ISR & 0xff); + return vectactive; +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set ,the number rang: [0-3] + * + * Set the priority for the specified interrupt. The interrupt + * number must be positive to specify an external (device specific) + * interrupt. + */ +__INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + + uint32_t tmp = ((IRQn & 0x03) << 3); + uint8_t index = IRQn>>2; + if(IRQn >= 0) { + CK801->IPR[index] &= ~(0xff << tmp); + CK801->IPR[index] |= priority << (tmp+6); + } + +} +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number must be positive to specify an external (device specific) + * interrupt. + */ +__INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + uint32_t tmp = ((IRQn & 0x03) << 3); + uint8_t index = IRQn>>2; + return (uint32_t)(CK801->IPR[index])>>(tmp + 6); +} + + +/*###################################################################*/ +/*############# Threshold Enable & Set Threshold ###############*/ +/*###################################################################*/ + +/************************************************************ + * @brief enable NVIC threshold + * @name: NVIC_EnableThreshold + * @no param + * + */ + +__INLINE void NVIC_EnableThreshold(void) +{ + CK801 ->IPTR |= 0x80000000; +} + +/************************************************************ + * @brief disnable NVIC threshold + * @name: NVIC_DisableThreshold + * @no param + * + */ + +__INLINE void NVIC_DisableThreshold(void) +{ + CK801 ->IPTR &= ~0x80000000; +} + + +/************************************************************ + * @brief set NVIC Priothreshold + * @name: NVIC_SetPrioThreshold + * @param prioshreshold the priority of threshold[0,3] + * + */ + +__INLINE void NVIC_SetPrioThreshold(uint8_t prioshreshold) +{ + CK801 -> IPTR &= 0xffffff00; + CK801 -> IPTR |= (prioshreshold << 6); +} + +/************************************************************ + * @brief set NVIC Vectthreshold + * @name: NVIC_SetVectThreshold + * @param vectthreshold the vector of threshold[0,31] + * + */ + +__INLINE void NVIC_SetVectThreshold(uint8_t vectthreshold) +{ + CK801 -> IPTR &= 0xffff00ff; + CK801 -> IPTR |= ((vectthreshold + 32) << 8); +} + + +/*###################################################################*/ +/*################ Low Power Wakeup Enable ###################*/ +/*###################################################################*/ + +/************************************************************* + * @name: NVIC_PowerWakeUp_Enable + * @brief: enable the bit for Power wake up + * @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn + */ +__INLINE void NVIC_PowerWakeUp_Enable(IRQn_Type irqn) +{ + CK801->IWER |= (1 << irqn); +} + +/************************************************************* + * @name: NVIC_PowerWakeUp_Disable + * @func: disable the bit for Power wake up + * @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn + */ +__INLINE void NVIC_PowerWakeUp_Disable(IRQn_Type irqn) +{ + CK801->IWDR |= (1 << irqn); +} + +/************************************************************* + * @name: NVIC_PowerWakeUp_EnableAll + * @func: enable all bits for Power wake up + * @param: none + */ +__INLINE void NVIC_PowerWakeUp_EnableAll(void) +{ + CK801->IWER = 0xffffffff; +} + +/************************************************************* + * @name: NVIC_PowerWakeUp_EnableAll + * @func: disable all bits for Power wake up + * @param: none + */ +__INLINE void NVIC_PowerWakeUp_DisableAll(void) +{ + CK801->IWDR = 0xffffffff; +} + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102.h b/Source/include/apt32f102.h new file mode 100644 index 0000000..05a3ad0 --- /dev/null +++ b/Source/include/apt32f102.h @@ -0,0 +1,774 @@ +/* + ****************************************************************************** + * @file apt32f102_initial.c + * @author APT AE Team + * @version V1.08 + * @date 2018/11/01 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_H +#define _apt32f102_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102_types_local.h" +#include "apt32f102_ck801.h" + +/** +@brief CK801 bits Structure +*/ +typedef struct { + volatile unsigned int ReservedA[4]; //0xE000E000 + volatile unsigned int CORET_CSR; //0xE000E010 + volatile unsigned int CORET_RVR; //0xE000E014 + volatile unsigned int CORET_CVR; //0xE000E018 + volatile unsigned int CORET_CALIB; //0xE000E01C + volatile unsigned int ReservedB[56]; //0xE000E020 + volatile unsigned int ISER; //0xE000E100 + volatile unsigned int ReservedC[15]; // + volatile unsigned int IWER; //0xE000E140 + volatile unsigned int ReservedD[15]; // + volatile unsigned int ICER; //0xE000E180 + volatile unsigned int ReservedE[15]; // + volatile unsigned int IWDR; //0xE000E1C0 + volatile unsigned int ReservedF[15]; // + volatile unsigned int ISPR; //0xE000E200 + volatile unsigned int ReservedG[31]; // + volatile unsigned int ICPR; //0xE000E280 + volatile unsigned int ReservedH[31]; // + volatile unsigned int IABR; //0xE000E300 + volatile unsigned int ReservedI[63]; // + volatile unsigned int IPR[8]; //0xE000E400 ~ 0xE000E41C + volatile unsigned int ReservedJ[504]; // + volatile unsigned int ISR; //0xE000EC00 + volatile unsigned int IPTR; //0xE000EC04 +} CSP_CK801_T; +/** +@brief IFC bits Structure +*/ +typedef volatile struct { + volatile unsigned int IDR ; + volatile unsigned int CEDR ; + volatile unsigned int SRR ; + volatile unsigned int CMR ; + volatile unsigned int CR ; + volatile unsigned int MR ; + volatile unsigned int FM_ADDR ; + volatile unsigned int Reserved ; + volatile unsigned int KR ; + volatile unsigned int IMCR ; + volatile unsigned int RISR ; + volatile unsigned int MISR ; + volatile unsigned int ICR ; +} CSP_IFC_T ; +/** +@brief SYSCON bits Structure +*/ +typedef volatile struct { /*!< SYSCON Structure */ + volatile unsigned int IDCCR; /*!< 0x000: Identification & System Controller Clock Control Register */ + volatile unsigned int GCER; /*!< 0x004: System Controller General Control Enable Register */ + volatile unsigned int GCDR; /*!< 0x008: System Controller General Control Disable Register */ + volatile unsigned int GCSR; /*!< 0x00C: System Controller General Control Status Register */ + volatile unsigned int CKST; /*!< 0x010*/ + volatile unsigned int RAMCHK; /*!< 0x014*/ + volatile unsigned int EFLCHK; /*!< 0x018*/ + volatile unsigned int SCLKCR; /*!< 0x01C: System Controller System Clock Selection & Division Register */ + volatile unsigned int PCLKCR; /*!< 0x020: System Controller Peripheral Clock Selection & Division Register */ + volatile unsigned int _RSVD0; /*!< 0x024*/ + volatile unsigned int PCER0; /*!< 0x028: System Controller Peripheral Clock Enable Register */ + volatile unsigned int PCDR0; /*!< 0x02C: System Controller Peripheral Clock Disable Register */ + volatile unsigned int PCSR0; /*!< 0x030: System Controller Peripheral Clock Status Register */ + volatile unsigned int PCER1; /*!< 0x034: System Controller Peripheral Clock Enable Register */ + volatile unsigned int PCDR1; /*!< 0x038: System Controller Peripheral Clock Disable Register */ + volatile unsigned int PCSR1; /*!< 0x03C: System Controller Peripheral Clock Status Register */ + volatile unsigned int OSTR; /*!< 0x040: System Controller External OSC Stable Time Control Register */ + volatile unsigned int _RSVD1; /*!< 0x044: System Controller PLL Stable Time Control Register */ + volatile unsigned int _RSVD2; /*!< 0x048: System Controller PLL PMS Value Control Register */ + volatile unsigned int LVDCR; /*!< 0x04C: System Controller LVD Control Register */ + volatile unsigned int CLCR; /*!< 0x050: System Controller IMOSC Fine Adjustment Register*/ + volatile unsigned int PWRCR; /*!< 0x054: System Controller Power Control Register */ + volatile unsigned int PWRKEY; /*!< 0x058: System Controller Power Control Register */ + volatile unsigned int _RSVD3; /*!< 0x05C: */ + volatile unsigned int _RSVD4; /*!< 0x060: */ + volatile unsigned int OPT1; /*!< 0x064: System Controller OSC Trim Control Register */ + volatile unsigned int OPT0; /*!< 0x068: System Controller Protection Control Register */ + volatile unsigned int WKCR; /*!< 0x06C: System Controller Clock Quality Check Control Register */ + volatile unsigned int _RSVD5; /*!< 0x070: System Controller Clock Quality Check Control Register */ + volatile unsigned int IMER; /*!< 0x074: System Controller Interrupt Enable Register */ + volatile unsigned int IMDR; /*!< 0x078: System Controller Interrupt Disable Register */ + volatile unsigned int IMCR; /*!< 0x07C: System Controller Interrupt Mask Register */ + volatile unsigned int IAR; /*!< 0x080: System Controller Interrupt Active Register */ + volatile unsigned int ICR; /*!< 0x084: System Controller Clear Status Register */ + volatile unsigned int RISR; /*!< 0x088: System Controller Raw Interrupt Status Register */ + volatile unsigned int MISR; /*!< 0x08C: System Controller Raw Interrupt Status Register */ + volatile unsigned int RSR; /*!< 0x090: System Controller Raw Interrupt Status Register */ + volatile unsigned int EXIRT; /*!< 0x094: System Controller Reset Status Register */ + volatile unsigned int EXIFT; /*!< 0x098: System Controller External Interrupt Mode 1 (Positive Edge) Register */ + volatile unsigned int EXIER; /*!< 0x09C: System Controller External Interrupt Mode 2 (Negative Edge) Register */ + volatile unsigned int EXIDR; /*!< 0x0A0: System Controller External Interrupt Enable Register */ + volatile unsigned int EXIMR; /*!< 0x0A4: System Controller External Interrupt Disable Register */ + volatile unsigned int EXIAR; /*!< 0x0A8: System Controller External Interrupt Mask Register */ + volatile unsigned int EXICR; /*!< 0x0AC: System Controller External Interrupt Active Register */ + volatile unsigned int EXIRS; /*!< 0x0B0: System Controller External Interrupt Clear Status Register */ + volatile unsigned int IWDCR; /*!< 0x0B4: System Controller Independent Watchdog Control Register */ + volatile unsigned int IWDCNT; /*!< 0x0B8: SystCem Controller Independent Watchdog Counter Value Register */ + volatile unsigned int IWDEDR; /*!< 0x0BC: System Controller Independent Watchdog Enable/disable Register*/ + volatile unsigned int IOMAP0; /*!< 0x0C0: Customer Information Content mirror of 1st byte*/ + volatile unsigned int IOMAP1; /*!< 0x0C4: Customer Information Content mirror of 1st byte*/ + volatile unsigned int CINF0; /*!< 0x0C8: Customer Information Content mirror of 1st byte*/ + volatile unsigned int CINF1; /*!< 0x0CC: Customer Information Content mirror of 1st byte*/ + volatile unsigned int FINF0; /*!< 0x0D0: Customer Information Content mirror of 1st byte*/ + volatile unsigned int FINF1; /*!< 0x0D4: Customer Information Content mirror of 1st byte*/ + volatile unsigned int FINF2; /*!< 0x0D8: Customer Information Content mirror of 1st byte*/ + volatile unsigned int _RSVD6; /*!< 0x0DC: Customer Information Content mirror of 1st byte*/ + volatile unsigned int ERRINF; /*!< 0x0E0:*/ + volatile unsigned int UID0 ; /*!< 0x0E4: Customer Information Content mirror of 1st byte*/ + volatile unsigned int UID1 ; /*!< 0x0E8: Customer Information Content mirror of 1st byte*/ + volatile unsigned int UID2 ; /*!< 0x0EC: Customer Information Content mirror of 1st byte*/ + volatile unsigned int PWROPT; /*!< 0x0F0: Power recovery timmming control */ + volatile unsigned int EVTRG; /*!< 0x0F4: Trigger gen */ + volatile unsigned int EVPS; /*!< 0x0F8: Trigger prs */ + volatile unsigned int EVSWF; /*!< 0x0FC: Trigger software force */ + volatile unsigned int UREG0; /*!< 0x100: User defined reg0 */ + volatile unsigned int UREG1; /*!< 0x104: User defined reg1 */ + volatile unsigned int UREG2; /*!< 0x108: User defined reg0 */ + volatile unsigned int UREG3; /*!< 0x10C: User defined reg1 */ +} CSP_SYSCON_T; +/** +@brief ETCB bits Structure +*/ + typedef volatile struct + { + volatile unsigned int EN; /* ETCB Enable */ + volatile unsigned int SWTRG; /* ETCB Software Trigger Generator */ + volatile unsigned int CH0CON0; /* ETCB Channel 0 Control Register 0 */ + volatile unsigned int CH0CON1; /* ETCB Channel 0 Control Register 1 */ + volatile unsigned int CH1CON0; /* ETCB Channel 1 Control Register 0 */ + volatile unsigned int CH1CON1; /* ETCB Channel 1 Control Register 1 */ + volatile unsigned int CH2CON0; /* ETCB Channel 2 Control Register 0 */ + volatile unsigned int CH2CON1; /* ETCB Channel 2 Control Register 1 */ + volatile unsigned int _RSVD0; + volatile unsigned int _RSVD1; + volatile unsigned int _RSVD2; + volatile unsigned int _RSVD3; + volatile unsigned int CH3CON; /* ETCB Channel 3 Control Register */ + volatile unsigned int CH4CON; /* ETCB Channel 3 Control Register */ + volatile unsigned int CH5CON; /* ETCB Channel 3 Control Register */ + volatile unsigned int CH6CON; /* ETCB Channel 3 Control Register */ + volatile unsigned int CH7CON; /* ETCB Channel 3 Control Register */ + } CSP_ETCB_T, *CSP_ETCB_PTR; +/** +@brief TKEY bits Structure +*/ +typedef volatile struct +{ + volatile unsigned int TCH_CCR; /* Control Register */ + volatile unsigned int TCH_CON0; /* Control Register */ + volatile unsigned int TCH_CON1; /* Control Register */ + volatile unsigned int TCH_SCCR; /* Hardmacro control */ + volatile unsigned int TCH_SENPRD; /* Sensing target value */ + volatile unsigned int TCH_VALBUF; /* Reference value capture value*/ + volatile unsigned int TCH_SENCNT; /* Sensing counter value*/ + volatile unsigned int TCH_TCHCNT; /* Reference counter value*/ + volatile unsigned int TCH_THR; /* Match Status */ + volatile unsigned int Reserved0; + volatile unsigned int TCH_RISR; /* Interrupt Enable */ + volatile unsigned int TCH_IER; /* Interrupt Clear */ + volatile unsigned int TCH_ICR; /* Sensing target value */ + volatile unsigned int TCH_RWSR; /* Reference value capture value*/ + volatile unsigned int TCH_OVW_THR; /* Sensing counter value*/ + volatile unsigned int TCH_OVF; /* Reference counter value*/ + volatile unsigned int TCH_OVT; /* Match Status */ + volatile unsigned int TCH_SYNCR; /* Interrupt Enable */ + volatile unsigned int TCH_EVTRG; /* Interrupt Clear */ + volatile unsigned int TCH_EVPS; /* Sensing target value */ + volatile unsigned int TCH_EVSWF; /* Reference value capture value*/ +} CSP_TKEY_T, *CSP_TKEY_PTR; +/** +@brief TKEY advance bits Structure +*/ +typedef volatile struct +{ + volatile unsigned int TCH_CHVAL[18]; /* Reference value capture value */ + volatile unsigned int TCH_SEQCON[18]; /* SEQ Hardmacro control */ +} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR; +/** +@brief ADC0 bits Structure +*/ + typedef volatile struct + { + volatile unsigned int ECR; /**< Clock Enable Register */ + volatile unsigned int DCR; /**< Clock Disable Register */ + volatile unsigned int PMSR; /**< Power Management Status Register */ + volatile unsigned int Reserved0; + volatile unsigned int CR; /**< Control Register */ + volatile unsigned int MR; /**< Mode Register */ + volatile unsigned int SHR; + volatile unsigned int CSR; /**< Clear Status Register */ + volatile unsigned int SR; /**< Status Register */ + volatile unsigned int IER; /**< Interrupt Enable Register */ + volatile unsigned int IDR; /**< Interrupt Disable Register */ + volatile unsigned int IMR; /**< Interrupt Mask Register */ + volatile unsigned int SEQ[16]; /**< Conversion Mode Register 0~11 */ + volatile unsigned int PRI; /**< Conversion Priority Register */ + volatile unsigned int TDL0; /**< Trigger Delay control Register */ + volatile unsigned int TDL1; /**< Trigger Delay control Register */ + volatile unsigned int SYNCR; /**< Sync Control Register */ + volatile unsigned int Reserved1; /**< Trigger Filter Control Register */ + volatile unsigned int Reserved2; /**< Trigger Filter Window Register */ + volatile unsigned int EVTRG; /**< Event Trigger Control Register */ + volatile unsigned int EVPS; /**< Event Prescale Register */ + volatile unsigned int EVSWF; /**< Event Softtrig Register */ + volatile unsigned int ReservedD[27]; + volatile unsigned int DR[16]; /**< Convert Data Register */ + volatile unsigned int CMP0; /**< Comparison Data Register */ + volatile unsigned int CMP1; /**< Comparison Data Register */ + volatile unsigned int DRMASK; + } CSP_ADC12_T, *CSP_ADC12_PTR; +/** +@brief GPIOX bits Structure +*/ + typedef volatile struct + { + volatile unsigned int CONLR; /**< Control Low Register */ + volatile unsigned int CONHR; /**< Control High Register */ + volatile unsigned int WODR; /**< Write Output Data Register */ + volatile unsigned int SODR; /**< Set Output Data (bit-wise) Register */ + volatile unsigned int CODR; /**< Clear Output Data (bit-wise) Register*/ + volatile unsigned int ODSR; /**< Output Data Status Register */ + volatile unsigned int PSDR; /**< Pin Data Status Register */ + volatile unsigned int FLTEN; + volatile unsigned int PUDR; /**< IO Pullup_Pulldown Register */ + volatile unsigned int DSCR; /**< Output Driving Strength Register */ + volatile unsigned int OMCR; /**< Slew-rate, Open-Drain Control */ + volatile unsigned int IECR; /**< EXI enable control */ + volatile unsigned int IEER; + volatile unsigned int IEDR; + } CSP_GPIO_T, *CSP_GPIO_PTR; + + typedef volatile struct + { + volatile unsigned int IGRPL; /**< EXI group control */ + volatile unsigned int IGRPH; /**< EXI group control */ + volatile unsigned int IGREX; + volatile unsigned int IO_CLKEN; + } CSP_IGRP_T, *CSP_IGRP_PTR; +/** +@brief UART0~UART1 bits Structure +*/ + typedef volatile struct + { + volatile unsigned int DATA; /**< Write and Read Data Register */ + volatile unsigned int SR; /**< Status Register */ + volatile unsigned int CTRL; /**< Control Register */ + volatile unsigned int ISR; /**< Interrupt Status Register */ + volatile unsigned int BRDIV; /**< Baud Rate Generator Register */ + volatile unsigned int ReservedA[20]; + } CSP_UART_T, *CSP_UART_PTR; +/** +@brief SPI0 bits Structure +*/ +typedef struct +{ + volatile unsigned int CR0; /**< Control Register 0 */ + volatile unsigned int CR1; /**< Control Register 1 */ + volatile unsigned int DR; /**< Receive FIFO(read) and transmit FIFO data register(write) */ + volatile unsigned int SR; /**< Status register */ + volatile unsigned int CPSR; /**< Clock prescale register */ + volatile unsigned int IMSCR; /**< Interrupt mask set and clear register */ + volatile unsigned int RISR; /**< Raw interrupt status register */ + volatile unsigned int MISR; /**< Masked interrupt status register */ + volatile unsigned int ICR; /**< Interrupt clear register */ +} CSP_SSP_T, *CSP_SSP_PTR; +/** +@brief SIO0 bits Structure +*/ +typedef struct +{ + volatile unsigned int CR; + volatile unsigned int TXCR0; + volatile unsigned int TXCR1; + volatile unsigned int TXBUF; + volatile unsigned int RXCR0; + volatile unsigned int RXCR1; + volatile unsigned int RXCR2; + volatile unsigned int RXBUF; + volatile unsigned int RISR; + volatile unsigned int MISR; + volatile unsigned int IMCR; + volatile unsigned int ICR; +} CSP_SIO_T, *CSP_SIO_PTR; +/** +@brief I2C0 bits Structure +*/ + typedef volatile struct + { + unsigned int CR; /* I2C Control */ + unsigned int TADDR; /* I2C Target Address */ + unsigned int SADDR; /* I2C Slave Address */ + unsigned int ReservedD; + unsigned int DATA_CMD; /* I2C Rx/Tx Data Buffer and Command */ + unsigned int SS_SCLH; /* I2C Standard Speed SCL High Count */ + unsigned int SS_SCLL; /* I2C Standard Speed SCL Low Count */ + unsigned int FS_SCLH; /* I2C Fast mode and Fast Plus SCL High Count*/ + unsigned int FS_SCLL; /* I2C Fast mode and Fast Plus SCL Low Count*/ + unsigned int ReservedA; /* I2C High Speed SCL High Count */ + unsigned int ReservedC; /* I2C High Speed SCL Low Count */ + unsigned int RX_FLSEL; /* I2C Receive FIFO Threshold */ + unsigned int TX_FLSEL; /* I2C Transmit FIFO Threshold */ + unsigned int RX_FL; /* I2C Receive FIFO Level */ + unsigned int TX_FL; /* I2C Transmit FIFO Level */ + unsigned int ENABLE; /* I2C Enable */ + unsigned int STATUS; /* I2C Status */ + unsigned int ReservedB; /* I2C Enable Status */ + unsigned int SDA_TSETUP; /* I2C SDA Setup Time */ + unsigned int SDA_THOLD; /* I2C SDA hold time length */ + unsigned int SPKLEN; /* I2C SS and FS Spike Suppression Limit */ + //unsigned int HS_SPKLEN; /* I2C HS Spike Suppression Limit */ + unsigned int ReservedE; + unsigned int MISR; /* I2C Masked Interrupt Status */ + unsigned int IMSCR; /* I2C Interrupt Enable */ + unsigned int RISR; /* I2C Raw Interrupt Status */ + unsigned int ICR; /* I2C Interrupt Clear */ + unsigned int ReservedF; + unsigned int SCL_TOUT; /* I2C SCL Stuck at Low Timeout */ + unsigned int SDA_TOUT; /* I2C SDA Stuck at Low Timeout */ + unsigned int TX_ABRT; /* I2C Transmit Abort Status */ + unsigned int GCALL; /* I2C ACK General Call */ + unsigned int NACK; /* I2C Generate SLV_DATA_NACK */ + } CSP_I2C_T, *CSP_I2C_PTR; +/** +@brief CA0 bits Structure +*/ + typedef struct + { + volatile unsigned int CADATAH; /**< DATA High Register */ + volatile unsigned int CADATAL; /**< DATA Low Register */ + volatile unsigned int CACON; /**< Control Register */ + volatile unsigned int INTMASK; /**< Interrupt Mask CR */ + } CSP_CA_T, *CSP_CA_PTR; +/** +@brief GPTX bits Structure +*/ + typedef struct + { + volatile unsigned int CEDR; //0x0000 Clock control & ID + volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl + volatile unsigned int PSCR; //0x0008 Clock prescaler + volatile unsigned int CR; //0x000C Control register + volatile unsigned int SYNCR; //0x0010 Synchronization control reg + volatile unsigned int GLDCR; //0x0014 Global load control reg + volatile unsigned int GLDCFG; //0x0018 Global load config + volatile unsigned int GLDCR2; //0x001C Global load control reg2 + volatile unsigned int Reserved0; //0x0020 + volatile unsigned int PRDR; //0x0024 Period reg + volatile unsigned int Reserved1; //0x0028 + volatile unsigned int CMPA; //0x002C Compare Value A + volatile unsigned int CMPB; //0x0030 Compare Value B + volatile unsigned int Reserved2; //0x0034 + volatile unsigned int Reserved3; //0x0038 + volatile unsigned int CMPLDR; //0x003C Cmp reg load control + volatile unsigned int CNT; //0x0040 Counter reg + volatile unsigned int AQLDR; //0x0044 AQ reg load control + volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A + volatile unsigned int AQCRB; //0x004C Action qualify of ch-B + volatile unsigned int Reserved4; //0x0050 + volatile unsigned int Reserved5; //0x0054 + volatile unsigned int Reserved6; //0x0058 + volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing + volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing + volatile unsigned int Reserved7; //0x0064 + volatile unsigned int Reserved8; //0x0068 + volatile unsigned int Reserved9; //0x006c + volatile unsigned int Reserved10; //0x0070 + volatile unsigned int Reserved11; //0x0074 + volatile unsigned int Reserved12; //0x0078 + volatile unsigned int Reserved13; //0x007c + volatile unsigned int Reserved14; //0x0080 + volatile unsigned int Reserved15; //0x0084 + volatile unsigned int Reserved16; //0x0088 + volatile unsigned int Reserved17; //0x008c + volatile unsigned int Reserved18; //0x0090 + volatile unsigned int Reserved19; //0x0094 + volatile unsigned int Reserved20; //0x0098 + volatile unsigned int Reserved21; //0x009c + volatile unsigned int Reserved22; //0x00a0 + volatile unsigned int Reserved23; //0x00a4 + volatile unsigned int Reserved24; //0x00a8 + volatile unsigned int Reserved25; //0x00ac + volatile unsigned int Reserved26; //0x00b0 + volatile unsigned int Reserved27; //0x00b4 + volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg + volatile unsigned int TRGFTWR; //0x00BC Trigger filter window + volatile unsigned int EVTRG; //0x00C0 Event trigger setting + volatile unsigned int EVPS; //0x00C4 Event presaler + volatile unsigned int EVCNTINIT; //0x00C8 + volatile unsigned int EVSWF; //0x00CC Event software forcing + volatile unsigned int RISR; //0x00D0 Interrupt RISR + volatile unsigned int MISR; //0x00D4 Interrupt MISR + volatile unsigned int IMCR; //0x00D8 Interrupt IMCR + volatile unsigned int ICR; //0x00DC Interrupt clear + volatile unsigned int REGLINK; //0x00E0 Register link + + }CSP_GPT_T,*CSP_GPT_PTR; +/** +@brief EPT0 bits Structure +*/ + typedef struct + { + volatile unsigned int CEDR; //0x0000 Clock control & ID + volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl + volatile unsigned int PSCR; //0x0008 Clock prescaler + volatile unsigned int CR; //0x000C Control register + volatile unsigned int SYNCR; //0x0010 Synchronization control reg + volatile unsigned int GLDCR; //0x0014 Global load control reg + volatile unsigned int GLDCFG; //0x0018 Global load config + volatile unsigned int GLDCR2; //0x001C Global load control reg2 + volatile unsigned int HRCFG; //0x0020 + volatile unsigned int PRDR; //0x0024 Period reg + volatile unsigned int PHSR; //0x0028 Phase control reg + volatile unsigned int CMPA; //0x002C Compare Value A + volatile unsigned int CMPB; //0x0030 Compare Value B + volatile unsigned int CMPC; //0x0034 Compare Value C + volatile unsigned int CMPD; //0x0038 Compare Value D + volatile unsigned int CMPLDR; //0x003C Cmp reg load control + volatile unsigned int CNT; //0x0040 Counter reg + volatile unsigned int AQLDR; //0x0044 AQ reg load control + volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A + volatile unsigned int AQCRB; //0x004C Action qualify of ch-B + volatile unsigned int AQCRC; //0x0050 Action qualify of ch-C + volatile unsigned int AQCRD; //0x0054 Action qualify of ch-D + volatile unsigned int AQTSCR; //0x0058 T event selection + volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing + volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing + volatile unsigned int DBLDR; //0x0064 Deadband control reg load control + volatile unsigned int DBCR; //0x0068 Deadband control reg + volatile unsigned int DPSCR; //0x006C Deadband clock prescaler + volatile unsigned int DBDTR; //0x0070 Deadband rising delay control + volatile unsigned int DBDTF; //0x0074 Deadband falling delay control + volatile unsigned int CPCR; //0x0078 Chop control + volatile unsigned int EMSRC; //0x007C EM source setting + volatile unsigned int EMSRC2; //0x0080 EM source setting + volatile unsigned int EMPOL; //0x0084 EM polarity setting + volatile unsigned int EMECR; //0x0088 EM enable control + volatile unsigned int EMOSR; //0x008C EM trip out status setting + volatile unsigned int Reserved; //0x0090 Reserved + volatile unsigned int EMSLSR; //0x0094 Softlock status + volatile unsigned int EMSLCLR; //0x0098 Softlock clear + volatile unsigned int EMHLSR; //0x009C Hardlock status + volatile unsigned int EMHLCLR; //0x00A0 Hardlock clear + volatile unsigned int EMFRCR; //0x00A4 Software forcing EM + volatile unsigned int EMRISR; //0x00A8 EM RISR + volatile unsigned int EMMISR; //0x00AC EM MISR + volatile unsigned int EMIMCR; //0x00B0 EM masking enable + volatile unsigned int EMICR; //0x00B4 EM pending clear + volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg + volatile unsigned int TRGFTWR; //0x00BC Trigger filter window + volatile unsigned int EVTRG; //0x00C0 Event trigger setting + volatile unsigned int EVPS; //0x00C4 Event presaler + volatile unsigned int EVCNTINIT; //0x00C8 + volatile unsigned int EVSWF; //0x00CC Event software forcing + volatile unsigned int RISR; //0x00D0 Interrupt RISR + volatile unsigned int MISR; //0x00D4 Interrupt MISR + volatile unsigned int IMCR; //0x00D8 Interrupt IMCR + volatile unsigned int ICR; //0x00DC Interrupt clear + volatile unsigned int REGLINK; //0x00E0 Register link + volatile unsigned int REGLINK2; //0x00E4 Register link2 + volatile unsigned int REGPROT; //0x00E8 Register protection +} CSP_EPT_T, *CSP_EPT_PTR; +/** +@brief LPT bits Structure +*/ + typedef volatile struct + { + volatile unsigned int CEDR; //0x0000 Clock control & ID + volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl + volatile unsigned int PSCR; //0x0008 Clock prescaler + volatile unsigned int CR; //0x000C Control register + volatile unsigned int SYNCR; //0x0010 Synchronization control reg + volatile unsigned int PRDR; //0x0024 Period reg + volatile unsigned int CMP; //0x002C Compare Value A + volatile unsigned int CNT; //0x0040 Counter reg + volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg + volatile unsigned int TRGFTWR; //0x00BC Trigger filter window + volatile unsigned int EVTRG; //0x00C0 Event trigger setting + volatile unsigned int EVPS; //0x00C4 Event presaler + volatile unsigned int EVSWF; //0x00C8 Event software forcing + volatile unsigned int RISR; //0x00CC Interrupt RISR + volatile unsigned int MISR; //0x00D0 Interrupt MISR + volatile unsigned int IMCR; //0x00D4 Interrupt IMCR + volatile unsigned int ICR; //0x00D8 Interrupt clear +} CSP_LPT_T, *CSP_LPT_PTR; +/** +@brief BT0 bits Structure +*/ + typedef struct + { + volatile unsigned int RSSR; //0x0000 Reset/Start Control + volatile unsigned int CR; //0x0004 General Control + volatile unsigned int PSCR; //0x0008 Prescaler + volatile unsigned int PRDR; //0x000C Period + volatile unsigned int CMP; //0X0010 + volatile unsigned int CNT; //0x0014 Counter + volatile unsigned int EVTRG; //0x0018 Event Trigger + volatile unsigned int EVPS; //0x001C Event Prescaler + volatile unsigned int EVCNTINTI; //0x0020 Event Counter + volatile unsigned int EVSWF; //0x0024 Software force Event Trigger + volatile unsigned int RISR; //0x0028 + volatile unsigned int IMCR; //0x002C + volatile unsigned int MISR; //0x0030 + volatile unsigned int ICR; //0x0034 +} CSP_BT_T, *CSP_BT_PTR; +/** +@brief CRC bits Structure +*/ +typedef struct +{ + volatile unsigned int IDR; /**< ID Register */ + volatile unsigned int CEDR; /**< Clock Enable/Disable Register */ + volatile unsigned int SRR; /**< Software Reset Register */ + volatile unsigned int CR; /**< Control Register */ + volatile unsigned int SEED; /**< Seed Value Register */ + volatile unsigned int DATAIN; /**< Data in Value Register */ + volatile unsigned int DATAOUT; /**< Data out Value Register */ + // TBD... // +} CSP_CRC_T, *CSP_CRC_PTR; +/** +@brief RTC bits Structure +*/ + typedef struct + { + volatile unsigned int TIMR; //0x0000 Time Control Register + volatile unsigned int DATR; //0x0004 Date Control Register + volatile unsigned int CR; //0x0008 Control Register + volatile unsigned int CCR; //0x000C Clock Control register + volatile unsigned int ALRAR; //0x0010 Alarm A + volatile unsigned int ALRBR; //0x0014 Alarm B + volatile unsigned int SSR; //0x0018 Sub second + volatile unsigned int CAL; //0x001C Calibration + volatile unsigned int RISR; //0x0020 + volatile unsigned int IMCR; //0x0024 + volatile unsigned int MISR; //0x0028 + volatile unsigned int ICR; //0x002C + volatile unsigned int KEY; //0x0030 + volatile unsigned int EVTRG; //0x0034 + volatile unsigned int EVPS; //0x0038 + volatile unsigned int EVSWF; //0x003C +} CSP_RTC_T, *CSP_RTC_PTR; + +/** +@brief WWDT bits Structure +*/ + typedef struct + { + volatile unsigned int CR; + volatile unsigned int CFGR; + volatile unsigned int RISR; + volatile unsigned int MISR; + volatile unsigned int IMCR; + volatile unsigned int ICR; + }CSP_WWDT_T,*CSP_WWDT_PTR; +/** +@brief HWD bits Structure +*/ + typedef struct + { + volatile S32_T DIVIDENT; + volatile S32_T DIVISOR; + volatile S32_T QUOTIENT; + volatile S32_T REMAIN; + volatile unsigned int CR; + }CSP_HWD_T,*CSP_HWD_PTR; + + #define FLASHBase 0x00000000 + #define FLASHSize 0x00010000 + #define FLASHLimit (FLASHBase + FLASHSize) + #define DFLASHBase 0x10000000 + #define DFLASHSize 0x10001000 + #define DFLASHLimit (FLASHBase + FLASHSize) + +#ifdef REMAP + #define SRAMBase 0x00000000 + #define SRAMSize 0x00000800 + #define SRAMLimit (SRAMBase + SRAMSize) + #define MEMVectorBase 0x00000700 + #define MEMVectorSize (0x50<<2) +#else + #define SRAMBase 0x20000000 + #define SRAMSize 0x00001000 + #define SRAMLimit (SRAMBase + SRAMSize) + #define MEMVectorBase 0x20000F00 + #define MEMVectorSize (0x50<<2) +#endif + +//--Peripheral Address Setting +#define APBPeriBase 0x40000000 + +//--Each Peripheral Address Setting +//#define APB_SFMBase (APBPeriBase + 0x10000) +#define APB_IFCBase (APBPeriBase + 0x10000) +#define APB_SYSCONBase (APBPeriBase + 0x11000) +#define APB_ETCBBase (APBPeriBase + 0x12000) + +#define APB_TKEYBase (APBPeriBase + 0x20000) +#define APB_TKEYBUFBase (APBPeriBase + 0x21000) +#define APB_ADC0Base (APBPeriBase + 0x30000) + +#define AHBGPIOBase 0x60000000 +#define APB_GPIOA0Base (AHBGPIOBase + 0x0000) //A0 +#define APB_GPIOB0Base (AHBGPIOBase + 0x2000) //B0 +#define APB_IGRPBase (AHBGPIOBase + 0xF000) + +#define APB_BT1Base (APBPeriBase + 0x52000) +#define APB_BT0Base (APBPeriBase + 0x51000) +#define APB_CNTABase (APBPeriBase + 0x50000) + +#define APB_GPT0Base (APBPeriBase + 0x55000) + +#define APB_EPT0Base (APBPeriBase + 0x59000) + +#define APB_RTCBase (APBPeriBase + 0x60000) +#define APB_LPTBase (APBPeriBase + 0x61000) +#define APB_WWDTBase (APBPeriBase + 0x62000) + +#define APB_UART0Base (APBPeriBase + 0x80000) +#define APB_UART1Base (APBPeriBase + 0x81000) +#define APB_UART2Base (APBPeriBase + 0x82000) + +#define APB_SPI0Base (APBPeriBase + 0x90000) +#define APB_SIO0Base (APBPeriBase + 0xB0000) + +#define APB_I2C0Base (APBPeriBase + 0xA0000) + + + +#define AHB_CRCBase 0x50000000 +#define APB_HWDBase 0x70000000 + +//--Interrupt Bit Position +#define CORET_INT (0x01ul<<0) //IRQ0 +#define SYSCON_INT (0x01ul<<1) //IRQ1 +#define IFC_INT (0x01ul<<2) //IRQ2 +#define ADC_INT (0x01ul<<3) //IRQ3 +#define EPT0_INT (0x01ul<<4) //IRQ4 +//DUMMY //IRQ5 +#define WWDT_INT (0x01ul<<6) //IRQ6 +#define EXI0_INT (0x01ul<<7) //IRQ7 +#define EXI1_INT (0x01ul<<8) //IRQ8 +#define GPT0_INT (0x01ul<<9) //IRQ9 +//DUMMY //IRQ10 +//DUMMY //IRQ11 +#define RTC_INT (0x01ul<<12) //IRQ12 +#define UART0_INT (0x01ul<<13) //IRQ13 +#define UART1_INT (0x01ul<<14) //IRQ14 +#define UART2_INT (0x01ul<<15) //IRQ15 +//DUMMY //IRQ16 +#define I2C_INT (0x01ul<<17) //IRQ17 +//DUMMY //IRQ18 +#define SPI_INT (0x01ul<<19) //IRQ19 +#define SIO_INT (0x01ul<<20) //IRQ20 +#define EXI2_INT (0x01ul<<21) //IRQ21 +#define EXI3_INT (0x01ul<<22) //IRQ22 +#define EXI4_INT (0x01ul<<23) //IRQ23 +#define CA_INT (0x01ul<<24) //IRQ24 +#define TKEY_INT (0x01ul<<25) //IRQ25 +#define LPT_INT (0x01ul<<26) //IRQ26 +//DUMMY //IRQ27 +#define BT0_INT (0x01ul<<28) //IRQ28 +#define BT1_INT (0x01ul<<29) //IRQ29 +//DUMMY //IRQ30 +//DUMMY //IRQ31 + + +extern CSP_CK801_T *CK801 ; + +extern CSP_IFC_T *IFC ; +extern CSP_SYSCON_T *SYSCON ; +extern CSP_ETCB_T *ETCB ; + +extern CSP_TKEY_T *TKEY ; +extern CSP_TKEYBUF_T *TKEYBUF ; +extern CSP_ADC12_T *ADC0 ; + +extern CSP_GPIO_T *GPIOA0 ; +extern CSP_GPIO_T *GPIOB0 ; +extern CSP_IGRP_T *GPIOGRP ; + +extern CSP_UART_T *UART0 ; +extern CSP_UART_T *UART1 ; +extern CSP_UART_T *UART2 ; +extern CSP_SSP_T *SPI0 ; +extern CSP_SIO_T *SIO0 ; +extern CSP_I2C_T *I2C0 ; +extern CSP_CA_T *CA0 ; + +extern CSP_GPT_T *GPT0 ; + +extern CSP_EPT_T *EPT0 ; + +extern CSP_LPT_T *LPT ; +extern CSP_HWD_T *HWD ; +extern CSP_WWDT_T *WWDT ; +extern CSP_BT_T *BT0 ; +extern CSP_BT_T *BT1 ; + +extern CSP_CRC_T *CRC ; +extern CSP_RTC_T *RTC ; + +//ISR Define for generating special interrupt related ASM (CK802), with compile option -mistack +void MisalignedHandler(void) __attribute__((isr)); +void IllegalInstrHandler(void) __attribute__((isr)); +void AccessErrHandler(void) __attribute__((isr)); +void BreakPointHandler(void) __attribute__((isr)); +void UnrecExecpHandler(void) __attribute__((isr)); +void Trap0Handler(void) __attribute__((isr)); +void Trap1Handler(void) __attribute__((isr)); +void Trap2Handler(void) __attribute__((isr)); +void Trap3Handler(void) __attribute__((isr)); +void PendTrapHandler(void) __attribute__((isr)); + +void CORETHandler(void) __attribute__((isr)); +void SYSCONIntHandler(void) __attribute__((isr)); +void IFCIntHandler(void) __attribute__((isr)); +void ADCIntHandler(void) __attribute__((isr)); +void EPT0IntHandler(void) __attribute__((isr)); +void WWDTHandler(void) __attribute__((isr)); +void EXI0IntHandler(void) __attribute__((isr)); +void EXI1IntHandler(void) __attribute__((isr)); +void EXI2to3IntHandler(void) __attribute__((isr)); +void EXI4to9IntHandler(void) __attribute__((isr)); +void EXI10to15IntHandler(void) __attribute__((isr)); +void UART0IntHandler(void) __attribute__((isr)); +void UART1IntHandler(void) __attribute__((isr)); +void UART2IntHandler(void) __attribute__((isr)); +void I2CIntHandler(void) __attribute__((isr)); +void GPT0IntHandler(void) __attribute__((isr)); +void LEDIntHandler(void) __attribute__((isr)); +void TKEYIntHandler(void) __attribute__((isr)); +void SPI0IntHandler(void) __attribute__((isr)); +void SIO0IntHandler(void) __attribute__((isr)); +void CNTAIntHandler(void) __attribute__((isr)); +void RTCIntHandler(void) __attribute__((isr)); +void LPTIntHandler(void) __attribute__((isr)); +void BT0IntHandler(void) __attribute__((isr)); +void BT1IntHandler(void) __attribute__((isr)); + +extern int __divsi3 (int a, int b); +extern unsigned int __udivsi3 (unsigned int a, unsigned int b); +extern int __modsi3 (int a, int b); +extern unsigned int __umodsi3 (unsigned int a, unsigned int b); +extern void delay_nms(unsigned int t); +extern void delay_nus(unsigned int t); + +#endif + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_adc.h b/Source/include/apt32f102_adc.h new file mode 100644 index 0000000..97896bf --- /dev/null +++ b/Source/include/apt32f102_adc.h @@ -0,0 +1,236 @@ +/* + ****************************************************************************** + * @file apt32f102_adc.h + * @author APT AE Team + * @version V1.13 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_adc_H +#define _apt32f102_adc_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +/****************************************************************************** +************************* ADC12 Registers reset value ************************ +******************************************************************************/ + #define ADC_ECR_RST (0x00000000ul) /**< ECR reset value */ + #define ADC_DCR_RST (0x00000000ul) /**< DCR reset value */ + #define ADC_PMSR_RST (0x00000000ul) /**< PMSR reset value */ + #define ADC_CR_RST (0x80000000ul) /**< CR reset value */ + #define ADC_MR_RST (0x00000000ul) /**< MR reset value */ + #define ADC_CSR_RST (0x00000000ul) /**< CSR reset value */ + #define ADC_SR_RST (0x00000000ul) /**< SR reset value */ + #define ADC_IER_RST (0x00000000ul) /**< IER reset value */ + #define ADC_IDR_RST (0x00000000ul) /**< IDR reset value */ + #define ADC_IMR_RST (0x00000000ul) /**< IMR reset value */ + #define ADC_SEQx_RST (0x00000000ul) /**< SEQx reset value */ + #define ADC_DR_RST (0x00000000ul) /**< DR reset value */ + #define ADC_CMP0_RST (0x00000000ul) /**< CMP0 reset value */ + #define ADC_CMP1_RST (0x00000000ul) /**< CMP1 reset value */ +/** + * @brief ADC12 Control register + */ +typedef enum +{ + ADC12_SWRST = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Software Reset */ + ADC12_ADCEN = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Enable */ + ADC12_ADCDIS = ((CSP_REGISTER_T)(0x01ul << 2)), /**< ADC Disable */ + ADC12_START = ((CSP_REGISTER_T)(0x01ul << 3)), /**< Start Conversion */ + ADC12_STOP = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Stop Conversion */ + ADC12_SWTRG = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Stop Conversion */ + ADC12_AVGEN = ((CSP_REGISTER_T)(0x01ul << 12)), /**< Conversion data get average */ + ADC12_AVGDIS = ((CSP_REGISTER_T)(0x00ul << 12)), /**< Conversion data get last one */ +}ADC12_Control_TypeDef; +/** + * @brief ADC12 IMR register + */ +typedef enum +{ + //CSR SR, IER, IDR, IMR Registers + ADC12_EOC = ((CSP_REGISTER_T)(0x01ul << 0)), /**< End Of Conversion */ + ADC12_READY = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Ready to Start */ + ADC12_OVR = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Over Run */ + ADC12_CMP0H = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Higher than CMP1 */ + ADC12_CMP0L = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Lower than CMP1 */ + ADC12_CMP1H = ((CSP_REGISTER_T)(0x01ul << 6)), /**< Higher than CMP2 */ + ADC12_CMP1L = ((CSP_REGISTER_T)(0x01ul << 7)), /**< Lower than CMP2 */ + ADC12_SEQ_END0 = ((CSP_REGISTER_T)(0x01ul << 16)), /**< SEQ0 Convert end */ + ADC12_SEQ_END1 = ((CSP_REGISTER_T)(0x01ul << 17)), /**< SEQ1 Convert end */ + ADC12_SEQ_END2 = ((CSP_REGISTER_T)(0x01ul << 18)), /**< SEQ2 Convert end */ + ADC12_SEQ_END3 = ((CSP_REGISTER_T)(0x01ul << 19)), /**< SEQ3 Convert end */ + ADC12_SEQ_END4 = ((CSP_REGISTER_T)(0x01ul << 20)), /**< SEQ4 Convert end */ + ADC12_SEQ_END5 = ((CSP_REGISTER_T)(0x01ul << 21)), /**< SEQ5 Convert end */ + ADC12_SEQ_END6 = ((CSP_REGISTER_T)(0x01ul << 22)), /**< SEQ6 Convert end */ + ADC12_SEQ_END7 = ((CSP_REGISTER_T)(0x01ul << 23)), /**< SEQ7 Convert end */ + ADC12_SEQ_END8 = ((CSP_REGISTER_T)(0x01ul << 24)), /**< SEQ8 Convert end */ + ADC12_SEQ_END9 = ((CSP_REGISTER_T)(0x01ul << 25)), /**< SEQ9 Convert end */ + ADC12_SEQ_END10 = ((CSP_REGISTER_T)(0x01ul << 26)), /**< SEQ10 Convert end */ + ADC12_SEQ_END11 = ((CSP_REGISTER_T)(0x01ul << 27)), /**< SEQ11 Convert end */ + ADC12_SEQ_END12 = ((CSP_REGISTER_T)(0x01ul << 28)), /**< SEQ12 Convert end */ + ADC12_SEQ_END13 = ((CSP_REGISTER_T)(0x01ul << 29)), /**< SEQ13 Convert end */ + ADC12_SEQ_END14 = ((CSP_REGISTER_T)(0x01ul << 30)), /**< SEQ14 Convert end */ + ADC12_SEQ_END15 = ((CSP_REGISTER_T)(0x01ul << 31)), /**< SEQ15 Convert end */ + /* SR Register Only */ + ADC12_ADCENS = ((CSP_REGISTER_T)(0x01ul << 8)), /**< ADC Enable Status */ + ADC12_CTCVS = ((CSP_REGISTER_T)(0x01ul << 9)) /**< Continuous Conversion Status*/ +} +ADC12_IMR_TypeDef; +/** + * @brief ADC12 CLK ENABLE AND DISABLE + */ +typedef enum +{ + ADC_CLK_CR = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Clock */ + ADC12_IPIDCODE_MASK = ((CSP_REGISTER_T)(0x3FFFFFFul << 4)), /**< ADC IPIDCODE mask */ + ADC_DEBUG_MODE = ((CSP_REGISTER_T)(0x01ul << 31)) /**< Debug Mode Enable */ +} +ADC12_CLK_TypeDef; +/** + * @brief ADC12 Bit slection + */ +typedef enum +{ + ADC12_12BIT = 1, /**< 12bit mode */ + ADC12_10BIT = 0, /**< 10bit mode */ + ADC12_10BITor12BIT = ((CSP_REGISTER_T)(0x01ul<<31)) +}ADC12_10bitor12bit_TypeDef; +/** + * @brief ADC12 Convertion mode + */ +typedef enum +{ + One_shot_mode = 0, + Continuous_mode = 1, + CONTCV = (CSP_REGISTER_T)0x01<<31 //Continuous Conversion 0: One shot mode. 1: Continuous mode. +}ADC12_ConverMode_TypeDef; +/** + * @brief ADC12 NBRCMPx selection + */ +typedef enum +{ + NBRCMP0_TypeDef = 0, + NBRCMP1_TypeDef = 1 +} +ADC12_NBRCMPx_TypeDef; +/** + * @brief ADC12 NBRCMPx_HorL selection + */ +typedef enum +{ + NBRCMPX_L_TypeDef = 0, + NBRCMPX_H_TypeDef = 1 +} +ADC12_NBRCMPx_HorL_TypeDef; +/** + * @brief ADC12 SEQx register + */ +typedef enum +{ + ADC12_ADCIN0 = (CSP_REGISTER_T)(0x0ul), /**< ADC Analog Input 0 */ + ADC12_ADCIN1 = (CSP_REGISTER_T)(0x1ul), /**< ADC Analog Input 1 */ + ADC12_ADCIN2 = (CSP_REGISTER_T)(0x2ul), /**< ADC Analog Input 2 */ + ADC12_ADCIN3 = (CSP_REGISTER_T)(0x3ul), /**< ADC Analog Input 3 */ + ADC12_ADCIN4 = (CSP_REGISTER_T)(0x4ul), /**< ADC Analog Input 4 */ + ADC12_ADCIN5 = (CSP_REGISTER_T)(0x5ul), /**< ADC Analog Input 5 */ + ADC12_ADCIN6 = (CSP_REGISTER_T)(0x6ul), /**< ADC Analog Input 6 */ + ADC12_ADCIN7 = (CSP_REGISTER_T)(0x7ul), /**< ADC Analog Input 7 */ + ADC12_ADCIN8 = (CSP_REGISTER_T)(0x8ul), /**< ADC Analog Input 8 */ + ADC12_ADCIN9 = (CSP_REGISTER_T)(0x9ul), /**< ADC Analog Input 9 */ + ADC12_ADCIN10 = (CSP_REGISTER_T)(0x0Aul), /**< ADC Analog Input 10 */ + ADC12_ADCIN11 = (CSP_REGISTER_T)(0x0Bul), /**< ADC Analog Input 11 */ + ADC12_ADCIN12 = (CSP_REGISTER_T)(0x0Cul), /**< ADC Analog Input 12 */ + ADC12_ADCIN13 = (CSP_REGISTER_T)(0x0Dul), /**< ADC Analog Input 13 */ + ADC12_ADCIN14 = (CSP_REGISTER_T)(0x0Eul), /**< ADC Analog Input 14 */ + ADC12_ADCIN15 = (CSP_REGISTER_T)(0x0Ful), /**< ADC Analog Input 15 */ + //ADC12_ADCIN16 = (CSP_REGISTER_T)(0x10ul), /**< ADC Analog Input 16 */ + //ADC12_ADCIN17 = (CSP_REGISTER_T)(0x11ul), /**< ADC Analog Input 17 */ + //ADC12_ADCIN18 = (CSP_REGISTER_T)(0x12ul), /**< ADC Analog Input 18 */ + //ADC12_ADCIN19 = (CSP_REGISTER_T)(0x13ul), /**< ADC Analog Input 19 */ + //ADC12_ADCIN20 = (CSP_REGISTER_T)(0x14ul), /**< ADC Analog Input 20 */ + //ADC12_ADCIN21 = (CSP_REGISTER_T)(0x15ul), /**< ADC Analog Input 21 */ + //ADC12_ADCIN22 = (CSP_REGISTER_T)(0x16ul), /**< ADC Analog Input 22 */ + //ADC12_ADCIN23 = (CSP_REGISTER_T)(0x17ul), /**< ADC Analog Input 23 */ + //ADC12_ADCIN24 = (CSP_REGISTER_T)(0x18ul), /**< ADC Analog Input 24 */ + //ADC12_ADCIN25 = (CSP_REGISTER_T)(0x19ul), /**< ADC Analog Input 25 */ + //ADC12_ADCIN26 = (CSP_REGISTER_T)(0x1Aul), /**< ADC Analog Input 26 */ + //ADC12_ADCIN27 = (CSP_REGISTER_T)(0x1Bul) /**< ADC Analog Input 27 */ + ADC12_INTVREF = (CSP_REGISTER_T)(0x1Cul), + ADC12_DIV4_VDD = (CSP_REGISTER_T)(0x1Dul), + ADC12_VSS = (CSP_REGISTER_T)(0x1Eul), +} +ADC12_InputSet_TypeDef; + +/** + * @brief ADC12 Convertion repeat number + */ +typedef enum +{ + ADC12_CV_RepeatNum1 = (CSP_REGISTER_T)(0x0ul<<8)|(0x0ul<<13), /**< ADC Convertion number 1 */ + ADC12_CV_RepeatNum2 = (CSP_REGISTER_T)(0x1ul<<8)|(0x1ul<<13), /**< ADC Convertion number 2 */ + ADC12_CV_RepeatNum4 = (CSP_REGISTER_T)(0x2ul<<8)|(0x2ul<<13), /**< ADC Convertion number 4 */ + ADC12_CV_RepeatNum8 = (CSP_REGISTER_T)(0x3ul<<8)|(0x3ul<<13), /**< ADC Convertion number 8 */ + ADC12_CV_RepeatNum16 = (CSP_REGISTER_T)(0x4ul<<8)|(0x4ul<<13), /**< ADC Convertion number 16 */ + ADC12_CV_RepeatNum32 = (CSP_REGISTER_T)(0x5ul<<8)|(0x5ul<<13), /**< ADC Convertion number 32 */ + ADC12_CV_RepeatNum64 = (CSP_REGISTER_T)(0x6ul<<8)|(0x6ul<<13), /**< ADC Convertion number 64 */ + ADC12_CV_RepeatNum128 = (CSP_REGISTER_T)(0x7ul<<8)|(0x7ul<<13), /**< ADC Convertion number 128 */ + ADC12_CV_RepeatNum256 = (CSP_REGISTER_T)(0x8ul<<8)|(0x8ul<<13), /**< ADC Convertion number 256 */ + ADC12_CV_RepeatNum512 = (CSP_REGISTER_T)(0x9ul<<8)|(0x9ul<<13) /**< ADC Convertion number 512 */ +}ADC12_CV_RepeatNum_TypeDef; + +/** + * @brief ADC12 VREFP VREFN Selecte + */ +typedef enum +{ + ADC12_VREFP_VDD_VREFN_VSS = 0, + ADC12_VREFP_EXIT_VREFN_VSS = 1, + ADC12_VREFP_FVR2048_VREFN_VSS = 2, + ADC12_VREFP_FVR4096_VREFN_VSS = 3, + //ADC12_VREFP_INTVREF0750_VREFN_VSS = 4, + ADC12_VREFP_INTVREF1000_VREFN_VSS = 5, + ADC12_VREFP_VDD_VREFN_EXIT = 6, + ADC12_VREFP_EXIT_VREFN_EXIT = 7, + ADC12_VREFP_FVR2048_VREFN_EXIT = 8, + ADC12_VREFP_FVR4096_VREFN_EXIT = 9, + //ADC12_VREFP_INTVREF0750_VREFN_EXIT = 10, + ADC12_VREFP_INTVREF1000_VREFN_EXIT = 11 +}ADC12_VREFP_VREFN_Selected_TypeDef; + +extern void ADC12_RESET_VALUE(void); +extern void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x ); +extern void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState); +extern uint8_t ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit); +extern void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState); +extern void ADC12_Software_Reset(void); +extern void ADC12_CMD(FunctionalStatus NewState); +extern void ADC12_ready_wait(void); +extern void ADC12_EOC_wait(void); +extern void ADC12_SEQEND_wait(U8_T val); +extern U16_T ADC12_DATA_OUPUT(U16_T Data_index ); +extern void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver ); +extern void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X ); +extern void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data ); +extern void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX , + ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx); +extern U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL); +extern void ADC_Int_Enable(void); +extern void ADC_Int_Disable(void); +extern void ADC12_CONFIG(void); +extern void adc12_SHR_SET(U8_T adc12_SHR); + +#endif /**< apt32f102_adc_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_bt.h b/Source/include/apt32f102_bt.h new file mode 100644 index 0000000..cb203fc --- /dev/null +++ b/Source/include/apt32f102_bt.h @@ -0,0 +1,193 @@ +/* + ****************************************************************************** + * @file apt32f102_bt.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_bt_H +#define _apt32f102_bt_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +#define BT_RESET_VALUE (0x00000000) + + +/** + * @brief bt pin numbner + */ +typedef enum +{ + BT0_PA00 = 0, /*!< Pin 0 selected */ + BT0_PA02 = 1, /*!< Pin 1 selected */ + BT0_PA05 = 2, /*!< Pin 2 selected */ + BT0_PB02 = 3, /*!< Pin 3 selected */ + BT0_PB05 = 4, /*!< Pin 4 selected */ + BT0_PA11 = 5, /*!< Pin 5 selected */ + BT0_PA13 = 6, /*!< Pin 6 selected */ + BT0_PA15 = 7, /*!< Pin 7 selected */ + BT1_PA01 = 8, /*!< Pin 8 selected */ + BT1_PA06 = 9, /*!< Pin 9 selected */ + BT1_PA08 = 10, /*!< Pin 10 selected */ + BT1_PA12 = 11, /*!< Pin 11 selected */ + BT1_PA14 = 12, /*!< Pin 12 selected */ + BT1_PB00 = 13, /*!< Pin 13 selected */ + BT1_PB04 = 14, /*!< Pin 13 selected */ +}BT_Pin_TypeDef; +/** + * @brief BT CLK EN register + */ +typedef enum +{ + BTCLK_DIS = 0, + BTCLK_EN = 1, +}BT_CLK_TypeDef; +/** + * @brief BT START SHADOW register + */ +typedef enum +{ + BT_SHADOW = (0<<3), + BT_IMMEDIATE= (1<<3), +}BT_SHDWSTP_TypeDef; +/** + * @brief BT OPM register + */ +typedef enum +{ + BT_CONTINUOUS= (0<<4), + BT_ONCE= (1<<4), +}BT_OPM_TypeDef; +/** + * @brief BT EXTCKM register + */ +typedef enum +{ + BT_PCLKDIV= (0<<5), + BT_EXTCKM= (1<<5), +}BT_EXTCKM_TypeDef; +/** + * @brief BT IDLEST register + */ +typedef enum +{ + BT_IDLE_LOW= (0<<6), + BT_IDLE_HIGH= (1<<6), +}BT_IDLEST_TypeDef; +/** + * @brief BT STARTST register + */ +typedef enum +{ + BT_START_LOW= (0<<7), + BT_START_HIGH= (1<<7), +}BT_STARTST_TypeDef; +/** + * @brief BT STARTST register + */ +typedef enum +{ + BT_SYNC_DIS= (0<<8), + BT_SYNC_EN= (1<<8), +}BT_SYNCEN_TypeDef; +/** + * @brief BT OSTMDX register + */ +typedef enum +{ + BT_OSTMDX_CONTINUOUS= (0<<10), + BT_OSTMDX_ONCE= (1<<10), +}BT_OSTMDX_TypeDef; +/** + * @brief BT AREARM register + */ +typedef enum +{ + BT_AREARM_DIS= (0<<14), + BT_AREARM_EN= (1<<14), +}BT_AREARM_TypeDef; +/** + * @brief BT SYNCMD register + */ +typedef enum +{ + BT_SYNCMD_DIS= (0<<15), + BT_SYNCMD_EN= (1<<15), +}BT_SYNCMD_TypeDef; +/** + * @brief BT CNTRLD register + */ +typedef enum +{ + BT_CNTRLD_EN= (0<<16), + BT_CNTRLD_DIS= (1<<16), +}BT_CNTRLD_TypeDef; +/** + * @brief BT CNTRLD register + */ +typedef enum +{ + BT_TRGSRC_DIS= (0<<0), + BT_TRGSRC_PEND= (1<<0), + BT_TRGSRC_CMP= (2<<0), + BT_TRGSRC_OVF= (3<<0), +}BT_TRGSRC_TypeDef; +/** + * @brief BT CNTRLD register + */ +typedef enum +{ + BT_TRGOE_DIS= (0<<20), + BT_TRGOE_EN= (1<<20), +}BT_TRGOE_TypeDef; +/** + * @brief BT INT MASK SET/CLR Set + */ +typedef enum +{ + BT_PEND = (0x01 << 0), + BT_CMP = (0x01 << 1), + BT_OVF = (0x01 << 2), + BT_EVTRG = (0x01 << 3), +}BT_IMSCR_TypeDef; + + +extern void BT_DeInit(CSP_BT_T *BTx); +extern void BT_IO_Init(BT_Pin_TypeDef BT_IONAME); +extern void BT_Start(CSP_BT_T *BTx); +extern void BT_Stop(CSP_BT_T *BTx); +extern void BT_Soft_Reset(CSP_BT_T *BTx); +extern void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM); +extern void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD, + BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD); +extern void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA); +extern void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA); +extern U16_T BT_PRDR_Read(CSP_BT_T *BTx); +extern U16_T BT_CMP_Read(CSP_BT_T *BTx); +extern U16_T BT_CNT_Read(CSP_BT_T *BTx); +extern void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE); +extern void BT_Soft_Tigger(CSP_BT_T *BTx); +extern void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X); +extern void BT0_INT_ENABLE(void); +extern void BT0_INT_DISABLE(void); +extern void BT1_INT_ENABLE(void); +extern void BT1_INT_DISABLE(void); +extern void BT_Stop_High(CSP_BT_T *BTx); +extern void BT_Stop_Low(CSP_BT_T *BTx); + + +#endif /**< apt32f102_bt_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_ck801.h b/Source/include/apt32f102_ck801.h new file mode 100644 index 0000000..1d99c9e --- /dev/null +++ b/Source/include/apt32f102_ck801.h @@ -0,0 +1,130 @@ +/* + ****************************************************************************** + * @file apt32f102_ck801.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_ck801_H +#define _apt32f102_ck801_H + +//---------------------------------------------------------------------------- +// Interrupt Controller +//---------------------------------------------------------------------------- +//#define CK801_BASEADDR ((unsigned int) 0xE000E000) +#define CK801_BASEADDR 0xE000E000 + +#define INTC_ISER CK801_BASEADDR+0x100 //INTC interrupt enable register +#define INTC_IWER CK801_BASEADDR+0x140 //INTC wake-up interrupt enable register +#define INTC_ICER CK801_BASEADDR+0x180 //INTC interrupt enable clear register +#define INTC_IWDR CK801_BASEADDR+0x1C0 //INTC wake-up interrupt enable clear register +#define INTC_ISPR CK801_BASEADDR+0x200 //INTC interrupt pending register +#define INTC_ICPR CK801_BASEADDR+0x280 //INTC interrupt pending clear register +#define INTC_IABR CK801_BASEADDR+0x300 //INTC interrupt acknowledge status register +#define INTC_IPR0 CK801_BASEADDR+0x400 //INTC interrupt priority register +#define INTC_IPR1 CK801_BASEADDR+0x404 //INTC interrupt priority register +#define INTC_IPR2 CK801_BASEADDR+0x408 //INTC interrupt priority register +#define INTC_IPR3 CK801_BASEADDR+0x40C //INTC interrupt priority register +#define INTC_IPR4 CK801_BASEADDR+0x410 //INTC interrupt priority register +#define INTC_IPR5 CK801_BASEADDR+0x414 //INTC interrupt priority register +#define INTC_IPR6 CK801_BASEADDR+0x418 //INTC interrupt priority register +#define INTC_IPR7 CK801_BASEADDR+0x41C //INTC interrupt priority register +#define INTC_ISR CK801_BASEADDR+0xC00 //INTC interrupt status register +#define INTC_IPTR CK801_BASEADDR+0xC04 //INTC interrupt pending threshold register + + +#define INTC_ISER_WRITE(val) *(volatile UINT32 *) (INTC_ISER ) = val +#define INTC_IWER_WRITE(val) *(volatile UINT32 *) (INTC_IWER ) = val +#define INTC_ICER_WRITE(val) *(volatile UINT32 *) (INTC_ICER ) = val +#define INTC_IWDR_WRITE(val) *(volatile UINT32 *) (INTC_IWDR ) = val +#define INTC_ISPR_WRITE(val) *(volatile UINT32 *) (INTC_ISPR ) = val +#define INTC_ICPR_WRITE(val) *(volatile UINT32 *) (INTC_ICPR ) = val +#define INTC_IABR_WRITE(val) *(volatile UINT32 *) (INTC_IABR ) = val +#define INTC_IPR0_WRITE(val) *(volatile UINT32 *) (INTC_IPR0 ) = val +#define INTC_IPR1_WRITE(val) *(volatile UINT32 *) (INTC_IPR1 ) = val +#define INTC_IPR2_WRITE(val) *(volatile UINT32 *) (INTC_IPR2 ) = val +#define INTC_IPR3_WRITE(val) *(volatile UINT32 *) (INTC_IPR3 ) = val +#define INTC_IPR4_WRITE(val) *(volatile UINT32 *) (INTC_IPR4 ) = val +#define INTC_IPR5_WRITE(val) *(volatile UINT32 *) (INTC_IPR5 ) = val +#define INTC_IPR6_WRITE(val) *(volatile UINT32 *) (INTC_IPR6 ) = val +#define INTC_IPR7_WRITE(val) *(volatile UINT32 *) (INTC_IPR7 ) = val +#define INTC_ISR_WRITE(val) *(volatile UINT32 *) (INTC_ISR ) = val +#define INTC_IPTR_WRITE(val) *(volatile UINT32 *) (INTC_IPTR ) = val + + +#define INTC_ISER_READ(intc) (intc->ISER ) +#define INTC_IWER_READ(intc) (intc->IWER ) +#define INTC_ICER_READ(intc) (intc->ICER ) +#define INTC_IWDR_READ(intc) (intc->IWDR ) +#define INTC_ISPR_READ(intc) (intc->ISPR ) +#define INTC_ICPR_READ(intc) (intc->ICPR ) +#define INTC_IABR_READ(intc) (intc->IABR ) +#define INTC_IPR0_READ(intc) (intc->IPR0 ) +#define INTC_IPR1_READ(intc) (intc->IPR1 ) +#define INTC_IPR2_READ(intc) (intc->IPR2 ) +#define INTC_IPR3_READ(intc) (intc->IPR3 ) +#define INTC_IPR4_READ(intc) (intc->IPR4 ) +#define INTC_IPR5_READ(intc) (intc->IPR5 ) +#define INTC_IPR6_READ(intc) (intc->IPR6 ) +#define INTC_IPR7_READ(intc) (intc->IPR7 ) +#define INTC_ISR_READ(intc) (intc->ISR ) +#define INTC_IPTR_READ(intc) (intc->IPTR ) + + +typedef enum IRQn +{ + + ISR_Restart = -32, + ISR_Misaligned_Access = -31, + ISR_Access_Error = -30, + ISR_Divided_By_Zero = -29, + ISR_Illegal = -28, + ISR_Privlege_Violation = -27, + ISR_Trace_Exection = -26, + ISR_Breakpoint_Exception = -25, + ISR_Unrecoverable_Error = -24, + ISR_Idly4_Error = -23, + ISR_Auto_INT = -22, + ISR_Auto_FINT = -21, + ISR_Reserved_HAI = -20, + ISR_Reserved_FP = -19, + ISR_TLB_Ins_Empty = -18, + ISR_TLB_Data_Empty = -17, + + INTC_CORETIM_IRQn = 0, + INTC_TIME1_IRQn = 1, + INTC_UART0_IRQn = 2, + INTC_GPIOA2_IRQn = 8, +} IRQn_Type; + + +void INTC_Init(void); +void force_interrupt(IRQn_Type IRQn); + +void CK_CPU_EnAllNormalIrq(void); +void CK_CPU_DisAllNormalIrq(void); + +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef uint32_t +#define uint32_t unsigned int +#endif + +#ifndef uint8_t +#define uint8_t unsigned char +#endif + +#endif +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_clkcalib.h b/Source/include/apt32f102_clkcalib.h new file mode 100644 index 0000000..17bfa98 --- /dev/null +++ b/Source/include/apt32f102_clkcalib.h @@ -0,0 +1,37 @@ + /****************************************************************************** + * @file apt32f102_clkcalib.h + * @author APT AE Team + * @version V1.22 + * @date 2021/11/22 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + + +#include "apt32f102.h" + + +/** + * @brief CALIB OSC SELECTE SET + */ +typedef enum +{ + CLK_HFOSC_48M = (0x0ul), + CLK_HFOSC_24M = (0x1ul), + CLK_HFOSC_12M = (0x2ul), + CLK_HFOSC_6M = (0x3ul), + CLK_IMOSC_5556K = (0x4ul), + CLK_IMOSC_4194K = (0x5ul), + CLK_IMOSC_2097K = (0x6ul), + CLK_IMOSC_131K = (0x7ul) +}CALIB_OSC_SELECTE_TypeDef; + + +extern U8_T std_clk_calib(CALIB_OSC_SELECTE_TypeDef OSC_CALIB_X); \ No newline at end of file diff --git a/Source/include/apt32f102_coret.h b/Source/include/apt32f102_coret.h new file mode 100644 index 0000000..190130e --- /dev/null +++ b/Source/include/apt32f102_coret.h @@ -0,0 +1,51 @@ +/* + ****************************************************************************** + * @file apt32f102_CORET.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_CORET_H +#define _apt32f102_CORET_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +/****************************************************************************** +************************* syscon Registers Definition ************************* +******************************************************************************/ +#define CORET_CSR_RST ((CSP_REGISTER_T)0x00000004) +#define CORET_RVR_RST ((CSP_REGISTER_T)0x00000000) +#define CORET_CVR_RST ((CSP_REGISTER_T)0x00000000) +#define CORET_CALIB_RST ((CSP_REGISTER_T)0x00000000) + + + + +extern void CORET_DeInit(void); +extern void CORET_Int_Enable(void); +extern void CORET_Int_Disable(void); +extern void CORET_WakeUp_Enable(void); +extern void CORET_WakeUp_Disable(void); +extern void CORET_start(void); +extern void CORET_stop(void); +extern void CORET_CLKSOURCE_EX(void); +extern void CORET_CLKSOURCE_IN(void); +extern void CORET_TICKINT_Enable(void); +extern void CORET_TICKINT_Disable(void); +extern void CORET_reload(void); + +#endif /**< apt32f102_coret_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_countera.h b/Source/include/apt32f102_countera.h new file mode 100644 index 0000000..6492c35 --- /dev/null +++ b/Source/include/apt32f102_countera.h @@ -0,0 +1,150 @@ +/* + ****************************************************************************** + * @file apt32f102_countera.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_countera_H +#define _apt32f102_countera_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define CA_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------countA value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief countA Period int + */ +typedef enum +{ + Period_NA = 0, //Interrupt enable/disable for High/low period elapsed + Period_H = 1, + Period_L = 2, + Period_H_L = 3, +}CA_INT_TypeDef; +/** + * @brief countA DIV + */ +typedef enum +{ + DIV1 = ((0 & 0x03ul)<<4) , //Counter A input clock frequency selection + DIV2 = ((1 & 0x03ul)<<4) , + DIV4 = ((2 & 0x03ul)<<4) , + DIV8 = ((3 & 0x03ul)<<4) , +}CA_CLKDIV_TypeDef; +/** + * @brief countA mode + */ +typedef enum +{ + ONESHOT_MODE = (0x00ul << 1), //Mode Selection:oneshotmode/repeat mode + REPEAT_MODE = (0x01ul << 1), +}CA_Mode_TypeDef; +/** + * @brief countA carrier setting + */ +typedef enum +{ + CARRIER_OFF = (0x00ul << 25), //Carrier signal + CARRIER_ON = (0x01ul << 25), +}CA_CARRIER_TypeDef; +/** + * @brief Carrier Waveform Output Starting Polarity + */ +typedef enum +{ + OSP_LOW = 0, //Carrier Waveform Output Starting Polarity + OSP_HIGH = 1, +}CA_OSP_TypeDef; +/** + * @brief Carrier register load + */ +typedef enum +{ + HW_STROBE_0 = (0x01ul<<17), //Counter A data register Hardware/software load enable. + HW_STROBE_1 = (0x01ul<<18), + SW_STROBE = (0x01ul<<16), +}CA_STROBE_TypeDef; +/** + * @brief Carrier rem output signal + */ +typedef enum +{ + ENVELOPE_0 = (0x00ul << 24), //REM output signal selection bit + ENVELOPE_1 = (0x01ul << 24), +}CA_ENVELOPE_TypeDef; +/** + * @brief Carrier PENDREM + */ +typedef enum +{ + PENDREM_OFF = ((0 & 0x03ul)<<21), + PENDREM_1 = ((1 & 0x03ul)<<21), + PENDREM_2 = ((2 & 0x03ul)<<21), +}CA_PENDREM_TypeDef; +/** + * @brief Carrier ATCHREM + */ +typedef enum +{ + MATCHREM_OFF = ((0 & 0x03ul)<<19), + MATCHREM_1 = ((1 & 0x03ul)<<19), + MATCHREM_2 = ((2 & 0x03ul)<<19), +}CA_MATCHREM_TypeDef; +/** + * @brief Carrier REMSTAT + */ +typedef enum +{ + REMSTAT_0 = ((0 & 0x01ul)<<23), + REMSTAT_1 = ((1 & 0x01ul)<<23), +}CA_REMSTAT_TypeDef; +/** + * @brief counterA IO + */ +typedef enum +{ + COUNTA_PB01 = 0, + COUNTA_PA05 = 1, + COUNTA_PA11 = 2, +}CA_COUNTAIO_TypeDef; + + + +extern void COUNTA_Init(uint32_t Data_H,uint32_t Data_L,CA_INT_TypeDef INT_Mode, + CA_CLKDIV_TypeDef DIVx,CA_Mode_TypeDef Mode,CA_CARRIER_TypeDef Carrier, + CA_OSP_TypeDef OSP_Mode) ; +extern void COUNTA_Config(CA_STROBE_TypeDef STROBE,CA_PENDREM_TypeDef Pend_CON, + CA_MATCHREM_TypeDef Match_CON,CA_REMSTAT_TypeDef Stat_CON,CA_ENVELOPE_TypeDef ENVELOPE ); +extern void COUNT_DeInit(void); +extern void COUNTA_Start(void); +extern void COUNTA_Stop(void); +extern void COUNTA_Int_Disable(void); +extern void COUNTA_Int_Enable(void); +extern void COUNTA_Wakeup_Disable(void); +extern void COUNTA_Wakeup_Enable(void); +extern void COUNTA_IO_Init(CA_COUNTAIO_TypeDef COUNTA_IO_G); +extern void COUNTA_Data_Update(uint32_t Data_H,uint32_t Data_L); + + + +/*************************************************************/ + +#endif /**< apt32f102_countera_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_crc.h b/Source/include/apt32f102_crc.h new file mode 100644 index 0000000..8516a64 --- /dev/null +++ b/Source/include/apt32f102_crc.h @@ -0,0 +1,87 @@ +/* + ****************************************************************************** + * @file apt32f102_crc.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_crc_H +#define _apt32f102_crc_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +#define CRC_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------CRC value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief CRC COMPIN register + */ +typedef enum +{ + XORIN_DIS = 0, + XORIN_EN = 1, +}CRC_COMPIN_TypeDef; +/** + * @brief CRC COMPOUT register + */ +typedef enum +{ + XOROUT_DIS = (0<<1), + XOROUT_EN = (1<<1), +}CRC_COMPOUT_TypeDef; +/** + * @brief CRC ENDIANIN register + */ +typedef enum +{ + REFIN_DIS = (0<<2), + REFIN_EN = (1<<2), +}CRC_ENDIANIN_TypeDef; +/** + * @brief CRC ENDIANOUT register + */ +typedef enum +{ + REFOUT_DIS = (0<<3), + REFOUT_EN = (1<<3), +}CRC_ENDIANOUT_TypeDef; +/** + * @brief CRC poly register + */ +typedef enum +{ + POLY_CCITT = (0<<4), + POLY_16 = (2<<4), + POLY_32 = (3<<4), +}CRC_POLY_TypeDef; + + +extern void CRC_CMD(FunctionalStatus NewState); +extern void CRC_Soft_Reset(void); +extern void CRC_Configure(CRC_COMPIN_TypeDef COMPINX,CRC_COMPOUT_TypeDef COMPOUTX,CRC_ENDIANIN_TypeDef ENDIANINX, + CRC_ENDIANOUT_TypeDef ENDIANOUT,CRC_POLY_TypeDef POLYX); +extern void CRC_Seed_Write(U32_T seed_data); +extern U32_T CRC_Seed_Read(void); +extern void CRC_Datain(U32_T data_in); +extern U32_T CRC_Result_Read(void); +extern U32_T Chip_CRC_CRC32(U32_T *data, U32_T words); +extern U32_T Chip_CRC_CRC16(U16_T *data, U32_T size); +extern U32_T Chip_CRC_CRC8(U8_T *data, U32_T size); +/*************************************************************/ + +#endif /**< apt32f102_crc_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_ept.h b/Source/include/apt32f102_ept.h new file mode 100644 index 0000000..d172a14 --- /dev/null +++ b/Source/include/apt32f102_ept.h @@ -0,0 +1,783 @@ +/* + ****************************************************************************** + * @file apt32f102_ept.h + * @author APT AE Team + * @version V1.020 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_ept_H +#define _apt32f102_ept_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" +/****************************************************************************** +************************* ept Registers Definition ************************* +******************************************************************************/ +/** + * @brief EPT io Mode set + */ +typedef enum +{ + EPT_IO_CHAX = 0, + EPT_IO_CHAY = 1, + EPT_IO_CHBX = 2, + EPT_IO_CHBY = 3, + EPT_IO_CHCX = 4, + EPT_IO_CHCY = 5, + EPT_IO_CHD = 6, + EPT_IO_EPI = 7 +}EPT_IO_Mode_Type; +/** + * @brief EPT io NUM set + */ +typedef enum +{ + IO_NUM_PA07 = 0X10, + IO_NUM_PA10 = 0X11, + IO_NUM_PA15 = 0X12, + IO_NUM_PB03 = 0X13, + IO_NUM_PB05 = 0X14, + IO_NUM_PA12 = 0X15, + IO_NUM_PB02 = 0X16, + IO_NUM_PA11 = 0X17, + IO_NUM_PA14 = 0X18, + IO_NUM_PB04 = 0X19, + IO_NUM_PA05 = 0X1A, + IO_NUM_PA08 = 0X1B, + IO_NUM_PA03 = 0X1C, + IO_NUM_PB00 = 0X1D, + IO_NUM_PA04 = 0X1E, + IO_NUM_PA09 = 0X1F, + IO_NUM_PA013 = 0X20 +}EPT_IO_NUM_Type; +/** + * @brief EPT TCLK selected + */ +typedef enum +{ + EPT_Selecte_PCLK = 0<<3, + EPT_Selecte_SYNCUSR3 = 1<<3 +}EPT_TCLK_Selecte_Type; +/** + * @brief EPT TIN selected + */ +typedef enum +{ + EPT_CGSRC_TIN_BT0OUT = 0, + EPT_CGSRC_TIN_BT1OUT = 1, + EPT_CGSRC_CHAX = 2, //设置CHAX CHBX后对应管脚将不能输出PWM + EPT_CGSRC_CHBX = 3, + EPT_CGSRC_DIS = 4 +}EPT_CGSRC_TIN_Selecte_Type; + +typedef enum +{ + EPT_BURST_ENABLE = 1<<9, + EPT_BURST_DIABLE = 0<<9 +}EPT_BURST_CMD_Type; +/** + * @brief EPT CNTMD selected + */ +typedef enum +{ + EPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)), + EPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)), + EPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0)) +}EPT_CNTMD_SELECTE_Type; +/** + * @brief EPT OPM selected + */ +typedef enum +{ + EPT_OPM_Once = ((CSP_REGISTER_T)(0x01ul << 6)), + EPT_OPM_Continue = ((CSP_REGISTER_T)(0x00ul << 6)) +}EPT_OPM_SELECTE_Type; +/** + * @brief EPT CAP CMD + */ +typedef enum +{ + EPT_CAP_EN = ((CSP_REGISTER_T)(0x01ul << 8)), + EPT_CAP_DIS = ((CSP_REGISTER_T)(0x00ul << 8)) +}EPT_CAPLDEN_CMD_Type; + +/** + * @brief EPT CAPMD selected + */ +typedef enum +{ + EPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)), + EPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20)) +}EPT_CAPMD_SELECTE_Type; + +/** + * @brief EPT CMPA RST CMD + */ +typedef enum +{ + EPT_LDARST_EN = ((CSP_REGISTER_T)(0x00ul << 23)), + EPT_LDARST_DIS = ((CSP_REGISTER_T)(0x01ul << 23)) +}EPT_LOAD_CMPA_RST_CMD_Type; +/** + * @brief EPT CMPB RST CMD + */ +typedef enum +{ + EPT_LDBRST_EN = ((CSP_REGISTER_T)(0x00ul << 24)), + EPT_LDBRST_DIS = ((CSP_REGISTER_T)(0x01ul << 24)) +}EPT_LOAD_CMPB_RST_CMD_Type; +/** + * @brief EPT CMPC RST CMD + */ +typedef enum +{ + EPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)), + EPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25)) +}EPT_LOAD_CMPC_RST_CMD_Type; +/** + * @brief EPT CMPD RST CMD + */ +typedef enum +{ + EPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)), + EPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26)) +}EPT_LOAD_CMPD_RST_CMD_Type; +/** + * @brief EPT FLT CMD + */ +typedef enum +{ + EPT_FLT_DIS = ((CSP_REGISTER_T)(0x00ul << 10)), + EPT_FLT_EN = ((CSP_REGISTER_T)(0x01ul << 10)) +}EPT_FLT_CMD_Type; +/** + * @brief EPT FLT CGFLT + */ +typedef enum +{ + EPT_FLT_Bypass = ((CSP_REGISTER_T)(0x00ul << 13)), + EPT_FLT_2 = ((CSP_REGISTER_T)(0x01ul << 13)), + EPT_FLT_3 = ((CSP_REGISTER_T)(0x02ul << 13)), + EPT_FLT_4 = ((CSP_REGISTER_T)(0x03ul << 13)), + EPT_FLT_6 = ((CSP_REGISTER_T)(0x04ul << 13)), + EPT_FLT_8 = ((CSP_REGISTER_T)(0x05ul << 13)), + EPT_FLT_16 = ((CSP_REGISTER_T)(0x06ul << 13)), + EPT_FLT_32 = ((CSP_REGISTER_T)(0x07ul << 13)) +}EPT_FLT_CGFLT_Type; +/** + * @brief EPT Triggle Mode + */ +typedef enum +{ + EPT_Triggle_Continue = ((CSP_REGISTER_T)(0x00ul << 8)), + EPT_Triggle_Once = ((CSP_REGISTER_T)(0x01ul << 8)) +}EPT_Triggle_Mode_Type; +/** + * @brief EPT Rearm select + */ +typedef enum +{ + EPT_REARM_SYNCEN0 = ((CSP_REGISTER_T)(0x01ul << 16)), + EPT_REARM_SYNCEN1 = ((CSP_REGISTER_T)(0x02ul << 16)), + EPT_REARM_SYNCEN2 = ((CSP_REGISTER_T)(0x04ul << 16)), + EPT_REARM_SYNCEN3 = ((CSP_REGISTER_T)(0x08ul << 16)), + EPT_REARM_SYNCEN4 = ((CSP_REGISTER_T)(0x10ul << 16)), + EPT_REARM_SYNCEN5 = ((CSP_REGISTER_T)(0x20ul << 16)) +}EPT_REARMX_Type; +/** + * @brief EPT Rearm select + */ +typedef enum +{ + EPT_REARM_Selected_DIS = ((CSP_REGISTER_T)(0x00ul << 30)), + EPT_REARM_Selected_ZRO_AUTO = ((CSP_REGISTER_T)(0x01ul << 30)), + EPT_REARM_Selected_PRD_AUTO = ((CSP_REGISTER_T)(0x02ul << 30)), + EPT_REARM_Selected_ZRO_PRD_AUTO = ((CSP_REGISTER_T)(0x03ul << 30)) +}EPT_REARM_MODE_Type; +/** + * @brief EPT Syncusr0 Trig select + */ +typedef enum +{ + EPT_SYNCUSR0_REARMTrig_DIS = ((CSP_REGISTER_T)(0x00ul << 22)), + EPT_SYNCUSR0_REARMTrig_T1 = ((CSP_REGISTER_T)(0x01ul << 22)), + EPT_SYNCUSR0_REARMTrig_T2 = ((CSP_REGISTER_T)(0x02ul << 22)), + EPT_SYNCUSR0_REARMTrig_T1T2 = ((CSP_REGISTER_T)(0x03ul << 22)) +}EPT_SYNCUSR0_REARMTrig_Selecte_Type; +/** + * @brief EPT TRGSRC0 ExtSync Selected + */ +typedef enum +{ + EPT_TRGSRC0_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 24)), + EPT_TRGSRC0_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 24)), + EPT_TRGSRC0_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 24)), + EPT_TRGSRC0_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 24)), + EPT_TRGSRC0_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 24)), + EPT_TRGSRC0_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 24)) +}EPT_TRGSRC0_ExtSync_Selected_Type; +/** + * @brief EPT TRGSRC1 ExtSync Selected + */ +typedef enum +{ + EPT_TRGSRC1_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 27)), + EPT_TRGSRC1_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 27)), + EPT_TRGSRC1_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 27)), + EPT_TRGSRC1_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 27)), + EPT_TRGSRC1_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 27)), + EPT_TRGSRC1_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 27)) +}EPT_TRGSRC1_ExtSync_Selected_Type; +/** + * @brief EPT PHSEN CMD + */ +typedef enum +{ + EPT_PHSEN_DIS = ((CSP_REGISTER_T)(0x00ul << 8)), + EPT_PHSEN_EN = ((CSP_REGISTER_T)(0x01ul << 8)) +}EPT_PHSEN_CMD_Type; +/** + * @brief EPT PHSDIR selecte + */ +typedef enum +{ + EPT_PHSDIR_increase = ((CSP_REGISTER_T)(0x01ul << 31)), + EPT_PHSEN_decrease = ((CSP_REGISTER_T)(0x00ul << 31)) +}EPT_PHSDIR_Type; +/** + * @brief EPT GLDCR Config + */ +typedef enum +{ + EPT_GLDMD_Selecte_ZRO = ((CSP_REGISTER_T)(0x00ul << 1)), + EPT_GLDMD_Selecte_PRD = ((CSP_REGISTER_T)(0x01ul << 1)), + EPT_GLDMD_Selecte_ZRO_PRD = ((CSP_REGISTER_T)(0x02ul << 1)), + EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x03ul << 1)), + EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x04ul << 1)), + EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x05ul << 1)), + EPT_GLDMD_Selecte_SW = ((CSP_REGISTER_T)(0x0Ful << 1)) +}EPT_GLDMD_Selecte_Type; +/** + * @brief EPT OSTMD Selecte + */ +typedef enum +{ + EPT_GLD_OneShot_DIS = ((CSP_REGISTER_T)(0x00ul << 5)), + EPT_GLD_OneShot_EN = ((CSP_REGISTER_T)(0x01ul << 5)) +}EPT_GLD_OneShot_CMD_Type; +/** + * @brief EPT PRDR Event Load + */ +typedef enum +{ + EPT_PRDR_EventLoad_PEND = ((CSP_REGISTER_T)(0x00ul << 4)), + EPT_PRDR_EventLoad_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x01ul << 4)), + EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x02ul << 4)), + EPT_PRDR_EventLoad_Immediate = ((CSP_REGISTER_T)(0x03ul << 4)) +} EPT_PRDR_EventLoad_Type; + +/** + * @brief EPT CMPX Event load + */ +typedef enum +{ + EPT_CMPX_EventLoad_DIS = 0, + EPT_CMPX_EventLoad_Immediate = 1, + EPT_CMPX_EventLoad_ZRO = 2, + EPT_CMPX_EventLoad_PRD = 3, + EPT_CMPX_EventLoad_ExiLoad_SYNC = 4 +}EPT_CMPX_EventLoad_Type; +/** + * @brief EPT AQCRX Event load + */ +typedef enum +{ + EPT_AQCRX_EventLoad_DIS = 0, + EPT_AQCRX_EventLoad_Immediate = 1, + EPT_AQCRX_EventLoad_ZRO = 2, + EPT_AQCRX_EventLoad_PRD = 3, + EPT_AQCRX_EventLoad_ExiLoad_SYNC = 4 +}EPT_AQCRX_EventLoad_Type; +/** + * @brief EPT PWMX Selecte + */ +typedef enum +{ + EPT_PWMA = 0, + EPT_PWMB = 1, + EPT_PWMC = 2, + EPT_PWMD = 3 +}EPT_PWMX_Selecte_Type; +/** + * @brief EPT CA Selecte + */ +typedef enum +{ + EPT_CA_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 20)), + EPT_CA_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 20)), + EPT_CA_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 20)), + EPT_CA_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 20)) +}EPT_CA_Selecte_Type; +/** + * @brief EPT CB Selecte + */ +typedef enum +{ + EPT_CB_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 22)), + EPT_CB_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 22)), + EPT_CB_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 22)), + EPT_CB_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 22)) +}EPT_CB_Selecte_Type; +/** + * @brief EPT PWM ZRO Output + */ +typedef enum +{ + EPT_PWM_ZRO_Event_Nochange = ((CSP_REGISTER_T)(0x00ul )), + EPT_PWM_ZRO_Event_OutLow = ((CSP_REGISTER_T)(0x01ul )), + EPT_PWM_ZRO_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul )), + EPT_PWM_ZRO_Event_Negate = ((CSP_REGISTER_T)(0x03ul )) +}EPT_PWM_ZRO_Output_Type; +/** + * @brief EPT PWM PRD Output + */ +typedef enum +{ + EPT_PWM_PRD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<2 )), + EPT_PWM_PRD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<2 )), + EPT_PWM_PRD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<2 )), + EPT_PWM_PRD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<2 )) +}EPT_PWM_PRD_Output_Type; +/** + * @brief EPT PWM CAU Output + */ +typedef enum +{ + EPT_PWM_CAU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<4 )), + EPT_PWM_CAU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<4 )), + EPT_PWM_CAU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<4 )), + EPT_PWM_CAU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<4 )) +}EPT_PWM_CAU_Output_Type; +/** + * @brief EPT PWM CAD Output + */ +typedef enum +{ + EPT_PWM_CAD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<6 )), + EPT_PWM_CAD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<6 )), + EPT_PWM_CAD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<6 )), + EPT_PWM_CAD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<6 )) +}EPT_PWM_CAD_Output_Type; +/** + * @brief EPT PWM CBU Output + */ +typedef enum +{ + EPT_PWM_CBU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<8 )), + EPT_PWM_CBU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<8 )), + EPT_PWM_CBU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<8 )), + EPT_PWM_CBU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<8 )) +}EPT_PWM_CBU_Output_Type; +/** + * @brief EPT PWM CBD Output + */ +typedef enum +{ + EPT_PWM_CBD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<10 )), + EPT_PWM_CBD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<10 )), + EPT_PWM_CBD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<10 )), + EPT_PWM_CBD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<10 )) +}EPT_PWM_CBD_Output_Type; +/** + * @brief EPT PWM T1U Output + */ +typedef enum +{ + EPT_PWM_T1U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<12 )), + EPT_PWM_T1U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<12 )), + EPT_PWM_T1U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<12 )), + EPT_PWM_T1U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<12 )) +}EPT_PWM_T1U_Output_Type; +/** + * @brief EPT PWM T1D Output + */ +typedef enum +{ + EPT_PWM_T1D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<14 )), + EPT_PWM_T1D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<14 )), + EPT_PWM_T1D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<14 )), + EPT_PWM_T1D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<14 )) +}EPT_PWM_T1D_Output_Type; +/** + * @brief EPT PWM T2U Output + */ +typedef enum +{ + EPT_PWM_T2U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<16 )), + EPT_PWM_T2U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<16 )), + EPT_PWM_T2U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<16 )), + EPT_PWM_T2U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<16 )) +}EPT_PWM_T2U_Output_Type; +/** + * @brief EPT PWM T2D Output + */ +typedef enum +{ + EPT_PWM_T2D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<18 )), + EPT_PWM_T2D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<18 )), + EPT_PWM_T2D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<18 )), + EPT_PWM_T2D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<18 )) +}EPT_PWM_T2D_Output_Type; +/** + * @brief EPT CPCR CMD + */ +typedef enum +{ + EPT_CPCR_ENALBE = ((CSP_REGISTER_T)(0x01ul<<16 )), + EPT_CPCR_Disable = ((CSP_REGISTER_T)(0x00ul<<16 )) +}EPT_CPCR_CMD_Type; +/** + * @brief EPT CPCR Source Selecte + */ +typedef enum +{ + EPT_CPCR_Source_TCLK = ((CSP_REGISTER_T)(0)), + EPT_CPCR_Source_TIN_BT0OUT = ((CSP_REGISTER_T)(1)), + EPT_CPCR_Source_TIN_BT1OUT = ((CSP_REGISTER_T)(2)) +}EPT_CPCR_Source_Selecte_Type; +/** + * @brief EPT CPCR CDUTY + */ +typedef enum +{ + EPT_CDUTY_DIS = ((CSP_REGISTER_T)(0<<11)), + EPT_CDUTY_7_8 = ((CSP_REGISTER_T)(1<<11)), + EPT_CDUTY_6_8 = ((CSP_REGISTER_T)(2<<11)), + EPT_CDUTY_5_8 = ((CSP_REGISTER_T)(3<<11)), + EPT_CDUTY_4_8 = ((CSP_REGISTER_T)(4<<11)), + EPT_CDUTY_3_8 = ((CSP_REGISTER_T)(5<<11)), + EPT_CDUTY_2_8 = ((CSP_REGISTER_T)(6<<11)), + EPT_CDUTY_1_8 = ((CSP_REGISTER_T)(7<<11)) +}EPT_CDUTY_Type; +/** + * @brief EPT EPX + */ +typedef enum +{ + EPT_EP0 = 0, + EPT_EP1 = 1, + EPT_EP2 = 2, + EPT_EP3 = 3, + EPT_EP4 = 4, + EPT_EP5 = 5, + EPT_EP6 = 6, + EPT_EP7 = 7 +}EPT_EPX_Type; +/** + * @brief EPT Input selecte + */ +typedef enum +{ + EPT_Input_selecte_EPI0 = ((CSP_REGISTER_T)(1)), + EPT_Input_selecte_EPI1 = ((CSP_REGISTER_T)(2)), + EPT_Input_selecte_EPI2 = ((CSP_REGISTER_T)(3)), + EPT_Input_selecte_EPI3 = ((CSP_REGISTER_T)(4)), + EPT_Input_selecte_EPI4 = ((CSP_REGISTER_T)(5)), + EPT_Input_selecte_ORL0 = ((CSP_REGISTER_T)(0XE)), + EPT_Input_selecte_ORL1 = ((CSP_REGISTER_T)(0XF)) +}EPT_Input_selecte_Type; +/** + * @brief EPT FLT PACE0 + */ +typedef enum +{ + EPT_FLT_PACE0_DIS = ((CSP_REGISTER_T)(0<<8)), + EPT_FLT_PACE0_2CLK = ((CSP_REGISTER_T)(1<<8)), + EPT_FLT_PACE0_3CLK = ((CSP_REGISTER_T)(2<<8)), + EPT_FLT_PACE0_4CLK = ((CSP_REGISTER_T)(3<<8)) +}EPT_FLT_PACE0_Type; +/** + * @brief EPT FLT PACE1 + */ +typedef enum +{ + EPT_FLT_PACE1_DIS = ((CSP_REGISTER_T)(0<<10)), + EPT_FLT_PACE1_2CLK = ((CSP_REGISTER_T)(1<<10)), + EPT_FLT_PACE1_3CLK = ((CSP_REGISTER_T)(2<<10)), + EPT_FLT_PACE1_4CLK = ((CSP_REGISTER_T)(3<<10)) +}EPT_FLT_PACE1_Type; +/** + * @brief EPT DB EventLoad + */ +typedef enum +{ + EPT_DB_EventLoad_DIS = 0, + EPT_DB_EventLoad_Immediate = 1, + EPT_DB_EventLoad_ZRO = 2, + EPT_DB_EventLoad_PRD = 3, + EPT_DB_EventLoad_ZRO_PRD = 4 +}EPT_DB_EventLoad_Type; +/** + * @brief EPT CHX Selecte + */ +typedef enum +{ + EPT_CHA_Selecte = 0, + EPT_CHB_Selecte = 1, + EPT_CHC_Selecte = 2, +}EPT_CHX_Selecte_Type; +/** + * @brief EPT INSEL + */ +typedef enum +{ + EPT_CHAINSEL_PWMA_RISE_FALL = ((CSP_REGISTER_T)(0<<4)), + EPT_CHAINSEL_PWMB_RISE_PWMA_FALL = ((CSP_REGISTER_T)(1<<4)), + EPT_CHAINSEL_PWMA_RISE_PWMB_FALL = ((CSP_REGISTER_T)(2<<4)), + EPT_CHAINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(3<<4)), + EPT_CHBINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(0<<12)), + EPT_CHBINSEL_PWMC_RISE_PWMB_FALL = ((CSP_REGISTER_T)(1<<12)), + EPT_CHBINSEL_PWMB_RISE_PWMC_FALL = ((CSP_REGISTER_T)(2<<12)), + EPT_CHBINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(3<<12)), + EPT_CHCINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(0<<20)), + EPT_CHCINSEL_PWMD_RISE_PWMC_FALL = ((CSP_REGISTER_T)(1<<20)), + EPT_CHCINSEL_PWMC_RISE_PWMD_FALL = ((CSP_REGISTER_T)(2<<20)), + EPT_CHCINSEL_PWMD_RISE_FALL = ((CSP_REGISTER_T)(3<<20)) +}EPT_INSEL_Type; +/** + * @brief EPT OUTSEL + */ +typedef enum +{ + EPT_CHA_OUTSEL_PWMA_PWMB_Bypass = ((CSP_REGISTER_T)(0)), + EPT_CHA_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1)), + EPT_CHA_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2)), + EPT_CHA_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3)), + EPT_CHB_OUTSEL_PWMB_PWMC_Bypass = ((CSP_REGISTER_T)(0<<8)), + EPT_CHB_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<8)), + EPT_CHB_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<8)), + EPT_CHB_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<8)), + EPT_CHC_OUTSEL_PWMC_PWMD_Bypass = ((CSP_REGISTER_T)(0<<16)), + EPT_CHC_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<16)), + EPT_CHC_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<16)), + EPT_CHC_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<16)) +}EPT_OUTSEL_Type; +/** + * @brief EPT OUT POLARITY + */ +typedef enum +{ + EPT_PA_PB_OUT_Direct = ((CSP_REGISTER_T)(0)), + EPT_PA_OUT_Reverse = ((CSP_REGISTER_T)(1)), + EPT_PB_OUT_Reverse = ((CSP_REGISTER_T)(2)), + EPT_PA_PB_OUT_Reverse = ((CSP_REGISTER_T)(3)) +}EPT_OUT_POLARITY_Type; +/** + * @brief EPT OUT SWAP + */ +typedef enum +{ + EPT_PAtoCHX_PBtoCHY = ((CSP_REGISTER_T)(0)), + EPT_PBtoCHX_PBtoCHY = ((CSP_REGISTER_T)(1)), + EPT_PAtoCHX_PAtoCHY = ((CSP_REGISTER_T)(2)), + EPT_PBtoCHX_PAtoCHY = ((CSP_REGISTER_T)(3)) +}EPT_OUT_SWAP_Type; +/** + * @brief EPT TRGSRCX Selecte + */ +typedef enum +{ + EPT_TRGSRC0 = 0, + EPT_TRGSRC1 = 1, + EPT_TRGSRC2 = 2, + EPT_TRGSRC3 = 3 +}EPT_TRGSRCX_Select_Type; +/** + * @brief EPT EVTRG TRGSRCX SET + */ + typedef enum +{ + EPT_EVTRG_TRGSRCX_DIS = ((CSP_REGISTER_T)(0x00ul )), + EPT_EVTRG_TRGSRCX_ZRO = ((CSP_REGISTER_T)(0x01ul )), + EPT_EVTRG_TRGSRCX_PRD = ((CSP_REGISTER_T)(0x02ul )), + EPT_EVTRG_TRGSRCX_ZROorPRD = ((CSP_REGISTER_T)(0x03ul )), + EPT_EVTRG_TRGSRCX_CMPAU = ((CSP_REGISTER_T)(0x04ul )), + EPT_EVTRG_TRGSRCX_CMPAD = ((CSP_REGISTER_T)(0x05ul )), + EPT_EVTRG_TRGSRCX_CMPBU = ((CSP_REGISTER_T)(0x06ul )), + EPT_EVTRG_TRGSRCX_CMPBD = ((CSP_REGISTER_T)(0x07ul )), + EPT_EVTRG_TRGSRCX_CMPCU = ((CSP_REGISTER_T)(0x08ul )), + EPT_EVTRG_TRGSRCX_CMPCD = ((CSP_REGISTER_T)(0x09ul )), + EPT_EVTRG_TRGSRCX_CMPDU = ((CSP_REGISTER_T)(0x0Aul )), + EPT_EVTRG_TRGSRCX_CMPDD = ((CSP_REGISTER_T)(0x0Bul )), + EPT_EVTRG_TRGSRC01_ExtSync = ((CSP_REGISTER_T)(0x0Cul )), + EPT_EVTRG_TRGSRC23_PeriodEnd = ((CSP_REGISTER_T)(0x0Cul )), + EPT_EVTRG_TRGSRCX_PE0 = ((CSP_REGISTER_T)(0x0Dul )), + EPT_EVTRG_TRGSRCX_PE1 = ((CSP_REGISTER_T)(0x0Eul )), + EPT_EVTRG_TRGSRCX_PE2 = ((CSP_REGISTER_T)(0x0Ful )) +}EPT_EVTRG_TRGSRCX_TypeDef; + typedef enum +{ + EPT_TRGSRCX_EN = ((CSP_REGISTER_T)0x01ul), + EPT_TRGSRCX_DIS = ((CSP_REGISTER_T)0x00ul) +}EPT_TRGSRCX_CMD_TypeDef; +/** + * @brief EPT INT register + */ +typedef enum +{ + //RISR IMCR MISR ICR + EPT_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 0)), + EPT_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 1)), + EPT_TRGEV2_INT = ((CSP_REGISTER_T)(0x01ul << 2)), + EPT_TRGEV3_INT = ((CSP_REGISTER_T)(0x01ul << 3)), + EPT_CAP_LD0 = ((CSP_REGISTER_T)(0x01ul << 4)), + EPT_CAP_LD1 = ((CSP_REGISTER_T)(0x01ul << 5)), + EPT_CAP_LD2 = ((CSP_REGISTER_T)(0x01ul << 6)), + EPT_CAP_LD3 = ((CSP_REGISTER_T)(0x01ul << 7)), + EPT_CAU = ((CSP_REGISTER_T)(0x01ul <<8)), + EPT_CAD = ((CSP_REGISTER_T)(0x01ul <<9)), + EPT_CBU = ((CSP_REGISTER_T)(0x01ul <<10)), + EPT_CBD = ((CSP_REGISTER_T)(0x01ul <<11)), + EPT_CCU = ((CSP_REGISTER_T)(0x01ul <<12)), + EPT_CCD = ((CSP_REGISTER_T)(0x01ul <<13)), + EPT_CDU = ((CSP_REGISTER_T)(0x01ul <<14)), + EPT_CDD = ((CSP_REGISTER_T)(0x01ul <<15)), + EPT_PEND = ((CSP_REGISTER_T)(0x01ul <<16)) +}EPT_INT_TypeDef; +/** + * @brief EPT EMINT register + */ +typedef enum +{ + //EMRISR EMIMCR EMMISR EMICR + EPT_EP0_EMINT = ((CSP_REGISTER_T)(0x01ul << 0)), + EPT_EP1_EMINT = ((CSP_REGISTER_T)(0x01ul << 1)), + EPT_EP2_EMINT = ((CSP_REGISTER_T)(0x01ul << 2)), + EPT_EP3_EMINT = ((CSP_REGISTER_T)(0x01ul << 3)), + EPT_EP4_EMINT = ((CSP_REGISTER_T)(0x01ul << 4)), + EPT_EP5_EMINT = ((CSP_REGISTER_T)(0x01ul << 5)), + EPT_EP6_EMINT = ((CSP_REGISTER_T)(0x01ul << 6)), + EPT_EP7_EMINT = ((CSP_REGISTER_T)(0x01ul << 7)), + EPT_CPU_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 8)), + EPT_MEM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 9)), + EPT_EOM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 10)) +}EPT_EMINT_TypeDef; +/** + * @brief EPT LKCR TRG Source + */ +typedef enum +{ + EPT_LKCR_TRG_EP0 = 0, + EPT_LKCR_TRG_EP1 = 2, + EPT_LKCR_TRG_EP2 = 4, + EPT_LKCR_TRG_EP3 = 6, + EPT_LKCR_TRG_EP4 = 8, + EPT_LKCR_TRG_EP5 = 10, + EPT_LKCR_TRG_EP6 = 12, + EPT_LKCR_TRG_EP7 = 14, + EPT_LKCR_TRG_CPU_FAULT = 15, + EPT_LKCR_TRG_MEM_FAULT = 16, + EPT_LKCR_TRG_EOM_FAULT = 17 +}EPT_LKCR_TRG_Source_Type; +/** + * @brief EPT LKCR Mode Selecte + */ +typedef enum +{ + EPT_LKCR_Mode_LOCK_DIS = ((CSP_REGISTER_T)0x00ul), + EPT_LKCR_Mode_SLOCK_EN = ((CSP_REGISTER_T)0x01ul), + EPT_LKCR_Mode_HLOCK_EN = ((CSP_REGISTER_T)0x02ul), + EPT_LKCR_TRG_X_FAULT_HLOCK_EN = ((CSP_REGISTER_T)0x03ul), + EPT_LKCR_TRG_X_FAULT_HLOCK_DIS = ((CSP_REGISTER_T)0x04ul), +}EPT_LKCR_Mode_Type; +/** + * @brief EPT OUTPUT Channel + */ +typedef enum +{ + EPT_OUTPUT_Channel_CHAX = 0, + EPT_OUTPUT_Channel_CHBX = 2, + EPT_OUTPUT_Channel_CHCX = 4, + EPT_OUTPUT_Channel_CHD = 6, + EPT_OUTPUT_Channel_CHAY = 8, + EPT_OUTPUT_Channel_CHBY = 10, + EPT_OUTPUT_Channel_CHCY = 12 +}EPT_OUTPUT_Channel_Type; +/** + * @brief EPT SHLOCK OUTPUT Statue + */ +typedef enum +{ + EPT_SHLOCK_OUTPUT_HImpedance = 0, + EPT_SHLOCK_OUTPUT_High = 1, + EPT_SHLOCK_OUTPUT_Low = 2, + EPT_SHLOCK_OUTPUT_Nochange = 3 +}EPT_SHLOCK_OUTPUT_Statue_Type; + +/** @addtogroup EPT_Exported_functions + * @{ + */ +extern void EPT_Software_Prg(void); +extern void EPT_Start(void); +extern void EPT_Stop(void); +extern void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X); +extern void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X + , U16_T EPT_PSCR); +extern void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD); +extern void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD + , EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD + , EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR); +extern void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected , + EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN); +extern void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR); +extern void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX ); +extern void EPT_Caputure_Rearm(void); +extern void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN); +extern void EPT_Globle_SwLoad_CMD(void); +extern void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV); +extern void EPT_PWMX_Output_Control( + EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X , + EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output , + EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output , + EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output , + EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output , + EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output + ); +extern void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte); +extern void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value); +extern void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x); +extern void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x); +extern void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X); +extern void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx); +extern void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL); +extern void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X); +extern void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X); +extern void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF); +extern void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD); +extern void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select); +extern void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT); +extern void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT); +extern void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT); +extern void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT); +extern void EPT_Vector_Int_Enable(void); +extern void EPT_Vector_Int_Disable(void); +extern void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT); +extern void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT); +extern void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT); +extern void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X); +extern void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X); + +#endif /**< apt32f102_ept_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_et.h b/Source/include/apt32f102_et.h new file mode 100644 index 0000000..8c66ee3 --- /dev/null +++ b/Source/include/apt32f102_et.h @@ -0,0 +1,146 @@ +/* + ****************************************************************************** + * @file apt32f102_et.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_et_H +#define _apt32f102_et_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define ET_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------ET value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief ET SWTRG register + */ +typedef enum +{ + ET_SWTRG_CH0 = 0, + ET_SWTRG_CH1 = (1<<1), + ET_SWTRG_CH2 = (1<<2), + ET_SWTRG_CH3 = (1<<3), + ET_SWTRG_CH4 = (1<<4), + ET_SWTRG_CH5 = (1<<5), + ET_SWTRG_CH6 = (1<<6), + ET_SWTRG_CH7 = (1<<7), +}CRC_ETSWTRG_TypeDef; +/** + * @brief SRCSEL register + */ +typedef enum +{ + ET_SRC0 = 0, + ET_SRC1 = 1, + ET_SRC2 = 2, +}CRC_ESRCSEL_TypeDef; +/** + * @brief SRCSEL register + */ +typedef enum +{ + ET_DST0 = 0, + ET_DST1 = 1, + ET_DST2 = 2, +}CRC_DSTSEL_TypeDef; +/** + * @brief SRCSEL register + */ +typedef enum +{ + ET_CH3 = 0, + ET_CH4 = 1, + ET_CH5 = 2, + ET_CH6 = 3, + ET_CH7 = 4, +}CRC_ETCHX_TypeDef; +/** + * @brief TRIG MODE register + */ +typedef enum +{ + TRG_HW = (0X00<<1), + TRG_SW = (0X01<<1), +}CRC_TRIGMODE_TypeDef; + +//Source IP Event +#define ET_LPT_SYNC (0X0) +#define ET_EXI_SYNC0 (0X4) +#define ET_EXI_SYNC1 (0X5) +#define ET_EXI_SYNC2 (0X6) +#define ET_EXI_SYNC3 (0X7) +#define ET_EXI_SYNC4 (0X8) +#define ET_EXI_SYNC5 (0X9) +#define ET_RTC_SYNC0 (0XA) +#define ET_RTC_SYNC1 (0XB) +#define ET_BT_SYNC0 (0XC) +#define ET_BT_SYNC1 (0XD) +#define ET_EPT0_SYNC0 (0X10) +#define ET_EPT0_SYNC1 (0X11) +#define ET_EPT0_SYNC2 (0X12) +#define ET_EPT0_SYNC3 (0X13) +#define ET_GPT0_SYNC0 (0X20) +#define ET_GPT0_SYNC1 (0X21) +#define ET_ADC_SYNC0 (0X30) +#define ET_ADC_SYNC1 (0X31) +#define ET_TOUCH_SYNC (0X3C) +//Destination IP Event +#define ET_LPT_TRGSRC (0X0) +#define ET_BT0_TRGSRC0 (0X2) +#define ET_BT0_TRGSRC1 (0X3) +#define ET_BT1_TRGSRC0 (0X4) +#define ET_BT1_TRGSRC1 (0X5) +#define ET_ADC_TRGSRC0 (0X6) +#define ET_ADC_TRGSRC1 (0X7) +#define ET_ADC_TRGSRC2 (0X8) +#define ET_ADC_TRGSRC3 (0X9) +#define ET_ADC_TRGSRC4 (0XA) +#define ET_ADC_TRGSRC5 (0XB) +#define ET_EPT0_TRGSRC0 (0X10) +#define ET_EPT0_TRGSRC1 (0X11) +#define ET_EPT0_TRGSRC2 (0X12) +#define ET_EPT0_TRGSRC3 (0X13) +#define ET_EPT0_TRGSRC4 (0X14) +#define ET_EPT0_TRGSRC5 (0X15) +#define ET_GPT0_TRGSRC0 (0X24) +#define ET_GPT0_TRGSRC1 (0X25) +#define ET_GPT0_TRGSRC2 (0X26) +#define ET_GPT0_TRGSRC3 (0X27) +#define ET_GPT0_TRGSRC4 (0X28) +#define ET_GPT0_TRGSRC5 (0X29) +#define ET_TOUCH_TRGSRC (0X3C) + + + + +extern void ET_DeInit(void); +extern void ET_ENABLE(void); +extern void ET_DISABLE(void); +extern void ET_SWTRG_CMD(CRC_ETSWTRG_TypeDef ETSWTRG_X,FunctionalStatus NewState); +extern void ET_CH0_SRCSEL(CRC_ESRCSEL_TypeDef ESRCSEL_X,FunctionalStatus NewState,U8_T SRCSEL_X); +extern void ET_CH0_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X); +extern void ET_CH1_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X); +extern void ET_CH1_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X); +extern void ET_CH2_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X); +extern void ET_CH2_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X); +extern void ET_CHx_CONTROL(CRC_ETCHX_TypeDef ETCHX,FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T SRCSEL_X,U8_T DSTSEL_X); + + + +#endif /**< apt32f102_crc_H */ \ No newline at end of file diff --git a/Source/include/apt32f102_gpio.h b/Source/include/apt32f102_gpio.h new file mode 100644 index 0000000..5e6994a --- /dev/null +++ b/Source/include/apt32f102_gpio.h @@ -0,0 +1,221 @@ +/* + ****************************************************************************** + * @file main.c + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_gpio_H +#define _apt32f102_gpio_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define GPIO_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------GPIO value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief GPIO pin numbner + */ +typedef enum +{ + PIN_0 = 0, /*!< Pin 0 selected */ + PIN_1 = 4, /*!< Pin 1 selected */ + PIN_2 = 8, /*!< Pin 2 selected */ + PIN_3 = 12, /*!< Pin 3 selected */ + PIN_4 = 16, /*!< Pin 4 selected */ + PIN_5 = 20, /*!< Pin 5 selected */ + PIN_6 = 24, /*!< Pin 6 selected */ + PIN_7 = 28, /*!< Pin 7 selected */ + PIN_8 = 0, /*!< Pin 8 selected */ + PIN_9 = 4, /*!< Pin 9 selected */ + PIN_10 = 8, /*!< Pin 10 selected */ + PIN_11 = 12, /*!< Pin 11 selected */ + PIN_12 = 16, /*!< Pin 12 selected */ + PIN_13 = 20, /*!< Pin 13 selected */ + PIN_14 = 24, /*!< Pin 13 selected */ + PIN_15 = 28, /*!< Pin 13 selected */ +}GPIO_Pin_TypeDef; +/** + * @brief GPIO high/low register + */ +typedef enum +{ + LowByte = 0, + HighByte = 1, +}GPIO_byte_TypeDef; +/** + * @brief GPIO IO status + */ +typedef enum +{ + Intput = 1, + Output = 0, +}GPIO_Dir_TypeDef; +/** + * @brief GPIO IO mode + */ +typedef enum +{ + PUDR = 0, //pull high or low + DSCR =1, //drive strenth + OMCR =2, //open drain + IECR =3, //int +}GPIO_Mode_TypeDef; +/** + * @brief GPIO IO Group + */ +typedef enum +{ + PA0 = 0, + PB0 = 2, + GPIOA = 0, + GPIOB = 2, +}GPIO_Group_TypeDef; +/** + * @brief GPIO exi number + */ +typedef enum +{ + EXI0 = 0, + EXI1 = 1, + EXI2 = 2, + EXI3 = 3, + EXI4 = 4, + EXI5 = 5, + EXI6 = 6, + EXI7 = 7, + EXI8 = 8, + EXI9 = 9, + EXI10 = 10, + EXI11 = 11, + EXI12 = 12, + EXI13 = 13, + EXI14 = 14, + EXI15 = 15, +}GPIO_EXI_TypeDef; + +/** + * @brief EXI PIN + */ +typedef enum +{ + Selete_EXI_PIN0 = (CSP_REGISTER_T)(0), + Selete_EXI_PIN1 = (CSP_REGISTER_T)(1), + Selete_EXI_PIN2 = (CSP_REGISTER_T)(2), + Selete_EXI_PIN3 = (CSP_REGISTER_T)(3), + Selete_EXI_PIN4 = (CSP_REGISTER_T)(4), + Selete_EXI_PIN5 = (CSP_REGISTER_T)(5), + Selete_EXI_PIN6 = (CSP_REGISTER_T)(6), + Selete_EXI_PIN7 = (CSP_REGISTER_T)(7), + Selete_EXI_PIN8 = (CSP_REGISTER_T)(8), + Selete_EXI_PIN9 = (CSP_REGISTER_T)(9), + Selete_EXI_PIN10 = (CSP_REGISTER_T)(10), + Selete_EXI_PIN11 = (CSP_REGISTER_T)(11), + Selete_EXI_PIN12 = (CSP_REGISTER_T)(12), + Selete_EXI_PIN13 = (CSP_REGISTER_T)(13), + Selete_EXI_PIN14 = (CSP_REGISTER_T)(14), + Selete_EXI_PIN15 = (CSP_REGISTER_T)(15), + Selete_EXI_PIN16 = (CSP_REGISTER_T)(16), + Selete_EXI_PIN17 = (CSP_REGISTER_T)(17), + Selete_EXI_PIN18 = (CSP_REGISTER_T)(18), + Selete_EXI_PIN19 = (CSP_REGISTER_T)(19) +}GPIO_EXIPIN_TypeDef; + + +/** + * @brief GPIO INPUT MODE SETECTED + */ +typedef enum +{ + INPUT_MODE_SETECTED_CMOS = 0, + INPUT_MODE_SETECTED_TTL1 = 1, + INPUT_MODE_SETECTED_TTL2 = 2 +}INPUT_MODE_SETECTED_TypeDef; + +#define nop asm ("nop") + +#define SetPA0(n) (GPIOA0->SODR = (1ul<CODR = (1ul<SODR = (1ul<CODR = (1ul<PSDR)>>n) & 1ul) +#define PB0in(n) (((GPIOB0->PSDR)>>n) & 1ul) + + +#define CSP_GPIO_SET_CONLR(cm,val) ((cm)->CONLR = val) +#define CSP_GPIO_GET_CONLR(cm) ((cm)->CONLR) + +#define CSP_GPIO_SET_CONHR(cm,val) ((cm)->CONHR = val) +#define CSP_GPIO_GET_CONHR(cm) ((cm)->CONHR) + +#define CSP_GPIO_SET_WODR(cm,val) ((cm)->WODR = val) +#define CSP_GPIO_SET_SODR(cm,val) ((cm)->SODR = val) +#define CSP_GPIO_SET_CODR(cm,val) ((cm)->CODR = val) +#define CSP_GPIO_GET_PSDR(cm) ((cm)->PSDR) + +#define CSP_GPIO_SET_PUDR(cm,val) ((cm)->PUDR = val) +#define CSP_GPIO_GET_PUDR(cm) ((cm)->PUDR) + +#define CSP_GPIO_SET_DSCR(cm,val) ((cm)->DSCR = val) +#define CSP_GPIO_GET_DSCR(cm) ((cm)->DSCR) + +#define CSP_GPIO_SET_OMCR(cm,val) ((cm)->OMCR = val) +#define CSP_GPIO_GET_OMCR(cm) ((cm)->OMCR) + +#define CSP_GPIO_SET_IECR(cm,val) ((cm)->IECR = val) +#define CSP_GPIO_GET_IECR(cm) ((cm)->IECR) + +#define CSP_GPIO_SET_IGRP(cm,val) ((cm)->IGRP = val) +#define CSP_GPIO_GET_IGRP(cm) ((cm)->IGRP) + +/****************************************************************************** +************************** Exported functions ************************ +******************************************************************************/ +extern void GPIOA0_DeInit(GPIO_Pin_TypeDef GPIO_Pin); +extern void GPIO_DeInit(void); +extern void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X); +extern void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val); +extern void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum); +extern void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir); +extern void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val); +extern uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit); +extern uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval); +extern void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO); +extern void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO); +extern void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO); +extern void GPIO_Debug_IO_12_13(void); +extern void GPIO_Debug_IO_01_02(void); +extern void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef EXIPIN_x); +extern void GPIOA00_Set_ResetPin(); +extern void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit); +extern void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit); +/*************************************************************/ + +#endif /**< apt32f102_gpio_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_gpt.h b/Source/include/apt32f102_gpt.h new file mode 100644 index 0000000..ad6a874 --- /dev/null +++ b/Source/include/apt32f102_gpt.h @@ -0,0 +1,695 @@ +/* + ****************************************************************************** + * @file apt32f102_gpt.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_gpt_H +#define _apt32f102_gpt_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define GPT_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------GPT value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief GPT CLK EN register + */ +typedef enum +{ + GPTCLK_DIS = 0, + GPTCLK_EN = 1, +}GPT_CLK_TypeDef; +/** + * @brief GPT CLK SOURCE register + */ +typedef enum +{ + GPT_PCLK = (0<<3), + GPT_TRGUSR3 = (1<<3), +}GPT_CSS_TypeDef; +/** + * @brief GPT START SHADOW register + */ +typedef enum +{ + GPT_SHADOW = (0<<6), + GPT_IMMEDIATE= (1<<6), +}GPT_SHDWSTP_TypeDef; +/** + * @brief GPT COUNT EDGE register + */ +typedef enum +{ + DIR_INCREASE = (0<<3), + DIR_DECREASE= (1<<3), +}GPT_CNTDIR_TypeDef; +/** + * @brief GPT COUNT EDGE register + */ +typedef enum +{ + GPT_INCREASE = (0<<0), + GPT_DECREASE= (1<<0), + GPT_IN_DECREASE= (2<<0), +}GPT_CNTMD_TypeDef; +/** + * @brief GPT START SYN EN register + */ +typedef enum +{ + GPT_SWSYNDIS= (0<<2), + GPT_SWSYNEN= (1<<2), +}GPT_SWSYN_TypeDef; +/** + * @brief GPT ILDE IO Status register + */ +typedef enum +{ + GPT_IDLE_Z= (0<<3), + GPT_IDLE_LOW= (1<<3), +}GPT_IDLEST_TypeDef; +/** + * @brief GPT PRDLD register + */ +typedef enum +{ + GPT_PRDLD_PEND= (0<<4), + GPT_PRDLD_LOAD_SYNC= (1<<4), + GPT_PRDLD_ZERO_LOAD_SYNC= (2<<4), + GPT_PRDLD_IMMEDIATELY= (3<<4), +}GPT_PRDLD0_TypeDef; +/** + * @brief GPT CAPLDEN register + */ +typedef enum +{ + GPT_CAP_DIS= (0<<8), + GPT_CAP_EN= (1<<8), +}GPT_CAPLDEN_TypeDef; +/** + * @brief GPT BURST register + */ +typedef enum +{ + GPT_BURST_DIS= (0<<9), + GPT_BURST_EN= (1<<9), +}GPT_BURST_TypeDef; +/** + * @brief GPT BURST register + */ +typedef enum +{ + GPT_CG_CHAX= (0<<11), + GPT_CG_CHBX= (1<<11), +}GPT_CGSRC_TypeDef; +/** + * @brief GPT CGFLT register + */ +typedef enum +{ + GPT_CGFLT_00= (0<<13), + GPT_CGFLT_02= (1<<13), + GPT_CGFLT_03= (2<<13), + GPT_CGFLT_04= (3<<13), + GPT_CGFLT_06= (4<<13), + GPT_CGFLT_08= (5<<13), + GPT_CGFLT_16= (6<<13), + GPT_CGFLT_32= (7<<13), +}GPT_CGFLT_TypeDef; +/** + * @brief GPT PSCLD register + */ +typedef enum +{ + GPT_PRDLD_ZERO= (0<<16), + GPT_PRDLD_PRD= (1<<16), + GPT_PRDLD_ZERO_PRD= (2<<16), + GPT_PRDLD_NONE= (3<<16), +}GPT_PSCLD_TypeDef; +/** + * @brief GPT CAPMD register + */ +typedef enum +{ + GPT_CAPMD_CONTINUOUS= (0<<20), + GPT_CAPMD_ONCE= (1<<20), +}GPT_CAPMD_TypeDef; +/** + * @brief GPT LDARST register + */ +typedef enum +{ + GPT_LDARST_EN= (0<<23), + GPT_LDARST_DIS= (1<<23), +}GPT_LDARST_TypeDef; +/** + * @brief GPT LDBRST register + */ +typedef enum +{ + GPT_LDBRST_EN= (0<<24), + GPT_LDBRST_DIS= (1<<24), +}GPT_LDBRST_TypeDef; +/** + * @brief GPT OPM register + */ +typedef enum +{ + GPT_OPM_CONTINUOUS= (0<<6), + GPT_OPM_ONCE= (1<<6), +}GPT_OPM_TypeDef; +/** + * @brief GPT CKS register + */ +typedef enum +{ + GPT_CKS_PCLK= (0<<10), + GPT_CKS_PCLKDIV2= (1<<10), +}GPT_CKS_TypeDef; +/** + * @brief GPT WAVE register + */ +typedef enum +{ + GPT_CAPTURE_MODE= (0<<18), + GPT_WAVE_MODE= (1<<18), +}GPT_WAVE_TypeDef; +/** + * @brief GPT SYNCEN register + */ +typedef enum +{ + GPT_SYNCUSR0_EN= (1<<0), + GPT_SYNCUSR1_EN= (1<<1), + GPT_SYNCUSR2_EN= (1<<2), + GPT_SYNCUSR3_EN= (1<<3), + GPT_SYNCUSR4_EN= (1<<4), + GPT_SYNCUSR5_EN= (1<<5) +}GPT_SYNCENX_TypeDef; + +/** + * @brief GPT OSTMDX register + */ +typedef enum +{ + GPT_OSTMD0_CONTINUOUS= (0<<8), + GPT_OSTMD0_ONCE= (1<<8), + GPT_OSTMD1_CONTINUOUS= (0<<9), + GPT_OSTMD1_ONCE= (1<<9), + GPT_OSTMD2_CONTINUOUS= (0<<10), + GPT_OSTMD2_ONCE= (1<<10), + GPT_OSTMD3_CONTINUOUS= (0<<11), + GPT_OSTMD3_ONCE= (1<<11), + GPT_OSTMD4_CONTINUOUS= (0<<12), + GPT_OSTMD4_ONCE= (1<<12), + GPT_OSTMD5_CONTINUOUS= (0<<13), + GPT_OSTMD5_ONCE= (1<<13), +}GPT_OSTMDX_TypeDef; +/** + * @brief GPT TXREARM0 register + */ +typedef enum +{ + GPT_TXREARM_DIS= (0<<22), + GPT_TXREARM_T1= (1<<22), + GPT_TXREARM_T2= (2<<22), + GPT_TXREARM_T1_T2= (3<<22), +}GPT_TXREARM0_TypeDef; + +/** + * @brief GPT TRGO0SEL register + */ +typedef enum +{ + GPT_TRGO0SEL_SR0= (0<<24), + GPT_TRGO0SEL_SR1= (1<<24), + GPT_TRGO0SEL_SR2= (2<<24), + GPT_TRGO0SEL_SR3= (3<<24), + GPT_TRGO0SEL_SR4= (4<<24), + GPT_TRGO0SEL_SR5= (5<<24), + GPT_TRGO0SEL_RSVD= (6<<24), +}GPT_TRGO0SEL_TypeDef; + +/** + * @brief GPT TRGO0SEL register + */ +typedef enum +{ + GPT_TRG10SEL_SR0= (0<<27), + GPT_TRG10SEL_SR1= (1<<27), + GPT_TRG10SEL_SR2= (2<<27), + GPT_TRG10SEL_SR3= (3<<27), + GPT_TRG10SEL_SR4= (4<<27), + GPT_TRG10SEL_SR5= (5<<27), + GPT_TRG10SEL_RSVD= (6<<27), +}GPT_TRGO1SEL_TypeDef; +/** + * @brief GPT AREARM register + */ +typedef enum +{ + GPT_AREARM_DIS= (0<<30), + GPT_AREARM_ZERO= (1<<30), + GPT_AREARM_PRD= (2<<30), + GPT_AREARM_ZERO_PRD= (3<<30), +}GPT_AREARM_TypeDef; +/** + * @brief BT INT MASK SET/CLR Set + */ +typedef enum +{ + GPT_TRGEV0 = (0x01 << 0), + GPT_TRGEV1 = (0x01 << 1), + GPT_TRGEV2 = (0x01 << 2), + GPT_TRGEV3 = (0x01 << 3), +}GPT_IMSCR_TypeDef; +/** + * @brief GPT IO Set + */ +typedef enum +{ + GPT_CHA_PB01 = 0, + GPT_CHA_PA09 = 1, + GPT_CHA_PA010 = 2, + GPT_CHB_PA010 = 3, + GPT_CHB_PA011 = 4, + GPT_CHB_PB00 = 5, + GPT_CHB_PB01 = 6, +}GPT_IOSET_TypeDef; +/** + * @brief CMPA SHADOW/IMMEDIATE + */ +typedef enum +{ + GPT_CMPA_SHADOW = (0x00 << 0), + GPT_CMPA_IMMEDIATE = (0x01 << 0), +}GPT_SHDWCMPA_TypeDef; +/** + * @brief CMPB SHADOW/IMMEDIATE + */ +typedef enum +{ + GPT_CMPB_SHADOW = (0x00 << 1), + GPT_CMPB_IMMEDIATE = (0x01 << 1), +}GPT_SHDWCMPB_TypeDef; +/** + * @brief CMPA LOAD MODE + */ +typedef enum +{ + GPT_LoadA_ZERO = (0x01 << 4), + GPT_LoadA_PRD = (0x02 << 4), + GPT_LoadA_EXT_SYNC = (0x04 << 4), + GPT_LoadA_NONE = (0x00 << 4), +}GPT_LDAMD_TypeDef; +/** + * @brief CMPB LOAD MODE + */ +typedef enum +{ + GPT_LoadB_ZERO = (0x01 << 4), + GPT_LoadB_PRD = (0x02 << 4), + GPT_LoadB_EXT_SYNC = (0x04 << 4), + GPT_LoadB_NONE = (0x00 << 4), +}GPT_LDBMD_TypeDef; + +/** + * @brief WAVEA SHADOW/IMMEDIATE + */ +typedef enum +{ + GPT_WAVEA_SHADOW = (0x00 << 0), + GPT_WAVEA_IMMEDIATE = (0x01 << 0), +}GPT_SHDWAQA_TypeDef; +/** + * @brief WAVEB SHADOW/IMMEDIATE + */ +typedef enum +{ + GPT_WAVEB_SHADOW = (0x00 << 1), + GPT_WAVEB_IMMEDIATE = (0x01 << 1), +}GPT_SHDWAQB_TypeDef; +/** + * @brief ACTIVE A LOAD MODE + */ +typedef enum +{ + GPT_AQLDA_ZERO = (0x01 << 2), + GPT_AQLDA_PRD = (0x02 << 2), + GPT_AQLDA_EXT_SYNC = (0x04 << 2), + GPT_AQLDA_NONE = (0x00 << 2), +}GPT_AQLDA_TypeDef; +/** + * @brief ACTIVE B LOAD MODE + */ +typedef enum +{ + GPT_AQLDB_ZERO = (0x01 << 5), + GPT_AQLDB_PRD = (0x02 << 5), + GPT_AQLDB_EXT_SYNC = (0x04 << 5), + GPT_AQLDB_NONE = (0x00 << 5), +}GPT_AQLDB_TypeDef; +/** + * @brief CASEL MODE + */ +typedef enum +{ + GPT_CASEL_CMPA = (0x00 << 20), + GPT_CASEL_CMPB = (0x01 << 20), +}GPT_CASEL_TypeDef; +/** + * @brief CBSEL MODE + */ +typedef enum +{ + GPT_CBSEL_CMPA = (0x00 << 22), + GPT_CBSEL_CMPB = (0x01 << 22), +}GPT_CBSEL_TypeDef; +/** + * @brief CBSEL MODE + */ +typedef enum +{ + GPT_CHA = 0, + GPT_CHB = 1, +}GPT_GPTCHX_TypeDef; +/** + * @brief A FORCE ENABLE + */ +typedef enum +{ + GPT_CHA_FORCE_DIS = 0, + GPT_CHA_FORCE_EN = 1, +}GPT_CHAFORCE_TypeDef; +/** + * @brief B FORCE ENABLE + */ +typedef enum +{ + GPT_CHB_FORCE_DIS = 0<<4, + GPT_CHB_FORCE_EN = 1<<4, +}GPT_CHBFORCE_TypeDef; +/** + * @brief FORCE LOAD + */ +typedef enum +{ + GPT_FORCELD_ZERO = (0<<16), + GPT_FORCELD_PRD = (1<<16), + GPT_FORCELD__ZERO_PRD = (3<<16), +}GPT_FORCELD_TypeDef; +/** + * @brief FORCE A + */ +typedef enum +{ + GPT_FORCECHA_LOW = (1<<0), + GPT_FORCECHA_HIGH = (2<<0), +}GPT_FORCEA_TypeDef; +/** + * @brief FORCE B + */ +typedef enum +{ + GPT_FORCECHB_LOW = (1<<2), + GPT_FORCECHB_HIGH = (2<<2), +}GPT_FORCEB_TypeDef; +/** + * @brief GPT SRCSEL register + */ +typedef enum +{ + GPT_SRCSEL_DIS= (0<<0), + GPT_SRCSEL_TRGUSR0EN= (1<<0), + GPT_SRCSEL_TRGUSR1EN= (2<<0), + GPT_SRCSEL_TRGUSR2EN= (3<<0), + GPT_SRCSEL_TRGUSR3EN= (4<<0), + GPT_SRCSEL_TRGUSR4EN= (5<<0), + GPT_SRCSEL_TRGUSR5EN= (6<<0) +}GPT_SRCSEL_TypeDef; +/** + * @brief GPT BLKINV register + */ +typedef enum +{ + GPT_BLKINV_DIS= (0<<4), + GPT_BLKINV_EN= (1<<4), +}GPT_BLKINV_TypeDef; +/** + * @brief GPT CROSSMD register + */ +typedef enum +{ + GPT_ALIGNMD_PRD= (0<<5), + GPT_ALIGNMD_ZRO= (1<<5), + GPT_ALIGNMD_PRD_ZRO= (2<<5), + GPT_ALIGNMD_T1= (3<<5), +}GPT_ALIGNMD_TypeDef; +/** + * @brief GPT CROSSMD register + */ +typedef enum +{ + GPT_CROSSMD_DIS= (0<<7), + GPT_CROSSMD_EN= (1<<7), +}GPT_CROSSMD_TypeDef; +/** + * @brief GPT TRGSRC0 register + */ +typedef enum +{ + GPT_TRGSRC0_DIS= (0<<0), + GPT_TRGSRC0_ZRO= (1<<0), + GPT_TRGSRC0_PRD= (2<<0), + GPT_TRGSRC0_ZRO_PRD= (3<<0), + GPT_TRGSRC0_CMPA_INC= (4<<0), + GPT_TRGSRC0_CMPA_DEC= (5<<0), + GPT_TRGSRC0_CMPB_INC= (6<<0), + GPT_TRGSRC0_CMPB_DEC= (7<<0), + GPT_TRGSRC0_EXTSYNC= (0X0C<<0), + GPT_TRGSRC0_PE0= (0X0D<<0), + GPT_TRGSRC0_PE1= (0X0E<<0), + GPT_TRGSRC0_PE2= (0X0F<<0), +}GPT_TRGSRC0_TypeDef; +/** + * @brief GPT TRGSRC1 register + */ +typedef enum +{ + GPT_TRGSRC1_DIS= (0<<4), + GPT_TRGSRC1_ZRO= (1<<4), + GPT_TRGSRC1_PRD= (2<<4), + GPT_TRGSRC1_ZRO_PRD= (3<<4), + GPT_TRGSRC1_CMPA_INC= (4<<4), + GPT_TRGSRC1_CMPA_DEC= (5<<4), + GPT_TRGSRC1_CMPB_INC= (6<<4), + GPT_TRGSRC1_CMPB_DEC= (7<<4), + GPT_TRGSRC1_EXTSYNC= (0X0C<<4), + GPT_TRGSRC1_PE0= (0X0D<<4), + GPT_TRGSRC1_PE1= (0X0E<<4), + GPT_TRGSRC1_PE2= (0X0F<<4), +}GPT_TRGSRC1_TypeDef; + +/** + * @brief GPT CNT0INITEN register + */ +typedef enum +{ + GPT_CNT0INIT_DIS= (0<<16), + GPT_CNT0INIT_EN= (1<<16), +}GPT_CNT0INIT_TypeDef; + +/** + * @brief GPT CNT1INITEN register + */ +typedef enum +{ + GPT_CNT1INIT_DIS= (0<<17), + GPT_CNT1INIT_EN= (1<<17), +}GPT_CNT1INIT_TypeDef; + +/** + * @brief GPT ESYN0OE register + */ +typedef enum +{ + GPT_ESYN0OE_DIS= (0<<20), + GPT_ESYN0OE_EN= (1<<20), +}GPT_ESYN0OE_TypeDef; + +/** + * @brief GPT ESYN1OE register + */ +typedef enum +{ + GPT_ESYN1OE_DIS= (0<<21), + GPT_ESYN1OE_EN= (1<<21), +}GPT_ESYN1OE_TypeDef; + + +/** + * @brief GPT CNTMD selected + */ +typedef enum +{ + GPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)), + GPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)), + GPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0)) +}GPT_CNTMD_SELECTE_Type; + +/** + * @brief GPT CAPMD selected + */ +typedef enum +{ + GPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)), + GPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20)) +}GPT_CAPMD_SELECTE_Type; + +/** + * @brief GPT CMPC RST CMD + */ +typedef enum +{ + GPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)), + GPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25)) +}GPT_LOAD_CMPC_RST_CMD_Type; +/** + * @brief GPT CMPD RST CMD + */ +typedef enum +{ + GPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)), + GPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26)) +}GPT_LOAD_CMPD_RST_CMD_Type; + +#define CH_ZRO_NONE (0X00) +#define CH_ZRO_LOW (0X01) +#define CH_ZRO_HIGH (0X02) +#define CH_ZRO_REVS (0X03) +#define CH_PRD_NONE (0X00) +#define CH_PRD_LOW (0X01) +#define CH_PRD_HIGH (0X02) +#define CH_PRD_REVS (0X03) +#define CH_CAU_NONE (0X00) +#define CH_CAU_LOW (0X01) +#define CH_CAU_HIGH (0X02) +#define CH_CAU_REVS (0X03) +#define CH_CAD_NONE (0X00) +#define CH_CAD_LOW (0X01) +#define CH_CAD_HIGH (0X02) +#define CH_CAD_REVS (0X03) +#define CH_CBU_NONE (0X00) +#define CH_CBU_LOW (0X01) +#define CH_CBU_HIGH (0X02) +#define CH_CBU_REVS (0X03) +#define CH_CBD_NONE (0X00) +#define CH_CBD_LOW (0X01) +#define CH_CBD_HIGH (0X02) +#define CH_CBD_REVS (0X03) +#define CH_T1U_NONE (0X00) +#define CH_T1U_LOW (0X01) +#define CH_T1U_HIGH (0X02) +#define CH_T1U_REVS (0X03) +#define CH_T1D_NONE (0X00) +#define CH_T1D_LOW (0X01) +#define CH_T1D_HIGH (0X02) +#define CH_T1D_REVS (0X03) +#define CH_T2U_NONE (0X00) +#define CH_T2U_LOW (0X01) +#define CH_T2U_HIGH (0X02) +#define CH_T2U_REVS (0X03) +#define CH_T2D_NONE (0X00) +#define CH_T2D_LOW (0X01) +#define CH_T2D_HIGH (0X02) +#define CH_T2D_REVS (0X03) + + +#define FORCE_ACT_NONE 0 +#define FORCE_ACT_LOW 1 +#define FORCE_ACT_HIGH 2 +#define FORCE_ACT_REVS 3 + + +#define GPT_INT_TRGEV0 (0X01) +#define GPT_INT_TRGEV1 (0X01<<1) +#define GPT_INT_TRGEV2 (0X01<<2) +#define GPT_INT_TRGEV3 (0X01<<3) +#define GPT_INT_CAPLD0 (0X01<<4) +#define GPT_INT_CAPLD1 (0X01<<5) +#define GPT_INT_CAPLD2 (0X01<<6) +#define GPT_INT_CAPLD3 (0X01<<7) +#define GPT_INT_CAU (0X01<<8) +#define GPT_INT_CAD (0X01<<9) +#define GPT_INT_CBU (0X01<<10) +#define GPT_INT_CBD (0X01<<11) +#define GPT_INT_PEND (0X01<<16) + + + +#define GPT_SYNCUSR0 (0X01) +#define GPT_SYNCUSR1 (0X01<<1) +#define GPT_SYNCUSR2 (0X01<<2) +#define GPT_SYNCUSR3 (0X01<<3) +#define GPT_SYNCUSR4 (0X01<<4) +#define GPT_SYNCUSR5 (0X01<<5) +#define GPT_DEBUG_MODE (0x01<<1) + + + +extern void GPT_DeInit(void); +extern void GPT_IO_Init(GPT_IOSET_TypeDef IONAME); +extern void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX); +extern void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX, + GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX); +extern void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX); +extern void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX, + U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX); +extern void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX); +extern void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX); +extern void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX); +extern void GPT_Debug_Mode(FunctionalStatus NewState); +extern void GPT_Start(void); +extern void GPT_Stop(void); +extern void GPT_Soft_Reset(void); +extern void GPT_Cap_Rearm(void); +extern void GPT_REARM_Write(void); +extern U8_T GPT_REARM_Read(void); +extern void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA); +extern U16_T GPT_PRDR_Read(void); +extern U16_T GPT_CMPA_Read(void); +extern U16_T GPT_CMPB_Read(void); +extern U16_T GPT_CNT_Read(void); +extern void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X); +extern void GPT_INT_ENABLE(void); +extern void GPT_INT_DISABLE(void); +extern void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx, + GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx); +extern void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx, + U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA); +extern void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx, + GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt); +extern void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD + , GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD , + GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP ); +/*************************************************************/ + +#endif /**< apt32f102_gpt_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_hwdiv.h b/Source/include/apt32f102_hwdiv.h new file mode 100644 index 0000000..821f6d9 --- /dev/null +++ b/Source/include/apt32f102_hwdiv.h @@ -0,0 +1,51 @@ +/* + ****************************************************************************** + * @file apt32f102_hwdiv.h + * @author APT AE Team + * @version V1.02 + * @date 2019/04/05 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_hwdiv_H +#define _apt32f102_hwdiv_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define HWDIV_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------HWDIV value enum define-------------------------- +//-------------------------------------------------------------------------------- +#define HWDIV_UNSIGN_BIT (0X01<<0) + +extern U32_T HWDIV_Calc_Remain(void); +extern U32_T HWDIV_Calc_Quotient(void); +extern void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x); +extern void HWDIV_UNSIGN_CMD(FunctionalStatus NewState); +extern void HWDIV_DeInit(void); +extern void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x); +extern void HWDIV_Calc_float(float DIVIDENDx,float DIVISOR_x); + + + + + + + + + + +#endif /**< apt32f102_hwdiv_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_i2c.h b/Source/include/apt32f102_i2c.h new file mode 100644 index 0000000..474e5a1 --- /dev/null +++ b/Source/include/apt32f102_i2c.h @@ -0,0 +1,250 @@ +/* + ****************************************************************************** + * @file apt32f102_i2c.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_i2c_H +#define _apt32f102_i2c_H + +/* Includes ------------------------------------------------------------------*/ + +#include "apt32f102.h" + +#define BUFSIZE 32 + + +/****************************************************************************** +************************** I2C Structure Definition *************************** +******************************************************************************/ + + +/** +******************************************************************************* +@brief description CSP_I2C_T and CSP_I2C_PTR +******************************************************************************* +*/ + + +/****************************************************************************** +************************** I2C Registers Definition *************************** +******************************************************************************/ + + +/****************************************************************************** +* CR : I2C Control Register +******************************************************************************/ + #define I2C_MASTER_EN (0x01ul << 0) /**< I2C Master Mode */ + #define I2C_MASTER_DIS (0x00ul << 0) /**< I2C Master Mode */ + #define I2C_SS (0x01ul << 1) /**< I2C Standard Speed Mode */ + #define I2C_FS (0x02ul << 1) /**< I2C Fast Speed Mode */ + #define I2C_HS (0x03ul << 1) /**< I2C High Speed Mode */ + #define I2C_10BIT_SLAVE (0x01ul << 3) /**< I2C 10bit or 7bit in Slave */ + #define I2C_7BIT_SLAVE (0x00ul << 3) /**< I2C 10bit or 7bit in Slave */ + #define I2C_10BIT_MASTER (0x01ul << 4) /**< I2C 10bit or 7bit in Master */ + #define I2C_7BIT_MASTER (0x00ul << 4) /**< I2C 10bit or 7bit in Master */ + #define I2C_RESTART_EN (0x01ul << 5) /**< I2C Restart Enable */ + #define I2C_RESTART_DIS (0x00ul << 5) /**< I2C Restart Disable */ + #define I2C_SLAVE_EN (0x00ul << 6) /**< I2C Slave Enable */ + #define I2C_SLAVE_DIS (0x01ul << 6) /**< I2C Slave Disable */ + #define I2C_STOPDET_IFADD (0x01ul << 7) /**< I2C STOPDET If Addressed */ + #define I2C_STOPDET_ALS (0x00ul << 7) /**< I2C STOPDET Always */ + #define I2C_TX_EMPTY_CTRL (0x01ul << 8) /**< I2C TX_EMPTY Control */ + #define I2C_TX_EMPTY_DONE (0x00ul << 8) /**< I2C TX_EMPTY and Send Done */ + #define I2C_RX_HOLD_CTRL (0x01ul << 9) /**< I2C Rx Hold Ctrl @FIFO Full */ + #define I2C_RX_HOLD_NONE (0x00ul << 9) /**< I2C Rx Hold None @FIFO Full */ + #define I2C_STOPDET_MM (0x01ul <<10) /**< I2C STOPDET only in Master */ + #define I2C_BUSCLR_EN (0x01ul <<11) /**< I2C Enable Bus Clear Feature*/ + #define I2C_BUSCLR_DIS (0x00ul <<11) /**< I2C Disable Bus Clear Feature*/ + + +/****************************************************************************** +* DATA_CMD : I2C Data and Command Register +******************************************************************************/ + #define I2C_CMD_READ (0x01ul << 8) /**< I2C Read Command */ + #define I2C_CMD_WRITE (0x00ul << 8) /**< I2C Write Command */ + #define I2C_CMD_STOP (0x01ul << 9) /**< I2C Stop after this byte */ + #define I2C_CMD_NONESTOP (0x00ul << 9) /**< I2C None Stop When FIFO Empty or Not */ + #define I2C_CMD_RESTART0 (0x00ul <<10) /**< I2C Restart Mode0 */ + #define I2C_CMD_RESTART1 (0x01ul <<10) /**< I2C Restart Mode1 */ + //#define I2C_CMD_1stDATA (0x01ul <<11) /**< I2C First Data Byte */ + #define I2C_DATA(val) (((val) & 0xFFul) << 0) /**< Data Writing Macro */ + +/***************************************************************************** +* ENABLE : I2C Enable Register +******************************************************************************/ + #define I2C_ENABLE (0x01ul << 0) /**< I2C Enable */ + #define I2C_DISABLE (0x00ul << 0) /**< I2C Enable */ + #define I2C_ABORT (0x01ul << 1) /**< I2C Abort Transfer */ + #define I2C_ABORT_OV (0x00ul << 1) /**< I2C Abort Transfer Over or No Abort */ + //#define I2C_TX_CMD_BLOCK (0x01ul << 2) /**< I2C Block Transmission */ + #define I2C_SDA_REC_EN (0x01ul << 3) /**< I2C Enable Stuck Recovery */ + #define I2C_SDA_REC_DIS (0x00ul << 3) /**< I2C Enable Stuck Recovery */ + +/***************************************************************************** +* STATUS : I2C STATUS Register +******************************************************************************/ + #define I2C_BUSY (0x01ul << 0) /**< I2C Activity */ + #define I2C_FREE (0x00ul << 0) /**< I2C Activity */ + #define I2C_TFNF (0x01ul << 1) /**< I2C Transmit FIFO Not Full */ + #define I2C_TFNF_FULL (0x00ul << 1) /**< I2C Transmit FIFO Is Full */ + #define I2C_TFE (0x01ul << 2) /**< I2C Transmit FIFO Empty */ + #define I2C_TFE_NOT (0x00ul << 2) /**< I2C Transmit FIFO Not Empty */ + #define I2C_RFNE (0x01ul << 3) /**< I2C Receive FIFO Not Empty */ + #define I2C_RFNE_EMPTY (0x00ul << 3) /**< I2C Receive FIFO Is Empty */ + #define I2C_RFF (0x01ul << 4) /**< I2C Receive FIFO Full */ + #define I2C_MST_BUSY (0x01ul << 5) /**< I2C Master FSM Activity */ + #define I2C_MST_FREE (0x00ul << 5) /**< I2C Master FSM Free */ + #define I2C_SLV_BUSY (0x01ul << 6) /**< I2C Slave FSM Activity */ + #define I2C_SLV_FREE (0x01ul << 6) /**< I2C Slave FSM Free */ + #define I2C_REC_FREE (0x00ul << 6) /**< I2C Recovery No FAIL */ + #define I2C_REC_FAIL (0x01ul << 11) /**< I2C Recovery FAIL */ + +/***************************************************************************** +* RISR/MISR/IMSCR/ICR : I2C Interrupt Mask/Status Register +******************************************************************************/ + #define I2C_RX_UNDER (0x01ul << 0) /**< I2C Interrupt Status */ + #define I2C_RX_OVER (0x01ul << 1) /**< I2C Interrupt Status */ + #define I2C_RX_FULL (0x01ul << 2) /**< I2C Interrupt Status */ + #define I2C_TX_OVER (0x01ul << 3) /**< I2C Interrupt Status */ + #define I2C_TX_EMPTY (0x01ul << 4) /**< I2C Interrupt Status */ + #define I2C_RD_REQ (0x01ul << 5) /**< I2C Interrupt Status */ + #define I2C_TX_ABRT (0x01ul << 6) /**< I2C Interrupt Status */ + #define I2C_RX_DONE (0x01ul << 7) /**< I2C Interrupt Status */ + #define I2C_INT_BUSY (0x01ul << 8) /**< I2C Interrupt Status */ + #define I2C_STOP_DET (0x01ul << 9) /**< I2C Interrupt Status */ + #define I2C_START_DET (0x01ul <<10) /**< I2C Interrupt Status */ + #define I2C_GEN_CALL (0x01ul <<11) /**< I2C Interrupt Status */ + #define I2C_RESTART_DET (0x01ul <<12) /**< I2C Interrupt Status */ + #define I2C_MST_ON_HOLD (0x01ul <<13) /**< I2C Interrupt Status */ + #define I2C_SCL_SLOW (0x01ul <<14) /**< I2C Interrupt Status */ + + +/***************************************************************************** +* SDA_HOLD/SETUP : I2C SDA hold/setup Timing Register +******************************************************************************/ + #define I2C_TX_HOLD(val) (((val) & 0xFFul) << 0) /**< SDA TX Hold Delay */ + #define I2C_RX_HOLD(val) (((val) & 0xFFul) <<16) /**< SDA RX Hold Delay */ + #define I2C_SETUP(val) (((val) & 0xFFul) << 0) /**< SDA Setup Delay */ + +/***************************************************************************** +* I2C_SPKLEN : I2C Burr Interference Filter Control Register +******************************************************************************/ + #define I2C_SPKLEN(val) (((val) & 0xFFul) << 0) /**CEDR = (IFC_CLK_EN)) +#define DisIFCClk (IFC->CEDR = (IFC_CLK_DIS)) + +#define USER_KEY (0x5A5A5A5Aul) +#define SetUserKey (IFC->KR = (USER_KEY)) +#define StartOp (0x01ul) + +#define IFC_CLKEN (0x01ul) //IFC CLKEN +#define IFC_SWRST (0x01ul) //IFC SWRST + +#define HIDM0 ((0x0ul)<<8) //HID0 +#define HIDM1 ((0x1ul)<<8) //HID1 +#define HIDM2 ((0x2ul)<<8) //HID2 +#define HIDM3 ((0x3ul)<<8) //HID3 + +// IFC Command +#define PROGRAM (0x01ul) +#define PAGE_ERASE (0x02ul) +#define CHIP_ERASE (0x04ul) +#define OPTION_ERASE (0x05ul) +#define PEP_ENABLE (0x06ul) //预编程设定 +#define PAGE_BUF_CLR (0x07ul) //页缓存清除 +#define DIS_SWD_SET (0x0Dul) //SWD 禁止重映射 +#define EN_SWD_SET (0x0Eul) //SWD 使能重映射 +#define USER_OPTION (0x0Ful) //User OPTION操作 + +#define USER_KEY (0x5A5A5A5Aul) +#define CSP_IFC_SET_KR(ifc, val) (ifc->KR = (val)) + +// +#define StartErase (IFC->CR=(StartOp)) +#define EnChipErase (IFC->CMR=(CHIP_ERASE|HIDM1)) +#define EnPageErase (IFC->CMR=(PAGE_ERASE|HIDM0)) + +/** + * @brief IFC page address + */ +typedef enum +{ + PROM_PageAdd0 = ((CSP_REGISTER_T)0x00000000), //PROM 每页256BYTE + PROM_PageAdd1 = ((CSP_REGISTER_T)0x00000100), + PROM_PageAdd2 = ((CSP_REGISTER_T)0x00000200), + PROM_PageAdd3 = ((CSP_REGISTER_T)0x00000300), + PROM_PageAdd4 = ((CSP_REGISTER_T)0x00000400), + PROM_PageAdd5 = ((CSP_REGISTER_T)0x00000500), + PROM_PageAdd6 = ((CSP_REGISTER_T)0x00000600), + PROM_PageAdd7 = ((CSP_REGISTER_T)0x00000700), + PROM_PageAdd8 = ((CSP_REGISTER_T)0x00000800), + PROM_PageAdd9 = ((CSP_REGISTER_T)0x00000900), + + PROM_PageAdd10 = ((CSP_REGISTER_T)0x00000A00), + PROM_PageAdd11 = ((CSP_REGISTER_T)0x00000B00), + PROM_PageAdd12 = ((CSP_REGISTER_T)0x00000C00), + PROM_PageAdd13 = ((CSP_REGISTER_T)0x00000D00), + PROM_PageAdd14 = ((CSP_REGISTER_T)0x00000E00), + PROM_PageAdd15 = ((CSP_REGISTER_T)0x00000F00), + PROM_PageAdd16 = ((CSP_REGISTER_T)0x00001000), + PROM_PageAdd17 = ((CSP_REGISTER_T)0x00001100), + PROM_PageAdd18 = ((CSP_REGISTER_T)0x00001200), + PROM_PageAdd19 = ((CSP_REGISTER_T)0x00001300), + + PROM_PageAdd20 = ((CSP_REGISTER_T)0x00001400), + PROM_PageAdd21 = ((CSP_REGISTER_T)0x00001500), + PROM_PageAdd22 = ((CSP_REGISTER_T)0x00001600), + PROM_PageAdd23 = ((CSP_REGISTER_T)0x00001700), + PROM_PageAdd24 = ((CSP_REGISTER_T)0x00001800), + PROM_PageAdd25 = ((CSP_REGISTER_T)0x00001900), + PROM_PageAdd26 = ((CSP_REGISTER_T)0x00001A00), + PROM_PageAdd27 = ((CSP_REGISTER_T)0x00001B00), + PROM_PageAdd28 = ((CSP_REGISTER_T)0x00001C00), + PROM_PageAdd29 = ((CSP_REGISTER_T)0x00001D00), + + PROM_PageAdd30 = ((CSP_REGISTER_T)0x00001E00), + PROM_PageAdd31 = ((CSP_REGISTER_T)0x00001F00), + PROM_PageAdd32 = ((CSP_REGISTER_T)0x00002000), + PROM_PageAdd33 = ((CSP_REGISTER_T)0x00002100), + PROM_PageAdd34 = ((CSP_REGISTER_T)0x00002200), + PROM_PageAdd35 = ((CSP_REGISTER_T)0x00002300), + PROM_PageAdd36 = ((CSP_REGISTER_T)0x00002400), + PROM_PageAdd37 = ((CSP_REGISTER_T)0x00002500), + PROM_PageAdd38 = ((CSP_REGISTER_T)0x00002600), + PROM_PageAdd39 = ((CSP_REGISTER_T)0x00002700), + + PROM_PageAdd40 = ((CSP_REGISTER_T)0x00002800), + PROM_PageAdd41 = ((CSP_REGISTER_T)0x00002900), + PROM_PageAdd42 = ((CSP_REGISTER_T)0x00002A00), + PROM_PageAdd43 = ((CSP_REGISTER_T)0x00002B00), + PROM_PageAdd44 = ((CSP_REGISTER_T)0x00002C00), + PROM_PageAdd45 = ((CSP_REGISTER_T)0x00002D00), + PROM_PageAdd46 = ((CSP_REGISTER_T)0x00002E00), + PROM_PageAdd47 = ((CSP_REGISTER_T)0x00002F00), + PROM_PageAdd48 = ((CSP_REGISTER_T)0x00003000), + PROM_PageAdd49 = ((CSP_REGISTER_T)0x00003100), + + PROM_PageAdd50 = ((CSP_REGISTER_T)0x00003200), + PROM_PageAdd51 = ((CSP_REGISTER_T)0x00003300), + PROM_PageAdd52 = ((CSP_REGISTER_T)0x00003400), + PROM_PageAdd53 = ((CSP_REGISTER_T)0x00003500), + PROM_PageAdd54 = ((CSP_REGISTER_T)0x00003600), + PROM_PageAdd55 = ((CSP_REGISTER_T)0x00003700), + PROM_PageAdd56 = ((CSP_REGISTER_T)0x00003800), + PROM_PageAdd57 = ((CSP_REGISTER_T)0x00003900), + PROM_PageAdd58 = ((CSP_REGISTER_T)0x00003A00), + PROM_PageAdd59 = ((CSP_REGISTER_T)0x00003B00), + + PROM_PageAdd60 = ((CSP_REGISTER_T)0x00003C00), + PROM_PageAdd61 = ((CSP_REGISTER_T)0x00003D00), + PROM_PageAdd62 = ((CSP_REGISTER_T)0x00003E00), + PROM_PageAdd63 = ((CSP_REGISTER_T)0x00003F00), + PROM_PageAdd64 = ((CSP_REGISTER_T)0x00004000), + PROM_PageAdd65 = ((CSP_REGISTER_T)0x00004100), + PROM_PageAdd66 = ((CSP_REGISTER_T)0x00004200), + PROM_PageAdd67 = ((CSP_REGISTER_T)0x00004300), + PROM_PageAdd68 = ((CSP_REGISTER_T)0x00004400), + PROM_PageAdd69 = ((CSP_REGISTER_T)0x00004500), + + PROM_PageAdd70 = ((CSP_REGISTER_T)0x00004600), + PROM_PageAdd71 = ((CSP_REGISTER_T)0x00004700), + PROM_PageAdd72 = ((CSP_REGISTER_T)0x00004800), + PROM_PageAdd73 = ((CSP_REGISTER_T)0x00004900), + PROM_PageAdd74 = ((CSP_REGISTER_T)0x00004A00), + PROM_PageAdd75 = ((CSP_REGISTER_T)0x00004B00), + PROM_PageAdd76 = ((CSP_REGISTER_T)0x00004C00), + PROM_PageAdd77 = ((CSP_REGISTER_T)0x00004D00), + PROM_PageAdd78 = ((CSP_REGISTER_T)0x00004E00), + PROM_PageAdd79 = ((CSP_REGISTER_T)0x00004F00), + + PROM_PageAdd80 = ((CSP_REGISTER_T)0x00005000), + PROM_PageAdd81 = ((CSP_REGISTER_T)0x00005100), + PROM_PageAdd82 = ((CSP_REGISTER_T)0x00005200), + PROM_PageAdd83 = ((CSP_REGISTER_T)0x00005300), + PROM_PageAdd84 = ((CSP_REGISTER_T)0x00005400), + PROM_PageAdd85 = ((CSP_REGISTER_T)0x00005500), + PROM_PageAdd86 = ((CSP_REGISTER_T)0x00005600), + PROM_PageAdd87 = ((CSP_REGISTER_T)0x00005700), + PROM_PageAdd88 = ((CSP_REGISTER_T)0x00005800), + PROM_PageAdd89 = ((CSP_REGISTER_T)0x00005900), + + PROM_PageAdd90 = ((CSP_REGISTER_T)0x00005A00), + PROM_PageAdd91 = ((CSP_REGISTER_T)0x00005B00), + PROM_PageAdd92 = ((CSP_REGISTER_T)0x00005C00), + PROM_PageAdd93 = ((CSP_REGISTER_T)0x00005D00), + PROM_PageAdd94 = ((CSP_REGISTER_T)0x00005E00), + PROM_PageAdd95 = ((CSP_REGISTER_T)0x00005F00), + PROM_PageAdd96 = ((CSP_REGISTER_T)0x00006000), + PROM_PageAdd97 = ((CSP_REGISTER_T)0x00006100), + PROM_PageAdd98 = ((CSP_REGISTER_T)0x00006200), + PROM_PageAdd99 = ((CSP_REGISTER_T)0x00006300), + + PROM_PageAdd100 = ((CSP_REGISTER_T)0x00006400), + PROM_PageAdd101 = ((CSP_REGISTER_T)0x00006500), + PROM_PageAdd102 = ((CSP_REGISTER_T)0x00006600), + PROM_PageAdd103 = ((CSP_REGISTER_T)0x00006700), + PROM_PageAdd104 = ((CSP_REGISTER_T)0x00006800), + PROM_PageAdd105 = ((CSP_REGISTER_T)0x00006900), + PROM_PageAdd106 = ((CSP_REGISTER_T)0x00006A00), + PROM_PageAdd107 = ((CSP_REGISTER_T)0x00006B00), + PROM_PageAdd108 = ((CSP_REGISTER_T)0x00006C00), + PROM_PageAdd109 = ((CSP_REGISTER_T)0x00006D00), + + PROM_PageAdd110 = ((CSP_REGISTER_T)0x00006E00), + PROM_PageAdd111 = ((CSP_REGISTER_T)0x00006F00), + PROM_PageAdd112 = ((CSP_REGISTER_T)0x00007000), + PROM_PageAdd113 = ((CSP_REGISTER_T)0x00007100), + PROM_PageAdd114 = ((CSP_REGISTER_T)0x00007200), + PROM_PageAdd115 = ((CSP_REGISTER_T)0x00007300), + PROM_PageAdd116 = ((CSP_REGISTER_T)0x00007400), + PROM_PageAdd117 = ((CSP_REGISTER_T)0x00007500), + PROM_PageAdd118 = ((CSP_REGISTER_T)0x00007600), + PROM_PageAdd119 = ((CSP_REGISTER_T)0x00007700), + + PROM_PageAdd120 = ((CSP_REGISTER_T)0x00007800), + PROM_PageAdd121 = ((CSP_REGISTER_T)0x00007900), + PROM_PageAdd122 = ((CSP_REGISTER_T)0x00007A00), + PROM_PageAdd123 = ((CSP_REGISTER_T)0x00007B00), + PROM_PageAdd124 = ((CSP_REGISTER_T)0x00007C00), + PROM_PageAdd125 = ((CSP_REGISTER_T)0x00007D00), + PROM_PageAdd126 = ((CSP_REGISTER_T)0x00007E00), + PROM_PageAdd127 = ((CSP_REGISTER_T)0x00007F00), + PROM_PageAdd128 = ((CSP_REGISTER_T)0x00008000), + PROM_PageAdd129 = ((CSP_REGISTER_T)0x00008100), + + PROM_PageAdd130 = ((CSP_REGISTER_T)0x00008200), + PROM_PageAdd131 = ((CSP_REGISTER_T)0x00008300), + PROM_PageAdd132 = ((CSP_REGISTER_T)0x00008400), + PROM_PageAdd133 = ((CSP_REGISTER_T)0x00008500), + PROM_PageAdd134 = ((CSP_REGISTER_T)0x00008600), + PROM_PageAdd135 = ((CSP_REGISTER_T)0x00008700), + PROM_PageAdd136 = ((CSP_REGISTER_T)0x00008800), + PROM_PageAdd137 = ((CSP_REGISTER_T)0x00008900), + PROM_PageAdd138 = ((CSP_REGISTER_T)0x00008A00), + PROM_PageAdd139 = ((CSP_REGISTER_T)0x00008B00), + + PROM_PageAdd140 = ((CSP_REGISTER_T)0x00008C00), + PROM_PageAdd141 = ((CSP_REGISTER_T)0x00008D00), + PROM_PageAdd142 = ((CSP_REGISTER_T)0x00008E00), + PROM_PageAdd143 = ((CSP_REGISTER_T)0x00008F00), + PROM_PageAdd144 = ((CSP_REGISTER_T)0x00009000), + PROM_PageAdd145 = ((CSP_REGISTER_T)0x00009100), + PROM_PageAdd146 = ((CSP_REGISTER_T)0x00009200), + PROM_PageAdd147 = ((CSP_REGISTER_T)0x00009300), + PROM_PageAdd148 = ((CSP_REGISTER_T)0x00009400), + PROM_PageAdd149 = ((CSP_REGISTER_T)0x00009500), + + PROM_PageAdd150 = ((CSP_REGISTER_T)0x00009600), + PROM_PageAdd151 = ((CSP_REGISTER_T)0x00009700), + PROM_PageAdd152 = ((CSP_REGISTER_T)0x00009800), + PROM_PageAdd153 = ((CSP_REGISTER_T)0x00009900), + PROM_PageAdd154 = ((CSP_REGISTER_T)0x00009A00), + PROM_PageAdd155 = ((CSP_REGISTER_T)0x00009B00), + PROM_PageAdd156 = ((CSP_REGISTER_T)0x00009C00), + PROM_PageAdd157 = ((CSP_REGISTER_T)0x00009D00), + PROM_PageAdd158 = ((CSP_REGISTER_T)0x00009E00), + PROM_PageAdd159 = ((CSP_REGISTER_T)0x00009F00), + + PROM_PageAdd160 = ((CSP_REGISTER_T)0x0000A000), + PROM_PageAdd161 = ((CSP_REGISTER_T)0x0000A100), + PROM_PageAdd162 = ((CSP_REGISTER_T)0x0000A200), + PROM_PageAdd163 = ((CSP_REGISTER_T)0x0000A300), + PROM_PageAdd164 = ((CSP_REGISTER_T)0x0000A400), + PROM_PageAdd165 = ((CSP_REGISTER_T)0x0000A500), + PROM_PageAdd166 = ((CSP_REGISTER_T)0x0000A600), + PROM_PageAdd167 = ((CSP_REGISTER_T)0x0000A700), + PROM_PageAdd168 = ((CSP_REGISTER_T)0x0000A800), + PROM_PageAdd169 = ((CSP_REGISTER_T)0x0000A900), + + PROM_PageAdd170 = ((CSP_REGISTER_T)0x0000AA00), + PROM_PageAdd171 = ((CSP_REGISTER_T)0x0000AB00), + PROM_PageAdd172 = ((CSP_REGISTER_T)0x0000AC00), + PROM_PageAdd173 = ((CSP_REGISTER_T)0x0000AD00), + PROM_PageAdd174 = ((CSP_REGISTER_T)0x0000AE00), + PROM_PageAdd175 = ((CSP_REGISTER_T)0x0000AF00), + PROM_PageAdd176 = ((CSP_REGISTER_T)0x0000B000), + PROM_PageAdd177 = ((CSP_REGISTER_T)0x0000B100), + PROM_PageAdd178 = ((CSP_REGISTER_T)0x0000B200), + PROM_PageAdd179 = ((CSP_REGISTER_T)0x0000B300), + + PROM_PageAdd180 = ((CSP_REGISTER_T)0x0000B400), + PROM_PageAdd181 = ((CSP_REGISTER_T)0x0000B500), + PROM_PageAdd182 = ((CSP_REGISTER_T)0x0000B600), + PROM_PageAdd183 = ((CSP_REGISTER_T)0x0000B700), + PROM_PageAdd184 = ((CSP_REGISTER_T)0x0000B800), + PROM_PageAdd185 = ((CSP_REGISTER_T)0x0000B900), + PROM_PageAdd186 = ((CSP_REGISTER_T)0x0000BA00), + PROM_PageAdd187 = ((CSP_REGISTER_T)0x0000BB00), + PROM_PageAdd188 = ((CSP_REGISTER_T)0x0000BC00), + PROM_PageAdd189 = ((CSP_REGISTER_T)0x0000BD00), + + PROM_PageAdd190 = ((CSP_REGISTER_T)0x0000BE00), + PROM_PageAdd191 = ((CSP_REGISTER_T)0x0000BF00), + PROM_PageAdd192 = ((CSP_REGISTER_T)0x0000C000), + PROM_PageAdd193 = ((CSP_REGISTER_T)0x0000C100), + PROM_PageAdd194 = ((CSP_REGISTER_T)0x0000C200), + PROM_PageAdd195 = ((CSP_REGISTER_T)0x0000C300), + PROM_PageAdd196 = ((CSP_REGISTER_T)0x0000C400), + PROM_PageAdd197 = ((CSP_REGISTER_T)0x0000C500), + PROM_PageAdd198 = ((CSP_REGISTER_T)0x0000C600), + PROM_PageAdd199 = ((CSP_REGISTER_T)0x0000C700), + + PROM_PageAdd200 = ((CSP_REGISTER_T)0x0000C800), + PROM_PageAdd201 = ((CSP_REGISTER_T)0x0000C900), + PROM_PageAdd202 = ((CSP_REGISTER_T)0x0000CA00), + PROM_PageAdd203 = ((CSP_REGISTER_T)0x0000CB00), + PROM_PageAdd204 = ((CSP_REGISTER_T)0x0000CC00), + PROM_PageAdd205 = ((CSP_REGISTER_T)0x0000CD00), + PROM_PageAdd206 = ((CSP_REGISTER_T)0x0000CE00), + PROM_PageAdd207 = ((CSP_REGISTER_T)0x0000CF00), + PROM_PageAdd208 = ((CSP_REGISTER_T)0x0000D000), + PROM_PageAdd209 = ((CSP_REGISTER_T)0x0000D100), + + PROM_PageAdd210 = ((CSP_REGISTER_T)0x0000D200), + PROM_PageAdd211 = ((CSP_REGISTER_T)0x0000D300), + PROM_PageAdd212 = ((CSP_REGISTER_T)0x0000D400), + PROM_PageAdd213 = ((CSP_REGISTER_T)0x0000D500), + PROM_PageAdd214 = ((CSP_REGISTER_T)0x0000D600), + PROM_PageAdd215 = ((CSP_REGISTER_T)0x0000D700), + PROM_PageAdd216 = ((CSP_REGISTER_T)0x0000D800), + PROM_PageAdd217 = ((CSP_REGISTER_T)0x0000D900), + PROM_PageAdd218 = ((CSP_REGISTER_T)0x0000DA00), + PROM_PageAdd219 = ((CSP_REGISTER_T)0x0000DB00), + + PROM_PageAdd220 = ((CSP_REGISTER_T)0x0000DC00), + PROM_PageAdd221 = ((CSP_REGISTER_T)0x0000DD00), + PROM_PageAdd222 = ((CSP_REGISTER_T)0x0000DE00), + PROM_PageAdd223 = ((CSP_REGISTER_T)0x0000DF00), + PROM_PageAdd224 = ((CSP_REGISTER_T)0x0000E000), + PROM_PageAdd225 = ((CSP_REGISTER_T)0x0000E100), + PROM_PageAdd226 = ((CSP_REGISTER_T)0x0000E200), + PROM_PageAdd227 = ((CSP_REGISTER_T)0x0000E300), + PROM_PageAdd228 = ((CSP_REGISTER_T)0x0000E400), + PROM_PageAdd229 = ((CSP_REGISTER_T)0x0000E500), + + PROM_PageAdd230 = ((CSP_REGISTER_T)0x0000E600), + PROM_PageAdd231 = ((CSP_REGISTER_T)0x0000E700), + PROM_PageAdd232 = ((CSP_REGISTER_T)0x0000E800), + PROM_PageAdd233 = ((CSP_REGISTER_T)0x0000E900), + PROM_PageAdd234 = ((CSP_REGISTER_T)0x0000EA00), + PROM_PageAdd235 = ((CSP_REGISTER_T)0x0000EB00), + PROM_PageAdd236 = ((CSP_REGISTER_T)0x0000EC00), + PROM_PageAdd237 = ((CSP_REGISTER_T)0x0000ED00), + PROM_PageAdd238 = ((CSP_REGISTER_T)0x0000EE00), + PROM_PageAdd239 = ((CSP_REGISTER_T)0x0000EF00), + + PROM_PageAdd240 = ((CSP_REGISTER_T)0x0000F000), + PROM_PageAdd241 = ((CSP_REGISTER_T)0x0000F100), + PROM_PageAdd242 = ((CSP_REGISTER_T)0x0000F200), + PROM_PageAdd243 = ((CSP_REGISTER_T)0x0000F300), + PROM_PageAdd244 = ((CSP_REGISTER_T)0x0000F400), + PROM_PageAdd245 = ((CSP_REGISTER_T)0x0000F50), + PROM_PageAdd246 = ((CSP_REGISTER_T)0x0000F600), + PROM_PageAdd247 = ((CSP_REGISTER_T)0x0000F700), + PROM_PageAdd248 = ((CSP_REGISTER_T)0x0000F800), + PROM_PageAdd249 = ((CSP_REGISTER_T)0x0000F900), + + PROM_PageAdd250 = ((CSP_REGISTER_T)0x0000FA00), + PROM_PageAdd251 = ((CSP_REGISTER_T)0x0000FB00), + PROM_PageAdd252 = ((CSP_REGISTER_T)0x0000FC00), + PROM_PageAdd253 = ((CSP_REGISTER_T)0x0000FD00), + PROM_PageAdd254 = ((CSP_REGISTER_T)0x0000FE00), + PROM_PageAdd255 = ((CSP_REGISTER_T)0x0000FF00), + + DROM_PageAdd0 = ((CSP_REGISTER_T)0x10000000), //DROM 每页64BYTE + DROM_PageAdd1 = ((CSP_REGISTER_T)0x10000040), + DROM_PageAdd2 = ((CSP_REGISTER_T)0x10000080), + DROM_PageAdd3 = ((CSP_REGISTER_T)0x100000C0), + DROM_PageAdd4 = ((CSP_REGISTER_T)0x10000100), + DROM_PageAdd5 = ((CSP_REGISTER_T)0x10000140), + DROM_PageAdd6 = ((CSP_REGISTER_T)0x10000180), + DROM_PageAdd7 = ((CSP_REGISTER_T)0x100001C0), + DROM_PageAdd8 = ((CSP_REGISTER_T)0x10000200), + DROM_PageAdd9 = ((CSP_REGISTER_T)0x10000240), + + DROM_PageAdd10 = ((CSP_REGISTER_T)0x10000280), + DROM_PageAdd11 = ((CSP_REGISTER_T)0x100002C0), + DROM_PageAdd12 = ((CSP_REGISTER_T)0x10000300), + DROM_PageAdd13 = ((CSP_REGISTER_T)0x10000340), + DROM_PageAdd14 = ((CSP_REGISTER_T)0x10000380), + DROM_PageAdd15 = ((CSP_REGISTER_T)0x100003C0), + DROM_PageAdd16 = ((CSP_REGISTER_T)0x10000400), + DROM_PageAdd17 = ((CSP_REGISTER_T)0x10000440), + DROM_PageAdd18 = ((CSP_REGISTER_T)0x10000480), + DROM_PageAdd19 = ((CSP_REGISTER_T)0x100004C0), + + DROM_PageAdd20 = ((CSP_REGISTER_T)0x10000500), + DROM_PageAdd21 = ((CSP_REGISTER_T)0x10000540), + DROM_PageAdd22 = ((CSP_REGISTER_T)0x10000580), + DROM_PageAdd23 = ((CSP_REGISTER_T)0x100005C0), + DROM_PageAdd24 = ((CSP_REGISTER_T)0x10000600), + DROM_PageAdd25 = ((CSP_REGISTER_T)0x10000640), + DROM_PageAdd26 = ((CSP_REGISTER_T)0x10000680), + DROM_PageAdd27 = ((CSP_REGISTER_T)0x100006C0), + DROM_PageAdd28 = ((CSP_REGISTER_T)0x10000700), + DROM_PageAdd29 = ((CSP_REGISTER_T)0x10000740), + + DROM_PageAdd30 = ((CSP_REGISTER_T)0x10000780), + DROM_PageAdd31 = ((CSP_REGISTER_T)0x100007C0) +}IFC_ROMSELETED_TypeDef; + +/** + * @brief IFC INT mode + */ +typedef enum +{ + ERS_END_INT = (0x01ul), + RGM_END_INT = ((0x01ul)<<1), + PEP_END_INT = ((0x01ul)<<2), + PROT_ERR_INT = ((0x01ul)<<12), + UDEF_ERR_INT = ((0x01ul)<<13), + ADDR_ERR_INT = ((0x01ul)<<14), + OVW_ERR_INT = ((0x01ul)<<15) +}IFC_INT_TypeDef; + + +extern void ChipErase(void); +extern void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAd); +extern void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x); +extern void IFC_Int_Enable(void); +extern void IFC_Int_Disable(void); +extern void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry); +extern void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry); +extern void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint); +extern void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint); +extern volatile unsigned int R_INT_FlashAdd; +extern volatile unsigned char f_Drom_write_complete; +extern volatile unsigned char f_Drom_writing; +extern volatile unsigned char ifc_step; +extern void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry); +extern void ReadDataArry_U32(unsigned int RdStartAdd,unsigned int DataLength,volatile U32_T *DataArryPoint); +#endif /**< apt32f102_ifc_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ diff --git a/Source/include/apt32f102_lpt.h b/Source/include/apt32f102_lpt.h new file mode 100644 index 0000000..7226993 --- /dev/null +++ b/Source/include/apt32f102_lpt.h @@ -0,0 +1,280 @@ +/* + ****************************************************************************** + * @file apt32f102_lpt.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_lpt_H +#define _apt32f102_lpt_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define LPT_RESET_VALUE (0x00000000) +//-------------------------------------------------------------------------------- +//-----------------------------LPT value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief LPT CLK EN register + */ +typedef enum +{ + LPTCLK_DIS = 0, + LPTCLK_EN = 1, +}LPT_CLK_TypeDef; +/** + * @brief LPT CLK source register + */ +typedef enum +{ + LPT_PCLK_DIV4= (0<<2), + LPT_ISCLK = (1<<2), + LPT_IMCLK_DIV4 = (2<<2), + LPT_EMCLK = (3<<2), + LPT_IN_RISE = (4<<2), + LPT_IN_FALL = (5<<2), +}LPT_CSS_TypeDef; +/** + * @brief LPT START SHADOW register + */ +typedef enum +{ + LPT_SHADOW = (0<<6), + LPT_IMMEDIATE= (1<<6), +}LPT_SHDWSTP_TypeDef; +/** + * @brief LPT CLK div register + */ +typedef enum +{ + LPT_PSC_DIV0= 0, + LPT_PSC_DIV2= 1, + LPT_PSC_DIV4= 2, + LPT_PSC_DIV8= 3, + LPT_PSC_DIV16= 4, + LPT_PSC_DIV32= 5, + LPT_PSC_DIV64= 6, + LPT_PSC_DIV128= 7, + LPT_PSC_DIV256= 8, + LPT_PSC_DIV512= 9, + LPT_PSC_DIV1024= 0X0A, + LPT_PSC_DIV2048= 0X0B, + LPT_PSC_DIV4096= 0X0C, +}LPT_PSCDIV_TypeDef; +/** + * @brief LPT START SYN EN register + */ +typedef enum +{ + LPT_SWSYNDIS= (0<<2), + LPT_SWSYNEN= (1<<2), +}LPT_SWSYN_TypeDef; +/** + * @brief LPT IO stop status register + */ +typedef enum +{ + LPT_IDLE_Z= (0<<3), //High-impedance output + LPT_IDLE_LOW= (1<<3), +}LPT_IDLEST_TypeDef; +/** + * @brief LPT PRDLD register + */ +typedef enum +{ + LPT_PRDLD_IMMEDIATELY= (0<<4), + LPT_PRDLD_DUTY_END= (1<<4), +}LPT_PRDLD_TypeDef; +/** + * @brief LPT POL register + */ +typedef enum +{ + LPT_POL_HIGH= (0<<5), + LPT_POL_LOW= (1<<5), +}LPT_POL_TypeDef; +/** + * @brief LPT OPM register + */ +typedef enum +{ + LPT_OPM_CONTINUOUS= (0<<6), + LPT_OPM_ONCE= (1<<6), +}LPT_OPM_TypeDef; +/** + * @brief LPT FLTIPSCLD register + */ +typedef enum +{ + LPT_FLTIPSCLD_NULL= (0<<10), + LPT_FLTIPSCLD_EN= (1<<10), +}LPT_FLTIPSCLD_TypeDef; +/** + * @brief LPT FLTDEB register + */ +typedef enum +{ + LPT_FLTDEB_00= (0<<13), + LPT_FLTDEB_02= (1<<13), + LPT_FLTDEB_03= (2<<13), + LPT_FLTDEB_04= (3<<13), + LPT_FLTDEB_06= (4<<13), + LPT_FLTDEB_08= (5<<13), + LPT_FLTDEB_16= (6<<13), + LPT_FLTDEB_32= (7<<13), +}LPT_FLTDEB_TypeDef; +/** + * @brief LPT PSCLD register + */ +typedef enum +{ + LPT_PSCLD_0= (0<<16), //PSCR + LPT_PSCLD_1= (1<<16), +}LPT_PSCLD_TypeDef; +/** + * @brief LPT CMPLD register + */ +typedef enum +{ + LPT_CMPLD_IMMEDIATELY= (0<<17), + LPT_CMPLD_DUTY_END= (1<<17), +}LPT_CMPLD_TypeDef; +/** + * @brief LPT TRGENX register + */ +typedef enum +{ + LPT_TRGEN_DIS= (0<<0), + LPT_TRGEN_EN= (1<<0), +}LPT_TRGENX_TypeDef; +/** + * @brief LPT OSTMDX register + */ +typedef enum +{ + LPT_OSTMD_CONTINUOUS= (0<<8), + LPT_OSTMD_ONCE= (1<<8), +}LPT_OSTMDX_TypeDef; +/** + * @brief LPT AREARM register + */ +typedef enum +{ + LPT_AREARM_DIS= (0<<30), + LPT_AREARM_EN= (1<<30), +}LPT_AREARM_TypeDef; +/** + * @brief LPT SRCSEL register + */ +typedef enum +{ + LPT_SRCSEL_DIS= (0<<0), + LPT_SRCSEL_EN= (1<<0), +}LPT_SRCSEL_TypeDef; +/** + * @brief LPT BLKINV register + */ +typedef enum +{ + LPT_BLKINV_DIS= (0<<4), + LPT_BLKINV_EN= (1<<4), +}LPT_BLKINV_TypeDef; +/** + * @brief LPT CROSSMD register + */ +typedef enum +{ + LPT_CROSSMD_DIS= (0<<7), + LPT_CROSSMD_EN= (1<<7), +}LPT_CROSSMD_TypeDef; +/** + * @brief LPT TRGSRC0 register + */ +typedef enum +{ + LPT_TRGSRC0_DIS= (0<<0), + LPT_TRGSRC0_ZRO= (1<<0), + LPT_TRGSRC0_PRD= (2<<0), + LPT_TRGSRC0_ZRO_PRD= (3<<0), + LPT_TRGSRC0_CMP= (4<<0), +}LPT_TRGSRC0_TypeDef; +/** + * @brief LPT ESYN0OE register + */ +typedef enum +{ + LPT_ESYN0OE_DIS= (0<<20), + LPT_ESYN0OE_EN= (1<<20), +}LPT_ESYN0OE_TypeDef; + +/** + * @brief LPT INT MASK SET/CLR Set + */ +typedef enum +{ + LPT_TRGEV0 = (0x01 << 0), + LPT_MATCH = (0x01 << 1), + LPT_PEND = (0x01 << 2), +}LPT_IMSCR_TypeDef; + +/** + * @brief LPT IO Set + */ +typedef enum +{ + LPT_OUT_PA09 = 0, + LPT_OUT_PB01 = 1, + LPT_IN_PA10 = 2, +}LPT_IOSET_TypeDef; + + +#define LPT_DEBUG_MODE (0X01<<1) + + +extern void LPT_DeInit(void); +extern void LPT_IO_Init(LPT_IOSET_TypeDef IONAME); +extern void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX, + LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX); +extern void LPT_Debug_Mode(FunctionalStatus NewState); +extern void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA); +extern void LPT_CNT_Write(U16_T CNT_DATA); +extern U16_T LPT_PRDR_Read(void); +extern U16_T LPT_CMP_Read(void); +extern U16_T LPT_CNT_Read(void); +extern void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX, + LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX); +extern void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX); +extern void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X, + LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA); +extern void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA); +extern void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA); +extern void LPT_Soft_Trigger(void); +extern void LPT_Start(void); +extern void LPT_Stop(void); +extern void LPT_Soft_Reset(void); +extern void LPT_REARM_Write(void); +extern U8_T LPT_REARM_Read(void); +extern void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X); +extern void LPT_INT_ENABLE(void); +extern void LPT_INT_DISABLE(void); + + + +/*************************************************************/ + +#endif /**< apt32f102_lpt_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_rtc.h b/Source/include/apt32f102_rtc.h new file mode 100644 index 0000000..746da50 --- /dev/null +++ b/Source/include/apt32f102_rtc.h @@ -0,0 +1,254 @@ +/* + ****************************************************************************** + * @file apt32f102_interrupt.c + * @author APT AE Team + * @version V1.10 + * @date 2021/08/25 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_rtc_H +#define _apt32f102_rtc_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" +/****************************************************************************** +************************* rtc Registers Definition ************************* +******************************************************************************/ +/** @addtogroup RTC Registers Reset Value + * @{ + */ + +#define RTC_TIMR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_DATR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_CR_RST ((CSP_REGISTER_T)0x00000001) +#define RTC_CCR_RST ((CSP_REGISTER_T)0x00800000) +#define RTC_ALRAR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_ALRBR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_SSR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_CAL_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_IMCR_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_EVTRG_RST ((CSP_REGISTER_T)0x00000000) +#define RTC_EVPS_RST ((CSP_REGISTER_T)0x00000000) + +//RTC KEY +#define RTC_KEY (0XCA53ul) + +/** + * @brief RTC DIVS Control + */ +typedef enum +{ + CLKSRC_ISOSC = (CSP_REGISTER_T)(0x00ul<<24), + CLKSRC_IMOSC_4div = (CSP_REGISTER_T)(0x01ul<<24), + CLKSRC_EMOSC = (CSP_REGISTER_T)(0x02ul<<24), + CLKSRC_EMOSC_4div = (CSP_REGISTER_T)(0x03ul<<24) +}RTC_CLKSRC_TypeDef; + + +/** + * @brief RTC INT register + */ +typedef enum +{ + //RISR IMCR MISR ICR + ALRA_INT = ((CSP_REGISTER_T)(0x01ul << 0)), + ALRB_INT = ((CSP_REGISTER_T)(0x01ul << 1)), + CPRD_INT = ((CSP_REGISTER_T)(0x01ul << 2)), + RTC_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 3)), + RTC_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 4)) +}RTC_INT_TypeDef; + +/** + * @brief RTC Alarm SEC MIN DAY mask + */ + typedef enum +{ + Alarm_Second_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 7)), + Alarm_Second_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 7)), +} RTC_Alarm_Second_mask_TypeDef; + typedef enum +{ + Alarm_Minute_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 15)), + Alarm_Minute_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 15)), +} RTC_Alarm_Minute_mask_TypeDef; + typedef enum +{ + Alarm_Hour_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 23)), + Alarm_Hour_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 23)), +} RTC_Alarm_Hour_mask_TypeDef; + typedef enum +{ + Alarm_DataOrWeek_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 31)), + Alarm_DataOrWeek_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 31)) +} RTC_Alarm_DataOrWeek_mask_TypeDef; ; +/** + * @brief RTC Alarm week data select + */ + typedef enum +{ + Alarm_data_selecte = ((CSP_REGISTER_T)(0x00ul << 30)), + Alarm_week_selecte = ((CSP_REGISTER_T)(0x01ul << 30)) +} RTC_Alarm_WeekData_select_TypeDef; +/** + * @brief RTC Alarm Register select + */ + typedef enum +{ + Alarm_A = 0, + Alarm_B = 1 +}RTC_Alarm_Register_select_TypeDef; + +/** + * @brief RTC Alarm io output mode + */ + typedef enum +{ + Alarm_A_pulse_output = ((CSP_REGISTER_T)(0x00ul << 10)), + Alarm_A_High = ((CSP_REGISTER_T)(0x01ul << 10)), + Alarm_A_Low = ((CSP_REGISTER_T)(0x02ul << 10)), + Alarm_B_pulse_output = ((CSP_REGISTER_T)(0x04ul << 10)), + Alarm_B_High = ((CSP_REGISTER_T)(0x05ul << 10)), + Alarm_B_Low = ((CSP_REGISTER_T)(0x06ul << 10)), +}Rtc_Output_Mode_TypeDef; +/** + * @brief RTC Alarm IO clock outpu + */ + typedef enum +{ + COSEL_Cali_512hz = ((CSP_REGISTER_T)(0x00ul << 8)), + COSEL_Cali_1hz = ((CSP_REGISTER_T)(0x01ul << 8)), + COSEL_NoCali_512hz = ((CSP_REGISTER_T)(0x02ul << 8)), + COSEL_NoCali_1hz = ((CSP_REGISTER_T)(0x03ul << 8)), +} +Rtc_ClockOutput_Mode_TypeDef; +/** + * @brief RTC AlarmA cmd select + */ + typedef enum +{ + Alarm_A_EN = ((CSP_REGISTER_T)(0x01ul << 3)), + Alarm_A_DIS = ((CSP_REGISTER_T)(0x00ul << 3)), + +}RTC_AlarmA_CMD_TypeDef; +/** + * @brief RTC AlarmB cmd select + */ + typedef enum +{ + Alarm_B_EN = ((CSP_REGISTER_T)(0x01ul << 4)), + Alarm_B_DIS = ((CSP_REGISTER_T)(0x00ul << 4)), +}RTC_AlarmB_CMD_TypeDef; +/** + * @brief RTC FMT mode select + */ + typedef enum +{ + RTC_24H = ((CSP_REGISTER_T)(0x00ul << 5)), + RTC_12H = ((CSP_REGISTER_T)(0x01ul << 5)), +}RTC_FMT_MODE_TypeDef; +/** + * @brief RTC CPRD select + */ + typedef enum +{ + CPRD_NONE = ((CSP_REGISTER_T)(0x00ul << 13)), + CPRD_05S = ((CSP_REGISTER_T)(0x01ul << 13)), + CPRD_1S = ((CSP_REGISTER_T)(0x02ul << 13)), + CPRD_1MIN = ((CSP_REGISTER_T)(0x03ul << 13)), + CPRD_1HOUR = ((CSP_REGISTER_T)(0x04ul << 13)), + CPRD_1DAY = ((CSP_REGISTER_T)(0x05ul << 13)), + CPRD_1MONTH = ((CSP_REGISTER_T)(0x06ul << 13)), +}RTC_CPRD_TypeDef; +/** + * @brief RTC EVTRG TRGSRC0 SET + */ + typedef enum +{ + RTC_EVTRG_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x00ul )), + RTC_EVTRG_TRGSRC0_AlarmA = ((CSP_REGISTER_T)(0x01ul )), + RTC_EVTRG_TRGSRC0_AlarmB = ((CSP_REGISTER_T)(0x02ul )), + RTC_EVTRG_TRGSRC0_AlarmAB = ((CSP_REGISTER_T)(0x03ul )), + RTC_EVTRG_TRGSRC0_CPRD = ((CSP_REGISTER_T)(0x04ul )), +}RTC_EVTRG_TRGSRC0_TypeDef; +/** + * @brief RTC EVTRG TRGSRC1 SET + */ + typedef enum +{ + RTC_EVTRG_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x00ul<<4 )), + RTC_EVTRG_TRGSRC1_AlarmA = ((CSP_REGISTER_T)(0x01ul<<4 )), + RTC_EVTRG_TRGSRC1_AlarmB = ((CSP_REGISTER_T)(0x02ul<<4 )), + RTC_EVTRG_TRGSRC1_AlarmAB = ((CSP_REGISTER_T)(0x03ul<<4 )), + RTC_EVTRG_TRGSRC1_CPRD = ((CSP_REGISTER_T)(0x04ul<<4 )), +}RTC_EVTRG_TRGSRC1_TypeDef; + typedef enum +{ + RTC_TRGSRC0_EN = ((CSP_REGISTER_T)(0x00ul<<20 )), + RTC_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x01ul<<20 )), + RTC_TRGSRC1_EN = ((CSP_REGISTER_T)(0x00ul<<21 )), + RTC_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x01ul<<21 )), +}RTC_TRGSRCX_CMD_TypeDef; +typedef struct +{ + volatile uint8_t u8Second; ///<闹钟分钟 + volatile uint8_t u8Minute; ///<闹钟分钟 + volatile uint8_t u8Hour; ///<闹钟小时 + volatile uint8_t u8WeekOrData; ///<闹钟周 +}RTC_Alarmset_T; + +typedef struct +{ + volatile uint8_t u8Second; ///<秒 + volatile uint8_t u8Minute; ///<分 + volatile uint8_t u8Hour; ///<时 + volatile uint8_t u8DayOfWeek; ///<周 + volatile uint8_t u8Day; ///<日 + volatile uint8_t u8Month; ///<月 + volatile uint8_t u8Year; ///<年 +} RTC_time_t; + + +/** @addtogroup RTC_Exported_functions + * @{ + */ +extern void RTC_RST_VALUE(void); +extern void RTCCLK_CONFIG(U16_T DIVS , U16_T DIVA , RTC_CLKSRC_TypeDef CLKSRC_X); +extern void RTC_ALM_IO_SET(Rtc_Output_Mode_TypeDef Rtc_Output_Mode_x ); +extern void RTC_TIMR_DATR_SET(RTC_time_t *RTC_TimeDate); +extern void RTC_TIMR_DATR_Read(RTC_time_t *RTC_TimeDate); +extern void RTC_Alarm_TIMR_DATR_SET(RTC_Alarm_Register_select_TypeDef Alarm_x , RTC_Alarmset_T *RTC_AlarmA , RTC_Alarm_Second_mask_TypeDef RTC_Alarm_Second_x , + RTC_Alarm_Minute_mask_TypeDef RTC_Alarm_Minute_x , RTC_Alarm_Hour_mask_TypeDef RTC_Alarm_Hour_x, + RTC_Alarm_DataOrWeek_mask_TypeDef RTC_Alarm_DataOrWeek_x, + RTC_Alarm_WeekData_select_TypeDef Alarm_x_selecte); +extern void RTC_Function_Config(RTC_FMT_MODE_TypeDef RTC_FMT_MODE , RTC_CPRD_TypeDef RTC_CPRD_x , Rtc_ClockOutput_Mode_TypeDef Rtc_ClockOutput_x); +extern void RTC_TRGSRC0_Config(RTC_EVTRG_TRGSRC0_TypeDef RTC_EVTRG_TRGSRC0_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev0Prd); +extern void RTC_TRGSRC1_Config(RTC_EVTRG_TRGSRC1_TypeDef RTC_EVTRG_TRGSRC1_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev1Prd); +extern void RTC_TRGSRC0_SWFTRG(void); +extern void RTC_TRGSRC1_SWFTRG(void); +extern void RTC_Start(void); +extern void RTC_Stop(void); +extern void RTC_AlarmA_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmA); +extern void RTC_AlarmB_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmB); +extern void RTC_Int_Enable(RTC_INT_TypeDef RTC_X_INT); +extern void RTC_Int_Disable(RTC_INT_TypeDef RTC_X_INT); +extern void RTC_Vector_Int_Enable(void); +extern void RTC_Vector_Int_Disable(void); +extern void RTC_WakeUp_Enable(void); +extern void RTC_WakeUp_Disable(void); +extern RTC_time_t RTC_TimeDate_buf; +extern RTC_Alarmset_T RTC_AlarmA_buf; +extern RTC_Alarmset_T RTC_AlarmB_buf; + +#endif /**< apt32f102_rtc_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_sio.h b/Source/include/apt32f102_sio.h new file mode 100644 index 0000000..e090013 --- /dev/null +++ b/Source/include/apt32f102_sio.h @@ -0,0 +1,211 @@ +/* + ****************************************************************************** + * @file apt32f102_sio.h + * @author APT AE Team + * @version V1.08 + * @date 2021/06/21 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_sio_H +#define _apt32f102_sio_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + + +#define SIO_RESET_VALUE (0x00000000) + + +//-------------------------------------------------------------------------------- +//-----------------------------SIO value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief SIO IO group register + */ +typedef enum +{ + SIO_PA02 = 0, + SIO_PA03 = 1, + SIO_PA012 = 2, + SIO_PB01 = 3, +}SIO_IOG_TypeDef; +/** + * @brief SIO CLK EN register + */ +typedef enum +{ + SIOCLK_DIS = 0, + SIOCLK_EN = 1, +}SIO_CLK_TypeDef; +/** + * @brief SIO TXDEB register + */ +typedef enum +{ + SIO_TXDEB_1CYCLE = (0<<1), + SIO_TXDEB_2CYCLE = (1<<1), + SIO_TXDEB_3CYCLE = (2<<1), + SIO_TXDEB_4CYCLE = (3<<1), + SIO_TXDEB_5CYCLE = (4<<1), + SIO_TXDEB_6CYCLE = (5<<1), + SIO_TXDEB_7CYCLE = (6<<1), + SIO_TXDEB_8CYCLE = (7<<1), +}SIO_RXDEB_TypeDef; +/** + * @brief SIO IO IDLE STATUS register + */ +typedef enum +{ + SIO_IDLE_Z = 0, + SIO_IDLE_HIGH = 1, + SIO_IDLE_LOW = 2, +}SIO_IDLEST_TypeDef; +/** + * @brief SIO TX DIR register + */ +typedef enum +{ + SIO_TX_LSB = (0<<2), + SIO_TX_MSB = (1<<2), +}SIO_TXDIR_TypeDef; +/** + * @brief SIO LENOBH register + */ +typedef enum +{ + SIO_OBH_1BIT = (0<<8), + SIO_OBH_2BIT = (1<<8), + SIO_OBH_3BIT = (2<<8), + SIO_OBH_4BIT = (3<<8), + SIO_OBH_5BIT = (4<<8), + SIO_OBH_6BIT = (5<<8), + SIO_OBH_7BIT = (6<<8), + SIO_OBH_8BIT = (7<<8), +}SIO_LENOBH_TypeDef; +/** + * @brief SIO LENOBL register + */ +typedef enum +{ + SIO_OBL_1BIT = (0<<11), + SIO_OBL_2BIT = (1<<11), + SIO_OBL_3BIT = (2<<11), + SIO_OBL_4BIT = (3<<11), + SIO_OBL_5BIT = (4<<11), + SIO_OBL_6BIT = (5<<11), + SIO_OBL_7BIT = (6<<11), + SIO_OBL_8BIT = (7<<11), +}SIO_LENOBL_TypeDef; +/** + * @brief SIO RX EDGE register + */ +typedef enum +{ + SIO_RX_RISE = 0, + SIO_RX_FALL = 1, + SIO_RX_RISE_FALL = 2, +}SIO_BSTSEL_TypeDef; +/** + * @brief SIO RX TRG MODE register + */ +typedef enum +{ + SIO_RX_DEB = (0<<3), + SIO_RX_FLT30NS = (1<<3), +}SIO_TRGMODE_TypeDef; +/** + * @brief SIO RX ALIGNEN register + */ +typedef enum +{ + SIO_RX_ALIGNDIS = (0<<28), + SIO_RX_ALIGNEN = (1<<28), +}SIO_ALIGNEN_TypeDef; +/** + * @brief SIO RX DIR register + */ +typedef enum +{ + SIO_RX_MSB = (0<<29), + SIO_RX_LSB = (1<<29), +}SIO_RXDIR_TypeDef; +/** + * @brief SIO RX MODE register + */ +typedef enum +{ + SIO_RMODE0 = (0<<30), + SIO_RMODE1 = (1<<30), +}SIO_RXMODE_TypeDef; +/** + * @brief SIO BREAKEN register + */ +typedef enum +{ + SIO_BREAKDIS = (0<<0), + SIO_BREAKEN = (1<<0), +}SIO_BREAKEN_TypeDef; +/** + * @brief SIO BREAKLVL register + */ +typedef enum +{ + SIO_BREAKLVL_LOW = (0<<1), + SIO_BREAKLVL_HIGH = (1<<1), +}SIO_BREAKLVL_TypeDef; +/** + * @brief SIO TORSTEN register + */ +typedef enum +{ + SIO_TORSTDIS = (0<<15), + SIO_TORSTEN = (1<<15), +}SIO_TORSTEN_TypeDef; +/** + * @brief LPT INT MASK SET/CLR Set + */ +typedef enum +{ + SIO_TXDNE = (0x01 << 0), + SIO_RXDNE = (0x01 << 1), + SIO_TXBUFEMPT = (0x01 << 2), + SIO_RXBUFEMPT = (0x01 << 3), + SIO_BREAK = (0x01 << 4), + SIO_TIME = (0x01 << 5), +}SIO_IMSCR_TypeDef; + + + +#define TX_D0 (0X00) +#define TX_D1 (0X01) +#define TX_DL (0X02) +#define TX_DH (0X03) + + +extern void SIO_DeInit(void); +extern void SIO_IO_Init(SIO_IOG_TypeDef IOGx); +extern void SIO_TX_Init(SIO_CLK_TypeDef CLKX,U8_T TCKPRSX); +extern void SIO_TX_Configure(SIO_IDLEST_TypeDef IDLEX,SIO_TXDIR_TypeDef TXDIRX,U8_T TXBUFLENX,U8_T TXCNTX,U8_T D0DURX,U8_T D1DURX,SIO_LENOBH_TypeDef LENOBHX, + SIO_LENOBL_TypeDef LENOBLX,U8_T HSQX,U8_T LSQX); +extern void SIO_TXBUF_Set(U8_T D30,U8_T D28,U8_T D26,U8_T D24,U8_T D22,U8_T D20,U8_T D18,U8_T D16, + U8_T D14,U8_T D12,U8_T D10,U8_T D08,U8_T D06,U8_T D04,U8_T D02,U8_T D00); +extern void SIO_RX_Init(SIO_CLK_TypeDef CLKX,SIO_RXDEB_TypeDef RXDEBX,U8_T DEBCKSX); +extern void SIO_RX_Configure0(SIO_BSTSEL_TypeDef BSTSELX,SIO_TRGMODE_TypeDef TRGMX,U8_T SPLCNTX,U8_T EXTRACTX,U8_T HITHRX, + SIO_ALIGNEN_TypeDef ALIGNX,SIO_RXDIR_TypeDef RXDIRX,SIO_RXMODE_TypeDef RXMODEX,U8_T RXLENX,U8_T RXBUFLENX,U8_T RXKPRSX); +extern void SIO_RX_Configure1(SIO_BREAKEN_TypeDef BREAKX,SIO_BREAKLVL_TypeDef BREAKLVLX,U8_T BREKCNTX,SIO_TORSTEN_TypeDef TORSTX,U8_T TOCNTX); +extern void SIO_ConfigInterrupt_CMD(FunctionalStatus NewState,SIO_IMSCR_TypeDef SIO_IMSCR_X); +extern void SIO_INT_ENABLE(void); +extern void SIO_INT_DISABLE(void); +/*************************************************************/ + +#endif /**< apt32f102_sio_H */ \ No newline at end of file diff --git a/Source/include/apt32f102_spi.h b/Source/include/apt32f102_spi.h new file mode 100644 index 0000000..0829ccd --- /dev/null +++ b/Source/include/apt32f102_spi.h @@ -0,0 +1,293 @@ +/* + ****************************************************************************** + * @file apt32f102_spi.c + * @author APT AE Team + * @version V1.025 + * @date 2020/06/08 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_spi_H +#define _apt32f102_spi_H +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +/****************************************************************************** +************************** spi Registers Definition **************************** +******************************************************************************/ +/******************************************************************************* +* SSPCR0 : Control Register 0 +*******************************************************************************/ +#define SSP_DSS(val) (((val-1) & 0x0Ful) << 0) /**< Data Size Select */ +#define SSP_FRF(val) (((val) & 0x03ul) << 4) /**< Frame Format */ +#define SSP_SPO (0x01ul << 6) /**< SSPCLK Polarity */ +#define SSP_SPH (0x01ul << 7) /**< SSPCLK Phase */ +#define SSP_SCR(val) (((val) & 0x0FFul) << 8) /**< Serial Clock Rate */ + +/******************************************************************************* +* SSPCR1 : Control Register 1 +*******************************************************************************/ +#define SSP_LBM (0x01ul << 0) /**< Loopback mode */ +#define SSP_SSE (0x01ul << 1) /**< Synchronous Serial Port Enable */ +#define SSP_MS (0x01ul << 2) /**< Master or Slave Mode Select */ +#define SSP_SOD (0x01ul << 3) /**< Slave Mode Output Disable */ +#define SSP_RXIFLSELFRF(val) (((val) & 0x07ul) << 4) + /**< Receive interrupt FIFO level select */ + +/******************************************************************************* +* SSPDR : Data Register +*******************************************************************************/ +#define SSP_DATA(val) (((val) & 0x0FFFF) << 0) /**< Transmit/Receive FIFO */ + +/******************************************************************************* +* SSPSR : Status Register +*******************************************************************************/ +#define SSP_TFE (0x01ul << 0) /**< Transmit FIFO Empty */ +#define SSP_TNF (0x01ul << 1) /**< Transmit FIFO is not Full */ +#define SSP_RNE (0x01ul << 2) /**< Receive is not Empty */ +#define SSP_RFF (0x01ul << 3) /**< Receive FIFO Full */ +#define SSP_BSY (0x01ul << 4) /**< PrimeCell SSP Busy Flag */ + +/******************************************************************************* +* SSPCPSR : Clock prescale register +*******************************************************************************/ +#define SSP_CPSDVSR(val) (((val) & 0x0FF) << 0) /**< Clock Prescale Devisor */ + +/******************************************************************************* +* SSPIMSC : Interrupt mask set and clear register +*******************************************************************************/ +#define SSP_RORIM (0x01ul << 0) /**< Receive Overrun Interrupt Mask */ +#define SSP_RTIM (0x01ul << 1) /**< Receive Timeout Interrupt Mask */ +#define SSP_RXIM (0x01ul << 2) /**< Receive FIFO Interrupt Mask */ +#define SSP_TXIM (0x01ul << 3) /**< Transmit FIFO interrupt Mask */ + +/******************************************************************************* +* SSPRIS : Raw interrupt status register +*******************************************************************************/ +#define SSP_RORRIS (0x01ul << 0) + /**< Gives the Raw Interrupt Status of the SSPRORINTR Interrupt */ +#define SSP_RTRIS (0x01ul << 1) + /**< Gives the raw interrupt state of the SSPRTINTR interrupt */ +#define SSP_RXRIS (0x01ul << 2) + /**< Gives the raw interrupt state of the SSPRXINTR interrupt */ +#define SSP_TXRIS (0x01ul << 3) + /**< Gives the raw interrupt state of the SSPTXINTR interrupt */ + +/******************************************************************************* +* SSPMIS : Masked interrupt status register +*******************************************************************************/ +#define SSP_RORRIS (0x01ul << 0) +/**CR0 = (val & 0xFFFFFFCFul)) + +/** Get CR0 register */ +#define CSP_SSP_GET_CR0(ssp) ((ssp)->CR0) + +/** Set CR1 register */ +#define CSP_SSP_SET_CR1(ssp, val) ((ssp)->CR1 = (val & 0xFFFF000Ful)) + +/** Get CR1 register */ +#define CSP_SSP_GET_CR1(ssp) ((ssp)->CR1) + +/** Set DR register */ +#define CSP_SSP_SET_DR(ssp, val) ((ssp)->DR = (val)) + +/** Get DR register */ +#define CSP_SSP_GET_DR(ssp) ((ssp)->DR) + +/** Get SR register */ +#define CSP_SSP_GET_SR(ssp) ((ssp)->SR) + +/** Set CPSR register */ +#define CSP_SSP_SET_CPSR(ssp, val) ((ssp)->CPSR = (val & 0xFFFF00FFul)) + +/** Get CPSR register */ +#define CSP_SSP_GET_CPSR(ssp) ((ssp)->CPSR) + +/** Set IMSC register */ +#define CSP_SSP_SET_IMSCR(ssp, val) ((ssp)->IMSC = (val & 0xFFFF000Ful)) + +/** Get IMSC register */ +#define CSP_SSP_GET_IMSCR(ssp) ((ssp)->IMSCR) + +/** Get RIS register */ +#define CSP_SSP_GET_RISR(ssp) ((ssp)->RISR) + +/** Get MIS register */ +#define CSP_SSP_GET_MISR(ssp) ((ssp)->MISR + +/** Set ICR register */ +#define CSP_SSP_SET_ICR(ssp, val) ((ssp)->ICR = (val & 0xFFFF0003ul)) + + + +/** @addtogroup spi Registers RST Value + * @{ + */ +#define SPI_CR0_RST (0x00000000) /**< CR0 reset value */ +#define SPI_CR1_RST (0x00000000) /**< CR1 reset value */ +#define SPI_DR_RST (0x00000000) /**< DR reset value */ +#define SPI_SR_RST (0x00000003) /**< SR reset value */ +#define SPI_CPSR_RST (0x00000000) /**< CPSR reset value */ +#define SPI_IMSCR_RST (0x00000000) /**< IMSCR reset value */ +#define SPI_RISR_RST (0x00000008) /**< RISR reset value */ +#define SPI_MISR_RST (0x00000000) /**< MISR reset value */ +#define SPI_ICR_RST (0x00000000) /**< ICR reset value */ + +/** + * @brief SPI INT MASK SET/CLR Set + */ +typedef enum +{ + SPI_PORIM = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Receive overflow Interrupt */ + SPI_RTIM = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Receive timeout Interrupt */ + SPI_RXIM = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Receive FIFO Interrupt */ + SPI_TXIM = ((CSP_REGISTER_T)(0x01ul << 3)) /**< transmit FIFO Interrupt */ +}SPI_IMSCR_TypeDef; + +/** + * @brief SPI IO selection + */ +typedef enum +{ + SPI_G0 = 0, + SPI_G1 = 1, + SPI_G2 = 2 +}SPI_IO_TypeDef; + +/** + * @brief SPI Data Size selection + */ +typedef enum +{ + SPI_DATA_SIZE_4BIT = 3, + SPI_DATA_SIZE_5BIT = 4, + SPI_DATA_SIZE_6BIT = 5, + SPI_DATA_SIZE_7BIT = 6, + SPI_DATA_SIZE_8BIT = 7, + SPI_DATA_SIZE_9BIT = 8, + SPI_DATA_SIZE_10BIT = 9, + SPI_DATA_SIZE_11BIT = 10, + SPI_DATA_SIZE_12BIT = 11, + SPI_DATA_SIZE_13BIT = 12, + SPI_DATA_SIZE_14BIT = 13, + SPI_DATA_SIZE_15BIT = 14, + SPI_DATA_SIZE_16BIT = 15 +}SPI_DATA_SIZE_TypeDef; + +/** + * @brief SPI SPO selection + */ +typedef enum +{ + SPI_SPO_0 = 0, + SPI_SPO_1 = 1 +}SPI_SPO_TypeDef; + +/** + * @brief SPI SPH selection + */ +typedef enum +{ + SPI_SPH_0 = 0, + SPI_SPH_1 = 1 +}SPI_SPH_TypeDef; + +/** + * @brief SPI LBM selection + */ +typedef enum +{ + SPI_LBM_0 = 0, + SPI_LBM_1 = 1 +}SPI_LBM_TypeDef; + +/** + * @brief SPI RXIFLSEL selection + */ +typedef enum +{ + SPI_RXIFLSEL_1_8 = 0x01, + SPI_RXIFLSEL_1_4 = 0x02, + SPI_RXIFLSEL_1_2 = 0x04 +}SPI_RXIFLSEL_TypeDef; +/****************************************************************************** +********************** SPI External Functions Declaration ********************** +******************************************************************************/ +extern void SPI_DeInit(void); +extern void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP); +extern void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR ); +extern void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR); +extern void SPI_WRITE_BYTE(U16_T wdata); +extern void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth); +extern void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X); +extern void SPI_Int_Enable(void); +extern void SPI_Int_Disable(void); +extern void SPI_Wakeup_Enable(void); +extern void SPI_Wakeup_Disable(void); + +#endif /**< apt32f102_spi_H */ + +/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_syscon.h b/Source/include/apt32f102_syscon.h new file mode 100644 index 0000000..1088d2e --- /dev/null +++ b/Source/include/apt32f102_syscon.h @@ -0,0 +1,524 @@ +/* + ****************************************************************************** + * @file main.c + * @author APT AE Team + * @version V1.09 + * @date 2021/07/30 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_syscon_H +#define _apt32f102_syscon_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" +/****************************************************************************** +************************* syscon Registers Definition ************************* +******************************************************************************/ +/** @addtogroup SYSCON Registers Reset Value + * @{ + */ + +#define SYSCON_IDCCR_RST ((CSP_REGISTER_T)0x00000001) +#define SYSCON_GCER_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_GCDR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_GCSR_RST ((CSP_REGISTER_T)0x00081103) +#define SYSCON_CKST_RST ((CSP_REGISTER_T)0x00000103) +#define SYSCON_RAMCHK_RST ((CSP_REGISTER_T)0x0000ffff) +#define SYSCON_EFLCHK_RST ((CSP_REGISTER_T)(0X0<<24)|0xffffff) +#define SYSCON_SCLKCR_RST ((CSP_REGISTER_T)0xD22Dul<<16) +#define SYSCON_PCLKCR_RST ((CSP_REGISTER_T)0x00000100) +#define SYSCON_PCER0_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_PCDR0_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_PCSR0_RST ((CSP_REGISTER_T)0x005107d1) +#define SYSCON_PCER1_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_PCDR1_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_PCSR1_RST ((CSP_REGISTER_T)0x3023f80) +#define SYSCON_OSTR_RST ((CSP_REGISTER_T)0x70ff3bff) +#define SYSCON_LVDCR_RST ((CSP_REGISTER_T)0x0000000a) +#define SYSCON_CLCR_RST ((CSP_REGISTER_T)0x00000100) +#define SYSCON_PWRCR_RST ((CSP_REGISTER_T)0x141f1f00) +#define SYSCON_IMER_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_IMDR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_IMCR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_IAR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_ICR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_RISR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_MISR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIRT_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIFT_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIER_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIDR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIMR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIAR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXICR_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EXIRS_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_IWDCR_RST ((CSP_REGISTER_T)0x0000070C) +#define SYSCON_IWDCNT_RST ((CSP_REGISTER_T)0x000003fe) +#define SYSCON_PWROPT_RST ((CSP_REGISTER_T)0x00004040) +#define SYSCON_EVTRG_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EVPS_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_EVSWF_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_UREG0_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_UREG1_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_UREG2_RST ((CSP_REGISTER_T)0x00000000) +#define SYSCON_UREG3_RST ((CSP_REGISTER_T)0x00000000) + +//SCLKCR +#define SYSCLK_KEY (0xD22Dul<<16) + +//PCLK CONTROL +#define PCLK_KEY (0xC33Cul<<16) + +//IDCCR +#define CLKEN (0X01ul) +#define CPUFTRST_EN (0X00<<1) +#define CPUFTRST_DIS (0XA<<1) +#define SWRST (0X01ul<<7) +#define IDCCR_KEY (0xE11Eul<<16) + +//LVDCR +#define LVDFLAG (0x01ul<<15) //0: VDD is higher than LVD threshold selected with INTDET_LVL bits. 1: VDD is lower than LVD threshold selected with INTDET_LVL bits +#define LVD_KEY (0xB44Bul<<16) + +//IECR IEDR IAR ICR IMSR RISR ISR +//Interrupt Enable/Disable/Active/Clear Control Register +//Interrupt Masking/Raw Interrupt/Masked Status Register +#define ISOSC_ST (0x01ul) +#define IMOSC_ST (0x01ul<<1) +#define ESOSC_ST (0x01ul<<2) +#define EMOSC_ST (0x01ul<<3) +#define HFOSC_ST (0x01ul<<4) +#define SYSCLK_ST (0x01ul<<7) +#define IWDT_INT_ST (0x01ul<<8) +#define WKI_INT_ST (0x01ul<<9) +#define RAMERRINT_ST (0X01ul<<10) +#define LVD_INT_ST (0x01ul<<11) +#define HWD_ERR_ST (0X01ul<<12) +#define EFL_ERR_ST (0X01ul<<13) +#define OPTERR_INT (0X01ul<<14) +#define EM_CMLST_ST (0x01ul<<18) +#define EM_EVTRG0_ST (0x01ul<<19) +#define EM_EVTRG1_ST (0x01ul<<20) +#define EM_EVTRG2_ST (0x01ul<<21) +#define EM_EVTRG3_ST (0x01ul<<22) +#define CMD_ERR_ST (0x01ul<<29) + +//RSR +//SYSCON Reset Status Register +#define PORST (0X01ul) +#define LVRRST (0X01ul<<1) +#define EXTRST (0X01ul<<2) +#define ALVRST (0X01ul<<3) +#define IWDRST (0X01ul<<4) +#define EMCMRST (0X01ul<<6) +#define CPURSTREQ (0X01ul<<7) +#define SWRST_RSR (0X01ul<<8) +#define CPUFAULT_RSR (0X01ul<<9) +#define SRAM_RSR (0X01ul<<11) +#define EFL_ERR (0X01ul<<12) +#define WWDTRST (0X01ul<<13) + +//IWDCR +#define Check_IWDT_BUSY (0x01ul<<12) //Indicates the independent watchdog operation +#define IWDT_KEY (0x8778ul<<16) + +//IWDCNT +#define CLR_IWDT (0x5aul<<24) + +//IWDEDR +#define Enable_IWDT (0x0) +#define Disable_IWDT (0x55aa) +#define IWDTEDR_KEY (0x7887ul<<16) + +#define CORET_IRQ 0 +#define SYSCON_IRQ 1 +#define IFC_IRQ 2 +#define ADC_IRQ 3 +#define EPT0_IRQ 4 +#define WWDT_IRQ 6 +#define EXI0_IRQ 7 +#define EXI1_IRQ 8 +#define GPT0_IRQ 9 +#define RTC_IRQ 12 +#define UART0_IRQ 13 +#define UART1_IRQ 14 +#define UART2_IRQ 15 +#define I2C_IRQ 17 +#define SPI_IRQ 19 +#define SIO_IRQ 20 +#define EXI2_IRQ 21 +#define EXI3_IRQ 22 +#define EXI4_IRQ 23 +#define CA_IRQ 24 +#define TKEY_IRQ 25 +#define LPT_IRQ 26 +#define BT0_IRQ 28 +#define BT1_IRQ 29 + +/** + * @brief SYSCON General Control + */ +typedef enum +{ + ENDIS_ISOSC = (CSP_REGISTER_T)(0x01ul), + ENDIS_IMOSC = (CSP_REGISTER_T)(0x01ul<<1), + ENDIS_EMOSC = (CSP_REGISTER_T)(0x01ul<<3), + ENDIS_HFOSC = (CSP_REGISTER_T)(0x01ul<<4), + ENDIS_IDLE_PCLK = (CSP_REGISTER_T)(0x01ul<<8), + ENDIS_SYSTICK = (CSP_REGISTER_T)(0x01ul<<11) +}SYSCON_General_CMD_TypeDef; + +/** + * @brief Selected SYSCON CLK + */ +typedef enum +{ + SYSCLK_IMOSC = (CSP_REGISTER_T)0x0ul, //IMOSC selected + SYSCLK_EMOSC = (CSP_REGISTER_T)0x1ul, //EMOSC selected + SYSCLK_HFOSC = (CSP_REGISTER_T)0x2ul, //HFOSC selected + SYSCLK_ISOSC = (CSP_REGISTER_T)0x4ul //ISOSC selected +}SystemCLK_TypeDef; +/** + * @brief SYSCON CLK Div + */ +typedef enum +{ + HCLK_DIV_1 = (CSP_REGISTER_T)(0x1ul<<8), + HCLK_DIV_2 = (CSP_REGISTER_T)(0x2ul<<8), + HCLK_DIV_3 = (CSP_REGISTER_T)(0x3ul<<8), + HCLK_DIV_4 = (CSP_REGISTER_T)(0x4ul<<8), + HCLK_DIV_5 = (CSP_REGISTER_T)(0x5ul<<8), + HCLK_DIV_6 = (CSP_REGISTER_T)(0x6ul<<8), + HCLK_DIV_7 = (CSP_REGISTER_T)(0x7ul<<8), + HCLK_DIV_8 = (CSP_REGISTER_T)(0x8ul<<8), + HCLK_DIV_12 = (CSP_REGISTER_T)(0x9ul<<8), + HCLK_DIV_16 = (CSP_REGISTER_T)(0xAul<<8), + HCLK_DIV_24 = (CSP_REGISTER_T)(0xBul<<8), + HCLK_DIV_32 = (CSP_REGISTER_T)(0xCul<<8), + HCLK_DIV_64 = (CSP_REGISTER_T)(0xDul<<8), + HCLK_DIV_128 = (CSP_REGISTER_T)(0xEul<<8), + HCLK_DIV_256 = (CSP_REGISTER_T)(0xFul<<8) +}SystemCLK_Div_TypeDef; + +/** + * @brief PCLK Div + */ +typedef enum +{ + PCLK_DIV_1 = (CSP_REGISTER_T)(0x00ul<<8), + PCLK_DIV_2 = (CSP_REGISTER_T)(0x01ul<<8), + PCLK_DIV_4 = (CSP_REGISTER_T)(0x02ul<<8), + PCLK_DIV_8 = (CSP_REGISTER_T)(0x04ul<<8), + PCLK_DIV_16 = (CSP_REGISTER_T)(0x08ul<<8) +}PCLK_Div_TypeDef; + +/** + * @brief LVD enable and disable + */ +typedef enum +{ + ENABLE_LVDEN = (CSP_REGISTER_T)0x00, //Power down LVD module + DISABLE_LVDEN = (CSP_REGISTER_T)0x0a //Power down LVD module +}X_LVDEN_TypeDef; + +/** + * @brief Detection voltage level to trigger the LVD interrupt + */ +typedef enum +{ + INTDET_LVL_2_1V = (CSP_REGISTER_T)(0X00ul<<8), //2.1V + INTDET_LVL_2_4V = (CSP_REGISTER_T)(0X01ul<<8), //2.4V + INTDET_LVL_2_7V = (CSP_REGISTER_T)(0X02ul<<8), //2.7V + INTDET_LVL_3_0V = (CSP_REGISTER_T)(0X03ul<<8), //3.0V + INTDET_LVL_3_3V = (CSP_REGISTER_T)(0X04ul<<8), //3.3V + INTDET_LVL_3_6V = (CSP_REGISTER_T)(0X05ul<<8), //3.6V + INTDET_LVL_3_9V = (CSP_REGISTER_T)(0X06ul<<8), //3.9V +}INTDET_LVL_X_TypeDef; + +/** + * @brief Detection voltage level to generate reset + */ +typedef enum +{ + RSTDET_LVL_1_9V = (CSP_REGISTER_T)(0X00ul<<12), //1.9V + RSTDET_LVL_2_2V = (CSP_REGISTER_T)(0X01ul<<12), //2.2V + RSTDET_LVL_2_5V = (CSP_REGISTER_T)(0X02ul<<12), //2.5V + RSTDET_LVL_2_8V = (CSP_REGISTER_T)(0X03ul<<12), //2.8V + RSTDET_LVL_3_1V = (CSP_REGISTER_T)(0X04ul<<12), //3.1V + RSTDET_LVL_3_4V = (CSP_REGISTER_T)(0X05ul<<12), //3.4V + RSTDET_LVL_3_7V = (CSP_REGISTER_T)(0X06ul<<12), //3.7V + RSTDET_LVL_4_0V = (CSP_REGISTER_T)(0X07ul<<12) //4.0V +}RSTDET_LVL_X_TypeDef; + +/** + * @brief Detection voltage level to trigger the LVD interrupt + */ +typedef enum +{ + ENABLE_LVD_INT = (CSP_REGISTER_T)(0X01ul<<11), //ENABLE LVD INT + DISABLE_LVD_INT = (CSP_REGISTER_T)(0X00ul<<11) //DISABLE LVD INT +}X_LVD_INT_TypeDef; + +/** + * @brief EXI PIN + */ +typedef enum +{ + EXI_PIN0 = (CSP_REGISTER_T)(0X01ul), + EXI_PIN1 = (CSP_REGISTER_T)(0X01ul<<1), + EXI_PIN2 = (CSP_REGISTER_T)(0X01ul<<2), + EXI_PIN3 = (CSP_REGISTER_T)(0X01ul<<3), + EXI_PIN4 = (CSP_REGISTER_T)(0X01ul<<4), + EXI_PIN5 = (CSP_REGISTER_T)(0X01ul<<5), + EXI_PIN6 = (CSP_REGISTER_T)(0X01ul<<6), + EXI_PIN7 = (CSP_REGISTER_T)(0X01ul<<7), + EXI_PIN8 = (CSP_REGISTER_T)(0X01ul<<8), + EXI_PIN9 = (CSP_REGISTER_T)(0X01ul<<9), + EXI_PIN10 = (CSP_REGISTER_T)(0X01ul<<10), + EXI_PIN11 = (CSP_REGISTER_T)(0X01ul<<11), + EXI_PIN12 = (CSP_REGISTER_T)(0X01ul<<12), + EXI_PIN13 = (CSP_REGISTER_T)(0X01ul<<13), + EXI_PIN14 = (CSP_REGISTER_T)(0X01ul<<14), + EXI_PIN15 = (CSP_REGISTER_T)(0X01ul<<15), + EXI_PIN16 = (CSP_REGISTER_T)(0X01ul<<16), + EXI_PIN17 = (CSP_REGISTER_T)(0X01ul<<17), + EXI_PIN18 = (CSP_REGISTER_T)(0X01ul<<18), + EXI_PIN19 = (CSP_REGISTER_T)(0X01ul<<19), +}SYSCON_EXIPIN_TypeDef; + +/** + * @brief EXT register + */ +typedef enum +{ + _EXIRT = 0, + _EXIFT = 1, +}EXI_tringer_mode_TypeDef; + + +/** + * @brief SYSON IWDT TIME SET + */ +typedef enum +{ + IWDT_TIME_125MS = (CSP_REGISTER_T)(0x00ul<<8), //IWDT_TIME 0x00fff + IWDT_TIME_250MS = (CSP_REGISTER_T)(0x01ul<<8), //IWDT_TIME 0x01fff + IWDT_TIME_500MS = (CSP_REGISTER_T)(0x02ul<<8), //IWDT_TIME 0x03fff + IWDT_TIME_1S = (CSP_REGISTER_T)(0x03ul<<8), //IWDT_TIME 0x07fff + IWDT_TIME_2S = (CSP_REGISTER_T)(0x04ul<<8), //IWDT_TIME 0x0ffff //2M ISOSC 2sec + IWDT_TIME_3S = (CSP_REGISTER_T)(0x05ul<<8), //IWDT_TIME 0x16fff + IWDT_TIME_4S = (CSP_REGISTER_T)(0x06ul<<8), //IWDT_TIME 0x1ffff + IWDT_TIME_8S = (CSP_REGISTER_T)(0x07ul<<8) //IWDT_TIME 0x3ffff +}IWDT_TIME_TypeDef; + +/** + * @brief SYSON IWDT TIME DIV SET + */ +typedef enum +{ + IWDT_INTW_DIV_1 = (0x00ul<<2), //1/8 of IWDT_TIME + IWDT_INTW_DIV_2 = (0x01ul<<2), //2/8 of IWDT_TIME + IWDT_INTW_DIV_3 = (0x02ul<<2), //3/8 of IWDT_TIME + IWDT_INTW_DIV_4 = (0x03ul<<2), //4/8 of IWDT_TIME + IWDT_INTW_DIV_5 = (0x04ul<<2), //5/8 of IWDT_TIME + IWDT_INTW_DIV_6 = (0x05ul<<2), //6/8 of IWDT_TIME + IWDT_INTW_DIV_7 = (0x06ul<<2) //7/8 of IWDT_TIME +}IWDT_TIMEDIV_TypeDef; + +/** + * @brief IMOSC SELECTE SET + */ +typedef enum +{ + IMOSC_SELECTE_5556K = (0x00ul<<0), + IMOSC_SELECTE_4194K = (0x01ul<<0), + IMOSC_SELECTE_2097K = (0x02ul<<0), + IMOSC_SELECTE_131K = (0x03ul<<0) +}IMOSC_SELECTE_TypeDef; + +/** + * @brief HFOSC SELECTE SET + */ +typedef enum +{ + HFOSC_SELECTE_48M = (0x0ul<<4), + HFOSC_SELECTE_24M = (0x1ul<<4), + HFOSC_SELECTE_12M = (0x2ul<<4), + HFOSC_SELECTE_6M = (0x3ul<<4) +}HFOSC_SELECTE_TypeDef; + +/** + * @brief EM Filter set + */ +typedef enum +{ + EM_FLSEL_5ns = (0x0ul<<26), + EM_FLSEL_10ns = (0x1ul<<26), + EM_FLSEL_15ns = (0x2ul<<26), + EM_FLSEL_20ns = (0x3ul<<26) +}EM_Filter_TypeDef; +/** + * @brief EM Filter CMD + */ +typedef enum +{ + EM_FLEN_DIS = (0x0ul<<25), + EM_FLEN_EN = (0x1ul<<25) +}EM_Filter_CMD_TypeDef; +/** + * @brief EM LFSEL BIT + */ +typedef enum +{ + EM_LFSEL_DIS = (0x0ul<<10), + EM_LFSEL_EN = (0x1ul<<10) +}EM_LFSEL_TypeDef; +/** + * @brief EM Systemclk data + */ +typedef enum +{ + EMOSC_24M = 0, + EMOSC_16M = 1, + EMOSC_12M = 2, + EMOSC_8M = 3, + EMOSC_4M = 4, + EMOSC_36K = 5, + IMOSC = 6, + ISOSC = 7, + HFOSC_48M = 8, + HFOSC_24M = 9, + HFOSC_12M = 10, + HFOSC_6M = 11 +}SystemClk_data_TypeDef; +typedef enum +{ + CLO_PA02 = 0, //PA0.0 as clo + CLO_PA08 = 1, //PA0.8 as clo +}CLO_IO_TypeDef; + +typedef enum +{ + INTDET_POL_fall = (1<<6), //fall Trigger + INTDET_POL_X_rise = (2<<6), //rise Trigger + INTDET_POL_X_riseORfall = (3<<6), //fall or rise Trigger +}INTDET_POL_X_TypeDef; + +typedef enum +{ + //IOMAP0 + PIN_I2C_SCL = 0X00, // + PIN_I2C_SDA = 0X01, // + PIN_GPT_CHA = 0X02, // + PIN_GPT_CHB = 0X03, // + PIN_SPI_MOSI = 0X04, // + PIN_SPI_MISO = 0X05, // + PIN_SPI_SCK = 0X06, // + PIN_SPI_NSS = 0X07, // + //IOMAP1 + PIN_UART0_RX = 0X10, // + PIN_UART0_TX = 0X11, // + PIN_EPT_CHAX = 0X12, // + PIN_EPT_CHBX = 0X13, // + PIN_EPT_CHCX = 0X14, // + PIN_EPT_CHAY = 0X15, // + PIN_EPT_CHBY = 0X16, // + PIN_EPT_CHCY = 0X17, // +}IOMAP_DIR_TypeDef; + +/** + * @brief CLOMX Systemclk data + */ +typedef enum +{ + CLO_ISCLK = 0, + CLO_IMCLK = 1, + CLO_EMCLK = 3, + CLO_HFCLK = 4, + CLO_RTCCLK = 6, + CLO_PCLK = 7, + CLO_HCLK = 8, + CLO_IWDTCLK = 9, + CLO_SYSCLK = 0X0D, +}SystemClk_CLOMX_TypeDef; + +/** + * @brief CLOMX Systemclk data + */ +typedef enum +{ + CLO_DIV0 = 1, + CLO_DIV4 = 0, + CLO_DIV2 = 2, + CLO_DIV8 = 4, + CLO_DIV16 = 5, +}SystemClk_CLODIV_TypeDef; + +/** @addtogroup SYSCON_Exported_functions + * @{ + */ +extern void SYSCON_RST_VALUE(void); +extern void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X ); +extern void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X); +extern void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x ); +extern void SYSCON_WDT_CMD(FunctionalStatus NewState); +extern void SYSCON_IWDCNT_Reload(void); +extern void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X ); +extern void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X); +extern void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode); +extern void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN); +extern void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io); +extern U32_T SYSCON_Read_CINF0(void); +extern U32_T SYSCON_Read_CINF1(void); +extern void SYSCON_INT_Priority(void); +extern void EXI0_Int_Enable(void); +extern void EXI0_Int_Disable(void); +extern void EXI1_Int_Enable(void); +extern void EXI1_Int_Disable(void); +extern void EXI2_Int_Enable(void); +extern void EXI2_Int_Disable(void); +extern void EXI3_Int_Enable(void); +extern void EXI3_Int_Disable(void); +extern void EXI4_Int_Enable(void); +extern void EXI4_Int_Disable(void); +extern void SYSCON_Int_Enable(void); +extern void SYSCON_Int_Disable(void); +extern void PCLK_goto_idle_mode(void); +extern void PCLK_goto_deepsleep_mode(void); +extern void LVD_Int_Enable(void); +extern void LVD_Int_Disable(void); +extern void IWDT_Int_Enable(void); +extern void IWDT_Int_Disable(void); +extern void EXI0_WakeUp_Enable(void); +extern void EXI0_WakeUp_Disable(void); +extern void EXI1_WakeUp_Enable(void); +extern void EXI1_WakeUp_Disable(void); +extern void EXI2_WakeUp_Enable(void); +extern void EXI2_WakeUp_Disable(void); +extern void EXI3_WakeUp_Enable(void); +extern void EXI3_WakeUp_Disable(void); +extern void EXI4_WakeUp_Enable(void); +extern void EXI4_WakeUp_Disable(void); +extern void SYSCON_WakeUp_Enable(void); +extern void SYSCON_WakeUp_Disable(void); +extern void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE); +extern void SYSCON_Software_Reset(void); +extern void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X); +extern void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X); +extern void SystemCLK_Clear(void); +extern void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data); +extern void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr); +extern void Set_INT_Priority(U8_T int_name,U8_T int_level); +#endif /**< apt32f102_syscon_H */ + +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_tkey.h b/Source/include/apt32f102_tkey.h new file mode 100644 index 0000000..bf1cf36 --- /dev/null +++ b/Source/include/apt32f102_tkey.h @@ -0,0 +1,184 @@ +/* + ****************************************************************************** + * @file apt32f102_tkey.h + * @author APT AE Team + * @version V1.01 + * @date 2019/04/05 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +#ifndef _apt32f102_TK_H +#define _apt32f102_TK_H + +#include "apt32f102.h" + +/** + * @brief tkey mode register + */ +typedef enum +{ + TK_HM_DIS = 0<<0, + TK_HM_EN = 1<<0, +}TKEY_HMEN_TypeDef; +/** + * @brief tkey mode register + */ +typedef enum +{ + TK_SINGLE = 0<<1, + TK_SEQ = 1<<1, +}TKEY_MODE_TypeDef; +/** + * @brief tkey ckspr register + */ +typedef enum +{ + TK_CKSPR_DIS = 0<<9, + TK_CKSPR_EN = 1<<9, +}TKEY_CKSPR_TypeDef; +/** + * @brief tkey CKRND register + */ +typedef enum +{ + TK_CKRND_DIS = 0<<10, + TK_CKRND_EN = 1<<10, +}TKEY_CKRND_TypeDef; +/** + * @brief tkey CKFEQ register + */ +typedef enum +{ + TK_CKFEQ_LOW = 0<<11, + TK_CKREQ_HIGH = 1<<11, +}TKEY_CKFEQ_TypeDef; + +/** + * @brief tkey RSSEL register + */ +typedef enum +{ + TK_RSSEL_OVW = 0<<12, + TK_RSSEL_OverTHR = 1<<12, +}TKEY_RSSEL_TypeDef; +/** + * @brief tkey IDLEP register + */ +typedef enum +{ + TK_IDLEP_DIS = 0<<14, + TK_IDLEP_EN = 1<<14, +}TKEY_IDLEP_TypeDef; + +/** + * @brief tkey DSR register + */ +typedef enum +{ + TK_DSR_Z = 0<<16, + TK_DSR_LOW = 1<<16, + TK_DSR_HIGH = 2<<16, +}TKEY_DSR_TypeDef; + +/** + * @brief tkey TSCANSTB register + */ +typedef enum +{ + TK_STB_1 = 0<<20, + TK_STB_2 = 1<<20, + TK_STB_3 = 2<<20, + TK_STB_4 = 3<<20, +}TKEY_TSSTB_TypeDef; + +/** + * @brief tkey OTHRCN register + */ +typedef enum +{ + TK_DCKDIV_0 = 0<<12, + TK_DCKDIV_2 = 1<<12, + TK_DCKDIV_4 = 2<<12, + TK_DCKDIV_8 = 3<<12, +}TKEY_DCKDIV_TypeDef; +#define TK_PSEL_FVR 0 +#define TK_PSEL_AVDD 1 +#define TK_FVR_2048V 0 +#define TK_FVR_4096V 1 +#define TK_EC_1V 0 +#define TK_EC_2V 1 +#define TK_EC_3V 2 +#define TK_EC_3_6V 3 + +U32_T TK_IO_ENABLE; //Tkey IO使能 bit=1 表示使能对应的 TCHx 做 touch key 功能，低位至高位的顺序对应 TCH0~TCH16 +U16_T TK_senprd[17]; //Tkey 通道扫描周期配置 值越大灵敏度越高，但不能超过理论值否则按键无法扫描通过，常用值不大于 150 +U16_T TK_Triggerlevel[17]; //Tkey 通道触发门槛值配置 值越大门槛值越高，取值范围为按键差值的 50%~60%，未使用的通道设置成 0xFF +U8_T Press_debounce_data; //Tkey 触发去抖配置 按下去抖 1~10，默认配置为 5 +U8_T Release_debounce_data; //Tkey 释放去抖配置 释放去抖 1~10，默认配置为 5 +U16_T TK_icon[17]; +U8_T MultiTimes_Filter; //OFFSET 滤波倍数 大于等于 4 时，表示开启相应的倍数滤波；小于 4 时表示倍数滤波关闭；默认配置关闭 +U8_T Valid_Key_Num; //最多有效按键个数 此配置表示允许同时按下按键时最多有效个数。默认为 4 +U8_T Key_mode; //Tkey 按键模式 0 表示单键模式，1 表示多键模式 +U8_T Base_Speed; //Baseline 更新速度 数值越小，baseline 更新速度越快；数值越大，baseline 更新速度越慢；默认为 10 约 100ms +U32_T TK_longpress_time; //按键长按强制更新时间设置 长按键强制更新配置。时间= TK_longpress_time*1s；默认 16 秒 +U32_T TK_BaseCnt; //按键扫描基准时间配置 若系统时钟修改时需要修改此参数，保证基准时间为 10ms；计算公式 TK_BaseCnt=10ms*PCLK/8-1，默认 59999 数值基于 48MHz +U16_T TK_PSEL_MODE; +U16_T TK_FVR_LEVEL; +U16_T TK_EC_LEVEL; +U8_T TK_Lowpower_mode; +U8_T TK_Lowpower_level; +U8_T TK_Wakeup_level; +//**************************************************************** +#define TK_CLK_EN (TKEY->CLKEN|=0X01) +#define TK_CLK_DIS (TKEY->CLKEN&=0XFFE) +#define TK_SCANTIME_DIS (0<<12) +#define TK_SCANTIME_1ms (1<<12) +#define TK_SCANTIME_1_5ms (2<<12) +#define TK_SCANTIME_2ms (3<<12) +#define TK_SCANTIME_3ms (4<<12) +#define TK_SCANTIME_5ms (5<<12) +#define TK_SCANTIME_10ms (6<<12) +#define TK_SCANTIME_100ms (7<<12) + +#define TKEY_TCHEN(val) (val) /**< TKEY CH Enable */ +#define TKEY_ICON(val) (((val) & 0x0Ful) << 8) +#define TKEY_START (0x01ul << 0) + +#define TKEY_SINDNE (0x01ul << 0) +#define TKEY_DNE (0x01ul << 1) +#define TKEY_THR (0x01ul << 2) +#define TKEY_FLW (0x01ul << 3) +#define TKEY_OVW (0x01ul << 4) +#define TKEY_TIME (0x01ul << 5) +#define TCH_EN(val) (0x01<= 8 bits + short >= 16 bits + long >= 32 bits + (from Harbison & Steele, "C, A Ref. Manual" 3rd ed. p. 99) + + so all ANSI C compliant compilers will accept the following. +**************************************************************************/ +#ifndef CSP_TYPES_H +#define CSP_TYPES_H + + +/* Signed Types */ +typedef signed char S8_T; +typedef short S16_T; +typedef long S32_T; + +/* Unsigned Types */ +typedef unsigned char U8_T; +typedef unsigned short U16_T; +typedef unsigned long U32_T; +typedef unsigned long long U64_T; + +/* Float Types */ +typedef float F32_T; +typedef double F64_T; + +/* Boolean types declared as U8_T, as enums are generated as 16 bit */ +typedef U8_T B_T; + +/* Definitions for the two members of the Boolean type */ +#ifndef FALSE +#define FALSE ((B_T) 0) +#endif + +#ifndef TRUE +#define TRUE ((B_T) 1) +#endif + +/* UNUSED Definition for unused Interrupt numbers * and unused PDC channels */ +/* in the CHIP structure. (cf. CSP.C file) */ +#ifndef UNUSED +#define UNUSED ((U8_T) 0xFF) +#endif + +/* NULL definition */ +#ifndef NULL +#define NULL 0 +#endif + +typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +/****************************************************************************** +* Peripherals Type +******************************************************************************/ +typedef volatile U32_T CSP_REGISTER_T; +typedef volatile U16_T CSP_REGISTER16_T; +typedef volatile U8_T CSP_REGISTER8_T; + +#endif /* CSP_TYPE_H */ + +/* define 8 bit types */ +typedef unsigned char UINT8; +typedef signed char SINT8; + +/* define 16 bit types */ +typedef unsigned short UINT16; +typedef signed short SINT16; + +/* define 32 bit types */ +typedef unsigned long UINT32; +typedef signed long SINT32; + +typedef void VOID; +typedef signed char CHAR; /* be careful of EOF!!! (EOF = -1) */ +typedef unsigned char BOOL; +typedef signed long TIME_T; + +typedef float SINGLE; +#ifdef DOUBLE +#undef DOUBLE +#endif +typedef double DOUBLE; + +typedef struct +{ + unsigned bit0 : 1; + unsigned bit1 : 1; + unsigned bit2 : 1; + unsigned bit3 : 1; + unsigned bit4 : 1; + unsigned bit5 : 1; + unsigned bit6 : 1; + unsigned bit7 : 1; +} REG8; + +typedef struct +{ + unsigned bit0 : 1; + unsigned bit1 : 1; + unsigned bit2 : 1; + unsigned bit3 : 1; + unsigned bit4 : 1; + unsigned bit5 : 1; + unsigned bit6 : 1; + unsigned bit7 : 1; + unsigned bit8 : 1; + unsigned bit9 : 1; + unsigned bit10: 1; + unsigned bit11: 1; + unsigned bit12: 1; + unsigned bit13: 1; + unsigned bit14: 1; + unsigned bit15: 1; +} REG16; + + + +/************************************************************************** +STANDARD STRING TYPEDEFS +**************************************************************************/ +typedef char STRING_3[4]; +typedef char STRING_5[6]; +typedef char STRING_8[9]; +typedef char STRING_10[11]; +typedef char STRING_12[13]; +typedef char STRING_16[17]; +typedef char STRING_24[25]; +typedef char STRING_30[31]; +typedef char STRING_32[33]; +typedef char STRING_48[49]; +typedef char STRING_50[51]; +typedef char STRING_60[61]; +typedef char STRING_80[81]; +typedef char STRING_132[133]; +typedef char STRING_256[257]; +typedef char STRING_512[513]; + + +/********************************************/ +/* STANDARD SYSTEM SIZES */ +/********************************************/ +#define SIZE_UINT8 (size_t)(sizeof (UINT8 )) +#define SIZE_SINT8 (size_t)(sizeof (SINT8 )) + +#define SIZE_UINT16 (size_t)(sizeof (UINT16)) +#define SIZE_SINT16 (size_t)(sizeof (SINT16)) + +#define SIZE_UINT32 (size_t)(sizeof (UINT32)) +#define SIZE_SINT32 (size_t)(sizeof (SINT32)) + +#define SIZE_VOID (size_t)(sizeof (VOID )) +#define SIZE_CHAR (size_t)(sizeof (CHAR )) +#define SIZE_BOOL (size_t)(sizeof (BOOL )) +#define SIZE_TIME_T (size_t)(sizeof (TIME_T)) + +#define SIZE_SINGLE (size_t)(sizeof (SINGLE)) +#define SIZE_DOUBLE (size_t)(sizeof (DOUBLE)) + +#define SIZE_STRING_3 (size_t)(sizeof (STRING_3 )) +#define SIZE_STRING_5 (size_t)(sizeof (STRING_5 )) +#define SIZE_STRING_8 (size_t)(sizeof (STRING_8 )) +#define SIZE_STRING_10 (size_t)(sizeof (STRING_10 )) +#define SIZE_STRING_12 (size_t)(sizeof (STRING_12 )) +#define SIZE_STRING_16 (size_t)(sizeof (STRING_16 )) +#define SIZE_STRING_24 (size_t)(sizeof (STRING_24 )) +#define SIZE_STRING_30 (size_t)(sizeof (STRING_30 )) +#define SIZE_STRING_32 (size_t)(sizeof (STRING_32 )) +#define SIZE_STRING_48 (size_t)(sizeof (STRING_48 )) +#define SIZE_STRING_50 (size_t)(sizeof (STRING_50 )) +#define SIZE_STRING_60 (size_t)(sizeof (STRING_60 )) +#define SIZE_STRING_80 (size_t)(sizeof (STRING_80 )) +#define SIZE_STRING_132 (size_t)(sizeof (STRING_132)) +#define SIZE_STRING_256 (size_t)(sizeof (STRING_256)) +#define SIZE_STRING_512 (size_t)(sizeof (STRING_512)) + + +/************************************************************************** +STANDARD BIT MANIPULATIONS +**************************************************************************/ +#define SETBIT( target, bit ) ((target) |= (1u << (bit))) +#define CLRBIT( target, bit ) ((target) &= ~(1u << (bit))) +#define TOGBIT( target, bit ) ((target) ^= (1u << (bit))) + +#define ISBITSET( target, bit ) (!!((target) & (1u << (bit)))) +#define ISBITCLR( target, bit ) ( !((target) & (1u << (bit)))) + + +/**************************************************************************/ +#endif + + + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_uart.h b/Source/include/apt32f102_uart.h new file mode 100644 index 0000000..03502ad --- /dev/null +++ b/Source/include/apt32f102_uart.h @@ -0,0 +1,145 @@ +/* + ****************************************************************************** + * @file apt32f102_uart.h + * @author APT AE Team + * @version V1.13 + * @date 2021/12/13 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_uart_H +#define _apt32f102_uart_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +typedef enum +{ + UART_PAR_NONE =0<<8, //无校验位 + UART_PAR_EVEN =4<<8, //偶校验位 + UART_PAR_ODD =5<<8, //奇校验位 + UART_PAR_SPACE =6<<8, //0校验位 + UART_PAR_MARK =7<<8 //1校验位 +}UART_PAR_TypeDef; +/** + * @brief UART IO setting + */ +typedef enum +{ + IO_UART0 = 0, + IO_UART1 = 1, + IO_UART2 = 2, +}UART_NUM_TypeDef; +/***************************************************************************** +************************** UART Function defined ***************************** +******************************************************************************/ +#define UART_RESET_VALUE (0x00000000) +/** SR : UART Status Register */ +#define UART_TX_FULL (0x01ul << 0) /**< Transmitter full */ +#define UART_RX_FULL (0x01ul << 1) /**< Receiver full */ +#define UART_TX_OVER (0x01ul << 2) /**< Transmitter buff over */ +#define UART_RX_OVER (0x01ul << 3) /**< Receiver buff over */ + +/** CTRL : UART Control Register */ +#define UART_TX (0x01ul << 0) /**< Transmitter Enable/disable */ +#define UART_RX (0x01ul << 1) /**< Receiver Enable/disable */ +#define UART_TX_INT (0x01ul << 2) /**< Transmitter INT Enable/disable */ +#define UART_RX_INT (0x01ul << 3) /**< Receiver INT Enable/disable */ +#define UART_TX_IOV (0x01ul << 4) /**< Transmitter INTOver Enable/disable*/ +#define UART_RX_IOV (0x01ul << 5) /**< Receiver INTOver Enable/disable */ +#define UART_PARUTY_ERR_INT (0x01ul << 7) /**< PARUTY ERROR Status */ +#define UART_TX_FIFO_INT (0x01ul << 12) /**< TX fifo int Enable/disable */ +#define UART_RX_FIFO_INT (0x01ul << 13) /**< RX fifo int Enable/disable */ +#define UART_RX_FIFOOV_INT (0x01ul << 18) /**< RX fifo int over Enable/disable */ +#define UART_TX_DONE_INT (0x01ul << 19) /**< Receiver TX done Enable/disable */ + +//#define UART_TEST_MODE (0x01ul << 6) /**< =1 Test mode */ + +/** ISR : UART Interrupt Status Register */ +#define UART_TX_INT_S (0x01ul << 0) /**< Transmitter INT Status */ +#define UART_RX_INT_S (0x01ul << 1) /**< Receiver INTStatus */ +#define UART_TX_IOV_S (0x01ul << 2) /**< Transmitter INTOver Status */ +#define UART_RX_IOV_S (0x01ul << 3) /**< Receiver INTOver Status */ +#define UART_PARUTY_ERR_S (0x01ul << 4) /**< PARUTY ERROR Status */ +#define UART_TXMIS_S (0x01ul << 5) /**< tx fifo Status */ +#define UART_RXMIS_S (0x01ul << 6) /**< rx fifo Status */ +#define UART_RORMIS_S (0x01ul << 7) /**< rx fifo over Status */ +#define UART_TX_DONE_S (0x01ul << 19) /**< Receiver INTOver Status */ + +/** Set DATA register */ +#define CSP_UART_SET_DATA(uart, val) ((uart)->DATA = (val)) +/** Get DATA register */ +#define CSP_UART_GET_DATA(uart) ((uart)->DATA) + +/** Set SR register */ +#define CSP_UART_SET_SR(uart, val) ((uart)->SR = (val)) +/** Get SR register */ +#define CSP_UART_GET_SR(uart) ((uart)->SR) + +/** Set CTRL register */ +#define CSP_UART_SET_CTRL(uart, val) ((uart)->CTRL = (val)) +/** Get CTRL register */ +#define CSP_UART_GET_CTRL(uart) ((uart)->CTRL) + +/** Set ISR register */ +#define CSP_UART_SET_ISR(uart, val) ((uart)->ISR = (val)) +/** Get ISR register */ +#define CSP_UART_GET_ISR(uart) ((uart)->ISR) + +/** Set BRDIV register */ +#define CSP_UART_SET_BRDIV(uart, val) ((uart)->BRDIV = (val)) +/** Get BRDIV register */ +#define CSP_UART_GET_BRDIV(uart) ((uart)->BRDIV) +/** UART External Variable Declaration */ +#define UART_BUFSIZE 32 +extern volatile U16_T RxDataBuf[12]; +extern volatile U16_T RxDataPtr; +extern volatile U16_T TxDataPtr; +extern volatile U8_T RxDataFlag; +extern volatile U8_T TxDataFlag; +extern volatile U8_T Uart_send_Length; +extern volatile U16_T Uart_send_Length_temp; +extern volatile U8_T Uart_buffer[UART_BUFSIZE]; + /** UART External Functions Declaration */ +extern void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT); +extern void UARTClose(CSP_UART_T *uart); +extern void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT); +extern void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT); +extern void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8); +extern void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16); +extern U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16); +extern U8_T UART_ReturnRxByte(CSP_UART_T *uart); +extern U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16); +extern void UART0_DeInit(void); +extern void UART1_DeInit(void); +extern void UART2_DeInit(void); +extern void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G); +extern void UART0_Int_Enable(void); +extern void UART1_Int_Enable(void); +extern void UART2_Int_Enable(void); +extern void UART0_Int_Disable(void); +extern void UART1_Int_Disable(void); +extern void UART2_Int_Disable(void); +extern void UART0_WakeUp_Enable(void); +extern void UART1_WakeUp_Enable(void); +extern void UART2_WakeUp_Enable(void); +extern void UART0_WakeUp_Disable(void); +extern void UART1_WakeUp_Disable(void); +extern void UART2_WakeUp_Disable(void); +extern void UART0_CONFIG(void); +extern void UART1_CONFIG(void); +extern void UART2_CONFIG(void); +extern void UARTTTransmit_data_set(CSP_UART_T *uart ); +extern void UARTTransmit_INT_Send(CSP_UART_T *uart ); +#endif /**< apt32f102_types_local_H */ + +/******************* (C) COPYRIGHT 2016 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/include/apt32f102_wwdt.h b/Source/include/apt32f102_wwdt.h new file mode 100644 index 0000000..3afc329 --- /dev/null +++ b/Source/include/apt32f102_wwdt.h @@ -0,0 +1,65 @@ +/* + ****************************************************************************** + * @file apt32f102_wwdt.h + * @author APT AE Team + * @version V1.02 + * @date 2020/11/20 + ****************************************************************************** + *THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES + *CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS. + *APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT, + *INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF + *SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + *CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES + *THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _apt32f102_wwdt_H +#define _apt32f102_wwdt_H + +/* Includes ------------------------------------------------------------------*/ +#include "apt32f102.h" + +#define WWDT_RESET_VALUE (0x00000000) + + +//-------------------------------------------------------------------------------- +//-----------------------------wwdt value enum define-------------------------- +//-------------------------------------------------------------------------------- +/** + * @brief PSC DIV register + */ +typedef enum +{ + PCLK_4096_DIV0 = (0<<8), + PCLK_4096_DIV2 = (1<<8), + PCLK_4096_DIV4 = (2<<8), + PCLK_4096_DIV8 = (3<<8), +}WWDT_PSCDIV_TypeDef; +/** + * @brief WWDT DEBUG MODE register + */ +typedef enum +{ + WWDT_DBGDIS = (0<<10), + WWDT_DBGEN = (1<<10), +}WWDT_DBGEN_TypeDef; + +#define WWDT_EVI 0X01 + + +extern void WWDT_DeInit(void); +extern void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX); +extern void WWDT_CMD(FunctionalStatus NewState); +extern void WWDT_CNT_Load(U8_T cnt_data); +extern void WWDT_Int_Config(FunctionalStatus NewState); + + + +/*************************************************************/ + +#endif /**< apt32f102_wwdt_H */ + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/includes.h b/Source/includes.h new file mode 100644 index 0000000..fd74ec0 --- /dev/null +++ b/Source/includes.h @@ -0,0 +1,45 @@ +#ifndef _INCLUDES_H_ +#define _INCLUDES_H_ + +#include "apt32f102.h" +#include "apt32f102_adc.h" +#include "apt32f102_bt.h" +#include "apt32f102_coret.h" +#include "apt32f102_countera.h" +#include "apt32f102_crc.h" +#include "apt32f102_ept.h" +#include "apt32f102_et.h" +#include "apt32f102_gpio.h" +#include "apt32f102_gpt.h" +#include "apt32f102_i2c.h" +#include "apt32f102_ifc.h" +#include "apt32f102_lpt.h" +#include "apt32f102_rtc.h" +#include "apt32f102_sio.h" +#include "apt32f102_spi.h" +#include "apt32f102_syscon.h" +#include "apt32f102_uart.h" +#include "apt32f102_wwdt.h" +#include "apt32f102_types_local.h" +#include "apt32f102_clkcalib.h" +//#include "apt32f102_tkey.h" + +#include +#include + +/*应用代码头文件*/ +#include "uart.h" +#include "pb_fun.h" +#include "pwm.h" +#include "eeprom.h" + +#define Project_Software_Ver 0x07 +#define Project_Hardware_Ver 0x04 //硬件版本 + +extern volatile U32_T SysTick_100us; +extern volatile U32_T SysTick_1ms; + + + + +#endif diff --git a/Source/lib_102ClkCalib_1_03.a b/Source/lib_102ClkCalib_1_03.a new file mode 100644 index 0000000..fe1f46c Binary files /dev/null and b/Source/lib_102ClkCalib_1_03.a differ diff --git a/Source/lib_102TKey_1_15.a b/Source/lib_102TKey_1_15.a new file mode 100644 index 0000000..c4b7504 Binary files /dev/null and b/Source/lib_102TKey_1_15.a differ diff --git a/Source/lib_102TKey_1_15C.a b/Source/lib_102TKey_1_15C.a new file mode 100644 index 0000000..78b7518 Binary files /dev/null and b/Source/lib_102TKey_1_15C.a differ diff --git a/Source/lib_102TKey_1_15M.a b/Source/lib_102TKey_1_15M.a new file mode 100644 index 0000000..d442d99 Binary files /dev/null and b/Source/lib_102TKey_1_15M.a differ diff --git a/Source/lib_102TKey_1_15MC.a b/Source/lib_102TKey_1_15MC.a new file mode 100644 index 0000000..bb55e43 Binary files /dev/null and b/Source/lib_102TKey_1_15MC.a differ diff --git a/Source/main.c b/Source/main.c new file mode 100644 index 0000000..15aa645 --- /dev/null +++ b/Source/main.c @@ -0,0 +1,48 @@ +#include "includes.h" + + +extern void delay_nms(unsigned int t); +extern void APT32F102_init(void); + +U32_T test_tick = 0; + +/***************************************************/ +//main +/**************************************************/ +int main(void) +{ + //delay_nms(10000); //power on delay if needed + APT32F102_init(); //102 initial + + PB_Init(); + + PWM_Init(); + + Dbg_Println(DBG_BIT_SYS_STATUS,"MCU Start!"); + + while(1) + { + SYSCON_IWDCNT_Reload(); //IWDT Clear + + UART1_TASK(); + + PB_Task(); + } +} + + + + + + + + + + + + + + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ + + diff --git a/Source/mcu_initial.c b/Source/mcu_initial.c new file mode 100644 index 0000000..34106ec --- /dev/null +++ b/Source/mcu_initial.c @@ -0,0 +1,320 @@ +#include "includes.h" + + +/*************************************************************/ +//software delay +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void delay_nms(unsigned int t) +{ + volatile unsigned int i,j ,k=0; + j = 50* t; + for ( i = 0; i < j; i++ ) + { + k++; + SYSCON_IWDCNT_Reload(); + } +} +void delay_nus(unsigned int t) +{ + volatile unsigned int i,j ,k=0; + j = 1* t; + for ( i = 0; i < j; i++ ) + { + k++; + } +} +/*************************************************************/ +//GPIO Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPIO_CONFIG(void) +{ + //外部中断初始化 + GPIO_IntGroup_Set(PB0,1,Selete_EXI_PIN1); //PB0.0 set as EXI18 + GPIO_Init(GPIOB0,1,1); //PB0.0 set as input + EXTI_trigger_CMD(ENABLE,EXI_PIN1,_EXIRT); //ENABLE falling edge + + EXTI_interrupt_CMD(ENABLE,EXI_PIN1); //enable EXI + GPIO_EXTI_interrupt(GPIOB0,0b0000000000000010); //enable GPIOB0.0 as EXI + + Set_INT_Priority(EXI1_IRQ,0); //0:set int priority 1st + EXI1_Int_Enable(); //EXI1 / EXI17 INT Vector + + //GPIO初始化 + GPIO_Init(GPIOB0,4,0); //PB0.4 set as output + GPIO_Init(GPIOA0,12,0); //PA0.12 set as output + GPIO_Init(GPIOA0,14,0); //PA0.14 set as output + + GPIO_DriveStrength_EN(GPIOB0,4); + GPIO_DriveStrength_EN(GPIOA0,12); + GPIO_DriveStrength_EN(GPIOA0,14); + + GPIO_Write_Low(GPIOB0,4); //上电默认为低电平 + GPIO_Write_Low(GPIOA0,12); + GPIO_Write_Low(GPIOA0,14); + + +} + +/*************************************************************/ +//ETP0 Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT0_CONFIG(void) +{ + //4路 PWM初始化 + EPT_Software_Prg(); //EPT software reset +//------------ EPT GPIO Setting --------------------------------/ + EPT_IO_SET(EPT_IO_CHAX,IO_NUM_PA10); //AX channel selection + EPT_IO_SET(EPT_IO_CHBX,IO_NUM_PA11); //BX channel selection + EPT_IO_SET(EPT_IO_CHCX,IO_NUM_PB05); //CX channel selection + EPT_IO_SET(EPT_IO_CHD,IO_NUM_PA08); //D channel selection +//------------ EPT Control --------------------------------/ + EPT_PWM_Config(EPT_Selecte_PCLK,EPT_CNTMD_increase,EPT_OPM_Continue,0);//PCLK as clock，increasing mode,continuous mode,TCLK=PCLK/(0+1) + + EPT_PWMX_Output_Control(EPT_PWMA,EPT_CA_Selecte_CMPA,EPT_CB_Selecte_CMPA,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMB,EPT_CA_Selecte_CMPB,EPT_CB_Selecte_CMPB,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMC,EPT_CA_Selecte_CMPC,EPT_CB_Selecte_CMPC,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + EPT_PWMX_Output_Control(EPT_PWMD,EPT_CA_Selecte_CMPD,EPT_CB_Selecte_CMPD,EPT_PWM_ZRO_Event_OutLow,EPT_PWM_PRD_Event_Nochange, + EPT_PWM_CAU_Event_OutHigh,EPT_PWM_CAD_Event_OutHigh, + EPT_PWM_CBU_Event_Nochange,EPT_PWM_CBD_Event_Nochange, + EPT_PWM_T1U_Event_Nochange,EPT_PWM_T1D_Event_Nochange, + EPT_PWM_T2U_Event_Nochange,EPT_PWM_T2D_Event_Nochange); + + EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(PWM_OUT_VAL_MAX,0,0,0,0);//PRDR=2400,CMPA=1200,CMPB=600,CMPC=2400,CMPD=0 + +//------------ EPT start --------------------------------/ + EPT_Start(); + +} + +/*************************************************************/ +//BT Initial +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT_CONFIG(void) +{ + //PB 保护电流PWM_CURR_LMT + BT_DeInit(BT0); + BT_IO_Init(BT0_PA15); + BT_Configure(BT0,BTCLK_EN,7,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV);//TCLK=PCLK/(0+1) + BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + //BT_ControlSet_Configure(BT0,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_EN,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + //BT_Trigger_Configure(BT0,BT_TRGSRC_PEND,BT_TRGOE_EN); + BT_Period_CMP_Write(BT0,4095,4000); + BT_Start(BT0); +// BT_ConfigInterrupt_CMD(BT0,ENABLE,BT_PEND); +// BT0_INT_ENABLE(); + + + //100us 定时器初始化 + BT_DeInit(BT1); + BT_Configure(BT1,BTCLK_EN,0,BT_IMMEDIATE,BT_CONTINUOUS,BT_PCLKDIV); + BT_ControlSet_Configure(BT1,BT_START_HIGH,BT_IDLE_LOW,BT_SYNC_DIS,BT_SYNCMD_DIS,BT_OSTMDX_ONCE,BT_AREARM_DIS,BT_CNTRLD_EN); + BT_Period_CMP_Write(BT1,4780,1); + BT_Start(BT1); + BT_ConfigInterrupt_CMD(BT1,ENABLE,BT_CMP); + BT1_INT_ENABLE(); + +} + + + +/*************************************************************/ +//UART0 CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0_CONFIG(void) +{ + UART0_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART0,0); //use PA0.1->RXD0, PA0.0->TXD0 + UARTInit(UART0,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 + + UARTInitRxTxIntEn(UART0,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200,tx rx int enabled + UART0_Int_Enable(); +} +/*************************************************************/ +//UART1 CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1_CONFIG(void) +{ + UART1_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART1,0); //use PA0.13->RXD1, PB0.0->TXD1 + UARTInit(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 + + UARTInitRxTxIntEn(UART1,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + UART1_Int_Enable(); +} +/*************************************************************/ +//UART2 CONFIG +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2_CONFIG(void) +{ + UART2_DeInit(); //clear all UART Register + UART_IO_Init(IO_UART2,2); //use PA0.7->RXD2, PA0.6->TXD2 + UARTInit(UART2,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 + //UARTInitRxTxIntEn(UART2,416,UART_PAR_NONE); //baudrate=sysclock 48M/416=115200 tx rx int enabled + //UART2_Int_Enable(); +} +/*************************************************************/ +//adc config +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADC12_CONFIG(void) +{ + + ADC12_RESET_VALUE(); //ADC所有寄存器复位 + ADC12_Software_Reset(); //ADC软件复位 + ADC12_CLK_CMD(ADC_CLK_CR,ENABLE); //使能ADC CLK + + ADC12_Configure_Mode(ADC12_12BIT,Continuous_mode,0,6,2,4); + + ADC12_Configure_VREF_Selecte(ADC12_VREFP_VDD_VREFN_VSS); + + ADC12_ConversionChannel_Config(ADC12_ADCIN4,ADC12_CV_RepeatNum1,ADC12_AVGDIS,0); + ADC12_ConversionChannel_Config(ADC12_ADCIN7,ADC12_CV_RepeatNum1,ADC12_AVGDIS,1); + ADC12_ConversionChannel_Config(ADC12_ADCIN8,ADC12_CV_RepeatNum1,ADC12_AVGDIS,2); + ADC12_ConversionChannel_Config(ADC12_ADCIN10,ADC12_CV_RepeatNum1,ADC12_AVGDIS,3); + + ADC12_CMD(ENABLE); + + ADC12_ready_wait(); + + ADC12_Control(ADC12_START); +} + +/*************************************************************/ +//GPT0 Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT0_CONFIG(void) +{ + + GPT_Configure(GPTCLK_EN,GPT_PCLK,GPT_IMMEDIATE,1); + GPT_WaveCtrl_Configure(GPT_INCREASE,GPT_SWSYNDIS,GPT_IDLE_LOW,GPT_PRDLD_PEND,GPT_OPM_CONTINUOUS,GPT_BURST_DIS,GPT_CKS_PCLK,GPT_CG_CHAX,GPT_CGFLT_00,GPT_PRDLD_ZERO); + GPT_Period_CMP_Write(24000,1,1000); + + //GPT_WaveLoad_Configure(GPT_WAVEA_IMMEDIATE,GPT_WAVEB_SHADOW,GPT_AQLDA_ZERO,GPT_AQLDB_ZERO); + + //GPT_SyncSet_Configure(GPT_SYNCUSR0_EN,GPT_OST_CONTINUOUS,GPT_TXREARM_DIS,GPT_TRGO0SEL_SR0,GPT_TRG10SEL_SR0,GPT_AREARM_DIS); + //GPT_Trigger_Configure(GPT_SRCSEL_TRGUSR0EN,GPT_BLKINV_DIS,GPT_ALIGNMD_PRD,GPT_CROSSMD_DIS,5,5); + //GPT_EVTRG_Configure(GPT_TRGSRC0_PRD,GPT_TRGSRC1_PRD,GPT_ESYN0OE_EN,GPT_ESYN1OE_EN,GPT_CNT0INIT_EN,GPT_CNT1INIT_EN,3,3,3,3); + GPT_Start(); + GPT_ConfigInterrupt_CMD(ENABLE,GPT_INT_PEND); + GPT_INT_ENABLE(); + +} + +/*************************************************************/ +//syscon Functions +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCON_CONFIG(void) +{ +//------SYSTEM CLK AND PCLK FUNTION---------------------------/ + SYSCON_RST_VALUE(); //SYSCON all register clr + SYSCON_General_CMD(ENABLE,ENDIS_ISOSC); //SYSCON enable/disable clock source + //EMOSC_OSTR_Config(0XAD,0X1f,EM_LFSEL_EN,EM_FLEN_EN,EM_FLSEL_10ns); //EM_CNT=0X3FF,0xAD(36K),EM_GM=0,Low F modedisable,EM filter disable,if enable,cont set 5ns + //SYSCON_General_CMD(ENABLE,ENDIS_EMOSC); + SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_48M); //HFOSC selected 48MHz + SystemCLK_HCLKDIV_PCLKDIV_Config(SYSCLK_HFOSC,HCLK_DIV_1,PCLK_DIV_1,HFOSC_48M);//system clock set, Hclk div ,Pclk div set system clock=SystemCLK/Hclk div/Pclk div +//------------ WDT FUNTION --------------------------------/ + SYSCON_IWDCNT_Config(IWDT_TIME_4S,IWDT_INTW_DIV_7); //WDT TIME 1s,WDT alarm interrupt time=1s-1s*1/8=0.875S + SYSCON_WDT_CMD(ENABLE); //enable/disable WDT + SYSCON_IWDCNT_Reload(); //reload WDT + IWDT_Int_Enable(); +//------------ WWDT FUNTION --------------------------------/ + WWDT_CNT_Load(0xFF); + WWDT_CONFIG(PCLK_4096_DIV0,0xFF,WWDT_DBGDIS); + WWDT_Int_Config(DISABLE); + //WWDT_CMD(ENABLE); //enable wwdt +//------------ CLO Output --------------------------------/ + //SYSCON_CLO_CONFIG(CLO_PA08); //CLO output setting + //SYSCON_CLO_SRC_SET(CLO_HFCLK,CLO_DIV16); //CLO output clock and div +//------------ LVD FUNTION --------------------------------/ + SYSCON_LVD_Config(ENABLE_LVDEN,INTDET_LVL_3_9V,RSTDET_LVL_1_9V,ENABLE_LVD_INT,INTDET_POL_fall); //LVD LVR Enable/Disable + LVD_Int_Enable(); +//------------ SYSCON Vector --------------------------------/ + SYSCON_Int_Enable(); //SYSCON VECTOR + //SYSCON_WakeUp_Enable(); //Enable WDT wakeup INT +//------------------------------------------------------------/ +//OSC CLOCK Calibration +//------------------------------------------------------------/ + std_clk_calib(CLK_HFOSC_48M); //Select the same clock source as the system + +} +/*********************************************************************************/ +/*********************************************************************************/ +//APT32F102_init / +//EntryParameter:NONE / +//ReturnValue:NONE / +/*********************************************************************************/ +/*********************************************************************************/ +/*********************************************************************************/ +void APT32F102_init(void) +{ +//------------------------------------------------------------/ +//Peripheral clock enable and disable +//EntryParameter:NONE +//ReturnValue:NONE +//------------------------------------------------------------/ + SYSCON->PCER0=0xFFFFFFF; //PCLK Enable + SYSCON->PCER1=0xFFFFFFF; //PCLK Enable + while(!(SYSCON->PCSR0&0x1)); //Wait PCLK enabled +//------------------------------------------------------------/ +//ISOSC/IMOSC/EMOSC/SYSCLK/IWDT/LVD/EM_CMFAIL/EM_CMRCV/CMD_ERR OSC stable interrupt +//EntryParameter:NONE +//ReturnValue:NONE +//------------------------------------------------------------/ + SYSCON_CONFIG(); //syscon initial + CK_CPU_EnAllNormalIrq(); //enable all IRQ + SYSCON_INT_Priority(); //initial all Priority=0xC0 + + Set_INT_Priority(EXI1_IRQ,0); + Set_INT_Priority(UART1_IRQ,1); + Set_INT_Priority(BT1_IRQ,1); + Set_INT_Priority(UART0_IRQ,2); +//------------------------------------------------------------/ +//Other IP config +//------------------------------------------------------------/ + GPIO_CONFIG(); //GPIO initial + EPT0_CONFIG(); //EPT0 initial + + BT_CONFIG(); //BT initial + GPT0_CONFIG(); //2024-06-16 修改 单独用于PWM 1ms定时控制 + + UARTx_Init(UART_0,NULL); + UARTx_Init(UART_1,BLV_PB_Control_Protocol_Processing); + + EEPROM_Init(); + + ADC12_CONFIG(); //ADC initial + +} + +/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ \ No newline at end of file diff --git a/Source/mcu_interrupt.c b/Source/mcu_interrupt.c new file mode 100644 index 0000000..09a911c --- /dev/null +++ b/Source/mcu_interrupt.c @@ -0,0 +1,970 @@ +#include "includes.h" + +/**************************************************** +//define +*****************************************************/ +volatile int R_CMPA_BUF,R_CMPB_BUF; +volatile int R_SIOTX_count,R_SIORX_count; +volatile int R_SIORX_buf[10]; +/**************************************************** +//extern +*****************************************************/ +extern void delay_nms(unsigned int t); +/*************************************************************/ +//CORET Interrupt +//If you use a touch library file that does not contain coret +//you need to open this interrupt entry +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CORETHandler(void) +{ + // ISR content ... +} +/*************************************************************/ +//SYSCON Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SYSCONIntHandler(void) +{ + // ISR content ... + nop; + if((SYSCON->MISR&ISOSC_ST)==ISOSC_ST) //ISOSC stable interrupt + { + SYSCON->ICR = ISOSC_ST; + } + else if((SYSCON->MISR&IMOSC_ST)==IMOSC_ST) //IMOSC stable interrupt + { + SYSCON->ICR = IMOSC_ST; + } + else if((SYSCON->MISR&EMOSC_ST)==EMOSC_ST) //EMOSC stable interrupt + { + SYSCON->ICR = EMOSC_ST; + } + else if((SYSCON->MISR&HFOSC_ST)==HFOSC_ST) //HFOSC stable interrupt + { + SYSCON->ICR = HFOSC_ST; + } + else if((SYSCON->MISR&SYSCLK_ST)==SYSCLK_ST) //SYSCLK change end & stable interrupt + { + SYSCON->ICR = SYSCLK_ST; + } + else if((SYSCON->MISR&IWDT_INT_ST)==IWDT_INT_ST) //IWDT alarm window interrupt + { + SYSCON->ICR = IWDT_INT_ST; + //SYSCON->IWDCNT=0x5aul<<24; + } + else if((SYSCON->MISR&WKI_INT_ST)==WKI_INT_ST) + { + SYSCON->ICR = WKI_INT_ST; + } + else if((SYSCON->MISR&RAMERRINT_ST)==RAMERRINT_ST) //SRAM check fail interrupt + { + SYSCON->ICR = RAMERRINT_ST; + } + else if((SYSCON->MISR&LVD_INT_ST)==LVD_INT_ST) //LVD threshold interrupt + { + nop; + SYSCON->ICR = LVD_INT_ST; + } + else if((SYSCON->MISR&HWD_ERR_ST)==HWD_ERR_ST) //Hardware Divider divisor = 0 interrupt + { + SYSCON->ICR = HWD_ERR_ST; + } + else if((SYSCON->MISR&EFL_ERR_ST)==EFL_ERR_ST) //Flash check fail interrupt + { + SYSCON->ICR = EFL_ERR_ST; + } + else if((SYSCON->MISR&OPTERR_INT)==OPTERR_INT) //Option load fail interrupt + { + SYSCON->ICR = OPTERR_INT; + } + else if((SYSCON->MISR&EM_CMLST_ST)==EM_CMLST_ST) //EMOSC clock monitor fail interrupt + { + SYSCON->ICR = EM_CMLST_ST; + } + else if((SYSCON->MISR&EM_EVTRG0_ST)==EM_EVTRG0_ST) //Event Trigger Channel 0 Interrupt + { + SYSCON->ICR = EM_EVTRG0_ST; + } + else if((SYSCON->MISR&EM_EVTRG1_ST)==EM_EVTRG1_ST) //Event Trigger Channel 1 Interrupt + { + SYSCON->ICR = EM_EVTRG1_ST; + } + else if((SYSCON->MISR&EM_EVTRG2_ST)==EM_EVTRG2_ST) //Event Trigger Channel 2 Interrupt + { + SYSCON->ICR = EM_EVTRG2_ST; + } + else if((SYSCON->MISR&EM_EVTRG3_ST)==EM_EVTRG3_ST) //Event Trigger Channel 3 Interrupt + { + SYSCON->ICR = EM_EVTRG3_ST; + } + else if((SYSCON->MISR&CMD_ERR_ST)==CMD_ERR_ST) //Command error interrupt + { + SYSCON->ICR = CMD_ERR_ST; + } +} +/*************************************************************/ +//IFC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void IFCIntHandler(void) +{ + // ISR content ... + if(IFC->MISR&ERS_END_INT) + { + IFC->ICR=ERS_END_INT; + } + else if(IFC->MISR&RGM_END_INT) + { + IFC->ICR=RGM_END_INT; + } + else if(IFC->MISR&PEP_END_INT) + { + IFC->ICR=PEP_END_INT; + } + else if(IFC->MISR&PROT_ERR_INT) + { + IFC->ICR=PROT_ERR_INT; + } + else if(IFC->MISR&UDEF_ERR_INT) + { + IFC->ICR=UDEF_ERR_INT; + } + else if(IFC->MISR&ADDR_ERR_INT) + { + IFC->ICR=ADDR_ERR_INT; + } + else if(IFC->MISR&OVW_ERR_INT) + { + IFC->ICR=OVW_ERR_INT; + } +} +/*************************************************************/ +//ADC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void ADCIntHandler(void) +{ + // ISR content ... + if((ADC0->SR&ADC12_EOC)==ADC12_EOC) //ADC EOC interrupt + { + ADC0->CSR = ADC12_EOC; + } + else if((ADC0->SR&ADC12_READY)==ADC12_READY) //ADC READY interrupt + { + ADC0->CSR = ADC12_READY; + } + else if((ADC0->SR&ADC12_OVR)==ADC12_OVR) //ADC OVR interrupt + { + ADC0->CSR = ADC12_OVR; + } + else if((ADC0->SR&ADC12_CMP0H)==ADC12_CMP0H) //ADC CMP0H interrupt + { + ADC0->CSR = ADC12_CMP0H; + } + else if((ADC0->SR&ADC12_CMP0L)==ADC12_CMP0L) //ADC CMP0L interrupt. + { + ADC0->CSR = ADC12_CMP0L; + } + else if((ADC0->SR&ADC12_CMP1H)==ADC12_CMP1H) //ADC CMP1H interrupt. + { + ADC0->CSR = ADC12_CMP1H; + } + else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L) //ADC CMP1L interrupt. + { + ADC0->CSR = ADC12_CMP1L; + } + else if((ADC0->SR&ADC12_SEQ_END0)==ADC12_SEQ_END0) //ADC SEQ0 interrupt,SEQ1~SEQ15 replace the parameter with ADC12_SEQ_END1~ADC12_SEQ_END15 + { + ADC0->CSR = ADC12_SEQ_END0; + } +} +/*************************************************************/ +//EPT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EPT0IntHandler(void) +{ + // ISR content ... + if((EPT0->MISR&EPT_TRGEV0_INT)==EPT_TRGEV0_INT) //TRGEV0 interrupt + { + EPT0->ICR=EPT_TRGEV0_INT; + } + else if((EPT0->MISR&EPT_TRGEV1_INT)==EPT_TRGEV1_INT) //TRGEV1 interrupt + { + EPT0->ICR=EPT_TRGEV1_INT; + } + else if((EPT0->MISR&EPT_TRGEV2_INT)==EPT_TRGEV2_INT) //TRGEV2 interrupt + { + EPT0->ICR=EPT_TRGEV2_INT; + } + else if((EPT0->MISR&EPT_TRGEV3_INT)==EPT_TRGEV3_INT) //TRGEV3 interrupt + { + EPT0->ICR=EPT_TRGEV3_INT; + } + else if((EPT0->MISR&EPT_CAP_LD0)==EPT_CAP_LD0) //Capture Load to CMPA interrupt + { + EPT0->ICR=EPT_CAP_LD0; + EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIRT); + EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT); + R_CMPA_BUF=EPT0->CMPA; //Low voltage counter + } + else if((EPT0->MISR&EPT_CAP_LD1)==EPT_CAP_LD1) //Capture Load to CMPB interrupt + { + EPT0->ICR=EPT_CAP_LD1; + EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIRT); + EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT); + R_CMPB_BUF=EPT0->CMPB; //Duty counter + } + else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2) //Capture Load to CMPC interrupt + { + EPT0->ICR=EPT_CAP_LD2; + } + else if((EPT0->MISR&EPT_CAP_LD3)==EPT_CAP_LD3) //Capture Load to CMPD interrupt + { + EPT0->ICR=EPT_CAP_LD3; + } + else if((EPT0->MISR&EPT_CAU)==EPT_CAU) //Up-Counting phase CNT = CMPA interrupt + { + EPT0->ICR=EPT_CAU; + } + else if((EPT0->MISR&EPT_CAD)==EPT_CAD) //Down-Counting phase CNT = CMPA interrupt + { + EPT0->ICR=EPT_CAD; + } + else if((EPT0->MISR&EPT_CBU)==EPT_CBU) //Up-Counting phase CNT = CMPB interrupt + { + EPT0->ICR=EPT_CBU; + } + else if((EPT0->MISR&EPT_CBD)==EPT_CBD) //Down-Counting phase CNT = CMPB interrupt + { + EPT0->ICR=EPT_CBD; + } + else if((EPT0->MISR&EPT_CCU)==EPT_CCU) //Up-Counting phase CNT = CMPC interrupt + { + EPT0->ICR=EPT_CCU; + } + else if((EPT0->MISR&EPT_CCD)==EPT_CCD) //Down-Counting phase CNT = CMPC interrupt + { + EPT0->ICR=EPT_CCD; + } + else if((EPT0->MISR&EPT_CDU)==EPT_CDU) //Up-Counting phase CNT = CMPD interrupt + { + EPT0->ICR=EPT_CDU; + } + else if((EPT0->MISR&EPT_CDD)==EPT_CDD) //Down-Counting phase CNT = CMPD interrupt + { + EPT0->ICR=EPT_CDD; + } + else if((EPT0->MISR&EPT_PEND)==EPT_PEND) //End of cycle interrupt + { + EPT0->ICR=EPT_PEND; + } + //Emergency interruption + if((EPT0->EMMISR&EPT_EP0_EMINT)==EPT_EP0_EMINT) //interrupt flag of EP0 event + { + EPT0->EMICR=EPT_EP0_EMINT; + } + else if((EPT0->EMMISR&EPT_EP1_EMINT)==EPT_EP1_EMINT) //interrupt flag of EP1 event + { + EPT0->EMICR=EPT_EP1_EMINT; + } + else if((EPT0->EMMISR&EPT_EP2_EMINT)==EPT_EP2_EMINT) //interrupt flag of EP2 event + { + EPT0->EMICR=EPT_EP2_EMINT; + } + else if((EPT0->EMMISR&EPT_EP3_EMINT)==EPT_EP3_EMINT) //interrupt flag of EP3 event + { + EPT0->EMICR=EPT_EP3_EMINT; + } + else if((EPT0->EMMISR&EPT_EP4_EMINT)==EPT_EP4_EMINT) //interrupt flag of EP4 event + { + EPT0->EMICR=EPT_EP4_EMINT; + } + else if((EPT0->EMMISR&EPT_EP5_EMINT)==EPT_EP5_EMINT) //interrupt flag of EP5 event + { + EPT0->EMICR=EPT_EP5_EMINT; + } + else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT) //interrupt flag of EP6 event + { + EPT0->EMICR=EPT_EP6_EMINT; + } + else if((EPT0->EMMISR&EPT_EP7_EMINT)==EPT_EP7_EMINT) //interrupt flag of EP7 event + { + EPT0->EMICR=EPT_EP7_EMINT; + } + else if((EPT0->EMMISR&EPT_CPU_FAULT_EMINT)==EPT_CPU_FAULT_EMINT) //interrupt flag of CPU_FAULT event + { + EPT0->EMICR=EPT_CPU_FAULT_EMINT; + } + else if((EPT0->EMMISR&EPT_MEM_FAULT_EMINT)==EPT_MEM_FAULT_EMINT) //interrupt flag of MEM_FAULT event + { + EPT0->EMICR=EPT_MEM_FAULT_EMINT; + } + else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT) //interrupt flag of EOM_FAULT event + { + EPT0->EMICR=EPT_EOM_FAULT_EMINT; + } +} +/*************************************************************/ +//WWDT Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void WWDTHandler(void) +{ + WWDT->ICR=0X01; + WWDT_CNT_Load(0xFF); + if((WWDT->MISR&WWDT_EVI)==WWDT_EVI) //WWDT EVI interrupt + { + WWDT->ICR = WWDT_EVI; + } +} +/*************************************************************/ +//GPT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void GPT0IntHandler(void) +{ + // ISR content ... + if((GPT0->MISR&GPT_INT_TRGEV0)==GPT_INT_TRGEV0) //TRGEV0 interrupt + { + GPT0->ICR = GPT_INT_TRGEV0; + } + else if((GPT0->MISR&GPT_INT_TRGEV1)==GPT_INT_TRGEV1) //TRGEV1 interrupt + { + GPT0->ICR = GPT_INT_TRGEV1; + } + else if((GPT0->MISR&GPT_INT_CAPLD0)==GPT_INT_CAPLD0) //Capture Load to CMPA interrupt + { + GPT0->ICR = GPT_INT_CAPLD0; + } + else if((GPT0->MISR&GPT_INT_CAPLD1)==GPT_INT_CAPLD1) //Capture Load to CMPB interrupt + { + GPT0->ICR = GPT_INT_CAPLD1; + } + else if((GPT0->MISR&GPT_INT_CAU)==GPT_INT_CAU) //Up-Counting phase CNT = CMPA Interrupt + { + GPT0->ICR = GPT_INT_CAU; + } + else if((GPT0->MISR&GPT_INT_CAD)==GPT_INT_CAD) //Down-Counting phase CNT = CMPA Interrupt + { + GPT0->ICR = GPT_INT_CAD; + } + else if((GPT0->MISR&GPT_INT_CBU)==GPT_INT_CBU) //Up-Counting phase CNT = CMPB Interrupt + { + GPT0->ICR = GPT_INT_CBU; + } + else if((GPT0->MISR&GPT_INT_CBD)==GPT_INT_CBD) //Down-Counting phase CNT = CMPB Interrupt + { + GPT0->ICR = GPT_INT_CBD; + } + else if((GPT0->MISR&GPT_INT_PEND)==GPT_INT_PEND) //End of cycle interrupt + { + GPT0->ICR = GPT_INT_PEND; + + //2024-06-16 修改 单独用于PWM 1ms定时控制 + PWM_Timer_1ms_Task(); + } +} +/*************************************************************/ +//RTC Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void RTCIntHandler(void) +{ + // ISR content ... + if((RTC->MISR&ALRA_INT)==ALRA_INT) //Interrupt of alarm A + { + RTC->ICR=ALRA_INT; + RTC->KEY=0XCA53; + RTC->CR=RTC->CR|0x01; + RTC->TIMR=(0x10<<16)|(0x00<<8)|(0x00); //Hour bit6->0:am 1:pm + while(RTC->CR&0x02); //busy TIMR DATR ALRAR ALRBR Update done + RTC->CR &= ~0x1; + } + else if((RTC->MISR&ALRB_INT)==ALRB_INT) //Interrupt of alarm B + { + RTC->ICR=ALRB_INT; + } + else if((RTC->MISR&CPRD_INT)==CPRD_INT) //Interrupt of alarm CPRD + { + RTC->ICR=CPRD_INT; + } + else if((RTC->MISR&RTC_TRGEV0_INT)==RTC_TRGEV0_INT) //Interrupt of trigger event 0 + { + RTC->ICR=RTC_TRGEV0_INT; + } + else if((RTC->MISR&RTC_TRGEV1_INT)==RTC_TRGEV1_INT) //Interrupt of trigger event 1 + { + RTC->ICR=RTC_TRGEV1_INT; + } +} +/*************************************************************/ +//UART0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART0IntHandler(void) +{ + char inchar = 0; + + // ISR content ... + if ((UART0->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + { + UART0->ISR=UART_RX_INT_S; + inchar = CSP_UART_GET_DATA(UART0); +// UARTTxByte(UART0,inchar); + } + else if( (UART0->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + { + UART0->ISR=UART_TX_INT_S; + //TxDataFlag = TRUE; + + PB_Send_String_INT(); + } + else if ((UART0->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + { + UART0->ISR=UART_RX_IOV_S; + } + else if ((UART0->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART0->ISR=UART_TX_IOV_S; + } +} +/*************************************************************/ +//UART1 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART1IntHandler(void) +{ + char inchar = 0; + + // ISR content ... + if ((UART1->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + { + UART1->ISR=UART_RX_INT_S; + inchar = CSP_UART_GET_DATA(UART1); + UART1_RecvINT_Processing(inchar); + + } + else if( (UART1->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + { + UART1->ISR=UART_TX_INT_S; + //TxDataFlag = TRUE; + } + else if ((UART1->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + { + UART1->ISR=UART_RX_IOV_S; + } + else if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART1->ISR=UART_TX_IOV_S; + } +} +/*************************************************************/ +//UART2 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void UART2IntHandler(void) +{ + // ISR content ... + if ((UART2->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt + { + UART2->ISR=UART_RX_INT_S; + //RxDataFlag = TRUE; + } + else if( (UART2->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt + { + UART2->ISR=UART_TX_INT_S; + //TxDataFlag = TRUE; + } + else if ((UART2->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt + { + UART2->ISR=UART_RX_IOV_S; + } + else if ((UART2->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt + { + UART2->ISR=UART_TX_IOV_S; + } +} +/*************************************************************/ +//I2C Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void I2CIntHandler(void) +{ + // ISR content ... + //I2C_Slave_Receive(); //I2C slave receive function in interruption +} +/*************************************************************/ +//SPI Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SPI0IntHandler(void) +{ + // ISR content ... + if((SPI0->MISR&SPI_PORIM)==SPI_PORIM) //Receive Overrun Interrupt + { + SPI0->ICR = SPI_PORIM; + } + else if((SPI0->MISR&SPI_RTIM)==SPI_RTIM) //Receive Timeout Interrupt + { + SPI0->ICR = SPI_RTIM; + } + else if((SPI0->MISR&SPI_RXIM)==SPI_RXIM) //Receive FIFO Interrupt,FIFO can be set 1/8,1/4,1/2 FIFO Interrupt + { + SPI0->ICR = SPI_RXIM; + if(SPI0->DR==0xaa) + { + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x11; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x12; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x13; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x14; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x15; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + +/* while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x16; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x17; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + + while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？ + SPI0->DR = 0x18; + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？*/ + } + else + { + if(((SPI0->SR) & SSP_TFE)!=SSP_TFE) + { + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + SPI0->DR=0x0; //FIFO=0 + while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？ + } + } + } + else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM) //Transmit FIFO Interrupt + { + SPI0->ICR = SPI_TXIM; + } + +} +/*************************************************************/ +//SIO Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void SIO0IntHandler(void) +{ + // ISR content ... + //The sequence is more than 16bit to send the program + //1.disable interrupt in main loop 2.set the highest priority in the interrupt + /*CK801->IPR[0]=0X40404040; + CK801->IPR[1]=0X40404040; + CK801->IPR[2]=0X40404040; + CK801->IPR[3]=0X40404040; + CK801->IPR[4]=0X40404040; + CK801->IPR[5]=0X40404000; + CK801->IPR[6]=0X40404040; + CK801->IPR[7]=0X40404040;*/ + //TXBUFEMPT The sequence length exceeds 15bit needs to be updated into this interrupt + /*if(SIO0->MISR&0X04) + { + SIO0->ICR=0X04; + if(R_SIOTX_count<1) + { + SIO0->TXBUF=(0x00<<30)|(0x00<<28)|(0x00<<26)|(0x00<<24)|(0x00<<22)|(0x00<<20)|(0x00<<18)|(0x00<<16)| + (0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x01<<4)|(0x01<<2)|(0x1<<0); //0:D0,1:D1,2:DL,3:DH; + R_SIOTX_count++; + } + } + if(SIO0->MISR&0X01) //TXDNE + { + SIO0->ICR=0X01; + if(R_SIOTX_count>=1) + { + delay_nms(10); + SIO0->TXBUF=(0x03<<30)|(0x02<<28)|(0x03<<26)|(0x02<<24)|(0x03<<22)|(0x02<<20)|(0x03<<18)|(0x02<<16)| + (0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x00<<4)|(0x01<<2)|(0x0<<0); //0:D0,1:D1,2:DL,3:DH; + R_SIOTX_count=0; + } + }*/ + + //The sequence is less than 16bit to send the program + /*if(SIO0->MISR&0X01) //TXDNE + { + SIO0->ICR=0X01; + delay_nms(10); + SIO0->TXBUF=(0x03<<30)|(0x02<<28)|(0x03<<26)|(0x02<<24)|(0x03<<22)|(0x02<<20)|(0x03<<18)|(0x02<<16)| + (0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x00<<4)|(0x01<<2)|(0x0<<0); //0:D0,1:D1,2:DL,3:DH; + }*/ + + if(SIO0->MISR&0X02) //RXDNE + { + SIO0->ICR=0X02; + if(R_SIORX_count>=1) + { + R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF&0xff000000; //8bit + nop; + R_SIORX_count=0; + } + } + else if(SIO0->MISR&0X08) //RXBUFFULL + { + SIO0->ICR=0X08; + if(R_SIORX_count<1) + { + R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF; //32bit + R_SIORX_count++; + } + } + else if(SIO0->MISR&0X010) //BREAK + { + SIO0->ICR=0X10; + } + else if(SIO0->MISR&0X020) //TIMEOUT + { + SIO0->ICR=0X20; + } +} +/*************************************************************/ +//EXT0/16 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI0IntHandler(void) +{ + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0) //EXT0 Interrupt + { + SYSCON->EXICR = EXI_PIN0; + } + else if ((SYSCON->EXIRS&EXI_PIN16)==EXI_PIN16) //EXT16 Interrupt + { + SYSCON->EXICR = EXI_PIN16; + } +} +/*************************************************************/ +//EXT1/17 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI1IntHandler(void) +{ + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1) //EXT1 Interrupt + { + SYSCON->EXICR = EXI_PIN1; + PB_OVERCURR_PWR_BUS_INT_Processing(); + } + else if ((SYSCON->EXIRS&EXI_PIN17)==EXI_PIN17) //EXT17 Interrupt + { + SYSCON->EXICR = EXI_PIN17; + } +} +/*************************************************************/ +//EXI2~3 18~19Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI2to3IntHandler(void) +{ + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2) //EXT2 Interrupt + { + SYSCON->EXICR = EXI_PIN2; + } + else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) //EXT3 Interrupt + { + SYSCON->EXICR = EXI_PIN3; + } + else if ((SYSCON->EXIRS&EXI_PIN18)==EXI_PIN18) //EXT18 Interrupt + { + SYSCON->EXICR = EXI_PIN18; + } + else if ((SYSCON->EXIRS&EXI_PIN19)==EXI_PIN19) //EXT19 Interrupt + { + SYSCON->EXICR = EXI_PIN19; + } +} +/*************************************************************/ +//EXI4~9 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI4to9IntHandler(void) +{ + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4) //EXT4 Interrupt + { + SYSCON->EXICR = EXI_PIN4; + } + else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5) //EXT5 Interrupt + { + SYSCON->EXICR = EXI_PIN5; + } + else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) //EXT6 Interrupt + { + SYSCON->EXICR = EXI_PIN6; + } + else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7) //EXT7 Interrupt + { + SYSCON->EXICR = EXI_PIN7; + } + else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8) //EXT8 Interrupt + { + SYSCON->EXICR = EXI_PIN8; + } + else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) //EXT9 Interrupt + { + SYSCON->EXICR = EXI_PIN9; + } + +} +/*************************************************************/ +//EXI4 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void EXI10to15IntHandler(void) +{ + // ISR content ... + if ((SYSCON->EXIRS&EXI_PIN10)==EXI_PIN10) //EXT10 Interrupt + { + SYSCON->EXICR = EXI_PIN10; + } + else if ((SYSCON->EXIRS&EXI_PIN11)==EXI_PIN11) //EXT11 Interrupt + { + SYSCON->EXICR = EXI_PIN11; + } + else if ((SYSCON->EXIRS&EXI_PIN12)==EXI_PIN12) //EXT12 Interrupt + { + SYSCON->EXICR = EXI_PIN12; + } + else if ((SYSCON->EXIRS&EXI_PIN13)==EXI_PIN13) //EXT13 Interrupt + { + SYSCON->EXICR = EXI_PIN13; + } + else if ((SYSCON->EXIRS&EXI_PIN14)==EXI_PIN14) //EXT14 Interrupt + { + SYSCON->EXICR = EXI_PIN14; + } + else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) //EXT15 Interrupt + { + SYSCON->EXICR = EXI_PIN15; + } +} +/*************************************************************/ +//CONTA Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void CNTAIntHandler(void) +{ + // ISR content ... +} +/*************************************************************/ +//LPT Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void LPTIntHandler(void) +{ + // ISR content ... + if((LPT->MISR&LPT_TRGEV0)==LPT_TRGEV0) //TRGEV0 interrupt + { + LPT->ICR = LPT_TRGEV0; + } + else if((LPT->MISR&LPT_MATCH)==LPT_MATCH) //MATCH interrupt + { + LPT->ICR = LPT_MATCH; + } + else if((LPT->MISR&LPT_PEND)==LPT_PEND) //PEND interrupt + { + LPT->ICR = LPT_PEND; + } +} + + +/*************************************************************/ +//BT0 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT0IntHandler(void) +{ + // ISR content ... + if((BT0->MISR&BT_PEND)==BT_PEND) //BT0 PEND interrupt + { + BT0->ICR = BT_PEND; + } + else if((BT0->MISR&BT_CMP)==BT_CMP) //BT0 CMP Match interrupt + { + BT0->ICR = BT_CMP; + + } + else if((BT0->MISR&BT_OVF)==BT_OVF) //BT0 OVF interrupt + { + BT0->ICR = BT_OVF; + } + else if((BT0->MISR&BT_EVTRG)==BT_EVTRG) //BT0 Event trigger interrupt + { + BT0->ICR = BT_EVTRG; + } +} + +volatile U32_T SysTick_100us = 0; +volatile U32_T SysTick_1ms = 0; + +/*************************************************************/ +//BT1 Interrupt +//EntryParameter:NONE +//ReturnValue:NONE +/*************************************************************/ +void BT1IntHandler(void) +{ + static U8_T NUM = 0; + // ISR content ... + if((BT1->MISR&BT_PEND)==BT_PEND) //BT1 PEND interrupt + { + BT1->ICR = BT_PEND; + } + else if((BT1->MISR&BT_CMP)==BT_CMP) //BT1 CMP Match interrupt + { + BT1->ICR = BT_CMP; + + NUM++; + SysTick_100us++; + + if(NUM >= 10){ + NUM = 0; + SysTick_1ms++; + + PB_Scan_State_Task(); + } + + } + else if((BT1->MISR&BT_OVF)==BT_OVF) //BT1 OVF interrupt + { + BT1->ICR = BT_OVF; + } + else if((BT1->MISR&BT_EVTRG)==BT_EVTRG) //BT1 Event trigger interrupt + { + BT1->ICR = BT_EVTRG; + } +} +/*************************************************************/ +/*************************************************************/ +/*************************************************************/ +void TKEYIntHandler(void) +{ + // ISR content ... + +} + +void PriviledgeVioHandler(void) +{ + // ISR content ... + +} + +void SystemDesPtr(void) +{ + // ISR content ... + +} + +void MisalignedHandler(void) +{ + // ISR content ... + +} + +void IllegalInstrHandler(void) +{ + // ISR content ... + +} + +void AccessErrHandler(void) +{ + // ISR content ... + +} + +void BreakPointHandler(void) +{ + // ISR content ... + +} + +void UnrecExecpHandler(void) +{ + // ISR content ... + +} + +void Trap0Handler(void) +{ + // ISR content ... + +} + +void Trap1Handler(void) +{ + // ISR content ... + +} + +void Trap2Handler(void) +{ + // ISR content ... + +} + +void Trap3Handler(void) +{ + // ISR content ... + +} + +void PendTrapHandler(void) +{ + // ISR content ... + +} +/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ + diff --git a/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.session b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.session new file mode 100644 index 0000000..ed59b42 --- /dev/null +++ b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.session @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.tags b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.tags new file mode 100644 index 0000000..6755c29 Binary files /dev/null and b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/APT32F102x_StdPeriph_Lib.tags differ diff --git a/Workspace/APT32F102x_StdPeriph_Lib/.cdk/refactoring.db b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/refactoring.db new file mode 100644 index 0000000..602adc9 Binary files /dev/null and b/Workspace/APT32F102x_StdPeriph_Lib/.cdk/refactoring.db differ diff --git a/Workspace/APT32F102x_StdPeriph_Lib/APT32F102x_StdPeriph_Lib.cdkws b/Workspace/APT32F102x_StdPeriph_Lib/APT32F102x_StdPeriph_Lib.cdkws new file mode 100644 index 0000000..9af6a88 --- /dev/null +++ b/Workspace/APT32F102x_StdPeriph_Lib/APT32F102x_StdPeriph_Lib.cdkws @@ -0,0 +1,11 @@ + + + $(CDKWS)\__workspace_pack__ + + + + + + + + diff --git a/Workspace/APT32F102x_StdPeriph_Lib/cdkws.mk b/Workspace/APT32F102x_StdPeriph_Lib/cdkws.mk new file mode 100644 index 0000000..f0f7a3b --- /dev/null +++ b/Workspace/APT32F102x_StdPeriph_Lib/cdkws.mk @@ -0,0 +1,14 @@ +.PHONY: clean All Project_Title Project_Build + +All: Project_Title Project_Build + +Project_Title: + @echo "----------Building project:[ apt32f102 - BuildSet ]----------" + +Project_Build: + @make -r -f apt32f102.mk -j 8 -C D:/MyCode/APT/Project_Code/APT32F1023_Test_20230728/Source + + +clean: + @echo "----------Cleaning project:[ apt32f102 - BuildSet ]----------" +