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修复开关控制组控的控制异常问题

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修改PB开关状态组控处理，解决后32路的开关状态会复用上前32个回路的数据
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yanghongfeng
2026-01-19 15:32:11 +08:00
commit f25132cbe3
292 changed files with 44556 additions and 0 deletions
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500
Source/FWlib/apt32f102_adc.c Normal file
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/*
******************************************************************************
* @file apt32f102_adc.c
* @author APT AE Team
* @version V1.13
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_adc.h"
/* defines -------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//ADC12 RESET VALUE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC12_RESET_VALUE(void)
{
ADC0->ECR = ADC_ECR_RST; /**< ECR reset value */
ADC0->DCR = ADC_DCR_RST; /**< DCR reset value */
ADC0->PMSR = ADC_PMSR_RST; /**< PMSR reset value */
//ADC0->CR = ADC_CR_RST; /**< CR reset value */
ADC0->MR = ADC_MR_RST; /**< MR reset value */
ADC0->CSR = ADC_CSR_RST; /**< CSR reset value */
ADC0->SR = ADC_SR_RST; /**< SR reset value */
ADC0->IER = ADC_IER_RST; /**< IER reset value */
ADC0->IDR = ADC_IDR_RST; /**< IDR reset value */
ADC0->IMR = ADC_IMR_RST; /**< IMR reset value */
ADC0->SEQ[0]= ADC_SEQx_RST; /**< SEQ0 reset value */
ADC0->SEQ[1]= ADC_SEQx_RST; /**< SEQ1 reset value */
ADC0->SEQ[2]= ADC_SEQx_RST; /**< SEQ2 reset value */
ADC0->SEQ[3]= ADC_SEQx_RST; /**< SEQ3 reset value */
ADC0->SEQ[4]= ADC_SEQx_RST; /**< SEQ4 reset value */
ADC0->SEQ[5]= ADC_SEQx_RST; /**< SEQ5 reset value */
ADC0->SEQ[6]= ADC_SEQx_RST; /**< SEQ6 reset value */
ADC0->SEQ[7]= ADC_SEQx_RST; /**< SEQ7 reset value */
ADC0->SEQ[8]= ADC_SEQx_RST; /**< SEQ8 reset value */
ADC0->SEQ[9]= ADC_SEQx_RST; /**< SEQ9 reset value */
ADC0->SEQ[10]= ADC_SEQx_RST; /**< SEQ10 reset value */
ADC0->SEQ[11]= ADC_SEQx_RST; /**< SEQ11 reset value */
ADC0->SEQ[12]= ADC_SEQx_RST; /**< SEQ12 reset value */
ADC0->SEQ[13]= ADC_SEQx_RST; /**< SEQ13 reset value */
ADC0->SEQ[14]= ADC_SEQx_RST; /**< SEQ14 reset value */
ADC0->SEQ[15]= ADC_SEQx_RST; /**< SEQ15 reset value */
ADC0->DR[0] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[1] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[2] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[3] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[4] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[5] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[6] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[7] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[8] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[9] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[10] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[11] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[12] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[13] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[14] = ADC_DR_RST; /**< DR reset value */
ADC0->DR[15] = ADC_DR_RST; /**< DR reset value */
ADC0->CMP0 = ADC_CMP0_RST; /**< CMP1 reset value */
ADC0->CMP1 = ADC_CMP1_RST; /**< CMP2 reset value */
}
/*************************************************************/
//ADC12 Control
//EntryParameter:ADC12_Control_x
//ADC12_Control_x:ADC12_SWRST , ADC12_ADCEN , ADC12_ADCDIS, ADC12_START, ADC12_STOP,ADC12_SWTRG
//ReturnValue:NONE
/*************************************************************/
//control:ADC enable/disable ,start/stop,swrst
void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x )
{
ADC0->CR |= ADC12_Control_x; //
}
/*************************************************************/
//ADC12 Interrupt ENABLE AND DISABLE
//EntryParameter:ADC_IMR_X,NewState
//ADC_IMR_X:ADC12_EOC,ADC12_READY,ADC12_OVR,ADC12_CMP0H,ADC12_CMP0L,ADC12_CMP1H,ADC12_CMP1L,ADC12_SEQ_END0~15
//NewState:ENABLE , DISABLE
//ReturnValue:NONE
/*************************************************************/
//ADC12_EOC:End of conversion interrupt
//ADC12_READY:ADC ready for conversion interrupt
//ADC12_OVR:Overrun interrupt
//ADC12_CMP0H:Higher than ADC_CMP1 interrupt
//ADC12_CMP0L:Lower than ADC_CMP1 interrupt
//ADC12_CMP1H:Higher than ADC_CMP2 interrupt
//ADC12_CMP1L:Lower than ADC_CMP2 interrupt
//ADC12_SEQ_END0~15:SEQx convert end interrupt
void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
ADC0->IER |= ADC_IMR_X; //SET
}
else
{
ADC0->IDR |= ADC_IMR_X; //CLR
}
}
/*************************************************************/
//Read ADC12 Interrupt ENABLE status
//EntryParameter:EnStatus_bit
//EnStatus_bit:ADC12_EOC,ADC12_READY,ADC12_OVR,ADC12_CMP1H,ADC12_CMP1L,ADC12_CMP2H,ADC12_CMP2L,ADC12_SEQ_END0~15
//ReturnValue:1=enabled/0=disabled
/*************************************************************/
uint8_t ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit)
{
uint8_t value = 0;
uint32_t dat = 0;
dat= ADC0->IMR&EnStatus_bit;
if (dat == EnStatus_bit)
{
value = 1;
}
return value;
}
/*************************************************************/
//ADC12 CLK ENABLE AND DISABLE
//EntryParameter:ADC_CLK_CMD,NewState
//ADC_CLK_CMD:ADC_CLK_CR,ADC_DEBUG_MODE
//NewState:ENABLE , DISABLE
//ReturnValue:NONE
/*************************************************************/
void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
ADC0->ECR |= ADC_CLK_CMD; //ENABLE
while(!(ADC0->PMSR&ADC_CLK_CMD));
}
else
{
ADC0->DCR |= ADC_CLK_CMD; //DISABLE
while(ADC0->PMSR&ADC_CLK_CMD);
}
}
/*************************************************************/
//ADC12 software reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC12_Software_Reset(void)
{
ADC12_Control(ADC12_SWRST);
}
/*************************************************************/
//ADC12 ENABLE
//EntryParameter:NewState
//NewState:ENABLE , DISABLE
//ReturnValue:NONE
/*************************************************************/
void ADC12_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
ADC12_Control(ADC12_ADCEN); //ADC12 ENABLE
while(!(ADC0->SR &ADC12_ADCENS));
}
else
{
ADC12_Control(ADC12_ADCDIS); //ADC12 DISABLE
while(ADC0->SR&ADC12_ADCENS);
}
}
/*************************************************************/
//ADC12 READY wait
//EntryParameter:NONE
//ReturnValue:ADC12 READ FLAG
/*************************************************************/
void ADC12_ready_wait(void)
{
while(!(ADC0->SR&ADC12_READY)); // Waiting for ADC0 Ready
}
/*************************************************************/
//ADC12 End of conversion wait
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/
void ADC12_EOC_wait(void)
{
while(!(ADC0->SR & ADC12_EOC)); // EOC wait
}
/*************************************************************/
//ADC12 End of conversion wait
//EntryParameter:NONE
//ReturnValue:ADC12 EOC
/*************************************************************/
void ADC12_SEQEND_wait(U8_T val)
{
while(!(ADC0->SR & (0x01ul << (16+val)))); // EOC wait
}
/*************************************************************/
//ADC12 Data Register output
//EntryParameter:NONE
//ReturnValue:ADC12 DR
/*************************************************************/
U16_T ADC12_DATA_OUPUT(U16_T Data_index )
{
return(ADC0->DR[Data_index]);
}
/*************************************************************/
//ADC12 Configure
//EntryParameter:ADC12_BIT_SELECTED,ADC12_ConverMode,ADC12_DIV,NumConver
//ADC12_BIT_SELECTED:ADC12_12BIT,ADC12_10BIT
//ADC12_ConverMode:One_shot_mode,Continuous_mode
//ADC12_PRI:0~15
//adc12_SHR:0~255
//ADC12_DIV:0~31
//NumConver:Number of Conversions value=(1~12);
//ReturnValue:NONE
/*************************************************************/
//10BIT or 12BIT adc ;
//ADC12_BIT_SELECTED:ADC12_12BIT/ADC12_10BIT;
//ADC12_ConverMode:One_shot_mode/Continuous_mode;
//adc date output=last number of Conversions;
void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver )
{
ADC0->MR=ADC12_DIV|((NumConver-1)<<10);
if(ADC12_ConverMode==One_shot_mode)
{
ADC0->MR&=~CONTCV; //one short mode
while(ADC0->SR&ADC12_CTCVS);
}
else if(ADC12_ConverMode==Continuous_mode)
{
ADC0->MR|=CONTCV; //Continuous mode
while(!(ADC0->SR&ADC12_CTCVS));
}
ADC12_CMD(ENABLE); //ADC0 enable
if(ADC12_BIT_SELECTED)
{
ADC0->CR|=ADC12_10BITor12BIT;
}
else
{
ADC0->CR&=~ADC12_10BITor12BIT;
}
//ADC0->CR|=ADC12_VREF_VDD | ADC12_FVR_DIS;
ADC0->PRI=ADC12_PRI;
ADC0->SHR=adc12_SHR; //adc Sampling & Holding cycles
}
/*************************************************************/
//ADC12 VREF slection=VDD
//EntryParameter:NONE
//ReturnValue:None
/*************************************************************/
void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X )
{
if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_VSS)
{
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x00<<6);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_VSS)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x01<<6);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_VSS)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x02<<6)|(0X01<<24)|(0X00<<25);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_VSS)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x03<<6)|(0X01<<24)|(0X01<<25);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_VSS)
{
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x04<<6)|(0X00<<16)|(0X02<<17);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_VDD_VREFN_EXIT)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000;
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x08<<6);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_EXIT_VREFN_EXIT)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000;
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x09<<6);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR2048_VREFN_EXIT)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000;
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0A<<6)|(0X01<<24)|(0X00<<25);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_FVR4096_VREFN_EXIT)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000;
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0x00000800;
ADC0->CR=(ADC0->CR&0xfcfefc3f)|(0x0B<<6)|(0X01<<24)|(0X01<<25);
}
else if(ADC12_VREFP_X_VREFN_X==ADC12_VREFP_INTVREF1000_VREFN_EXIT)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x0000B000;
ADC0->CR=(ADC0->CR&0xfffefc3f)|(0x0C<<6)|(0X00<<16)|(0X02<<17);
}
}
/*************************************************************/
//ADC12 Compare function set
//EntryParameter:ConverNum_CM0,ConverNum_CM1,CMP0_data,CMP1_data
//ConverNum_CM0:VALUE=(0~15)
//ConverNum_CM1:VALUE=(0~15)
//CMP0_data:VALUE=(1~(0X3FF/0XFFF))
//CMP1_data:VALUE=(1~(0X3FF/0XFFF))
//ReturnValue:NONE
/*************************************************************/
//ConverNum_CM0:Number of Conversions for Compare Function
//ConverNum_CM1:Number of Conversions for Compare Function
//ADC will generate a CMPxH/CMPxL interrupt when result of this number of conversion is higher/lower than data set in ADC_CMPx register.
//ConverNum_CM1Number of Conversions for Compare Function
//ADC will generate a CMP1H/CMP1L interrupt when result of this number of conversion is greater/less than data set in ADC_CMP1 register.
void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data )
{
ADC0->MR|=((ConverNum_CM0-0)<<16)|((ConverNum_CM1-0)<<22);
ADC0->CMP0=CMP0_data;
ADC0->CMP1=CMP1_data;
}
/*************************************************************/
//ADC12 Conversion chanle seting
//EntryParameter:ADC12_3/4/6/8CYCLES,SEQx,ADC12_ADCINX,ADC12_CV_RepeatNum1/2/4/8/16/32/64/128
//SEQx:VALUE=(1~18)
//ADC12_ADCINX:ADC12_ADCIN0~ADC12_ADCIN17,ADC12_INTVREF,ADC12_DIV4_VDD,ADC12_VSS
//ReturnValue:NONE
/*************************************************************/
void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx)
{
U8_T i;
for(i=0;i<15;i++)
{
ADC0->SEQ[i] &=~(0x01<<7);
}
switch(ADC12_ADCINX)
{
case 0:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC0 PB0.1
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0x00000010;
break;
case 1:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000001; //ADC1 PA0.0
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 2:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000010; //ADC2 PA0.1
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 3:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00001000; //ADC3 PA0.3
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 4:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00100000; //ADC4 PA0.5
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 5:
GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x01000000; //ADC5 PA0.6
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 6:
GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x10000000; //ADC6 PA0.7
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 7:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC7 PB0.2
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000100;
break;
case 8:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC8 PB0.3
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0x00001000;
break;
case 9:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC9 PA0.8
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000001;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 10:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC10 PA0.9
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0x00000010;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 11:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC11 PA0.10
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0x00000100;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 12:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC12 PA0.11
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0x00001000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 13:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC13 PA0.12
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00010000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 14:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC14 PA0.13
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00100000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFFF) | 0x00000000;
break;
case 15:
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFFF) | 0x00000000; //ADC15 PB0.0
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0x00000000;
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000001;
break;
//case 18: break;
//case 19: break;
//case 20: break;
//case 21: break;
//case 22: break;
//case 23: break;
//case 24: break;
//case 25: break;
//case 26: break;
//case 27: break;
case 0x1Cul: break;
case 0x1Dul: break;
case 0x1Eul: break;
}
ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] & 0;
ADC0->SEQ[SEQx] = ADC0->SEQ[SEQx] | ADC12_ADCINX | CV_RepeatTime | AVG_Set;
}
/*************************************************************/
//ADC12 Compare statue output
//EntryParameter:NBRCMPx_TypeDef,NBRCMPX_L_TypeDef
//NBRCMPx_TypeDef:NBRCMP0_TypeDef,NBRCMP1_TypeDef
//NBRCMPX_L_TypeDef:NBRCMPX_L_TypeDef,NBRCMPX_H_TypeDef
//ReturnValue:ADC12 Compare result flag
/*************************************************************/
//output statue:ADC-SR(ADC12_CMP0H/ADC12_CMP0L/ADC12_CMP1H/ADC12_CMP1L)
U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL)
{
if(ADC12_NBRCMPx==NBRCMP0_TypeDef)
{
if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
{
return((ADC0->SR)&ADC12_CMP0L);
}
else
{
return((ADC0->SR)&ADC12_CMP0H);
}
}
else
{
if(ADC12_NBRCMPx_HorL==NBRCMPX_L_TypeDef)
{
return((ADC0->SR)&ADC12_CMP1L);
}
else
{
return((ADC0->SR)&ADC12_CMP1H);
}
}
}
/*************************************************************/
//ADC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Enable(void)
{
ADC0->CSR=0xFFFFFFFF;
INTC_ISER_WRITE(ADC_INT);
}
/*************************************************************/
//ADC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ADC_Int_Disable(void)
{
INTC_ICER_WRITE(ADC_INT);
}

287
Source/FWlib/apt32f102_bt.c Normal file
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/*
******************************************************************************
* @file apt32f102_bt.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_bt.h"
/* defines -------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_DeInit(CSP_BT_T *BTx)
{
BTx->RSSR=BT_RESET_VALUE;
BTx->CR=BT_RESET_VALUE;
BTx->PSCR=BT_RESET_VALUE;
BTx->PRDR=BT_RESET_VALUE;
BTx->CMP=BT_RESET_VALUE;
BTx->CNT=BT_RESET_VALUE;
BTx->EVTRG=BT_RESET_VALUE;
BTx->EVSWF=BT_RESET_VALUE;
BTx->RISR=BT_RESET_VALUE;
BTx->IMCR=BT_RESET_VALUE;
BTx->MISR=BT_RESET_VALUE;
BTx->ICR=BT_RESET_VALUE;
}
/*************************************************************/
//BT IO Init
//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10,
//ReturnValue:NONE
/*************************************************************/
void BT_IO_Init(BT_Pin_TypeDef BT_IONAME)
{
if(BT_IONAME==BT0_PA00)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; //BT0 PA0.0
}
if(BT_IONAME==BT0_PA02)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000600; //BT0 PA0.2
}
if(BT_IONAME==BT0_PA05)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00500000; //BT0 PA0.5
}
if(BT_IONAME==BT0_PB02)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFF0FF)|0x00000500; //BT0 PB0.2
}
if(BT_IONAME==BT0_PB05)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFF0FFFFF)|0x00700000; //BT0 PB0.5
}
if(BT_IONAME==BT0_PA11)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00008000; //BT0 PA0.11
}
if(BT_IONAME==BT0_PA13)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00800000; //BT0 PA0.13
}
if(BT_IONAME==BT0_PA15)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x50000000; //BT0 PA0.15
}
if(BT_IONAME==BT1_PA01)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000060; //BT1 PA0.1
}
if(BT_IONAME==BT1_PA06)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x04000000; //BT1 PA0.6
}
if(BT_IONAME==BT1_PA08)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFFF0)|0x00000006; //BT1 PA0.8
}
if(BT_IONAME==BT1_PA12)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00060000; //BT1 PA0.12
}
if(BT_IONAME==BT1_PA14)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x05000000; //BT1 PA0.14
}
if(BT_IONAME==BT1_PB00)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000008; //BT1 PB0.0
}
if(BT_IONAME==BT1_PB04)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFF0FFFF)|0x00070000; //BT1 PB0.4
}
}
/*************************************************************/
// BT start
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Start(CSP_BT_T *BTx)
{
BTx->RSSR |=0X01;
}
/*************************************************************/
// BT stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop(CSP_BT_T *BTx)
{
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT stop High
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop_High(CSP_BT_T *BTx)
{
BTx->CR |=(0x01<<6);
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT stop Low
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Stop_Low(CSP_BT_T *BTx)
{
BTx->CR =BTx->CR & ~(0x01<<6);
BTx->RSSR &=0X0;
}
/*************************************************************/
// BT soft reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT_Soft_Reset(CSP_BT_T *BTx)
{
BTx->RSSR |= (0X5<<12);
}
/*************************************************************/
//BT Configure
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM)
{
BTx->CR |=BTCLK| BTSHDWSTP| BTOPM| BTEXTCKM;
BTx->PSCR = PSCR_DATA;
}
/*************************************************************/
//BT ControlSet
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD,
BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD)
{
BTx->CR |=BTSTART| BTIDLE| BTSYNC| BTSYNCMD| BTOSTMD| BTAREARM| BTCNTRLD;
}
/*************************************************************/
//BT Period / Compare set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA)
{
//BTx->CR|=0X01<<2;
BTx->PRDR =BTPRDR_DATA;
BTx->CMP =BTCMP_DATA;
}
/*************************************************************/
//BT COUNTER set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA)
{
BTx->CNT =BTCNT_DATA;
}
/*************************************************************/
//BT read counters
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
U16_T BT_PRDR_Read(CSP_BT_T *BTx)
{
return BTx->PRDR;
}
U16_T BT_CMP_Read(CSP_BT_T *BTx)
{
return BTx->CMP;
}
U16_T BT_CNT_Read(CSP_BT_T *BTx)
{
return BTx->CNT;
}
/*************************************************************/
//BT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE)
{
BTx->EVTRG|=BTTRG| BTTRGOE;
}
/*************************************************************/
//BT SOFT Trigger
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void BT_Soft_Tigger(CSP_BT_T *BTx)
{
BTx->EVSWF=0x01;
}
/*************************************************************/
//BT inturrpt Configure
//EntryParameter:BT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X)
{
if (NewState != DISABLE)
{
BTx->IMCR |= BT_IMSCR_X;
}
else
{
BTx->IMCR &= ~BT_IMSCR_X;
}
}
/*************************************************************/
//BT0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT0_INT_ENABLE(void)
{
INTC_ISER_WRITE(BT0_INT);
}
/*************************************************************/
//BT0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT0_INT_DISABLE(void)
{
INTC_ICER_WRITE(BT0_INT);
}
/*************************************************************/
//BT0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT1_INT_ENABLE(void)
{
INTC_ISER_WRITE(BT1_INT);
}
/*************************************************************/
//BT0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void BT1_INT_DISABLE(void)
{
INTC_ICER_WRITE(BT1_INT);
}

147
Source/FWlib/apt32f102_coret.c Normal file
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/*
******************************************************************************
* @file apt32f102_CORET.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_coret.h"
#include "apt32f102_syscon.h"
/* defines -------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the syscon registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_DeInit(void)
{
CK801->CORET_CSR=CORET_CSR_RST;
CK801->CORET_RVR=CORET_RVR_RST;
CK801->CORET_CVR=CORET_CVR_RST;
CK801->CORET_CALIB=CORET_CALIB_RST;
}
/*************************************************************/
//CORET Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_Int_Enable(void)
{
CK801->CORET_CVR = 0x0; // Clear counter and flag
INTC_ISER_WRITE(CORET_INT);
}
/*************************************************************/
//CORET Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_Int_Disable(void)
{
INTC_ICER_WRITE(CORET_INT);
}
/*************************************************************/
// CORET Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_WakeUp_Enable(void)
{
INTC_IWER_WRITE(CORET_INT);
}
/*************************************************************/
// CORET Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(CORET_INT);
}
/*************************************************************/
// CORET START
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_start(void)
{
CK801->CORET_CSR|=0x01;
}
/*************************************************************/
// CORET stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_stop(void)
{
CK801->CORET_CSR&=0Xfffffffe;
}
/*************************************************************/
// CORET CLKSOURC EX
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_CLKSOURCE_EX(void)
{
CK801->CORET_CSR&=0Xfffffffb;
}
/*************************************************************/
// CORET CLKSOURC IN
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_CLKSOURCE_IN(void)
{
CK801->CORET_CSR|=0x04;
}
/*************************************************************/
//CORET TICKINT enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_TICKINT_Enable(void)
{
CK801->CORET_CSR|=0x02;
}
/*************************************************************/
//CORET TICKINT enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_TICKINT_Disable(void)
{
CK801->CORET_CSR&=0Xfffffffd;
}
/*************************************************************/
// CORET reload
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CORET_reload(void)
{
CK801->CORET_CVR = 0x0; // Clear counter and flag
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

153
Source/FWlib/apt32f102_countera.c Normal file
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/*
******************************************************************************
* @file apt32f102_countera.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_countera.h"
/* defines -------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Count A RESET,CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void COUNT_DeInit(void)
{
CA0->CADATAH = CA_RESET_VALUE;
CA0->CADATAL = CA_RESET_VALUE;
CA0->CACON = CA_RESET_VALUE;
CA0->INTMASK = CA_RESET_VALUE;
}
/*************************************************************/
//CountA Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Int_Enable(void)
{
INTC_ISER_WRITE(CA_INT);
}
/*************************************************************/
//CountA Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Int_Disable(void)
{
INTC_ICER_WRITE(CA_INT);
}
/*************************************************************/
//CountA Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Wakeup_Enable(void)
{
INTC_IWER_WRITE(CA_INT);
}
/*************************************************************/
//CountA Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Wakeup_Disable(void)
{
INTC_IWDR_WRITE(CA_INT);
}
/*************************************************************/
//CountA Init
//EntryParameter:Data_H,Data_L,INT_Mode,DIVx,Mode,Carrier,OSP_Mode
//Data_H,Data_L:0x0000~0xFFFF
//INT_MODE:Period_NA/Period_H/Period_L/Period_H_L
//DIVx:DIV1/DIV2/DIV4/DIV8
//Mode:ONESHOT_MODE / REPEAT_MODE
//Carrier:CARRIER_OFF / CARRIER_ON
//OSP_Mode:OSP_LOW /OSP_HIGH
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Init(uint32_t Data_H,uint32_t Data_L,CA_INT_TypeDef INT_Mode,
CA_CLKDIV_TypeDef DIVx,CA_Mode_TypeDef Mode,CA_CARRIER_TypeDef Carrier,
CA_OSP_TypeDef OSP_Mode)
{
COUNT_DeInit();
CA0->CADATAH = Data_H;//0x0000~0xFFFF time(us)/(1/F Mhz) eg:10us/(1/4)=10us/0.25us=40,Data_H=40
CA0->CADATAL = Data_L;//0x0000~0xFFFF
CA0->CACON = DIVx | Mode | Carrier | OSP_Mode ;
CA0->INTMASK = INT_Mode ;
}
/*************************************************************/
//CountA config
//EntryParameter:STROBE,Pend_val,Match_val,Stat_val,ENVELOPE
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Config(CA_STROBE_TypeDef STROBE,CA_PENDREM_TypeDef Pend_CON,
CA_MATCHREM_TypeDef Match_CON,CA_REMSTAT_TypeDef Stat_CON,CA_ENVELOPE_TypeDef ENVELOPE )
{
CA0->CACON = CA0->CACON | STROBE | Pend_CON | Match_CON | Stat_CON | ENVELOPE;
}
/*************************************************************/
//CountA Start
//EntryParameter:none
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Start(void)
{
CA0->CACON=(CA0->CACON&0xFFFFFFF3)|0X04; //bit 2,This bit be cleared automatically
}
/*************************************************************/
//CountA Stop
//EntryParameter:none
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Stop(void)
{
CA0->CACON=(CA0->CACON&0xFFFFFFF7)|0X08; //bit 4
}
/*************************************************************/
//CountA data update
//EntryParameter:none
//ReturnValue:NONE
/*************************************************************/
void COUNTA_Data_Update(uint32_t Data_H,uint32_t Data_L)
{
CA0->CADATAH = Data_H;//0x0000~0xFFFF time(us)/(1/F Mhz) eg:10us/(1/4)=10us/0.25us=40,Data_H=40
CA0->CADATAL = Data_L;//0x0000~0xFFFF
CA0->CACON = CA0->CACON | (1ul<<16);
}
/*************************************************************/
//CountA Stop
//EntryParameter:COUNTA_IO_G0
//COUNTA_IO_G:0 PB0.01 1 PA0.05 2 PA0.11
//ReturnValue:NONE
/*************************************************************/
void COUNTA_IO_Init(CA_COUNTAIO_TypeDef COUNTA_IO_G)
{
if(COUNTA_IO_G==0)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000040; //BUZZ (PB0.01->AF1)
}
else if(COUNTA_IO_G==1)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFF0FFFFF)|0x00600000; //BUZZ (PA0.05->AF4)
}
else if(COUNTA_IO_G==2)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00007000; //BUZZ (PA0.11->AF3)
}
}

150
Source/FWlib/apt32f102_crc.c Normal file
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/*
******************************************************************************
* @file apt32f102_crc.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_crc.h"
/*************************************************************/
// CRC enable/disable
//EntryParameter:ENABLE/DISABLE
//ReturnValue:NONE
/*************************************************************/
void CRC_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
CRC->CEDR =0X01; //SET
}
else
{
CRC->CEDR =0X00; //CLR
}
}
/*************************************************************/
//CRC RESET
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CRC_Soft_Reset(void)
{
CRC->SRR = 0X01;
}
/*************************************************************/
//CRC CONTROL
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CRC_Configure(CRC_COMPIN_TypeDef COMPINX,CRC_COMPOUT_TypeDef COMPOUTX,CRC_ENDIANIN_TypeDef ENDIANINX,
CRC_ENDIANOUT_TypeDef ENDIANOUT,CRC_POLY_TypeDef POLYX)
{
CRC->CR = 0;
CRC->CR |= COMPINX |COMPOUTX |ENDIANINX |ENDIANOUT| POLYX;
}
/*************************************************************/
//CRC seed write
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CRC_Seed_Write(U32_T seed_data)
{
CRC->SEED = seed_data;
}
/*************************************************************/
//CRC seed read
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U32_T CRC_Seed_Read(void)
{
return CRC->SEED;
}
/*************************************************************/
//CRC datain
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void CRC_Datain(U32_T data_in)
{
CRC->DATAIN=data_in;
}
/*************************************************************/
//CRC Result read
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U32_T CRC_Result_Read(void)
{
return CRC->DATAOUT;
}
/*************************************************************/
//CRC calc 32bit input
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U32_T Chip_CRC_CRC32(U32_T *data, U32_T words)
{
while (words > 0) {
CRC_Datain(*data);
data++;
words--;
}
return CRC_Result_Read();
}
/*************************************************************/
//CRC calc 16bit input
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U32_T Chip_CRC_CRC16(U16_T *data, U32_T size)
{
U32_T i,j;
U8_T data_temp;
for (i=0; i<size; i++)
{
for(j=0;j<=1;j++)
{
if(j==0)data_temp=*data>>8;
if(j==1)data_temp=*data&0xff;
*(U8_T *)(AHB_CRCBase + 0x14 + (i%4)) = data_temp;
}
data++;
}
return CRC_Result_Read();
}
/*************************************************************/
//CRC calc 8bit input
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U32_T Chip_CRC_CRC8(U8_T *data, U32_T size)
{
U32_T i;
for (i=0; i<size; i++)
{
*(U8_T *)(AHB_CRCBase + 0x14 + (i%4)) = *data;
data++;
}
return CRC_Result_Read();
}

868
Source/FWlib/apt32f102_ept.c Normal file
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/*
******************************************************************************
* @file apt32f102_ept.c
* @author APT AE Team
* @version V1.08
* @date 2021/03/29
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_ept.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the EPT Software prg
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT_Software_Prg(void)
{
EPT0->CEDR|=0X01;
EPT0->RSSR=(EPT0->RSSR&0XFFFF0FFF)|(0X05<<12);
}
/*************************************************************/
//Deinitializes the EPT start prg
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT_Start(void)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->RSSR|=0X01;
while(!(EPT0->RSSR&0x01));
}
/*************************************************************/
//Deinitializes the EPT stop prg
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT_Stop(void)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->RSSR&=0Xfe;
while(EPT0->RSSR&0x01);
}
/*************************************************************/
//Deinitializes the EPT IO Config,IO_Num_X
//EntryParameter:EPT_IO_Mode_Type
//EPT_IO_X:EPT_IO_CHAX,EPT_IO_CHAY,EPT_IO_CHBX,EPT_IO_CHBY,EPT_IO_CHCX,EPT_IO_CHCX,EPT_IO_CHD,EPT_IO_EPI
//ReturnValue:NONE
/*************************************************************/
void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X)
{
if(EPT_IO_X==EPT_IO_CHAX)
{
if(IO_Num_X==IO_NUM_PA07)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X60000000; //PA0.7
}
else if(IO_Num_X==IO_NUM_PA10)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)|0X00000500; //PA0.10
}
else if(IO_Num_X==IO_NUM_PA15)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF)|0X40000000; //PA0.15
}
}
else if(EPT_IO_X==EPT_IO_CHAY)
{
if(IO_Num_X==IO_NUM_PB03)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00005000; //PB0.3
}
else if(IO_Num_X==IO_NUM_PB05)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00500000; //PB0.5
}
else if(IO_Num_X==IO_NUM_PA12)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)|0X00050000; //PA0.12
}
}
else if(EPT_IO_X==EPT_IO_CHBX)
{
if(IO_Num_X==IO_NUM_PB02)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000600; //PB0.2
}
else if(IO_Num_X==IO_NUM_PA11)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)|0X00005000; //PA0.11
}
else if(IO_Num_X==IO_NUM_PA14)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)|0X04000000; //PA0.14
}
}
else if(EPT_IO_X==EPT_IO_CHBY)
{
if(IO_Num_X==IO_NUM_PB04)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00050000; //PB0.4
}
else if(IO_Num_X==IO_NUM_PA05)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)|0X00800000; //PA0.5
}
else if(IO_Num_X==IO_NUM_PA08)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000005; //PA0.8
}
}
else if(EPT_IO_X==EPT_IO_CHCX)
{
if(IO_Num_X==IO_NUM_PB05)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00400000; //PB0.5
}
else if(IO_Num_X==IO_NUM_PA03)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF)|0X00005000; //PA0.3
}
else if(IO_Num_X==IO_NUM_PB03)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00004000; //PB0.3
}
else if(IO_Num_X==IO_NUM_PB00)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)|0X00000005; //PB0.0
}
}
else if(EPT_IO_X==EPT_IO_CHCY)
{
if(IO_Num_X==IO_NUM_PB04)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00040000; //PB0.4
}
else if(IO_Num_X==IO_NUM_PA04)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF)|0X00050000; //PA0.4
}
else if(IO_Num_X==IO_NUM_PA09)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)|0X00000070; //PA0.9
}
else if(IO_Num_X==IO_NUM_PA013)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00500000; //PA0.13
}
}
else if(EPT_IO_X==EPT_IO_CHD)
{
if(IO_Num_X==IO_NUM_PB03)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00006000; //PB0.3
}
else if(IO_Num_X==IO_NUM_PA08)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000004; //PA0.8
}
}
else if(EPT_IO_X==EPT_IO_EPI)
{
if(IO_Num_X==IO_NUM_PA07)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X50000000; //PA0.7 EPI0
}
else if(IO_Num_X==IO_NUM_PA013)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00400000; //PA0.13 EPI1
}
else if(IO_Num_X==IO_NUM_PB03)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00007000; //PB0.3 EPI2
}
else if(IO_Num_X==IO_NUM_PB02)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700; //PB0.2 EPI3
}
}
}
/*************************************************************/
//Deinitializes the EPT PWM Config
//EntryParameter:EPT_TCLK_Selecte_X,EPT_CNTMD_SELECTE_X,EPT_OPM_SELECTE_X,EPT_PSCR
//EPT_TCLK_Selecte_X:EPT_Selecte_PCLK,EPT_Selecte_SYNCUSR3
//EPT_CNTMD_SELECTE_X:EPT_CNTMD_increase,EPT_CNTMD_decrease,EPT_CNTMD_increaseTOdecrease
//EPT_OPM_SELECTE_X:EPT_OPM_Once,EPT_OPM_Continue
//EPT_PSCR:0~0XFFFF
//ReturnValue:NONE
/*************************************************************/
//Fclk=Fpclk/(PSC+1)
void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X
, U16_T EPT_PSCR)
{
EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6));
if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK)
{
EPT0->PSCR=EPT_PSCR;
}
EPT0->CR=(EPT0->CR&0xfff8ffc0)|EPT_CNTMD_SELECTE_X|(0x1<<2)|(0x0<<3)|(0x0<<4)|EPT_OPM_SELECTE_X|(0X0<<16)|(0x1<<18);
}
/*************************************************************/
//Deinitializes the EPT PWM Config
//EntryParameter:EPT_CGSRC_TIN_Selecte_X,EPT_CGFLT_DIV,EPT_CGFLT_CNT,EPT_BURST_CMD
//EPT_CGSRC_TIN_Selecte_X:EPT_CGSRC_TIN_BT0OUT,EPT_CGSRC_TIN_BT1OUT,EPT_CGSRC_CHAX,EPT_CGSRC_CHBX,EPT_CGSRC_DIS
//EPT_CGFLT_DIV:0~255
//EPT_CGFLT_CNT:0~7
//EPT_BURST_CMD:EPT_BURST_ENABLE,EPT_BURST_DISABLE
//ReturnValue:NONE
/*************************************************************/
void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD)
{
EPT0->CR=(EPT0->CR&0xffff01ff)|EPT_BURST_CMD|EPT_CGFLT_CNT<<13|0x01<<10;
EPT0->CEDR=(EPT0->CEDR&0XFFFF00CF)|(EPT_CGFLT_DIV<<8);
if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_DIS)
{
EPT0->CEDR|=0X00<<4;
EPT0->CR|=0X03<<11;
}
else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT0OUT)
{
EPT0->CEDR|=0X01<<4;
EPT0->CR|=0X02<<11;
}
else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT1OUT)
{
EPT0->CEDR|=0X02<<4;
EPT0->CR|=0X02<<11;
}
else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHAX)
{
EPT0->CEDR|=0X00<<4;
EPT0->CR|=0X00<<11;
}
else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHBX)
{
EPT0->CEDR|=0X00<<4;
EPT0->CR|=0X01<<11;
}
}
/*************************************************************/
//Deinitializes the EPT Caputer Config
//EntryParameter:EPT_TCLK_Selecte_X,EPT_CNTMD_SELECTE_X,EPT_CAPMD_SELECTE_X,EPT_LOAD_CMPA_RST_CMD~EPT_LOAD_CMPD_RST_CMD,EPT_STOP_WRAP,EPT_PSCR
//EPT_TCLK_Selecte_X:EPT_Selecte_PCLK,EPT_Selecte_SYNCUSR3
//EPT_CNTMD_SELECTE_X:EPT_CNTMD_increase,EPT_CNTMD_decrease,EPT_CNTMD_increaseTOdecrease
//EPT_CAPMD_SELECTE_X:EPT_CAPMD_Once,EPT_CAPMD_Continue
//EPT_LOAD_CMPA_RST_CMD:EPT_LDARST_EN,EPT_LDARST_DIS
//EPT_LOAD_CMPB_RST_CMD:EPT_LDBRST_EN,EPT_LDBRST_DIS
//EPT_LOAD_CMPC_RST_CMD:EPT_LDCRST_EN,EPT_LDCRST_DIS
//EPT_LOAD_CMPD_RST_CMD:EPT_LDDRST_EN,EPT_LDDRST_DIS
//EPT_STOP_WRAP:0~3
//EPT_PSCR:0~0XFFFF
//ReturnValue:NONE
/*************************************************************/
void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD
, EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD
, EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR)
{
EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6));
if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK)
{
EPT0->PSCR=EPT_PSCR;
}
EPT0->CR=(EPT0->CR&0xf800fec0)|EPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|EPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(EPT_STOP_WRAP<<21)|
EPT_LOAD_CMPA_RST_CMD|EPT_LOAD_CMPB_RST_CMD|EPT_LOAD_CMPC_RST_CMD|EPT_LOAD_CMPD_RST_CMD;
}
/*************************************************************/
//Deinitializes the EPT SYNCR Config
//EntryParameter:EPT_Triggle_X,EPT_SYNCR_EN,EPT_SYNCUSR0_REARMTrig_Selecte,EPT_TRGSRC0_ExtSync_Selected,EPT_TRGSRC1_ExtSync_Selected
//EPT_Triggle_X:EPT_Triggle_Continue,EPT_Triggle_Once
//EPT_SYNCUSR0_REARMTrig_Selecte:EPT_SYNCUSR0_REARMTrig_DIS,EPT_SYNCUSR0_REARMTrig_T1,EPT_SYNCUSR0_REARMTrig_T2
//EPT_SYNCUSR0_REARMTrig_T1T2
//EPT_TRGSRC0_ExtSync_Selected:EPT_TRGSRC0_ExtSync_SYNCUSR0~EPT_TRGSRC0_ExtSync_SYNCUSR5
//EPT_TRGSRC1_ExtSync_Selected:EPT_TRGSRC1_ExtSync_SYNCUSR0~EPT_TRGSRC1_ExtSync_SYNCUSR5
//EPT_SYNCR_EN:0~0X3F
//ReturnValue:NONE
/*************************************************************/
void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected ,
EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->SYNCR = (EPT0->SYNCR&0XC03F0000) |EPT_SYNCR_EN|EPT_Triggle_X|EPT_SYNCUSR0_REARMTrig_Selecte|EPT_TRGSRC0_ExtSync_Selected|EPT_TRGSRC1_ExtSync_Selected;
}
/*************************************************************/
//Deinitializes the EPT CPCR Config
//EntryParameter:EPT_CPCR_CMD,EPT_CPCR_Source_X,EPT_CDUTY_X,EPT_CPCR_OSPWTH,EPT_CPCR_CDIV
//EPT_CPCR_CMD:EPT_CPCR_ENALBE,EPT_CPCR_Disable
//EPT_CPCR_Source_X:EPT_CPCR_Source_TCLK,EPT_CPCR_Source_TIN_BT0OUT,EPT_CPCR_Source_TIN_BT1OUT
//EPT_CDUTY_X:EPT_CDUTY_7_8~EPT_CDUTY_DIS
//EPT_CPCR_OSPWTH:0~0X1F
//EPT_CPCR_CDIV:0~0xf
//ReturnValue:NONE
/*************************************************************/
//Fchop=PCLK/((CDIV+1)/8) //Carrier frequency setting (CDIV>=1)
//Twidth=Tchop*OSPWTH //First pulse width setting
void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV)
{
if(EPT_CPCR_Source_X==EPT_CPCR_Source_TCLK)
{
EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x00<<14);
}
else
{
EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x01<<14);
if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT0OUT)
{
EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x01<<4);
}
if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT1OUT)
{
EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x02<<4);
}
}
}
/*************************************************************/
//Deinitializes the EPT DBCR Config
//EntryParameter:EPT_CHX_Selecte,EPT_INSEL_X,EPT_OUTSEL_X,EPT_OUT_POLARITY_X,EPT_OUT_SWAP_X
//EPT_CHX_Selecte:EPT_CHA_Selecte,EPT_CHB_Selecte,EPT_CHC_Selecte
//EPT_INSEL_X:EPT_PWMA_RISE_FALL,EPT_PWMB_RISE_PWMA_FALL,EPT_PWMA_RISE_PWMB_FALL,EPT_PWMB_RISE_FALL
//EPT_OUTSEL_X:EPT_OUTSEL_PWMA_PWMB_Bypass,EPT_OUTSEL_DisRise_EnFall,EPT_OUTSEL_EnRise_DisFall,EPT_OUTSEL_EnRise_EnFall
//EPT_OUT_POLARITY_X:EPT_PA_PB_OUT_Direct,EPT_PA_OUT_Reverse,EPT_PB_OUT_Reverse,EPT_PA_PB_OUT_Reverse
//EPT_OUT_SWAP_X:EPT_PAtoCHX_PBtoCHY,EPT_PBtoCHX_PBtoCHY,EPT_PAtoCHX_PAtoCHY,EPT_PBtoCHX_PAtoCHY
//ReturnValue:NONE
/*************************************************************/
void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X)
{
if(EPT_CHX_Selecte==EPT_CHA_Selecte)
{
EPT0->DBCR=(EPT0->DBCR&0XFFFFFF00)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<2)|(EPT_OUT_SWAP_X<<6);
}
else if(EPT_CHX_Selecte==EPT_CHB_Selecte)
{
EPT0->DBCR=(EPT0->DBCR&0XFFFF00FF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<10)|(EPT_OUT_SWAP_X<<14);
}
else if(EPT_CHX_Selecte==EPT_CHC_Selecte)
{
EPT0->DBCR=(EPT0->DBCR&0XFF00FFFF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<18)|(EPT_OUT_SWAP_X<<22);
}
EPT0->DBCR|=0x01<<24;
}
/*************************************************************/
//Deinitializes the EPT DB CLK Config
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
//Fdbclk=Fhclk/(DPSC+1)
void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF)
{
EPT0->DPSCR=DPSC;
EPT0->DBDTR=DTR;
EPT0->DBDTF=DTF;
}
/*************************************************************/
//Deinitializes the EPT PWMA~PWMD Control
//EntryParameter:EPT_PWMX_Selecte,EPT_CA_Selecte_X,EPT_CB_Selecte_X,
//EPT_PWMX_Selecte:EPT_PWMA,EPT_PWMB,EPT_PWMC,EPT_PWMD
//EPT_CA_Selecte_X:EPT_CA_Selecte_CMPA,EPT_CA_Selecte_CMPB,EPT_CA_Selecte_CMPC,EPT_CA_Selecte_CMPD
//EPT_CB_Selecte_X:EPT_CB_Selecte_CMPA,EPT_CB_Selecte_CMPB,EPT_CB_Selecte_CMPC,EPT_CB_Selecte_CMPD
//ReturnValue:NONE
/*************************************************************/
void EPT_PWMX_Output_Control(
EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X ,
EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output ,
EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output ,
EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output ,
EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output ,
EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output
)
{
if(EPT_PWMX_Selecte==EPT_PWMA)
{
EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
}
else if(EPT_PWMX_Selecte==EPT_PWMB)
{
EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
}
else if(EPT_PWMX_Selecte==EPT_PWMC)
{
EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
}
else if(EPT_PWMX_Selecte==EPT_PWMD)
{
EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
}
}
/*************************************************************/
//Deinitializes the EPT Tevent selecte
//EntryParameter:EPT_T1_Selecte,EPT_T2_Selecte
//EPT_T1_Selecte:0->SYNCUSR4,1->EP0,2->EP1,3->EP2,4->EP3,5->EP4,6->EP5,7->EP6
//EPT_T2_Selecte:0->SYNCUSR5,1->EP0,2->EP1,3->EP2,4->EP3,5->EP4,6->EP5,7->EP6
//ReturnValue:NONE
/*************************************************************/
void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte)
{
EPT0->AQTSCR=EPT_T1_Selecte|(EPT_T2_Selecte<<4);
}
/*************************************************************/
//Deinitializes the EPT PHSEN Config
//EntryParameter:EPT_PHSEN_CMD,EPT_PHSDIR,PHSR
//EPT_PHSEN_CMD:EPT_PHSEN_EN,EPT_PHSEN_DIS
//EPT_PHSDIR:EPT_PHSDIR_increase,EPT_PHSEN_decrease
//PHSR:0~0xffff
//ReturnValue:NONE
/*************************************************************/
void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR)
{
EPT0->CR=(EPT0->CR&0xffffff7f)|EPT_PHSEN_CMD;
EPT0->PHSR=PHSR|EPT_PHSDIR;
}
/*************************************************************/
//Deinitializes the EPT PRDR CMPA CMPB CMPC CMPD_Config
//EntryParameter:EPT_PRDR_Value,EPT_CMPA_Value,EPT_CMPB_Value,EPT_CMPC_Value,EPT_CMPD_Value
//EPT_PRDR_Value:0~0xff
//EPT_CMPA_Value:0~0xff
//EPT_CMPB_Value:0~0xff
//EPT_CMPC_Value:0~0xff
//EPT_CMPD_Value:0~0xff
/*************************************************************/
void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value)
{
EPT0->PRDR=EPT_PRDR_Value;
EPT0->CMPA=EPT_CMPA_Value;
EPT0->CMPB=EPT_CMPB_Value;
EPT0->CMPC=EPT_CMPC_Value;
EPT0->CMPD=EPT_CMPD_Value;
}
/*************************************************************/
//Deinitializes the EPT SYNCR Rearm
//EntryParameter:EPT_REARMX,EPT_REARM_MODE
//EPT_REARMX:EPT_REARM_SYNCEN0,EPT_REARM_SYNCEN1,EPT_REARM_SYNCEN2,EPT_REARM_SYNCEN3,EPT_REARM_SYNCEN4,EPT_REARM_SYNCEN5
//ReturnValue:NONE
/*************************************************************/
void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX )
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->SYNCR = (EPT0->SYNCR&0X3FC0FFFF)|EPT_REARMX;
}
/*************************************************************/
//Deinitializes the EPT Caputer Rearm
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
//EPT Caputer Rearm:clear counter， enable CAPLDEN automatic
void EPT_Caputure_Rearm(void)
{
EPT0->CR=(EPT0->CR&0xfffdffff)|(0x01<<19);
}
/*************************************************************/
//Deinitializes the EPT Globle Event Load
//EntryParameter:EPT_GLDMD_Selecte_X,GLDCFG_EN,EPT_GLD_OneShot_CMD,GLDPRD_CNT
//EPT_GLD_OneShot_CMD:EPT_GLD_OneShot_DIS,EPT_GLD_OneShot_EN
//EPT_GLDMD_Selecte_X:EPT_GLDMD_Selecte_ZRO,EPT_GLDMD_Selecte_PRD,EPT_GLDMD_Selecte_ZRO_PRD,EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC
//EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC,EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC,
//GLDPRD_CNT:0~7(0->Trigger immediately,1->trigger when the event happens the 2nd time,7->trigger when the event happens the 7th time)
//GLDCFG_EN:0~0x3fff
//ReturnValue:NONE
/*************************************************************/
//PRDR/CMPA/CMPB/CMPC/CMPD/DBDTR/DBCR/AQCRA/AQCRB/AQCRD/AQCSF/EMPSR load config
void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN)
{
EPT0->GLDCR=0X01|EPT_GLD_OneShot_CMD|EPT_GLDMD_Selecte_X|(GLDPRD_CNT<<7);
EPT0->GLDCFG=GLDCFG_EN;
/*if(EPT_GLDMD_Selecte_X==EPT_GLDMD_Selecte_SW)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->GLDCR2=0X02;
}*/
}
/*************************************************************/
//Deinitializes the EPT Globle SW Load
//EntryParameter:GLDCFG_EN
//GLDCFG_EN:0X0~0X3FFF
//EPT_GLDMD_Selecte_X:
/*************************************************************/
//PRDR/CMPA/CMPB/CMPC/CMPD/DBDTR/DBCR/AQCRA/AQCRB/AQCRD/AQCSF/EMPSR load config
void EPT_Globle_SwLoad_CMD(void)
{
//EPT0->GLDCR=0X01|EPT_GLDMD_Selecte_SW;
//EPT0->GLDCFG=GLDCFG_EN;
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->GLDCR2=0X03;
}
/*************************************************************/
//Deinitializes the EPT PRDR Load
//EntryParameter:EPT_PRDR_EventLoad_x
//EPT_PRDR_EventLoad_x:EPT_PRDR_EventLoad_PEND,EPT_PRDR_EventLoad_ExiLoad_SYNC,EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC,
//EPT_PRDR_EventLoad_Immediate
/*************************************************************/
void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x)
{
EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations
EPT0->CR=(EPT0->CR&0xffffffcf)|EPT_PRDR_EventLoad_x;
}
/*************************************************************/
//Deinitializes the EPT CMPX Load Config
//EntryParameter:EPT_CMPX_EventLoad_x
//EPT_CMPX_EventLoad_x:EPT_CMPX_EventLoad_DIS,EPT_CMPX_EventLoad_Immediate,EPT_CMPX_EventLoad_ZRO,
//EPT_CMPX_EventLoad_PRD,EPT_CMPX_EventLoad_ExiLoad_SYNC
/*************************************************************/
//Unified load register:CMPA,CMPB,CMPC,CMPD
void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x)
{
EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations
if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_DIS)
{
EPT0->CMPLDR=0;
}
else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_Immediate)
{
EPT0->CMPLDR=0xf;
}
else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ZRO)
{
EPT0->CMPLDR=0x2410;
}
else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_PRD)
{
EPT0->CMPLDR=0x4920;
}
else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ExiLoad_SYNC)
{
EPT0->CMPLDR=0x8240;
}
}
/*************************************************************/
//Deinitializes the EPT AQCRX Load Config
//EntryParameter:EPT_AQCRX_EventLoad_X
//EPT_AQCRX_EventLoad_X:EPT_AQCRX_EventLoad_DIS,EPT_AQCRX_EventLoad_Immediate,EPT_AQCRX_EventLoad_ZRO,
//EPT_AQCRX_EventLoad_PRD,EPT_AQCRX_EventLoad_ExiLoad_SYNC
/*************************************************************/
//Unified load register:AQCRA,AQCRB,AQCRC,AQCRD
void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X)
{
EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations
if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_DIS)
{
EPT0->AQLDR=0;
}
else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_Immediate)
{
EPT0->AQLDR=0x303;
}
else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ZRO)
{
EPT0->AQLDR=0x2424;
}
else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_PRD)
{
EPT0->AQLDR=0x4848;
}
else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ExiLoad_SYNC)
{
EPT0->AQLDR=0x9090;
}
}
/*************************************************************/
//Deinitializes the EPT DB Load Config
//EntryParameter:EPT_DB_EventLoad_X
//EPT_DB_EventLoad_X:EPT_DB_EventLoad_DIS,EPT_DB_EventLoad_Immediate,EPT_DB_EventLoad_ZRO,
//EPT_DB_EventLoad_PRD,EPT_DB_EventLoad_ZRO_PRD
/*************************************************************/
//Unified load register:DBCR,DBDTR,DBDTF,DPSCR
void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X)
{
EPT0->GLDCR&=0XFFFFFFFE; //Use independent configurations
if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_DIS)
{
EPT0->DBLDR=0X249;
}
else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_Immediate)
{
EPT0->DBLDR=0;
}
else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO)
{
EPT0->DBLDR=0X249|(0X01<<1)|(0X01<<4)|(0X01<<7)|(0X01<<10);
}
else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_PRD)
{
EPT0->DBLDR=0X249|(0X02<<1)|(0X02<<4)|(0X02<<7)|(0X02<<10);
}
else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO_PRD)
{
EPT0->DBLDR=0X249|(0X03<<1)|(0X03<<4)|(0X03<<7)|(0X03<<10);
}
}
/*************************************************************/
//EPT EVTRG Config
//EntryParameter:EPT_TRGSRCX_Select,EPT_EVTRG_TRGSRCX_X,EPT_TRGSRCX_CMD,TRGEVXPRD
//EPT_TRGSRCX_Select:EPT_TRGSRC0,EPT_TRGSRC1,EPT_TRGSRC2,EPT_TRGSRC3
//EPT_EVTRG_TRGSRCX_X:
//EPT_TRGSRCX_CMD:
//TRGEVXPRD:0~0xf
//ReturnValue: NONE
/*************************************************************/
void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD)
{
if(EPT_TRGSRCX_Select==EPT_TRGSRC0)
{
EPT0->EVTRG=(EPT0->EVTRG&0xffeffff0)|(EPT_EVTRG_TRGSRCX_X<<0)|(EPT_TRGSRCX_CMD<<20);
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC1)
{
EPT0->EVTRG=(EPT0->EVTRG&0xffdfff0f)|(EPT_EVTRG_TRGSRCX_X<<4)|(EPT_TRGSRCX_CMD<<21);
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC2)
{
EPT0->EVTRG=(EPT0->EVTRG&0xffbff0ff)|(EPT_EVTRG_TRGSRCX_X<<8)|(EPT_TRGSRCX_CMD<<22);
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC3)
{
EPT0->EVTRG=(EPT0->EVTRG&0xff7f0fff)|(EPT_EVTRG_TRGSRCX_X<<12)|(EPT_TRGSRCX_CMD<<23);
}
EPT0->EVTRG|=0x0f0f0000;
}
/*************************************************************/
//EPT EVTRG SWFTRG
//EntryParameter:EPT_TRGSRCX_Select
//EPT_TRGSRCX_Select:EPT_TRGSRC0,EPT_TRGSRC1,EPT_TRGSRC2,EPT_TRGSRC3
//ReturnValue: NONE
/*************************************************************/
void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select)
{
if(EPT_TRGSRCX_Select==EPT_TRGSRC0)
{
EPT0->EVSWF|=0X01;
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC1)
{
EPT0->EVSWF|=0X02;
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC2)
{
EPT0->EVSWF|=0X04;
}
else if(EPT_TRGSRCX_Select==EPT_TRGSRC3)
{
EPT0->EVSWF|=0X08;
}
}
/*************************************************************/
//EPT INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT)
{
EPT0->ICR = EPT_X_INT; //clear LVD INT status
EPT0->IMCR |= EPT_X_INT;
}
/*************************************************************/
//EPT INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT)
{
EPT0->IMCR &= ~EPT_X_INT;
}
/*************************************************************/
//EPT EMINT ENABLE.
//EntryParameter:EPT_X_EMINT
//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT
//ReturnValue: NONE
/*************************************************************/
void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT)
{
EPT0->EMICR = EPT_X_EMINT; //clear LVD INT status
EPT0->EMIMCR |= EPT_X_EMINT;
}
/*************************************************************/
//EPT EMINT DISABLE.
//EntryParameter:EPT_X_EMINT
//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT
//ReturnValue: NONE
/*************************************************************/
void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT)
{
EPT0->EMIMCR &= ~EPT_X_EMINT;
}
/*************************************************************/
//EPT INT VECTOR enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT_Vector_Int_Enable(void)
{
INTC_ISER_WRITE(EPT0_INT);
}
/*************************************************************/
//EPT INT VECTOR disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EPT_Vector_Int_Disable(void)
{
INTC_ICER_WRITE(EPT0_INT);
}
/*************************************************************/
//Deinitializes the EPT EP0~EP7 Config
//EntryParameter:EPT_EPX,EPT_Input_selecte_x,EPT_FLT_PACE0_x,EPT_FLT_PACE1_x,EPT_EPIX_POL
//EPT_EPX:EPT_EP0,EPT_EP1,EPT_EP2,EPT_EP3,EPT_EP4,EPT_EP5,EPT_EP6,EPT_EP7
//EPT_Input_selecte_x:EPT_Input_selecte_EPI0~EPT_Input_selecte_EPI5,EPT_Input_selecte_ORL0,EPT_Input_selecte_ORL1
//EPT_FLT_PACE0_x:EPT_FLT_PACE0_DIS~EPT_FLT_PACE0_4CLK(EP0~EP3)
//EPT_FLT_PACE1_x:EPT_FLT_PACE1_DIS~EPT_FLT_PACE1_4CLK(EP4~EP7)
//ReturnValue:NONE
/*************************************************************/
void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
if(EPT_EPX==EPT_EP0)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFFF0)|(EPT_Input_selecte_x<<0);
}
else if(EPT_EPX==EPT_EP1)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFF0F)|(EPT_Input_selecte_x<<4);
}
else if(EPT_EPX==EPT_EP2)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFFFFF0FF)|(EPT_Input_selecte_x<<8);
}
else if(EPT_EPX==EPT_EP3)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFFFF0FFF)|(EPT_Input_selecte_x<<12);
}
else if(EPT_EPX==EPT_EP4)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFFF0FFFF)|(EPT_Input_selecte_x<<16);
}
else if(EPT_EPX==EPT_EP5)
{
EPT0->EMSRC=(EPT0->EMSRC&0XFF0FFFFF)|(EPT_Input_selecte_x<<20);
}
else if(EPT_EPX==EPT_EP6)
{
EPT0->EMSRC=(EPT0->EMSRC&0XF0FFFFFF)|(EPT_Input_selecte_x<<24);
}
else if(EPT_EPX==EPT_EP7)
{
EPT0->EMSRC=(EPT0->EMSRC&0X0FFFFFFF)|(EPT_Input_selecte_x<<28);
}
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->EMSRC2=ORL0_EPIx|(ORL1_EPIx<<16)|EPT_FLT_PACE0_x|EPT_FLT_PACE1_x;
}
/*************************************************************/
//Deinitializes EPT_EPIX POL Config
//EntryParameter:EPT_EPIX_POL
//EPT_EPIX_POL:BIT0->EPI0(0:Active high 1:Active low),BIT1->EPI1(0:Active high 1:Active low),
//BIT2->EPI2(0:Active high 1:Active low),BIT3->EPI3(0:Active high 1:Active low),BIT4->EPI4(0:Active high 1:Active low)
//ReturnValue:NONE
/*************************************************************/
void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->EMPOL=EPT_EPIX_POL;
}
/*************************************************************/
//EPT EM Config
//EntryParameter:EPT_LKCR_TRG_X,EPT_LKCR_Mode_X
//EPT_LKCR_TRG_X:EPT_LKCR_TRG_EP0~EPT_LKCR_TRG_EP7,EPT_LKCR_TRG_CPU_FAULT,EPT_LKCR_TRG_MEM_FAULT,EPT_LKCR_TRG_EOM_FAULT
//EPT_LKCR_Mode_X:EPT_LKCR_Mode_LOCK_DIS,EPT_LKCR_Mode_SLOCK_EN,EPT_LKCR_Mode_HLOCK_EN,EPT_LKCR_TRG_X_FAULT_HLOCK_EN,EPT_LKCR_TRG_X_FAULT_HLOCK_DIS
//ReturnValue:NONE
/*************************************************************/
void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->EMECR|=(0X01<<21)|(0X01<<22)|(0X02<<24); //EMOSR CNT=ZRO load，Automatically clear soft lock when CNT=ZRO&PRD
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_CPU_FAULT)
{
if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
{
EPT0->EMECR|=(0x01<<28);
}
else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
{
EPT0->EMECR&=~(0x01<<28);
}
}
else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_MEM_FAULT)
{
if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
{
EPT0->EMECR|=(0x01<<29);
}
else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
{
EPT0->EMECR&=~(0x01<<29);
}
}
else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_EOM_FAULT)
{
if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
{
EPT0->EMECR|=(0x01<<30);
}
else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
{
EPT0->EMECR&=~(0x01<<30);
}
}
else
{
EPT0->EMECR|=(EPT_LKCR_Mode_X<<(EPT_LKCR_TRG_X))|(0X01<<26);
}
}
/*************************************************************/
//EPT EM Config
//EntryParameter:EPT_OUTPUT_Channel_X,EPT_SHLOCK_OUTPUT_X
//EPT_OUTPUT_Channel_X:EPT_OUTPUT_Channel_CHAX,EPT_OUTPUT_Channel_CHAY,EPT_OUTPUT_Channel_CHBX,EPT_OUTPUT_Channel_CHBY
//EPT_OUTPUT_Channel_CHCX,EPT_OUTPUT_Channel_CHCY,EPT_OUTPUT_Channel_CHD
//EPT_SHLOCK_OUTPUT_X:EPT_SHLOCK_OUTPUT_HImpedance,EPT_SHLOCK_OUTPUT_High,EPT_SHLOCK_OUTPUT_Low,EPT_SHLOCK_OUTPUT_Nochange
//ReturnValue:NONE
/*************************************************************/
void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->EMOSR|=EPT_SHLOCK_OUTPUT_X<<EPT_OUTPUT_Channel_X;
}
/*************************************************************/
//EPT software lock clr
//EntryParameter:EPT_X_EMINT
//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT
//ReturnValue:NONE
/*************************************************************/
void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT)
{
EPT0->EMSLCLR|=EPT_X_EMINT;
}
/*************************************************************/
//EPT H lock clr
//EntryParameter:EPT_X_EMINT
//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT
//ReturnValue:NONE
/*************************************************************/
void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT)
{
EPT0->EMHLCLR|=EPT_X_EMINT;
}
/*************************************************************/
//EPT software lock SET
//EntryParameter:EPT_X_EMINT
//EPT_X_EMINT:EPT_EP0_EMINT~EPT_EP7_EMINT,EPT_CPU_FAULT_EMINT,EPT_MEM_FAULT_EMINT,EPT_EOM_FAULT_EMINT
//ReturnValue:NONE
/*************************************************************/
void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT)
{
EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
EPT0->EMFRCR|=EPT_X_EMINT;
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

274
Source/FWlib/apt32f102_et.c Normal file
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@@ -0,0 +1,274 @@
/*
******************************************************************************
* @file apt32f102_et.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_et.h"
/*************************************************************/
//ET RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ET_DeInit(void)
{
ETCB->EN = ET_RESET_VALUE;
ETCB->SWTRG = ET_RESET_VALUE;
ETCB->CH0CON0 = ET_RESET_VALUE;
ETCB->CH0CON1 = ET_RESET_VALUE;
ETCB->CH1CON0 = ET_RESET_VALUE;
ETCB->CH1CON1 = ET_RESET_VALUE;
ETCB->CH2CON0 = ET_RESET_VALUE;
ETCB->CH2CON1 = ET_RESET_VALUE;
ETCB->CH3CON = ET_RESET_VALUE;
ETCB->CH4CON = ET_RESET_VALUE;
ETCB->CH5CON = ET_RESET_VALUE;
ETCB->CH6CON = ET_RESET_VALUE;
ETCB->CH7CON = ET_RESET_VALUE;
}
/*************************************************************/
//ET ENABLE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ET_ENABLE(void)
{
ETCB->EN = 0x01;
}
/*************************************************************/
//ET DISABLE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void ET_DISABLE(void)
{
ETCB->EN = 0x00;
}
/*************************************************************/
//ET SWTRG Configure
//EntryParameter:ETSWTRG_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_SWTRG_CMD(CRC_ETSWTRG_TypeDef ETSWTRG_X,FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
ETCB->SWTRG |= ETSWTRG_X;
}
else
{
ETCB->SWTRG &= ~ETSWTRG_X;
}
}
/*************************************************************/
//ET CH0 source selection Configure
//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH0_SRCSEL(CRC_ESRCSEL_TypeDef ESRCSEL_X,FunctionalStatus NewState,U8_T SRCSEL_X)
{
if (NewState != DISABLE)
{
if(ESRCSEL_X==0)
{
ETCB->CH0CON0 |= 0X01| (SRCSEL_X<<1);
}
if(ESRCSEL_X==1)
{
ETCB->CH0CON0 |= (0X01<<10)| (SRCSEL_X<<11);
}
if(ESRCSEL_X==2)
{
ETCB->CH0CON0 |= (0X01<<20)| (SRCSEL_X<<21);
}
}
else
{
if(ESRCSEL_X==0)
{
ETCB->CH0CON0 &= 0X01| (SRCSEL_X<<1);
}
if(ESRCSEL_X==1)
{
ETCB->CH0CON0 &= (0X00<<10)| (SRCSEL_X<<11);
}
if(ESRCSEL_X==2)
{
ETCB->CH0CON0 &= (0X00<<20)| (SRCSEL_X<<21);
}
}
}
/*************************************************************/
//ET CHO CONTROL Configure
//EntryParameter:NewState,TRIGMODEX,DSTSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH0_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
ETCB->CH0CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX;
}
else
{
ETCB->CH0CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX;
}
}
/*************************************************************/
//ET CHI1 source selection Configure
//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH1_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
if(DST_X==0)
{
ETCB->CH1CON0 |= 0X01| (DSTSEL_X<<1);
}
if(DST_X==1)
{
ETCB->CH1CON0 |= (0X01<<10)| (DSTSEL_X<<11);
}
if(DST_X==2)
{
ETCB->CH1CON0 |= (0X01<<20)| (DSTSEL_X<<21);
}
}
else
{
if(DST_X==0)
{
ETCB->CH1CON0 &= 0X01| (DSTSEL_X<<1);
}
if(DST_X==1)
{
ETCB->CH1CON0 &= (0X00<<10)| (DSTSEL_X<<11);
}
if(DST_X==2)
{
ETCB->CH1CON0 &= (0X00<<20)| (DSTSEL_X<<21);
}
}
}
/*************************************************************/
//ET CH1 CONTROL Configure
//EntryParameter:NewState,TRIGMODEX,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH1_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
ETCB->CH1CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX;
}
else
{
ETCB->CH1CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX;
}
}
/*************************************************************/
//ET CHI2 source selection Configure
//EntryParameter:ETSWTRG_X,NewState,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH2_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
if(DST_X==0)
{
ETCB->CH2CON0 |= 0X01| (DSTSEL_X<<1);
}
if(DST_X==1)
{
ETCB->CH2CON0 |= (0X01<<10)| (DSTSEL_X<<11);
}
if(DST_X==2)
{
ETCB->CH2CON0 |= (0X01<<20)| (DSTSEL_X<<21);
}
}
else
{
if(DST_X==0)
{
ETCB->CH2CON0 &= 0X01| (DSTSEL_X<<1);
}
if(DST_X==1)
{
ETCB->CH2CON0 &= (0X00<<10)| (DSTSEL_X<<11);
}
if(DST_X==2)
{
ETCB->CH2CON0 &= (0X00<<20)| (DSTSEL_X<<21);
}
}
}
/*************************************************************/
//ET CH2 CONTROL Configure
//EntryParameter:NewState,TRIGMODEX,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CH2_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
ETCB->CH2CON1 |= 0x01| (DSTSEL_X<<26)| TRIGMODEX;
}
else
{
ETCB->CH2CON1 &= 0x00| (DSTSEL_X<<26)| TRIGMODEX;
}
}
/*************************************************************/
//ET CH3~7 source selection/CONTROL Configure
//EntryParameter:NewState,TRIGMODEX,SRCSEL_X
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void ET_CHx_CONTROL(CRC_ETCHX_TypeDef ETCHX,FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T SRCSEL_X,U8_T DSTSEL_X)
{
if (NewState != DISABLE)
{
if(ETCHX==0)ETCB->CH3CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==1)ETCB->CH4CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==2)ETCB->CH5CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==3)ETCB->CH6CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==4)ETCB->CH7CON |= 0x01|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
}
else
{
if(ETCHX==0)ETCB->CH3CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==1)ETCB->CH4CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==2)ETCB->CH5CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==3)ETCB->CH6CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
if(ETCHX==4)ETCB->CH7CON &= 0x00|(SRCSEL_X<<12)| (DSTSEL_X<<26)| TRIGMODEX;
}
}

508
Source/FWlib/apt32f102_gpio.c Normal file
View File

@@ -0,0 +1,508 @@
/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_gpio.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//IO RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_DeInit(void)
{
GPIOA0->CONLR &= 0xFF000000;
GPIOA0->CONHR = GPIO_RESET_VALUE;
GPIOB0->CONLR = GPIO_RESET_VALUE;
GPIOB0->CONHR = GPIO_RESET_VALUE;
GPIOA0->WODR = GPIO_RESET_VALUE;
GPIOB0->WODR = GPIO_RESET_VALUE;
GPIOA0->SODR = GPIO_RESET_VALUE;
GPIOB0->SODR = GPIO_RESET_VALUE;
GPIOA0->CODR = GPIO_RESET_VALUE;
GPIOB0->CODR = GPIO_RESET_VALUE;
GPIOA0->ODSR = GPIO_RESET_VALUE;
GPIOB0->ODSR = GPIO_RESET_VALUE;
GPIOA0->PSDR = GPIO_RESET_VALUE;
GPIOB0->PSDR = GPIO_RESET_VALUE;
GPIOA0->FLTEN = 0xffff;
GPIOB0->FLTEN = 0x3f;
GPIOA0->PUDR = GPIO_RESET_VALUE;
GPIOB0->PUDR = GPIO_RESET_VALUE;
GPIOA0->DSCR = GPIO_RESET_VALUE;
GPIOB0->DSCR = GPIO_RESET_VALUE;
GPIOA0->OMCR = GPIO_RESET_VALUE;
GPIOB0->OMCR = GPIO_RESET_VALUE;
GPIOA0->IECR = GPIO_RESET_VALUE;
GPIOB0->IECR = GPIO_RESET_VALUE;
GPIOGRP->IGRPL = GPIO_RESET_VALUE;
GPIOGRP->IGRPH = GPIO_RESET_VALUE;
GPIOGRP->IGREX = GPIO_RESET_VALUE;
GPIOGRP->IO_CLKEN = 0xf;
}
/*************************************************************/
//IO OUTPUT INPUT SET 2
//EntryParameter:GPIOx,byte,val
//GPIOx:GPIOA0,GPIOB0
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//val:0x0000000~0xFFFFFFFF
//val=0x11111111 all IO as input
//val=0x22222222 all IO as output
//ReturnValue:NONE
/*************************************************************/
void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val)
{
if (byte==0)
{
(GPIOx)->CONLR=val;
}
else if(byte==1)
{
(GPIOx)->CONHR=val;
}
}
/*************************************************************/
//IO OUTPUT INPUT SET 1
//EntryParameter:GPIOx,GPIO_Pin(0~15),byte,Dir
//GPIOx:GPIOA0,GPIOB0
//GPIO_Pin:PIN_0~15
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//Dir:0:output 1:input
//ReturnValue:NONE
/*************************************************************/
void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir)
{
uint32_t data_temp;
uint8_t GPIO_Pin;
if(PinNum<8)
{
switch (PinNum)
{
case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
case 1:data_temp=0xffffff0f;GPIO_Pin=4;break;
case 2:data_temp=0xfffff0ff;GPIO_Pin=8;break;
case 3:data_temp=0xffff0fff;GPIO_Pin=12;break;
case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
}
if (Dir)
{
(GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
}
else
{
(GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin;
}
}
else if (PinNum<16)
{
switch (PinNum)
{
case 8:data_temp=0xfffffff0;GPIO_Pin=0;break;
case 9:data_temp=0xffffff0f;GPIO_Pin=4;break;
case 10:data_temp=0xfffff0ff;GPIO_Pin=8;break;
case 11:data_temp=0xffff0fff;GPIO_Pin=12;break;
case 12:data_temp=0xfff0ffff;GPIO_Pin=16;break;
case 13:data_temp=0xff0fffff;GPIO_Pin=20;break;
case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
case 15:data_temp=0x0fffffff;GPIO_Pin=28;break;
}
if (Dir)
{
(GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;
}
else
{
(GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;
}
}
}
/*************************************************************/
//IO OUTPUT INPUT Disable
//EntryParameter:GPIOx,GPIO_Pin(0~15)
//GPIOx:GPIOA0,GPIOB0
//GPIO_Pin:PIN_0~15
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//ReturnValue:NONE
/*************************************************************/
void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum)
{
uint32_t data_temp;
if(PinNum<8)
{
switch (PinNum)
{
case 0:data_temp=0xfffffff0;break;
case 1:data_temp=0xffffff0f;break;
case 2:data_temp=0xfffff0ff;break;
case 3:data_temp=0xffff0fff;break;
case 4:data_temp=0xfff0ffff;break;
case 5:data_temp=0xff0fffff;break;
case 6:data_temp=0xf0ffffff;break;
case 7:data_temp=0x0fffffff;break;
}
(GPIOx)->CONLR = (GPIOx)->CONLR & data_temp;
}
else if (PinNum<16)
{
switch (PinNum)
{
case 8:data_temp=0xfffffff0;break;
case 9:data_temp=0xffffff0f;break;
case 10:data_temp=0xfffff0ff;break;
case 11:data_temp=0xffff0fff;break;
case 12:data_temp=0xfff0ffff;break;
case 13:data_temp=0xff0fffff;break;
case 14:data_temp=0xf0ffffff;break;
case 15:data_temp=0x0fffffff;break;
}
(GPIOx)->CONHR = (GPIOx)->CONHR & data_temp;
}
}
/*************************************************************/
//IO OUTPUT INPUT SET
//EntryParameter:IO_MODE,GPIOx,val
//GPIOx:GPIOA0,GPIOB0
//IO_MODE:PUDR(IO PULL HIGH/LOW)
//IO_MODE:DSCR(IO DRIVE STRENGHT)
//IO_MODE:OMCR(OUTPUT MODE SET)
//IO_MODE:IECR(IO INT ENABLE)
//ReturnValue:NONE
/*************************************************************/
void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val)
{
switch (IO_MODE)
{
case PUDR:(GPIOx)->PUDR = val;break;
case DSCR:(GPIOx)->DSCR = val;break;
case OMCR:(GPIOx)->OMCR = val;break;
case IECR:(GPIOx)->IECR = val;break;
}
}
/*************************************************************/
//Write GPIO pull high/low
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x01<<(bit*2));
}
void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x02<<(bit*2));
}
void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->PUDR = ((GPIOx)->PUDR) & ~(0x03<<(bit*2));
}
/*************************************************************/
//Write GPIO open drain init
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<<bit);
}
void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) & ~(0x01<<bit);
}
/*************************************************************/
//Write GPIO open drain init
//EntryParameter:GPIOx,uint8_t bit,INPUT_MODE_SETECTED_X
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//INPUT_MODE_SETECTED_X:INPUT_MODE_TTL1,INPUT_MODE_SETECTED_TTL2,INPUT_MODE_SETECTED_CMOSS
//ReturnValue:VALUE
/*************************************************************/
//默认cmos口
void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X)
{
if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_CMOS)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2+1));
}
else
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2+1));
if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL1)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) | (0x01<<(bit+16));
}
else if(INPUT_MODE_SETECTED_X==INPUT_MODE_SETECTED_TTL2)
{
(GPIOx)->OMCR = ((GPIOx)->OMCR) & ~(0x01<<(bit+16));
}
}
}
/*************************************************************/
//Write GPIO Drive Strength init
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) | (0x01<<(bit*2));
}
void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->DSCR = ((GPIOx)->DSCR) & ~(0x01<<(bit*2));
}
/*************************************************************/
//IO OUTPUT INPUT SET
//EntryParameter:
//IO_MODE:IGRP(IO INT GROUP)
//PinNum：0~15
//SYSCON_EXIPIN_TypeDef:EXI_PIN0~EXI_PIN19
//EXI0~EXI15:GPIOA0,GPIOB0
//EXI16~EXI17:GPIOA0.0~GPIOA0.7
//EXI18~EXI19:GPIOB0.0~GPIOB0.3
//ReturnValue:NONE
/*************************************************************/
void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef Selete_EXI_x)
{
volatile unsigned int R_data_temp;
volatile unsigned char R_GPIO_Pin;
if(Selete_EXI_x<16)
{
if((Selete_EXI_x==0)||(Selete_EXI_x==8))
{
R_data_temp=0xfffffff0;
R_GPIO_Pin=0;
}
else if((Selete_EXI_x==1)||(Selete_EXI_x==9))
{
R_data_temp=0xffffff0f;
R_GPIO_Pin=4;
}
else if((Selete_EXI_x==2)||(Selete_EXI_x==10))
{
R_data_temp=0xfffff0ff;
R_GPIO_Pin=8;
}
else if((Selete_EXI_x==3)||(Selete_EXI_x==11))
{
R_data_temp=0xffff0fff;
R_GPIO_Pin=12;
}
else if((Selete_EXI_x==4)||(Selete_EXI_x==12))
{
R_data_temp=0xfff0ffff;
R_GPIO_Pin=16;
}
else if((Selete_EXI_x==5)||(Selete_EXI_x==13))
{
R_data_temp=0xff0fffff;
R_GPIO_Pin=20;
}
else if((Selete_EXI_x==6)||(Selete_EXI_x==14))
{
R_data_temp=0xf0ffffff;
R_GPIO_Pin=24;
}
else if((Selete_EXI_x==7)||(Selete_EXI_x==15))
{
R_data_temp=0x0fffffff;
R_GPIO_Pin=28;
}
if(Selete_EXI_x<8)
{
GPIOGRP->IGRPL =(GPIOGRP->IGRPL & R_data_temp) | (IO_MODE<<R_GPIO_Pin);
}
else if((Selete_EXI_x<16)&&(Selete_EXI_x>=8))
{
GPIOGRP->IGRPH =(GPIOGRP->IGRPH & R_data_temp) | (IO_MODE<<R_GPIO_Pin);
}
}
else if(Selete_EXI_x<20)
{
if((IO_MODE==0)&&((Selete_EXI_x==16)||((Selete_EXI_x==17)))) //PA0.0~PA0.7
{
if(Selete_EXI_x==16)
{
GPIOGRP->IGREX =(GPIOGRP->IGREX)|PinNum;
}
else if(Selete_EXI_x==17)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<4);
}
}
else if((IO_MODE==2)&&((Selete_EXI_x==18)||(Selete_EXI_x==19))) //PB0.0~PB0.3
{
if(Selete_EXI_x==18)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<8);
}
else if(Selete_EXI_x==19)
{
GPIOGRP->IGREX=(GPIOGRP->IGREX)|(PinNum<<12);
}
}
}
}
/*************************************************************/
//IO EXI SET
//EntryParameter:EXI_IO(EXI0~EXI13)
//ReturnValue:NONE
/*************************************************************/
void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
switch (EXI_IO)
{
case 0:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
case 2:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
case 3:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
case 4:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
case 5:GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
case 7:GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0X10000000;break;
case 8:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000001;break;
case 9:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0X00000010;break;
case 10:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0X00000100;break;
case 11:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0X00001000;break;
case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X01000000;break;
case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0X10000000;break;
}
}
void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
switch (EXI_IO)
{
case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
case 2:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0X00000100;break;
case 3:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF) | 0X00001000;break;
case 4:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0X00010000;break;
case 5:GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0X00100000;break;
default:break;
}
}
void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
(GPIOx)->IECR |= 1<<EXI_IO;
}
/*************************************************************/
//Write GPIO
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->SODR = (1ul<<bit);
}
void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit)
{
(GPIOx)->CODR = (1ul<<bit);
}
/*************************************************************/
//Write GPIO
//EntryParameter:GPIOx,uint8_t bitposi bitval
//GPIOx:GPIOA0,GPIOB0
//bitposi:0~15 bitval:0~1 0=low 1=high
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval)
{
if (bitval==1)
{
(GPIOx)->SODR = (1ul<<bitposi);
}
else if ((bitval==0))
{
(GPIOx)->CODR = (1ul<<bitposi);
}
}
/*************************************************************/
//Write GPIO reverse
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint32_t dat = 0;
dat=((GPIOx)->ODSR>>bit)&1ul;
{
if (dat==1)
{
(GPIOx)->CODR = (1ul<<bit);
return;
}
if (dat==0)
{
(GPIOx)->SODR = (1ul<<bit);
return;
}
}
}
/*************************************************************/
//READ PA IO STATUS
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=((GPIOx)->PSDR)&(1<<bit);
if (dat == (1<<bit))
{
value = 1;
}
return value;
}
/*************************************************************/
//READ PA OUTPUT STATUS
//EntryParameter:GPIOx,uint8_t bit
//GPIOx:GPIOA0,GPIOB0
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=((GPIOx)->ODSR)&(1<<bit);
if (dat == (1<<bit))
{
value = 1;
}
return value;
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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Source/FWlib/apt32f102_gpt.c Normal file
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/*
******************************************************************************
* @file apt32f102_gpt.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_gpt.h"
/*************************************************************/
//GPT RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_DeInit(void)
{
GPT0->CEDR = 0xBE980000;
GPT0->RSSR = GPT_RESET_VALUE;
GPT0->PSCR = GPT_RESET_VALUE;
GPT0->CR = 0X00010010;
GPT0->SYNCR = GPT_RESET_VALUE;
GPT0->GLDCR = GPT_RESET_VALUE;
GPT0->GLDCFG = GPT_RESET_VALUE;
GPT0->GLDCR2 = GPT_RESET_VALUE;
GPT0->PRDR = GPT_RESET_VALUE;
GPT0->CMPA = GPT_RESET_VALUE;
GPT0->CMPB = GPT_RESET_VALUE;
GPT0->CMPLDR = 0X00002490;
GPT0->CNT = GPT_RESET_VALUE;
GPT0->AQLDR = 0X00000024;
GPT0->AQCRA = GPT_RESET_VALUE;
GPT0->AQCRB = GPT_RESET_VALUE;
GPT0->AQOSF = 0X00000100;
GPT0->AQCSF = GPT_RESET_VALUE;
GPT0->TRGFTCR = GPT_RESET_VALUE;
GPT0->TRGFTWR = GPT_RESET_VALUE;
GPT0->EVTRG = GPT_RESET_VALUE;
GPT0->EVPS = GPT_RESET_VALUE;
GPT0->EVCNTINIT = GPT_RESET_VALUE;
GPT0->EVSWF = GPT_RESET_VALUE;
GPT0->RISR = GPT_RESET_VALUE;
GPT0->MISR = GPT_RESET_VALUE;
GPT0->IMCR = GPT_RESET_VALUE;
GPT0->ICR = GPT_RESET_VALUE;
GPT0->REGLINK = GPT_RESET_VALUE;
}
/*************************************************************/
//GPT IO Init
//EntryParameter:GPT_CHA_PB01,GPT_CHA_PA09,GPT_CHA_PA010,GPT_CHB_PA010,GPT_CHB_PA011,GPT_CHB_PB00,GPT_CHB_PB01
//ReturnValue:NONE
/*************************************************************/
void GPT_IO_Init(GPT_IOSET_TypeDef IONAME)
{
if(IONAME==GPT_CHA_PB01)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;
}
if(IONAME==GPT_CHA_PA09)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000050;
}
if(IONAME==GPT_CHA_PA010)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000600;
}
if(IONAME==GPT_CHB_PA010)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000700;
}
if(IONAME==GPT_CHB_PA011)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00006000;
}
if(IONAME==GPT_CHB_PB00)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000004;
}
if(IONAME==GPT_CHB_PB01)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000060;
}
}
/*************************************************************/
//GPT Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX)
{
GPT0->CEDR = GPTCLKX| GCSSX|GSHDWSTPX;
GPT0->PSCR=GPSCX;
}
/*************************************************************/
//GPT Wave control Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
//GPT0->CR = (0X0<<0)|(0x00<<2)|(0x01<<3)|(0x00<<4)|(0X00<<6)|(0x01<<18)|(0x00<<9)|(0X00<<10)|(0x00<<11)|(0x00<<13) ;
//GPT0->CMPLDR=(0X00<<0)|(0X00<<1)|(0X03<<4)|(0X03<<7);
void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX)
{
GPT0->CR =GCNTMDX|GSWSYNX|GIDLEX|GPRDLD0|GOPMX|GBURSTX|GCKS|CGSRCX|CGFLT|PSCLDX|GPT_WAVE_MODE;
}
/*************************************************************/
//GPT Wave control Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX)
{
GPT0->AQLDR=SHDWAQAX|SHDWAQBX|AQLDAX|AQLDBX;
}
/*************************************************************/
//GPT Wave A OUT Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX)
{
if(GPTCHX==GPT_CHA)
{
GPT0->AQCRA=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18);
}
if(GPTCHX==GPT_CHB)
{
GPT0->AQCRB=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18);
}
}
/*************************************************************/
//Deinitializes the GPT Caputer Config
//EntryParameter:GPT_CNTMD_SELECTE_X,GPT_CAPMD_SELECTE_X,GPT_LOAD_CMPA_RST_CMD~GPT_LOAD_CMPB_RST_CMD,GPT_STOP_WRAP,GPT_PSCR
//GPT_CNTMD_SELECTE_X:GPT_CNTMD_increase,GPT_CNTMD_decrease,GPT_CNTMD_increaseTOdecrease
//GPT_CAPMD_SELECTE_X:GPT_CAPMD_Once,GPT_CAPMD_Continue
//GPT_LOAD_CMPA_RST_CMD:GPT_LDARST_EN,GPT_LDARST_DIS
//GPT_LOAD_CMPB_RST_CMD:GPT_LDBRST_EN,GPT_LDBRST_DIS
//GPT_STOP_WRAP:0~3
//GPT_PSCR:0~0XFFFF
//ReturnValue:NONE
/*************************************************************/
void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
, GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP )
{
GPT0->CR=(GPT0->CR&0xf800fec0)|GPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|GPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(GPT_STOP_WRAP<<21)|
GPT_LOAD_CMPA_RST_CMD|GPT_LOAD_CMPB_RST_CMD|GPT_LOAD_CMPC_RST_CMD|GPT_LOAD_CMPD_RST_CMD;
}
/*************************************************************/
//GPT SYNC Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx)
{
GPT0->SYNCR |= SYNCENx| OSTMDx| TXREARM0x |TRGO0SELx|TRGO1SELx|AREARMx;
}
/*************************************************************/
//GPT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA)
{
GPT0->TRGFTCR |= SRCSELx| BLKINVx|ALIGNMDx| CROSSMDx;
GPT0->TRGFTWR |= G_OFFSET_DATA |(G_WINDOW_DATA<<16);
}
/*************************************************************/
//GPT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt)
{
GPT0->EVTRG |= TRGSRC0x |TRGSRC1x|ESYN0OEx|ESYN1OEx|CNT0INITx|CNT1INITx;
GPT0->EVPS |= TRGEV0prd|(TRGEV1prd<<4)|(TRGEV0cnt<<16)|(TRGEV1cnt<<20);
}
/*************************************************************/
//GPT OneceForce Out
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX)
{
GPT0->AQOSF =CHAFORCEX|CHBFORCEX|FORCELDX|(AFORCE_STATUS<<1)|(BFORCE_STATUS<<5);
}
/*************************************************************/
//GPT Continue Force Out
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX)
{
GPT0->AQCSF =FORCEAX|FORCEBX;
}
/*************************************************************/
//GPT Wave Compare Load Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX)
{
GPT0->CMPLDR=SHDWCMPAX|SHDWCMPBX|LDAMDX|LDBMDX;
}
/*************************************************************/
//GPT DEBUG MODE
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_Debug_Mode(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
GPT0->CEDR |= GPT_DEBUG_MODE;
}
else
{
GPT0->CEDR &= ~GPT_DEBUG_MODE;
}
}
/*************************************************************/
// GPT start
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_Start(void)
{
GPT0->RSSR |= 0X01;
}
/*************************************************************/
// GPT stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_Stop(void)
{
GPT0->RSSR &= 0XFFFFFFFE;
}
/*************************************************************/
// GPT soft reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_Soft_Reset(void)
{
GPT0->RSSR |= (0X5<<12);
}
/*************************************************************/
// GPT Capture rearm
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_Cap_Rearm(void)
{
GPT0->CR |= (0X01<<19);
}
/*************************************************************/
// GPT MODE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_Mode_CMD(GPT_WAVE_TypeDef WAVEX)
{
GPT0->CR |= WAVEX;
}
/*************************************************************/
// GPT soft reset at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_REARM_Write(void)
{
GPT0->SYNCR |= (0X1<<16);
}
/*************************************************************/
// GPT soft read at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T GPT_REARM_Read(void)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=(GPT0->SYNCR)&(1<<16);
if (dat)
{
value = 1;
}
return value;
}
/*************************************************************/
//GPT Period / Compare set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA)
{
GPT0->PRDR =PRDR_DATA;
GPT0->CMPA =CMPA_DATA;
GPT0->CMPB =CMPB_DATA;
}
/*************************************************************/
//GPT read counters
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
U16_T GPT_PRDR_Read(void)
{
return GPT0->PRDR;
}
U16_T GPT_CMPA_Read(void)
{
return GPT0->CMPA;
}
U16_T GPT_CMPB_Read(void)
{
return GPT0->CMPB;
}
U16_T GPT_CNT_Read(void)
{
return GPT0->CNT;
}
/*************************************************************/
//GPT inturrpt Configure
//EntryParameter:LPT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X)
{
if (NewState != DISABLE)
{
GPT0->IMCR |= GPT_IMSCR_X;
}
else
{
GPT0->IMCR &= ~GPT_IMSCR_X;
}
}
/*************************************************************/
//GPT Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_INT_ENABLE(void)
{
INTC_ISER_WRITE(GPT0_INT);
}
/*************************************************************/
//LPT Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPT_INT_DISABLE(void)
{
INTC_ICER_WRITE(GPT0_INT);
}

89
Source/FWlib/apt32f102_hwdiv.c Normal file
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/*
******************************************************************************
* @file apt32f102_gpio.c
* @author APT AE Team
* @version V1.24
* @date 2018/10/15
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_hwdiv.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//HWDIV RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_DeInit(void)
{
HWD->DIVIDENT = HWDIV_RESET_VALUE;
HWD->DIVISOR = HWDIV_RESET_VALUE;
HWD->QUOTIENT = HWDIV_RESET_VALUE;
HWD->REMAIN = HWDIV_RESET_VALUE;
HWD->CR = HWDIV_RESET_VALUE;
}
/*************************************************************/
//HWDIV UNSIGN Configure
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_UNSIGN_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
HWD->CR |= HWDIV_UNSIGN_BIT;
}
else
{
HWD->CR &= ~HWDIV_UNSIGN_BIT;
}
}
/*************************************************************/
//HWDIV Calculate
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x)
{
HWD->DIVIDENT=DIVIDENDx;
HWD->DIVISOR=DIVISOR_x;
}
/*************************************************************/
//HWDIV Calculate result
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
U32_T HWDIV_Calc_Quotient(void)
{
return HWD->QUOTIENT;
}
/*************************************************************/
//HWDIV Calculate result
//EntryParameter:NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
U32_T HWDIV_Calc_Remain(void)
{
return HWD->REMAIN;
}
/*************************************************************/
void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x)
{
HWD->DIVIDENT=DIVIDENDx;
HWD->DIVISOR=DIVISOR_x;
}

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Source/FWlib/apt32f102_i2c.c Normal file
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/*
******************************************************************************
* @file apt32f102_i2c.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#include "apt32f102_i2c.h"
volatile uint8_t I2CWrBuffer[BUFSIZE];
volatile uint8_t I2CRdBuffer[BUFSIZE];
volatile uint8_t RdIndex = 0;
volatile uint8_t WrIndex = 0;
volatile uint8_t I2C_Data_Adress;
volatile uint8_t I2C_St_Adress;
volatile U8_T f_ERROR=0;
volatile U32_T R_IIC_ERROR_CONT;
extern void delay_nms(unsigned int t);
/*************************************************************/
//I2C RESET,CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_DeInit(void)
{
I2C0->ENABLE = 0;
I2C0->IMSCR = 0;
I2C0->ICR = 0X7FFF;
}
/*************************************************************/
//I2C MASTER Initial
//EntryParameter:SPEEDMODE,MASTERBITS,
//SPEEDMODE:FAST_MODE(>100K),STANDARD_MODE(<100K)
//MASTERBITS:I2C_MASTRER_7BIT/I2C_MASTRER_10BIT
//ReturnValue:NONE
/*************************************************************/
void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX)
{
//SDA IO Initial
if(I2C_SDA_IO==I2C_SDA_PA00)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005; //PA0.0->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA03)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000; //PA0.3->SDA
}
else if (I2C_SDA_IO==I2C_SDA_PA07)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000; //PA0.7->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA013)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000; //PA0.13->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA014)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000; //PA0.14->SDA
}
//SCL IO Initial
if (I2C_SCL_IO==I2C_SCL_PB00)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006; //PB0.0->SCL
}
else if (I2C_SCL_IO==I2C_SCL_PB02)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400; //PB0.2->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA01)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050; //PA0.1->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA04)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000; //PA0.4->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA06)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000; //PA0.6->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA015)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000; //PA0.15->SCL
}
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE;
I2C0->CR =(I2C0->CR&0XFFFFF000)|I2C_MASTER_EN |I2C_SLAVE_DIS| SPEEDMODE | MASTERBITS | I2C_RESTART_EN; //Repeat start bit enable
I2C0->TADDR =I2C_MASTER_ADDS;
if(SPEEDMODE==FAST_MODE)
{
I2C0->FS_SCLH = SS_SCLHX; //SCL high time
I2C0->FS_SCLL = SS_SCLLX; //SCL low time
}
else if(SPEEDMODE==STANDARD_MODE)
{
I2C0->SS_SCLH = SS_SCLHX; //SCL high time
I2C0->SS_SCLL = SS_SCLLX; //SCL low time
}
}
/*************************************************************/
//I2C SLAVE Initial
//EntryParameter:SPEEDMODE,SLAVEBITS,I2C_SALVE_ADD
//SPEEDMODE:FAST_MODE(>100K),STANDARD_MODE(<100K)
//SLAVEBITS:I2C_SLAVE_7BIT/I2C_SLAVE_10BIT
//I2C_SALVE_ADD:I2C SLAVE ADDRESS
//ReturnValue:NONE
/*************************************************************/
void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX)
{
//SDA IO Initial
if(I2C_SDA_IO==I2C_SDA_PA00)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000005; //PA0.0->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA03)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0x00006000; //PA0.3->SDA ///
}
else if (I2C_SDA_IO==I2C_SDA_PA07)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0x40000000; //PA0.7->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA013)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00600000; //PA0.13->SDA
}
else if(I2C_SDA_IO==I2C_SDA_PA014)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0x06000000; //PA0.14->SDA
}
//SCL IO Initial
if (I2C_SCL_IO==I2C_SCL_PB00)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000006; //PB0.0->SCL
}
else if (I2C_SCL_IO==I2C_SCL_PB02)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF) | 0x00000400; //PB0.2->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA01)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0x00000050; //PA0.1->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA04)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0x00060000; //PA0.4->SCL //
}
else if(I2C_SCL_IO==I2C_SCL_PA06)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x06000000; //PA0.6->SCL
}
else if(I2C_SCL_IO==I2C_SCL_PA015)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF) | 0x60000000; //PA0.15->SCL
}
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE;
I2C0->CR =(I2C0->CR&0XFFFFF000)| I2C_MASTER_DIS |I2C_SLAVE_EN | SPEEDMODE | SLAVEBITS;
I2C0->SADDR = I2C_SALVE_ADDS;
if(SPEEDMODE==FAST_MODE)
{
I2C0->FS_SCLH = SS_SCLHX; //SCL high time
I2C0->FS_SCLL = SS_SCLLX; //SCL low time
}
else if(SPEEDMODE==STANDARD_MODE)
{
I2C0->SS_SCLH = SS_SCLHX; //SCL high time
I2C0->SS_SCLL = SS_SCLLX; //SCL low time
}
INTC_IPR4_WRITE(0X40400040); //setting highest INT Priority when using i2c as salve
}
/*************************************************************/
//I2C SDA TSETUP THOLD CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD)
{
I2C0->SDA_TSETUP=SDA_TSETUP;
I2C0->SDA_THOLD=(SDA_RX_THOLD<<16)|SDA_TX_THOLD;
}
/*************************************************************/
//I2C INT CONFIG
//EntryParameter:I2C_RX_UNDER,I2C_RX_OVER,I2C_RX_FULL,I2C_TX_OVER
// I2C_TX_EMPTY,I2C_RD_REQ,I2C_TX_ABRT,I2C_RX_DONE
// I2C_INT_BUSY,I2C_STOP_DET,I2C_START_DET,I2C_GEN_CALL
// I2C_RESTART_DET,I2C_MST_ON_HOLD,I2C_SCL_SLOW
//NewState:ENABLE/DISABLE
//ReturnValue:NONE
/*************************************************************/
void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE)
{
if(NewState != DISABLE)
{
I2C0->IMSCR |= INT_TYPE;
}
else
{
I2C0->IMSCR &= (~INT_TYPE);
}
}
/*************************************************************/
//I2C FIFO trigger data
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL)
{
I2C0->RX_FLSEL = RX_FLSEL;
I2C0->TX_FLSEL = TX_FLSEL;
}
/*************************************************************/
//I2C Stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Stop(void)
{
I2C0->DATA_CMD = (I2C0->DATA_CMD&0XFFFFFDFF)|I2C_CMD_STOP; //Enable I2C
}
/*************************************************************/
//I2C enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Enable(void)
{
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFE)|I2C_ENABLE; //Enable I2C
while((I2C0->STATUS&0x1000)!=0x1000);
}
/*************************************************************/
//I2C disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Disable(void)
{
I2C0->ENABLE =(I2C0->ENABLE&0XFFFFFFFE)|I2C_DISABLE; //Disable I2C
while((I2C0->STATUS&0x1000)==0x1000);
}
/*************************************************************/
//I2C Abort enable in master mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Abort_EN(void)
{
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFFD)|I2C_ABORT; //Enable Abort
}
/*************************************************************/
//I2C Abort status
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T I2C_Abort_Status(void)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=(I2C0->ENABLE)&0x02;
if (dat == 0x02)
{
value = 1; //aborting
}
return value; //no abort or abort over
}
/*************************************************************/
//I2C RECOVER enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_SDA_Recover_EN(void)
{
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|I2C_SDA_REC_EN; //Enable Recover Enable
}
/*************************************************************/
//I2C RECOVER enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_SDA_Recover_DIS(void)
{
I2C0->ENABLE = (I2C0->ENABLE&0XFFFFFFF7)|I2C_SDA_REC_DIS; //Enable Recover Disable
}
/*************************************************************/
//I2C Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Int_Enable(void)
{
INTC_ISER_WRITE(I2C_INT); //Enable I2C interrupt
}
/*************************************************************/
//I2C Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Int_Disable(void)
{
INTC_ICER_WRITE(I2C_INT); //Disable I2C interrupt
}
/*************************************************************/
//I2C WRITE OneByte
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data)
{
U16_T R_EEROR_CONT=0;
I2C0->DATA_CMD = I2C_CMD_WRITE|write_adds ;
I2C0->DATA_CMD = i2c_data |I2C_CMD_STOP;
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
I2C_Disable();
I2C_Enable();
break;
}
}
while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
I2C_Disable();
I2C_Enable();
break;
}
}
while(((I2C0->STATUS) & I2C_TFE) != I2C_TFE);
}
/*************************************************************/
//I2C WRITE nByte
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite)
{
U16_T R_EEROR_CONT=0;
U8_T i;
I2C0->DATA_CMD = I2C_CMD_WRITE|write_adds ;
for(i=0;i<NumByteToWrite;i++)
{
if(i>=NumByteToWrite-1)
{
I2C0->DATA_CMD = *(i2c_data+i) |I2C_CMD_STOP;
}
else
{
I2C0->DATA_CMD = *(i2c_data+i);
}
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
I2C_Disable();
I2C_Enable();
break;
}
}
while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
I2C_Disable();
I2C_Enable();
break;
}
}
while(((I2C0->STATUS) & I2C_TFNF) != I2C_TFNF);
}
}
/*************************************************************/
//I2C READ OneByte
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T I2C_READ_Byte(U8_T read_adds)
{
U8_T value;
U16_T R_EEROR_CONT=0;
I2C0->DATA_CMD = I2C_CMD_WRITE|read_adds|I2C_CMD_RESTART1;
I2C0->DATA_CMD = I2C_CMD_READ |I2C_CMD_STOP;
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
break;
}
}
while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
break;
}
}
while( (I2C0->STATUS & I2C_RFNE) != I2C_RFNE ); //Wait for RX done
value=I2C0->DATA_CMD &0XFF;
return value;
}
/*************************************************************/
//I2C READ nByte
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite)
{
U16_T R_EEROR_CONT=0;
U8_T i;
I2C0->DATA_CMD = I2C_CMD_WRITE|read_adds|I2C_CMD_RESTART1;
for(i=0;i<NumByteToWrite;i++)
{
if(i>=NumByteToWrite-1)
{
I2C0->DATA_CMD = I2C_CMD_READ |I2C_CMD_STOP;
}
else
{
I2C0->DATA_CMD = I2C_CMD_READ;
}
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
break;
}
}
while( (I2C0->STATUS & I2C_BUSY) != I2C_BUSY ); //Wait for FSM working
do
{
if(R_EEROR_CONT++>=10000)
{
R_EEROR_CONT=0;
f_ERROR=1;
break;
}
}
while( (I2C0->STATUS & I2C_RFNE) != I2C_RFNE ); //Wait for RX done
*(i2c_data+i)=I2C0->DATA_CMD &0XFF;
}
}
U16_T R_READ_BUF=0;
/*************************************************************/
//I2C slave Receive
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void I2C_Slave_Receive(void)
{
if(!(((I2C0->MISR&I2C_SCL_SLOW)==I2C_SCL_SLOW)
||((I2C0->MISR&I2C_TX_ABRT)==I2C_TX_ABRT))) //IIC is aborted when sclk locked))
{
if((I2C0->MISR&I2C_RX_FULL)==I2C_RX_FULL) //Data received？
{
if(RdIndex==0)
{
RdIndex=1;
I2C_Data_Adress=I2C0->DATA_CMD&0XFF;
I2C_St_Adress=I2C_Data_Adress;
}
else
{
if(I2C_Data_Adress<BUFSIZE)
{
I2CRdBuffer[I2C_Data_Adress]= I2C0->DATA_CMD&0XFF;
}
I2C_Data_Adress++;
}
I2C0->ICR = I2C_RX_FULL;
R_IIC_ERROR_CONT=0;
}
if((I2C0->MISR&I2C_RD_REQ)==I2C_RD_REQ) //Read request generated
{
if(RdIndex==1)
{
RdIndex=2;
WrIndex = I2C_St_Adress;
//I2C_ConfigInterrupt_CMD(ENABLE,I2C_TX_EMPTY);
if(WrIndex<BUFSIZE)
{
I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex];
}
}
I2C0->ICR = I2C_RD_REQ;
R_IIC_ERROR_CONT=0;
}
if((I2C0->MISR&I2C_TX_EMPTY)==I2C_TX_EMPTY) //IIC send empty
{
if(RdIndex==2)
{
if(WrIndex+1<BUFSIZE)
{
I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00) |I2CWrBuffer[WrIndex+1];
}
WrIndex++;
}
else
{
if(R_IIC_ERROR_CONT>10000)
{
I2C_Disable();
I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00);
I2C_SLAVE_CONFIG();
R_IIC_ERROR_CONT=0;
}
else
{
R_IIC_ERROR_CONT++;
}
}
I2C0->CR = I2C_TX_EMPTY;
}
else if((I2C0->MISR&I2C_STOP_DET)==I2C_STOP_DET)
{
I2C0->ICR =I2C_STOP_DET;
if(RdIndex!=0)
{
RdIndex=0;
//I2C_ConfigInterrupt_CMD(DISABLE,I2C_TX_EMPTY);
}
R_READ_BUF=I2C0->DATA_CMD&0XFF;
R_IIC_ERROR_CONT=0;
}
}
else
{
I2C_Disable();
I2C0->DATA_CMD= (I2C0->DATA_CMD&0XFFFFFF00);
I2C_SLAVE_CONFIG();
RdIndex=0;
//I2C_ConfigInterrupt_CMD(ENABLE,I2C_TX_EMPTY);
I2C0->ICR = I2C_SCL_SLOW|I2C_TX_ABRT;
R_IIC_ERROR_CONT=0;
}
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

264
Source/FWlib/apt32f102_ifc.c Normal file
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/*
******************************************************************************
* @file apt32f102_ifc.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_ifc.h"
volatile unsigned int R_INT_FlashAdd;
volatile unsigned char f_Drom_writing=0;
/* define --------------------------------------------------------------------*/
extern void delay_nms(unsigned int t);
/* externs--------------------------------------------------------------------*/
/*************************************************************
//ChipErase fuction
//EntryParameter:NONE
//ReturnValue:NONE
*************************************************************/
void ChipErase(void)
{
SetUserKey;
EnChipErase;
StartErase;
while(IFC->CR!=0x0); //Wait for the operation to complete
}
/*************************************************************
//PageErase fuction
//EntryParameter:XROM_PageAdd
//XROM_PageAdd:PROM_PageAdd0~PROM_PageAdd255
//DROM_PageAdd0~DROM_PageAdd31
//ReturnValue:NONE
*************************************************************/
void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAdd)
{
SetUserKey;
EnPageErase;
IFC->FM_ADDR=XROM_PageAdd;
StartErase;
while(IFC->CR!=0x0);
}
/*************************************************************
//Enable or Disable IFC Interrupt when Operate FlashData
//EntryParameter:FlashAdd、DataSize、*BufArry
//ReturnValue:NONE
*************************************************************/
//PROM:Write at most 256 bytes once time
//DROM:Write at most 64 bytes at once time
//Interrupt mode requires multiple loop queries to complete
void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry)
{
int i,DataBuffer;
if(!f_Drom_writing)
{
f_Drom_writing=1;
R_INT_FlashAdd=FlashAdd;
ifc_step=0;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07; //Page cache wipe
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<((DataSize+3)/4);i++) //sizeof structure
{
DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24);
*(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer;
BufArry +=4;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
}
}
//Normal mode, when the call is completed once, it will delay 4.2ms in the program
void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry)
{
int i,DataBuffer;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<((DataSize+3)/4);i++) //sizeof structure
{
DataBuffer=*BufArry+(*(BufArry+1)<<8)+(*(BufArry+2)<<16)+(*(BufArry+3)<<24);
*(volatile unsigned int *)(FlashAdd+4*i)=DataBuffer;
BufArry +=4;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete
//Page erase 5
SetUserKey;
IFC->CMR=0x02;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete
//Write page cache data to flash memory 6
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete
}
void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry)
{
int i,DataBuffer;
//Page cache wipe 1
SetUserKey;
IFC->CMR=0x07;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Write data to the cache 2
for(i=0;i<DataSize;i++) //sizeof structure
{
DataBuffer=*BufArry;
*(volatile unsigned int *)(FlashAdd)=DataBuffer;
BufArry +=1;
}
//Pre-programmed operation settings 3
SetUserKey;
IFC->CMR=0x06;
IFC->FM_ADDR=FlashAdd;
IFC->CR=0X01; //Start Program
while(IFC->CR!=0x0); //Wait for the operation to complete
//Perform pre-programming 4
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=PEP_END_INT); //Wait for the operation to complete
//Page erase 5
SetUserKey;
IFC->CMR=0x02;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=ERS_END_INT); //Wait for the operation to complete
//Write page cache data to flash memory 6
SetUserKey;
IFC->CMR=0x01;
IFC->FM_ADDR=FlashAdd; //
IFC->CR=0X01; //Start Program
while(IFC->RISR!=RGM_END_INT); //Wait for the operation to complete
}
/*************************************************************
// ReadFlashData fuction return Data arry save in Flash
// DataLength must be a multiple of 4, DataLength % 4 ==0.
//EntryParameter:RdStartAdd、DataLength、*DataArryPoint
//ReturnValue:NONE
*************************************************************/
void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint)
{
unsigned int i,Buffer;
//delay_nms(1);
for(i=0;i<((DataLength+3)/4);i++)
{
Buffer=*(volatile unsigned int *)RdStartAdd;
*DataArryPoint=Buffer;
*(DataArryPoint+1)=Buffer>>8;
*(DataArryPoint+2)=Buffer>>16;
*(DataArryPoint+3)=Buffer>>24;
RdStartAdd +=4;
DataArryPoint +=4;
}
}
/*************************************************************
//ReadFlashData fuction return Data arry save in Flash
//EntryParameter:RdStartAdd、DataLength、*DataArryPoint
//ReturnValue:NONE
*************************************************************/
void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint)
{
unsigned int i;
for (i=0;i<DataLength;i++)
{
if((i!=0)&&(i%4==0))
{
RdStartAdd +=4;
}
*DataArryPoint=*(U8_T *)(RdStartAdd+ (i%4));
DataArryPoint++;
}
}
void ReadDataArry_U32(unsigned int RdStartAdd,unsigned int DataLength,volatile U32_T *DataArryPoint)
{
unsigned int i;
for (i=0;i<DataLength;i++)
{
*DataArryPoint=*(U32_T *)(RdStartAdd);
DataArryPoint++;
}
}
/*************************************************************
//Enable or Disable IFC Interrupt when Operate FlashData
//EntryParameter:IFC_INT_x
//IFC_INT_x:ERS_END_INT,RGM_END_INT,PEP_END_INT,PROT_ERR_INT,UDEF_ERR_INT,ADDR_ERR_INT,OVW_ERR_INT
//ReturnValue:NONE
*************************************************************/
void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x)
{
if(NewState != DISABLE)
{
IFC->IMCR =IFC->IMCR|IFC_INT_x;
}
else
{
IFC->IMCR =IFC->IMCR & (~IFC_INT_x);
}
}
/*************************************************************/
//IFC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFC_Int_Enable(void)
{
IFC->ICR=0Xf007; //CLAER IFC INT status
INTC_ISER_WRITE(IFC_INT);
}
/*************************************************************/
//IFC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void IFC_Int_Disable(void)
{
INTC_ICER_WRITE(IFC_INT);
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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Source/FWlib/apt32f102_iostring.c Normal file
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/*
******************************************************************************
* @file apt32f102_iostring.c
* @author APT AE Team
* @version V1.00
* @date 2020/05/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/******************************************************************************
* Include Files
******************************************************************************/
#include "apt32f102.h"
#include "apt32f102_uart.h"
#include "stdarg.h"
#include "stddef.h"
#include "stdio.h"
/******************************************************************************
* Main code
******************************************************************************/
void __putchar__ (char s)
{
// UARTTxByte(UART0,s);
UARTTxByte(UART1,s);
}
char *myitoa(int value, int* string, int radix)
{
int tmp[33];
int* tp = tmp;
int i;
unsigned v;
int sign;
int* sp;
if (radix > 36 || radix <= 1)
{
return 0;
}
sign = (radix == 10 && value < 0);
if (sign)
v = -value;
else
v = (unsigned)value;
while (v || tp == tmp)
{
i = v % radix;
v = v / radix;
if (i < 10) {
*tp++ = i+'0';
} else {
*tp++ = i + 'a' - 10;
}
}
sp = string;
if (sign)
*sp++ = '-';
while (tp > tmp)
*sp++ = *--tp;
*sp = 0;
return string;
}
void my_printf(const char *fmt, ...)
{
// const char *s;
const int *s;
int d;
//char ch, *pbuf, buf[16];
char ch, *pbuf;
int buf[16];
va_list ap;
va_start(ap, fmt);
while (*fmt) {
if (*fmt != '%') {
__putchar__(*fmt++);
continue;
}
switch (*++fmt) {
case 's':
s = va_arg(ap, const char *);
for ( ; *s; s++) {
__putchar__(*s);
}
break;
case 'd':
d = va_arg(ap, int);
myitoa(d, buf, 10);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
case 'x':
case 'X':
d = va_arg(ap, int);
myitoa(d, buf, 16);
for (s = buf; *s; s++) {
__putchar__(*s);
}
break;
// Add other specifiers here...
case 'c':
case 'C':
ch = (unsigned char)va_arg(ap, int);
pbuf = &ch;
__putchar__(*pbuf);
break;
default:
__putchar__(*fmt);
break;
}
fmt++;
}
va_end(ap);
}

260
Source/FWlib/apt32f102_lpt.c Normal file
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/*
******************************************************************************
* @file apt32f102_lpt.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_lpt.h"
/*************************************************************/
//LPT RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_DeInit(void)
{
LPT->CEDR = 0xBE980000;
LPT->RSSR = LPT_RESET_VALUE;
LPT->PSCR = LPT_RESET_VALUE;
LPT->CR = 0X00010010;
LPT->SYNCR = LPT_RESET_VALUE;
LPT->PRDR = LPT_RESET_VALUE;
LPT->CMP = LPT_RESET_VALUE;
LPT->CNT = LPT_RESET_VALUE;
LPT->TRGFTCR = LPT_RESET_VALUE;
LPT->TRGFTWR = LPT_RESET_VALUE;
LPT->EVTRG = LPT_RESET_VALUE;
LPT->EVPS = LPT_RESET_VALUE;
LPT->EVSWF = LPT_RESET_VALUE;
LPT->RISR = LPT_RESET_VALUE;
LPT->MISR = LPT_RESET_VALUE;
LPT->IMCR = LPT_RESET_VALUE;
LPT->ICR = LPT_RESET_VALUE;
}
/*************************************************************/
//LPT IO Init
//EntryParameter:LPT_OUT_PA09,LPT_OUT_PB01,LPT_IN_PA10,
//ReturnValue:NONE
/*************************************************************/
void LPT_IO_Init(LPT_IOSET_TypeDef IONAME)
{
if(IONAME==LPT_OUT_PA09)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000080;
}
if(IONAME==LPT_OUT_PB01)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000080;
}
if(IONAME==LPT_IN_PA10)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000800;
}
}
/*************************************************************/
//LPT Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX)
{
LPT->CEDR |=CLKX| CSSX| SHDWSTPX| (FLTCKPRSX<<8);
LPT->PSCR = PSCDIVX;
LPT->CR |=OPMX;
}
/*************************************************************/
//LPT DEBUG MODE
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Debug_Mode(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
LPT->CEDR |= LPT_DEBUG_MODE;
}
else
{
LPT->CEDR &= ~LPT_DEBUG_MODE;
}
}
/*************************************************************/
//LPT Period / Compare set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA)
{
LPT->PRDR =PRDR_DATA;
LPT->CMP =CMP_DATA;
}
/*************************************************************/
//LPT COUNTER set
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_CNT_Write(U16_T CNT_DATA)
{
LPT->CNT =CNT_DATA;
}
/*************************************************************/
//LPT read counters
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
U16_T LPT_PRDR_Read(void)
{
return LPT->PRDR;
}
U16_T LPT_CMP_Read(void)
{
return LPT->CMP;
}
U16_T LPT_CNT_Read(void)
{
return LPT->CNT;
}
/*************************************************************/
//LPT ControlSet Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX)
{
LPT->CR |= SWSYNX| IDLESTX| PRDLDX| POLX| FLTDEBX| FLTDEBX| CMPLDX;
}
/*************************************************************/
//LPT SYNC Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX)
{
LPT->SYNCR |= TRGENX| OSTMDX| AREARMX;
}
/*************************************************************/
//LPT Trigger Init
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA)
{
LPT->TRGFTCR |= SRCSELX| BLKINVX| CROSSMDX;
LPT->TRGFTWR |= OFFSET_DATA |(WINDOW_DATA<<16);
LPT->EVTRG |= TRGSRC0X |ESYN0OEX;
LPT->EVPS |=TRGEC0PRD_DATA;
}
void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA)
{
LPT->EVPS |= TRGEC0PRD_DATA |(TRGEV0CNT_DATA<<16);
}
void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA)
{
LPT->EVPS |= (TRGEV0CNT_DATA<<16);
}
void LPT_Soft_Trigger(void)
{
LPT->EVSWF = 0X01;
}
/*************************************************************/
// LPT start
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Start(void)
{
LPT->RSSR |= 0X01;
}
/*************************************************************/
// LPT stop
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Stop(void)
{
LPT->RSSR &= 0XFFFFFFFE;
}
/*************************************************************/
// LPT soft reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_Soft_Reset(void)
{
LPT->RSSR |= (0X5<<12);
}
/*************************************************************/
// LPT soft reset at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_REARM_Write(void)
{
LPT->SYNCR |= (0X1<<16);
}
/*************************************************************/
// LPT soft read at once sync mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
U8_T LPT_REARM_Read(void)
{
uint8_t value = 0;
uint32_t dat = 0;
dat=(LPT->SYNCR)&(1<<16);
if (dat)
{
value = 1;
}
return value;
}
/*************************************************************/
//LPT inturrpt Configure
//EntryParameter:LPT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X)
{
if (NewState != DISABLE)
{
LPT->IMCR |= LPT_IMSCR_X;
}
else
{
LPT->IMCR &= ~LPT_IMSCR_X;
}
}
/*************************************************************/
//LPT Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_INT_ENABLE(void)
{
INTC_ISER_WRITE(LPT_INT);
}
/*************************************************************/
//LPT Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void LPT_INT_DISABLE(void)
{
INTC_ICER_WRITE(LPT_INT);
}

316
Source/FWlib/apt32f102_rtc.c Normal file
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/*
******************************************************************************
* @file apt32f102_interrupt.c
* @author APT AE Team
* @version V1.11
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_rtc.h"
/* define --------------------------------------------------------------------*/
RTC_time_t RTC_TimeDate_buf;
RTC_Alarmset_T RTC_AlarmA_buf;
RTC_Alarmset_T RTC_AlarmB_buf;
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the RTC registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void RTC_RST_VALUE(void) //reset value
{
RTC->TIMR=RTC_TIMR_RST;
RTC->DATR=RTC_DATR_RST;
RTC->CR=RTC_CR_RST;
RTC->CCR=RTC_CCR_RST;
RTC->ALRAR=RTC_ALRAR_RST;
RTC->ALRBR=RTC_ALRBR_RST;
RTC->SSR=RTC_SSR_RST;
RTC->CAL=RTC_CAL_RST;
RTC->IMCR=RTC_IMCR_RST;
RTC->EVTRG=RTC_EVTRG_RST;
RTC->EVPS=RTC_EVPS_RST;
}
/*************************************************************/
//Deinitializes the RTC GPIO
//EntryParameter:Rtc_Output_Mode_TypeDef
//Rtc_Output_Mode_x:Alarm_A_pulse_output,Alarm_A_High,Alarm_A_Low,Alarm_B_pulse_output,Alarm_B_High,Alarm_B_Low
//ReturnValue:NONE
/*************************************************************/
void RTC_ALM_IO_SET(Rtc_Output_Mode_TypeDef Rtc_Output_Mode_x )
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF)|0X00000500;
RTC->KEY=0XCA53;
RTC->CR=(RTC->CR&0XFFFFE3FF)|Rtc_Output_Mode_x;
while(RTC->CR&0x02);
}
/*************************************************************/
//Deinitializes the RTC clk config
//EntryParameter:CLKSRC_X,DIVS,DIVA
//CLKSRC_X:CLKSRC_ISOSC,CLKSRC_IMOSC,CLKSRC_EMOSC
//DIVS:0~0X7FFF
//DIVA:0~0X7F
//ReturnValue:NONE
/*************************************************************/
//RTC CLK=(EMCLK/4)/(DIVS+1)/(DIVA+1)/4
// (ISCLK)/(DIVS+1)/(DIVA+1)/4
// (IMCLK/4)/(DIVS+1)/(DIVA+1)/4
void RTCCLK_CONFIG(U16_T DIVS , U16_T DIVA , RTC_CLKSRC_TypeDef CLKSRC_X)
{
RTC->KEY=0XCA53;
RTC->CCR|=(0X01<<27);
while(!(RTC->CCR&0x04000000)); //Wait for RTC to stabilize
RTC->CCR=(RTC->CCR&0xfc000000)|DIVS|(DIVA<<16)|(0X01<<23)|CLKSRC_X;
while(!(RTC->CCR&0x04000000)); //Wait for RTC to stabilize
}
/*************************************************************/
//Deinitializes the RTC function config
//EntryParameter:RTC_FMT_MODE_TypeDef,RTC_CPRD_TypeDef,Rtc_ClockOutput_Mode_TypeDe
//RTC_FMT_MODE:RTC_24H,RTC_12H
//RTC_CPRD_x:CPRD_NONE,CPRD_05S,CPRD_1S,CPRD_1MIN,CPRD_1HOUR,CPRD_1DAY,CPRD_1MONTH
//Rtc_ClockOutput_x:COSEL_Cali_512hz,COSEL_Cali_1hz,COSEL_NoCali_512hz,COSEL_NoCali_1hz
//ReturnValue:NONE
/*************************************************************/
void RTC_Function_Config(RTC_FMT_MODE_TypeDef RTC_FMT_MODE , RTC_CPRD_TypeDef RTC_CPRD_x , Rtc_ClockOutput_Mode_TypeDef Rtc_ClockOutput_x)
{
RTC->KEY=0XCA53;
RTC->CR=(RTC->CR&0xffff1cdf)|RTC_FMT_MODE|RTC_CPRD_x|Rtc_ClockOutput_x|0X01<<16;//enable read
}
/*************************************************************/
//Deinitializes the RTC Start
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void RTC_Start(void)
{
RTC->KEY=0XCA53;
RTC->CR=RTC->CR&0xfffffffe;
while((RTC->CR&0x01)!=0||(RTC->CR&0x02)==2);
}
/*************************************************************/
//Deinitializes the RTC Stop
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void RTC_Stop(void)
{
RTC->KEY=0XCA53;
RTC->CR=RTC->CR|0x01;
while((RTC->CR&0x01)!=1||(RTC->CR&0x02)==2);
}
/*************************************************************/
//Deinitializes the RTC timer date set
//EntryParameter:*RTC_TimeDate
//ReturnValue:NONE
/*************************************************************/
void RTC_TIMR_DATR_SET(RTC_time_t *RTC_TimeDate)
{
RTC->KEY=0XCA53;
RTC->TIMR=(RTC_TimeDate->u8Hour<<16)|(RTC_TimeDate->u8Minute<<8)|(RTC_TimeDate->u8Second); //Hour bit6->0:am 1:pm
RTC->DATR=(RTC_TimeDate->u8DayOfWeek<<24)|(RTC_TimeDate->u8Year<<16)|(RTC_TimeDate->u8Month<<8)|(RTC_TimeDate->u8Day<<0);
while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written
}
/*************************************************************/
//Deinitializes the RTC timer date Read
//EntryParameter:*RTC_TimeDate
//ReturnValue:NONE
/*************************************************************/
void RTC_TIMR_DATR_Read(RTC_time_t *RTC_TimeDate)
{
RTC->KEY=0XCA53;
//RTC->CR|=0X01<<16; //enable read
//while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written
RTC_TimeDate->u8Second=(RTC->TIMR)&0x7f;
RTC_TimeDate->u8Minute=(RTC->TIMR>>8)&0x7f;
RTC_TimeDate->u8Hour=(RTC->TIMR>>16)&0x7f;
RTC_TimeDate->u8Day=(RTC->DATR)&0x7f;
RTC_TimeDate->u8Month=(RTC->DATR>>8)&0x7f;
RTC_TimeDate->u8Year=(RTC->DATR>>16)&0x7f;
RTC_TimeDate->u8DayOfWeek=(RTC->DATR>>24)&0x7f;
//RTC->CR&=0XFFFEFFFF; //disable read
}
/*************************************************************/
//Deinitializes the RTC AlarmA set
//EntryParameter:*RTC_AlarmA,RTC_Alarm_Second_mask_TypeDef,RTC_Alarm_Minute_mask_TypeDef,
// RTC_Alarm_Hour_mask_TypeDef,RTC_Alarm_DataOrWeek_mask_TypeDef,RTC_Alarm_WeekData_select_TypeDef,
// RTC_Alarm_Register_select_TypeDef
//RTC_Alarm_Second_x:Alarm_Second_EN,Alarm_Second_DIS
//RTC_Alarm_Minute_x:Alarm_Minute_EN,Alarm_Minute_DIS
//RTC_Alarm_Hour_x:Alarm_Hour_EN,Alarm_Hour_DIS
//RTC_Alarm_DataOrWeek_x:Alarm_DataOrWeek_EN,Alarm_DataOrWeek_DIS
//Alarm_x_selecte:Alarm_data_selecte,Alarm_week_selecte
//Alarm_x:Alarm_A,Alarm_B
//ReturnValue:NONE
/*************************************************************/
void RTC_Alarm_TIMR_DATR_SET(RTC_Alarm_Register_select_TypeDef Alarm_x , RTC_Alarmset_T *RTC_AlarmA , RTC_Alarm_Second_mask_TypeDef RTC_Alarm_Second_x ,
RTC_Alarm_Minute_mask_TypeDef RTC_Alarm_Minute_x , RTC_Alarm_Hour_mask_TypeDef RTC_Alarm_Hour_x,
RTC_Alarm_DataOrWeek_mask_TypeDef RTC_Alarm_DataOrWeek_x,
RTC_Alarm_WeekData_select_TypeDef Alarm_x_selecte)
{
RTC->KEY=0XCA53;
if(Alarm_x==Alarm_A)
{
RTC->CR=RTC->CR&0xfffffff7;
RTC->ALRAR=(Alarm_x_selecte)|(RTC_Alarm_DataOrWeek_x)|(RTC_Alarm_Hour_x)|(RTC_Alarm_Minute_x)|(RTC_Alarm_Second_x)|
(RTC_AlarmA->u8WeekOrData<<24)|(RTC_AlarmA->u8Hour<<16)|(RTC_AlarmA->u8Minute<<8)|(RTC_AlarmA->u8Second);
while(RTC->CR&0x02);
RTC->CR|=Alarm_A_EN;
}
if(Alarm_x==Alarm_B)
{
RTC->CR=RTC->CR&0xffffffef;
RTC->ALRBR=(Alarm_x_selecte)|(RTC_Alarm_DataOrWeek_x)|(RTC_Alarm_Hour_x)|(RTC_Alarm_Minute_x)|(RTC_Alarm_Second_x)|
(RTC_AlarmA->u8WeekOrData<<24)|(RTC_AlarmA->u8Hour<<16)|(RTC_AlarmA->u8Minute<<8)|(RTC_AlarmA->u8Second);
while(RTC->CR&0x02);
RTC->CR|=Alarm_B_EN;
}
RTC->KEY = 0;
while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written
}
/*************************************************************/
//Deinitializes the RTC AlarmA read
//EntryParameter:*RTC_AlarmA
//ReturnValue:NONE
/*************************************************************/
void RTC_AlarmA_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmA)
{
RTC->KEY=0XCA53;
//RTC->CR|=0X01<<16; //enable read
//while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written
RTC_AlarmA->u8Second=(RTC->ALRAR)&0x7f;
RTC_AlarmA->u8Minute=(RTC->ALRAR>>8)&0x7f;
RTC_AlarmA->u8Hour=(RTC->ALRAR>>16)&0x7f;
RTC_AlarmA->u8WeekOrData=(RTC->ALRAR>>24)&0x3f;
//RTC->CR&=0XFFFEFFFF; //disable read
}
/*************************************************************/
//Deinitializes the RTC AlarmB read
//EntryParameter:*RTC_AlarmB
//ReturnValue:NONE
/*************************************************************/
void RTC_AlarmB_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmB)
{
RTC->KEY=0XCA53;
//RTC->CR|=0X01<<16; //enable read
//while(RTC->CR&0x02);//busy wait TIMR DATR ALRAR ALRBR Data written
RTC_AlarmB->u8Second=(RTC->ALRBR)&0x7f;
RTC_AlarmB->u8Minute=(RTC->ALRBR>>8)&0x7f;
RTC_AlarmB->u8Hour=(RTC->ALRBR>>16)&0x7f;
RTC_AlarmB->u8WeekOrData=(RTC->ALRBR>>24)&0x3f;
//RTC->CR&=0XFFFEFFFF; //disable read
}
/*************************************************************/
//RTC EVTRG Config
//EntryParameter:RTC_EVTRG_TRGSRC0_x,RTC_TRGSRCX_CMD,Trgev0Prd
//RTC_EVTRG_TRGSRC0_x:RTC_EVTRG_TRGSRC0_DIS,RTC_EVTRG_TRGSRC0_AlarmA,
//RTC_EVTRG_TRGSRC0_AlarmB,RTC_EVTRG_TRGSRC0_AlarmAB,RTC_EVTRG_TRGSRC0_CPRD
//RTC_TRGSRCX_CMD:RTC_TRGSRC0_EN,RTC_TRGSRC0_DIS
//Trgev0Prd:0~0x0f
//ReturnValue: NONE
/*************************************************************/
void RTC_TRGSRC0_Config(RTC_EVTRG_TRGSRC0_TypeDef RTC_EVTRG_TRGSRC0_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev0Prd)
{
RTC->EVTRG=(RTC->EVTRG&0XFFEFFFF0)|RTC_EVTRG_TRGSRC0_x|RTC_TRGSRCX_CMD;
RTC->EVPS=(RTC->EVPS&0XFFFFFFF0)|Trgev0Prd;
}
/*************************************************************/
//RTC EVTRG SWFTRG
//EntryParameter:RTC_EVTRG_TRGSRC1_x,RTC_TRGSRCX_CMD,Trgev1Prd
//RTC_EVTRG_TRGSRC1_x:RTC_EVTRG_TRGSRC1_DIS,RTC_EVTRG_TRGSRC1_AlarmA,
//RTC_EVTRG_TRGSRC1_AlarmB,RTC_EVTRG_TRGSRC1_AlarmAB,RTC_EVTRG_TRGSRC1_CPRD
//RTC_TRGSRCX_CMD:RTC_TRGSRC1_EN,RTC_TRGSRC1_DIS
//Trgev1Prd:0~0x0f
//ReturnValue: NONE
/*************************************************************/
void RTC_TRGSRC1_Config(RTC_EVTRG_TRGSRC1_TypeDef RTC_EVTRG_TRGSRC1_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev1Prd)
{
RTC->EVTRG=(RTC->EVTRG&0XFFDFFF0F)|RTC_EVTRG_TRGSRC1_x|RTC_TRGSRCX_CMD;
RTC->EVPS=(RTC->EVPS&0XFFFFFF0F)|Trgev1Prd<<4;
}
/*************************************************************/
//RTC EVTRG SWFTRG
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void RTC_TRGSRC0_SWFTRG(void)
{
RTC->EVSWF|=0X01;
}
/*************************************************************/
//RTC EVTRG SWFTRG
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void RTC_TRGSRC1_SWFTRG(void)
{
RTC->EVSWF|=0X02;
}
/*************************************************************/
//RTC INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void RTC_Int_Enable(RTC_INT_TypeDef RTC_X_INT)
{
RTC->ICR = RTC_X_INT; //clear LVD INT status
RTC->IMCR |= RTC_X_INT;
}
/*************************************************************/
//RTC INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void RTC_Int_Disable(RTC_INT_TypeDef RTC_X_INT)
{
RTC->IMCR &= ~RTC_X_INT;
}
/*************************************************************/
//RTC Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void RTC_Vector_Int_Enable(void)
{
INTC_ISER_WRITE(RTC_INT);
}
/*************************************************************/
//RTC Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void RTC_Vector_Int_Disable(void)
{
INTC_ICER_WRITE(RTC_INT);
}
/*************************************************************/
//RTC Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void RTC_WakeUp_Enable(void)
{
INTC_IWER_WRITE(RTC_INT);
}
/*************************************************************/
//RTC Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void RTC_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(RTC_INT);
}
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_sio.c
* @author APT AE Team
* @version V1.11
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_sio.h"
/*************************************************************/
//SIO RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_DeInit(void)
{
SIO0->CR = SIO_RESET_VALUE;
SIO0->TXCR0 = SIO_RESET_VALUE;
SIO0->TXCR1 = SIO_RESET_VALUE;
//SIO0->TXBUF = SIO_RESET_VALUE;
SIO0->RXCR0 = SIO_RESET_VALUE;
SIO0->RXCR1 = SIO_RESET_VALUE;
SIO0->RXCR1 = SIO_RESET_VALUE;
//SIO0->RXBUF = SIO_RESET_VALUE;
SIO0->RISR = SIO_RESET_VALUE;
SIO0->MISR = SIO_RESET_VALUE;
SIO0->IMCR = SIO_RESET_VALUE;
SIO0->ICR = SIO_RESET_VALUE;
}
/*************************************************************/
//SIO IO Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_IO_Init(SIO_IOG_TypeDef IOGx)
{
if(IOGx==SIO_PA02)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFF0FF)|0x00000400;
}
if(IOGx==SIO_PA03)
{
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFF0FFF)|0x00008000;
}
if(IOGx==SIO_PA012)
{
GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00080000;
}
if(IOGx==SIO_PB01)
{
GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000070;
}
}
/*************************************************************/
//SIO TX Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_TX_Init(SIO_CLK_TypeDef CLKX,U8_T TCKPRSX)
{
SIO0->CR =CLKX | (TCKPRSX<<16) |(0X00<<8);
}
/*************************************************************/
//SIO TX Configure
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_TX_Configure(SIO_IDLEST_TypeDef IDLEX,SIO_TXDIR_TypeDef TXDIRX,U8_T TXBUFLENX,U8_T TXCNTX,U8_T D0DURX,U8_T D1DURX,SIO_LENOBH_TypeDef LENOBHX,
SIO_LENOBL_TypeDef LENOBLX,U8_T HSQX,U8_T LSQX)
{
SIO0->TXCR0 =IDLEX | TXDIRX | (TXBUFLENX<<4) |(TXCNTX<<8);
SIO0->TXCR1=(D0DURX<<2)|(D1DURX<<5)|LENOBHX|LENOBLX|(HSQX<<16)|(LSQX<<24);
}
/*************************************************************/
//SIO TX BUFFER SET
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_TXBUF_Set(U8_T D30,U8_T D28,U8_T D26,U8_T D24,U8_T D22,U8_T D20,U8_T D18,U8_T D16,
U8_T D14,U8_T D12,U8_T D10,U8_T D08,U8_T D06,U8_T D04,U8_T D02,U8_T D00)
{
SIO0->TXBUF=(D30<<30)|(D28<<28)|(D26<<26)|(D24<<24)|(D22<<22)|(D20<<20)|(D18<<18)|(D16<<16)|
(D14<<14)|(D12<<12)|(D10<<10)|(D08<<8)|(D06<<6)|(D04<<4)|(D02<<2)|(D00<<0);
}
/*************************************************************/
//SIO RX Initial
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_RX_Init(SIO_CLK_TypeDef CLKX,SIO_RXDEB_TypeDef RXDEBX,U8_T DEBCKSX)
{
SIO0->CR =CLKX | RXDEBX |(0X01<<8) | (DEBCKSX<<4);
}
/*************************************************************/
//SIO RX Basic Configure
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_RX_Configure0(SIO_BSTSEL_TypeDef BSTSELX,SIO_TRGMODE_TypeDef TRGMX,U8_T SPLCNTX,U8_T EXTRACTX,U8_T HITHRX,
SIO_ALIGNEN_TypeDef ALIGNX,SIO_RXDIR_TypeDef RXDIRX,SIO_RXMODE_TypeDef RXMODEX,U8_T RXLENX,U8_T RXBUFLENX,U8_T RXKPRSX)
{
SIO0->RXCR0=BSTSELX|TRGMX|(SPLCNTX<<4)|(EXTRACTX<<10)|(HITHRX<<16)|(ALIGNX)|RXDIRX|RXMODEX;
SIO0->RXCR1=(RXLENX)|(RXBUFLENX<<8)|(RXKPRSX<<16);
}
/*************************************************************/
//SIO RX Configure 1
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_RX_Configure1(SIO_BREAKEN_TypeDef BREAKX,SIO_BREAKLVL_TypeDef BREAKLVLX,U8_T BREKCNTX,SIO_TORSTEN_TypeDef TORSTX,U8_T TOCNTX)
{
SIO0->RXCR2=BREAKX|BREAKLVLX|(BREKCNTX<<3)|TORSTX|(TOCNTX<<16);
}
/*************************************************************/
//SIO inturrpt Configure
//EntryParameter:LPT_IMSCR_X,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void SIO_ConfigInterrupt_CMD(FunctionalStatus NewState,SIO_IMSCR_TypeDef SIO_IMSCR_X)
{
if (NewState != DISABLE)
{
SIO0->IMCR |= SIO_IMSCR_X;
}
else
{
SIO0->IMCR &= ~SIO_IMSCR_X;
}
}
/*************************************************************/
//SIO Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_INT_ENABLE(void)
{
INTC_ISER_WRITE(SIO_INT);
}
/*************************************************************/
//SIO Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SIO_INT_DISABLE(void)
{
INTC_ICER_WRITE(SIO_INT);
}

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/*
******************************************************************************
* @file apt32f102_spi.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#include "apt32f102_spi.h"
/* defines -------------------------------------------------------------------*/
/* -------- variables ---------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
extern void delay_nus(unsigned int t);
/*************************************************************/
//SPI RESET,CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_DeInit(void)
{
SPI0->CR0 = SPI_CR0_RST;
SPI0->CR1 = SPI_CR1_RST;
//SPI0->DR = SPI_DR_RST;
SPI0->SR = SPI_SR_RST;
SPI0->CPSR = SPI_CPSR_RST;
SPI0->IMSCR = SPI_IMSCR_RST;
SPI0->RISR = SPI_RISR_RST;
SPI0->MISR = SPI_MISR_RST;
SPI0->ICR = SPI_ICR_RST;
}
/*************************************************************/
//SPI NSS IO Initial
//ReturnValue:NONE
/*************************************************************/
void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP)
{
if(SPI_NSS_IO_GROUP==0)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x05000000; //PA0.6
}
else if(SPI_NSS_IO_GROUP==1)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0x00800000; //PB0.5
}
}
/*************************************************************/
//SPI Master Init
//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_SPO_X,SPI_SPH_X,SPI_LBM_X,SPI_SCR,SPI_CPSDVSR
//SPI_IO:SPI_G0,SPI_G1,SPI_G2
//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT
//SPI_SPO_X:SPI_SPO_0,SPI_SPO_1
//SPI_SPH_X:SPI_SPH_0,SPI_SPH_1
//SPI_LBM_X:SPI_LBM_0,SPI_LBM_1
//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2
//SPI_SCR:0~255
//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254
//ReturnValue:NONE
/*************************************************************/
//SPI Baud rate:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
//FPCLK (max) → 2 × FSSPCLKOUT (max) master Fastest speed
void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR )
{
if (SPI_IO==SPI_G0)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800;
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MOSI,PA0.8->SPI_MIS0
}
else if(SPI_IO==SPI_G1)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MOSI,PA0.11->SPI_MIS0
}
else if(SPI_IO==SPI_G2)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4
GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15
}
SPI0->CPSR=SPI_CPSDVSR;
SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPO_X<<6)|(SPI_SPH_X<<7)|(SPI_SCR<<8);
SPI0->CR1|=0X02|SPI_LBM_X|(SPI_RXIFLSEL_X<<4);
}
/*************************************************************/
//SPI Slave Init
//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_RXIFLSEL_X,SPI_SCR,SPI_CPSDVSR
//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT
//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2
//SPI_SCR:0~255
//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254
//ReturnValue:NONE
/*************************************************************/
//SPI波特率:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
//FPCLK (max) → 12 × FSSPCLKIN (max) slave Fastest speed
void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR)
{
if (SPI_IO==SPI_G0)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800;
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MISO,PA0.8->SPI_MOSI
}
else if(SPI_IO==SPI_G1)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MISO,PA0.11->SPI_MOSI
}
else if(SPI_IO==SPI_G2)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4
GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15
}
SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPH_X<<7)|(SPI_SCR<<8);
SPI0->CPSR=SPI_CPSDVSR;
SPI0->CR1|=0X06|(SPI_RXIFLSEL_X<<4);
}
/*************************************************************/
//SPI WRITE BYTE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_WRITE_BYTE(U16_T wdata)
{
while(((SPI0->SR) & SSP_TNF) != SSP_TNF);
SPI0->DR = wdata;
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //wait for transmition finish
}
/*************************************************************/
//SPI READ BYTE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth)
{
U8_T i;
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
SPI0->DR = wdata;
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
delay_nus(1);
*rdata = SPI0->DR;
for(i=0;i<Longth;i++)
{
while(((SPI0->SR) & SSP_TNF) != SSP_TNF);
SPI0->DR=0;
while(((SPI0->SR) & SSP_BSY) == SSP_BSY);
*(rdata+i) = SPI0->DR; //get data from FIFO
}
}
/*************************************************************/
//SPI inturrpt Configure
//EntryParameter:SPI_IMSCR_X,NewState
//SPI_IMSCR_X:SPI_PORIM,SPI_RTIM,SPI_RXIM,SPI_TXIM
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X)
{
if (NewState != DISABLE)
{
SPI0->IMSCR |= SPI_IMSCR_X; //SET
}
else
{
SPI0->IMSCR &= ~SPI_IMSCR_X; //CLR
}
}
/*************************************************************/
//SPI Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Int_Enable(void)
{
INTC_ISER_WRITE(SPI_INT);
}
/*************************************************************/
//SPI Interrupt disalbe
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Int_Disable(void)
{
INTC_ICER_WRITE(SPI_INT);
}
/*************************************************************/
//SPI Interrupt wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Wakeup_Enable(void)
{
INTC_IWER_WRITE(SPI_INT);
}
/*************************************************************/
//SPI Interrupt wake up disalbe
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SPI_Wakeup_Disable(void)
{
INTC_IWDR_WRITE(SPI_INT);
}
/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/

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Source/FWlib/apt32f102_syscon.c Normal file
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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.09
* @date 2021/07/30
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_syscon.h"
/* define --------------------------------------------------------------------*/
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//Deinitializes the syscon registers to their default reset
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_RST_VALUE(void) //reset value
{
//SYSCON->IDCCR=SYSCON_IDCCR_RST;
//SYSCON->GCER=SYSCON_GCER_RST;
//SYSCON->GCDR=SYSCON_GCDR_RST;
//SYSCON->GCSR=SYSCON_GCSR_RST;
//SYSCON->CKST=SYSCON_CKST_RST;
SYSCON->RAMCHK=SYSCON_RAMCHK_RST;
SYSCON->EFLCHK=SYSCON_EFLCHK_RST;
SYSCON->SCLKCR=SYSCON_SCLKCR_RST;
//SYSCON->PCLKCR=SYSCON_PCLKCR_RST;
//SYSCON->PCER0=SYSCON_PCER0_RST;
//SYSCON->PCDR0=SYSCON_PCDR0_RST;
//SYSCON->PCSR0=SYSCON_PCSR0_RST;
//SYSCON->PCER1=SYSCON_PCER1_RST;
//SYSCON->PCDR1=SYSCON_PCDR1_RST;
//SYSCON->PCSR1=SYSCON_PCSR1_RST;
SYSCON->OSTR=SYSCON_OSTR_RST;
SYSCON->LVDCR=SYSCON_LVDCR_RST;
//SYSCON->CLCR=SYSCON_CLCR_RST;
//SYSCON->PWRCR=SYSCON_PWRCR_RST;
//SYSCON->IMER=SYSCON_IMER_RST;
//SYSCON->IMDR=SYSCON_IMDR_RST;
//SYSCON->IMCR=SYSCON_IMCR_RST;
//SYSCON->IAR=SYSCON_IAR_RST;
//SYSCON->ICR=SYSCON_ICR_RST;
//SYSCON->RISR=SYSCON_RISR_RST;
//SYSCON->MISR=SYSCON_MISR_RST;
SYSCON->EXIRT=SYSCON_EXIRT_RST;
SYSCON->EXIFT=SYSCON_EXIFT_RST;
//SYSCON->EXIER=SYSCON_EXIER_RST;
//SYSCON->EXIDR=SYSCON_EXIDR_RST;
//SYSCON->EXIMR=SYSCON_EXIMR_RST;
//SYSCON->EXIAR=SYSCON_EXIAR_RST;
//SYSCON->EXICR=SYSCON_EXICR_RST;
//SYSCON->EXIRS=SYSCON_EXIRS_RST;
SYSCON->IWDCR=SYSCON_IWDCR_RST;
SYSCON->IWDCNT=SYSCON_IWDCNT_RST;
//SYSCON->PWROPT=SYSCON_PWROPT_RST;
SYSCON->EVTRG=SYSCON_EVTRG_RST;
SYSCON->EVPS=SYSCON_EVPS_RST;
SYSCON->EVSWF=SYSCON_EVSWF_RST;
SYSCON->UREG0=SYSCON_UREG0_RST;
SYSCON->UREG1=SYSCON_UREG1_RST;
SYSCON->UREG2=SYSCON_UREG2_RST;
SYSCON->UREG3=SYSCON_UREG3_RST;
}
/*************************************************************/
//EMOSC OSTR Config
//EM_CNT:0~0X3FF
//EM_GM:0~0X1F
//EM_FLEN;EM_FLEN_DIS,EM_FLEN_EN
//EM_FLSEL:EM_FLSEL_5ns,EM_FLSEL_10ns,EM_FLSEL_15ns,EM_FLSEL_20ns
/*************************************************************/
void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X)
{
SYSCON->OSTR=EM_CNT|(EM_GM<<11)|EM_LFSEL_X|EM_FLEN_X|EM_FLSEL_X;
}
/*************************************************************/
//SYSCON General Control
//EntryParameter:NewState:,ENDIS_X
//NewState:ENABLE,DISABLE
//ENDIS_X:ENDIS_ISOSC,ENDIS_IMOSC,ENDIS_EMOSC,ENDIS_HFOSC
//ReturnValue:NONE
/*************************************************************/
void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X )
{
if (NewState != DISABLE)
{
if(ENDIS_X==ENDIS_EMOSC)
GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF00FFF)|0x00044000; //enable EMOSC PIN
SYSCON->GCER|=ENDIS_X; //enable SYSCON General Control
while(!(SYSCON->GCSR&ENDIS_X)); //check Enable?
switch(ENDIS_X)
{
case ENDIS_IMOSC:
while (!(SYSCON->CKST & ENDIS_IMOSC));
break;
case ENDIS_EMOSC:
while (!(SYSCON->CKST & ENDIS_EMOSC));
break;
case ENDIS_ISOSC:
while (!(SYSCON->CKST & ENDIS_ISOSC));
break;
case ENDIS_HFOSC:
while (!(SYSCON->CKST & ENDIS_HFOSC));
break;
case ENDIS_IDLE_PCLK:
break;
case ENDIS_SYSTICK:
break;
}
}
else
{
SYSCON->GCDR|=ENDIS_X; //disable SYSCON General Control
while(SYSCON->GCSR&ENDIS_X); //check Disable?
SYSCON->ICR|=ENDIS_X; //Clear ENDIS_X stable bit
}
}
/*************************************************************/
//Seleted system clk and seleted clk div
//EntryParameter:SYSCLK_X,HCLK_DIV_X,PCLK_DIV_X
//SYSCLK_X:SYSCLK_IMOSC,SYSCLK_EMOSC,SYSCLK_ISOSC,SYSCLK_HFOSC
//HCLK_DIV_X:HCLK_DIV_1/2/3/4/5/6/7/8/12/16/24/32/64/128/256
//PCLK_DIV_X:PCLK_DIV_1,PCLK_DIV_2,PCLK_DIV_4,PCLK_DIV_8,PCLK_DIV_16
//SystemClk_data_x:EMOSC_24M,EMOSC_16M,EMOSC_12M,EMOSC_8M,EMOSC_4M,EMOSC_36K,
//ISOSC,IMOSC,HFOSC_48M,HFOSC_24M,HFOSC_12M,HFOSC_6M
//ReturnValue:NONE
/*************************************************************/
void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x )
{
if(SystemClk_data_x==HFOSC_48M)
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X04|(0X00<<16); //High speed mode
}
if((SystemClk_data_x==EMOSC_24M)||(SystemClk_data_x==HFOSC_24M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X02|(0X00<<16); //Medium speed mode
}
if((SystemClk_data_x==EMOSC_12M)||(SystemClk_data_x==HFOSC_12M)||(SystemClk_data_x==EMOSC_16M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X01|(0X00<<16); //Low speed mode
}
if((SystemClk_data_x==EMOSC_8M)||(SystemClk_data_x==EMOSC_4M)||(SystemClk_data_x==EMOSC_36K)
||(SystemClk_data_x==IMOSC)||(SystemClk_data_x==ISOSC)||(SystemClk_data_x==HFOSC_6M))
{
IFC->CEDR=0X01; //CLKEN
IFC->MR=0X00|(0X00<<16); //Low speed mode
}
SYSCON->SCLKCR=SYSCLK_KEY | HCLK_DIV_X| SYSCLK_X;
while (!(SYSCON->CKST & (1<<8))); // waiting for sysclk stable
SYSCON->PCLKCR=PCLK_KEY|PCLK_DIV_X; //PCLK DIV 1 2 4 6 8 16
while(SYSCON->PCLKCR!=PCLK_DIV_X); //Wait PCLK DIV
}
/*************************************************************/
//clear system clk register
//ReturnValue:NONE
/*************************************************************/
void SystemCLK_Clear(void)
{
SYSCON->SCLKCR=0xd22d0000;
while(SYSCON->SCLKCR!=0);
}
/*************************************************************/
//SYSCON IMOSC SELECTE
//EntryParameter:IMOSC_SELECTE_X
//IMOSC_SELECTE_X:IMOSC_SELECTE_5556K,IMOSC_SELECTE_4194K;IMOSC_SELECTE_2097K;IMOSC_SELECTE_131K
//ReturnValue:NONE
/*************************************************************/
void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X)
{
//SYSCON_General_CMD(DISABLE,ENDIS_IMOSC); //disalbe IMOSC
SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFFC)|IMOSC_SELECTE_X; //IMOSC CLK selected
//SYSCON_General_CMD(ENABLE,ENDIS_IMOSC); //enable IMOSC
}
/*************************************************************/
//SYSCON HFOSC SELECTE
//EntryParameter:HFOSC_SELECTE_X
//HFOSC_SELECTE_X:HFOSC_SELECTE_48M,HFOSC_SELECTE_24M;HFOSC_SELECTE_12M;HFOSC_SELECTE_6M
//ReturnValue:NONE
/*************************************************************/
void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X)
{
SYSCON_General_CMD(DISABLE,ENDIS_HFOSC); //disable HFOSC
SYSCON->OPT1 = (SYSCON->OPT1 & 0XFFFFFFCF)|HFOSC_SELECTE_X;
SYSCON_General_CMD(ENABLE,ENDIS_HFOSC); //enable HFOSC
}
/*************************************************************/
//WDT enable and disable
//EntryParameter:,NewState
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WDT_CMD(FunctionalStatus NewState)
{
if(NewState != DISABLE)
{
SYSCON->IWDEDR=IWDTEDR_KEY|Enable_IWDT;
while(!(SYSCON->IWDCR&Check_IWDT_BUSY));
}
else
{
SYSCON->IWDEDR=IWDTEDR_KEY|Disable_IWDT;
while(SYSCON->IWDCR&Check_IWDT_BUSY);
}
}
/*************************************************************/
//reload WDT CN
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void SYSCON_IWDCNT_Reload(void)
{
SYSCON->IWDCNT=CLR_IWDT;
}
/*************************************************************/
//IWDCNT Config
//EntryParameter:NewStateE_IWDT_SHORT,IWDT_TIME_X,IWDT_INTW_DIV_X
//NewStateE_IWDT_SHORT:ENABLE_IWDT_SHORT,DISABLE_IWDT_SHORT
//IWDT_TIME_X:IWDT_TIME_128MS,IWDT_TIME_256MS,IWDT_TIME_500MS,IWDT_TIME_1S,IWDT_TIME_2S,IWDT_TIME_3S,IWDT_TIME_4S,IWDT_TIME_8S
//IWDT_INTW_DIV_X:IWDT_INTW_DIV_1/2/3/4/4/5/6
//ReturnValue: NONE
/*************************************************************/
void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X )
{
SYSCON->IWDCR=IWDT_KEY|IWDT_TIME_X|IWDT_INTW_DIV_X;
}
/*************************************************************/
//LVD Config and set LVD INT
//EntryParameter:X_LVDEN,INTDET_LVL_X,RSTDET_LVL_X,X_LVD_INT
//X_LVDEN:ENABLE_LVDEN,DISABLE_LVDEN
//INTDET_LVL_X:INTDET_LVL_1_8V,INTDET_LVL_2_1V,INTDET_LVL_2_5V,INTDET_LVL_2_9V,INTDET_LVL_3_3V,INTDET_LVL_3_7V,INTDET_LVL_4_1V,INTDET_LVL_4_5V
//RSTDET_LVL_X:RSTDET_LVL_1_6V,RSTDET_LVL_2_0V,RSTDET_LVL_2_4V,RSTDET_LVL_2_8V,RSTDET_LVL_3_2V,RSTDET_LVL_3_6V,RSTDET_LVL_4_0V,RSTDET_LVL_4_4V
//X_LVD_INT:ENABLE_LVD_INT,DISABLE_LVD_INT
//INTDET_POL_X:INTDET_POL_fall,INTDET_POL_X_rise,INTDET_POL_X_riseORfall
//ReturnValue: NONE
/*************************************************************/
void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X)
{
//SYSCON->LVDCR=LVD_KEY;
SYSCON->LVDCR=LVD_KEY|X_LVDEN|INTDET_LVL_X|RSTDET_LVL_X|X_LVD_INT|INTDET_POL_X;
}
/*************************************************************/
//LVD INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Enable(void)
{
SYSCON->ICR = LVD_INT_ST; //clear LVD INT status
SYSCON->IMER |= LVD_INT_ST;
}
/*************************************************************/
//LVD INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void LVD_Int_Disable(void)
{
SYSCON->IMDR |= LVD_INT_ST;
}
/*************************************************************/
//WDT INT ENABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void IWDT_Int_Enable(void)
{
SYSCON->ICR = IWDT_INT_ST; //clear LVD INT status
SYSCON->IMER |= IWDT_INT_ST;
}
/*************************************************************/
//WDT INT DISABLE.
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void IWDT_Int_Disable(void)
{
SYSCON->IMDR |= IWDT_INT_ST;
}
/*************************************************************/
//Reset status.
//EntryParameter:NONE
//ReturnValue: rsr_dat
//rsr_dat=0x01 power on reset
//rsr_dat=0x02 low voltage reset
//rsr_dat=0x04 ex-pin reset
//rsr_dat=0x10 wdt reset
//rsr_dat=0x40 ex clock invalid reset
//rsr_dat=0x80 cpu request reset
//rsr_dat=0x100 software reset
/*************************************************************/
U32_T Read_Reset_Status(void)
{
return (SYSCON->RSR & 0x1ff);
}
/*************************************************************/
//external trigger Mode Selection Functions
//EntryParameter:NewState,EXIPIN,EXI_tringer_mode
//NewState:ENABLE,DISABLE
//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13
//EXI_tringer_mode:_EXIRT,_EXIFT
//ReturnValue: LVD detection flag
/*************************************************************/
void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode)
{
switch(EXI_tringer_mode)
{
case _EXIRT:
if(NewState != DISABLE)
{
SYSCON->EXIRT |=EXIPIN;
}
else
{
SYSCON->EXIRT &=~EXIPIN;
}
break;
case _EXIFT:
if(NewState != DISABLE)
{
SYSCON->EXIFT |=EXIPIN;
}
else
{
SYSCON->EXIFT &=~EXIPIN;
}
break;
}
}
/*************************************************************/
//external interrupt enable and disable
//EntryParameter:NewState,EXIPIN,* GPIOX
//* GPIOX:GPIOA,GPIOB
//EXIPIN:EXI_PIN0/1/2/3/4/5/6/7/8/9/10/11/12/13
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/
void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN)
{
SYSCON->EXICR = 0X3FFF; //Claer EXI INT status
if(NewState != DISABLE)
{
SYSCON->EXIER|=EXIPIN; //EXI4 interrupt enable
while(!(SYSCON->EXIMR&EXIPIN)); //Check EXI is enabled or not
SYSCON->EXICR |=EXIPIN; // Clear EXI status bit
}
else
{
SYSCON->EXIDR|=EXIPIN;
}
}
/*************************************************************/
//GPIO EXTI interrupt
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE)
{
GPIOX->IECR=GPIO_IECR_VALUE;
}
/*************************************************************/
//PLCK goto SLEEP mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_idle_mode(void)
{
asm ("doze"); // Enter sleep mode
}
/*************************************************************/
//PLCK goto SLEEP mode
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void PCLK_goto_deepsleep_mode(void)
{
SYSCON->WKCR=0X3F<<8;
asm ("stop");
}
/*************************************************************/
//EXI0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Enable(void)
{
INTC_ISER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI0 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_Int_Disable(void)
{
INTC_ICER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Enable(void)
{
INTC_ISER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI1 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_Int_Disable(void)
{
INTC_ICER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI2 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Enable(void)
{
INTC_ISER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI2 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_Int_Disable(void)
{
INTC_ICER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI3 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Enable(void)
{
INTC_ISER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI3 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_Int_Disable(void)
{
INTC_ICER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI4 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Enable(void)
{
INTC_ISER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI4 Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_Int_Disable(void)
{
INTC_ICER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI0 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI0_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI0_INT);
}
/*************************************************************/
//EXI1 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI1 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI1_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI1_INT);
}
/*************************************************************/
//EXI2 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI2 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI2_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI2_INT);
}
/*************************************************************/
//EXI3 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI3 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI3_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI3_INT);
}
/*************************************************************/
//EXI4 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Enable(void)
{
INTC_IWER_WRITE(EXI4_INT);
}
/*************************************************************/
//EXI4 Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void EXI4_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(EXI4_INT);
}
/*************************************************************/
//SYSCON Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Enable(void)
{
INTC_ISER_WRITE(SYSCON_INT);
}
/*************************************************************/
//SYSCON Interrupt disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_Int_Disable(void)
{
INTC_ICER_WRITE(SYSCON_INT);
}
/*************************************************************/
//SYSCON Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Enable(void)
{
INTC_IWER_WRITE(SYSCON_INT);
}
/*************************************************************/
//set PA0.0/PA0.8 as CLO output
//EntryParameter:CLO_PA02/CLO_PA08
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io)
{
if (clo_io==CLO_PA02)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000700;
}
if (clo_io==CLO_PA08)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000007;
}
}
/*************************************************************/
//set CLO clk and div
//EntryParameter:clomxr/clodivr
//ReturnValue:NONE
/*************************************************************/
void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr)
{
SYSCON->OPT1=(SYSCON->OPT1 & 0XFFFF00FF)|(clomxr<<8)|(clodivr<<12);
}
/*************************************************************/
//SYSCON Wake up disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void SYSCON_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(SYSCON_INT);
}
/*************************************************************/
//READ CIF0 data
//EntryParameter:None
//ReturnValue:VALUE
/*************************************************************/
U32_T SYSCON_Read_CINF0(void)
{
U32_T value = 0;
value=SYSCON->CINF0;
return value;
}
/*************************************************************/
//READ CIF1 data
//EntryParameter:None
//ReturnValue:VALUE
/*************************************************************/
U32_T SYSCON_Read_CINF1(void)
{
U32_T value = 0;
value=SYSCON->CINF1;
return value;
}
/*************************************************************/
//Software_Reset
//EntryParameter:None
//ReturnValue:MCU reset
/*************************************************************/
void SYSCON_Software_Reset(void)
{
SYSCON->IDCCR=IDCCR_KEY|SWRST;
}
/*************************************************************/
//Interrupt Priority initial
//EntryParameter:00/40/80/C0
//----------------------
//CORET_INT IRQ0
//SYSCON_INT IRQ1
//IFC_INT IRQ2
//ADC_INT IRQ3
//----------------------
//EPT0_INT IRQ4
//****DUMMY IRQ5
//WWDT_INT IRQ6
//EXI0_INT IRQ7
//----------------------
//EXI1_INT IRQ8
//GPT0_INT IRQ9
//****DUMMY IRQ10
//****DUMMY IRQ11
//----------------------
//RTC_INT IRQ12
//UART0_INT IRQ13
//UART1_INT IRQ14
//UART2_INT IRQ15
//----------------------
//****DUMMY IRQ16
//I2C_INT IRQ17
//****DUMMY IRQ18
//SPI_INT IRQ19
//----------------------
//SIO_INT IRQ20
//EXI2_INT IRQ21
//EXI3_INT IRQ22
//EXI4_INT IRQ23
//----------------------
//CA_INT IRQ24
//TKEY_INT IRQ25
//LPT_INT IRQ26
//****DUMMY IRQ27
//----------------------
//BT0_INT IRQ28
//BT1_INT IRQ29
//----------------------
//ReturnValue:None
//00:Priority 0 highest
//40:Priority 1
//80:Priority 2
//C0:Priority 3 lowest
/*************************************************************/
void SYSCON_INT_Priority(void)
{
INTC_IPR0_WRITE(0XC0C0C0C0); //IQR0-3 low bit-->high bit
INTC_IPR1_WRITE(0XC0C0C0C0); //IQR4-7
INTC_IPR2_WRITE(0XC0C0C0C0); //IQR8-11
INTC_IPR3_WRITE(0XC0C0C0C0); //IQR12-15
INTC_IPR4_WRITE(0XC0C0C0C0); //IQR16-19
INTC_IPR5_WRITE(0XC0C0C0C0); //IQR20-23
INTC_IPR6_WRITE(0XC0C000C0); //IQR24-27
INTC_IPR7_WRITE(0XC0C0C0C0); //IQR28-31
}
/*************************************************************/
//Set Interrupt Priority
//EntryParameter:
//int_name:CORET_IRQ~BT1_IRQ
//int_level:0~3 0=highest 3=lowest
//ReturnValue:None
/*************************************************************/
void Set_INT_Priority(U8_T int_name,U8_T int_level)
{
U8_T i_temp,j_temp;
U32_T k_temp;
i_temp=(int_name%4)*8;
j_temp=int_name/4;
k_temp=CK801 -> IPR[j_temp]&(~(0xff<<i_temp));
CK801 -> IPR[j_temp]=k_temp|((int_level*0x40)<<(i_temp));
}
/*************************************************************/
//IO REMAP
//EntryParameter:GPIOA0(0,1,2,3,4,5,6,7) GPIOB0(2,3),GPIOA0(8,9,10,11,12,13)
//0x00=I2C_SCL 0X01=I2C_SDA 0X02=GPT_CHA 0X03=GPT_CHB
//0X04=SPI_MOSI 0X05=SPI_MISO 0X06=SPI_SCK 0X07=SPI_NSS
//0x00=UART0_RX 0X01=UART0_TX 0X02=EPT_CHAX 0X03=PT_CHBX
//0X04=PT_CHCX 0X05=PT_CHAY 0X06=PT_CHBY 0X07=PT_CHCY
//ReturnValue:NONE
/*************************************************************/
void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data)
{
U8_T i;
if(iomap_data&0x10)
{
iomap_data=iomap_data&0X0F;
if(iomap_data==0)
{
for(i=0;i<28;i+=4)
{
if((SYSCON->IOMAP1&(0xf<<i))==0)
{
SYSCON->IOMAP1=SYSCON->IOMAP1|(0xf<<i);
}
}
}
if(bit==2){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;}
if(bit==3){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;}
if(bit==8){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFFF0) | 0x0000000A;}
if(bit==9){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFFF0F) | 0x000000A0;}
if(bit==10){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFFF0FF) | 0x00000A00;}
if(bit==11){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFFF0FFF) | 0x0000A000;}
if(bit==12){SYSCON->IOMAP1=(SYSCON->IOMAP1&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFFF0FFFF) | 0x000A0000;}
if(bit==13){SYSCON->IOMAP1=(SYSCON->IOMAP1&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONHR =((GPIOx)->CONHR&0XFF0FFFFF) | 0x00A00000;}
}
else
{
if(iomap_data==0)
{
for(i=0;i<28;i+=4)
{
if((SYSCON->IOMAP0&(0xf<<i))==0)
{
SYSCON->IOMAP0=SYSCON->IOMAP0|(0xf<<i);
}
}
}
if(bit==0){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfffffff0)|iomap_data;(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFFF0) | 0x0000000A;}
if(bit==1){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffffff0f)|(iomap_data<<4);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFFF0F) | 0x000000A0;}
if(bit==2){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfffff0ff)|(iomap_data<<8);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFFF0FF) | 0x00000A00;}
if(bit==3){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xffff0fff)|(iomap_data<<12);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFFF0FFF) | 0x0000A000;}
if(bit==4){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xfff0ffff)|(iomap_data<<16);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFFF0FFFF) | 0x000A0000;}
if(bit==5){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xff0fffff)|(iomap_data<<20);(GPIOx)->CONLR =((GPIOx)->CONLR&0XFF0FFFFF) | 0x00A00000;}
if(bit==6){SYSCON->IOMAP0=(SYSCON->IOMAP0&0xf0ffffff)|(iomap_data<<24);(GPIOx)->CONLR =((GPIOx)->CONLR&0XF0FFFFFF) | 0x0A000000;}
if(bit==7){SYSCON->IOMAP0=(SYSCON->IOMAP0&0x0fffffff)|(iomap_data<<28);(GPIOx)->CONLR =((GPIOx)->CONLR&0X0FFFFFFF) | 0x0A0000000;}
}
}
/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/

99
Source/FWlib/apt32f102_tkey_parameter.c Normal file
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@@ -0,0 +1,99 @@
/*
******************************************************************************
* @file apt32f102_tkey_parameter.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#include "apt32f102_tkey.h"
void tk_parameter_init(void)
{
/****************************************************
//TK parameter define
*****************************************************/
TK_IO_ENABLE=TCH_EN(4)|TCH_EN(5)|TCH_EN(7)|TCH_EN(8);
//TK IO ENABLE Bit16-->Bit0;0=DISABLE 1=ENABLE
TK_senprd[0]=30; //TCH0 scan period = TCH0 sens
TK_senprd[1]=50; //TCH1 scan period = TCH1 sens
TK_senprd[2]=50; //TCH2 scan period = TCH2 sens
TK_senprd[3]=50; //TCH3 scan period = TCH3 sens
TK_senprd[4]=140; //TCH4 scan period = TCH4 sens
TK_senprd[5]=50; //TCH5 scan period = TCH5 sens
TK_senprd[6]=50; //TCH6 scan period = TCH6 sens
TK_senprd[7]=50; //TCH7 scan period = TCH7 sens
TK_senprd[8]=50; //TCH8 scan period = TCH8 sens
TK_senprd[9]=50; //TCH9 scan period = TCH9 sens
TK_senprd[10]=50; //TCH10 scan period = TCH10 sens
TK_senprd[11]=50; //TCH11 scan period = TCH11 sens
TK_senprd[12]=50; //TCH12 scan period = TCH12 sens
TK_senprd[13]=50; //TCH13 scan period = TCH13 sens
TK_senprd[14]=50; //TCH14 scan period = TCH14 sens
TK_senprd[15]=50; //TCH15 scan period = TCH15 sens
TK_senprd[16]=50; //TCH16 scan period = TCH16 sens
TK_Triggerlevel[0]=60; //TCH0 TK_Trigger level
TK_Triggerlevel[1]=60; //TCH1 TK_Trigger level
TK_Triggerlevel[2]=60; //TCH2 TK_Trigger level
TK_Triggerlevel[3]=60; //TCH3 TK_Trigger level
TK_Triggerlevel[4]=60; //TCH4 TK_Trigger level
TK_Triggerlevel[5]=60; //TCH5 TK_Trigger level
TK_Triggerlevel[6]=60; //TCH6 TK_Trigger level
TK_Triggerlevel[7]=60; //TCH7 TK_Trigger level
TK_Triggerlevel[8]=60; //TCH8 TK_Trigger level
TK_Triggerlevel[9]=60; //TCH9 TK_Trigger level
TK_Triggerlevel[10]=60; //TCH10 TK_Trigger level
TK_Triggerlevel[11]=60; //TCH11 TK_Trigger level
TK_Triggerlevel[12]=60; //TCH12 TK_Trigger level
TK_Triggerlevel[13]=60; //TCH13 TK_Trigger level
TK_Triggerlevel[14]=60; //TCH14 TK_Trigger level
TK_Triggerlevel[15]=60; //TCH15 TK_Trigger level
TK_Triggerlevel[16]=60; //TCH16 TK_Trigger level
Press_debounce_data=5; //Press debounce 1~10
Release_debounce_data=5; //Release debounce 1~10
Key_mode=1; //Key mode 0=single key 1=multi key
MultiTimes_Filter=0; //MultiTimes Filter,>4 ENABLE <4 DISABLE
Valid_Key_Num=4; //Valid Key number when touched
Base_Speed=10; //baseline update speed
TK_longpress_time=16; //longpress rebuild time = _TK_longpress_time1*1s 0=disable
TK_BaseCnt=59999; //10ms TK_BaseCnt=10ms*48M/8-1,this register need to modify when mcu's Freq changed
/****************************************************
//TK low power function define
*****************************************************/
TK_Lowpower_mode=DISABLE; //touch key can goto sleep when TK lowpower mode enable
TK_Lowpower_level=2; //0=20ms 1=50ms 2=100ms 3=150ms 4=200ms,Scan interval when sleep
TK_Wakeup_level=50; //touch key Trigger level in sleep
/****************************************************
//TK special parameter define
*****************************************************/
TK_PSEL_MODE=TK_PSEL_AVDD; //tk power sel:TK_PSEL_FVR/TK_PSEL_AVDD when select TK_PSEL_FVR PA0.2(TCH3) need a 104 cap
TK_FVR_LEVEL=TK_FVR_4096V; //FVR level:TK_FVR_2048V/TK_FVR_4096V
TK_EC_LEVEL=TK_EC_3_6V; //C0 voltage sel:TK_EC_1V/TK_EC_2V/TK_EC_3V/TK_EC_3_6V
TK_icon[0]=5; //TCH0 TK Scan icon range 0~7
TK_icon[1]=4; //TCH1 TK Scan icon range 0~7
TK_icon[2]=4; //TCH2 TK Scan icon range 0~7
TK_icon[3]=4; //TCH3 TK Scan icon range 0~7
TK_icon[4]=4; //TCH4 TK Scan icon range 0~7
TK_icon[5]=4; //TCH5 TK Scan icon range 0~7
TK_icon[6]=4; //TCH6 TK Scan icon range 0~7
TK_icon[7]=4; //TCH7 TK Scan icon range 0~7
TK_icon[8]=4; //TCH8 TK Scan icon range 0~7
TK_icon[9]=4; //TCH9 TK Scan icon range 0~7
TK_icon[10]=4; //TCH10 TK Scan icon range 0~7
TK_icon[11]=4; //TCH11 TK Scan icon range 0~7
TK_icon[12]=4; //TCH12 TK Scan icon range 0~7
TK_icon[13]=4; //TCH13 TK Scan icon range 0~7
TK_icon[14]=4; //TCH14 TK Scan icon range 0~7
TK_icon[15]=4; //TCH15 TK Scan icon range 0~7
TK_icon[16]=4; //TCH16 TK Scan icon range 0~7
}

397
Source/FWlib/apt32f102_uart.c Normal file
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/*
******************************************************************************
* @file apt32f102_uart.c
* @author APT AE Team
* @version V1.15
* @date 2022/09/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_uart.h"
/* define --------------------------------------------------------------------*/
volatile U8_T RxDataFlag=0;
volatile U8_T TxDataFlag=0;
volatile U8_T f_Uart_send_Complete;
volatile U16_T Uart_send_Length_temp;
volatile U8_T Uart_send_Length;
volatile U8_T Uart_buffer[UART_BUFSIZE];
/* externs--------------------------------------------------------------------*/
/*************************************************************/
//UART RESET,CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_DeInit(void)
{
UART0->DATA = UART_RESET_VALUE;
UART0->SR = UART_RESET_VALUE;
UART0->CTRL = UART_RESET_VALUE;
UART0->ISR = UART_RESET_VALUE;
UART0->BRDIV =UART_RESET_VALUE;
}
void UART1_DeInit(void)
{
UART1->DATA = UART_RESET_VALUE;
UART1->SR = UART_RESET_VALUE;
UART1->CTRL = UART_RESET_VALUE;
UART1->ISR = UART_RESET_VALUE;
UART1->BRDIV =UART_RESET_VALUE;
}
void UART2_DeInit(void)
{
UART2->DATA = UART_RESET_VALUE;
UART2->SR = UART_RESET_VALUE;
UART2->CTRL = UART_RESET_VALUE;
UART2->ISR = UART_RESET_VALUE;
UART2->BRDIV =UART_RESET_VALUE;
}
/*************************************************************/
//UART0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_Int_Enable(void)
{
UART0->ISR=0x0F; //clear UART0 INT status
INTC_ISER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART0 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_Int_Disable(void)
{
INTC_ICER_WRITE(UART0_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Enable(void)
{
UART1->ISR=0x0F; //clear UART1 INT status
INTC_ISER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt Disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_Int_Disable(void)
{
INTC_ICER_WRITE(UART1_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_Int_Enable(void)
{
UART2->ISR=0x0F; //clear UART1 INT status
INTC_ISER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART1 Interrupt Disable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_Int_Disable(void)
{
INTC_ICER_WRITE(UART2_INT); //INT Vector Enable UART0/1 Interrupt in CK802
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART0_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART0_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART0_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART1_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART1_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART1_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_WakeUp_Enable(void)
{
INTC_IWER_WRITE(UART2_INT);
}
/*************************************************************/
//UART0 Wake up enable
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void UART2_WakeUp_Disable(void)
{
INTC_IWDR_WRITE(UART2_INT);
}
/*************************************************************/
//UART IO Init
//EntryParameter:IO_UARTX,UART_IO_G
//IO_UARTX:IO_UART0,IO_UART1
//UART_IO_G:0 1
//ReturnValue:NONE
/*************************************************************/
void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G)
{
if (IO_UART_NUM==IO_UART0)
{
if(UART_IO_G==0)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0x00000004; //PA0.1->RXD0, PA0.0->TXD0
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0x00700000; //PA0.5->RXD0, PA0.12->TXD0
GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0x00070000;
}
}
if (IO_UART_NUM==IO_UART1)
{
if(UART_IO_G==0)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0x00000007; //PA0.13->RXD1, PB0.0->TXD1
GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0x00700000;
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF00FFF) | 0X00077000; //PA0.4->RXD1, PA0.3->TXD1
}
else if(UART_IO_G==2)
{
GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0X77000000; //PA0.15->RXD1, PA0.14->TXD1
}
}
if (IO_UART_NUM==IO_UART2)
{
if(UART_IO_G==0)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF00) | 0x00000077; //PA0.0->RXD2, PA0.1->TXD2
}
else if(UART_IO_G==1)
{
GPIOA0->CONLR = (GPIOA0->CONLR&0X00FFFFFF) | 0X77000000; //PA0.7->RXD2, PA0.6->TXD2
}
else if(UART_IO_G==2)
{
GPIOB0->CONLR = (GPIOB0->CONLR&0XFF00FFFF) | 0X00660000; //PB0.5->RXD2, PB0.4->TXD2
}
}
}
/*************************************************************/
//UART Init
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//e.g:
//sys_clk@24MHz, 24/4(div)=6MHz, 6000000/115200bps=52,baudrate_u16=52
//sys_clk@24MHz, 24/2(div)=12MHz, 12000000/115200bps=104,baudrate_u16=104
//ReturnValue:NONE
/*************************************************************/
void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX |PAR_DAT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART init and enable RX,TX interrupt
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//ReturnValue:NONE
/*************************************************************/
void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT | UART_TX_INT|PAR_DAT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART init and enable RX interrupt
//EntryParameter:UART0,UART1,UART2 ,baudrate_u16
//ReturnValue:NONE
/*************************************************************/
void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT)
{
// Set Transmitter Enable
CSP_UART_SET_CTRL(uart, UART_TX | UART_RX | UART_RX_INT |PAR_DAT);
// Set Baudrate
CSP_UART_SET_BRDIV(uart, baudrate_u16);
}
/*************************************************************/
//UART Close
//EntryParameter:UART0,UART1,UART2
//ReturnValue:NONE
/*************************************************************/
void UARTClose(CSP_UART_T *uart)
{
// Set Transmitter Disable
CSP_UART_SET_CTRL(uart, 0x00);
}
/*************************************************************/
//UART TX Byte loop send
//EntryParameter:UART0,UART1,UART2,txdata_u8
//ReturnValue:NONE
/*************************************************************/
void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8)
{
unsigned int DataI;
// Write the transmit buffer
CSP_UART_SET_DATA(uart,txdata_u8);
do
{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_TX_FULL;
}
while(DataI == UART_TX_FULL); //Loop when tx is full
}
/*************************************************************/
//UART Transmit
//EntryParameter:UART0,UART1,UART2,sourceAddress_u16,length_u16
//ReturnValue:NONE
/*************************************************************/
void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16)
{
unsigned int DataI,DataJ;
for(DataJ = 0;DataJ < length_u16 ;DataJ ++)
{
CSP_UART_SET_DATA(uart,*sourceAddress_u16++);
do{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_TX_FULL;
}while(DataI == UART_TX_FULL); //Loop when tx is full
}
}
/*************************************************************/
//UART INT Transmit
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/
void UARTTTransmit_data_set(CSP_UART_T *uart )
{
if(!f_Uart_send_Complete)
{
f_Uart_send_Complete=1;
Uart_send_Length_temp++;
CSP_UART_SET_DATA(uart,Uart_buffer[0]);
}
}
void UARTTransmit_INT_Send(CSP_UART_T *uart )
{
if(f_Uart_send_Complete)
{
if(Uart_send_Length_temp>=Uart_send_Length)
{
f_Uart_send_Complete=0;
Uart_send_Length_temp=0;
}
else
{
CSP_UART_SET_DATA(uart,Uart_buffer[Uart_send_Length_temp++]);
}
}
}
/*************************************************************/
//UART RX Byte
//EntryParameter:UART0,UART1,UART2,Rxdata_u16
//ReturnValue:NONE
/*************************************************************/
U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16)
{
unsigned int DataI;
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_RX_FULL;
if(DataI != UART_RX_FULL) //Loop when rx is not full
return FALSE;
else
{
*Rxdata_u16 = CSP_UART_GET_DATA(uart);
return TRUE;
}
}
/*************************************************************/
//UART RX Return Byte
//EntryParameter:UART0,UART1,UART2
//ReturnValue:(uart)->DATA
/*************************************************************/
U8_T UART_ReturnRxByte(CSP_UART_T *uart)
{
RxDataFlag = FALSE;
while(RxDataFlag != TRUE);
return CSP_UART_GET_DATA(uart);
}
/*************************************************************/
//UART Receive
//EntryParameter:UART0,UART1,UART2，destAddress_u16，length_u16
//ReturnValue:FALSE/TRUE
/*************************************************************/
U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16)
{
unsigned int DataI,DataJ,LoopTime;
DataJ = 0;
LoopTime = 0;
do{
DataI = CSP_UART_GET_SR(uart);
DataI = DataI & UART_RX_FULL;
if(DataI == UART_RX_FULL) //Loop when rx is full
{
*destAddress_u16++ = CSP_UART_GET_DATA(uart);
DataJ++;
LoopTime = 0;
}
if(LoopTime ++ >= 0xfff0)
return FALSE;
}while(DataJ < length_u16);
return TRUE;
}

90
Source/FWlib/apt32f102_wwdt.c Normal file
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/*
******************************************************************************
* @file apt32f102_wwdt.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_wwdt.h"
/*************************************************************/
//WWDT RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_DeInit(void)
{
WWDT->CR = 0x000000FF;
WWDT->CFGR = 0x000000FF;
WWDT->RISR = WWDT_RESET_VALUE;
WWDT->MISR = WWDT_RESET_VALUE;
WWDT->IMCR = WWDT_RESET_VALUE;
WWDT->ICR = WWDT_RESET_VALUE;
}
/*************************************************************/
//WWDT CONFIG
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX)
{
WWDT->CFGR =WND_DATA;
WWDT->CFGR |= PSCDIVX |DBGENX;
}
/*************************************************************/
//WWDT ENABLE/DISABLE
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CMD(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
WWDT->CR |= 0x01<<8;
}
else
{
WWDT->CR &= 0xfffffeff;
}
}
/*************************************************************/
//WWDT load data
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void WWDT_CNT_Load(U8_T cnt_data)
{
WWDT->CR |= cnt_data; //SET
}
/*************************************************************/
//WWDT INT ENABLE/DISABLE
//EntryParameter:NONE
//ReturnValue: NONE
/*************************************************************/
void WWDT_Int_Config(FunctionalStatus NewState)
{
if (NewState != DISABLE)
{
WWDT->ICR = WWDT_EVI;
WWDT->IMCR |= WWDT_EVI;
INTC_ISER_WRITE(WWDT_INT);
}
else
{
WWDT->IMCR &= ~WWDT_EVI; //CLR
INTC_ICER_WRITE(WWDT_INT);
}
}