250 lines
13 KiB
C
250 lines
13 KiB
C
/*
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******************************************************************************
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* @file apt32f102_i2c.h
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_i2c_H
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#define _apt32f102_i2c_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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#define BUFSIZE 32
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/******************************************************************************
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************************** I2C Structure Definition ***************************
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******************************************************************************/
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/**
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*******************************************************************************
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@brief description CSP_I2C_T and CSP_I2C_PTR
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*******************************************************************************
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*/
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/******************************************************************************
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************************** I2C Registers Definition ***************************
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******************************************************************************/
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/******************************************************************************
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* CR : I2C Control Register
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******************************************************************************/
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#define I2C_MASTER_EN (0x01ul << 0) /**< I2C Master Mode */
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#define I2C_MASTER_DIS (0x00ul << 0) /**< I2C Master Mode */
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#define I2C_SS (0x01ul << 1) /**< I2C Standard Speed Mode */
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#define I2C_FS (0x02ul << 1) /**< I2C Fast Speed Mode */
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#define I2C_HS (0x03ul << 1) /**< I2C High Speed Mode */
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#define I2C_10BIT_SLAVE (0x01ul << 3) /**< I2C 10bit or 7bit in Slave */
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#define I2C_7BIT_SLAVE (0x00ul << 3) /**< I2C 10bit or 7bit in Slave */
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#define I2C_10BIT_MASTER (0x01ul << 4) /**< I2C 10bit or 7bit in Master */
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#define I2C_7BIT_MASTER (0x00ul << 4) /**< I2C 10bit or 7bit in Master */
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#define I2C_RESTART_EN (0x01ul << 5) /**< I2C Restart Enable */
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#define I2C_RESTART_DIS (0x00ul << 5) /**< I2C Restart Disable */
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#define I2C_SLAVE_EN (0x00ul << 6) /**< I2C Slave Enable */
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#define I2C_SLAVE_DIS (0x01ul << 6) /**< I2C Slave Disable */
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#define I2C_STOPDET_IFADD (0x01ul << 7) /**< I2C STOPDET If Addressed */
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#define I2C_STOPDET_ALS (0x00ul << 7) /**< I2C STOPDET Always */
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#define I2C_TX_EMPTY_CTRL (0x01ul << 8) /**< I2C TX_EMPTY Control */
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#define I2C_TX_EMPTY_DONE (0x00ul << 8) /**< I2C TX_EMPTY and Send Done */
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#define I2C_RX_HOLD_CTRL (0x01ul << 9) /**< I2C Rx Hold Ctrl @FIFO Full */
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#define I2C_RX_HOLD_NONE (0x00ul << 9) /**< I2C Rx Hold None @FIFO Full */
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#define I2C_STOPDET_MM (0x01ul <<10) /**< I2C STOPDET only in Master */
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#define I2C_BUSCLR_EN (0x01ul <<11) /**< I2C Enable Bus Clear Feature*/
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#define I2C_BUSCLR_DIS (0x00ul <<11) /**< I2C Disable Bus Clear Feature*/
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/******************************************************************************
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* DATA_CMD : I2C Data and Command Register
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******************************************************************************/
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#define I2C_CMD_READ (0x01ul << 8) /**< I2C Read Command */
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#define I2C_CMD_WRITE (0x00ul << 8) /**< I2C Write Command */
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#define I2C_CMD_STOP (0x01ul << 9) /**< I2C Stop after this byte */
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#define I2C_CMD_NONESTOP (0x00ul << 9) /**< I2C None Stop When FIFO Empty or Not */
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#define I2C_CMD_RESTART0 (0x00ul <<10) /**< I2C Restart Mode0 */
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#define I2C_CMD_RESTART1 (0x01ul <<10) /**< I2C Restart Mode1 */
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//#define I2C_CMD_1stDATA (0x01ul <<11) /**< I2C First Data Byte */
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#define I2C_DATA(val) (((val) & 0xFFul) << 0) /**< Data Writing Macro */
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/*****************************************************************************
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* ENABLE : I2C Enable Register
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******************************************************************************/
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#define I2C_ENABLE (0x01ul << 0) /**< I2C Enable */
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#define I2C_DISABLE (0x00ul << 0) /**< I2C Enable */
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#define I2C_ABORT (0x01ul << 1) /**< I2C Abort Transfer */
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#define I2C_ABORT_OV (0x00ul << 1) /**< I2C Abort Transfer Over or No Abort */
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//#define I2C_TX_CMD_BLOCK (0x01ul << 2) /**< I2C Block Transmission */
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#define I2C_SDA_REC_EN (0x01ul << 3) /**< I2C Enable Stuck Recovery */
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#define I2C_SDA_REC_DIS (0x00ul << 3) /**< I2C Enable Stuck Recovery */
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/*****************************************************************************
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* STATUS : I2C STATUS Register
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******************************************************************************/
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#define I2C_BUSY (0x01ul << 0) /**< I2C Activity */
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#define I2C_FREE (0x00ul << 0) /**< I2C Activity */
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#define I2C_TFNF (0x01ul << 1) /**< I2C Transmit FIFO Not Full */
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#define I2C_TFNF_FULL (0x00ul << 1) /**< I2C Transmit FIFO Is Full */
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#define I2C_TFE (0x01ul << 2) /**< I2C Transmit FIFO Empty */
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#define I2C_TFE_NOT (0x00ul << 2) /**< I2C Transmit FIFO Not Empty */
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#define I2C_RFNE (0x01ul << 3) /**< I2C Receive FIFO Not Empty */
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#define I2C_RFNE_EMPTY (0x00ul << 3) /**< I2C Receive FIFO Is Empty */
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#define I2C_RFF (0x01ul << 4) /**< I2C Receive FIFO Full */
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#define I2C_MST_BUSY (0x01ul << 5) /**< I2C Master FSM Activity */
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#define I2C_MST_FREE (0x00ul << 5) /**< I2C Master FSM Free */
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#define I2C_SLV_BUSY (0x01ul << 6) /**< I2C Slave FSM Activity */
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#define I2C_SLV_FREE (0x01ul << 6) /**< I2C Slave FSM Free */
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#define I2C_REC_FREE (0x00ul << 6) /**< I2C Recovery No FAIL */
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#define I2C_REC_FAIL (0x01ul << 11) /**< I2C Recovery FAIL */
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/*****************************************************************************
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* RISR/MISR/IMSCR/ICR : I2C Interrupt Mask/Status Register
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******************************************************************************/
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#define I2C_RX_UNDER (0x01ul << 0) /**< I2C Interrupt Status */
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#define I2C_RX_OVER (0x01ul << 1) /**< I2C Interrupt Status */
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#define I2C_RX_FULL (0x01ul << 2) /**< I2C Interrupt Status */
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#define I2C_TX_OVER (0x01ul << 3) /**< I2C Interrupt Status */
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#define I2C_TX_EMPTY (0x01ul << 4) /**< I2C Interrupt Status */
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#define I2C_RD_REQ (0x01ul << 5) /**< I2C Interrupt Status */
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#define I2C_TX_ABRT (0x01ul << 6) /**< I2C Interrupt Status */
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#define I2C_RX_DONE (0x01ul << 7) /**< I2C Interrupt Status */
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#define I2C_INT_BUSY (0x01ul << 8) /**< I2C Interrupt Status */
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#define I2C_STOP_DET (0x01ul << 9) /**< I2C Interrupt Status */
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#define I2C_START_DET (0x01ul <<10) /**< I2C Interrupt Status */
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#define I2C_GEN_CALL (0x01ul <<11) /**< I2C Interrupt Status */
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#define I2C_RESTART_DET (0x01ul <<12) /**< I2C Interrupt Status */
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#define I2C_MST_ON_HOLD (0x01ul <<13) /**< I2C Interrupt Status */
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#define I2C_SCL_SLOW (0x01ul <<14) /**< I2C Interrupt Status */
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/*****************************************************************************
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* SDA_HOLD/SETUP : I2C SDA hold/setup Timing Register
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******************************************************************************/
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#define I2C_TX_HOLD(val) (((val) & 0xFFul) << 0) /**< SDA TX Hold Delay */
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#define I2C_RX_HOLD(val) (((val) & 0xFFul) <<16) /**< SDA RX Hold Delay */
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#define I2C_SETUP(val) (((val) & 0xFFul) << 0) /**< SDA Setup Delay */
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/*****************************************************************************
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* I2C_SPKLEN : I2C Burr Interference Filter Control Register
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******************************************************************************/
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#define I2C_SPKLEN(val) (((val) & 0xFFul) << 0) /**<I2C Burr interference filter control register */
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/*****************************************************************************
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* SCL/SDA TOUT : I2C SCL/SDA Stuck Time Out
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******************************************************************************/
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#define I2C_SCL_TOUT(val) (((val) & 0xFFFFFFFFul) << 0) /**<I2C SCL Stuck Time Out */
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#define I2C_SDA_TOUT(val) (((val) & 0xFFFFFFFFul) << 0) /**<I2C SDA Stuck Time Out */
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/*****************************************************************************
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* GCALL : I2C General Call Register
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******************************************************************************/
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#define I2C_GCALL_EN (0x01ul << 0) /**< I2C uses ACK to answer General Call */
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#define I2C_GCALL_DIS (0x00ul << 0) /**< I2C does not generate a General Call interrupt */
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/*****************************************************************************
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* NACK : I2C Slave NACK Control Register
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******************************************************************************/
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#define I2C_NACK_DATA (0x01ul << 0) /**< I2C Generate a NACK after the data byte is received */
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#define I2C_NACK_NORMAL (0x00ul << 0) /**< I2C Generate NACK/ACK as normal */
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/**
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* @brief I2C IO selection
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*/
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typedef enum
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{
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I2C_SDA_PA00= 0,
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I2C_SDA_PA03 = 1,
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I2C_SDA_PA07= 2,
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I2C_SDA_PA013= 3,
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I2C_SDA_PA014 = 4,
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}I2C_SDA_TypeDef;
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/**
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* @brief I2C IO selection
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*/
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typedef enum
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{
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I2C_SCL_PB00 = 0,
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I2C_SCL_PB02 = 1,
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I2C_SCL_PA01 = 2,
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I2C_SCL_PA04 = 3,
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I2C_SCL_PA06 = 4,
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I2C_SCL_PA015 = 5,
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}I2C_SCL_TypeDef;
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/**
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* @brief I2C MODE
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*/
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typedef enum
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{
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STANDARD_MODE = (0x01ul << 1),
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FAST_MODE=(0x02ul << 1),
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}I2C_SPEEDMODE_TypeDef;
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/**
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* @brief I2C SLAVE BIT
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*/
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typedef enum
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{
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I2C_SLAVE_7BIT= (0x00ul << 3),
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I2C_SLAVE_10BIT=(0x01ul << 3),
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}I2C_SLAVEBITS_TypeDef;
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/**
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* @brief I2C MASTER BITS
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*/
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typedef enum
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{
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I2C_MASTRER_7BIT= (0x00ul << 4),
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I2C_MASTRER_10BIT=(0x01ul << 4),
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}I2C_MASTRERBITS_TypeDef;
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/******************************************************************************
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********************* I2C External Functions Declaration **********************
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******************************************************************************/
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extern void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
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I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADD,U16_T SS_SCLH,U16_T SS_SCLL);
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extern void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
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I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX);
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extern void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD);
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extern void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE);
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extern void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL);
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extern void I2C_Stop(void);
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extern void I2C_Enable(void);
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extern void I2C_Disable(void);
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extern void I2C_Abort_EN(void);
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extern U8_T I2C_Abort_Status(void);
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extern void I2C_SDA_Recover_EN(void);
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extern void I2C_SDA_Recover_DIS(void);
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extern void I2C_Int_Enable(void);
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extern void I2C_Int_Disable(void);
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extern void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data);
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extern void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
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extern U8_T I2C_READ_Byte(U8_T read_adds);
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extern void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
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extern void I2C_Slave_Receive(void);
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extern void I2C_DeInit(void);
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extern volatile uint8_t I2CWrBuffer[BUFSIZE];
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extern volatile uint8_t I2CRdBuffer[BUFSIZE];
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extern volatile U8_T f_ERROR;
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extern void I2C_SLAVE_CONFIG(void);
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#endif /**< apt32f102_i2c_H */
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/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ |