commit 2dd675869accef720f455f762c0210d94afc083c Author: caocong Date: Mon Dec 15 20:48:52 2025 +0800 fix：修复调光时间BUG 解决调光时间一样的情况下，调光亮与调光灭的实际调光时间不一致问题 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..dc38a97 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +Objects/*.obj diff --git a/GPIO.c b/GPIO.c new file mode 100644 index 0000000..bb54f79 --- /dev/null +++ b/GPIO.c @@ -0,0 +1,71 @@ +#include "GPIO.h" + +//======================================================================== +// : u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) +// : ʼIO. +// : GPIOx: ṹ,οtimer.hĶ. +// : ɹ0, ղ1,󷵻2. +// 汾: V1.0, 2012-10-22 +//======================================================================== +u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) +{ + if(GPIO > GPIO_P7) return 1; //ղ + if(GPIOx->Mode > GPIO_OUT_PP) return 2; // + if(GPIO == GPIO_P0) + { + if(GPIOx->Mode == GPIO_PullUp) P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P1) + { + if(GPIOx->Mode == GPIO_PullUp) P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P2) + { + if(GPIOx->Mode == GPIO_PullUp) P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P3) + { + if(GPIOx->Mode == GPIO_PullUp) P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P4) + { + if(GPIOx->Mode == GPIO_PullUp) P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P5) + { + if(GPIOx->Mode == GPIO_PullUp) P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P6) + { + if(GPIOx->Mode == GPIO_PullUp) P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; // + } + if(GPIO == GPIO_P7) + { + if(GPIOx->Mode == GPIO_PullUp) P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; //׼˫ + if(GPIOx->Mode == GPIO_HighZ) P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // + if(GPIOx->Mode == GPIO_OUT_OD) P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; //© + if(GPIOx->Mode == GPIO_OUT_PP) P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; // + } + return 0; //ɹ +} diff --git a/GPIO.h b/GPIO.h new file mode 100644 index 0000000..6345ba8 --- /dev/null +++ b/GPIO.h @@ -0,0 +1,41 @@ + +#ifndef __GPIO_H +#define __GPIO_H + +#include "config.h" + +#define GPIO_PullUp 0 //׼˫ +#define GPIO_HighZ 1 // +#define GPIO_OUT_OD 2 //© +#define GPIO_OUT_PP 3 // + +#define GPIO_Pin_0 0x01 //IO Px.0 +#define GPIO_Pin_1 0x02 //IO Px.1 +#define GPIO_Pin_2 0x04 //IO Px.2 +#define GPIO_Pin_3 0x08 //IO Px.3 +#define GPIO_Pin_4 0x10 //IO Px.4 +#define GPIO_Pin_5 0x20 //IO Px.5 +#define GPIO_Pin_6 0x40 //IO Px.6 +#define GPIO_Pin_7 0x80 //IO Px.7 +#define GPIO_Pin_All 0xFF //IO +#define GPIO_Pin_Left 0x0F //IO1,2,3,4 + +#define GPIO_P0 0 +#define GPIO_P1 1 +#define GPIO_P2 2 +#define GPIO_P3 3 +#define GPIO_P4 4 +#define GPIO_P5 5 +#define GPIO_P6 6 +#define GPIO_P7 7 + + +typedef struct +{ + u8 Mode; //IOģʽ, GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + u8 Pin; //ҪõĶ˿ +} GPIO_InitTypeDef; + +u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx); + +#endif diff --git a/Listings/BLV_C12_Dimm_V19.m51 b/Listings/BLV_C12_Dimm_V19.m51 new file mode 100644 index 0000000..b27009c --- /dev/null +++ b/Listings/BLV_C12_Dimm_V19.m51 @@ -0,0 +1,2652 @@ +BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 1 + + +BL51 BANKED LINKER/LOCATER V6.22, INVOKED BY: +D:\KEIL_V5\C51\BIN\BL51.EXE .\Objects\GPIO.obj, .\Objects\main.obj, .\Objects\UART.obj, .\Objects\UART_Set.obj, .\Object +>> s\pwm_control.obj, .\Objects\Start_Init.obj, .\Objects\PWM15bit.obj, .\Objects\timer.obj, .\Objects\key.obj, .\Object +>> s\WDT.obj TO .\Objects\BLV_C12_Dimm_V19 PRINT (.\Listings\BLV_C12_Dimm_V19.m51) RAMSIZE (256) + + +MEMORY MODEL: SMALL WITH FLOATING POINT ARITHMETIC + + +INPUT MODULES INCLUDED: + .\Objects\GPIO.obj (GPIO) + .\Objects\main.obj (MAIN) + .\Objects\UART.obj (UART) + .\Objects\UART_Set.obj (UART_SET) + .\Objects\pwm_control.obj (PWM_CONTROL) + .\Objects\Start_Init.obj (START_INIT) + .\Objects\PWM15bit.obj (PWM15BIT) + .\Objects\timer.obj (TIMER) + .\Objects\key.obj (KEY) + .\Objects\WDT.obj (WDT) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?FPADD) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?FPDIV) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?FPCMP) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?FCAST) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?CASTF) + D:\KEIL_V5\C51\LIB\C51FPS.LIB (?C?FPGETOPN) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C_STARTUP) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDPTR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDOPTR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?IILDX) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ILDOPTR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LMUL) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ULDIV) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LNEG) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ULCMP) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ULSHR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LLDOPTR0) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LSTXDATA) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LSTKXDATA) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?OFFXADD) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LIMUL) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?MEMSET) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C_INIT) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LLDIDATA0) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LLDXDATA0) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LLDPDATA0) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?LLDCODE0) + + +LINK MAP OF MODULE: .\Objects\BLV_C12_Dimm_V19 (GPIO) + + + TYPE BASE LENGTH RELOCATION SEGMENT NAME + ----------------------------------------------------- + + * * * * * * * D A T A M E M O R Y * * * * * * * + REG 0000H 0008H ABSOLUTE "REG BANK 0" + DATA 0008H 0015H UNIT _DATA_GROUP_ + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 2 + + + DATA 001DH 0014H UNIT ?DT?UART + DATA 0031H 000AH UNIT ?DT?KEY + DATA 003BH 0008H UNIT ?DT?PWM_CONTROL + DATA 0043H 0004H UNIT ?DT?TIMER + DATA 0047H 0003H UNIT ?DT?_PRINTBUFFER1?UART + DATA 004AH 0001H UNIT ?DT?MAIN + DATA 004BH 0001H UNIT ?DT?UART_SET + IDATA 004CH 0001H UNIT ?STACK + + * * * * * * * X D A T A M E M O R Y * * * * * * * + XDATA 0000H 0110H UNIT ?XD?UART_SET + XDATA 0110H 00F1H UNIT ?XD?PWM_CONTROL + XDATA 0201H 0080H UNIT ?XD?UART + + * * * * * * * C O D E M E M O R Y * * * * * * * + CODE 0000H 0003H ABSOLUTE + CODE 0003H 0004H UNIT ?PR?WDT_CLEAR?WDT + CODE 0007H 0003H UNIT ?PR?TIMER0_INT?TIMER + CODE 000AH 0001H UNIT ?PR?TIMER3_INT?TIMER + CODE 000BH 0003H ABSOLUTE + CODE 000EH 000AH UNIT ?CO?MAIN + CODE 0018H 0003H UNIT ?PR?TIMER1_INT?TIMER + CODE 001BH 0003H ABSOLUTE + CODE 001EH 0003H UNIT ?PR?TIMER4_INT?TIMER + 0021H 0002H *** GAP *** + CODE 0023H 0003H ABSOLUTE + CODE 0026H 0031H UNIT ?PR?PWM0_HANDLER?PWM15BIT + 0057H 000CH *** GAP *** + CODE 0063H 0003H ABSOLUTE + CODE 0066H 0024H UNIT ?PR?_TX3_WRITE2BUFF?UART + 008AH 0001H *** GAP *** + CODE 008BH 0003H ABSOLUTE + 008EH 000DH *** GAP *** + CODE 009BH 0003H ABSOLUTE + 009EH 0005H *** GAP *** + CODE 00A3H 0003H ABSOLUTE + 00A6H 000DH *** GAP *** + CODE 00B3H 0003H ABSOLUTE + CODE 00B6H 002BH UNIT ?C_INITSEG + 00E1H 0002H *** GAP *** + CODE 00E3H 0003H ABSOLUTE + 00E6H 0005H *** GAP *** + CODE 00EBH 0003H ABSOLUTE + 00EEH 0005H *** GAP *** + CODE 00F3H 0003H ABSOLUTE + 00F6H 0005H *** GAP *** + CODE 00FBH 0003H ABSOLUTE + CODE 00FEH 0FD8H UNIT ?PR?USART_DEAL_DATA?UART_SET + CODE 10D6H 0753H UNIT ?PR?DEAL_COMMAND2?PWM_CONTROL + CODE 1829H 05AFH UNIT ?C?LIB_CODE + CODE 1DD8H 0482H UNIT ?PR?DEAL_COMMAND1?PWM_CONTROL + CODE 225AH 035BH UNIT ?PR?_UART_CONFIGURATION?UART + CODE 25B5H 02F3H UNIT ?PR?_TIMER_INILIZE?TIMER + CODE 28A8H 0254H UNIT ?PR?_GPIO_INILIZE?GPIO + CODE 2AFCH 01B8H UNIT ?PR?_PWM15_INIT?PWM15BIT + CODE 2CB4H 018DH UNIT ?PR?USART_ANSWER?UART_SET + CODE 2E41H 0180H UNIT ?CO?PWM15BIT + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 3 + + + CODE 2FC1H 0178H UNIT ?PR?PWM_CONFIG?PWM_CONTROL + CODE 3139H 013BH UNIT ?PR?KEY_TEST?KEY + CODE 3274H 00E0H UNIT ?PR?USART_JUDGE_DATA?UART_SET + CODE 3354H 00CFH UNIT ?PR?KEY_SCANTASK?KEY + CODE 3423H 009AH UNIT ?PR?_PWM_WRITE?PWM_CONTROL + CODE 34BDH 008CH UNIT ?PR?UART1_INT?UART + CODE 3549H 008CH UNIT ?C_C51STARTUP + CODE 35D5H 0087H UNIT ?PR?START_INIT?START_INIT + CODE 365CH 007EH UNIT ?PR?UART3_INT?UART + CODE 36DAH 0078H UNIT ?PR?_PWMCHANNELCTRL?PWM15BIT + CODE 3752H 006AH UNIT ?PR?_QPWM15DUTY?PWM15BIT + CODE 37BCH 0066H UNIT ?PR?SHOW_LIGHT?PWM_CONTROL + CODE 3822H 0065H UNIT ?PR?MAIN?MAIN + CODE 3887H 0065H UNIT ?CO?UART_SET + CODE 38ECH 005EH UNIT ?PR?_OPEN_LIGHT?PWM_CONTROL + CODE 394AH 0054H UNIT ?PR?_PWM15DUTY?PWM15BIT + CODE 399EH 0043H UNIT ?PR?GPIO_CONFIG?PWM_CONTROL + CODE 39E1H 003FH UNIT ?PR?_PWMLEVELSET?PWM15BIT + CODE 3A20H 0031H UNIT ?PR?PWM1_HANDLER?PWM15BIT + CODE 3A51H 0031H UNIT ?PR?PWM2_HANDLER?PWM15BIT + CODE 3A82H 0031H UNIT ?PR?PWM3_HANDLER?PWM15BIT + CODE 3AB3H 0031H UNIT ?PR?PWM4_HANDLER?PWM15BIT + CODE 3AE4H 002AH UNIT ?PR?_SUMFUNC?UART_SET + CODE 3B0EH 0029H UNIT ?PR?UART1_CONFIG?MAIN + CODE 3B37H 0029H UNIT ?PR?_WDT_INILIZE?WDT + CODE 3B60H 0028H UNIT ?PR?UART3_CONFIG?UART + CODE 3B88H 0026H UNIT ?PR?_PRINTBUFFER3?UART + CODE 3BAEH 0023H UNIT ?PR?_TX1_WRITE2BUFF?UART + CODE 3BD1H 0023H UNIT ?PR?_PRINTBUFFER1?UART + CODE 3BF4H 0021H UNIT ?PR?TIMER2_INIT_1MS?START_INIT + CODE 3C15H 001FH UNIT ?PR?KEY_INIT?KEY + CODE 3C34H 001EH UNIT ?PR?TIMER2_INT?TIMER + CODE 3C52H 0014H UNIT ?PR?_CLOSE_LIGHT?PWM_CONTROL + CODE 3C66H 0013H UNIT ?PR?_PRINTSTRING1?UART + CODE 3C79H 0013H UNIT ?PR?_PRINTSTRING3?UART + CODE 3C8CH 0011H UNIT ?PR?WDT_CONFIG?MAIN + CODE 3C9DH 0010H UNIT ?PR?GPIO1_CONFIG?MAIN + + + +OVERLAY MAP OF MODULE: .\Objects\BLV_C12_Dimm_V19 (GPIO) + + +SEGMENT DATA_GROUP + +--> CALLED SEGMENT START LENGTH +------------------------------------------------------ +?C_C51STARTUP ----- ----- + +--> ?PR?MAIN?MAIN + +--> ?C_INITSEG + +?PR?MAIN?MAIN ----- ----- + +--> ?PR?GPIO_CONFIG?PWM_CONTROL + +--> ?PR?UART3_CONFIG?UART + +--> ?PR?START_INIT?START_INIT + +--> ?PR?PWM_CONFIG?PWM_CONTROL + +--> ?PR?TIMER2_INIT_1MS?START_INIT + +--> ?PR?KEY_INIT?KEY + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 4 + + + +--> ?PR?GPIO1_CONFIG?MAIN + +--> ?PR?UART1_CONFIG?MAIN + +--> ?PR?WDT_CONFIG?MAIN + +--> ?CO?MAIN + +--> ?PR?_PRINTSTRING1?UART + +--> ?PR?WDT_CLEAR?WDT + +--> ?PR?USART_JUDGE_DATA?UART_SET + +--> ?PR?USART_DEAL_DATA?UART_SET + +--> ?PR?DEAL_COMMAND1?PWM_CONTROL + +--> ?PR?DEAL_COMMAND2?PWM_CONTROL + +--> ?PR?SHOW_LIGHT?PWM_CONTROL + +--> ?PR?USART_ANSWER?UART_SET + +--> ?PR?KEY_SCANTASK?KEY + +--> ?PR?KEY_TEST?KEY + +?PR?GPIO_CONFIG?PWM_CONTROL 0008H 0002H + +--> ?PR?_GPIO_INILIZE?GPIO + +?PR?UART3_CONFIG?UART 0008H 000CH + +--> ?PR?_UART_CONFIGURATION?UART + +?PR?_UART_CONFIGURATION?UART 0014H 0009H + +?PR?PWM_CONFIG?PWM_CONTROL 0008H 0007H + +--> ?PR?_PWM15_INIT?PWM15BIT + +--> ?PR?_PWM15DUTY?PWM15BIT + +--> ?PR?_PWMCHANNELCTRL?PWM15BIT + +?PR?_PWM15DUTY?PWM15BIT ----- ----- + +--> ?CO?PWM15BIT + +?PR?_PWMCHANNELCTRL?PWM15BIT 000FH 0006H + +--> ?CO?PWM15BIT + +?PR?TIMER2_INIT_1MS?START_INIT 0008H 0008H + +--> ?PR?_TIMER_INILIZE?TIMER + +?PR?KEY_INIT?KEY 0008H 0002H + +--> ?PR?_GPIO_INILIZE?GPIO + +?PR?GPIO1_CONFIG?MAIN 0008H 0002H + +--> ?PR?_GPIO_INILIZE?GPIO + +?PR?UART1_CONFIG?MAIN 0008H 000CH + +--> ?PR?_UART_CONFIGURATION?UART + +?PR?WDT_CONFIG?MAIN 0008H 0003H + +--> ?PR?_WDT_INILIZE?WDT + +?PR?_PRINTSTRING1?UART ----- ----- + +--> ?PR?_TX1_WRITE2BUFF?UART + +?PR?USART_JUDGE_DATA?UART_SET 0008H 0002H + +?PR?USART_DEAL_DATA?UART_SET 0008H 0001H + +--> ?CO?UART_SET + +--> ?PR?_PRINTSTRING1?UART + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 5 + + + +--> ?PR?_OPEN_LIGHT?PWM_CONTROL + +--> ?PR?_CLOSE_LIGHT?PWM_CONTROL + +?PR?_OPEN_LIGHT?PWM_CONTROL 0009H 0001H + +?PR?DEAL_COMMAND1?PWM_CONTROL 0008H 0002H + +?PR?DEAL_COMMAND2?PWM_CONTROL 0008H 0002H + +?PR?SHOW_LIGHT?PWM_CONTROL 0008H 0002H + +--> ?PR?_CLOSE_LIGHT?PWM_CONTROL + +--> ?PR?_PWM_WRITE?PWM_CONTROL + +?PR?_PWM_WRITE?PWM_CONTROL 000AH 0002H + +--> ?PR?_PWM15DUTY?PWM15BIT + +?PR?USART_ANSWER?UART_SET 0008H 0001H + +--> ?PR?_SUMFUNC?UART_SET + +--> ?PR?_PRINTBUFFER3?UART + +--> ?CO?UART_SET + +--> ?PR?_PRINTSTRING1?UART + +?PR?_SUMFUNC?UART_SET 0009H 0003H + +?PR?_PRINTBUFFER3?UART 0009H 0003H + +--> ?PR?_TX3_WRITE2BUFF?UART + + + +SYMBOL TABLE OF MODULE: .\Objects\BLV_C12_Dimm_V19 (GPIO) + + VALUE TYPE NAME + ---------------------------------- + + ------- MODULE GPIO + C:0000H SYMBOL _ICE_DUMMY_ + D:0093H PUBLIC P0M1 + D:0092H PUBLIC P1M0 + D:0096H PUBLIC P2M0 + D:0091H PUBLIC P1M1 + D:0080H PUBLIC P0 + D:00B2H PUBLIC P3M0 + D:0095H PUBLIC P2M1 + D:0090H PUBLIC P1 + D:00B4H PUBLIC P4M0 + D:00B1H PUBLIC P3M1 + D:00A0H PUBLIC P2 + D:00CAH PUBLIC P5M0 + D:00B3H PUBLIC P4M1 + D:00B0H PUBLIC P3 + D:00CCH PUBLIC P6M0 + D:00C9H PUBLIC P5M1 + D:00C0H PUBLIC P4 + D:00E2H PUBLIC P7M0 + D:00CBH PUBLIC P6M1 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 6 + + + D:00E1H PUBLIC P7M1 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + C:28A8H PUBLIC _GPIO_Inilize + D:00D0H PUBLIC PSW + D:0094H PUBLIC P0M0 + ------- PROC _GPIO_INILIZE + D:0007H SYMBOL GPIO + D:0001H SYMBOL GPIOx + C:28A8H LINE# 10 + C:28A8H LINE# 11 + C:28A8H LINE# 12 + C:28B1H LINE# 13 + C:28BDH LINE# 14 + C:28C0H LINE# 15 + C:28C0H LINE# 16 + C:28CEH LINE# 17 + C:28DFH LINE# 18 + C:28F0H LINE# 19 + C:2901H LINE# 20 + C:2901H LINE# 21 + C:2906H LINE# 22 + C:2906H LINE# 23 + C:2917H LINE# 24 + C:2926H LINE# 25 + C:2936H LINE# 26 + C:2949H LINE# 27 + C:2949H LINE# 28 + C:294EH LINE# 29 + C:294EH LINE# 30 + C:295FH LINE# 31 + C:296EH LINE# 32 + C:297EH LINE# 33 + C:2991H LINE# 34 + C:2991H LINE# 35 + C:2996H LINE# 36 + C:2996H LINE# 37 + C:29A7H LINE# 38 + C:29B6H LINE# 39 + C:29C6H LINE# 40 + C:29D9H LINE# 41 + C:29D9H LINE# 42 + C:29DEH LINE# 43 + C:29DEH LINE# 44 + C:29EFH LINE# 45 + C:29FEH LINE# 46 + C:2A0EH LINE# 47 + C:2A21H LINE# 48 + C:2A21H LINE# 49 + C:2A26H LINE# 50 + C:2A26H LINE# 51 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 7 + + + C:2A37H LINE# 52 + C:2A46H LINE# 53 + C:2A56H LINE# 54 + C:2A69H LINE# 55 + C:2A69H LINE# 56 + C:2A6EH LINE# 57 + C:2A6EH LINE# 58 + C:2A7FH LINE# 59 + C:2A8EH LINE# 60 + C:2A9EH LINE# 61 + C:2AB1H LINE# 62 + C:2AB1H LINE# 63 + C:2AB6H LINE# 64 + C:2AB6H LINE# 65 + C:2AC7H LINE# 66 + C:2AD6H LINE# 67 + C:2AE6H LINE# 68 + C:2AF9H LINE# 69 + C:2AF9H LINE# 70 + C:2AFBH LINE# 71 + ------- ENDPROC _GPIO_INILIZE + ------- ENDMOD GPIO + + ------- MODULE MAIN + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + B:00A8H.7 PUBLIC EA + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + C:3822H PUBLIC main + D:004AH PUBLIC count_flag + B:0090H.0 PUBLIC P10 + D:0087H PUBLIC PCON + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + C:3C9DH PUBLIC GPIO1_config + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + C:3B0EH PUBLIC UART1_config + C:3C8CH PUBLIC WDT_config + D:00FFH PUBLIC RSTCFG + D:00D0H PUBLIC PSW + ------- PROC GPIO1_CONFIG + ------- DO + D:0008H SYMBOL GPIO_InitStructure + ------- ENDDO + C:3C9DH LINE# 28 + C:3C9DH LINE# 29 + C:3C9DH LINE# 32 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 8 + + + C:3CA0H LINE# 33 + C:3CA3H LINE# 34 + ------- ENDPROC GPIO1_CONFIG + ------- PROC UART1_CONFIG + ------- DO + D:0008H SYMBOL COMx_InitStructure + ------- ENDDO + C:3B0EH LINE# 38 + C:3B0EH LINE# 39 + C:3B0EH LINE# 41 + C:3B11H LINE# 42 + C:3B14H LINE# 43 + C:3B20H LINE# 44 + C:3B23H LINE# 45 + C:3B26H LINE# 46 + C:3B29H LINE# 47 + C:3B2BH LINE# 48 + C:3B2DH LINE# 49 + ------- ENDPROC UART1_CONFIG + ------- PROC WDT_CONFIG + ------- DO + D:0008H SYMBOL WDT_InitStructure + ------- ENDDO + C:3C8CH LINE# 55 + C:3C8CH LINE# 56 + C:3C8CH LINE# 59 + C:3C8FH LINE# 60 + C:3C92H LINE# 61 + C:3C95H LINE# 62 + ------- ENDPROC WDT_CONFIG + ------- PROC MAIN + C:3822H LINE# 66 + C:3822H LINE# 67 + C:3822H LINE# 68 + C:3825H LINE# 69 + C:3828H LINE# 70 + C:382BH LINE# 71 + C:382EH LINE# 72 + C:3831H LINE# 73 + C:3834H LINE# 74 + C:3837H LINE# 75 + C:383AH LINE# 76 + C:383DH LINE# 78 + C:3840H LINE# 79 + C:3843H LINE# 80 + C:3845H LINE# 82 + C:3849H LINE# 83 + C:3849H LINE# 84 + C:3852H LINE# 85 + C:3852H LINE# 87 + C:3852H LINE# 88 + C:3852H LINE# 89 + C:3855H LINE# 90 + C:3857H LINE# 93 + C:385CH LINE# 94 + C:385CH LINE# 95 + C:385EH LINE# 96 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 9 + + + C:385EH LINE# 97 + C:3863H LINE# 98 + C:3863H LINE# 99 + C:3865H LINE# 100 + C:3865H LINE# 101 + C:386AH LINE# 102 + C:386AH LINE# 103 + C:386DH LINE# 104 + C:386DH LINE# 106 + C:3870H LINE# 108 + C:3873H LINE# 110 + C:3876H LINE# 112 + C:3879H LINE# 116 + C:387CH LINE# 118 + C:387FH LINE# 120 + C:3882H LINE# 122 + C:3885H LINE# 124 + ------- ENDPROC MAIN + ------- ENDMOD MAIN + + ------- MODULE UART + C:0000H SYMBOL _ICE_DUMMY_ + C:225AH PUBLIC _UART_Configuration + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A2H PUBLIC P_SW1 + D:00BAH PUBLIC P_SW2 + D:00A8H PUBLIC IE + D:001EH PUBLIC COM1 + D:0025H PUBLIC COM3 + D:00EEH PUBLIC IP3H + B:00A8H.4 PUBLIC ES + D:00B8H PUBLIC IP + X:0201H PUBLIC RX1_Buffer + B:0098H.0 PUBLIC RI + C:34BDH PUBLIC UART1_int + X:0221H PUBLIC RX3_Buffer + X:0241H PUBLIC TX1_Buffer + B:0098H.1 PUBLIC TI + C:365CH PUBLIC UART3_int + X:0261H PUBLIC TX3_Buffer + B:00B8H.4 PUBLIC PS + D:00D8H PUBLIC CCON + D:0099H PUBLIC SBUF + D:0087H PUBLIC PCON + D:0098H PUBLIC SCON + D:0089H PUBLIC TMOD + D:0088H PUBLIC TCON + C:3C66H PUBLIC _PrintString1 + C:3C79H PUBLIC _PrintString3 + C:3BD1H PUBLIC _Printbuffer1 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 10 + + + D:00AFH PUBLIC IE2 + D:002CH PUBLIC recv_start_flag + D:00F0H PUBLIC B + D:008EH PUBLIC AUXR + C:3B88H PUBLIC _Printbuffer3 + D:00C7H PUBLIC IAP_CONTR + D:002DH PUBLIC recv_time + C:3BAEH PUBLIC _TX1_write2buff + C:0066H PUBLIC _TX3_write2buff + D:00E0H PUBLIC ACC + B:00A8H.3 PUBLIC ET1 + C:3B60H PUBLIC UART3_config + D:00DFH PUBLIC IP3 + D:008DH PUBLIC TH1 + D:00D6H PUBLIC TH2 + D:00D4H PUBLIC TH3 + D:008BH PUBLIC TL1 + D:00D7H PUBLIC TL2 + D:00D5H PUBLIC TL3 + B:0088H.6 PUBLIC TR1 + D:00D1H PUBLIC T4T3M + D:00B7H PUBLIC IPH + D:00ADH PUBLIC S3BUF + B:0098H.4 PUBLIC REN + D:00ACH PUBLIC S3CON + D:008FH PUBLIC INT_CLKO + D:00D0H PUBLIC PSW + ------- PROC _UART_CONFIGURATION + D:0014H SYMBOL UARTx + D:0015H SYMBOL COMx + ------- DO + D:0018H SYMBOL i + D:0019H SYMBOL j + ------- ENDDO + C:225AH LINE# 37 + C:2262H LINE# 38 + C:2262H LINE# 43 + C:226BH LINE# 44 + C:226BH LINE# 45 + C:226EH LINE# 46 + C:2270H LINE# 47 + C:2272H LINE# 48 + C:2274H LINE# 49 + C:2276H LINE# 50 + C:2278H LINE# 51 + C:227AH LINE# 52 + C:2290H LINE# 53 + C:22A7H LINE# 55 + C:22BCH LINE# 56 + C:22EAH LINE# 57 + C:22F5H LINE# 58 + C:2300H LINE# 59 + C:230DH LINE# 60 + C:230DH LINE# 61 + C:2326H LINE# 62 + C:233DH LINE# 63 + C:2353H LINE# 64 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 11 + + + C:2364H LINE# 65 + C:2364H LINE# 66 + C:2366H LINE# 67 + C:2369H LINE# 68 + C:236CH LINE# 69 + C:236FH LINE# 70 + C:2372H LINE# 71 + C:2381H LINE# 72 + C:2384H LINE# 73 + C:2386H LINE# 74 + C:2389H LINE# 75 + C:238CH LINE# 76 + C:238EH LINE# 77 + C:2390H LINE# 78 + C:2395H LINE# 79 + C:2395H LINE# 80 + C:2398H LINE# 81 + C:239BH LINE# 82 + C:239EH LINE# 83 + C:23A1H LINE# 84 + C:23B0H LINE# 85 + C:23B3H LINE# 86 + C:23B6H LINE# 87 + C:23B9H LINE# 88 + C:23BBH LINE# 89 + C:23BEH LINE# 90 + C:23BEH LINE# 91 + C:23CAH LINE# 92 + C:23CAH LINE# 93 + C:23D8H LINE# 94 + C:23DBH LINE# 95 + C:23DDH LINE# 96 + C:23E1H LINE# 97 + C:23E1H LINE# 98 + C:23EFH LINE# 99 + C:23F2H LINE# 100 + C:23F2H LINE# 101 + C:2405H LINE# 102 + C:2407H LINE# 103 + C:2414H LINE# 104 + C:2416H LINE# 105 + C:2426H LINE# 106 + C:2429H LINE# 107 + C:2429H LINE# 149 + C:2432H LINE# 150 + C:2432H LINE# 151 + C:2435H LINE# 152 + C:2437H LINE# 153 + C:2439H LINE# 154 + C:243BH LINE# 155 + C:243DH LINE# 156 + C:243FH LINE# 157 + C:2441H LINE# 158 + C:2457H LINE# 159 + C:246EH LINE# 161 + C:2484H LINE# 162 + C:2484H LINE# 163 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 12 + + + C:2493H LINE# 164 + C:24C5H LINE# 165 + C:24D0H LINE# 166 + C:24D3H LINE# 167 + C:24ECH LINE# 168 + C:2503H LINE# 169 + C:2519H LINE# 170 + C:2529H LINE# 171 + C:2529H LINE# 172 + C:252CH LINE# 173 + C:253BH LINE# 174 + C:253EH LINE# 175 + C:2541H LINE# 176 + C:2544H LINE# 177 + C:2546H LINE# 178 + C:254BH LINE# 179 + C:254BH LINE# 180 + C:254EH LINE# 181 + C:2551H LINE# 182 + C:2554H LINE# 183 + C:2557H LINE# 184 + C:2566H LINE# 185 + C:2569H LINE# 186 + C:256CH LINE# 187 + C:256FH LINE# 188 + C:2571H LINE# 189 + C:2574H LINE# 190 + C:2574H LINE# 191 + C:2577H LINE# 192 + C:258BH LINE# 193 + C:258EH LINE# 194 + C:259CH LINE# 195 + C:259FH LINE# 196 + C:25AFH LINE# 197 + C:25B2H LINE# 198 + C:25B2H LINE# 252 + C:25B4H LINE# 253 + ------- ENDPROC _UART_CONFIGURATION + ------- PROC _TX1_WRITE2BUFF + D:0007H SYMBOL dat + C:3BAEH LINE# 259 + C:3BAEH LINE# 260 + C:3BAEH LINE# 261 + C:3BBBH LINE# 262 + C:3BC7H LINE# 264 + C:3BCBH LINE# 265 + C:3BCBH LINE# 266 + C:3BCEH LINE# 267 + C:3BD0H LINE# 268 + C:3BD0H LINE# 269 + ------- ENDPROC _TX1_WRITE2BUFF + ------- PROC _PRINTSTRING1 + D:0001H SYMBOL puts + C:3C66H LINE# 271 + C:3C66H LINE# 272 + C:3C66H LINE# 273 + C:3C78H LINE# 274 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 13 + + + ------- ENDPROC _PRINTSTRING1 + ------- PROC _PRINTBUFFER1 + D:0047H SYMBOL puts + D:0005H SYMBOL len + ------- DO + D:0006H SYMBOL i + ------- ENDDO + C:3BD1H LINE# 275 + C:3BD7H LINE# 276 + C:3BD7H LINE# 278 + C:3BF3H LINE# 279 + ------- ENDPROC _PRINTBUFFER1 + ------- PROC UART1_INT + ------- DO + D:001DH SYMBOL stage + D:0007H SYMBOL dat + ------- ENDDO + C:34BDH LINE# 283 + C:34CAH LINE# 287 + C:34CDH LINE# 288 + C:34CDH LINE# 289 + C:34CFH LINE# 290 + C:34D2H LINE# 291 + C:34DEH LINE# 293 + C:34E2H LINE# 294 + C:34E2H LINE# 295 + C:34E4H LINE# 296 + C:34EEH LINE# 297 + C:34F1H LINE# 298 + C:34F1H LINE# 299 + C:34F3H LINE# 300 + C:34F5H LINE# 302 + C:34F5H LINE# 303 + C:34F8H LINE# 304 + C:34F8H LINE# 305 + C:34FDH LINE# 306 + C:34FDH LINE# 307 + C:3500H LINE# 308 + C:3500H LINE# 309 + C:3511H LINE# 310 + C:3514H LINE# 311 + C:3514H LINE# 312 + C:3514H LINE# 314 + C:3517H LINE# 315 + C:3517H LINE# 316 + C:3519H LINE# 317 + C:351FH LINE# 318 + C:351FH LINE# 319 + C:352DH LINE# 320 + C:3539H LINE# 321 + C:353BH LINE# 322 + C:353EH LINE# 323 + C:353EH LINE# 324 + ------- ENDPROC UART1_INT + ------- PROC _TX3_WRITE2BUFF + D:0007H SYMBOL dat + C:0066H LINE# 374 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 14 + + + C:0066H LINE# 375 + C:0066H LINE# 376 + C:0073H LINE# 377 + C:007FH LINE# 379 + C:0083H LINE# 380 + C:0083H LINE# 381 + C:0086H LINE# 382 + C:0089H LINE# 383 + C:0089H LINE# 384 + ------- ENDPROC _TX3_WRITE2BUFF + ------- PROC _PRINTSTRING3 + D:0001H SYMBOL puts + C:3C79H LINE# 386 + C:3C79H LINE# 387 + C:3C79H LINE# 388 + C:3C8BH LINE# 389 + ------- ENDPROC _PRINTSTRING3 + ------- PROC _PRINTBUFFER3 + D:0009H SYMBOL puts + D:0005H SYMBOL len + ------- DO + D:0006H SYMBOL i + ------- ENDDO + C:3B88H LINE# 391 + C:3B8EH LINE# 392 + C:3B8EH LINE# 394 + C:3BADH LINE# 395 + ------- ENDPROC _PRINTBUFFER3 + ------- PROC UART3_INT + C:365CH LINE# 397 + C:3669H LINE# 399 + C:366EH LINE# 400 + C:366EH LINE# 401 + C:3671H LINE# 402 + C:367DH LINE# 403 + C:3680H LINE# 404 + C:3684H LINE# 405 + C:3684H LINE# 406 + C:368EH LINE# 407 + C:369FH LINE# 408 + C:36A2H LINE# 409 + C:36A2H LINE# 410 + C:36A2H LINE# 412 + C:36A7H LINE# 413 + C:36A7H LINE# 414 + C:36AAH LINE# 415 + C:36B0H LINE# 416 + C:36B0H LINE# 417 + C:36BEH LINE# 418 + C:36CAH LINE# 419 + C:36CCH LINE# 420 + C:36CFH LINE# 421 + C:36CFH LINE# 422 + ------- ENDPROC UART3_INT + ------- PROC UART3_CONFIG + ------- DO + D:0008H SYMBOL COMx_InitStructure + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 15 + + + ------- ENDDO + C:3B60H LINE# 471 + C:3B60H LINE# 472 + C:3B60H LINE# 474 + C:3B63H LINE# 475 + C:3B66H LINE# 476 + C:3B72H LINE# 477 + C:3B75H LINE# 478 + C:3B78H LINE# 479 + C:3B7BH LINE# 480 + C:3B7EH LINE# 481 + ------- ENDPROC UART3_CONFIG + ------- ENDMOD UART + + ------- MODULE UART_SET + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + C:3AE4H PUBLIC _sumfunc + X:0000H PUBLIC s_recv + D:00E8H PUBLIC P6 + C:2CB4H PUBLIC Usart_answer + D:00F8H PUBLIC P7 + D:004BH PUBLIC debug + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + D:00F0H PUBLIC B + C:00FEH PUBLIC Usart_Deal_Data + D:00E0H PUBLIC ACC + X:00C6H PUBLIC g_Usart + X:00E9H PUBLIC g_answer + C:3274H PUBLIC Usart_judge_Data + D:00D0H PUBLIC PSW + ------- PROC USART_JUDGE_DATA + ------- DO + D:0008H SYMBOL len + D:0007H SYMBOL i + D:0009H SYMBOL sum + ------- ENDDO + C:3274H LINE# 20 + C:3274H LINE# 21 + C:3274H LINE# 22 + C:3277H LINE# 24 + C:3279H LINE# 25 + C:327DH LINE# 27 + C:32AAH LINE# 28 + C:32AAH LINE# 29 + C:32ADH LINE# 40 + C:32ADH LINE# 41 + C:32B0H LINE# 42 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 16 + + + C:32B7H LINE# 43 + C:32B7H LINE# 44 + C:32CFH LINE# 45 + C:32D2H LINE# 46 + C:32D5H LINE# 47 + C:32E2H LINE# 49 + C:32E2H LINE# 52 + C:32EEH LINE# 53 + C:32EEH LINE# 54 + C:32FDH LINE# 55 + C:3300H LINE# 56 + C:3305H LINE# 57 + C:3305H LINE# 58 + C:330AH LINE# 59 + C:330AH LINE# 60 + C:331AH LINE# 61 + C:331AH LINE# 62 + C:3324H LINE# 64 + C:332BH LINE# 65 + C:332BH LINE# 66 + C:332BH LINE# 67 + C:332DH LINE# 69 + C:332DH LINE# 70 + C:3337H LINE# 71 + C:3337H LINE# 72 + C:333AH LINE# 73 + C:3340H LINE# 74 + C:3343H LINE# 75 + C:3345H LINE# 77 + C:3345H LINE# 78 + C:334BH LINE# 79 + C:334BH LINE# 80 + C:334BH LINE# 81 + C:3353H LINE# 82 + C:3353H LINE# 83 + C:3353H LINE# 84 + C:3353H LINE# 85 + C:3353H LINE# 86 + ------- ENDPROC USART_JUDGE_DATA + ------- PROC USART_DEAL_DATA + ------- DO + D:0008H SYMBOL i + ------- ENDDO + C:00FEH LINE# 88 + C:00FEH LINE# 89 + C:00FEH LINE# 91 + C:0107H LINE# 92 + C:0107H LINE# 93 + C:010BH LINE# 94 + C:010BH LINE# 95 + C:0114H LINE# 96 + C:0114H LINE# 97 + C:0145H LINE# 98 + C:0145H LINE# 100 + C:0145H LINE# 101 + C:0149H LINE# 102 + C:0149H LINE# 103 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 17 + + + C:0152H LINE# 104 + C:0152H LINE# 105 + C:0158H LINE# 106 + C:015BH LINE# 107 + C:015EH LINE# 109 + C:015EH LINE# 110 + C:0164H LINE# 111 + C:0168H LINE# 112 + C:0168H LINE# 113 + C:0171H LINE# 114 + C:0171H LINE# 116 + C:0174H LINE# 117 + C:0174H LINE# 118 + C:0191H LINE# 119 + C:0191H LINE# 120 + C:01A3H LINE# 121 + C:01B4H LINE# 122 + C:01DCH LINE# 124 + C:01FDH LINE# 125 + C:01FDH LINE# 126 + C:020FH LINE# 127 + C:020FH LINE# 129 + C:0230H LINE# 130 + C:0230H LINE# 131 + C:0242H LINE# 132 + C:0242H LINE# 134 + C:02BEH LINE# 135 + C:02E6H LINE# 137 + C:0302H LINE# 141 + C:0316H LINE# 142 + C:0316H LINE# 143 + C:0328H LINE# 144 + C:0328H LINE# 147 + C:0355H LINE# 148 + C:0355H LINE# 149 + C:03B5H LINE# 150 + C:03DDH LINE# 151 + C:03DDH LINE# 152 + C:03F3H LINE# 153 + C:03F3H LINE# 154 + C:03F3H LINE# 156 + C:0420H LINE# 157 + C:0420H LINE# 158 + C:047EH LINE# 159 + C:04A6H LINE# 160 + C:04A6H LINE# 161 + C:04BCH LINE# 162 + C:04BCH LINE# 163 + C:04BCH LINE# 164 + C:04BCH LINE# 165 + C:04C7H LINE# 168 + C:04CAH LINE# 169 + C:04CAH LINE# 170 + C:04E7H LINE# 171 + C:04E7H LINE# 172 + C:04F9H LINE# 173 + C:050AH LINE# 174 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 18 + + + C:0532H LINE# 176 + C:0553H LINE# 177 + C:0553H LINE# 178 + C:0565H LINE# 179 + C:0565H LINE# 181 + C:0586H LINE# 182 + C:0586H LINE# 183 + C:0598H LINE# 184 + C:0598H LINE# 186 + C:0614H LINE# 187 + C:063CH LINE# 189 + C:0658H LINE# 194 + C:066CH LINE# 195 + C:066CH LINE# 196 + C:067EH LINE# 197 + C:067EH LINE# 200 + C:06ABH LINE# 201 + C:06ABH LINE# 202 + C:070BH LINE# 203 + C:0733H LINE# 204 + C:0733H LINE# 205 + C:0749H LINE# 206 + C:0749H LINE# 207 + C:0749H LINE# 210 + C:0776H LINE# 211 + C:0776H LINE# 212 + C:07D4H LINE# 213 + C:07FCH LINE# 214 + C:07FCH LINE# 215 + C:0812H LINE# 216 + C:0812H LINE# 217 + C:0812H LINE# 218 + C:0812H LINE# 219 + C:081DH LINE# 221 + C:0820H LINE# 222 + C:0823H LINE# 226 + C:0823H LINE# 227 + C:0829H LINE# 228 + C:082DH LINE# 229 + C:082DH LINE# 230 + C:0836H LINE# 231 + C:0836H LINE# 233 + C:0839H LINE# 234 + C:0839H LINE# 235 + C:0856H LINE# 236 + C:0856H LINE# 237 + C:0867H LINE# 238 + C:0879H LINE# 239 + C:0890H LINE# 240 + C:08A7H LINE# 242 + C:08BEH LINE# 243 + C:08BEH LINE# 244 + C:08C5H LINE# 245 + C:08C5H LINE# 246 + C:08D6H LINE# 247 + C:08D6H LINE# 249 + C:08DAH LINE# 250 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 19 + + + C:08DAH LINE# 251 + C:08ECH LINE# 252 + C:08ECH LINE# 254 + C:08F4H LINE# 255 + C:08F4H LINE# 256 + C:090AH LINE# 257 + C:090AH LINE# 258 + C:091BH LINE# 259 + C:091DH LINE# 260 + C:091DH LINE# 262 + C:0931H LINE# 263 + C:0931H LINE# 264 + C:0943H LINE# 265 + C:0943H LINE# 266 + C:0943H LINE# 267 + C:0943H LINE# 268 + C:0943H LINE# 269 + C:0943H LINE# 270 + C:094EH LINE# 273 + C:0951H LINE# 274 + C:0951H LINE# 275 + C:096EH LINE# 276 + C:096EH LINE# 277 + C:097FH LINE# 278 + C:0991H LINE# 279 + C:09A8H LINE# 280 + C:09BFH LINE# 282 + C:09D6H LINE# 283 + C:09D6H LINE# 284 + C:09DDH LINE# 285 + C:09DDH LINE# 286 + C:09EEH LINE# 287 + C:09EEH LINE# 289 + C:09F2H LINE# 290 + C:09F2H LINE# 291 + C:0A04H LINE# 292 + C:0A04H LINE# 294 + C:0A0CH LINE# 295 + C:0A0CH LINE# 296 + C:0A22H LINE# 297 + C:0A22H LINE# 298 + C:0A33H LINE# 299 + C:0A35H LINE# 300 + C:0A35H LINE# 302 + C:0A49H LINE# 303 + C:0A49H LINE# 304 + C:0A5BH LINE# 305 + C:0A5BH LINE# 306 + C:0A5BH LINE# 307 + C:0A5BH LINE# 308 + C:0A5BH LINE# 309 + C:0A5BH LINE# 310 + C:0A66H LINE# 311 + C:0A69H LINE# 312 + C:0A6CH LINE# 316 + C:0A6CH LINE# 317 + C:0A72H LINE# 319 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 20 + + + C:0A76H LINE# 320 + C:0A76H LINE# 321 + C:0A7FH LINE# 322 + C:0A7FH LINE# 325 + C:0A86H LINE# 326 + C:0A86H LINE# 327 + C:0A93H LINE# 328 + C:0A96H LINE# 329 + C:0A96H LINE# 330 + C:0AB7H LINE# 331 + C:0AB7H LINE# 332 + C:0AC9H LINE# 333 + C:0AC9H LINE# 334 + C:0AD0H LINE# 335 + C:0AD0H LINE# 337 + C:0AD7H LINE# 338 + C:0AD7H LINE# 339 + C:0AE4H LINE# 340 + C:0AE7H LINE# 341 + C:0AE7H LINE# 342 + C:0B08H LINE# 343 + C:0B08H LINE# 344 + C:0B1AH LINE# 345 + C:0B1AH LINE# 346 + C:0B21H LINE# 347 + C:0B21H LINE# 349 + C:0B2BH LINE# 350 + C:0B2BH LINE# 351 + C:0B36H LINE# 353 + C:0B39H LINE# 354 + C:0B39H LINE# 357 + C:0B4BH LINE# 358 + C:0B5CH LINE# 360 + C:0BD8H LINE# 361 + C:0C00H LINE# 362 + C:0C21H LINE# 363 + C:0C21H LINE# 364 + C:0C35H LINE# 365 + C:0C35H LINE# 368 + C:0C62H LINE# 369 + C:0C62H LINE# 370 + C:0CC2H LINE# 371 + C:0CEAH LINE# 372 + C:0CEAH LINE# 373 + C:0D00H LINE# 374 + C:0D00H LINE# 375 + C:0D00H LINE# 377 + C:0D2DH LINE# 378 + C:0D2DH LINE# 379 + C:0D8BH LINE# 380 + C:0DB3H LINE# 381 + C:0DB3H LINE# 382 + C:0DC9H LINE# 383 + C:0DC9H LINE# 384 + C:0DC9H LINE# 385 + C:0DD4H LINE# 386 + C:0DD4H LINE# 389 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 21 + + + C:0DD7H LINE# 390 + C:0DDAH LINE# 394 + C:0DDAH LINE# 395 + C:0DE0H LINE# 396 + C:0DE4H LINE# 397 + C:0DE4H LINE# 398 + C:0DEDH LINE# 399 + C:0DEDH LINE# 401 + C:0DF0H LINE# 402 + C:0DF0H LINE# 403 + C:0E0DH LINE# 404 + C:0E0DH LINE# 405 + C:0E1CH LINE# 406 + C:0E1CH LINE# 407 + C:0E2EH LINE# 409 + C:0E33H LINE# 410 + C:0E33H LINE# 412 + C:0E41H LINE# 413 + C:0E41H LINE# 415 + C:0E46H LINE# 416 + C:0E57H LINE# 417 + C:0E68H LINE# 418 + C:0E7BH LINE# 419 + C:0E8CH LINE# 420 + C:0E8CH LINE# 422 + C:0E9FH LINE# 423 + C:0E9FH LINE# 424 + C:0EB3H LINE# 425 + C:0EB3H LINE# 426 + C:0EC5H LINE# 428 + C:0ECAH LINE# 429 + C:0ECCH LINE# 430 + C:0ECCH LINE# 432 + C:0EE2H LINE# 433 + C:0EE2H LINE# 435 + C:0EE7H LINE# 436 + C:0EF8H LINE# 437 + C:0F09H LINE# 438 + C:0F1CH LINE# 439 + C:0F2DH LINE# 440 + C:0F2DH LINE# 441 + C:0F2DH LINE# 442 + C:0F2DH LINE# 443 + C:0F2DH LINE# 444 + C:0F39H LINE# 447 + C:0F3CH LINE# 448 + C:0F3CH LINE# 449 + C:0F59H LINE# 450 + C:0F59H LINE# 451 + C:0F68H LINE# 452 + C:0F68H LINE# 453 + C:0F7AH LINE# 455 + C:0F82H LINE# 456 + C:0F82H LINE# 458 + C:0F90H LINE# 459 + C:0F90H LINE# 461 + C:0F98H LINE# 462 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 22 + + + C:0FA9H LINE# 463 + C:0FBAH LINE# 464 + C:0FCDH LINE# 465 + C:0FDEH LINE# 466 + C:0FDEH LINE# 468 + C:0FF1H LINE# 469 + C:0FF1H LINE# 470 + C:1005H LINE# 471 + C:1005H LINE# 472 + C:1017H LINE# 474 + C:101FH LINE# 475 + C:1021H LINE# 476 + C:1021H LINE# 479 + C:1037H LINE# 480 + C:1037H LINE# 482 + C:103FH LINE# 483 + C:1050H LINE# 484 + C:1061H LINE# 485 + C:1074H LINE# 486 + C:1085H LINE# 487 + C:1085H LINE# 488 + C:1085H LINE# 489 + C:1085H LINE# 490 + C:1085H LINE# 491 + C:1091H LINE# 492 + C:1094H LINE# 493 + C:1096H LINE# 494 + C:1096H LINE# 495 + C:109CH LINE# 496 + C:10A0H LINE# 497 + C:10A0H LINE# 498 + C:10A9H LINE# 499 + C:10A9H LINE# 500 + C:10AFH LINE# 501 + C:10B5H LINE# 502 + C:10B7H LINE# 503 + C:10B7H LINE# 504 + C:10BDH LINE# 505 + C:10C3H LINE# 506 + C:10C7H LINE# 507 + C:10C7H LINE# 508 + C:10D0H LINE# 509 + C:10D0H LINE# 510 + C:10D0H LINE# 511 + C:10D0H LINE# 512 + C:10D5H LINE# 513 + C:10D5H LINE# 514 + ------- ENDPROC USART_DEAL_DATA + ------- PROC USART_ANSWER + ------- DO + D:0007H SYMBOL i + D:0008H SYMBOL checksum + ------- ENDDO + C:2CB4H LINE# 516 + C:2CB4H LINE# 517 + C:2CB4H LINE# 518 + C:2CB6H LINE# 519 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 23 + + + C:2CB8H LINE# 520 + C:2CC1H LINE# 521 + C:2CC1H LINE# 522 + C:2CC7H LINE# 523 + C:2CCFH LINE# 524 + C:2CD3H LINE# 525 + C:2CDBH LINE# 526 + C:2CDFH LINE# 527 + C:2CE8H LINE# 528 + C:2CE8H LINE# 529 + C:2CE8H LINE# 530 + C:2D13H LINE# 531 + C:2D28H LINE# 532 + C:2D28H LINE# 533 + C:2D36H LINE# 534 + C:2D36H LINE# 535 + C:2D3AH LINE# 536 + C:2D47H LINE# 537 + C:2D4DH LINE# 539 + C:2D58H LINE# 541 + C:2D58H LINE# 542 + C:2D58H LINE# 544 + C:2D58H LINE# 545 + C:2D5DH LINE# 546 + C:2D6AH LINE# 547 + C:2D6AH LINE# 548 + C:2D70H LINE# 549 + C:2D70H LINE# 550 + C:2D76H LINE# 551 + C:2D7EH LINE# 552 + C:2D82H LINE# 553 + C:2D8AH LINE# 554 + C:2D8EH LINE# 555 + C:2D9AH LINE# 556 + C:2DA0H LINE# 557 + C:2DABH LINE# 558 + C:2DAFH LINE# 559 + C:2DAFH LINE# 560 + C:2DB8H LINE# 561 + C:2DB8H LINE# 564 + C:2DBDH LINE# 565 + C:2DCAH LINE# 566 + C:2DCAH LINE# 568 + C:2DD0H LINE# 569 + C:2DD0H LINE# 570 + C:2DD4H LINE# 571 + C:2DDCH LINE# 572 + C:2DE0H LINE# 573 + C:2DE8H LINE# 574 + C:2DECH LINE# 575 + C:2DF2H LINE# 576 + C:2DF5H LINE# 578 + C:2E02H LINE# 579 + C:2E08H LINE# 580 + C:2E13H LINE# 581 + C:2E17H LINE# 582 + C:2E17H LINE# 583 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 24 + + + C:2E20H LINE# 584 + C:2E20H LINE# 585 + C:2E25H LINE# 586 + C:2E32H LINE# 587 + C:2E32H LINE# 588 + ------- ENDPROC USART_ANSWER + ------- PROC _SUMFUNC + D:0009H SYMBOL answer + D:0005H SYMBOL len + ------- DO + D:0007H SYMBOL m + D:0006H SYMBOL j + ------- ENDDO + C:3AE4H LINE# 591 + C:3AEAH LINE# 592 + C:3AEAH LINE# 593 + C:3AECH LINE# 595 + C:3AF2H LINE# 596 + C:3AF2H LINE# 597 + C:3AF7H LINE# 598 + C:3B07H LINE# 599 + C:3B0AH LINE# 600 + C:3B0DH LINE# 601 + ------- ENDPROC _SUMFUNC + ------- ENDMOD UART_SET + + ------- MODULE PWM_CONTROL + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + C:3423H PUBLIC _PWM_write + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + C:399EH PUBLIC GPIO_config + C:1DD8H PUBLIC deal_command1 + D:00A8H PUBLIC IE + C:10D6H PUBLIC deal_command2 + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + X:0110H PUBLIC s_pwm + C:2FC1H PUBLIC pwm_config + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + C:37BCH PUBLIC show_light + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + C:3C52H PUBLIC _Close_Light + C:38ECH PUBLIC _Open_Light + D:00D0H PUBLIC PSW + ------- PROC GPIO_CONFIG + ------- DO + D:0008H SYMBOL GPIO_InitStructure + ------- ENDDO + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 25 + + + C:399EH LINE# 15 + C:399EH LINE# 16 + C:399EH LINE# 19 + C:39A1H LINE# 20 + C:39A4H LINE# 21 + C:39AEH LINE# 24 + C:39B1H LINE# 25 + C:39B4H LINE# 26 + C:39BFH LINE# 28 + C:39C2H LINE# 29 + C:39C5H LINE# 30 + C:39D0H LINE# 33 + C:39D3H LINE# 34 + C:39D6H LINE# 35 + ------- ENDPROC GPIO_CONFIG + ------- PROC PWM_CONFIG + ------- DO + D:0007H SYMBOL i + D:0008H SYMBOL PWM15_InitStructure + ------- ENDDO + C:2FC1H LINE# 38 + C:2FC1H LINE# 39 + C:2FC1H LINE# 43 + C:2FC4H LINE# 44 + C:2FCAH LINE# 45 + C:2FCDH LINE# 46 + C:2FCFH LINE# 47 + C:2FD2H LINE# 49 + C:2FDBH LINE# 50 + C:2FE6H LINE# 52 + C:2FEFH LINE# 53 + C:2FF8H LINE# 54 + C:3001H LINE# 55 + C:300AH LINE# 56 + C:3013H LINE# 57 + C:301CH LINE# 58 + C:3025H LINE# 59 + C:302EH LINE# 61 + C:3037H LINE# 62 + C:3040H LINE# 63 + C:3049H LINE# 64 + C:3052H LINE# 66 + C:3061H LINE# 67 + C:3063H LINE# 68 + C:3063H LINE# 69 + C:3076H LINE# 70 + C:307AH LINE# 71 + C:3089H LINE# 72 + C:3099H LINE# 73 + C:30A9H LINE# 74 + C:30B9H LINE# 75 + C:30C9H LINE# 76 + C:30D9H LINE# 77 + C:30E9H LINE# 78 + C:30F9H LINE# 80 + C:3109H LINE# 81 + C:3119H LINE# 82 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 26 + + + C:3129H LINE# 83 + ------- ENDPROC PWM_CONFIG + ------- PROC DEAL_COMMAND1 + ------- DO + D:0008H SYMBOL i + D:003BH SYMBOL systick_command1 + ------- ENDDO + C:1DD8H LINE# 89 + C:1DD8H LINE# 90 + C:1DD8H LINE# 91 + C:1DDDH LINE# 94 + C:1E01H LINE# 95 + C:1E01H LINE# 96 + C:1E0DH LINE# 97 + C:1E12H LINE# 98 + C:1E12H LINE# 99 + C:1E2FH LINE# 100 + C:1E2FH LINE# 101 + C:1E5EH LINE# 102 + C:1E5EH LINE# 104 + C:1EBEH LINE# 105 + C:1EFEH LINE# 107 + C:1F08H LINE# 108 + C:1F08H LINE# 109 + C:1F16H LINE# 110 + C:1F18H LINE# 112 + C:1F18H LINE# 113 + C:1F89H LINE# 114 + C:1F89H LINE# 116 + C:1FB6H LINE# 117 + C:1FB6H LINE# 118 + C:1FCEH LINE# 119 + C:1FCEH LINE# 120 + C:1FCEH LINE# 124 + C:1FFDH LINE# 125 + C:1FFDH LINE# 127 + C:205DH LINE# 128 + C:209DH LINE# 130 + C:20A7H LINE# 131 + C:20A7H LINE# 132 + C:20B5H LINE# 133 + C:20B7H LINE# 135 + C:20B7H LINE# 136 + C:2128H LINE# 137 + C:2128H LINE# 139 + C:21B1H LINE# 140 + C:21B1H LINE# 141 + C:21C8H LINE# 142 + C:21E6H LINE# 143 + C:21E6H LINE# 144 + C:21E6H LINE# 147 + C:2213H LINE# 148 + C:2213H LINE# 149 + C:223AH LINE# 150 + C:2248H LINE# 151 + C:2248H LINE# 152 + C:2248H LINE# 153 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 27 + + + C:2259H LINE# 154 + C:2259H LINE# 155 + ------- ENDPROC DEAL_COMMAND1 + ------- PROC DEAL_COMMAND2 + ------- DO + D:0008H SYMBOL i + D:003FH SYMBOL systick_command2 + ------- ENDDO + C:10D6H LINE# 157 + C:10D6H LINE# 158 + C:10D6H LINE# 159 + C:10DBH LINE# 161 + C:10FFH LINE# 162 + C:10FFH LINE# 163 + C:110BH LINE# 164 + C:1110H LINE# 165 + C:1110H LINE# 166 + C:112DH LINE# 167 + C:112DH LINE# 168 + C:1156H LINE# 169 + C:1156H LINE# 171 + C:1156H LINE# 173 + C:1173H LINE# 174 + C:1173H LINE# 175 + C:11F1H LINE# 176 + C:1210H LINE# 177 + C:121AH LINE# 178 + C:121AH LINE# 179 + C:1231H LINE# 180 + C:1233H LINE# 182 + C:1233H LINE# 183 + C:12A4H LINE# 184 + C:12A4H LINE# 185 + C:12D0H LINE# 186 + C:12D0H LINE# 187 + C:12E7H LINE# 188 + C:1305H LINE# 189 + C:131CH LINE# 190 + C:131CH LINE# 191 + C:131CH LINE# 193 + C:133BH LINE# 194 + C:133BH LINE# 195 + C:13B9H LINE# 196 + C:13F8H LINE# 197 + C:13F8H LINE# 198 + C:1408H LINE# 199 + C:1408H LINE# 200 + C:1408H LINE# 201 + C:140BH LINE# 203 + C:140BH LINE# 204 + C:1444H LINE# 205 + C:144EH LINE# 206 + C:144EH LINE# 207 + C:144EH LINE# 208 + C:1451H LINE# 210 + C:1451H LINE# 211 + C:1451H LINE# 212 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 28 + + + C:1451H LINE# 213 + C:1451H LINE# 214 + C:1451H LINE# 215 + C:1454H LINE# 218 + C:1454H LINE# 220 + C:1471H LINE# 221 + C:1471H LINE# 222 + C:14EFH LINE# 223 + C:150EH LINE# 224 + C:1518H LINE# 225 + C:1518H LINE# 226 + C:152FH LINE# 227 + C:1531H LINE# 229 + C:1531H LINE# 230 + C:15A2H LINE# 231 + C:15A2H LINE# 232 + C:15CEH LINE# 233 + C:15CEH LINE# 234 + C:15E6H LINE# 235 + C:1604H LINE# 236 + C:161BH LINE# 237 + C:161BH LINE# 238 + C:161BH LINE# 240 + C:163AH LINE# 241 + C:163AH LINE# 242 + C:16B8H LINE# 243 + C:16F7H LINE# 244 + C:16F7H LINE# 245 + C:170EH LINE# 246 + C:172CH LINE# 247 + C:1734H LINE# 248 + C:1737H LINE# 250 + C:1737H LINE# 251 + C:1770H LINE# 252 + C:177AH LINE# 253 + C:177AH LINE# 254 + C:178AH LINE# 255 + C:178DH LINE# 257 + C:178DH LINE# 258 + C:17FEH LINE# 259 + C:17FEH LINE# 260 + C:17FEH LINE# 261 + C:17FEH LINE# 262 + C:1800H LINE# 263 + C:1800H LINE# 265 + C:1817H LINE# 266 + C:1817H LINE# 267 + C:1817H LINE# 268 + C:1817H LINE# 269 + C:1828H LINE# 270 + C:1828H LINE# 271 + ------- ENDPROC DEAL_COMMAND2 + ------- PROC _CLOSE_LIGHT + D:0007H SYMBOL i + C:3C52H LINE# 275 + C:3C52H LINE# 276 + C:3C52H LINE# 277 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 29 + + + C:3C65H LINE# 278 + ------- ENDPROC _CLOSE_LIGHT + ------- PROC _OPEN_LIGHT + D:0009H SYMBOL pin + C:38ECH LINE# 281 + C:38EEH LINE# 282 + C:38EEH LINE# 283 + C:3949H LINE# 284 + ------- ENDPROC _OPEN_LIGHT + ------- PROC _PWM_WRITE + D:0007H SYMBOL i + D:000AH SYMBOL Val + C:3423H LINE# 286 + C:3427H LINE# 287 + C:3427H LINE# 288 + C:345BH LINE# 289 + C:345BH LINE# 290 + C:345BH LINE# 291 + C:3461H LINE# 292 + C:3463H LINE# 293 + C:3463H LINE# 294 + C:3469H LINE# 295 + C:346BH LINE# 296 + C:346BH LINE# 297 + C:3471H LINE# 298 + C:3473H LINE# 299 + C:3473H LINE# 300 + C:3479H LINE# 301 + C:347BH LINE# 302 + C:347BH LINE# 303 + C:3481H LINE# 304 + C:3483H LINE# 305 + C:3483H LINE# 306 + C:3489H LINE# 307 + C:348BH LINE# 308 + C:348BH LINE# 309 + C:3491H LINE# 310 + C:3493H LINE# 311 + C:3493H LINE# 312 + C:3499H LINE# 313 + C:349BH LINE# 314 + C:349BH LINE# 315 + C:34A1H LINE# 316 + C:34A3H LINE# 317 + C:34A3H LINE# 318 + C:34A9H LINE# 319 + C:34ABH LINE# 320 + C:34ABH LINE# 321 + C:34B1H LINE# 322 + C:34B3H LINE# 323 + C:34B3H LINE# 324 + C:34BCH LINE# 325 + C:34BCH LINE# 326 + C:34BCH LINE# 327 + ------- ENDPROC _PWM_WRITE + ------- PROC SHOW_LIGHT + ------- DO + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 30 + + + D:0008H SYMBOL i + ------- ENDDO + C:37BCH LINE# 328 + C:37BCH LINE# 329 + C:37BCH LINE# 331 + C:37C1H LINE# 332 + C:37C1H LINE# 333 + C:37EAH LINE# 334 + C:37EAH LINE# 335 + C:37EDH LINE# 336 + C:37EFH LINE# 338 + C:37EFH LINE# 339 + C:380EH LINE# 340 + C:380EH LINE# 341 + C:3821H LINE# 342 + ------- ENDPROC SHOW_LIGHT + ------- ENDMOD PWM_CONTROL + + ------- MODULE START_INIT + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + C:35D5H PUBLIC Start_Init + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + C:3BF4H PUBLIC Timer2_Init_1ms + D:00D8H PUBLIC CCON + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + D:00D0H PUBLIC PSW + ------- PROC START_INIT + ------- DO + D:0007H SYMBOL i + ------- ENDDO + C:35D5H LINE# 8 + C:35D5H LINE# 9 + C:35D5H LINE# 11 + C:35E4H LINE# 12 + C:35F3H LINE# 13 + C:3602H LINE# 14 + C:3608H LINE# 15 + C:360FH LINE# 16 + C:3617H LINE# 17 + C:3620H LINE# 19 + C:3622H LINE# 20 + C:3622H LINE# 21 + C:3633H LINE# 22 + C:3644H LINE# 23 + C:3657H LINE# 24 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 31 + + + C:365BH LINE# 25 + ------- ENDPROC START_INIT + ------- PROC TIMER2_INIT_1MS + ------- DO + D:0008H SYMBOL TIM_InitStructure + ------- ENDDO + C:3BF4H LINE# 28 + C:3BF4H LINE# 29 + C:3BF4H LINE# 31 + C:3BF7H LINE# 32 + C:3BFAH LINE# 33 + C:3BFDH LINE# 34 + C:3C00H LINE# 35 + C:3C02H LINE# 36 + C:3C08H LINE# 37 + C:3C0BH LINE# 38 + ------- ENDPROC TIMER2_INIT_1MS + ------- ENDMOD START_INIT + + ------- MODULE PWM15BIT + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + C:2E41H PUBLIC PWMxCR + D:00C0H PUBLIC P4 + C:394AH PUBLIC _PWM15Duty + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00BAH PUBLIC P_SW2 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + C:39E1H PUBLIC _PWMLevelSet + D:00D8H PUBLIC CCON + D:00F6H PUBLIC PWMCFG01 + D:00F7H PUBLIC PWMCFG23 + D:00FEH PUBLIC PWMCFG45 + D:0098H PUBLIC SCON + B:00A0H.3 PUBLIC P23 + D:0088H PUBLIC TCON + B:00A0H.4 PUBLIC P24 + B:00A0H.5 PUBLIC P25 + B:00A0H.6 PUBLIC P26 + B:00A0H.7 PUBLIC P27 + D:00F0H PUBLIC B + C:2F61H PUBLIC PWMxHLD + D:00E0H PUBLIC ACC + C:0026H PUBLIC PWM0_Handler + C:3A20H PUBLIC PWM1_Handler + C:3A51H PUBLIC PWM2_Handler + C:3A82H PUBLIC PWM3_Handler + C:36DAH PUBLIC _PWMChannelCtrl + C:3AB3H PUBLIC PWM4_Handler + C:2AFCH PUBLIC _PWM15_Init + D:00F1H PUBLIC PWMSET + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 32 + + + C:2EA1H PUBLIC PWMxT1 + C:2F01H PUBLIC PWMxT2 + C:3752H PUBLIC _qPWM15Duty + D:00D0H PUBLIC PSW + ------- PROC _PWMCHANNELCTRL + D:0007H SYMBOL PWM_id + D:0005H SYMBOL pwm_eno + D:0003H SYMBOL pwm_ini + D:0012H SYMBOL pwm_eni + D:0013H SYMBOL pwm_ent2i + D:0014H SYMBOL pwm_ent1i + ------- DO + D:0082H SYMBOL pPWMxCR + ------- ENDDO + C:36DAH LINE# 231 + C:36DAH LINE# 232 + C:36DAH LINE# 235 + C:36E3H LINE# 236 + C:36ECH LINE# 237 + C:36F5H LINE# 238 + C:36FFH LINE# 239 + C:3709H LINE# 240 + C:3713H LINE# 242 + C:3716H LINE# 243 + C:372CH LINE# 244 + C:374CH LINE# 245 + C:374FH LINE# 246 + C:3751H LINE# 247 + ------- ENDPROC _PWMCHANNELCTRL + ------- PROC _PWM15DUTY + D:0007H SYMBOL PWM_id + D:0004H SYMBOL dutyL + ------- DO + D:0082H SYMBOL pPWMxT1 + D:0082H SYMBOL pPWMxT2 + ------- ENDDO + C:394AH LINE# 258 + C:394AH LINE# 259 + C:394AH LINE# 263 + C:3953H LINE# 264 + C:395FH LINE# 267 + C:3962H LINE# 268 + C:3978H LINE# 269 + C:397FH LINE# 271 + C:3995H LINE# 272 + C:3999H LINE# 273 + C:399CH LINE# 274 + C:399DH LINE# 275 + ------- ENDPROC _PWM15DUTY + ------- PROC _QPWM15DUTY + D:0001H SYMBOL PWM_id + D:0004H SYMBOL dutyL + D:0002H SYMBOL dutyH + ------- DO + D:0082H SYMBOL pPWMxT1 + D:0082H SYMBOL pPWMxT2 + ------- ENDDO + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 33 + + + C:3752H LINE# 277 + C:3754H LINE# 278 + C:3754H LINE# 282 + C:375DH LINE# 283 + C:3769H LINE# 284 + C:3775H LINE# 286 + C:3778H LINE# 287 + C:378EH LINE# 288 + C:3797H LINE# 290 + C:37ADH LINE# 291 + C:37B6H LINE# 292 + C:37B9H LINE# 293 + C:37BBH LINE# 294 + ------- ENDPROC _QPWM15DUTY + ------- PROC _PWMLEVELSET + D:0007H SYMBOL PWM_id + D:0005H SYMBOL pwm_hldl + D:0003H SYMBOL pwm_hldh + ------- DO + D:0082H SYMBOL pPWMxHLD + ------- ENDDO + C:39E1H LINE# 304 + C:39E1H LINE# 305 + C:39E1H LINE# 308 + C:39EAH LINE# 309 + C:39F3H LINE# 310 + C:39FCH LINE# 312 + C:39FFH LINE# 313 + C:3A15H LINE# 314 + C:3A1AH LINE# 315 + C:3A1DH LINE# 316 + C:3A1FH LINE# 317 + ------- ENDPROC _PWMLEVELSET + ------- PROC _PWM15_INIT + D:0007H SYMBOL PWM_id + D:0001H SYMBOL PWMx + C:2AFCH LINE# 327 + C:2AFCH LINE# 328 + C:2AFCH LINE# 329 + C:2B05H LINE# 331 + C:2B08H LINE# 332 + C:2B0BH LINE# 333 + C:2B0BH LINE# 334 + C:2B16H LINE# 335 + C:2B19H LINE# 336 + C:2B2AH LINE# 337 + C:2B3CH LINE# 338 + C:2B4AH LINE# 339 + C:2B4DH LINE# 340 + C:2B4DH LINE# 342 + C:2B52H LINE# 343 + C:2B52H LINE# 344 + C:2B5DH LINE# 345 + C:2B60H LINE# 346 + C:2B71H LINE# 347 + C:2B83H LINE# 348 + C:2B91H LINE# 349 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 34 + + + C:2B94H LINE# 350 + C:2B94H LINE# 352 + C:2B99H LINE# 353 + C:2B99H LINE# 354 + C:2BA4H LINE# 355 + C:2BA7H LINE# 356 + C:2BB8H LINE# 357 + C:2BCAH LINE# 358 + C:2BD8H LINE# 359 + C:2BDBH LINE# 360 + C:2BDBH LINE# 362 + C:2BE0H LINE# 363 + C:2BE0H LINE# 364 + C:2BEBH LINE# 365 + C:2BEEH LINE# 366 + C:2BFFH LINE# 367 + C:2C11H LINE# 368 + C:2C1FH LINE# 369 + C:2C22H LINE# 370 + C:2C22H LINE# 372 + C:2C27H LINE# 373 + C:2C27H LINE# 374 + C:2C32H LINE# 375 + C:2C35H LINE# 376 + C:2C46H LINE# 377 + C:2C58H LINE# 378 + C:2C66H LINE# 379 + C:2C69H LINE# 380 + C:2C69H LINE# 382 + C:2C6EH LINE# 383 + C:2C6EH LINE# 384 + C:2C79H LINE# 385 + C:2C7CH LINE# 386 + C:2C8DH LINE# 387 + C:2C9FH LINE# 388 + C:2CADH LINE# 389 + C:2CB0H LINE# 390 + C:2CB0H LINE# 391 + C:2CB3H LINE# 392 + ------- ENDPROC _PWM15_INIT + ------- PROC PWM0_HANDLER + ------- DO + D:0007H SYMBOL store + ------- ENDDO + C:0026H LINE# 402 + C:0033H LINE# 405 + C:0035H LINE# 406 + C:0038H LINE# 408 + C:003DH LINE# 409 + C:003DH LINE# 410 + C:0040H LINE# 412 + C:0040H LINE# 413 + C:0046H LINE# 414 + C:0046H LINE# 415 + C:0048H LINE# 416 + C:004AH LINE# 417 + C:004AH LINE# 418 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 35 + + + C:004CH LINE# 419 + ------- ENDPROC PWM0_HANDLER + ------- PROC PWM1_HANDLER + ------- DO + D:0007H SYMBOL store + ------- ENDDO + C:3A20H LINE# 427 + C:3A2DH LINE# 430 + C:3A2FH LINE# 431 + C:3A32H LINE# 433 + C:3A37H LINE# 434 + C:3A37H LINE# 435 + C:3A3AH LINE# 437 + C:3A3AH LINE# 438 + C:3A40H LINE# 439 + C:3A40H LINE# 440 + C:3A42H LINE# 441 + C:3A44H LINE# 442 + C:3A44H LINE# 443 + C:3A46H LINE# 444 + ------- ENDPROC PWM1_HANDLER + ------- PROC PWM2_HANDLER + ------- DO + D:0007H SYMBOL store + ------- ENDDO + C:3A51H LINE# 452 + C:3A5EH LINE# 455 + C:3A60H LINE# 456 + C:3A63H LINE# 458 + C:3A68H LINE# 459 + C:3A68H LINE# 460 + C:3A6BH LINE# 462 + C:3A6BH LINE# 463 + C:3A71H LINE# 464 + C:3A71H LINE# 465 + C:3A73H LINE# 466 + C:3A75H LINE# 467 + C:3A75H LINE# 468 + C:3A77H LINE# 469 + ------- ENDPROC PWM2_HANDLER + ------- PROC PWM3_HANDLER + ------- DO + D:0007H SYMBOL store + ------- ENDDO + C:3A82H LINE# 477 + C:3A8FH LINE# 480 + C:3A91H LINE# 481 + C:3A94H LINE# 483 + C:3A99H LINE# 484 + C:3A99H LINE# 485 + C:3A9CH LINE# 487 + C:3A9CH LINE# 488 + C:3AA2H LINE# 489 + C:3AA2H LINE# 490 + C:3AA4H LINE# 491 + C:3AA6H LINE# 492 + C:3AA6H LINE# 493 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 36 + + + C:3AA8H LINE# 494 + ------- ENDPROC PWM3_HANDLER + ------- PROC PWM4_HANDLER + ------- DO + D:0007H SYMBOL store + ------- ENDDO + C:3AB3H LINE# 502 + C:3AC0H LINE# 505 + C:3AC2H LINE# 506 + C:3AC5H LINE# 508 + C:3ACAH LINE# 509 + C:3ACAH LINE# 510 + C:3ACDH LINE# 512 + C:3ACDH LINE# 513 + C:3AD3H LINE# 514 + C:3AD3H LINE# 515 + C:3AD5H LINE# 516 + C:3AD7H LINE# 517 + C:3AD7H LINE# 518 + C:3AD9H LINE# 519 + ------- ENDPROC PWM4_HANDLER + ------- ENDMOD PWM15BIT + + ------- MODULE TIMER + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + C:0007H PUBLIC timer0_int + D:0043H PUBLIC systick_1ms + D:00A0H PUBLIC P2 + C:0018H PUBLIC timer1_int + D:00B0H PUBLIC P3 + C:3C34H PUBLIC timer2_int + D:00C0H PUBLIC P4 + C:000AH PUBLIC timer3_int + D:00C8H PUBLIC P5 + C:001EH PUBLIC timer4_int + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + D:0098H PUBLIC SCON + D:0089H PUBLIC TMOD + D:0088H PUBLIC TCON + B:00E8H.3 PUBLIC P63 + B:00E8H.6 PUBLIC P66 + C:25B5H PUBLIC _Timer_Inilize + B:00E8H.7 PUBLIC P67 + D:00AFH PUBLIC IE2 + D:00F0H PUBLIC B + D:008EH PUBLIC AUXR + D:00E0H PUBLIC ACC + B:00A8H.1 PUBLIC ET0 + B:00A8H.3 PUBLIC ET1 + D:008CH PUBLIC TH0 + D:008DH PUBLIC TH1 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 37 + + + D:00D6H PUBLIC TH2 + D:00D4H PUBLIC TH3 + D:00D2H PUBLIC TH4 + D:008AH PUBLIC TL0 + D:008BH PUBLIC TL1 + D:00D7H PUBLIC TL2 + D:00D5H PUBLIC TL3 + B:00B8H.1 PUBLIC PT0 + D:00D3H PUBLIC TL4 + B:00B8H.3 PUBLIC PT1 + B:0088H.4 PUBLIC TR0 + B:0088H.6 PUBLIC TR1 + D:00D1H PUBLIC T4T3M + D:00B7H PUBLIC IPH + D:008FH PUBLIC INT_CLKO + D:00D0H PUBLIC PSW + ------- PROC TIMER0_INT + C:0007H LINE# 22 + C:0007H LINE# 24 + C:0009H LINE# 25 + ------- ENDPROC TIMER0_INT + ------- PROC TIMER1_INT + C:0018H LINE# 28 + C:0018H LINE# 30 + C:001AH LINE# 31 + ------- ENDPROC TIMER1_INT + ------- PROC TIMER2_INT + C:3C34H LINE# 34 + C:3C38H LINE# 36 + C:3C4DH LINE# 37 + ------- ENDPROC TIMER2_INT + ------- PROC TIMER3_INT + C:000AH LINE# 40 + C:000AH LINE# 43 + ------- ENDPROC TIMER3_INT + ------- PROC TIMER4_INT + C:001EH LINE# 46 + C:001EH LINE# 48 + C:0020H LINE# 49 + ------- ENDPROC TIMER4_INT + ------- PROC _TIMER_INILIZE + D:0005H SYMBOL TIM + D:0001H SYMBOL TIMx + C:25B5H LINE# 59 + C:25B7H LINE# 60 + C:25B7H LINE# 61 + C:25C0H LINE# 63 + C:25C6H LINE# 64 + C:25C6H LINE# 65 + C:25C8H LINE# 66 + C:25D5H LINE# 67 + C:25D7H LINE# 68 + C:25E6H LINE# 69 + C:2614H LINE# 71 + C:2620H LINE# 72 + C:2627H LINE# 73 + C:2634H LINE# 74 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 38 + + + C:263AH LINE# 75 + C:2643H LINE# 76 + C:2646H LINE# 77 + C:2654H LINE# 78 + C:2657H LINE# 80 + C:2669H LINE# 81 + C:2674H LINE# 82 + C:2677H LINE# 83 + C:2677H LINE# 85 + C:267FH LINE# 86 + C:267FH LINE# 87 + C:2681H LINE# 88 + C:268EH LINE# 89 + C:2690H LINE# 90 + C:269FH LINE# 91 + C:26CDH LINE# 92 + C:26D9H LINE# 93 + C:26E0H LINE# 94 + C:26EDH LINE# 95 + C:26F3H LINE# 96 + C:26FCH LINE# 97 + C:26FFH LINE# 98 + C:270DH LINE# 99 + C:2710H LINE# 101 + C:2722H LINE# 102 + C:272DH LINE# 103 + C:2730H LINE# 104 + C:2730H LINE# 106 + C:2735H LINE# 107 + C:2735H LINE# 108 + C:2738H LINE# 109 + C:2746H LINE# 110 + C:2749H LINE# 111 + C:2758H LINE# 112 + C:275FH LINE# 113 + C:276AH LINE# 114 + C:2778H LINE# 115 + C:277BH LINE# 116 + C:2789H LINE# 117 + C:278CH LINE# 119 + C:279EH LINE# 120 + C:27AAH LINE# 121 + C:27ADH LINE# 122 + C:27ADH LINE# 124 + C:27B2H LINE# 125 + C:27B2H LINE# 126 + C:27B5H LINE# 127 + C:27C3H LINE# 128 + C:27C6H LINE# 129 + C:27D5H LINE# 130 + C:27DCH LINE# 131 + C:27E7H LINE# 132 + C:27F5H LINE# 133 + C:27F8H LINE# 134 + C:2806H LINE# 135 + C:2809H LINE# 137 + C:281BH LINE# 138 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 39 + + + C:2827H LINE# 139 + C:282AH LINE# 140 + C:282AH LINE# 142 + C:282FH LINE# 143 + C:282FH LINE# 144 + C:2832H LINE# 145 + C:2840H LINE# 146 + C:2843H LINE# 147 + C:2852H LINE# 148 + C:2859H LINE# 149 + C:2864H LINE# 150 + C:2872H LINE# 151 + C:2875H LINE# 152 + C:2883H LINE# 153 + C:2886H LINE# 155 + C:2896H LINE# 156 + C:28A2H LINE# 157 + C:28A5H LINE# 158 + C:28A5H LINE# 159 + C:28A7H LINE# 160 + ------- ENDPROC _TIMER_INILIZE + ------- ENDMOD TIMER + + ------- MODULE KEY + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + C:3139H PUBLIC KEY_TEST + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + C:3C15H PUBLIC Key_Init + D:00D8H PUBLIC CCON + C:3354H PUBLIC Key_ScanTask + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + B:00C0H.4 PUBLIC P44 + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + D:0035H PUBLIC g_Key + D:00D0H PUBLIC PSW + ------- PROC KEY_INIT + ------- DO + D:0008H SYMBOL GPIO_InitStructure1 + ------- ENDDO + C:3C15H LINE# 8 + C:3C15H LINE# 9 + C:3C15H LINE# 12 + C:3C18H LINE# 13 + C:3C1BH LINE# 14 + C:3C25H LINE# 15 + ------- ENDPROC KEY_INIT + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 40 + + + ------- PROC KEY_SCANTASK + ------- DO + D:0007H SYMBOL i + D:0031H SYMBOL update_10ms + ------- ENDDO + C:3354H LINE# 18 + C:3354H LINE# 19 + C:3354H LINE# 23 + C:3378H LINE# 24 + C:3378H LINE# 25 + C:3384H LINE# 27 + C:3386H LINE# 28 + C:3386H LINE# 29 + C:3398H LINE# 30 + C:3398H LINE# 31 + C:3398H LINE# 32 + C:339BH LINE# 33 + C:339BH LINE# 34 + C:33A5H LINE# 35 + C:33A5H LINE# 36 + C:33A6H LINE# 37 + C:33A8H LINE# 39 + C:33A8H LINE# 40 + C:33AEH LINE# 41 + C:33B4H LINE# 42 + C:33B6H LINE# 43 + C:33B6H LINE# 44 + C:33B8H LINE# 46 + C:33B8H LINE# 47 + C:33BEH LINE# 48 + C:33C4H LINE# 49 + C:33C6H LINE# 50 + C:33C6H LINE# 51 + C:33C8H LINE# 52 + C:33C8H LINE# 53 + C:33CDH LINE# 54 + C:33D3H LINE# 55 + C:33D3H LINE# 56 + C:33D6H LINE# 57 + C:33D6H LINE# 58 + C:33DCH LINE# 59 + C:33E2H LINE# 60 + C:33E8H LINE# 61 + C:33E8H LINE# 62 + C:33EAH LINE# 64 + C:33EAH LINE# 65 + C:33F0H LINE# 66 + C:33F6H LINE# 67 + C:33FCH LINE# 68 + C:3402H LINE# 69 + C:3402H LINE# 70 + C:3404H LINE# 72 + C:3404H LINE# 73 + C:340AH LINE# 74 + C:340DH LINE# 75 + C:340DH LINE# 76 + C:3413H LINE# 77 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 41 + + + C:3419H LINE# 78 + C:3419H LINE# 79 + C:3419H LINE# 80 + C:3419H LINE# 81 + C:3422H LINE# 82 + C:3422H LINE# 83 + ------- ENDPROC KEY_SCANTASK + ------- PROC KEY_TEST + ------- DO + D:0007H SYMBOL flag + ------- ENDDO + C:3139H LINE# 86 + C:3139H LINE# 87 + C:3139H LINE# 89 + C:3142H LINE# 90 + C:3142H LINE# 91 + C:3144H LINE# 92 + C:314AH LINE# 93 + C:3189H LINE# 94 + C:3189H LINE# 95 + C:3189H LINE# 96 + C:3193H LINE# 97 + C:3196H LINE# 98 + C:3199H LINE# 99 + C:3199H LINE# 100 + C:31A3H LINE# 101 + C:31A6H LINE# 102 + C:31A9H LINE# 103 + C:31A9H LINE# 104 + C:31B3H LINE# 105 + C:31B6H LINE# 106 + C:31B9H LINE# 107 + C:31B9H LINE# 108 + C:31C3H LINE# 109 + C:31C6H LINE# 110 + C:31C8H LINE# 111 + C:31C8H LINE# 112 + C:31D2H LINE# 113 + C:31D5H LINE# 114 + C:31D7H LINE# 115 + C:31D7H LINE# 116 + C:31E1H LINE# 117 + C:31E4H LINE# 118 + C:31E6H LINE# 119 + C:31E6H LINE# 120 + C:31F0H LINE# 121 + C:31F3H LINE# 122 + C:31F5H LINE# 123 + C:31F5H LINE# 124 + C:31FFH LINE# 125 + C:3202H LINE# 126 + C:3204H LINE# 127 + C:3204H LINE# 128 + C:320EH LINE# 129 + C:3211H LINE# 130 + C:3213H LINE# 131 + C:3213H LINE# 132 + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 42 + + + C:321DH LINE# 133 + C:3220H LINE# 134 + C:3222H LINE# 135 + C:3222H LINE# 136 + C:322CH LINE# 137 + C:322FH LINE# 138 + C:3231H LINE# 139 + C:3231H LINE# 140 + C:323BH LINE# 141 + C:3244H LINE# 142 + C:3245H LINE# 143 + C:3245H LINE# 144 + C:3247H LINE# 145 + C:3247H LINE# 146 + C:325AH LINE# 147 + C:326AH LINE# 148 + C:326EH LINE# 149 + C:3273H LINE# 150 + C:3273H LINE# 151 + C:3273H LINE# 152 + C:3273H LINE# 153 + C:3273H LINE# 154 + C:3273H LINE# 155 + ------- ENDPROC KEY_TEST + ------- ENDMOD KEY + + ------- MODULE WDT + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + C:3B37H PUBLIC _WDT_Inilize + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + C:0003H PUBLIC WDT_Clear + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + D:00C1H PUBLIC WDT_CONTR + D:00D0H PUBLIC PSW + ------- PROC _WDT_INILIZE + D:0001H SYMBOL WDT + C:3B37H LINE# 22 + C:3B37H LINE# 23 + C:3B37H LINE# 24 + C:3B40H LINE# 26 + C:3B50H LINE# 27 + C:3B5CH LINE# 28 + C:3B5FH LINE# 29 + ------- ENDPROC _WDT_INILIZE + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 43 + + + ------- PROC WDT_CLEAR + C:0003H LINE# 32 + C:0003H LINE# 33 + C:0003H LINE# 34 + C:0006H LINE# 35 + ------- ENDPROC WDT_CLEAR + ------- ENDMOD WDT + + ------- MODULE ?C?FPADD + C:1830H PUBLIC ?C?FPADD + C:182CH PUBLIC ?C?FPSUB + ------- ENDMOD ?C?FPADD + + ------- MODULE ?C?FPDIV + C:1924H PUBLIC ?C?FPDIV + ------- ENDMOD ?C?FPDIV + + ------- MODULE ?C?FPCMP + C:19C3H PUBLIC ?C?FPCMP + C:19C1H PUBLIC ?C?FPCMP3 + ------- ENDMOD ?C?FPCMP + + ------- MODULE ?C?FCAST + C:1A38H PUBLIC ?C?FCASTC + C:1A33H PUBLIC ?C?FCASTI + C:1A2EH PUBLIC ?C?FCASTL + ------- ENDMOD ?C?FCAST + + ------- MODULE ?C?CASTF + C:1A6CH PUBLIC ?C?CASTF + ------- ENDMOD ?C?CASTF + + ------- MODULE ?C?CLDPTR + C:1AEDH PUBLIC ?C?CLDPTR + ------- ENDMOD ?C?CLDPTR + + ------- MODULE ?C?CLDOPTR + C:1B06H PUBLIC ?C?CLDOPTR + ------- ENDMOD ?C?CLDOPTR + + ------- MODULE ?C?IILDX + C:1B33H PUBLIC ?C?IILDX + ------- ENDMOD ?C?IILDX + + ------- MODULE ?C?ILDOPTR + C:1B49H PUBLIC ?C?ILDOPTR + ------- ENDMOD ?C?ILDOPTR + + ------- MODULE ?C?LMUL + C:1B81H PUBLIC ?C?LMUL + ------- ENDMOD ?C?LMUL + + ------- MODULE ?C?ULDIV + C:1C0CH PUBLIC ?C?ULDIV + ------- ENDMOD ?C?ULDIV + + ------- MODULE ?C?LNEG + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 44 + + + C:1C9EH PUBLIC ?C?LNEG + ------- ENDMOD ?C?LNEG + + ------- MODULE ?C?ULCMP + C:1CACH PUBLIC ?C?ULCMP + ------- ENDMOD ?C?ULCMP + + ------- MODULE ?C?ULSHR + C:1CBDH PUBLIC ?C?ULSHR + ------- ENDMOD ?C?ULSHR + + ------- MODULE ?C?LLDOPTR0 + C:1CD0H PUBLIC ?C?LLDOPTR0 + ------- ENDMOD ?C?LLDOPTR0 + + ------- MODULE ?C?LSTXDATA + C:1D00H PUBLIC ?C?LSTXDATA + ------- ENDMOD ?C?LSTXDATA + + ------- MODULE ?C?LSTKXDATA + C:1D0CH PUBLIC ?C?LSTKXDATA + ------- ENDMOD ?C?LSTKXDATA + + ------- MODULE ?C?OFFXADD + C:1D3DH PUBLIC ?C?OFFXADD + ------- ENDMOD ?C?OFFXADD + + ------- MODULE ?C?LIMUL + C:1D49H PUBLIC ?C?LIMUL + ------- ENDMOD ?C?LIMUL + + ------- MODULE ?C?MEMSET + C:1D76H PUBLIC ?C?MEMSET + ------- ENDMOD ?C?MEMSET + + ------- MODULE ?C?LLDIDATA0 + C:1DA2H PUBLIC ?C?LLDIDATA0 + ------- ENDMOD ?C?LLDIDATA0 + + ------- MODULE ?C?LLDXDATA0 + C:1DAFH PUBLIC ?C?LLDXDATA0 + ------- ENDMOD ?C?LLDXDATA0 + + ------- MODULE ?C?LLDPDATA0 + C:1DBBH PUBLIC ?C?LLDPDATA0 + ------- ENDMOD ?C?LLDPDATA0 + + ------- MODULE ?C?LLDCODE0 + C:1DC8H PUBLIC ?C?LLDCODE0 + ------- ENDMOD ?C?LLDCODE0 + +*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS + SEGMENT: ?PR?_PRINTBUFFER1?UART + +*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS + SEGMENT: ?PR?_PRINTSTRING3?UART + + BL51 BANKED LINKER/LOCATER V6.22 12/15/2025 20:45:04 PAGE 45 + + +*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS + SEGMENT: ?PR?_QPWM15DUTY?PWM15BIT + +*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS + SEGMENT: ?PR?_PWMLEVELSET?PWM15BIT + +Program Size: data=77.0 xdata=641 code=15470 +LINK/LOCATE RUN COMPLETE. 4 WARNING(S), 0 ERROR(S) diff --git a/Listings/GPIO.lst b/Listings/GPIO.lst new file mode 100644 index 0000000..28482aa --- /dev/null +++ b/Listings/GPIO.lst @@ -0,0 +1,97 @@ +C51 COMPILER V9.01 GPIO 12/15/2025 20:45:03 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE GPIO +OBJECT MODULE PLACED IN .\Objects\GPIO.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE GPIO.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\GPIO + -.lst) OBJECT(.\Objects\GPIO.obj) + +line level source + + 1 #include "GPIO.h" + 2 + 3 //======================================================================== + 4 // : u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) + 5 // : ʼIO. + 6 // : GPIOx: ṹ,οtimer.hĶ. + 7 // : ɹ0, ղ1,󷵻2. + 8 // 汾: V1.0, 2012-10-22 + 9 //======================================================================== + 10 u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) + 11 { + 12 1 if(GPIO > GPIO_P7) return 1; //ղ + 13 1 if(GPIOx->Mode > GPIO_OUT_PP) return 2; // + 14 1 if(GPIO == GPIO_P0) + 15 1 { + 16 2 if(GPIOx->Mode == GPIO_PullUp) P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; //׼˫ + 17 2 if(GPIOx->Mode == GPIO_HighZ) P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // + 18 2 if(GPIOx->Mode == GPIO_OUT_OD) P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; //© + 19 2 if(GPIOx->Mode == GPIO_OUT_PP) P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; // + 20 2 } + 21 1 if(GPIO == GPIO_P1) + 22 1 { + 23 2 if(GPIOx->Mode == GPIO_PullUp) P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; //׼˫ + 24 2 if(GPIOx->Mode == GPIO_HighZ) P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // + 25 2 if(GPIOx->Mode == GPIO_OUT_OD) P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; //© + 26 2 if(GPIOx->Mode == GPIO_OUT_PP) P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; // + 27 2 } + 28 1 if(GPIO == GPIO_P2) + 29 1 { + 30 2 if(GPIOx->Mode == GPIO_PullUp) P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; //׼˫ + 31 2 if(GPIOx->Mode == GPIO_HighZ) P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // + 32 2 if(GPIOx->Mode == GPIO_OUT_OD) P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; //© + 33 2 if(GPIOx->Mode == GPIO_OUT_PP) P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; // + 34 2 } + 35 1 if(GPIO == GPIO_P3) + 36 1 { + 37 2 if(GPIOx->Mode == GPIO_PullUp) P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; //׼˫ + 38 2 if(GPIOx->Mode == GPIO_HighZ) P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // + 39 2 if(GPIOx->Mode == GPIO_OUT_OD) P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; //© + 40 2 if(GPIOx->Mode == GPIO_OUT_PP) P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; // + 41 2 } + 42 1 if(GPIO == GPIO_P4) + 43 1 { + 44 2 if(GPIOx->Mode == GPIO_PullUp) P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; //׼˫ + 45 2 if(GPIOx->Mode == GPIO_HighZ) P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // + 46 2 if(GPIOx->Mode == GPIO_OUT_OD) P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; //© + 47 2 if(GPIOx->Mode == GPIO_OUT_PP) P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; // + 48 2 } + 49 1 if(GPIO == GPIO_P5) + 50 1 { + 51 2 if(GPIOx->Mode == GPIO_PullUp) P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; //׼˫ + 52 2 if(GPIOx->Mode == GPIO_HighZ) P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // + 53 2 if(GPIOx->Mode == GPIO_OUT_OD) P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; //© + 54 2 if(GPIOx->Mode == GPIO_OUT_PP) P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; // + C51 COMPILER V9.01 GPIO 12/15/2025 20:45:03 PAGE 2 + + 55 2 } + 56 1 if(GPIO == GPIO_P6) + 57 1 { + 58 2 if(GPIOx->Mode == GPIO_PullUp) P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; //׼˫ + 59 2 if(GPIOx->Mode == GPIO_HighZ) P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // + 60 2 if(GPIOx->Mode == GPIO_OUT_OD) P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; //© + 61 2 if(GPIOx->Mode == GPIO_OUT_PP) P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; // + 62 2 } + 63 1 if(GPIO == GPIO_P7) + 64 1 { + 65 2 if(GPIOx->Mode == GPIO_PullUp) P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; //׼˫ + 66 2 if(GPIOx->Mode == GPIO_HighZ) P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // + 67 2 if(GPIOx->Mode == GPIO_OUT_OD) P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; //© + 68 2 if(GPIOx->Mode == GPIO_OUT_PP) P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; // + 69 2 } + 70 1 return 0; //ɹ + 71 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 596 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/PWM15bit.lst b/Listings/PWM15bit.lst new file mode 100644 index 0000000..e9a5dbc --- /dev/null +++ b/Listings/PWM15bit.lst @@ -0,0 +1,575 @@ +C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE PWM15BIT +OBJECT MODULE PLACED IN .\Objects\PWM15bit.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE PWM15bit.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\ + -PWM15bit.lst) OBJECT(.\Objects\PWM15bit.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 #include "PWM15bit.h" + 14 + 15 u16 code PWMxCR[48] = { + 16 0xff14, /* PWM00CR */ + 17 0xff1c, /* PWM01CR */ + 18 0xff24, /* PWM02CR */ + 19 0xff2c, /* PWM03CR */ + 20 0xff34, /* PWM04CR */ + 21 0xff3c, /* PWM05CR */ + 22 0xff44, /* PWM06CR */ + 23 0xff4c, /* PWM07CR */ + 24 0xff64, /* PWM10CR */ + 25 0xff6c, /* PWM11CR */ + 26 0xff74, /* PWM12CR */ + 27 0xff7c, /* PWM13CR */ + 28 0xff84, /* PWM14CR */ + 29 0xff8c, /* PWM15CR */ + 30 0xff94, /* PWM16CR */ + 31 0xff9c, /* PWM17CR */ + 32 0xffb4, /* PWM20CR */ + 33 0xffbc, /* PWM21CR */ + 34 0xffc4, /* PWM22CR */ + 35 0xffcc, /* PWM23CR */ + 36 0xffd4, /* PWM24CR */ + 37 0xffdc, /* PWM25CR */ + 38 0xffe4, /* PWM26CR */ + 39 0xffec, /* PWM27CR */ + 40 0xfc14, /* PWM30CR */ + 41 0xfc1c, /* PWM31CR */ + 42 0xfc24, /* PWM32CR */ + 43 0xfc2c, /* PWM33CR */ + 44 0xfc34, /* PWM34CR */ + 45 0xfc3c, /* PWM35CR */ + 46 0xfc44, /* PWM36CR */ + 47 0xfc4c, /* PWM37CR */ + 48 0xfc64, /* PWM40CR */ + 49 0xfc6c, /* PWM41CR */ + 50 0xfc74, /* PWM42CR */ + 51 0xfc7c, /* PWM43CR */ + 52 0xfc84, /* PWM44CR */ + 53 0xfc8c, /* PWM45CR */ + 54 0xfc94, /* PWM46CR */ + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 2 + + 55 0xfc9c, /* PWM47CR */ + 56 0xfcb4, /* PWM50CR */ + 57 0xfcbc, /* PWM51CR */ + 58 0xfcc4, /* PWM52CR */ + 59 0xfccc, /* PWM53CR */ + 60 0xfcd4, /* PWM54CR */ + 61 0xfcdc, /* PWM55CR */ + 62 0xfce4, /* PWM56CR */ + 63 0xfcec, /* PWM57CR */ + 64 }; + 65 + 66 u16 code PWMxT1[48] = { + 67 0xff10, /* PWM00T1 */ + 68 0xff18, /* PWM01T1 */ + 69 0xff20, /* PWM02T1 */ + 70 0xff28, /* PWM03T1 */ + 71 0xff30, /* PWM04T1 */ + 72 0xff38, /* PWM05T1 */ + 73 0xff40, /* PWM06T1 */ + 74 0xff48, /* PWM07T1 */ + 75 0xff60, /* PWM10T1 */ + 76 0xff68, /* PWM11T1 */ + 77 0xff70, /* PWM12T1 */ + 78 0xff78, /* PWM13T1 */ + 79 0xff80, /* PWM14T1 */ + 80 0xff88, /* PWM15T1 */ + 81 0xff90, /* PWM16T1 */ + 82 0xff98, /* PWM17T1 */ + 83 0xffb0, /* PWM20T1 */ + 84 0xffb8, /* PWM21T1 */ + 85 0xffc0, /* PWM22T1 */ + 86 0xffc8, /* PWM23T1 */ + 87 0xffd0, /* PWM24T1 */ + 88 0xffd8, /* PWM25T1 */ + 89 0xffe0, /* PWM26T1 */ + 90 0xffe8, /* PWM27T1 */ + 91 0xfc10, /* PWM30T1 */ + 92 0xfc18, /* PWM31T1 */ + 93 0xfc20, /* PWM32T1 */ + 94 0xfc28, /* PWM33T1 */ + 95 0xfc30, /* PWM34T1 */ + 96 0xfc38, /* PWM35T1 */ + 97 0xfc40, /* PWM36T1 */ + 98 0xfc48, /* PWM37T1 */ + 99 0xfc60, /* PWM40T1 */ + 100 0xfc68, /* PWM41T1 */ + 101 0xfc70, /* PWM42T1 */ + 102 0xfc78, /* PWM43T1 */ + 103 0xfc80, /* PWM44T1 */ + 104 0xfc88, /* PWM45T1 */ + 105 0xfc90, /* PWM46T1 */ + 106 0xfc98, /* PWM47T1 */ + 107 0xfcb0, /* PWM50T1 */ + 108 0xfcb8, /* PWM51T1 */ + 109 0xfcc0, /* PWM52T1 */ + 110 0xfcc8, /* PWM53T1 */ + 111 0xfcd0, /* PWM54T1 */ + 112 0xfcd8, /* PWM55T1 */ + 113 0xfce0, /* PWM56T1 */ + 114 0xfce8, /* PWM57T1 */ + 115 }; + 116 + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 3 + + 117 u16 code PWMxT2[48] = { + 118 0xff12, /* PWM00T2 */ + 119 0xff1a, /* PWM01T2 */ + 120 0xff22, /* PWM02T2 */ + 121 0xff2a, /* PWM03T2 */ + 122 0xff32, /* PWM04T2 */ + 123 0xff3a, /* PWM05T2 */ + 124 0xff42, /* PWM06T2 */ + 125 0xff4a, /* PWM07T2 */ + 126 0xff62, /* PWM10T2 */ + 127 0xff6a, /* PWM11T2 */ + 128 0xff72, /* PWM12T2 */ + 129 0xff7a, /* PWM13T2 */ + 130 0xff82, /* PWM14T2 */ + 131 0xff8a, /* PWM15T2 */ + 132 0xff92, /* PWM16T2 */ + 133 0xff9a, /* PWM17T2 */ + 134 0xffb2, /* PWM20T2 */ + 135 0xffba, /* PWM21T2 */ + 136 0xffc2, /* PWM22T2 */ + 137 0xffca, /* PWM23T2 */ + 138 0xffd2, /* PWM24T2 */ + 139 0xffda, /* PWM25T2 */ + 140 0xffe2, /* PWM26T2 */ + 141 0xffea, /* PWM27T2 */ + 142 0xfc12, /* PWM30T2 */ + 143 0xfc1a, /* PWM31T2 */ + 144 0xfc22, /* PWM32T2 */ + 145 0xfc2a, /* PWM33T2 */ + 146 0xfc32, /* PWM34T2 */ + 147 0xfc3a, /* PWM35T2 */ + 148 0xfc42, /* PWM36T2 */ + 149 0xfc4a, /* PWM37T2 */ + 150 0xfc62, /* PWM40T2 */ + 151 0xfc6a, /* PWM41T2 */ + 152 0xfc72, /* PWM42T2 */ + 153 0xfc7a, /* PWM43T2 */ + 154 0xfc82, /* PWM44T2 */ + 155 0xfc8a, /* PWM45T2 */ + 156 0xfc92, /* PWM46T2 */ + 157 0xfc9a, /* PWM47T2 */ + 158 0xfcb2, /* PWM50T2 */ + 159 0xfcba, /* PWM51T2 */ + 160 0xfcc2, /* PWM52T2 */ + 161 0xfcca, /* PWM53T2 */ + 162 0xfcd2, /* PWM54T2 */ + 163 0xfcda, /* PWM55T2 */ + 164 0xfce2, /* PWM56T2 */ + 165 0xfcea, /* PWM57T2 */ + 166 }; + 167 + 168 u16 code PWMxHLD[48] = { + 169 0xff15, /* PWM00HLD */ + 170 0xff1d, /* PWM01HLD */ + 171 0xff25, /* PWM02HLD */ + 172 0xff2d, /* PWM03HLD */ + 173 0xff35, /* PWM04HLD */ + 174 0xff3d, /* PWM05HLD */ + 175 0xff45, /* PWM06HLD */ + 176 0xff4d, /* PWM07HLD */ + 177 0xff65, /* PWM10HLD */ + 178 0xff6d, /* PWM11HLD */ + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 4 + + 179 0xff75, /* PWM12HLD */ + 180 0xff7d, /* PWM13HLD */ + 181 0xff85, /* PWM14HLD */ + 182 0xff8d, /* PWM15HLD */ + 183 0xff95, /* PWM16HLD */ + 184 0xff9d, /* PWM17HLD */ + 185 0xffb5, /* PWM20HLD */ + 186 0xffbd, /* PWM21HLD */ + 187 0xffc5, /* PWM22HLD */ + 188 0xffcd, /* PWM23HLD */ + 189 0xffd5, /* PWM24HLD */ + 190 0xffdd, /* PWM25HLD */ + 191 0xffe5, /* PWM26HLD */ + 192 0xffed, /* PWM27HLD */ + 193 0xfc15, /* PWM30HLD */ + 194 0xfc1d, /* PWM31HLD */ + 195 0xfc25, /* PWM32HLD */ + 196 0xfc2d, /* PWM33HLD */ + 197 0xfc35, /* PWM34HLD */ + 198 0xfc3d, /* PWM35HLD */ + 199 0xfc45, /* PWM36HLD */ + 200 0xfc4d, /* PWM37HLD */ + 201 0xfc65, /* PWM40HLD */ + 202 0xfc6d, /* PWM41HLD */ + 203 0xfc75, /* PWM42HLD */ + 204 0xfc7d, /* PWM43HLD */ + 205 0xfc85, /* PWM44HLD */ + 206 0xfc8d, /* PWM45HLD */ + 207 0xfc95, /* PWM46HLD */ + 208 0xfc9d, /* PWM47HLD */ + 209 0xfcb5, /* PWM50HLD */ + 210 0xfcbd, /* PWM51HLD */ + 211 0xfcc5, /* PWM52HLD */ + 212 0xfccd, /* PWM53HLD */ + 213 0xfcd5, /* PWM54HLD */ + 214 0xfcdd, /* PWM55HLD */ + 215 0xfce5, /* PWM56HLD */ + 216 0xfced, /* PWM57HLD */ + 217 }; + 218 + 219 //======================================================================== + 220 // : u8 PWMChannelCtrl(u8 PWM_id, u8 pwm_eno, u8 pwm_ini, u8 pwm_eni, u8 pwm_ent2i, u8 pwm_ent1i) + 221 // : PWMͨƼĴ. + 222 // : PWM_id: PWMͨ. ȡֵ 0~57 + 223 // pwm_eno: pwmʹ, 0ΪGPIO, 1ΪPWM. + 224 // pwm_ini: pwm˵ijʼƽ, 0Ϊ͵ƽ, 1Ϊߵƽ. + 225 // pwm_eni: pwmͨжʹܿ, 0ΪرPWMж, 1ΪʹPWMж. + 226 // pwm_ent2i: pwmͨڶжʹܿ, 0ΪرPWMڶж, 1ΪʹPWMڶж. + 227 // pwm_ent1i: pwmͨһжʹܿ, 0ΪرPWMһж, 1ΪʹPWMһж. + 228 // : 0:ȷ, 2:. + 229 // 汾: V1.0, 2020-09-22 + 230 //======================================================================== + 231 u8 PWMChannelCtrl(u8 PWM_id, u8 pwm_eno, u8 pwm_ini, u8 pwm_eni, u8 pwm_ent2i, u8 pwm_ent1i) + 232 { + 233 1 u8 xdata *pPWMxCR; + 234 1 + 235 1 if(PWM_id > PWM57) return 2; //id + 236 1 if(pwm_eno > 1) return 2; //ʹܴ + 237 1 if(pwm_ini > 1) return 2; //˵ijʼƽ + 238 1 if(pwm_eni > 1) return 2; //жʹܿƴ + 239 1 if(pwm_ent2i > 1) return 2; //ڶжʹܿƴ + 240 1 if(pwm_ent1i > 1) return 2; //һжʹܿƴ + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 5 + + 241 1 + 242 1 EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + 243 1 pPWMxCR = (u8 *)PWMxCR[PWM_id]; + 244 1 *pPWMxCR = (pwm_eno << 7) | (pwm_ini << 6) | (pwm_eni << 2)| (pwm_ent2i << 1)| pwm_ent1i; + 245 1 EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + 246 1 return 0; + 247 1 } + 248 + 249 //======================================================================== + 250 // : u8 PWMPeriodDuty(u8 PWM_id, u16 Period, u16 dutyL, u16 dutyH) + 251 // : PWM, ռձ. + 252 // : PWM_id: PWMͨ. ȡֵ 0~57 + 253 // dutyL: pwm͵ƽλ, ȡֵ 0~0x7fff. + 254 // dutyH: pwmߵƽλ, ȡֵ 0~0x7fff. + 255 // : 0:ȷ, 2:. + 256 // 汾: V1.0, 2020-09-22 + 257 //======================================================================== + 258 u8 PWM15Duty(u8 PWM_id,u16 dutyL) + 259 { + 260 1 u16 xdata *pPWMxT1; + 261 1 u16 xdata *pPWMxT2; + 262 1 + 263 1 if(PWM_id > PWM57) return 2; //id + 264 1 if(dutyL > 0x7fff) return 2; //͵ƽʱô + 265 1 //if(dutyH > 0x7fff) return 2; //ߵƽʱô + 266 1 + 267 1 EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + 268 1 pPWMxT1 = (u16 *)PWMxT1[PWM_id]; + 269 1 *pPWMxT1 = dutyL & 0x7fff; + 270 1 + 271 1 pPWMxT2 = (u16 *)PWMxT2[PWM_id]; + 272 1 *pPWMxT2 = 0x0000 & 0x7fff; + 273 1 EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + 274 1 return 0; + 275 1 } + 276 + 277 u8 qPWM15Duty(u8 PWM_id,u16 dutyL, u16 dutyH) + 278 { + 279 1 u16 xdata *pPWMxT1; + 280 1 u16 xdata *pPWMxT2; + 281 1 + 282 1 if(PWM_id > PWM57) return 2; //id + 283 1 if(dutyL > 0x7fff) return 2; //͵ƽʱô + 284 1 if(dutyH > 0x7fff) return 2; //ߵƽʱô + 285 1 + 286 1 EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + 287 1 pPWMxT1 = (u16 *)PWMxT1[PWM_id]; + 288 1 *pPWMxT1 = dutyL & 0x7fff; + 289 1 + 290 1 pPWMxT2 = (u16 *)PWMxT2[PWM_id]; + 291 1 *pPWMxT2 = dutyH & 0x7fff; + 292 1 EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + 293 1 return 0; + 294 1 } + 295 //======================================================================== + 296 // : u8 PWMOutputSet(u8 PWM_id, u8 pwm_hldl, u8 pwm_hldh) + 297 // : PWMͨƼĴ. + 298 // : PWM_id: PWMͨ. ȡֵ 0~57 + 299 // pwm_hldl: pwmǿ͵ƽλ, 0, 1ǿ͵ƽ. + 300 // pwm_hldh: pwmǿߵƽλ, 0, 1ǿߵƽ. + 301 // : 0:ȷ, 2:. + 302 // 汾: V1.0, 2020-09-22 + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 6 + + 303 //======================================================================== + 304 u8 PWMLevelSet(u8 PWM_id, u8 pwm_hldl, u8 pwm_hldh) + 305 { + 306 1 u8 xdata *pPWMxHLD; + 307 1 + 308 1 if(PWM_id > PWM57) return 2; //id + 309 1 if(pwm_hldh > 1) return 2; //ʹܴ + 310 1 if(pwm_hldl > 1) return 2; //˵ijʼƽ + 311 1 + 312 1 EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + 313 1 pPWMxHLD = (u8 *)PWMxHLD[PWM_id]; + 314 1 *pPWMxHLD = (pwm_hldh << 1) | pwm_hldl; + 315 1 EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + 316 1 return 0; + 317 1 } + 318 + 319 //======================================================================== + 320 // : void PWM15_Init(u8 PWM_id, PWM15_InitTypeDef *PWMx) + 321 // : 15λǿPWMʼ. + 322 // : PWM_id: PWM. ȡֵ PWM0,PWM1,PWM2,PWM3,PWM4,PWM5 + 323 // PWMx: ṹ,οͷļĶ. + 324 // : none. + 325 // 汾: V1.0, 2020-09-22 + 326 //======================================================================== + 327 void PWM15_Init(u8 PWM_id, PWM15_InitTypeDef *PWMx) + 328 { + 329 1 if(PWM_id > PWM5) return; //id + 330 1 + 331 1 EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + 332 1 if(PWM_id == PWM0) + 333 1 { + 334 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM0_Enable(); //ʹPWM0 + 335 2 else PWM15_PWM0_Disable(); //رPWM0 + 336 2 PWM0_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 337 2 PWM0C = PWMx->PWM_Period & 0x7fff; + 338 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter0_Enable(); //ʹܼ + 339 2 else PWM15_Counter0_Disable(); //رռ + 340 2 } + 341 1 + 342 1 if(PWM_id == PWM1) + 343 1 { + 344 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM1_Enable(); //ʹPWM1 + 345 2 else PWM15_PWM1_Disable(); //رPWM1 + 346 2 PWM1_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 347 2 PWM1C = PWMx->PWM_Period & 0x7fff; + 348 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter1_Enable(); //ʹܼ + 349 2 else PWM15_Counter1_Disable(); //رռ + 350 2 } + 351 1 + 352 1 if(PWM_id == PWM2) + 353 1 { + 354 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM2_Enable(); //ʹPWM2 + 355 2 else PWM15_PWM2_Disable(); //رPWM2 + 356 2 PWM2_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 357 2 PWM2C = PWMx->PWM_Period & 0x7fff; + 358 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter2_Enable(); //ʹܼ + 359 2 else PWM15_Counter2_Disable(); //رռ + 360 2 } + 361 1 + 362 1 if(PWM_id == PWM3) + 363 1 { + 364 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM3_Enable(); //ʹPWM3 + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 7 + + 365 2 else PWM15_PWM3_Disable(); //رPWM3 + 366 2 PWM3_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 367 2 PWM3C = PWMx->PWM_Period & 0x7fff; + 368 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter3_Enable(); //ʹܼ + 369 2 else PWM15_Counter3_Disable(); //رռ + 370 2 } + 371 1 + 372 1 if(PWM_id == PWM4) + 373 1 { + 374 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM4_Enable(); //ʹPWM4 + 375 2 else PWM15_PWM4_Disable(); //رPWM4 + 376 2 PWM4_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 377 2 PWM4C = PWMx->PWM_Period & 0x7fff; + 378 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter4_Enable(); //ʹܼ + 379 2 else PWM15_Counter4_Disable(); //رռ + 380 2 } + 381 1 + 382 1 if(PWM_id == PWM5) + 383 1 { + 384 2 if(PWMx->PWM_Enable == ENABLE) PWM15_PWM5_Enable(); //ʹPWM5 + 385 2 else PWM15_PWM5_Disable(); //رPWM5 + 386 2 PWM5_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + 387 2 PWM5C = PWMx->PWM_Period & 0x7fff; + 388 2 if(PWMx->PWM_Counter == ENABLE) PWM15_Counter5_Enable(); //ʹܼ + 389 2 else PWM15_Counter5_Disable(); //رռ + 390 2 } + 391 1 EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + 392 1 } + 393 + 394 + 395 //======================================================================== + 396 // : void PWM0_Handler (void) interrupt PWM0_VECTOR + 397 // : PWM0жϴ. + 398 // : None + 399 // : none. + 400 // 汾: V1.0, 2020-10-13 + 401 //======================================================================== + 402 void PWM0_Handler (void) interrupt PWM0_VECTOR + 403 { + 404 1 char store; + 405 1 store = P_SW2; + 406 1 P_SW2 |= 0x80; + 407 1 + 408 1 if(PWMCFG01 & 0x08) //PWM0ж + 409 1 { + 410 2 PWMCFG01 &= ~0x08; //PWM0жϱ־ + 411 2 // TODO: ڴ˴û + 412 2 } + 413 1 if(PWM0IF) + 414 1 { + 415 2 PWM0IF = 0; + 416 2 P27 = ~P27; + 417 2 } + 418 1 P_SW2 = store; + 419 1 } + 420 //======================================================================== + 421 // : void PWM1_Handler (void) interrupt PWM1_VECTOR + 422 // : PWM1жϴ. + 423 // : None + 424 // : none. + 425 // 汾: V1.0, 2020-10-13 + 426 //======================================================================== + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 8 + + 427 void PWM1_Handler (void) interrupt PWM1_VECTOR + 428 { + 429 1 char store; + 430 1 store = P_SW2; + 431 1 P_SW2 |= 0x80; + 432 1 + 433 1 if(PWMCFG01 & 0x80) //PWM1ж + 434 1 { + 435 2 PWMCFG01 &= ~0x80; //PWM1жϱ־ + 436 2 // TODO: ڴ˴û + 437 2 } + 438 1 if(PWM1IF) + 439 1 { + 440 2 PWM1IF = 0; + 441 2 P26 = ~P26; + 442 2 } + 443 1 P_SW2 = store; + 444 1 } + 445 //======================================================================== + 446 // : void PWM2_Handler (void) interrupt PWM2_VECTOR + 447 // : PWM2жϴ. + 448 // : None + 449 // : none. + 450 // 汾: V1.0, 2020-10-13 + 451 //======================================================================== + 452 void PWM2_Handler (void) interrupt PWM2_VECTOR + 453 { + 454 1 char store; + 455 1 store = P_SW2; + 456 1 P_SW2 |= 0x80; + 457 1 + 458 1 if(PWMCFG23 & 0x08) //PWM2ж + 459 1 { + 460 2 PWMCFG23 &= ~0x08; //PWM2жϱ־ + 461 2 // TODO: ڴ˴û + 462 2 } + 463 1 if(PWM2IF) + 464 1 { + 465 2 PWM2IF = 0; + 466 2 P25 = ~P25; + 467 2 } + 468 1 P_SW2 = store; + 469 1 } + 470 //======================================================================== + 471 // : void PWM3_Handler (void) interrupt PWM3_VECTOR + 472 // : PWM3жϴ. + 473 // : None + 474 // : none. + 475 // 汾: V1.0, 2020-10-13 + 476 //======================================================================== + 477 void PWM3_Handler (void) interrupt PWM3_VECTOR + 478 { + 479 1 char store; + 480 1 store = P_SW2; + 481 1 P_SW2 |= 0x80; + 482 1 + 483 1 if(PWMCFG23 & 0x80) //PWM3ж + 484 1 { + 485 2 PWMCFG23 &= ~0x80; //PWM3жϱ־ + 486 2 // TODO: ڴ˴û + 487 2 } + 488 1 if(PWM3IF) + C51 COMPILER V9.01 PWM15BIT 12/15/2025 20:45:04 PAGE 9 + + 489 1 { + 490 2 PWM3IF = 0; + 491 2 P24 = ~P24; + 492 2 } + 493 1 P_SW2 = store; + 494 1 } + 495 //======================================================================== + 496 // : void PWM4_Handler (void) interrupt PWM4_VECTOR + 497 // : PWM4жϴ. + 498 // : None + 499 // : none. + 500 // 汾: V1.0, 2020-10-13 + 501 //======================================================================== + 502 void PWM4_Handler (void) interrupt PWM4_VECTOR + 503 { + 504 1 char store; + 505 1 store = P_SW2; + 506 1 P_SW2 |= 0x80; + 507 1 + 508 1 if(PWMCFG45 & 0x08) //PWM4ж + 509 1 { + 510 2 PWMCFG45 &= ~0x08; //PWM4жϱ־ + 511 2 // TODO: ڴ˴û + 512 2 } + 513 1 if(PWM4IF) + 514 1 { + 515 2 PWM4IF = 0; + 516 2 P23 = ~P23; + 517 2 } + 518 1 P_SW2 = store; + 519 1 } + 520 //======================================================================== + 521 // : void PWM5_Handler (void) interrupt PWM5_VECTOR + 522 // : PWM5жϴ. + 523 // : None + 524 // : none. + 525 // 汾: V1.0, 2020-10-13 + 526 //======================================================================== + 527 //void PWM5_Handler (void) interrupt PWM5_VECTOR //жų31ɽжϺת + - + 528 //{ + 529 // if(PWMCFG45 & 0x80) //PWM5ж + 530 // { + 531 // PWMCFG45 &= ~0x80; //PWM5жϱ־ + 532 // // TODO: ڴ˴û + 533 // } + 534 //} + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 1058 ---- + CONSTANT SIZE = 384 ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- 6 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/Start_Init.lst b/Listings/Start_Init.lst new file mode 100644 index 0000000..336336c --- /dev/null +++ b/Listings/Start_Init.lst @@ -0,0 +1,69 @@ +C51 COMPILER V9.01 START_INIT 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE START_INIT +OBJECT MODULE PLACED IN .\Objects\Start_Init.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE Start_Init.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listing + -s\Start_Init.lst) OBJECT(.\Objects\Start_Init.obj) + +line level source + + 1 #include "STC8xxxx.h" + 2 #include "Start_Init.h" + 3 #include "string.h" + 4 #include "UART_Set.h" + 5 #include "timer.h" + 6 #include "pwm_control.h" + 7 + 8 void Start_Init(void) + 9 { + 10 1 u8 i; + 11 1 memset(&g_Usart,0,sizeof(g_Usart)); + 12 1 memset(&s_recv, 0, sizeof(s_recv)); + 13 1 memset(&g_answer,0,sizeof(g_answer)); + 14 1 g_Usart.lastsn=0xFF; + 15 1 s_recv.B_min = 0; + 16 1 s_recv.B_max = 100; + 17 1 s_recv.global_brightness = 100; + 18 1 + 19 1 for(i=0;i<12;i++) + 20 1 { + 21 2 s_recv.pwm_step[i] = 1; + 22 2 s_recv.key_status[i] = 1; + 23 2 s_recv.gradual_time[i] = 300; + 24 2 } + 25 1 } + 26 + 27 //ʱ21msʱ + 28 void Timer2_Init_1ms(void) + 29 { + 30 1 TIM_InitTypeDef TIM_InitStructure; //ṹ + 31 1 TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload; //ָģʽ, TIM_16BitAutoReload,TIM_16Bit,TI + -M_8BitAutoReload,TIM_16BitAutoReloadNoMask + 32 1 TIM_InitStructure.TIM_Priority = Priority_3; //ָжȼ(͵) Priority_0,Priority_1,Priority + -_2,Priority_3 + 33 1 TIM_InitStructure.TIM_Interrupt = ENABLE; //жǷ, ENABLEDISABLE. (ע: Timer2̶Ϊ16λ + -Զװ, жϹ̶Ϊȼ) + 34 1 TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_12T; //ָʱԴ, TIM_CLOCK_1T,TIM_CLOCK_12T,TIM_CLOCK_ + -Ext + 35 1 TIM_InitStructure.TIM_ClkOut = DISABLE; //Ƿ, ENABLEDISABLE + 36 1 TIM_InitStructure.TIM_Value = 63693UL; //ֵ,ʱΪ1ms + 37 1 TIM_InitStructure.TIM_Run = ENABLE; //Ƿʼʱ, ENABLEDISABLE + 38 1 Timer_Inilize(Timer2,&TIM_InitStructure); //ʼTimer2 Timer0,Timer1,Timer2,Timer3,Timer4 + 39 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 168 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- 8 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + C51 COMPILER V9.01 START_INIT 12/15/2025 20:45:04 PAGE 2 + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/UART.lst b/Listings/UART.lst new file mode 100644 index 0000000..76f958a --- /dev/null +++ b/Listings/UART.lst @@ -0,0 +1,531 @@ +C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE UART +OBJECT MODULE PLACED IN .\Objects\UART.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE UART.C OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\UART + -.lst) OBJECT(.\Objects\UART.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 #include "UART.h" + 14 #include "timer.h" + 15 + 16 #ifdef UART1 + 17 COMx_Define COM1; + 18 u8 xdata TX1_Buffer[COM_TX1_Lenth]; //ͻ + 19 u8 xdata RX1_Buffer[COM_RX1_Lenth]; //ջ + 20 #endif + 21 #ifdef UART2 + COMx_Define COM2; + u8 xdata TX2_Buffer[COM_TX2_Lenth]; //ͻ + u8 xdata RX2_Buffer[COM_RX2_Lenth]; //ջ + #endif + 26 #ifdef UART3 + 27 COMx_Define COM3; + 28 u8 xdata TX3_Buffer[COM_TX3_Lenth]; //ͻ + 29 u8 xdata RX3_Buffer[COM_RX3_Lenth]; //ջ + 30 #endif + 31 #ifdef UART4 + COMx_Define COM4; + u8 xdata TX4_Buffer[COM_TX4_Lenth]; //ͻ + u8 xdata RX4_Buffer[COM_RX4_Lenth]; //ջ + #endif + 36 + 37 u8 UART_Configuration(u8 UARTx, COMx_InitDefine *COMx) + 38 { + 39 1 u8 i; + 40 1 u32 j; + 41 1 + 42 1 #ifdef UART1 + 43 1 if(UARTx == UART1) + 44 1 { + 45 2 COM1.id = 1; + 46 2 COM1.TX_read = 0; + 47 2 COM1.TX_write = 0; + 48 2 COM1.B_TX_busy = 0; + 49 2 COM1.RX_Cnt = 0; + 50 2 COM1.RX_TimeOut = 0; + 51 2 COM1.B_RX_OK = 0; + 52 2 for(i=0; iUART_Priority > Priority_3) return 2; // + 56 2 UART1_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_ + -3 + 57 2 if(COMx->UART_Mode > UART_9bit_BRTx) return 2; //ģʽ + 58 2 SCON = (SCON & 0x3f) | COMx->UART_Mode; + 59 2 if((COMx->UART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + 60 2 { + 61 3 j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + 62 3 if(j >= 65536UL) return 2; // + 63 3 j = 65536UL - j; + 64 3 if(COMx->UART_BRT_Use == BRT_Timer1) + 65 3 { + 66 4 TR1 = 0; + 67 4 AUXR &= ~0x01; //S1 BRT Use Timer1; + 68 4 TMOD &= ~(1<<6); //Timer1 set As Timer + 69 4 TMOD &= ~0x30; //Timer1_16bitAutoReload; + 70 4 AUXR |= (1<<6); //Timer1 set as 1T mode + 71 4 TH1 = (u8)(j>>8); + 72 4 TL1 = (u8)j; + 73 4 ET1 = 0; //ֹж + 74 4 TMOD &= ~0x40; //ʱ + 75 4 INT_CLKO &= ~0x02; //ʱ + 76 4 TR1 = 1; + 77 4 } + 78 3 else if(COMx->UART_BRT_Use == BRT_Timer2) + 79 3 { + 80 4 AUXR &= ~(1<<4); //Timer stop + 81 4 AUXR |= 0x01; //S1 BRT Use Timer2; + 82 4 AUXR &= ~(1<<3); //Timer2 set As Timer + 83 4 AUXR |= (1<<2); //Timer2 set as 1T mode + 84 4 TH2 = (u8)(j>>8); + 85 4 TL2 = (u8)j; + 86 4 IE2 &= ~(1<<2); //ֹж + 87 4 AUXR |= (1<<4); //Timer run enable + 88 4 } + 89 3 else return 2; // + 90 3 } + 91 2 else if(COMx->UART_Mode == UART_ShiftRight) + 92 2 { + 93 3 if(COMx->BaudRateDouble == ENABLE) AUXR |= (1<<5); //̶SysClk/2 + 94 3 else AUXR &= ~(1<<5); //̶SysClk/12 + 95 3 } + 96 2 else if(COMx->UART_Mode == UART_9bit) //̶SysClk*2^SMOD/64 + 97 2 { + 98 3 if(COMx->BaudRateDouble == ENABLE) PCON |= (1<<7); //̶SysClk/32 + 99 3 else PCON &= ~(1<<7); //̶SysClk/64 + 100 3 } + 101 2 if(COMx->UART_Interrupt == ENABLE) ES = 1; //ж + 102 2 else ES = 0; //ֹж + 103 2 if(COMx->UART_RxEnable == ENABLE) REN = 1; // + 104 2 else REN = 0; //ֹ + 105 2 P_SW1 = (P_SW1 & 0x3f) | (COMx->UART_P_SW & 0xc0); //лIO + 106 2 return 0; + 107 2 } + 108 1 #endif + 109 1 #ifdef UART2 + if(UARTx == UART2) + { + COM2.id = 2; + COM2.TX_read = 0; + COM2.TX_write = 0; + COM2.B_TX_busy = 0; + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 3 + + COM2.RX_Cnt = 0; + COM2.RX_TimeOut = 0; + COM2.B_RX_OK = 0; + for(i=0; iUART_Mode == UART_9bit_BRTx) ||(COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + if(COMx->UART_Priority > Priority_3) return 2; // + UART2_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority + -_3 + if(COMx->UART_Mode == UART_9bit_BRTx) S2CON |= (1<<7); //9bit + else S2CON &= ~(1<<7); //8bit + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + AUXR &= ~(1<<4); //Timer stop + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; //ģʽ + if(COMx->UART_Interrupt == ENABLE) IE2 |= 1; //ж + else IE2 &= ~1; //ֹж + if(COMx->UART_RxEnable == ENABLE) S2CON |= (1<<4); // + else S2CON &= ~(1<<4); //ֹ + P_SW2 = (P_SW2 & ~1) | (COMx->UART_P_SW & 0x01); //лIO + return 0; + } + #endif + 148 1 #ifdef UART3 + 149 1 if(UARTx == UART3) + 150 1 { + 151 2 COM3.id = 3; + 152 2 COM3.TX_read = 0; + 153 2 COM3.TX_write = 0; + 154 2 COM3.B_TX_busy = 0; + 155 2 COM3.RX_Cnt = 0; + 156 2 COM3.RX_TimeOut = 0; + 157 2 COM3.B_RX_OK = 0; + 158 2 for(i=0; iUART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + 162 2 { + 163 3 if(COMx->UART_Priority > Priority_3) return 2; // + 164 3 UART3_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priorit + -y_3 + 165 3 if(COMx->UART_Mode == UART_9bit_BRTx) S3_9bit(); //9bit + 166 3 else S3_8bit(); //8bit + 167 3 j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + 168 3 if(j >= 65536UL) return 2; // + 169 3 j = 65536UL - j; + 170 3 if(COMx->UART_BRT_Use == BRT_Timer3) + 171 3 { + 172 4 S3_BRT_UseTimer3(); //S3 BRT Use Timer3; + 173 4 TH3 = (u8)(j>>8); + 174 4 TL3 = (u8)j; + 175 4 T4T3M &= 0xf0; + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 4 + + 176 4 T4T3M |= 0x0a; //Timer3 set As Timer, 1T mode, Start timer3 + 177 4 } + 178 3 else if(COMx->UART_BRT_Use == BRT_Timer2) + 179 3 { + 180 4 AUXR &= ~(1<<4); //Timer stop + 181 4 S3_BRT_UseTimer2(); //S3 BRT Use Timer2; + 182 4 AUXR &= ~(1<<3); //Timer2 set As Timer + 183 4 AUXR |= (1<<2); //Timer2 set as 1T mode + 184 4 TH2 = (u8)(j>>8); + 185 4 TL2 = (u8)j; + 186 4 IE2 &= ~(1<<2); //ֹж + 187 4 AUXR |= (1<<4); //Timer run enable + 188 4 } + 189 3 else return 2; // + 190 3 } + 191 2 else return 2; //ģʽ + 192 2 if(COMx->UART_Interrupt == ENABLE) S3_Int_Enable(); //ж + 193 2 else S3_Int_Disable(); //ֹж + 194 2 if(COMx->UART_RxEnable == ENABLE) S3_RX_Enable(); // + 195 2 else S3_RX_Disable(); //ֹ + 196 2 P_SW2 = (P_SW2 & ~2) | (COMx->UART_P_SW & 0x02); //лIO + 197 2 return 0; + 198 2 } + 199 1 #endif + 200 1 #ifdef UART4 + if(UARTx == UART4) + { + COM4.id = 3; + COM4.TX_read = 0; + COM4.TX_write = 0; + COM4.B_TX_busy = 0; + COM4.RX_Cnt = 0; + COM4.RX_TimeOut = 0; + COM4.B_RX_OK = 0; + for(i=0; iUART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + if(COMx->UART_Priority > Priority_3) return 2; // + UART4_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority + -_3 + if(COMx->UART_Mode == UART_9bit_BRTx) S4_9bit(); //9bit + else S4_8bit(); //8bit + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + if(COMx->UART_BRT_Use == BRT_Timer4) + { + S4_BRT_UseTimer4(); //S4 BRT Use Timer4; + TH4 = (u8)(j>>8); + TL4 = (u8)j; + T4T3M &= 0x0f; + T4T3M |= 0xa0; //Timer4 set As Timer, 1T mode, Start timer4 + } + else if(COMx->UART_BRT_Use == BRT_Timer2) + { + AUXR &= ~(1<<4); //Timer stop + S4_BRT_UseTimer2(); //S4 BRT Use Timer2; + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 5 + + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; // + } + else return 2; //ģʽ + if(COMx->UART_Interrupt == ENABLE) S4_Int_Enable(); //ж + else S4_Int_Disable(); //ֹж + if(COMx->UART_RxEnable == ENABLE) S4_RX_Enable(); // + else S4_RX_Disable(); //ֹ + P_SW2 = (P_SW2 & ~4) | (COMx->UART_P_SW & 0x04); //лIO + return 0; + } + #endif + 252 1 return 2; // + 253 1 } + 254 + 255 /*********************************************************/ + 256 + 257 /********************* UART1 ************************/ + 258 #ifdef UART1 + 259 void TX1_write2buff(u8 dat) //д뷢ͻ壬ָ+1 + 260 { + 261 1 TX1_Buffer[COM1.TX_write] = dat; //װͻ + 262 1 if(++COM1.TX_write >= COM_TX1_Lenth) COM1.TX_write = 0; + 263 1 + 264 1 if(COM1.B_TX_busy == 0) // + 265 1 { + 266 2 COM1.B_TX_busy = 1; //־æ + 267 2 TI = 1; //ж + 268 2 } + 269 1 } + 270 + 271 void PrintString1(u8 *puts) + 272 { + 273 1 for (; *puts != 0; puts++) TX1_write2buff(*puts); //ֹͣ0 + 274 1 } + 275 void Printbuffer1(u8 *puts,u8 len) + 276 { + 277 1 u8 i; + 278 1 for (i=0; i= COM_RX1_Lenth) COM1.RX_Cnt = 0; + 297 3 if(dat=='D') //10'D',ϵͳ + 298 3 { + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 6 + + 299 4 stage++; + 300 4 } + 301 3 else + 302 3 { + 303 4 stage=0; + 304 4 } + 305 3 if(stage==10) + 306 3 { + 307 4 IAP_CONTR=0x60; + 308 4 } + 309 3 RX1_Buffer[COM1.RX_Cnt++] = SBUF; + 310 3 COM1.RX_TimeOut = TimeOutSet1; + 311 3 } + 312 2 } + 313 1 + 314 1 if(TI) + 315 1 { + 316 2 TI = 0; + 317 2 if(COM1.TX_read != COM1.TX_write) + 318 2 { + 319 3 SBUF = TX1_Buffer[COM1.TX_read]; + 320 3 if(++COM1.TX_read >= COM_TX1_Lenth) COM1.TX_read = 0; + 321 3 } + 322 2 else COM1.B_TX_busy = 0; + 323 2 } + 324 1 } + 325 #endif + 326 + 327 /********************* UART2 ************************/ + 328 #ifdef UART2 + void TX2_write2buff(u8 dat) //д뷢ͻ壬ָ+1 + { + TX2_Buffer[COM2.TX_write] = dat; //װͻ + if(++COM2.TX_write >= COM_TX2_Lenth) COM2.TX_write = 0; + + if(COM2.B_TX_busy == 0) // + { + COM2.B_TX_busy = 1; //־æ + SET_TI2(); //ж + } + } + + void PrintString2(u8 *puts) + { + for (; *puts != 0; puts++) TX2_write2buff(*puts); //ֹͣ0 + } + + void UART2_int (void) interrupt UART2_VECTOR + { + if(RI2) + { + CLR_RI2(); + if(COM2.B_RX_OK == 0) + { + if(COM2.RX_Cnt >= COM_RX2_Lenth) COM2.RX_Cnt = 0; + RX2_Buffer[COM2.RX_Cnt++] = S2BUF; + COM2.RX_TimeOut = TimeOutSet2; + } + } + + if(TI2) + { + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 7 + + CLR_TI2(); + if(COM2.TX_read != COM2.TX_write) + { + S2BUF = TX2_Buffer[COM2.TX_read]; + if(++COM2.TX_read >= COM_TX2_Lenth) COM2.TX_read = 0; + } + else COM2.B_TX_busy = 0; + } + } + #endif + 371 + 372 /********************* UART3 ************************/ + 373 #ifdef UART3 + 374 void TX3_write2buff(u8 dat) //д뷢ͻ壬ָ+1 + 375 { + 376 1 TX3_Buffer[COM3.TX_write] = dat; //װͻ + 377 1 if(++COM3.TX_write >= COM_TX3_Lenth) COM3.TX_write = 0; + 378 1 + 379 1 if(COM3.B_TX_busy == 0) // + 380 1 { + 381 2 COM3.B_TX_busy = 1; //־æ + 382 2 SET_TI3(); //ж + 383 2 } + 384 1 } + 385 + 386 void PrintString3(u8 *puts) + 387 { + 388 1 for (; *puts != 0; puts++) TX3_write2buff(*puts); //ֹͣ0 + 389 1 } + 390 + 391 void Printbuffer3(u8 *puts,u8 len) + 392 { + 393 1 u8 i; + 394 1 for (i=0; i= COM_RX3_Lenth) COM3.RX_Cnt = 0; + 407 3 RX3_Buffer[COM3.RX_Cnt++] = S3BUF; + 408 3 COM3.RX_TimeOut = TimeOutSet3; + 409 3 } + 410 2 } + 411 1 + 412 1 if(TI3) //ɱ־λ + 413 1 { + 414 2 CLR_TI3(); + 415 2 if(COM3.TX_read != COM3.TX_write) + 416 2 { + 417 3 S3BUF = TX3_Buffer[COM3.TX_read]; + 418 3 if(++COM3.TX_read >= COM_TX3_Lenth) COM3.TX_read = 0; + 419 3 } + 420 2 else COM3.B_TX_busy = 0; + 421 2 } + 422 1 } + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 8 + + 423 #endif + 424 + 425 /********************* UART4 ************************/ + 426 #ifdef UART4 + void TX4_write2buff(u8 dat) //д뷢ͻ壬ָ+1 + { + TX4_Buffer[COM4.TX_write] = dat; //װͻ + if(++COM4.TX_write >= COM_TX4_Lenth) COM4.TX_write = 0; + + if(COM4.B_TX_busy == 0) // + { + COM4.B_TX_busy = 1; //־æ + SET_TI4(); //ж + } + } + + void PrintString4(u8 *puts) + { + for (; *puts != 0; puts++) TX4_write2buff(*puts); //ֹͣ0 + } + + void UART4_int (void) interrupt UART4_VECTOR + { + if(RI4) + { + CLR_RI4(); + if(COM4.B_RX_OK == 0) + { + if(COM4.RX_Cnt >= COM_RX4_Lenth) COM4.RX_Cnt = 0; + RX4_Buffer[COM4.RX_Cnt++] = S4BUF; + COM4.RX_TimeOut = TimeOutSet4; + } + } + + if(TI4) + { + CLR_TI4(); + if(COM4.TX_read != COM4.TX_write) + { + S4BUF = TX4_Buffer[COM4.TX_read]; + if(++COM4.TX_read >= COM_TX4_Lenth) COM4.TX_read = 0; + } + else COM4.B_TX_busy = 0; + } + } + #endif + 469 + 470 /*************** ڳʼ *****************/ + 471 void UART3_config(void) + 472 { + 473 1 COMx_InitDefine COMx_InitStructure; //ṹ + 474 1 COMx_InitStructure.UART_Mode = UART_8bit_BRTx; //ģʽ, UART_ShiftRight,UART_8bit_BRTx,UART_9bit,U + -ART_9bit_BRTx + 475 1 COMx_InitStructure.UART_BRT_Use = BRT_Timer3; //ʹò, BRT_Timer2, BRT_Timer3 (ע: 2̶ + -ʹBRT_Timer2) + 476 1 COMx_InitStructure.UART_BaudRate = 115200; //, 110 ~ 115200 + 477 1 COMx_InitStructure.UART_RxEnable = ENABLE; //, ENABLEDISABLE + 478 1 COMx_InitStructure.UART_Interrupt = ENABLE; //ж, ENABLEDISABLE + 479 1 COMx_InitStructure.UART_Priority = Priority_0; //ָжȼ(͵) Priority_0,Priority_1,Priori + -ty_2,Priority_3 + 480 1 COMx_InitStructure.UART_P_SW = UART3_SW_P50_P51; //л˿, UART3_SW_P00_P01,UART3_SW_P50_P51 + 481 1 UART_Configuration(UART3, &COMx_InitStructure); //ʼ3 UART1,UART2,UART3,UART4 + C51 COMPILER V9.01 UART 12/15/2025 20:45:03 PAGE 9 + + 482 1 + 483 1 //PrintString3("STC8 UART3 Test Programme!\r\n"); //UART3һַ + 484 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 1347 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 128 ---- + PDATA SIZE = ---- ---- + DATA SIZE = 20 27 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/UART_Set.lst b/Listings/UART_Set.lst new file mode 100644 index 0000000..dbc741a --- /dev/null +++ b/Listings/UART_Set.lst @@ -0,0 +1,657 @@ +C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE UART_SET +OBJECT MODULE PLACED IN .\Objects\UART_Set.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE UART_Set.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\ + -UART_Set.lst) OBJECT(.\Objects\UART_Set.obj) + +line level source + + 1 #include "UART_Set.h" + 2 #include "UART.h" + 3 #include "pwm_control.h" + 4 #include "string.h" + 5 #include "config.h" + 6 #include "timer.h" + 7 #include "STC8xxxx.h" + 8 #include "PWM15bit.h" + 9 + 10 G_Usart g_Usart; + 11 G_answer g_answer; + 12 S_recv s_recv; + 13 + 14 u8 debug = 0x00; + 15 + 16 + 17 /* + 18 жϽյָǷϷ + 19 */ + 20 void Usart_judge_Data(void) + 21 { + 22 1 u8 len = 0; + 23 1 u8 i, sum; + 24 1 sum = 0; + 25 1 g_Usart.ok_flag = 0; + 26 1 + 27 1 if((recv_start_flag==1)&&(systick_1ms-recv_time>8)) + 28 1 { + 29 2 recv_start_flag=0; + 30 2 #if DEBUG_ + { + for(i=0;i s_recv.B_max) + 130 5 { + 131 6 s_recv.B_Ch[i] = s_recv.B_max; + 132 6 } + 133 5 + 134 5 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_Ch[i] * PWM_MAX_VALUE * s_recv.global_ + -brightness / 100 / 100 * s_recv.key_status[i]; + 135 5 s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + 136 5 + 137 5 s_recv.gradual_time[i] = g_Usart.recv_buffer[9] * 10; /*յĽʱ*/ + 138 5 /* + 139 5 Ϊ + 140 5 */ + 141 5 if (s_recv.gradual_time[i] == 0) + 142 5 { + 143 6 s_recv.gradual_time[i] = 1; + 144 6 } + 145 5 + 146 5 /*10mspwmֵ*/ + 147 5 if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + 148 5 { + 149 6 s_pwm.every_change_10ms[i] = (float)(s_pwm.wanttopwm[i] - s_pwm.currpwm[i]) / s_ + -recv.gradual_time[i]; + 150 6 if (s_pwm.every_change_10ms[i] < 1) + 151 6 { + 152 7 s_pwm.every_change_10ms[i] = 1; + 153 7 } + 154 6 } + 155 5 + 156 5 if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + 157 5 { + 158 6 s_pwm.every_change_10ms[i] = (float)(s_pwm.currpwm[i] - s_pwm.wanttopwm[i]) / s_ + -recv.gradual_time[i]; + 159 6 if (s_pwm.every_change_10ms[i] < 1) + 160 6 { + 161 7 s_pwm.every_change_10ms[i] = 1; + 162 7 } + 163 6 } + 164 5 } + 165 4 } + 166 3 + 167 3 //ڶʹλ + 168 3 for (i = 0; i < 4; i++) + 169 3 { + 170 4 if (g_Usart.recv_buffer[8] & (1 << i)) + 171 4 { + 172 5 s_recv.flag1[i+8] = 1; + 173 5 s_recv.flag2[i+8] = 0; + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 4 + + 174 5 s_recv.B_Ch[i+8] = g_Usart.recv_buffer[13 - i]; + 175 5 + 176 5 if (s_recv.B_Ch[i+8] < s_recv.B_min) + 177 5 { + 178 6 s_recv.B_Ch[i+8] = s_recv.B_min; + 179 6 } + 180 5 + 181 5 if (s_recv.B_Ch[i+8] > s_recv.B_max) + 182 5 { + 183 6 s_recv.B_Ch[i+8] = s_recv.B_max; + 184 6 } + 185 5 + 186 5 s_pwm.wanttopwm[i+8] = PWM_MAX_VALUE - s_recv.B_Ch[i+8] * PWM_MAX_VALUE * s_recv.g + -lobal_brightness / 100 / 100 * s_recv.key_status[i+8]; + 187 5 s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + 188 5 + 189 5 s_recv.gradual_time[i+8] = g_Usart.recv_buffer[9] * 10; /*յĽʱ*/ + 190 5 + 191 5 /* + 192 5 Ϊ + 193 5 */ + 194 5 if (s_recv.gradual_time[i+8] == 0) + 195 5 { + 196 6 s_recv.gradual_time[i+8] = 1; + 197 6 } + 198 5 + 199 5 /*10mspwmֵ*/ + 200 5 if (s_pwm.wanttopwm[i+8] > s_pwm.currpwm[i+8]) + 201 5 { + 202 6 s_pwm.every_change_10ms[i+8] = (float)(s_pwm.wanttopwm[i+8] - s_pwm.currpwm[i+ + -8]) / s_recv.gradual_time[i+8]; + 203 6 if (s_pwm.every_change_10ms[i+8] < 1) + 204 6 { + 205 7 s_pwm.every_change_10ms[i+8] = 1; + 206 7 } + 207 6 } + 208 5 + 209 5 + 210 5 if (s_pwm.wanttopwm[i+8] < s_pwm.currpwm[i+8]) + 211 5 { + 212 6 s_pwm.every_change_10ms[i+8] = (float)(s_pwm.currpwm[i+8] - s_pwm.wanttopwm[i + -+8]) / s_recv.gradual_time[i+8]; + 213 6 if (s_pwm.every_change_10ms[i+8] < 1) + 214 6 { + 215 7 s_pwm.every_change_10ms[i+8] = 1; + 216 7 } + 217 6 } + 218 5 } + 219 4 } + 220 3 + 221 3 g_answer.short_answer_flag=0x01; + 222 3 break; + 223 3 + 224 3 + 225 3 //ģʽݼѭ + 226 3 case USART_CMD_SET_MODE: + 227 3 g_answer.short_answer[UART_FMT_CMD]=USART_CMD_SET_MODE_A; + 228 3 if(debug) + 229 3 { + 230 4 PrintString1("change light"); + 231 4 } + 232 3 + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 5 + + 233 3 for (i = 0; i < 8; i++) + 234 3 { + 235 4 if (g_Usart.recv_buffer[7] & (1 << i)) + 236 4 { + 237 5 s_recv.flag1[i] = 0; + 238 5 s_recv.flag2[i] = 1; + 239 5 s_recv.mode[i] = g_Usart.recv_buffer[9]; + 240 5 s_recv.pwm_step[i] = g_Usart.recv_buffer[11]; + 241 5 + 242 5 if (s_recv.mode[i] == 0x00) + 243 5 { + 244 6 if (g_Usart.recv_buffer[10] == 0x00) + 245 6 { + 246 7 s_recv.forward[i] = 0; + 247 7 } + 248 6 + 249 6 if (g_Usart.recv_buffer[10] == 0x01) + 250 6 { + 251 7 s_recv.forward[i] = 1; + 252 7 } + 253 6 + 254 6 if (g_Usart.recv_buffer[10] == 0x02) //ת + 255 6 { + 256 7 if (s_recv.forward[i] == 0x01) + 257 7 { + 258 8 s_recv.forward[i] = 0x00; + 259 8 continue; // Ϊֹתֱ֮ӽһ״̬ + 260 8 } + 261 7 + 262 7 if (s_recv.forward[i] == 0x00) + 263 7 { + 264 8 s_recv.forward[i] = 0x01; + 265 8 continue; + 266 8 } + 267 7 } + 268 6 } + 269 5 } + 270 4 } + 271 3 + 272 3 + 273 3 for (i = 0; i < 4; i++) + 274 3 { + 275 4 if (g_Usart.recv_buffer[8] & (1 << i)) + 276 4 { + 277 5 s_recv.flag1[i+8] = 0; + 278 5 s_recv.flag2[i+8] = 1; + 279 5 s_recv.mode[i+8] = g_Usart.recv_buffer[9]; + 280 5 s_recv.pwm_step[i+8] = g_Usart.recv_buffer[11]; + 281 5 + 282 5 if (s_recv.mode[i+8] == 0x00) + 283 5 { + 284 6 if (g_Usart.recv_buffer[10] == 0x00) + 285 6 { + 286 7 s_recv.forward[i+8] = 0; + 287 7 } + 288 6 + 289 6 if (g_Usart.recv_buffer[10] == 0x01) + 290 6 { + 291 7 s_recv.forward[i+8] = 1; + 292 7 } + 293 6 + 294 6 if (g_Usart.recv_buffer[10] == 0x02) //ת + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 6 + + 295 6 { + 296 7 if (s_recv.forward[i+8] == 0x01) + 297 7 { + 298 8 s_recv.forward[i+8] = 0x00; + 299 8 continue; // Ϊֹתֱ֮ӽһ״̬ + 300 8 } + 301 7 + 302 7 if (s_recv.forward[i+8] == 0x00) + 303 7 { + 304 8 s_recv.forward[i+8] = 0x01; + 305 8 continue; + 306 8 } + 307 7 } + 308 6 } + 309 5 } + 310 4 } + 311 3 g_answer.short_answer_flag=0x01; + 312 3 break; + 313 3 + 314 3 + 315 3 // + 316 3 case USART_CMD_ALL_BRIGHTNESS: + 317 3 g_answer.short_answer[UART_FMT_CMD]=USART_CMD_ALL_BRIGHTNESS_A; + 318 3 + 319 3 if(debug) + 320 3 { + 321 4 PrintString1("global light"); + 322 4 } + 323 3 + 324 3 // s_recv.changeflag = 1; + 325 3 if (g_Usart.recv_buffer[7] & (1 << 5)) //ȫֿɵ + 326 3 { + 327 4 s_recv.B_min = g_Usart.recv_buffer[10]; + 328 4 for (i = 0; i < 12; i++) + 329 4 { + 330 5 if ( s_pwm.currvalue[i] < s_recv.B_min) + 331 5 { + 332 6 s_pwm.currvalue[i] = s_recv.B_min; + 333 6 } + 334 5 } + 335 4 } + 336 3 + 337 3 if (g_Usart.recv_buffer[7] & (1 << 6)) //ȫֿɵ + 338 3 { + 339 4 s_recv.B_max = g_Usart.recv_buffer[9]; + 340 4 for (i = 0; i < 12; i++) + 341 4 { + 342 5 if ( s_pwm.currvalue[i] > s_recv.B_max) + 343 5 { + 344 6 s_pwm.currvalue[i] = s_recv.B_max; + 345 6 } + 346 5 } + 347 4 } + 348 3 + 349 3 if (g_Usart.recv_buffer[7] & (1 << 7)) //ȫ + 350 3 { + 351 4 s_recv.global_brightness = g_Usart.recv_buffer[8]; + 352 4 + 353 4 for (i = 0; i < 12; i++) + 354 4 { + 355 5 // s_pwm.wanttopwmflash[i] = PWM_MAX_VALUE - s_pwm.currvalue[i] * PWM_MAX_VALUE * + -s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 7 + + 356 5 + 357 5 s_recv.flag1[i] = 1; + 358 5 s_recv.flag2[i] = 0; + 359 5 + 360 5 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_Ch[i] * PWM_MAX_VALUE * s_recv.glo + -bal_brightness / 100 / 100 * s_recv.key_status[i]; + 361 5 s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + 362 5 if(s_pwm.wanttopwm[i] > PWM_MAX_VALUE) + 363 5 { + 364 6 s_pwm.wanttopwm[i] = PWM_MAX_VALUE; + 365 6 } + 366 5 + 367 5 /*10mspwmֵ*/ + 368 5 if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + 369 5 { + 370 6 s_pwm.every_change_10ms[i] = (float)(s_pwm.wanttopwm[i] - s_pwm.currpwm[i]) + -/ s_recv.gradual_time[i]; + 371 6 if (s_pwm.every_change_10ms[i] < 1) + 372 6 { + 373 7 s_pwm.every_change_10ms[i] = 1; + 374 7 } + 375 6 } + 376 5 + 377 5 if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + 378 5 { + 379 6 s_pwm.every_change_10ms[i] = (float)(s_pwm.currpwm[i] - s_pwm.wanttopwm[i]) + -/ s_recv.gradual_time[i]; + 380 6 if (s_pwm.every_change_10ms[i] < 1) + 381 6 { + 382 7 s_pwm.every_change_10ms[i] = 1; + 383 7 } + 384 6 } + 385 5 } + 386 4 } + 387 3 + 388 3 + 389 3 g_answer.short_answer_flag=0x01; + 390 3 break; + 391 3 + 392 3 + 393 3 //ÿ״̬ + 394 3 case USART_CMD_SWITCH_STATUS: + 395 3 g_answer.short_answer[UART_FMT_CMD]=USART_CMD_SWITCH_STATUS_A; + 396 3 if(debug) + 397 3 { + 398 4 PrintString1("switch state"); + 399 4 } + 400 3 + 401 3 for (i = 0; i < 8; i++) + 402 3 { + 403 4 if (g_Usart.recv_buffer[7] & (1 << i)) + 404 4 { + 405 5 if (g_Usart.recv_buffer[9 + i] == 0x01) + 406 5 { + 407 6 s_recv.key_status[i] = 0x01; + 408 6 //s_pwm.currvalue[i] = s_pwm.thenvalue[i]; + 409 6 Open_Light(i); + 410 6 } + 411 5 + 412 5 if (g_Usart.recv_buffer[9 + i] == 0x00) + 413 5 { + 414 6 //s_pwm.thenvalue[i] = s_pwm.currvalue[i]; + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 8 + + 415 6 Close_Light(i); + 416 6 s_recv.flag1[i] = 0; + 417 6 s_recv.flag2[i] = 0; + 418 6 s_recv.mode[i] = 2; + 419 6 s_recv.key_status[i] = 0x00; + 420 6 } + 421 5 + 422 5 if (g_Usart.recv_buffer[9 + i] == 0x02) + 423 5 { + 424 6 if (s_recv.key_status[i] == 0x00) + 425 6 { + 426 7 s_recv.key_status[i] = 0x01; + 427 7 //s_pwm.currvalue[i] = s_pwm.thenvalue[i]; + 428 7 Open_Light(i); + 429 7 continue; + 430 7 } + 431 6 + 432 6 if (s_recv.key_status[i] == 0x01) + 433 6 { + 434 7 //s_pwm.thenvalue[i] = s_pwm.currvalue[i]; + 435 7 Close_Light(i); + 436 7 s_recv.flag1[i] = 0; + 437 7 s_recv.flag2[i] = 0; + 438 7 s_recv.mode[i] = 2; + 439 7 s_recv.key_status[i] = 0x00; + 440 7 continue; + 441 7 } + 442 6 } + 443 5 } + 444 4 } + 445 3 + 446 3 + 447 3 for (i = 0; i < 4; i++) + 448 3 { + 449 4 if (g_Usart.recv_buffer[8] & (1 << i)) + 450 4 { + 451 5 if (g_Usart.recv_buffer[9 + 8 + i] == 0x01) + 452 5 { + 453 6 s_recv.key_status[i+8] = 0x01; + 454 6 //s_pwm.currvalue[i+8] = s_pwm.thenvalue[i]; + 455 6 Open_Light(i+8); + 456 6 } + 457 5 + 458 5 if (g_Usart.recv_buffer[9 +8 + i] == 0x00) + 459 5 { + 460 6 //s_pwm.thenvalue[i+8] = s_pwm.currvalue[i+8]; + 461 6 Close_Light(i+8); + 462 6 s_recv.flag1[i+8] = 0; + 463 6 s_recv.flag2[i+8] = 0; + 464 6 s_recv.mode[i+8] = 2; + 465 6 s_recv.key_status[i+8] = 0x00; + 466 6 } + 467 5 + 468 5 if (g_Usart.recv_buffer[9 + 8 + i] == 0x02) + 469 5 { + 470 6 if (s_recv.key_status[i+8] == 0x00) + 471 6 { + 472 7 s_recv.key_status[i+8] = 0x01; + 473 7 //s_pwm.currvalue[i+8] = s_pwm.thenvalue[i]; + 474 7 Open_Light(i+8); + 475 7 continue; + 476 7 } + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 9 + + 477 6 + 478 6 + 479 6 if (s_recv.key_status[i+8] == 0x01) + 480 6 { + 481 7 //s_pwm.thenvalue[i+8] = s_pwm.currvalue[i+8]; + 482 7 Close_Light(i+8); + 483 7 s_recv.flag1[i+8] = 0; + 484 7 s_recv.flag2[i+8] = 0; + 485 7 s_recv.mode[i+8] = 2; + 486 7 s_recv.key_status[i+8] = 0x00; + 487 7 continue; + 488 7 } + 489 6 } + 490 5 } + 491 4 } + 492 3 g_answer.short_answer_flag=0x01; + 493 3 break; + 494 3 case USART_CMD_DEBUG_SET: + 495 3 g_answer.short_answer[UART_FMT_CMD]=USART_CMD_DEBUG_SET_A; + 496 3 if(debug) + 497 3 { + 498 4 PrintString1("debug"); + 499 4 } + 500 3 debug = g_Usart.recv_buffer[7]; + 501 3 g_answer.short_answer_flag=0x01; + 502 3 break; + 503 3 case Usart_CMD_Version: + 504 3 g_answer.version_answer[UART_FMT_CMD]=Usart_CMD_Version_A; + 505 3 g_answer.version_answer_flag=0x01; + 506 3 if(debug) + 507 3 { + 508 4 PrintString1("version"); + 509 4 } + 510 3 break; + 511 3 } + 512 2 g_Usart.ok_flag=0; + 513 2 } + 514 1 } + 515 + 516 void Usart_answer(void) + 517 { + 518 1 u8 i=0; + 519 1 u8 checksum=0; + 520 1 if(g_answer.long_answer_flag) + 521 1 { + 522 2 g_answer.long_answer[UART_FMT_ADDR_TX]=ADDR_RX; + 523 2 g_answer.long_answer[UART_FMT_TYPE]=g_Usart.Sn; + 524 2 g_answer.long_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + 525 2 g_answer.long_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + 526 2 g_answer.long_answer[UART_FMT_LEN]=0x14; + 527 2 g_answer.long_answer[7] = s_recv.global_brightness; + 528 2 for(i=0;i<12;i++) + 529 2 { + 530 3 g_answer.long_answer[8+i] = s_pwm.currvalue[11-i]; + 531 3 if(s_recv.key_status[i] == 0x01) + 532 3 { + 533 4 g_answer.long_answer[8+i] |= 0x80; + 534 4 } + 535 3 } + 536 2 checksum=sumfunc(g_answer.long_answer,0x14); + 537 2 g_answer.long_answer[UART_FMT_CKS]=checksum; + 538 2 + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 10 + + 539 2 Printbuffer3(g_answer.long_answer,0x14); //3ӡ + 540 2 + 541 2 if(debug) + 542 2 { + 543 3 // PrintString1("long answer"); + 544 3 } + 545 2 g_answer.long_answer_flag=0; + 546 2 memset(g_Usart.recv_buffer,0,32); + 547 2 } + 548 1 if(g_answer.short_answer_flag) + 549 1 { + 550 2 g_answer.short_answer[UART_FMT_ADDR_TX]=ADDR_RX; + 551 2 g_answer.short_answer[UART_FMT_TYPE]=g_Usart.Sn; + 552 2 g_answer.short_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + 553 2 g_answer.short_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + 554 2 g_answer.short_answer[UART_FMT_LEN]=0x07; + 555 2 checksum=sumfunc(g_answer.short_answer,0x07); + 556 2 g_answer.short_answer[UART_FMT_CKS]=checksum; + 557 2 Printbuffer3(g_answer.short_answer,0x07); + 558 2 if(debug) + 559 2 { + 560 3 PrintString1("short answer"); + 561 3 } + 562 2 + 563 2 + 564 2 g_answer.short_answer_flag=0; + 565 2 memset(g_Usart.recv_buffer,0,32); + 566 2 } + 567 1 + 568 1 if(g_answer.version_answer_flag) + 569 1 { + 570 2 g_answer.version_answer[UART_FMT_ADDR_TX]=ADDR_RX; + 571 2 g_answer.version_answer[UART_FMT_TYPE]=g_Usart.Sn; + 572 2 g_answer.version_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + 573 2 g_answer.version_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + 574 2 g_answer.version_answer[UART_FMT_LEN]=0x09; + 575 2 g_answer.version_answer[UART_FMT_CMD+1]=Version_High; + 576 2 g_answer.version_answer[UART_FMT_CMD+2]=Version_Low; + 577 2 + 578 2 checksum=sumfunc(g_answer.version_answer,0x09); + 579 2 g_answer.version_answer[UART_FMT_CKS]=checksum; + 580 2 Printbuffer3(g_answer.version_answer,0x09); + 581 2 if(debug) + 582 2 { + 583 3 PrintString1("version_answer"); + 584 3 } + 585 2 g_answer.version_answer_flag=0; + 586 2 memset(g_Usart.recv_buffer,0,32); + 587 2 } + 588 1 memset(&g_answer,0,sizeof(g_answer)); + 589 1 } + 590 + 591 u8 sumfunc(u8* answer,u8 len) + 592 { + 593 1 u8 m = 0; + 594 1 u8 j; + 595 1 for (j = 0; j < len; j++) + 596 1 { + 597 2 if (5 == j) continue; + 598 2 m += *(answer+j); + 599 2 } + 600 1 return ~m; + C51 COMPILER V9.01 UART_SET 12/15/2025 20:45:04 PAGE 11 + + 601 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 4719 ---- + CONSTANT SIZE = 101 ---- + XDATA SIZE = 272 ---- + PDATA SIZE = ---- ---- + DATA SIZE = 1 7 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/WDT.lst b/Listings/WDT.lst new file mode 100644 index 0000000..30367ae --- /dev/null +++ b/Listings/WDT.lst @@ -0,0 +1,60 @@ +C51 COMPILER V9.01 WDT 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE WDT +OBJECT MODULE PLACED IN .\Objects\WDT.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE WDT.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\WDT.l + -st) OBJECT(.\Objects\WDT.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 #include "WDT.h" + 14 + 15 //======================================================================== + 16 // : void WDT_Inilize(WDT_InitTypeDef *WDT) + 17 // : Źʼ. + 18 // : WDT: ṹ,οWDT.hĶ. + 19 // : none. + 20 // 汾: V1.0, 2020-09-16 + 21 //======================================================================== + 22 void WDT_Inilize(WDT_InitTypeDef *WDT) + 23 { + 24 1 if(WDT->WDT_Enable == ENABLE) WDT_CONTR = D_EN_WDT; //ʹܿŹ + 25 1 + 26 1 WDT_PS_Set(WDT->WDT_PS); //ŹʱʱӷƵϵ WDT_SCALE_2,WDT_SCALE_4,WDT_SCALE_8,WDT_SCALE_16,WDT + -_SCALE_32,WDT_SCALE_64,WDT_SCALE_128,WDT_SCALE_256 + 27 1 if(WDT->WDT_IDLE_Mode == WDT_IDLE_STOP) WDT_CONTR &= ~0x08; //IDLEģʽֹͣ + 28 1 else WDT_CONTR |= 0x08; //IDLEģʽ + 29 1 } + 30 + 31 /********************* Ź *************************/ + 32 void WDT_Clear (void) + 33 { + 34 1 WDT_CONTR |= D_CLR_WDT; // ι + 35 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 45 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/key.lst b/Listings/key.lst new file mode 100644 index 0000000..3dd4669 --- /dev/null +++ b/Listings/key.lst @@ -0,0 +1,183 @@ +C51 COMPILER V9.01 KEY 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE KEY +OBJECT MODULE PLACED IN .\Objects\key.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE key.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\key.l + -st) OBJECT(.\Objects\key.obj) + +line level source + + 1 #include "key.h" + 2 #include "GPIO.h" + 3 #include "timer.h" + 4 #include "string.h" + 5 #include "pwm_control.h" + 6 KEY_t g_Key; + 7 + 8 void Key_Init(void) + 9 { + 10 1 GPIO_InitTypeDef GPIO_InitStructure1; //ṹ + 11 1 /***********************************1*******************************************/ + 12 1 GPIO_InitStructure1.Pin = GPIO_Pin_4; //ָҪʼIO 4 + 13 1 GPIO_InitStructure1.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp + 14 1 GPIO_Inilize(GPIO_P4,&GPIO_InitStructure1); //ʼ + 15 1 memset(&g_Key, 0, sizeof(g_Key)); + 16 1 } + 17 + 18 void Key_ScanTask(void) + 19 { + 20 1 u8 i; + 21 1 static u32 update_10ms = 0; + 22 1 + 23 1 if (systick_1ms - update_10ms > 10) + 24 1 { + 25 2 update_10ms = systick_1ms; + 26 2 + 27 2 for (i = 0; i < KEY_CHN_MAX; i++) + 28 2 { + 29 3 switch (g_Key.KEY_STA[i]) + 30 3 { + 31 4 case KEY_STA_S0: + 32 4 if ( P44 == KEY_PRESS ) + 33 4 { + 34 5 if (g_Key.delayCnt[i] < KEY_DELAY_COUNT) + 35 5 { + 36 6 g_Key.delayCnt[i]++; + 37 6 } + 38 5 else + 39 5 { + 40 6 g_Key.KEY_STA[i] = KEY_STA_S1; // + 41 6 g_Key.key_time[i] = 0; + 42 6 g_Key.delayCnt[i] = 0; + 43 6 } + 44 5 } + 45 4 else + 46 4 { + 47 5 g_Key.delayCnt[i] = 0; + 48 5 g_Key.KEY_STA[i] = KEY_STA_S0; + 49 5 g_Key.key_val[i] = KEY_VAL_NOT; + 50 5 } + 51 4 break; + 52 4 case KEY_STA_S1: + 53 4 g_Key.key_time[i] ++; + 54 4 if ( g_Key.key_time[i] < KEY_DELAY_COUNT_LONG ) + C51 COMPILER V9.01 KEY 12/15/2025 20:45:04 PAGE 2 + + 55 4 { + 56 5 if ( P44 == KEY_LOOSEN ) //ɿ + 57 5 { + 58 6 g_Key.key_val[i] = KEY_VAL_SHORT_PRESS; //̰ɿ + 59 6 g_Key.key_time[i] = 0; + 60 6 g_Key.KEY_STA[i] = KEY_STA_S0; + 61 6 } + 62 5 } + 63 4 else + 64 4 { + 65 5 g_Key.KEY_STA[i] = KEY_STA_S2; + 66 5 g_Key.key_time[i] = 0; + 67 5 g_Key.key_longPress[i] = KEY_VAL_SINGLE_LONG_PRESS; // + 68 5 g_Key.key_val[i] = KEY_VAL_CONT_LONG_PRESS; // + 69 5 } + 70 4 break; + 71 4 + 72 4 case KEY_STA_S2: + 73 4 g_Key.key_longPress[i] = KEY_VAL_NOT; + 74 4 if ( P44 == KEY_LOOSEN ) + 75 4 { + 76 5 g_Key.KEY_STA[i] = KEY_STA_S0; + 77 5 g_Key.key_val[i] = KEY_VAL_LONG_PRESS_LOOSEN; //ɿ + 78 5 } + 79 4 break; + 80 4 } + 81 3 } + 82 2 } + 83 1 } + 84 + 85 + 86 void KEY_TEST(void) + 87 { + 88 1 u8 flag; + 89 1 if (g_Key.key_val[KEY_CH1] == KEY_VAL_SHORT_PRESS) + 90 1 { + 91 2 g_Key.key_val[KEY_CH1] = KEY_VAL_NOT; + 92 2 s_pwm.key_value++; + 93 2 switch (s_pwm.key_value) + 94 2 { + 95 3 case 1: + 96 3 s_pwm.currpwm[0] = 2000ul; //90% + 97 3 s_pwm.currvalue[0]=0x5A; + 98 3 break; + 99 3 case 2: + 100 3 s_pwm.currpwm[1] = 2000ul; + 101 3 s_pwm.currvalue[1]=0x5A; + 102 3 break; + 103 3 case 3: + 104 3 s_pwm.currpwm[2] = 2000ul; + 105 3 s_pwm.currvalue[2]=0x5A; + 106 3 break; + 107 3 case 4: + 108 3 s_pwm.currpwm[3] = 2000ul; + 109 3 s_pwm.currvalue[3]=0x5A; + 110 3 break; + 111 3 case 5: + 112 3 s_pwm.currpwm[4] = 2000ul; + 113 3 s_pwm.currvalue[4]=0x5A; + 114 3 break; + 115 3 case 6: + 116 3 s_pwm.currpwm[5] = 2000ul; + C51 COMPILER V9.01 KEY 12/15/2025 20:45:04 PAGE 3 + + 117 3 s_pwm.currvalue[5]=0x5A; + 118 3 break; + 119 3 case 7: + 120 3 s_pwm.currpwm[6] = 2000ul; + 121 3 s_pwm.currvalue[6]=0x5A; + 122 3 break; + 123 3 case 8: + 124 3 s_pwm.currpwm[7] = 2000ul; + 125 3 s_pwm.currvalue[7]=0x5A; + 126 3 break; + 127 3 case 9: + 128 3 s_pwm.currpwm[8] = 2000ul; + 129 3 s_pwm.currvalue[8]=0x5A; + 130 3 break; + 131 3 case 10: + 132 3 s_pwm.currpwm[9] = 2000ul; + 133 3 s_pwm.currvalue[9]=0x5A; + 134 3 break; + 135 3 case 11: + 136 3 s_pwm.currpwm[10] = 2000ul; + 137 3 s_pwm.currvalue[10]=0x5A; + 138 3 break; + 139 3 case 12: + 140 3 s_pwm.currpwm[11] = 2000ul; + 141 3 s_pwm.currvalue[11]=0x5A; + 142 3 break; + 143 3 case 13: + 144 3 for(flag=0;flag<12;flag++) + 145 3 { + 146 4 s_pwm.currpwm[flag] = PWM_MAX_VALUE; + 147 4 s_pwm.currvalue[flag]=0x00; + 148 4 } + 149 3 s_pwm.key_value = 0; + 150 3 break; + 151 3 default: + 152 3 break; + 153 3 } + 154 2 } + 155 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 553 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = 10 2 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/main.lst b/Listings/main.lst new file mode 100644 index 0000000..9598aa2 --- /dev/null +++ b/Listings/main.lst @@ -0,0 +1,162 @@ +C51 COMPILER V9.01 MAIN 12/15/2025 20:45:03 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE MAIN +OBJECT MODULE PLACED IN .\Objects\main.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE main.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\main + -.lst) OBJECT(.\Objects\main.obj) + +line level source + + 1 #include "config.h" + 2 #include "gpio.h" + 3 #include "UART.h" + 4 #include "string.h" + 5 #include "UART_Set.h" + 6 #include "pwm_control.h" + 7 #include "Start_Init.h" + 8 #include "key.h" + 9 #include "WDT.h" + 10 /************* ˵ ************** + 11 + 12 ̻STC8H8K64UΪоƬʵ8бдԣSTC8GSTC8HϵоƬͨòο. + 13 + 14 ˫ȫ˫жϷʽշͨѶ + 15 + 16 ͨPCMCU, MCUյͨڰյԭ, Ĭϲʣ115200,N,8,1. + 17 + 18 ͨ UART.h ͷļ UART1~UART4 壬ͬͨĴͨš + 19 + 20 öʱʷʹ1Tģʽ(ǵͲ12T)ѡɱʱƵʣ߾ȡ + 21 + 22 ʱ, ѡʱ 22.1184MHz (ļ"config.h"޸). + 23 + 24 + 25 /******************* IOú *******************/ + 26 + 27 + 28 void GPIO1_config(void) + 29 { + 30 1 GPIO_InitTypeDef GPIO_InitStructure; //ṹ + 31 1 + 32 1 GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + 33 1 GPIO_InitStructure.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_O + -UT_PP + 34 1 GPIO_Inilize(GPIO_P3,&GPIO_InitStructure); //ʼ + 35 1 } + 36 + 37 /*************** ڳʼ *****************/ + 38 void UART1_config(void) + 39 { + 40 1 COMx_InitDefine COMx_InitStructure; //ṹ + 41 1 COMx_InitStructure.UART_Mode = UART_8bit_BRTx; //ģʽ, UART_ShiftRight,UART_8bit_BRTx,UART_9bit,UART + -_9bit_BRTx + 42 1 COMx_InitStructure.UART_BRT_Use = BRT_Timer1; //ʹò, BRT_Timer1, BRT_Timer2 (ע: 2̶ʹ + -BRT_Timer2) + 43 1 COMx_InitStructure.UART_BaudRate = 115200; //, һ 110 ~ 115200 + 44 1 COMx_InitStructure.UART_RxEnable = ENABLE; //, ENABLEDISABLE + 45 1 COMx_InitStructure.BaudRateDouble = DISABLE; //ʼӱ, ENABLEDISABLE + 46 1 COMx_InitStructure.UART_Interrupt = ENABLE; //ж, ENABLEDISABLE + 47 1 COMx_InitStructure.UART_Priority = Priority_0; //ָжȼ(͵) Priority_0,Priority_1,Priori + -ty_2,Priority_3 + 48 1 COMx_InitStructure.UART_P_SW = UART1_SW_P30_P31; //л˿, UART1_SW_P30_P31,UART1_SW_P36_P37,UAR + -T1_SW_P16_P17,UART1_SW_P43_P44 + 49 1 UART_Configuration(UART1, &COMx_InitStructure); //ʼ1 UART1,UART2,UART3,UART4 + C51 COMPILER V9.01 MAIN 12/15/2025 20:45:03 PAGE 2 + + 50 1 + 51 1 //PrintString1("STC8H8K64U UART1 Test Programme!\r\n"); //UART1һַ + 52 1 } + 53 + 54 /********************WDT INT ********************/ + 55 void WDT_config(void) + 56 { + 57 1 WDT_InitTypeDef WDT_InitStructure; //ṹ + 58 1 + 59 1 WDT_InitStructure.WDT_Enable = ENABLE; //жʹ ENABLEDISABLE + 60 1 WDT_InitStructure.WDT_IDLE_Mode = WDT_IDLE_STOP; //IDLEģʽǷֹͣ WDT_IDLE_STOP,WDT_IDLE_RUN + 61 1 WDT_InitStructure.WDT_PS = WDT_SCALE_32; //ŹʱʱӷƵϵ WDT_SCALE_2,WDT_SCALE_4,WDT + -_SCALE_8,WDT_SCALE_16,WDT_SCALE_32,WDT_SCALE_64,WDT_SCALE_128,WDT_SCALE_256 + 62 1 WDT_Inilize(&WDT_InitStructure); //ʼ + 63 1 } + 64 + 65 u8 count_flag=0; + 66 void main(void) + 67 { + 68 1 GPIO_config(); + 69 1 UART3_config(); + 70 1 Start_Init(); + 71 1 pwm_config(); + 72 1 Timer2_Init_1ms(); + 73 1 Key_Init(); + 74 1 GPIO1_config(); + 75 1 UART1_config(); + 76 1 WDT_config(); //Ź629msλ + 77 1 + 78 1 PCON &= ~POF; //LVDжϱ־λ + 79 1 RSTCFG = 0x41; //LVD:2.4Vѹλ + 80 1 EA = 1; + 81 1 + 82 1 if(debug) + 83 1 { + 84 2 PrintString1("MCU Start"); + 85 2 } + 86 1 + 87 1 while (1) + 88 1 { + 89 2 WDT_Clear(); //幷 + 90 2 count_flag++; + 91 2 + 92 2 //Ϊ˱֤ijѹ2.2V + 93 2 if(count_flag==1) + 94 2 { + 95 3 P10=1; + 96 3 } + 97 2 if(count_flag==8) + 98 2 { + 99 3 P10=0; + 100 3 } + 101 2 if(count_flag==10) + 102 2 { + 103 3 count_flag=0; + 104 3 } + 105 2 + 106 2 Usart_judge_Data(); + 107 2 + 108 2 Usart_Deal_Data(); + 109 2 + 110 2 deal_command1(); + C51 COMPILER V9.01 MAIN 12/15/2025 20:45:03 PAGE 3 + + 111 2 + 112 2 deal_command2(); + 113 2 + 114 2 // checkpwm(); + 115 2 + 116 2 show_light(); + 117 2 + 118 2 Usart_answer(); + 119 2 + 120 2 Key_ScanTask(); + 121 2 + 122 2 KEY_TEST(); + 123 2 + 124 2 } + 125 1 } + 126 + 127 + 128 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 175 ---- + CONSTANT SIZE = 10 ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = 1 17 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/pwm_control.lst b/Listings/pwm_control.lst new file mode 100644 index 0000000..33bf1e5 --- /dev/null +++ b/Listings/pwm_control.lst @@ -0,0 +1,421 @@ +C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE PWM_CONTROL +OBJECT MODULE PLACED IN .\Objects\pwm_control.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE pwm_control.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listin + -gs\pwm_control.lst) OBJECT(.\Objects\pwm_control.obj) + +line level source + + 1 #include "pwm_control.h" + 2 #include "GPIO.h" + 3 #include "STC8xxxx.h" + 4 #include "PWM15bit.h" + 5 #include "timer.h" + 6 #include "UART_Set.h" + 7 #include "string.h" + 8 S_PWM s_pwm; + 9 /* + 10 *1.5.0/5.1ijʼ + 11 *2.ʼPWM + 12 *3.LED_DRV_12V_ENõƬ + 13 */ + 14 /******************* IOú *******************/ + 15 void GPIO_config(void) + 16 { + 17 1 GPIO_InitTypeDef GPIO_InitStructure; //ṹ + 18 1 /***********************************1*******************************************/ + 19 1 GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + 20 1 GPIO_InitStructure.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_O + -UT_PP + 21 1 GPIO_Inilize(GPIO_P5,&GPIO_InitStructure); //ʼ + 22 1 + 23 1 /***********************************2*******************************************/ + 24 1 GPIO_InitStructure.Pin = GPIO_Pin_All; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + 25 1 GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_O + -UT_PP + 26 1 GPIO_Inilize(GPIO_P0,&GPIO_InitStructure); //ʼ + 27 1 + 28 1 GPIO_InitStructure.Pin = GPIO_Pin_Left; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + 29 1 GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_O + -UT_PP + 30 1 GPIO_Inilize(GPIO_P2,&GPIO_InitStructure); //ʼ + 31 1 + 32 1 /***********************************3*******************************************/ + 33 1 GPIO_InitStructure.Pin = GPIO_Pin_0; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + 34 1 GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_O + -UT_PP + 35 1 GPIO_Inilize(GPIO_P1,&GPIO_InitStructure); //ʼ + 36 1 } + 37 + 38 void pwm_config(void) + 39 { + 40 1 u8 i; + 41 1 PWM15_InitTypeDef PWM15_InitStructure; + 42 1 + 43 1 PWM15_InitStructure.PWM_Enable = ENABLE; //PWMʹ, ENABLE, DISABLE + 44 1 PWM15_InitStructure.PWM_Period = 0x04E2; //PWM, 1250,ƵΪ16khz + 45 1 PWM15_InitStructure.PWM_Clock_Sel = PWMn_CLK_SYS; //ʱԴѡ, PWMn_CLK_SYS, PWMn_CLK_TM2 + 46 1 PWM15_InitStructure.PWM_Clock_PS = 0; //ϵͳʱӷƵ(PS+1Ƶ), 0~15 + 47 1 PWM15_InitStructure.PWM_Counter = ENABLE; //ʹ, ENABLE, DISABLE + 48 1 + 49 1 PWM15_Init(PWM0,&PWM15_InitStructure); //ʼPWM0 + 50 1 PWM15_Init(PWM2,&PWM15_InitStructure); //ʼPWM2 + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 2 + + 51 1 + 52 1 PWM15Duty(PWM00,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + 53 1 PWM15Duty(PWM01,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + 54 1 PWM15Duty(PWM02,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + 55 1 PWM15Duty(PWM03,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + 56 1 PWM15Duty(PWM04,initial_Val); + 57 1 PWM15Duty(PWM05,initial_Val); + 58 1 PWM15Duty(PWM06,initial_Val); + 59 1 PWM15Duty(PWM07,initial_Val); + 60 1 + 61 1 PWM15Duty(PWM20,initial_Val); + 62 1 PWM15Duty(PWM21,initial_Val); + 63 1 PWM15Duty(PWM22,initial_Val); + 64 1 PWM15Duty(PWM23,initial_Val); + 65 1 + 66 1 memset(&s_pwm,0,sizeof(s_pwm)); + 67 1 for(i=0;i<12;i++) + 68 1 { + 69 2 s_pwm.currpwm[i]=initial_Val; + 70 2 } + 71 1 PWMChannelCtrl(PWM00,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 72 1 PWMChannelCtrl(PWM01,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 73 1 PWMChannelCtrl(PWM02,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 74 1 PWMChannelCtrl(PWM03,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 75 1 PWMChannelCtrl(PWM04,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 76 1 PWMChannelCtrl(PWM05,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 77 1 PWMChannelCtrl(PWM06,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 78 1 PWMChannelCtrl(PWM07,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 79 1 + 80 1 PWMChannelCtrl(PWM20,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 81 1 PWMChannelCtrl(PWM21,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 82 1 PWMChannelCtrl(PWM22,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 83 1 PWMChannelCtrl(PWM23,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶ + -ж, һж + 84 1 + 85 1 } + 86 + 87 + 88 //10msһ + 89 void deal_command1(void) + 90 { + 91 1 int i=0; + 92 1 static u32 systick_command1 = 0; + 93 1 + 94 1 if (systick_1ms - systick_command1 >= 10) + 95 1 { + 96 2 systick_command1 = systick_1ms; + 97 2 for (i = 0; i < 12; i++) + 98 2 { + 99 3 if (s_recv.flag1[i]) + 100 3 { + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 3 + + 101 4 if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + 102 4 { + 103 5 //s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; + 104 5 s_pwm.doublecurrpwm[i] += s_pwm.every_change_10ms[i]; + 105 5 s_pwm.currpwm[i] = (u16)s_pwm.doublecurrpwm[i]; + 106 5 + 107 5 if(s_recv.global_brightness==0) + 108 5 { + 109 6 s_pwm.currvalue[i]=0; + 110 6 } + 111 5 else + 112 5 { + 113 6 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALU + -E / s_recv.global_brightness; + 114 6 } + 115 5 + 116 5 if ( s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + 117 5 { + 118 6 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 119 6 } + 120 5 } + 121 4 + 122 4 + 123 4 //Ҫȴڵǰֵʱ + 124 4 if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + 125 4 { + 126 5 //s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; + 127 5 s_pwm.doublecurrpwm[i] -= s_pwm.every_change_10ms[i]; + 128 5 s_pwm.currpwm[i] = (u16)s_pwm.doublecurrpwm[i]; + 129 5 + 130 5 if(s_recv.global_brightness==0) + 131 5 { + 132 6 s_pwm.currvalue[i]=0; + 133 6 } + 134 5 else + 135 5 { + 136 6 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_ + -brightness; + 137 6 } + 138 5 + 139 5 if (s_pwm.currpwm[i] < s_pwm.wanttopwm[i] + s_pwm.every_change_10ms[i]) + 140 5 { + 141 6 s_pwm.currpwm[i] = 0; + 142 6 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 143 6 } + 144 5 } + 145 4 + 146 4 + 147 4 if (s_pwm.wanttopwm[i] == s_pwm.currpwm[i]) + 148 4 { + 149 5 s_pwm.currvalue[i] = s_recv.B_Ch[i]; + 150 5 s_recv.flag1[i] = 0; + 151 5 } + 152 4 } + 153 3 } + 154 2 } + 155 1 } + 156 + 157 void deal_command2(void) + 158 { + 159 1 int i=0; + 160 1 static u32 systick_command2 = 0; + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 4 + + 161 1 if (systick_1ms - systick_command2 >= 10) + 162 1 { + 163 2 systick_command2 = systick_1ms; + 164 2 for (i = 0; i < 12; i++) + 165 2 { + 166 3 if (s_recv.flag2[i]) + 167 3 { + 168 4 switch (s_recv.mode[i]) + 169 4 { + 170 5 //ֹͣģʽ + 171 5 case 0x00: + 172 5 //Ƚ + 173 5 if (s_recv.forward[i] == 0x00) + 174 5 { + 175 6 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_min * PWM_MAX_VALUE * s_recv.global_brightness + - / 100 / 100 * s_recv.key_status[i]; + 176 6 s_pwm.currpwm[i] += s_recv.pwm_step[i]; + 177 6 if(s_recv.global_brightness==0) + 178 6 { + 179 7 s_pwm.currvalue[i]=0; + 180 7 } + 181 6 else + 182 6 { + 183 7 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_re + -cv.global_brightness; + 184 7 } + 185 6 if (s_pwm.currpwm[i] >= s_pwm.wanttopwm[i]) + 186 6 { + 187 7 s_recv.flag2[i] = 0; + 188 7 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 189 7 s_pwm.currvalue[i] = s_recv.B_min; //ڻظ + 190 7 } + 191 6 } + 192 5 // + 193 5 if (s_recv.forward[i] == 0x01) + 194 5 { + 195 6 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_max * PWM_MAX_VALUE * s_recv.global_brightness + - / 100 / 100 * s_recv.key_status[i]; + 196 6 if (s_pwm.currpwm[i] <= s_pwm.wanttopwm[i] + s_recv.pwm_step[i]) + 197 6 { + 198 7 s_recv.flag2[i] = 0; + 199 7 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 200 7 s_pwm.currvalue[i] = s_recv.B_max; + 201 7 } + 202 6 else + 203 6 { + 204 7 s_pwm.currpwm[i] -= s_recv.pwm_step[i]; + 205 7 if(s_recv.global_brightness==0) + 206 7 { + 207 8 s_pwm.currvalue[i]=0; + 208 8 } + 209 7 else + 210 7 { + 211 8 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_b + -rightness; + 212 8 } + 213 7 } + 214 6 } + 215 5 break; + 216 5 + 217 5 //˫ѭģʽ + 218 5 case 0x01: + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 5 + + 219 5 //ݼ + 220 5 if (s_recv.forward[i] == 0x00) + 221 5 { + 222 6 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_min * PWM_MAX_VALUE * s_recv.global_brightness + - / 100 / 100 * s_recv.key_status[i]; + 223 6 s_pwm.currpwm[i] += s_recv.pwm_step[i]; + 224 6 if(s_recv.global_brightness==0) + 225 6 { + 226 7 s_pwm.currvalue[i]=0; + 227 7 } + 228 6 else + 229 6 { + 230 7 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_re + -cv.global_brightness; + 231 7 } + 232 6 if (s_pwm.currpwm[i] >= s_pwm.wanttopwm[i]) + 233 6 { + 234 7 s_recv.forward[i] = 0x01; + 235 7 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 236 7 s_pwm.currvalue[i] = s_recv.B_min; //ڻظ + 237 7 } + 238 6 } + 239 5 // + 240 5 if (s_recv.forward[i] == 0x01) + 241 5 { + 242 6 s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_max * PWM_MAX_VALUE * s_recv.global_brightness + - / 100 / 100 * s_recv.key_status[i]; + 243 6 if (s_pwm.currpwm[i] <= s_pwm.wanttopwm[i] + s_recv.pwm_step[i]) + 244 6 { + 245 7 s_recv.forward[i] = 0x00; + 246 7 s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + 247 7 s_pwm.currvalue[i] = s_recv.B_max; + 248 7 } + 249 6 else + 250 6 { + 251 7 s_pwm.currpwm[i] -= s_recv.pwm_step[i]; + 252 7 if(s_recv.global_brightness==0) + 253 7 { + 254 8 s_pwm.currvalue[i]=0; + 255 8 } + 256 7 else + 257 7 { + 258 8 s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_b + -rightness; + 259 8 } + 260 7 } + 261 6 } + 262 5 break; + 263 5 case 0x02: + 264 5 //ֹͣ + 265 5 s_recv.flag2[i] = 0; + 266 5 break; + 267 5 } + 268 4 } + 269 3 } + 270 2 } + 271 1 } + 272 + 273 + 274 //ֱӹص,¼״̬ + 275 void Close_Light(u8 i) + 276 { + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 6 + + 277 1 s_pwm.currpwm[i]=20001ul; //ߵƽdz⣬ + 278 1 } + 279 + 280 //򿪵ʱظԭ + 281 void Open_Light(u8 pin) + 282 { + 283 1 s_pwm.currpwm[pin] = PWM_MAX_VALUE - s_pwm.currvalue[pin] * PWM_MAX_VALUE * s_recv.global_brightness / 10 + -0 / 100; + 284 1 } + 285 + 286 void PWM_write(u8 i, u16 Val) + 287 { + 288 1 switch (i) + 289 1 { + 290 2 case 0: + 291 2 PWM15Duty(PWM07,Val); + 292 2 break; + 293 2 case 1: + 294 2 PWM15Duty(PWM06,Val); + 295 2 break; + 296 2 case 2: + 297 2 PWM15Duty(PWM05,Val); + 298 2 break; + 299 2 case 3: + 300 2 PWM15Duty(PWM04,Val); + 301 2 break; + 302 2 case 4: + 303 2 PWM15Duty(PWM03,Val); + 304 2 break; + 305 2 case 5: + 306 2 PWM15Duty(PWM02,Val); + 307 2 break; + 308 2 case 6: + 309 2 PWM15Duty(PWM01,Val); + 310 2 break; + 311 2 case 7: + 312 2 PWM15Duty(PWM00,Val); + 313 2 break; + 314 2 case 8: + 315 2 PWM15Duty(PWM23,Val); + 316 2 break; + 317 2 case 9: + 318 2 PWM15Duty(PWM22,Val); + 319 2 break; + 320 2 case 10: + 321 2 PWM15Duty(PWM21,Val); + 322 2 break; + 323 2 case 11: + 324 2 PWM15Duty(PWM20,Val); + 325 2 break; + 326 2 } + 327 1 } + 328 void show_light(void) + 329 { + 330 1 int i; + 331 1 for (i = 0; i < 12; i++) + 332 1 { + 333 2 if(s_pwm.currpwm[i]==20000ul) + 334 2 { + 335 3 Close_Light(i); + 336 3 } + 337 2 else + C51 COMPILER V9.01 PWM_CONTROL 12/15/2025 20:45:04 PAGE 7 + + 338 2 { + 339 3 PWM_write(i, s_pwm.currpwm[i]); + 340 3 } + 341 2 } + 342 1 } + 343 + 344 //void checkpwm(void) + 345 //{ + 346 // int i; + 347 // for (i = 0; i < 12; i++) + 348 // { + 349 // if ((s_recv.flag1[i] == 0) && (s_recv.flag2[i] == 0) && (s_recv.changeflag == 1)) + 350 // { + 351 // if (s_pwm.wanttopwmflash[i] != s_pwm.currpwm[i]) + 352 // { + 353 // s_pwm.currpwm[i] = s_pwm.wanttopwmflash[i]; + 354 // } + 355 // } + 356 // } + 357 // s_recv.changeflag = 0; + 358 //} + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 3842 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 241 ---- + PDATA SIZE = ---- ---- + DATA SIZE = 8 18 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/timer.lst b/Listings/timer.lst new file mode 100644 index 0000000..13690f3 --- /dev/null +++ b/Listings/timer.lst @@ -0,0 +1,190 @@ +C51 COMPILER V9.01 TIMER 12/15/2025 20:45:04 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE TIMER +OBJECT MODULE PLACED IN .\Objects\timer.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE timer.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listings\tim + -er.lst) OBJECT(.\Objects\timer.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 /************* ˵ ************** + 14 + 15 ļΪSTC8ϵеĶʱʼжϳ,ûļ޸ԼҪжϳ. + 16 + 17 ******************************************/ + 18 + 19 #include "timer.h" + 20 u32 systick_1ms=0; + 21 /********************* Timer0жϺ************************/ + 22 void timer0_int (void) interrupt TIMER0_VECTOR + 23 { + 24 1 P67 = ~P67; + 25 1 } + 26 + 27 /********************* Timer1жϺ************************/ + 28 void timer1_int (void) interrupt TIMER1_VECTOR + 29 { + 30 1 P66 = ~P66; + 31 1 } + 32 + 33 /********************* Timer2жϺ************************/ + 34 void timer2_int (void) interrupt TIMER2_VECTOR + 35 { + 36 1 systick_1ms++; + 37 1 } + 38 + 39 /********************* Timer3жϺ************************/ + 40 void timer3_int (void) interrupt TIMER3_VECTOR + 41 { + 42 1 + 43 1 } + 44 + 45 /********************* Timer4жϺ************************/ + 46 void timer4_int (void) interrupt TIMER4_VECTOR + 47 { + 48 1 P63 = ~P63; + 49 1 } + 50 + 51 + 52 //======================================================================== + 53 // : u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) + 54 // : ʱʼ. + C51 COMPILER V9.01 TIMER 12/15/2025 20:45:04 PAGE 2 + + 55 // : TIMx: ṹ,οtimer.hĶ. + 56 // : ɹ0, ղ1,󷵻2. + 57 // 汾: V1.0, 2012-10-22 + 58 //======================================================================== + 59 u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) + 60 { + 61 1 if(TIM > Timer4) return 1; //ղ + 62 1 + 63 1 if(TIM == Timer0) + 64 1 { + 65 2 Timer0_Stop(); //ֹͣ + 66 2 if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ж + 67 2 else Timer0_InterruptDisable(); //ֹж + 68 2 if(TIMx->TIM_Priority > Priority_3) return 2; // + 69 2 Timer0_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_ + -3 + 70 2 + 71 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; // + 72 2 TMOD = (TMOD & ~0x30) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ + 73 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T + 74 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T + 75 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //Ƶ + 76 2 else Timer0_AsTimer(); //ʱ + 77 2 if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //ʱ + 78 2 else Timer0_CLKO_Disable(); //ʱ + 79 2 + 80 2 T0_Load(TIMx->TIM_Value); + 81 2 if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //ʼ + 82 2 return 0; //ɹ + 83 2 } + 84 1 + 85 1 if(TIM == Timer1) + 86 1 { + 87 2 Timer1_Stop(); //ֹͣ + 88 2 if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ж + 89 2 else Timer1_InterruptDisable(); //ֹж + 90 2 if(TIMx->TIM_Priority > Priority_3) return 2; // + 91 2 Timer1_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_ + -3 + 92 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; // + 93 2 TMOD = (TMOD & ~0x30) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ + 94 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T + 95 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T + 96 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //Ƶ + 97 2 else Timer1_AsTimer(); //ʱ + 98 2 if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //ʱ + 99 2 else Timer1_CLKO_Disable(); //ʱ + 100 2 + 101 2 T1_Load(TIMx->TIM_Value); + 102 2 if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //ʼ + 103 2 return 0; //ɹ + 104 2 } + 105 1 + 106 1 if(TIM == Timer2) //Timer2,̶Ϊ16λԶװ, жȼ + 107 1 { + 108 2 Timer2_Stop(); //ֹͣ + 109 2 if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ж + 110 2 else Timer2_InterruptDisable(); //ֹж + 111 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 112 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T + 113 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T + 114 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //Ƶ + C51 COMPILER V9.01 TIMER 12/15/2025 20:45:04 PAGE 3 + + 115 2 else Timer2_AsTimer(); //ʱ + 116 2 if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //ʱ + 117 2 else Timer2_CLKO_Disable(); //ʱ + 118 2 + 119 2 T2_Load(TIMx->TIM_Value); + 120 2 if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //ʼ + 121 2 return 0; //ɹ + 122 2 } + 123 1 + 124 1 if(TIM == Timer3) //Timer3,̶Ϊ16λԶװ, жȼ + 125 1 { + 126 2 Timer3_Stop(); //ֹͣ + 127 2 if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ж + 128 2 else Timer3_InterruptDisable(); //ֹж + 129 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 130 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T + 131 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T + 132 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //Ƶ + 133 2 else Timer3_AsTimer(); //ʱ + 134 2 if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //ʱ + 135 2 else Timer3_CLKO_Disable(); //ʱ + 136 2 + 137 2 T3_Load(TIMx->TIM_Value); + 138 2 if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //ʼ + 139 2 return 0; //ɹ + 140 2 } + 141 1 + 142 1 if(TIM == Timer4) //Timer3,̶Ϊ16λԶװ, жȼ + 143 1 { + 144 2 Timer4_Stop(); //ֹͣ + 145 2 if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ж + 146 2 else Timer4_InterruptDisable(); //ֹж + 147 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 148 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T + 149 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T + 150 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //Ƶ + 151 2 else Timer4_AsTimer(); //ʱ + 152 2 if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //ʱ + 153 2 else Timer4_CLKO_Disable(); //ʱ + 154 2 + 155 2 T4_Load(TIMx->TIM_Value); + 156 2 if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //ʼ + 157 2 return 0; //ɹ + 158 2 } + 159 1 return 2; // + 160 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 795 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = 4 ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Objects/BLV_C12_Dimm_V19 b/Objects/BLV_C12_Dimm_V19 new file mode 100644 index 0000000..9152d17 Binary files /dev/null and b/Objects/BLV_C12_Dimm_V19 differ diff --git a/Objects/BLV_C12_Dimm_V19.build_log.htm b/Objects/BLV_C12_Dimm_V19.build_log.htm new file mode 100644 index 0000000..a34d82b --- /dev/null +++ b/Objects/BLV_C12_Dimm_V19.build_log.htm @@ -0,0 +1,54 @@ + + +
+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.29.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: cc cc, cc, LIC=9W1BF-6PVU2-D80FM-XPSKK-ZUPXX-GN4UD
+ 
+Tool Versions:
+Toolchain:       PK51 Prof. Developers Kit  Version: 9.01
+Toolchain Path:  D:\Keil_v5\C51\BIN
+C Compiler:      C51.exe V9.01
+Assembler:       A51.exe V8.02
+Linker/Locator:  BL51.exe V6.22
+Library Manager: LIB51.exe V4.24
+Hex Converter:   OH51.exe V2.6
+CPU DLL:         S8051.DLL V3.72
+Dialog DLL:      DP51.DLL V2.59
+Target DLL:      STCMON51.DLL V0, 1, 0, 17
+Dialog DLL:      TP51.DLL V2.58
+ 
+
Project:

+E:\Git_Project_Sourcode\RCU_C12_Dimming\light_V19.uvproj
+Project File Date:  12/15/2025
+
+
Output:

+Rebuild target 'Target 1'
+compiling GPIO.c...
+compiling main.c...
+compiling UART.C...
+compiling UART_Set.c...
+compiling pwm_control.c...
+compiling Start_Init.c...
+compiling PWM15bit.c...
+compiling timer.c...
+compiling key.c...
+compiling WDT.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_PRINTBUFFER1?UART
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_PRINTSTRING3?UART
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_QPWM15DUTY?PWM15BIT
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_PWMLEVELSET?PWM15BIT
+Program Size: data=77.0 xdata=641 code=15470
+creating hex file from ".\Objects\BLV_C12_Dimm_V19"...
+".\Objects\BLV_C12_Dimm_V19" - 0 Error(s), 4 Warning(s).
+Build Time Elapsed:  00:00:01
+
+ + diff --git a/Objects/BLV_C12_Dimm_V19.hex b/Objects/BLV_C12_Dimm_V19.hex new file mode 100644 index 0000000..7384007 --- /dev/null +++ b/Objects/BLV_C12_Dimm_V19.hex @@ -0,0 +1,1042 @@ +:1028A800EFD3940740037F0122121AEDFED394035D +:1028B80040037F0222EF7041EE700B900001121B63 +:1028C80006F452935294121AEDB4010B90000112BF +:1028D8001B064293F45294121AEDFEB4020A9000B9 +:1028E80001121B0642934294EEB4030D90000112AC +:1028F8001B06FEF45293EE4294EF64017043121AE1 +:10290800EDFE700B900001121B06F452915292EEEC +:10291800B4010B900001121B064291F45292121A54 +:10292800EDB4020A900001121B0642914292121A5B +:10293800EDB4030D900001121B06FEF45291EE4215 +:1029480092EF64027043121AEDFE700B90000112B0 +:102958001B06F452955296EEB4010B900001121B1F +:10296800064295F45296121AEDB4020A900001122A +:102978001B0642954296121AEDB4030D90000112FF +:102988001B06FEF45295EE4296EF64037043121A4A +:10299800EDFE700B900001121B06F452B152B2EE1C +:1029A800B4010B900001121B0642B1F452B2121A84 +:1029B800EDB4020A900001121B0642B142B2121A8B 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+:1035A500A360010ECF54C025E060A840B8E493A302 +:1035B500FAE493A3F8E493A3C8C582C8CAC583CA2D +:1035C500F0A3C8C582C8CAC583CADFE9DEE780BEE5 +:0100E000001F +:0D1DA200E6FB08E6F908E6FA08E6CBF822B1 +:0C1DAF00E0F8A3E0F9A3E0FAA3E0FB22B7 +:0D1DBB00E2FB08E2F908E2FA08E2CBF822A8 +:101DC800E493F8740193F9740293FA740393FB2271 +:00000001FF diff --git a/Objects/BLV_C12_Dimm_V19.lnp b/Objects/BLV_C12_Dimm_V19.lnp new file mode 100644 index 0000000..65e30a6 --- /dev/null +++ b/Objects/BLV_C12_Dimm_V19.lnp @@ -0,0 +1,12 @@ +".\Objects\GPIO.obj", +".\Objects\main.obj", +".\Objects\UART.obj", +".\Objects\UART_Set.obj", +".\Objects\pwm_control.obj", +".\Objects\Start_Init.obj", +".\Objects\PWM15bit.obj", +".\Objects\timer.obj", +".\Objects\key.obj", +".\Objects\WDT.obj" +TO ".\Objects\BLV_C12_Dimm_V19" +PRINT(".\Listings\BLV_C12_Dimm_V19.m51") RAMSIZE(256) diff --git a/PWM15bit.c b/PWM15bit.c new file mode 100644 index 0000000..769becb --- /dev/null +++ b/PWM15bit.c @@ -0,0 +1,534 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#include "PWM15bit.h" + +u16 code PWMxCR[48] = { + 0xff14, /* PWM00CR */ + 0xff1c, /* PWM01CR */ + 0xff24, /* PWM02CR */ + 0xff2c, /* PWM03CR */ + 0xff34, /* PWM04CR */ + 0xff3c, /* PWM05CR */ + 0xff44, /* PWM06CR */ + 0xff4c, /* PWM07CR */ + 0xff64, /* PWM10CR */ + 0xff6c, /* PWM11CR */ + 0xff74, /* PWM12CR */ + 0xff7c, /* PWM13CR */ + 0xff84, /* PWM14CR */ + 0xff8c, /* PWM15CR */ + 0xff94, /* PWM16CR */ + 0xff9c, /* PWM17CR */ + 0xffb4, /* PWM20CR */ + 0xffbc, /* PWM21CR */ + 0xffc4, /* PWM22CR */ + 0xffcc, /* PWM23CR */ + 0xffd4, /* PWM24CR */ + 0xffdc, /* PWM25CR */ + 0xffe4, /* PWM26CR */ + 0xffec, /* PWM27CR */ + 0xfc14, /* PWM30CR */ + 0xfc1c, /* PWM31CR */ + 0xfc24, /* PWM32CR */ + 0xfc2c, /* PWM33CR */ + 0xfc34, /* PWM34CR */ + 0xfc3c, /* PWM35CR */ + 0xfc44, /* PWM36CR */ + 0xfc4c, /* PWM37CR */ + 0xfc64, /* PWM40CR */ + 0xfc6c, /* PWM41CR */ + 0xfc74, /* PWM42CR */ + 0xfc7c, /* PWM43CR */ + 0xfc84, /* PWM44CR */ + 0xfc8c, /* PWM45CR */ + 0xfc94, /* PWM46CR */ + 0xfc9c, /* PWM47CR */ + 0xfcb4, /* PWM50CR */ + 0xfcbc, /* PWM51CR */ + 0xfcc4, /* PWM52CR */ + 0xfccc, /* PWM53CR */ + 0xfcd4, /* PWM54CR */ + 0xfcdc, /* PWM55CR */ + 0xfce4, /* PWM56CR */ + 0xfcec, /* PWM57CR */ +}; + +u16 code PWMxT1[48] = { + 0xff10, /* PWM00T1 */ + 0xff18, /* PWM01T1 */ + 0xff20, /* PWM02T1 */ + 0xff28, /* PWM03T1 */ + 0xff30, /* PWM04T1 */ + 0xff38, /* PWM05T1 */ + 0xff40, /* PWM06T1 */ + 0xff48, /* PWM07T1 */ + 0xff60, /* PWM10T1 */ + 0xff68, /* PWM11T1 */ + 0xff70, /* PWM12T1 */ + 0xff78, /* PWM13T1 */ + 0xff80, /* PWM14T1 */ + 0xff88, /* PWM15T1 */ + 0xff90, /* PWM16T1 */ + 0xff98, /* PWM17T1 */ + 0xffb0, /* PWM20T1 */ + 0xffb8, /* PWM21T1 */ + 0xffc0, /* PWM22T1 */ + 0xffc8, /* PWM23T1 */ + 0xffd0, /* PWM24T1 */ + 0xffd8, /* PWM25T1 */ + 0xffe0, /* PWM26T1 */ + 0xffe8, /* PWM27T1 */ + 0xfc10, /* PWM30T1 */ + 0xfc18, /* PWM31T1 */ + 0xfc20, /* PWM32T1 */ + 0xfc28, /* PWM33T1 */ + 0xfc30, /* PWM34T1 */ + 0xfc38, /* PWM35T1 */ + 0xfc40, /* PWM36T1 */ + 0xfc48, /* PWM37T1 */ + 0xfc60, /* PWM40T1 */ + 0xfc68, /* PWM41T1 */ + 0xfc70, /* PWM42T1 */ + 0xfc78, /* PWM43T1 */ + 0xfc80, /* PWM44T1 */ + 0xfc88, /* PWM45T1 */ + 0xfc90, /* PWM46T1 */ + 0xfc98, /* PWM47T1 */ + 0xfcb0, /* PWM50T1 */ + 0xfcb8, /* PWM51T1 */ + 0xfcc0, /* PWM52T1 */ + 0xfcc8, /* PWM53T1 */ + 0xfcd0, /* PWM54T1 */ + 0xfcd8, /* PWM55T1 */ + 0xfce0, /* PWM56T1 */ + 0xfce8, /* PWM57T1 */ +}; + +u16 code PWMxT2[48] = { + 0xff12, /* PWM00T2 */ + 0xff1a, /* PWM01T2 */ + 0xff22, /* PWM02T2 */ + 0xff2a, /* PWM03T2 */ + 0xff32, /* PWM04T2 */ + 0xff3a, /* PWM05T2 */ + 0xff42, /* PWM06T2 */ + 0xff4a, /* PWM07T2 */ + 0xff62, /* PWM10T2 */ + 0xff6a, /* PWM11T2 */ + 0xff72, /* PWM12T2 */ + 0xff7a, /* PWM13T2 */ + 0xff82, /* PWM14T2 */ + 0xff8a, /* PWM15T2 */ + 0xff92, /* PWM16T2 */ + 0xff9a, /* PWM17T2 */ + 0xffb2, /* PWM20T2 */ + 0xffba, /* PWM21T2 */ + 0xffc2, /* PWM22T2 */ + 0xffca, /* PWM23T2 */ + 0xffd2, /* PWM24T2 */ + 0xffda, /* PWM25T2 */ + 0xffe2, /* PWM26T2 */ + 0xffea, /* PWM27T2 */ + 0xfc12, /* PWM30T2 */ + 0xfc1a, /* PWM31T2 */ + 0xfc22, /* PWM32T2 */ + 0xfc2a, /* PWM33T2 */ + 0xfc32, /* PWM34T2 */ + 0xfc3a, /* PWM35T2 */ + 0xfc42, /* PWM36T2 */ + 0xfc4a, /* PWM37T2 */ + 0xfc62, /* PWM40T2 */ + 0xfc6a, /* PWM41T2 */ + 0xfc72, /* PWM42T2 */ + 0xfc7a, /* PWM43T2 */ + 0xfc82, /* PWM44T2 */ + 0xfc8a, /* PWM45T2 */ + 0xfc92, /* PWM46T2 */ + 0xfc9a, /* PWM47T2 */ + 0xfcb2, /* PWM50T2 */ + 0xfcba, /* PWM51T2 */ + 0xfcc2, /* PWM52T2 */ + 0xfcca, /* PWM53T2 */ + 0xfcd2, /* PWM54T2 */ + 0xfcda, /* PWM55T2 */ + 0xfce2, /* PWM56T2 */ + 0xfcea, /* PWM57T2 */ +}; + +u16 code PWMxHLD[48] = { + 0xff15, /* PWM00HLD */ + 0xff1d, /* PWM01HLD */ + 0xff25, /* PWM02HLD */ + 0xff2d, /* PWM03HLD */ + 0xff35, /* PWM04HLD */ + 0xff3d, /* PWM05HLD */ + 0xff45, /* PWM06HLD */ + 0xff4d, /* PWM07HLD */ + 0xff65, /* PWM10HLD */ + 0xff6d, /* PWM11HLD */ + 0xff75, /* PWM12HLD */ + 0xff7d, /* PWM13HLD */ + 0xff85, /* PWM14HLD */ + 0xff8d, /* PWM15HLD */ + 0xff95, /* PWM16HLD */ + 0xff9d, /* PWM17HLD */ + 0xffb5, /* PWM20HLD */ + 0xffbd, /* PWM21HLD */ + 0xffc5, /* PWM22HLD */ + 0xffcd, /* PWM23HLD */ + 0xffd5, /* PWM24HLD */ + 0xffdd, /* PWM25HLD */ + 0xffe5, /* PWM26HLD */ + 0xffed, /* PWM27HLD */ + 0xfc15, /* PWM30HLD */ + 0xfc1d, /* PWM31HLD */ + 0xfc25, /* PWM32HLD */ + 0xfc2d, /* PWM33HLD */ + 0xfc35, /* PWM34HLD */ + 0xfc3d, /* PWM35HLD */ + 0xfc45, /* PWM36HLD */ + 0xfc4d, /* PWM37HLD */ + 0xfc65, /* PWM40HLD */ + 0xfc6d, /* PWM41HLD */ + 0xfc75, /* PWM42HLD */ + 0xfc7d, /* PWM43HLD */ + 0xfc85, /* PWM44HLD */ + 0xfc8d, /* PWM45HLD */ + 0xfc95, /* PWM46HLD */ + 0xfc9d, /* PWM47HLD */ + 0xfcb5, /* PWM50HLD */ + 0xfcbd, /* PWM51HLD */ + 0xfcc5, /* PWM52HLD */ + 0xfccd, /* PWM53HLD */ + 0xfcd5, /* PWM54HLD */ + 0xfcdd, /* PWM55HLD */ + 0xfce5, /* PWM56HLD */ + 0xfced, /* PWM57HLD */ +}; + +//======================================================================== +// : u8 PWMChannelCtrl(u8 PWM_id, u8 pwm_eno, u8 pwm_ini, u8 pwm_eni, u8 pwm_ent2i, u8 pwm_ent1i) +// : PWMͨƼĴ. +// : PWM_id: PWMͨ. ȡֵ 0~57 +// pwm_eno: pwmʹ, 0ΪGPIO, 1ΪPWM. +// pwm_ini: pwm˵ijʼƽ, 0Ϊ͵ƽ, 1Ϊߵƽ. +// pwm_eni: pwmͨжʹܿ, 0ΪرPWMж, 1ΪʹPWMж. +// pwm_ent2i: pwmͨڶжʹܿ, 0ΪرPWMڶж, 1ΪʹPWMڶж. +// pwm_ent1i: pwmͨһжʹܿ, 0ΪرPWMһж, 1ΪʹPWMһж. +// : 0:ȷ, 2:. +// 汾: V1.0, 2020-09-22 +//======================================================================== +u8 PWMChannelCtrl(u8 PWM_id, u8 pwm_eno, u8 pwm_ini, u8 pwm_eni, u8 pwm_ent2i, u8 pwm_ent1i) +{ + u8 xdata *pPWMxCR; + + if(PWM_id > PWM57) return 2; //id + if(pwm_eno > 1) return 2; //ʹܴ + if(pwm_ini > 1) return 2; //˵ijʼƽ + if(pwm_eni > 1) return 2; //жʹܿƴ + if(pwm_ent2i > 1) return 2; //ڶжʹܿƴ + if(pwm_ent1i > 1) return 2; //һжʹܿƴ + + EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + pPWMxCR = (u8 *)PWMxCR[PWM_id]; + *pPWMxCR = (pwm_eno << 7) | (pwm_ini << 6) | (pwm_eni << 2)| (pwm_ent2i << 1)| pwm_ent1i; + EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + return 0; +} + +//======================================================================== +// : u8 PWMPeriodDuty(u8 PWM_id, u16 Period, u16 dutyL, u16 dutyH) +// : PWM, ռձ. +// : PWM_id: PWMͨ. ȡֵ 0~57 +// dutyL: pwm͵ƽλ, ȡֵ 0~0x7fff. +// dutyH: pwmߵƽλ, ȡֵ 0~0x7fff. +// : 0:ȷ, 2:. +// 汾: V1.0, 2020-09-22 +//======================================================================== +u8 PWM15Duty(u8 PWM_id,u16 dutyL) +{ + u16 xdata *pPWMxT1; + u16 xdata *pPWMxT2; + + if(PWM_id > PWM57) return 2; //id + if(dutyL > 0x7fff) return 2; //͵ƽʱô + //if(dutyH > 0x7fff) return 2; //ߵƽʱô + + EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + pPWMxT1 = (u16 *)PWMxT1[PWM_id]; + *pPWMxT1 = dutyL & 0x7fff; + + pPWMxT2 = (u16 *)PWMxT2[PWM_id]; + *pPWMxT2 = 0x0000 & 0x7fff; + EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + return 0; +} + +u8 qPWM15Duty(u8 PWM_id,u16 dutyL, u16 dutyH) +{ + u16 xdata *pPWMxT1; + u16 xdata *pPWMxT2; + + if(PWM_id > PWM57) return 2; //id + if(dutyL > 0x7fff) return 2; //͵ƽʱô + if(dutyH > 0x7fff) return 2; //ߵƽʱô + + EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + pPWMxT1 = (u16 *)PWMxT1[PWM_id]; + *pPWMxT1 = dutyL & 0x7fff; + + pPWMxT2 = (u16 *)PWMxT2[PWM_id]; + *pPWMxT2 = dutyH & 0x7fff; + EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + return 0; +} +//======================================================================== +// : u8 PWMOutputSet(u8 PWM_id, u8 pwm_hldl, u8 pwm_hldh) +// : PWMͨƼĴ. +// : PWM_id: PWMͨ. ȡֵ 0~57 +// pwm_hldl: pwmǿ͵ƽλ, 0, 1ǿ͵ƽ. +// pwm_hldh: pwmǿߵƽλ, 0, 1ǿߵƽ. +// : 0:ȷ, 2:. +// 汾: V1.0, 2020-09-22 +//======================================================================== +u8 PWMLevelSet(u8 PWM_id, u8 pwm_hldl, u8 pwm_hldh) +{ + u8 xdata *pPWMxHLD; + + if(PWM_id > PWM57) return 2; //id + if(pwm_hldh > 1) return 2; //ʹܴ + if(pwm_hldl > 1) return 2; //˵ijʼƽ + + EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + pPWMxHLD = (u8 *)PWMxHLD[PWM_id]; + *pPWMxHLD = (pwm_hldh << 1) | pwm_hldl; + EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + return 0; +} + +//======================================================================== +// : void PWM15_Init(u8 PWM_id, PWM15_InitTypeDef *PWMx) +// : 15λǿPWMʼ. +// : PWM_id: PWM. ȡֵ PWM0,PWM1,PWM2,PWM3,PWM4,PWM5 +// PWMx: ṹ,οͷļĶ. +// : none. +// 汾: V1.0, 2020-09-22 +//======================================================================== +void PWM15_Init(u8 PWM_id, PWM15_InitTypeDef *PWMx) +{ + if(PWM_id > PWM5) return; //id + + EAXSFR(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ + if(PWM_id == PWM0) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM0_Enable(); //ʹPWM0 + else PWM15_PWM0_Disable(); //رPWM0 + PWM0_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM0C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter0_Enable(); //ʹܼ + else PWM15_Counter0_Disable(); //رռ + } + + if(PWM_id == PWM1) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM1_Enable(); //ʹPWM1 + else PWM15_PWM1_Disable(); //رPWM1 + PWM1_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM1C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter1_Enable(); //ʹܼ + else PWM15_Counter1_Disable(); //رռ + } + + if(PWM_id == PWM2) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM2_Enable(); //ʹPWM2 + else PWM15_PWM2_Disable(); //رPWM2 + PWM2_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM2C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter2_Enable(); //ʹܼ + else PWM15_Counter2_Disable(); //رռ + } + + if(PWM_id == PWM3) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM3_Enable(); //ʹPWM3 + else PWM15_PWM3_Disable(); //رPWM3 + PWM3_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM3C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter3_Enable(); //ʹܼ + else PWM15_Counter3_Disable(); //رռ + } + + if(PWM_id == PWM4) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM4_Enable(); //ʹPWM4 + else PWM15_PWM4_Disable(); //رPWM4 + PWM4_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM4C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter4_Enable(); //ʹܼ + else PWM15_Counter4_Disable(); //رռ + } + + if(PWM_id == PWM5) + { + if(PWMx->PWM_Enable == ENABLE) PWM15_PWM5_Enable(); //ʹPWM5 + else PWM15_PWM5_Disable(); //رPWM5 + PWM5_PS_Set(PWMx->PWM_Clock_PS); //ϵͳʱӷƵ, 0~15 + PWM5C = PWMx->PWM_Period & 0x7fff; + if(PWMx->PWM_Counter == ENABLE) PWM15_Counter5_Enable(); //ʹܼ + else PWM15_Counter5_Disable(); //رռ + } + EAXRAM(); /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ +} + + +//======================================================================== +// : void PWM0_Handler (void) interrupt PWM0_VECTOR +// : PWM0жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +void PWM0_Handler (void) interrupt PWM0_VECTOR +{ + char store; + store = P_SW2; + P_SW2 |= 0x80; + + if(PWMCFG01 & 0x08) //PWM0ж + { + PWMCFG01 &= ~0x08; //PWM0жϱ־ + // TODO: ڴ˴û + } + if(PWM0IF) + { + PWM0IF = 0; + P27 = ~P27; + } + P_SW2 = store; +} +//======================================================================== +// : void PWM1_Handler (void) interrupt PWM1_VECTOR +// : PWM1жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +void PWM1_Handler (void) interrupt PWM1_VECTOR +{ + char store; + store = P_SW2; + P_SW2 |= 0x80; + + if(PWMCFG01 & 0x80) //PWM1ж + { + PWMCFG01 &= ~0x80; //PWM1жϱ־ + // TODO: ڴ˴û + } + if(PWM1IF) + { + PWM1IF = 0; + P26 = ~P26; + } + P_SW2 = store; +} +//======================================================================== +// : void PWM2_Handler (void) interrupt PWM2_VECTOR +// : PWM2жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +void PWM2_Handler (void) interrupt PWM2_VECTOR +{ + char store; + store = P_SW2; + P_SW2 |= 0x80; + + if(PWMCFG23 & 0x08) //PWM2ж + { + PWMCFG23 &= ~0x08; //PWM2жϱ־ + // TODO: ڴ˴û + } + if(PWM2IF) + { + PWM2IF = 0; + P25 = ~P25; + } + P_SW2 = store; +} +//======================================================================== +// : void PWM3_Handler (void) interrupt PWM3_VECTOR +// : PWM3жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +void PWM3_Handler (void) interrupt PWM3_VECTOR +{ + char store; + store = P_SW2; + P_SW2 |= 0x80; + + if(PWMCFG23 & 0x80) //PWM3ж + { + PWMCFG23 &= ~0x80; //PWM3жϱ־ + // TODO: ڴ˴û + } + if(PWM3IF) + { + PWM3IF = 0; + P24 = ~P24; + } + P_SW2 = store; +} +//======================================================================== +// : void PWM4_Handler (void) interrupt PWM4_VECTOR +// : PWM4жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +void PWM4_Handler (void) interrupt PWM4_VECTOR +{ + char store; + store = P_SW2; + P_SW2 |= 0x80; + + if(PWMCFG45 & 0x08) //PWM4ж + { + PWMCFG45 &= ~0x08; //PWM4жϱ־ + // TODO: ڴ˴û + } + if(PWM4IF) + { + PWM4IF = 0; + P23 = ~P23; + } + P_SW2 = store; +} +//======================================================================== +// : void PWM5_Handler (void) interrupt PWM5_VECTOR +// : PWM5жϴ. +// : None +// : none. +// 汾: V1.0, 2020-10-13 +//======================================================================== +//void PWM5_Handler (void) interrupt PWM5_VECTOR //жų31ɽжϺת +//{ +// if(PWMCFG45 & 0x80) //PWM5ж +// { +// PWMCFG45 &= ~0x80; //PWM5жϱ־ +// // TODO: ڴ˴û +// } +//} diff --git a/PWM15bit.h b/PWM15bit.h new file mode 100644 index 0000000..2ecdc26 --- /dev/null +++ b/PWM15bit.h @@ -0,0 +1,94 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#ifndef __PWM15BIT_H +#define __PWM15BIT_H + +#include "config.h" + +#define PWM0 0 +#define PWM1 1 +#define PWM2 2 +#define PWM3 3 +#define PWM4 4 +#define PWM5 5 + +#define PWM00 0 +#define PWM01 1 +#define PWM02 2 +#define PWM03 3 +#define PWM04 4 +#define PWM05 5 +#define PWM06 6 +#define PWM07 7 +#define PWM10 8 +#define PWM11 9 +#define PWM12 10 +#define PWM13 11 +#define PWM14 12 +#define PWM15 13 +#define PWM16 14 +#define PWM17 15 +#define PWM20 16 +#define PWM21 17 +#define PWM22 18 +#define PWM23 19 +#define PWM24 20 +#define PWM25 21 +#define PWM26 22 +#define PWM27 23 +#define PWM30 24 +#define PWM31 25 +#define PWM32 26 +#define PWM33 27 +#define PWM34 28 +#define PWM35 29 +#define PWM36 30 +#define PWM37 31 +#define PWM40 32 +#define PWM41 33 +#define PWM42 34 +#define PWM43 35 +#define PWM44 36 +#define PWM45 37 +#define PWM46 38 +#define PWM47 39 +#define PWM50 40 +#define PWM51 41 +#define PWM52 42 +#define PWM53 43 +#define PWM54 44 +#define PWM55 45 +#define PWM56 46 +#define PWM57 47 + +#define PWMn_CLK_SYS 0 +#define PWMn_CLK_TM2 1 + +typedef struct +{ + u8 PWM_Enable; //PWMʹ, ENABLE, DISABLE + + u8 PWM_Interrupt; //жʹ, ENABLE, DISABLE + u8 PWM_Counter; //ʹ, ENABLE, DISABLE + u8 PWM_Clock_Sel; //ʱԴѡ, PWMn_CLK_SYS, PWMn_CLK_TM2 + u8 PWM_Clock_PS; //ϵͳʱӷƵ, 0~15 + u16 PWM_Period; //PWM, 0~0x7fff +} PWM15_InitTypeDef; + +void PWM15_Init(u8 PWM_id, PWM15_InitTypeDef *PWMx); +u8 PWMChannelCtrl(u8 PWM_id, u8 pwm_eno, u8 pwm_ini, u8 pwm_eni, u8 pwm_ent2i, u8 pwm_ent1i); +u8 PWM15Duty(u8 PWM_id,u16 dutyL); +u8 PWMLevelSet(u8 PWM_id, u8 pwm_hldl, u8 pwm_hldh); +u8 qPWM15Duty(u8 PWM_id,u16 dutyL, u16 dutyH); +#endif + diff --git a/Readme.md b/Readme.md new file mode 100644 index 0000000..f66219e --- /dev/null +++ b/Readme.md @@ -0,0 +1,57 @@ +### 项目名称：RCU_C12_Dimming + +### 协议文档：..\RCU-Cx\Document\BLV-BUS-485协议文档 + +### 共享路径：..\RCU-Cx\Reference\BLV_C12_CH12_Source_Code + + + +# 版本说明 + + + +#### 2025-12-15 修改人：曹聪 类型：解决BUG + +​ 问题描述：调光时间一样的情况下，调光亮与调光灭的实际调光时间不一致 + +```c +/* 问题点：在于pwm_control.c文件中的deal_command1函数处理上 + + s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; + s_pwm.doublecurrpwm[i] += s_pwm.every_change_10ms[i]; + s_pwm.currpwm[i] = (u16)s_pwm.doublecurrpwm[i]; + + 其中： + currpwm 是当前PWM对应的寄存器值(整数) + doublecurrpwm 是用于计算PWM步进后的值(浮点数) + 此逻辑导致用于计算PWM步进后的浮点数，直接丢失小数部分，然后用于下一次运算；导致PWM增加的步进值与降低的步进值不同，从而导致实际调光时间不一致 +*/ +``` + + + + + +#### V18之前版本说明如下： + +- V18 2024-09-27 + + 修改内容：解决全局亮度设置时变量溢出导致亮度不能调节问题。 + +- V17 杨鸿锋 + + 修改内容：全局亮度设置增加渐变 + +- V16 2024-05-06 曹聪 + + 修改内容：修改调光频率导致循环调光时间过短问题 - 调整后与之前循环调光渐变时间差不多(最慢的时候 10S左右) + +- V15 + + 修改了pwm调光的频率，调成16khz，解决了低频主机啸叫的问题 + +- V14 + + 修改串口接收，最终发布版本 + +- 以下版本说明全是开发临时记录 \ No newline at end of file diff --git a/STC8xxxx.H b/STC8xxxx.H new file mode 100644 index 0000000..db07392 --- /dev/null +++ b/STC8xxxx.H @@ -0,0 +1,2748 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#ifndef _STC8xxxx_H +#define _STC8xxxx_H + +#include + +/* BYTE Registers */ +sfr P0 = 0x80; +sfr SP = 0x81; +sfr DPL = 0x82; +sfr DPH = 0x83; +sfr S4CON = 0x84; +sfr S4BUF = 0x85; +sfr PCON = 0x87; + +sfr TCON = 0x88; +sfr TMOD = 0x89; +sfr TL0 = 0x8A; +sfr TL1 = 0x8B; +sfr TH0 = 0x8C; +sfr TH1 = 0x8D; +sfr AUXR = 0x8E; +sfr WAKE_CLKO = 0x8F; +sfr INT_CLKO = 0x8F; + +sfr P1 = 0x90; +sfr P1M1 = 0x91; //P1M1.n,P1M0.n =00--->Standard, 01--->push-pull ʵ1TĶһ +sfr P1M0 = 0x92; // =10--->pure input, 11--->open drain +sfr P0M1 = 0x93; //P0M1.n,P0M0.n =00--->Standard, 01--->push-pull +sfr P0M0 = 0x94; // =10--->pure input, 11--->open drain +sfr P2M1 = 0x95; //P2M1.n,P2M0.n =00--->Standard, 01--->push-pull +sfr P2M0 = 0x96; // =10--->pure input, 11--->open drain +//sfr PCON2 = 0x97; +//sfr AUXR2 = 0x97; + +sfr SCON = 0x98; +sfr SBUF = 0x99; +sfr S2CON = 0x9A; // +sfr S2BUF = 0x9B; // + +sfr P2 = 0xA0; +sfr BUS_SPEED = 0xA1; +sfr P_SW1 = 0xA2; + +sfr IE = 0xA8; +sfr SADDR = 0xA9; +sfr WKTCL = 0xAA; //Ѷʱֽ +sfr WKTCH = 0xAB; //Ѷʱֽ +sfr S3CON = 0xAC; +sfr S3BUF = 0xAD; +sfr TA = 0xAE; +sfr IE2 = 0xAF; + +sfr P3 = 0xB0; +sfr P3M1 = 0xB1; //P3M1.n,P3M0.n =00--->Standard, 01--->push-pull +sfr P3M0 = 0xB2; // =10--->pure input, 11--->open drain +sfr P4M1 = 0xB3; //P4M1.n,P4M0.n =00--->Standard, 01--->push-pull +sfr P4M0 = 0xB4; // =10--->pure input, 11--->open drain +sfr IP2 = 0xB5; +sfr IP2H = 0xB6; +sfr IPH = 0xB7; + +sfr IP = 0xB8; +sfr SADEN = 0xB9; +sfr P_SW2 = 0xBA; +sfr VOCTRL = 0xBB; +sfr ADC_CONTR = 0xBC; //ADCƼĴ +sfr ADC_RES = 0xBD; //ADCֽ +sfr ADC_RESL = 0xBE; //ADCֽ + +sfr P4 = 0xC0; +sfr WDT_CONTR = 0xC1; + +sfr IAP_DATA = 0xC2; +sfr IAP_ADDRH = 0xC3; +sfr IAP_ADDRL = 0xC4; +sfr IAP_CMD = 0xC5; +sfr IAP_TRIG = 0xC6; +sfr IAP_CONTR = 0xC7; + +sfr ISP_DATA = 0xC2; +sfr ISP_ADDRH = 0xC3; +sfr ISP_ADDRL = 0xC4; +sfr ISP_CMD = 0xC5; +sfr ISP_TRIG = 0xC6; +sfr ISP_CONTR = 0xC7; + +sfr P5 = 0xC8; // +sfr P5M1 = 0xC9; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull +sfr P5M0 = 0xCA; // =10--->pure input, 11--->open drain +sfr P6M1 = 0xCB; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull +sfr P6M0 = 0xCC; // =10--->pure input, 11--->open drain +sfr SPSTAT = 0xCD; // +sfr SPCTL = 0xCE; // +sfr SPDAT = 0xCF; // + +sfr PSW = 0xD0; +sfr T4T3M = 0xD1; +sfr T4H = 0xD2; +sfr T4L = 0xD3; +sfr T3H = 0xD4; +sfr T3L = 0xD5; +sfr T2H = 0xD6; +sfr T2L = 0xD7; + +sfr TH4 = 0xD2; +sfr TL4 = 0xD3; +sfr TH3 = 0xD4; +sfr TL3 = 0xD5; +sfr TH2 = 0xD6; +sfr TL2 = 0xD7; + +sfr CCON = 0xD8; // +sfr CMOD = 0xD9; // +sfr CCAPM0 = 0xDA; //PCAģ0ĹģʽĴ +sfr CCAPM1 = 0xDB; //PCAģ1ĹģʽĴ +sfr CCAPM2 = 0xDC; //PCAģ2ĹģʽĴ +//sfr CCAPM3 = 0xDD; //PCAģ3ĹģʽĴ +sfr USBCLK = 0xDC; +sfr ADCCFG = 0xDE; // +sfr IP3 = 0xDF; //жȼĴ + +sfr ACC = 0xE0; +sfr P7M1 = 0xE1; +sfr P7M0 = 0xE2; +sfr DPS = 0xE3; +sfr DPL1 = 0xE4; +sfr DPH1 = 0xE5; +sfr CMPCR1 = 0xE6; +sfr CMPCR2 = 0xE7; + +sfr P6 = 0xE8; +sfr CL = 0xE9; // +sfr CCAP0L = 0xEA; //PCAģ0IJ׽/ȽϼĴ8λ +sfr CCAP1L = 0xEB; //PCAģ1IJ׽/ȽϼĴ8λ +sfr CCAP2L = 0xEC; //PCAģ2IJ׽/ȽϼĴ8λ +//sfr CCAP3L = 0xED; //PCAģ3IJ׽/ȽϼĴ8λ +sfr USBDAT = 0xEC; +sfr IP3H = 0xEE; +sfr AUXINTIF = 0xEF; //жϱ־ B6-INT4IF, B5-INT3IF, B4-INT2IF, B2-T4IF, B1-T3IF, B0-T2IF + +sfr B = 0xF0; +sfr PWMSET = 0xF1; //ǿPWMȫüĴ +sfr PCA_PWM0 = 0xF2; //PCAģ0 PWMĴ +sfr PCA_PWM1 = 0xF3; //PCAģ1 PWMĴ +sfr PCA_PWM2 = 0xF4; //PCAģ2 PWMĴ +//sfr PCA_PWM3 = 0xF5; //PCAģ3 PWMĴ +sfr PWMCFG01 = 0xF6; //ǿPWMüĴ +sfr PWMCFG23 = 0xF7; //ǿPWMüĴ +sfr USBCON = 0xF4; +sfr IAP_TPS = 0xF5; + +sfr P7 = 0xF8; +sfr CH = 0xF9; +sfr CCAP0H = 0xFA; //PCAģ0IJ׽/ȽϼĴ8λ +sfr CCAP1H = 0xFB; //PCAģ1IJ׽/ȽϼĴ8λ +sfr CCAP2H = 0xFC; //PCAģ2IJ׽/ȽϼĴ8λ +//sfr CCAP3H = 0xFD; //PCAģ3IJ׽/ȽϼĴ8λ +sfr PWMCFG45 = 0xFE; //ǿPWMüĴ +sfr USBADR = 0xFC; +sfr RSTCFG = 0xFF; // + + +// 7 6 5 4 3 2 1 0 Reset Value +//INT_CLKO: жʱƼĴ - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000 +#define INT4_Enable() INT_CLKO |= (1 << 6) +#define INT3_Enable() INT_CLKO |= (1 << 5) +#define INT2_Enable() INT_CLKO |= (1 << 4) +#define INT1_Enable() EX1 = 1 +#define INT0_Enable() EX0 = 1 + +#define INT4_Disable() INT_CLKO &= ~(1 << 6) +#define INT3_Disable() INT_CLKO &= ~(1 << 5) +#define INT2_Disable() INT_CLKO &= ~(1 << 4) +#define INT1_Disable() EX1 = 0 +#define INT0_Disable() EX0 = 0 + +// 7 6 5 4 3 2 1 0 Reset Value +//AUXINTIF: жϱ־Ĵ - INT4IF INT3IF INT2IF - T4IF T3IF T2IF 0000,0000 +#define INT4IF 0x40 +#define INT3IF 0x20 +#define INT2IF 0x10 +#define T4IF 0x04 +#define T3IF 0x02 +#define T2IF 0x01 + +#define INT4_Clear() AUXINTIF &= ~INT4IF /* ж4־λ */ +#define INT3_Clear() AUXINTIF &= ~INT3IF /* ж3־λ */ +#define INT2_Clear() AUXINTIF &= ~INT2IF /* ж2־λ */ +#define INT1_Clear() IE1 = 0 /* ж1־λ */ +#define INT0_Clear() IE0 = 0 /* ж0־λ */ + +#define INT0_Fall() IT0 = 1 /* INT0 ½ж */ +#define INT0_RiseFall() IT0 = 0 /* INT0 ½ؾж */ +#define INT1_Fall() IT1 = 1 /* INT1 ½ж */ +#define INT1_RiseFall() IT0 = 0 /* INT1 ½ؾж */ + + +//=============================================================== +#define EAXSFR() P_SW2 |= 0x80 /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */ +#define EAXRAM() P_SW2 &= ~0x80 /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */ + +#define I2C_USE_P14P15() P_SW2 &= ~0x30 /* I2CлP1.4(SDA) P1.5(SCL)(ϵĬ).*/ +#define I2C_USE_P24P25() P_SW2 = (P_SW2 & ~0x30) | 0x10 /* I2CлP2.4(SDA) P2.5(SCL).*/ +#define I2C_USE_P76P77() P_SW2 = (P_SW2 & ~0x30) | 0x20 /* I2CлP7.6(SDA) P7.7(SCL).*/ +#define I2C_USE_P33P32() P_SW2 |= 0x30 /* I2CлP3.3(SDA) P3.2(SCL).*/ + +#define CLKSEL (*(unsigned char volatile xdata *)0xfe00) +#define CKSEL (*(unsigned char volatile xdata *)0xfe00) /* ʱԴѡ */ +#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) /* ʱӷƵ */ +#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) /* IRC 24MHZ */ +#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) /* XOSC */ +#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) /* IRC 32KHZ */ +#define MCLKOCR (*(unsigned char volatile xdata *)0xfe05) +#define IRCDB (*(unsigned char volatile xdata *)0xfe06) +#define X32KCR (*(unsigned char volatile xdata *)0xfe08) + +#define MainFosc_IRC24M() CKSEL = (CKSEL & ~0x03) /* ѡڲ24MHZʱ */ +#define MainFosc_XTAL() CKSEL = (CKSEL & ~0x03) | 0x01 /* ѡⲿʱ */ +#define MainFosc_IRC32K() CKSEL = CKSEL | 0x03 /* ѡڲ32Kʱ */ +#define EXT_CLOCK() XOSCCR = 0x80 /* ѡⲿʱ */ +#define EXT_CRYSTAL() XOSCCR = 0xC0 /* ѡⲿ */ + + +#define P0PU (*(unsigned char volatile xdata *)0xfe10) /* P0 4.1K Pull Up Enable */ +#define P1PU (*(unsigned char volatile xdata *)0xfe11) /* P1 4.1K Pull Up Enable */ +#define P2PU (*(unsigned char volatile xdata *)0xfe12) /* P2 4.1K Pull Up Enable */ +#define P3PU (*(unsigned char volatile xdata *)0xfe13) /* P3 4.1K Pull Up Enable */ +#define P4PU (*(unsigned char volatile xdata *)0xfe14) /* P4 4.1K Pull Up Enable */ +#define P5PU (*(unsigned char volatile xdata *)0xfe15) /* P5 4.1K Pull Up Enable */ +#define P6PU (*(unsigned char volatile xdata *)0xfe16) /* P6 4.1K Pull Up Enable */ +#define P7PU (*(unsigned char volatile xdata *)0xfe17) /* P7 4.1K Pull Up Enable */ + +#define P0NCS (*(unsigned char volatile xdata *)0xfe18) /* P0 Non Schmit Trigger 0: ʹܶ˿ʩش(Ĭ), 1: ֹ */ +#define P1NCS (*(unsigned char volatile xdata *)0xfe19) /* P1 Non Schmit Trigger */ +#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) /* P2 Non Schmit Trigger */ +#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) /* P3 Non Schmit Trigger */ +#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) /* P4 Non Schmit Trigger */ +#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) /* P5 Non Schmit Trigger */ +#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) /* P6 Non Schmit Trigger */ +#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) /* P7 Non Schmit Trigger */ + +#define P0SR (*(unsigned char volatile xdata *)0xfe20) /* ˿ڵƽתٶ 0: , 1: (Ĭ) */ +#define P1SR (*(unsigned char volatile xdata *)0xfe21) +#define P2SR (*(unsigned char volatile xdata *)0xfe22) +#define P3SR (*(unsigned char volatile xdata *)0xfe23) +#define P4SR (*(unsigned char volatile xdata *)0xfe24) +#define P5SR (*(unsigned char volatile xdata *)0xfe25) +#define P6SR (*(unsigned char volatile xdata *)0xfe26) +#define P7SR (*(unsigned char volatile xdata *)0xfe27) + +#define P0DR (*(unsigned char volatile xdata *)0xfe28) /* ˿ 0: ǿ, 1: һ(Ĭ) */ +#define P1DR (*(unsigned char volatile xdata *)0xfe29) +#define P2DR (*(unsigned char volatile xdata *)0xfe2a) +#define P3DR (*(unsigned char volatile xdata *)0xfe2b) +#define P4DR (*(unsigned char volatile xdata *)0xfe2c) +#define P5DR (*(unsigned char volatile xdata *)0xfe2d) +#define P6DR (*(unsigned char volatile xdata *)0xfe2e) +#define P7DR (*(unsigned char volatile xdata *)0xfe2f) + +#define P0IE (*(unsigned char volatile xdata *)0xfe30)/* ˿źʹ 0: ֹź, 1: ʹź(Ĭ) */ +#define P1IE (*(unsigned char volatile xdata *)0xfe31) +#define P2IE (*(unsigned char volatile xdata *)0xfe32) +#define P3IE (*(unsigned char volatile xdata *)0xfe33) +#define P4IE (*(unsigned char volatile xdata *)0xfe34) +#define P5IE (*(unsigned char volatile xdata *)0xfe35) +#define P6IE (*(unsigned char volatile xdata *)0xfe36) +#define P7IE (*(unsigned char volatile xdata *)0xfe37) + +#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) /* */ +#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) /* */ +#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) /* */ +#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) /* */ +#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) /* */ +#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) /* */ +#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) /* */ +#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) /* */ +#define I2CMSAUX (*(unsigned char volatile xdata *)0xfe88) + +#define TM2PS (*(unsigned char volatile xdata *)0xfea2) +#define TM3PS (*(unsigned char volatile xdata *)0xfea3) +#define TM4PS (*(unsigned char volatile xdata *)0xfea4) +#define ADCTIM (*(unsigned char volatile xdata *)0xfea8) +#define T3T4PIN (*(unsigned char volatile xdata *)0xfeac) + +#define PWMA_ETRPS (*(unsigned char volatile xdata *)0xfeb0) +#define PWMA_ENO (*(unsigned char volatile xdata *)0xfeb1) +#define PWMA_PS (*(unsigned char volatile xdata *)0xfeb2) +#define PWMA_IOAUX (*(unsigned char volatile xdata *)0xfeb3) +#define PWMB_ETRPS (*(unsigned char volatile xdata *)0xfeb4) +#define PWMB_ENO (*(unsigned char volatile xdata *)0xfeb5) +#define PWMB_PS (*(unsigned char volatile xdata *)0xfeb6) +#define PWMB_IOAUX (*(unsigned char volatile xdata *)0xfeb7) +#define PWMA_CR1 (*(unsigned char volatile xdata *)0xfec0) +#define PWMA_CR2 (*(unsigned char volatile xdata *)0xfec1) +#define PWMA_SMCR (*(unsigned char volatile xdata *)0xfec2) +#define PWMA_ETR (*(unsigned char volatile xdata *)0xfec3) +#define PWMA_IER (*(unsigned char volatile xdata *)0xfec4) +#define PWMA_SR1 (*(unsigned char volatile xdata *)0xfec5) +#define PWMA_SR2 (*(unsigned char volatile xdata *)0xfec6) +#define PWMA_EGR (*(unsigned char volatile xdata *)0xfec7) +#define PWMA_CCMR1 (*(unsigned char volatile xdata *)0xfec8) +#define PWMA_CCMR2 (*(unsigned char volatile xdata *)0xfec9) +#define PWMA_CCMR3 (*(unsigned char volatile xdata *)0xfeca) +#define PWMA_CCMR4 (*(unsigned char volatile xdata *)0xfecb) +#define PWMA_CCER1 (*(unsigned char volatile xdata *)0xfecc) +#define PWMA_CCER2 (*(unsigned char volatile xdata *)0xfecd) +#define PWMA_CNTR (*(unsigned int volatile xdata *)0xfece) +#define PWMA_CNTRH (*(unsigned char volatile xdata *)0xfece) +#define PWMA_CNTRL (*(unsigned char volatile xdata *)0xfecf) +#define PWMA_PSCR (*(unsigned int volatile xdata *)0xfed0) +#define PWMA_PSCRH (*(unsigned char volatile xdata *)0xfed0) +#define PWMA_PSCRL (*(unsigned char volatile xdata *)0xfed1) +#define PWMA_ARR (*(unsigned int volatile xdata *)0xfed2) +#define PWMA_ARRH (*(unsigned char volatile xdata *)0xfed2) +#define PWMA_ARRL (*(unsigned char volatile xdata *)0xfed3) +#define PWMA_RCR (*(unsigned char volatile xdata *)0xfed4) +#define PWMA_CCR1 (*(unsigned int volatile xdata *)0xfed5) +#define PWMA_CCR1H (*(unsigned char volatile xdata *)0xfed5) +#define PWMA_CCR1L (*(unsigned char volatile xdata *)0xfed6) +#define PWMA_CCR2 (*(unsigned int volatile xdata *)0xfed7) +#define PWMA_CCR2H (*(unsigned char volatile xdata *)0xfed7) +#define PWMA_CCR2L (*(unsigned char volatile xdata *)0xfed8) +#define PWMA_CCR3 (*(unsigned int volatile xdata *)0xfed9) +#define PWMA_CCR3H (*(unsigned char volatile xdata *)0xfed9) +#define PWMA_CCR3L (*(unsigned char volatile xdata *)0xfeda) +#define PWMA_CCR4 (*(unsigned int volatile xdata *)0xfedb) +#define PWMA_CCR4H (*(unsigned char volatile xdata *)0xfedb) +#define PWMA_CCR4L (*(unsigned char volatile xdata *)0xfedc) +#define PWMA_BRK (*(unsigned char volatile xdata *)0xfedd) +#define PWMA_DTR (*(unsigned char volatile xdata *)0xfede) +#define PWMA_OISR (*(unsigned char volatile xdata *)0xfedf) + +#define PWMB_CR1 (*(unsigned char volatile xdata *)0xfee0) +#define PWMB_CR2 (*(unsigned char volatile xdata *)0xfee1) +#define PWMB_SMCR (*(unsigned char volatile xdata *)0xfee2) +#define PWMB_ETR (*(unsigned char volatile xdata *)0xfee3) +#define PWMB_IER (*(unsigned char volatile xdata *)0xfee4) +#define PWMB_SR1 (*(unsigned char volatile xdata *)0xfee5) +#define PWMB_SR2 (*(unsigned char volatile xdata *)0xfee6) +#define PWMB_EGR (*(unsigned char volatile xdata *)0xfee7) +#define PWMB_CCMR1 (*(unsigned char volatile xdata *)0xfee8) +#define PWMB_CCMR2 (*(unsigned char volatile xdata *)0xfee9) +#define PWMB_CCMR3 (*(unsigned char volatile xdata *)0xfeea) +#define PWMB_CCMR4 (*(unsigned char volatile xdata *)0xfeeb) +#define PWMB_CCER1 (*(unsigned char volatile xdata *)0xfeec) +#define PWMB_CCER2 (*(unsigned char volatile xdata *)0xfeed) +#define PWMB_CNTR (*(unsigned int volatile xdata *)0xfeee) +#define PWMB_CNTRH (*(unsigned char volatile xdata *)0xfeee) +#define PWMB_CNTRL (*(unsigned char volatile xdata *)0xfeef) +#define PWMB_PSCR (*(unsigned int volatile xdata *)0xfef0) +#define PWMB_PSCRH (*(unsigned char volatile xdata *)0xfef0) +#define PWMB_PSCRL (*(unsigned char volatile xdata *)0xfef1) +#define PWMB_ARR (*(unsigned int volatile xdata *)0xfef2) +#define PWMB_ARRH (*(unsigned char volatile xdata *)0xfef2) +#define PWMB_ARRL (*(unsigned char volatile xdata *)0xfef3) +#define PWMB_RCR (*(unsigned char volatile xdata *)0xfef4) +#define PWMB_CCR5 (*(unsigned int volatile xdata *)0xfef5) +#define PWMB_CCR5H (*(unsigned char volatile xdata *)0xfef5) +#define PWMB_CCR5L (*(unsigned char volatile xdata *)0xfef6) +#define PWMB_CCR6 (*(unsigned int volatile xdata *)0xfef7) +#define PWMB_CCR6H (*(unsigned char volatile xdata *)0xfef7) +#define PWMB_CCR6L (*(unsigned char volatile xdata *)0xfef8) +#define PWMB_CCR7 (*(unsigned int volatile xdata *)0xfef9) +#define PWMB_CCR7H (*(unsigned char volatile xdata *)0xfef9) +#define PWMB_CCR7L (*(unsigned char volatile xdata *)0xfefa) +#define PWMB_CCR8 (*(unsigned int volatile xdata *)0xfefb) +#define PWMB_CCR8H (*(unsigned char volatile xdata *)0xfefb) +#define PWMB_CCR8L (*(unsigned char volatile xdata *)0xfefc) +#define PWMB_BRK (*(unsigned char volatile xdata *)0xfefd) +#define PWMB_DTR (*(unsigned char volatile xdata *)0xfefe) +#define PWMB_OISR (*(unsigned char volatile xdata *)0xfeff) + +///////////////////////////////////////////////// +//FD00H-FDFFH +///////////////////////////////////////////////// + +#define PWM0C (*(unsigned int volatile xdata *)0xff00) +#define PWM0CH (*(unsigned char volatile xdata *)0xff00) +#define PWM0CL (*(unsigned char volatile xdata *)0xff01) +#define PWM0CKS (*(unsigned char volatile xdata *)0xff02) +#define PWM0TADC (*(unsigned int volatile xdata *)0xff03) +#define PWM0TADCH (*(unsigned char volatile xdata *)0xff03) +#define PWM0TADCL (*(unsigned char volatile xdata *)0xff04) +#define PWM0IF (*(unsigned char volatile xdata *)0xff05) +#define PWM0FDCR (*(unsigned char volatile xdata *)0xff06) +#define PWM00T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM00T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM00T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM00T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM00T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM00T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM00CR (*(unsigned char volatile xdata *)0xff14) +#define PWM00HLD (*(unsigned char volatile xdata *)0xff15) +#define PWM01T1 (*(unsigned int volatile xdata *)0xff18) +#define PWM01T1H (*(unsigned char volatile xdata *)0xff18) +#define PWM01T1L (*(unsigned char volatile xdata *)0xff19) +#define PWM01T2 (*(unsigned int volatile xdata *)0xff1a) +#define PWM01T2H (*(unsigned char volatile xdata *)0xff1a) +#define PWM01T2L (*(unsigned char volatile xdata *)0xff1b) +#define PWM01CR (*(unsigned char volatile xdata *)0xff1c) +#define PWM01HLD (*(unsigned char volatile xdata *)0xff1d) +#define PWM02T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM02T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM02T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM02T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM02T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM02T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM02CR (*(unsigned char volatile xdata *)0xff24) +#define PWM02HLD (*(unsigned char volatile xdata *)0xff25) +#define PWM03T1 (*(unsigned int volatile xdata *)0xff28) +#define PWM03T1H (*(unsigned char volatile xdata *)0xff28) +#define PWM03T1L (*(unsigned char volatile xdata *)0xff29) +#define PWM03T2 (*(unsigned int volatile xdata *)0xff2a) +#define PWM03T2H (*(unsigned char volatile xdata *)0xff2a) +#define PWM03T2L (*(unsigned char volatile xdata *)0xff2b) +#define PWM03CR (*(unsigned char volatile xdata *)0xff2c) +#define PWM03HLD (*(unsigned char volatile xdata *)0xff2d) +#define PWM04T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM04T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM04T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM04T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM04T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM04T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM04CR (*(unsigned char volatile xdata *)0xff34) +#define PWM04HLD (*(unsigned char volatile xdata *)0xff35) +#define PWM05T1 (*(unsigned int volatile xdata *)0xff38) +#define PWM05T1H (*(unsigned char volatile xdata *)0xff38) +#define PWM05T1L (*(unsigned char volatile xdata *)0xff39) +#define PWM05T2 (*(unsigned int volatile xdata *)0xff3a) +#define PWM05T2H (*(unsigned char volatile xdata *)0xff3a) +#define PWM05T2L (*(unsigned char volatile xdata *)0xff3b) +#define PWM05CR (*(unsigned char volatile xdata *)0xff3c) +#define PWM05HLD (*(unsigned char volatile xdata *)0xff3d) +#define PWM06T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM06T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM06T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM06T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM06T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM06T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM06CR (*(unsigned char volatile xdata *)0xff44) +#define PWM06HLD (*(unsigned char volatile xdata *)0xff45) +#define PWM07T1 (*(unsigned int volatile xdata *)0xff48) +#define PWM07T1H (*(unsigned char volatile xdata *)0xff48) +#define PWM07T1L (*(unsigned char volatile xdata *)0xff49) +#define PWM07T2 (*(unsigned int volatile xdata *)0xff4a) +#define PWM07T2H (*(unsigned char volatile xdata *)0xff4a) +#define PWM07T2L (*(unsigned char volatile xdata *)0xff4b) +#define PWM07CR (*(unsigned char volatile xdata *)0xff4c) +#define PWM07HLD (*(unsigned char volatile xdata *)0xff4d) +#define PWM1C (*(unsigned int volatile xdata *)0xff50) +#define PWM1CH (*(unsigned char volatile xdata *)0xff50) +#define PWM1CL (*(unsigned char volatile xdata *)0xff51) +#define PWM1CKS (*(unsigned char volatile xdata *)0xff52) +#define PWM1IF (*(unsigned char volatile xdata *)0xff55) +#define PWM1FDCR (*(unsigned char volatile xdata *)0xff56) +#define PWM10T1 (*(unsigned int volatile xdata *)0xff60) +#define PWM10T1H (*(unsigned char volatile xdata *)0xff60) +#define PWM10T1L (*(unsigned char volatile xdata *)0xff61) +#define PWM10T2 (*(unsigned int volatile xdata *)0xff62) +#define PWM10T2H (*(unsigned char volatile xdata *)0xff62) +#define PWM10T2L (*(unsigned char volatile xdata *)0xff63) +#define PWM10CR (*(unsigned char volatile xdata *)0xff64) +#define PWM10HLD (*(unsigned char volatile xdata *)0xff65) +#define PWM11T1 (*(unsigned int volatile xdata *)0xff68) +#define PWM11T1H (*(unsigned char volatile xdata *)0xff68) +#define PWM11T1L (*(unsigned char volatile xdata *)0xff69) +#define PWM11T2 (*(unsigned int volatile xdata *)0xff6a) +#define PWM11T2H (*(unsigned char volatile xdata *)0xff6a) +#define PWM11T2L (*(unsigned char volatile xdata *)0xff6b) +#define PWM11CR (*(unsigned char volatile xdata *)0xff6c) +#define PWM11HLD (*(unsigned char volatile xdata *)0xff6d) +#define PWM12T1 (*(unsigned int volatile xdata *)0xff70) +#define PWM12T1H (*(unsigned char volatile xdata *)0xff70) +#define PWM12T1L (*(unsigned char volatile xdata *)0xff71) +#define PWM12T2 (*(unsigned int volatile xdata *)0xff72) +#define PWM12T2H (*(unsigned char volatile xdata *)0xff72) +#define PWM12T2L (*(unsigned char volatile xdata *)0xff73) +#define PWM12CR (*(unsigned char volatile xdata *)0xff74) +#define PWM12HLD (*(unsigned char volatile xdata *)0xff75) +#define PWM13T1 (*(unsigned int volatile xdata *)0xff78) +#define PWM13T1H (*(unsigned char volatile xdata *)0xff78) +#define PWM13T1L (*(unsigned char volatile xdata *)0xff79) +#define PWM13T2 (*(unsigned int volatile xdata *)0xff7a) +#define PWM13T2H (*(unsigned char volatile xdata *)0xff7a) +#define PWM13T2L (*(unsigned char volatile xdata *)0xff7b) +#define PWM13CR (*(unsigned char volatile xdata *)0xff7c) +#define PWM13HLD (*(unsigned char volatile xdata *)0xff7d) +#define PWM14T1 (*(unsigned int volatile xdata *)0xff80) +#define PWM14T1H (*(unsigned char volatile xdata *)0xff80) +#define PWM14T1L (*(unsigned char volatile xdata *)0xff81) +#define PWM14T2 (*(unsigned int volatile xdata *)0xff82) +#define PWM14T2H (*(unsigned char volatile xdata *)0xff82) +#define PWM14T2L (*(unsigned char volatile xdata *)0xff83) +#define PWM14CR (*(unsigned char volatile xdata *)0xff84) +#define PWM14HLD (*(unsigned char volatile xdata *)0xff85) +#define PWM15T1 (*(unsigned int volatile xdata *)0xff88) +#define PWM15T1H (*(unsigned char volatile xdata *)0xff88) +#define PWM15T1L (*(unsigned char volatile xdata *)0xff89) +#define PWM15T2 (*(unsigned int volatile xdata *)0xff8a) +#define PWM15T2H (*(unsigned char volatile xdata *)0xff8a) +#define PWM15T2L (*(unsigned char volatile xdata *)0xff8b) +#define PWM15CR (*(unsigned char volatile xdata *)0xff8c) +#define PWM15HLD (*(unsigned char volatile xdata *)0xff8d) +#define PWM16T1 (*(unsigned int volatile xdata *)0xff90) +#define PWM16T1H (*(unsigned char volatile xdata *)0xff90) +#define PWM16T1L (*(unsigned char volatile xdata *)0xff91) +#define PWM16T2 (*(unsigned int volatile xdata *)0xff92) +#define PWM16T2H (*(unsigned char volatile xdata *)0xff92) +#define PWM16T2L (*(unsigned char volatile xdata *)0xff93) +#define PWM16CR (*(unsigned char volatile xdata *)0xff94) +#define PWM16HLD (*(unsigned char volatile xdata *)0xff95) +#define PWM17T1 (*(unsigned int volatile xdata *)0xff98) +#define PWM17T1H (*(unsigned char volatile xdata *)0xff98) +#define PWM17T1L (*(unsigned char volatile xdata *)0xff99) +#define PWM17T2 (*(unsigned int volatile xdata *)0xff9a) +#define PWM17T2H (*(unsigned char volatile xdata *)0xff9a) +#define PWM17T2L (*(unsigned char volatile xdata *)0xff9b) +#define PWM17CR (*(unsigned char volatile xdata *)0xff9c) +#define PWM17HLD (*(unsigned char volatile xdata *)0xff9d) +#define PWM2C (*(unsigned int volatile xdata *)0xffa0) +#define PWM2CH (*(unsigned char volatile xdata *)0xffa0) +#define PWM2CL (*(unsigned char volatile xdata *)0xffa1) +#define PWM2CKS (*(unsigned char volatile xdata *)0xffa2) +#define PWM2TADC (*(unsigned int volatile xdata *)0xffa3) +#define PWM2TADCH (*(unsigned char volatile xdata *)0xffa3) +#define PWM2TADCL (*(unsigned char volatile xdata *)0xffa4) +#define PWM2IF (*(unsigned char volatile xdata *)0xffa5) +#define PWM2FDCR (*(unsigned char volatile xdata *)0xffa6) +#define PWM20T1 (*(unsigned int volatile xdata *)0xffb0) +#define PWM20T1H (*(unsigned char volatile xdata *)0xffb0) +#define PWM20T1L (*(unsigned char volatile xdata *)0xffb1) +#define PWM20T2 (*(unsigned int volatile xdata *)0xffb2) +#define PWM20T2H (*(unsigned char volatile xdata *)0xffb2) +#define PWM20T2L (*(unsigned char volatile xdata *)0xffb3) +#define PWM20CR (*(unsigned char volatile xdata *)0xffb4) +#define PWM20HLD (*(unsigned char volatile xdata *)0xffb5) +#define PWM21T1 (*(unsigned int volatile xdata *)0xffb8) +#define PWM21T1H (*(unsigned char volatile xdata *)0xffb8) +#define PWM21T1L (*(unsigned char volatile xdata *)0xffb9) +#define PWM21T2 (*(unsigned int volatile xdata *)0xffba) +#define PWM21T2H (*(unsigned char volatile xdata *)0xffba) +#define PWM21T2L (*(unsigned char volatile xdata *)0xffbb) +#define PWM21CR (*(unsigned char volatile xdata *)0xffbc) +#define PWM21HLD (*(unsigned char volatile xdata *)0xffbd) +#define PWM22T1 (*(unsigned int volatile xdata *)0xffc0) +#define PWM22T1H (*(unsigned char volatile xdata *)0xffc0) +#define PWM22T1L (*(unsigned char volatile xdata *)0xffc1) +#define PWM22T2 (*(unsigned int volatile xdata *)0xffc2) +#define PWM22T2H (*(unsigned char volatile xdata *)0xffc2) +#define PWM22T2L (*(unsigned char volatile xdata *)0xffc3) +#define PWM22CR (*(unsigned char volatile xdata *)0xffc4) +#define PWM22HLD (*(unsigned char volatile xdata *)0xffc5) +#define PWM23T1 (*(unsigned int volatile xdata *)0xffc8) +#define PWM23T1H (*(unsigned char volatile xdata *)0xffc8) +#define PWM23T1L (*(unsigned char volatile xdata *)0xffc9) +#define PWM23T2 (*(unsigned int volatile xdata *)0xffca) +#define PWM23T2H (*(unsigned char volatile xdata *)0xffca) +#define PWM23T2L (*(unsigned char volatile xdata *)0xffcb) +#define PWM23CR (*(unsigned char volatile xdata *)0xffcc) +#define PWM23HLD (*(unsigned char volatile xdata *)0xffcd) +#define PWM24T1 (*(unsigned int volatile xdata *)0xffd0) +#define PWM24T1H (*(unsigned char volatile xdata *)0xffd0) +#define PWM24T1L (*(unsigned char volatile xdata *)0xffd1) +#define PWM24T2 (*(unsigned int volatile xdata *)0xffd2) +#define PWM24T2H (*(unsigned char volatile xdata *)0xffd2) +#define PWM24T2L (*(unsigned char volatile xdata *)0xffd3) +#define PWM24CR (*(unsigned char volatile xdata *)0xffd4) +#define PWM24HLD (*(unsigned char volatile xdata *)0xffd5) +#define PWM25T1 (*(unsigned int volatile xdata *)0xffd8) +#define PWM25T1H (*(unsigned char volatile xdata *)0xffd8) +#define PWM25T1L (*(unsigned char volatile xdata *)0xffd9) +#define PWM25T2 (*(unsigned int volatile xdata *)0xffda) +#define PWM25T2H (*(unsigned char volatile xdata *)0xffda) +#define PWM25T2L (*(unsigned char volatile xdata *)0xffdb) +#define PWM25CR (*(unsigned char volatile xdata *)0xffdc) +#define PWM25HLD (*(unsigned char volatile xdata *)0xffdd) +#define PWM26T1 (*(unsigned int volatile xdata *)0xffe0) +#define PWM26T1H (*(unsigned char volatile xdata *)0xffe0) +#define PWM26T1L (*(unsigned char volatile xdata *)0xffe1) +#define PWM26T2 (*(unsigned int volatile xdata *)0xffe2) +#define PWM26T2H (*(unsigned char volatile xdata *)0xffe2) +#define PWM26T2L (*(unsigned char volatile xdata *)0xffe3) +#define PWM26CR (*(unsigned char volatile xdata *)0xffe4) +#define PWM26HLD (*(unsigned char volatile xdata *)0xffe5) +#define PWM27T1 (*(unsigned int volatile xdata *)0xffe8) +#define PWM27T1H (*(unsigned char volatile xdata *)0xffe8) +#define PWM27T1L (*(unsigned char volatile xdata *)0xffe9) +#define PWM27T2 (*(unsigned int volatile xdata *)0xffea) +#define PWM27T2H (*(unsigned char volatile xdata *)0xffea) +#define PWM27T2L (*(unsigned char volatile xdata *)0xffeb) +#define PWM27CR (*(unsigned char volatile xdata *)0xffec) +#define PWM27HLD (*(unsigned char volatile xdata *)0xffed) + +///////////////////////////////////////////////// +//FC00H-FCFFH +///////////////////////////////////////////////// + +#define PWM3C (*(unsigned int volatile xdata *)0xfc00) +#define PWM3CH (*(unsigned char volatile xdata *)0xfc00) +#define PWM3CL (*(unsigned char volatile xdata *)0xfc01) +#define PWM3CKS (*(unsigned char volatile xdata *)0xfc02) +#define PWM3IF (*(unsigned char volatile xdata *)0xfc05) +#define PWM3FDCR (*(unsigned char volatile xdata *)0xfc06) +#define PWM30T1 (*(unsigned int volatile xdata *)0xfc10) +#define PWM30T1H (*(unsigned char volatile xdata *)0xfc10) +#define PWM30T1L (*(unsigned char volatile xdata *)0xfc11) +#define PWM30T2 (*(unsigned int volatile xdata *)0xfc12) +#define PWM30T2H (*(unsigned char volatile xdata *)0xfc12) +#define PWM30T2L (*(unsigned char volatile xdata *)0xfc13) +#define PWM30CR (*(unsigned char volatile xdata *)0xfc14) +#define PWM30HLD (*(unsigned char volatile xdata *)0xfc15) +#define PWM31T1 (*(unsigned int volatile xdata *)0xfc18) +#define PWM31T1H (*(unsigned char volatile xdata *)0xfc18) +#define PWM31T1L (*(unsigned char volatile xdata *)0xfc19) +#define PWM31T2 (*(unsigned int volatile xdata *)0xfc1a) +#define PWM31T2H (*(unsigned char volatile xdata *)0xfc1a) +#define PWM31T2L (*(unsigned char volatile xdata *)0xfc1b) +#define PWM31CR (*(unsigned char volatile xdata *)0xfc1c) +#define PWM31HLD (*(unsigned char volatile xdata *)0xfc1d) +#define PWM32T1 (*(unsigned int volatile xdata *)0xfc20) +#define PWM32T1H (*(unsigned char volatile xdata *)0xfc20) +#define PWM32T1L (*(unsigned char volatile xdata *)0xfc21) +#define PWM32T2 (*(unsigned int volatile xdata *)0xfc22) +#define PWM32T2H (*(unsigned char volatile xdata *)0xfc22) +#define PWM32T2L (*(unsigned char volatile xdata *)0xfc23) +#define PWM32CR (*(unsigned char volatile xdata *)0xfc24) +#define PWM32HLD (*(unsigned char volatile xdata *)0xfc25) +#define PWM33T1 (*(unsigned int volatile xdata *)0xfc28) +#define PWM33T1H (*(unsigned char volatile xdata *)0xfc28) +#define PWM33T1L (*(unsigned char volatile xdata *)0xfc29) +#define PWM33T2 (*(unsigned int volatile xdata *)0xfc2a) +#define PWM33T2H (*(unsigned char volatile xdata *)0xfc2a) +#define PWM33T2L (*(unsigned char volatile xdata *)0xfc2b) +#define PWM33CR (*(unsigned char volatile xdata *)0xfc2c) +#define PWM33HLD (*(unsigned char volatile xdata *)0xfc2d) +#define PWM34T1 (*(unsigned int volatile xdata *)0xfc30) +#define PWM34T1H (*(unsigned char volatile xdata *)0xfc30) +#define PWM34T1L (*(unsigned char volatile xdata *)0xfc31) +#define PWM34T2 (*(unsigned int volatile xdata *)0xfc32) +#define PWM34T2H (*(unsigned char volatile xdata *)0xfc32) +#define PWM34T2L (*(unsigned char volatile xdata *)0xfc33) +#define PWM34CR (*(unsigned char volatile xdata *)0xfc34) +#define PWM34HLD (*(unsigned char volatile xdata *)0xfc35) +#define PWM35T1 (*(unsigned int volatile xdata *)0xfc38) +#define PWM35T1H (*(unsigned char volatile xdata *)0xfc38) +#define PWM35T1L (*(unsigned char volatile xdata *)0xfc39) +#define PWM35T2 (*(unsigned int volatile xdata *)0xfc3a) +#define PWM35T2H (*(unsigned char volatile xdata *)0xfc3a) +#define PWM35T2L (*(unsigned char volatile xdata *)0xfc3b) +#define PWM35CR (*(unsigned char volatile xdata *)0xfc3c) +#define PWM35HLD (*(unsigned char volatile xdata *)0xfc3d) +#define PWM36T1 (*(unsigned int volatile xdata *)0xfc40) +#define PWM36T1H (*(unsigned char volatile xdata *)0xfc40) +#define PWM36T1L (*(unsigned char volatile xdata *)0xfc41) +#define PWM36T2 (*(unsigned int volatile xdata *)0xfc42) +#define PWM36T2H (*(unsigned char volatile xdata *)0xfc42) +#define PWM36T2L (*(unsigned char volatile xdata *)0xfc43) +#define PWM36CR (*(unsigned char volatile xdata *)0xfc44) +#define PWM36HLD (*(unsigned char volatile xdata *)0xfc45) +#define PWM37T1 (*(unsigned int volatile xdata *)0xfc48) +#define PWM37T1H (*(unsigned char volatile xdata *)0xfc48) +#define PWM37T1L (*(unsigned char volatile xdata *)0xfc49) +#define PWM37T2 (*(unsigned int volatile xdata *)0xfc4a) +#define PWM37T2H (*(unsigned char volatile xdata *)0xfc4a) +#define PWM37T2L (*(unsigned char volatile xdata *)0xfc4b) +#define PWM37CR (*(unsigned char volatile xdata *)0xfc4c) +#define PWM37HLD (*(unsigned char volatile xdata *)0xfc4d) +#define PWM4C (*(unsigned int volatile xdata *)0xfc50) +#define PWM4CH (*(unsigned char volatile xdata *)0xfc50) +#define PWM4CL (*(unsigned char volatile xdata *)0xfc51) +#define PWM4CKS (*(unsigned char volatile xdata *)0xfc52) +#define PWM4TADC (*(unsigned int volatile xdata *)0xfc53) +#define PWM4TADCH (*(unsigned char volatile xdata *)0xfc53) +#define PWM4TADCL (*(unsigned char volatile xdata *)0xfc54) +#define PWM4IF (*(unsigned char volatile xdata *)0xfc55) +#define PWM4FDCR (*(unsigned char volatile xdata *)0xfc56) +#define PWM40T1 (*(unsigned int volatile xdata *)0xfc60) +#define PWM40T1H (*(unsigned char volatile xdata *)0xfc60) +#define PWM40T1L (*(unsigned char volatile xdata *)0xfc61) +#define PWM40T2 (*(unsigned int volatile xdata *)0xfc62) +#define PWM40T2H (*(unsigned char volatile xdata *)0xfc62) +#define PWM40T2L (*(unsigned char volatile xdata *)0xfc63) +#define PWM40CR (*(unsigned char volatile xdata *)0xfc64) +#define PWM40HLD (*(unsigned char volatile xdata *)0xfc65) +#define PWM41T1 (*(unsigned int volatile xdata *)0xfc68) +#define PWM41T1H (*(unsigned char volatile xdata *)0xfc68) +#define PWM41T1L (*(unsigned char volatile xdata *)0xfc69) +#define PWM41T2 (*(unsigned int volatile xdata *)0xfc6a) +#define PWM41T2H (*(unsigned char volatile xdata *)0xfc6a) +#define PWM41T2L (*(unsigned char volatile xdata *)0xfc6b) +#define PWM41CR (*(unsigned char volatile xdata *)0xfc6c) +#define PWM41HLD (*(unsigned char volatile xdata *)0xfc6d) +#define PWM42T1 (*(unsigned int volatile xdata *)0xfc70) +#define PWM42T1H (*(unsigned char volatile xdata *)0xfc70) +#define PWM42T1L (*(unsigned char volatile xdata *)0xfc71) +#define PWM42T2 (*(unsigned int volatile xdata *)0xfc72) +#define PWM42T2H (*(unsigned char volatile xdata *)0xfc72) +#define PWM42T2L (*(unsigned char volatile xdata *)0xfc73) +#define PWM42CR (*(unsigned char volatile xdata *)0xfc74) +#define PWM42HLD (*(unsigned char volatile xdata *)0xfc75) +#define PWM43T1 (*(unsigned int volatile xdata *)0xfc78) +#define PWM43T1H (*(unsigned char volatile xdata *)0xfc78) +#define PWM43T1L (*(unsigned char volatile xdata *)0xfc79) +#define PWM43T2 (*(unsigned int volatile xdata *)0xfc7a) +#define PWM43T2H (*(unsigned char volatile xdata *)0xfc7a) +#define PWM43T2L (*(unsigned char volatile xdata *)0xfc7b) +#define PWM43CR (*(unsigned char volatile xdata *)0xfc7c) +#define PWM43HLD (*(unsigned char volatile xdata *)0xfc7d) +#define PWM44T1 (*(unsigned int volatile xdata *)0xfc80) +#define PWM44T1H (*(unsigned char volatile xdata *)0xfc80) +#define PWM44T1L (*(unsigned char volatile xdata *)0xfc81) +#define PWM44T2 (*(unsigned int volatile xdata *)0xfc82) +#define PWM44T2H (*(unsigned char volatile xdata *)0xfc82) +#define PWM44T2L (*(unsigned char volatile xdata *)0xfc83) +#define PWM44CR (*(unsigned char volatile xdata *)0xfc84) +#define PWM44HLD (*(unsigned char volatile xdata *)0xfc85) +#define PWM45T1 (*(unsigned int volatile xdata *)0xfc88) +#define PWM45T1H (*(unsigned char volatile xdata *)0xfc88) +#define PWM45T1L (*(unsigned char volatile xdata *)0xfc89) +#define PWM45T2 (*(unsigned int volatile xdata *)0xfc8a) +#define PWM45T2H (*(unsigned char volatile xdata *)0xfc8a) +#define PWM45T2L (*(unsigned char volatile xdata *)0xfc8b) +#define PWM45CR (*(unsigned char volatile xdata *)0xfc8c) +#define PWM45HLD (*(unsigned char volatile xdata *)0xfc8d) +#define PWM46T1 (*(unsigned int volatile xdata *)0xfc90) +#define PWM46T1H (*(unsigned char volatile xdata *)0xfc90) +#define PWM46T1L (*(unsigned char volatile xdata *)0xfc91) +#define PWM46T2 (*(unsigned int volatile xdata *)0xfc92) +#define PWM46T2H (*(unsigned char volatile xdata *)0xfc92) +#define PWM46T2L (*(unsigned char volatile xdata *)0xfc93) +#define PWM46CR (*(unsigned char volatile xdata *)0xfc94) +#define PWM46HLD (*(unsigned char volatile xdata *)0xfc95) +#define PWM47T1 (*(unsigned int volatile xdata *)0xfc98) +#define PWM47T1H (*(unsigned char volatile xdata *)0xfc98) +#define PWM47T1L (*(unsigned char volatile xdata *)0xfc99) +#define PWM47T2 (*(unsigned int volatile xdata *)0xfc9a) +#define PWM47T2H (*(unsigned char volatile xdata *)0xfc9a) +#define PWM47T2L (*(unsigned char volatile xdata *)0xfc9b) +#define PWM47CR (*(unsigned char volatile xdata *)0xfc9c) +#define PWM47HLD (*(unsigned char volatile xdata *)0xfc9d) +#define PWM5C (*(unsigned int volatile xdata *)0xfca0) +#define PWM5CH (*(unsigned char volatile xdata *)0xfca0) +#define PWM5CL (*(unsigned char volatile xdata *)0xfca1) +#define PWM5CKS (*(unsigned char volatile xdata *)0xfca2) +#define PWM5IF (*(unsigned char volatile xdata *)0xfca5) +#define PWM5FDCR (*(unsigned char volatile xdata *)0xfca6) +#define PWM50T1 (*(unsigned int volatile xdata *)0xfcb0) +#define PWM50T1H (*(unsigned char volatile xdata *)0xfcb0) +#define PWM50T1L (*(unsigned char volatile xdata *)0xfcb1) +#define PWM50T2 (*(unsigned int volatile xdata *)0xfcb2) +#define PWM50T2H (*(unsigned char volatile xdata *)0xfcb2) +#define PWM50T2L (*(unsigned char volatile xdata *)0xfcb3) +#define PWM50CR (*(unsigned char volatile xdata *)0xfcb4) +#define PWM50HLD (*(unsigned char volatile xdata *)0xfcb5) +#define PWM51T1 (*(unsigned int volatile xdata *)0xfcb8) +#define PWM51T1H (*(unsigned char volatile xdata *)0xfcb8) +#define PWM51T1L (*(unsigned char volatile xdata *)0xfcb9) +#define PWM51T2 (*(unsigned int volatile xdata *)0xfcba) +#define PWM51T2H (*(unsigned char volatile xdata *)0xfcba) +#define PWM51T2L (*(unsigned char volatile xdata *)0xfcbb) +#define PWM51CR (*(unsigned char volatile xdata *)0xfcbc) +#define PWM51HLD (*(unsigned char volatile xdata *)0xfcbd) +#define PWM52T1 (*(unsigned int volatile xdata *)0xfcc0) +#define PWM52T1H (*(unsigned char volatile xdata *)0xfcc0) +#define PWM52T1L (*(unsigned char volatile xdata *)0xfcc1) +#define PWM52T2 (*(unsigned int volatile xdata *)0xfcc2) +#define PWM52T2H (*(unsigned char volatile xdata *)0xfcc2) +#define PWM52T2L (*(unsigned char volatile xdata *)0xfcc3) +#define PWM52CR (*(unsigned char volatile xdata *)0xfcc4) +#define PWM52HLD (*(unsigned char volatile xdata *)0xfcc5) +#define PWM53T1 (*(unsigned int volatile xdata *)0xfcc8) +#define PWM53T1H (*(unsigned char volatile xdata *)0xfcc8) +#define PWM53T1L (*(unsigned char volatile xdata *)0xfcc9) +#define PWM53T2 (*(unsigned int volatile xdata *)0xfcca) +#define PWM53T2H (*(unsigned char volatile xdata *)0xfcca) +#define PWM53T2L (*(unsigned char volatile xdata *)0xfccb) +#define PWM53CR (*(unsigned char volatile xdata *)0xfccc) +#define PWM53HLD (*(unsigned char volatile xdata *)0xfccd) +#define PWM54T1 (*(unsigned int volatile xdata *)0xfcd0) +#define PWM54T1H (*(unsigned char volatile xdata *)0xfcd0) +#define PWM54T1L (*(unsigned char volatile xdata *)0xfcd1) +#define PWM54T2 (*(unsigned int volatile xdata *)0xfcd2) +#define PWM54T2H (*(unsigned char volatile xdata *)0xfcd2) +#define PWM54T2L (*(unsigned char volatile xdata *)0xfcd3) +#define PWM54CR (*(unsigned char volatile xdata *)0xfcd4) +#define PWM54HLD (*(unsigned char volatile xdata *)0xfcd5) +#define PWM55T1 (*(unsigned int volatile xdata *)0xfcd8) +#define PWM55T1H (*(unsigned char volatile xdata *)0xfcd8) +#define PWM55T1L (*(unsigned char volatile xdata *)0xfcd9) +#define PWM55T2 (*(unsigned int volatile xdata *)0xfcda) +#define PWM55T2H (*(unsigned char volatile xdata *)0xfcda) +#define PWM55T2L (*(unsigned char volatile xdata *)0xfcdb) +#define PWM55CR (*(unsigned char volatile xdata *)0xfcdc) +#define PWM55HLD (*(unsigned char volatile xdata *)0xfcdd) +#define PWM56T1 (*(unsigned int volatile xdata *)0xfce0) +#define PWM56T1H (*(unsigned char volatile xdata *)0xfce0) +#define PWM56T1L (*(unsigned char volatile xdata *)0xfce1) +#define PWM56T2 (*(unsigned int volatile xdata *)0xfce2) +#define PWM56T2H (*(unsigned char volatile xdata *)0xfce2) +#define PWM56T2L (*(unsigned char volatile xdata *)0xfce3) +#define PWM56CR (*(unsigned char volatile xdata *)0xfce4) +#define PWM56HLD (*(unsigned char volatile xdata *)0xfce5) +#define PWM57T1 (*(unsigned int volatile xdata *)0xfce8) +#define PWM57T1H (*(unsigned char volatile xdata *)0xfce8) +#define PWM57T1L (*(unsigned char volatile xdata *)0xfce9) +#define PWM57T2 (*(unsigned int volatile xdata *)0xfcea) +#define PWM57T2H (*(unsigned char volatile xdata *)0xfcea) +#define PWM57T2L (*(unsigned char volatile xdata *)0xfceb) +#define PWM57CR (*(unsigned char volatile xdata *)0xfcec) +#define PWM57HLD (*(unsigned char volatile xdata *)0xfced) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMSET = 0xF1H; ENGLBSET PWMRST ENPWM5 ENPWM4 ENPWM3 ENPWM2 ENPWM1 ENPWM0 0000,0000 /* ǿPWMȫüĴ */ +#define PWM15_SET_Uniform() PWMSET |= 0x80 //16PWMͳһ÷ʽ +#define PWM15_SET_Independent() PWMSET &= ~0x80 //06PWMøԶ÷ʽ + +#define PWM15_Reset() PWMSET |= 0x40 //1λPWMXFRĴSFR + +#define PWM15_PWM5_Enable() PWMSET |= 0x20 //1ʹPWM5 PWM50~PWM54 +#define PWM15_PWM5_Disable() PWMSET &= ~0x20 //0رPWM5 + +#define PWM15_PWM4_Enable() PWMSET |= 0x10 //1ʹPWM4 PWM40~PWM47 +#define PWM15_PWM4_Disable() PWMSET &= ~0x10 //0رPWM4 + +#define PWM15_PWM3_Enable() PWMSET |= 0x08 //1ʹPWM3 PWM30~PWM37 +#define PWM15_PWM3_Disable() PWMSET &= ~0x08 //0رPWM3 + +#define PWM15_PWM2_Enable() PWMSET |= 0x04 //1ʹPWM2 PWM20~PWM27 +#define PWM15_PWM2_Disable() PWMSET &= ~0x04 //0رPWM2 + +#define PWM15_PWM1_Enable() PWMSET |= 0x02 //1ʹPWM1 PWM10~PWM17 +#define PWM15_PWM1_Disable() PWMSET &= ~0x02 //0رPWM1 + +#define PWM15_PWM0_Enable() PWMSET |= 0x01 //1ʹPWM0 PWM00~PWM07 +#define PWM15_PWM0_Disable() PWMSET &= ~0x01 //0رPWM0 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMCFG01= 0xF6H; PWM1CBIF EPWM1CBI FLTPS0 PWM1CEN PWM0CBIF EPWM0CBI ENPWM0TA PWM0CEN 0000,0000 /* ǿPWMüĴ */ +//sfr PWMCFG23= 0xF7H; PWM3CBIF EPWM3CBI FLTPS1 PWM3CEN PWM2CBIF EPWM2CBI ENPWM2TA PWM2CEN 0000,0000 /* ǿPWMüĴ */ +//sfr PWMCFG45= 0xFEH; PWM5CBIF EPWM5CBI FLTPS2 PWM5CEN PWM4CBIF EPWM4CBI ENPWM4TA PWM4CEN 0000,0000 /* ǿPWMüĴ */ +#define PWM1CBIF 0x80 +#define PWM0CBIF 0x08 +#define FLTPSn 0x20 + +#define PWM15_Counter1Int_Enable() PWMCFG01 |= 0x40 //1ʹܼж +#define PWM15_Counter1Int_Disable() PWMCFG01 &= ~0x40 //0رռж +#define PWM15_Counter1_Enable() PWMCFG01 |= 0x10 //1ʹܼ +#define PWM15_Counter1_Disable() PWMCFG01 &= ~0x10 //0رռ +#define PWM15_Counter0Int_Enable() PWMCFG01 |= 0x04 //1ʹܼж +#define PWM15_Counter0Int_Disable() PWMCFG01 &= ~0x04 //0رռж +#define PWM15_Counter0_Enable() PWMCFG01 |= 0x01 //1ʹܼ +#define PWM15_Counter0_Disable() PWMCFG01 &= ~0x01 //0رռ +#define PWM15_PWM0_ADC_Enable() PWMCFG01 |= 0x02 //1PWMADC +#define PWM15_PWM0_ADC_Disable() PWMCFG01 &= ~0x02 //0PWMADC + +#define PWM15_Counter3Int_Enable() PWMCFG23 |= 0x40 //1ʹܼж +#define PWM15_Counter3Int_Disable() PWMCFG23 &= ~0x40 //0رռж +#define PWM15_Counter3_Enable() PWMCFG23 |= 0x10 //1ʹܼ +#define PWM15_Counter3_Disable() PWMCFG23 &= ~0x10 //0رռ +#define PWM15_Counter2Int_Enable() PWMCFG23 |= 0x04 //1ʹܼж +#define PWM15_Counter2Int_Disable() PWMCFG23 &= ~0x04 //0رռж +#define PWM15_Counter2_Enable() PWMCFG23 |= 0x01 //1ʹܼ +#define PWM15_Counter2_Disable() PWMCFG23 &= ~0x01 //0رռ +#define PWM15_PWM2_ADC_Enable() PWMCFG23 |= 0x02 //1PWMADC +#define PWM15_PWM2_ADC_Disable() PWMCFG23 &= ~0x02 //0PWMADC + +#define PWM15_Counter5Int_Enable() PWMCFG45 |= 0x40 //1ʹܼж +#define PWM15_Counter5Int_Disable() PWMCFG45 &= ~0x40 //0رռж +#define PWM15_Counter5_Enable() PWMCFG45 |= 0x10 //1ʹܼ +#define PWM15_Counter5_Disable() PWMCFG45 &= ~0x10 //0رռ +#define PWM15_Counter4Int_Enable() PWMCFG45 |= 0x04 //1ʹܼж +#define PWM15_Counter4Int_Disable() PWMCFG45 &= ~0x04 //0رռж +#define PWM15_Counter4_Enable() PWMCFG45 |= 0x01 //1ʹܼ +#define PWM15_Counter4_Disable() PWMCFG45 &= ~0x01 //0رռ +#define PWM15_PWM4_ADC_Enable() PWMCFG45 |= 0x02 //1PWMADC +#define PWM15_PWM4_ADC_Disable() PWMCFG45 &= ~0x02 //0PWMADC + +/* PWMnIF */ +#define C7IF = (1<<7) +#define C6IF = (1<<6) +#define C5IF = (1<<5) +#define C4IF = (1<<4) +#define C3IF = (1<<3) +#define C2IF = (1<<2) +#define C1IF = (1<<1) +#define C0IF = 1 + +/* PWMnFDCR */ +#define INVCMP = (1<<7) +#define INVIO = (1<<6) +#define ENFD = (1<<5) +#define FLTFLIO = (1<<4) +#define EFDI = (1<<3) +#define FDCMP = (1<<2) +#define FDIO = (1<<1) +#define FDIF = 1 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWM0CKS = 0xFF02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +//sfr PWM1CKS = 0xFF52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +//sfr PWM2CKS = 0xFFA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +//sfr PWM3CKS = 0xFC02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +//sfr PWM4CKS = 0xFC52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +//sfr PWM5CKS = 0xFCA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */ +#define PWM0_PS_Clock() PWM0CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM0_T2_Clock() PWM0CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM0_PS_Set(n) PWM0CKS = (PWM0CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) +#define PWM1_PS_Clock() PWM1CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM1_T2_Clock() PWM1CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM1_PS_Set(n) PWM1CKS = (PWM1CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) +#define PWM2_PS_Clock() PWM2CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM2_T2_Clock() PWM2CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM2_PS_Set(n) PWM2CKS = (PWM2CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) +#define PWM3_PS_Clock() PWM3CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM3_T2_Clock() PWM3CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM3_PS_Set(n) PWM3CKS = (PWM3CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) +#define PWM4_PS_Clock() PWM4CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM4_T2_Clock() PWM4CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM4_PS_Set(n) PWM4CKS = (PWM4CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) +#define PWM5_PS_Clock() PWM5CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ +#define PWM5_T2_Clock() PWM5CKS |= 0x10 //1PWMnʱԴΪʱ2 +#define PWM5_PS_Set(n) PWM5CKS = (PWM5CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1) + +/* PWMnTADC */ +#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWMADCʱ +#define PWM15_PWM2TADC(n) PWM2TADC = (n & 0x7fff) //PWMADCʱ +#define PWM15_PWM4TADC(n) PWM4TADC = (n & 0x7fff) //PWMADCʱ + +/* PWMnTADC */ +#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWMADCʱ + + +/* BIT Registers */ +/* PSW */ +sbit CY = PSW^7; +sbit AC = PSW^6; +sbit F0 = PSW^5; +sbit RS1 = PSW^4; +sbit RS0 = PSW^3; +sbit OV = PSW^2; +sbit F1 = PSW^1; +sbit P = PSW^0; + +/* TCON */ +sbit TF1 = TCON^7; //ʱ1жϱ־λ +sbit TR1 = TCON^6; //ʱ1пλ +sbit TF0 = TCON^5; //ʱ0жϱ־λ +sbit TR0 = TCON^4; //ʱ0пλ +sbit IE1 = TCON^3; //ж1־λ +sbit IT1 = TCON^2; //ж1źŷʽλ1½жϣ0½жϡ +sbit IE0 = TCON^1; //ж0־λ +sbit IT0 = TCON^0; //ж0źŷʽλ1½жϣ0½жϡ + +/* P0 */ +sbit P00 = P0^0; +sbit P01 = P0^1; +sbit P02 = P0^2; +sbit P03 = P0^3; +sbit P04 = P0^4; +sbit P05 = P0^5; +sbit P06 = P0^6; +sbit P07 = P0^7; + +/* P1 */ +sbit P10 = P1^0; +sbit P11 = P1^1; +sbit P12 = P1^2; +sbit P13 = P1^3; +sbit P14 = P1^4; +sbit P15 = P1^5; +sbit P16 = P1^6; +sbit P17 = P1^7; + +sbit RXD2 = P1^0; +sbit TXD2 = P1^1; +sbit CCP1 = P1^0; +sbit CCP0 = P1^1; +sbit SPI_SS = P1^2; +sbit SPI_MOSI = P1^3; +sbit SPI_MISO = P1^4; +sbit SPI_SCLK = P1^5; + +sbit SPI_SS_2 = P2^2; +sbit SPI_MOSI_2 = P2^3; +sbit SPI_MISO_2 = P2^4; +sbit SPI_SCLK_2 = P2^5; + +sbit SPI_SS_3 = P5^4; +sbit SPI_MOSI_3 = P4^0; +sbit SPI_MISO_3 = P4^1; +sbit SPI_SCLK_3 = P4^3; + +sbit SPI_SS_4 = P3^5; +sbit SPI_MOSI_4 = P3^4; +sbit SPI_MISO_4 = P3^3; +sbit SPI_SCLK_4 = P3^2; + +/* P2 */ +sbit P20 = P2^0; +sbit P21 = P2^1; +sbit P22 = P2^2; +sbit P23 = P2^3; +sbit P24 = P2^4; +sbit P25 = P2^5; +sbit P26 = P2^6; +sbit P27 = P2^7; + +/* P3 */ +sbit P30 = P3^0; +sbit P31 = P3^1; +sbit P32 = P3^2; +sbit P33 = P3^3; +sbit P34 = P3^4; +sbit P35 = P3^5; +sbit P36 = P3^6; +sbit P37 = P3^7; + +sbit RXD = P3^0; +sbit TXD = P3^1; +sbit INT0 = P3^2; +sbit INT1 = P3^3; +sbit T0 = P3^4; +sbit T1 = P3^5; +sbit WR = P3^6; +sbit RD = P3^7; + +sbit INT2 = P3^6; +sbit INT3 = P3^7; +sbit INT4 = P3^0; +sbit CCP2 = P3^7; + +sbit CLKOUT0 = P3^5; +sbit CLKOUT1 = P3^4; + +/* P4 */ +sbit P40 = P4^0; +sbit P41 = P4^1; +sbit P42 = P4^2; +sbit P43 = P4^3; +sbit P44 = P4^4; +sbit P45 = P4^5; +sbit P46 = P4^6; +sbit P47 = P4^7; + +/* P5 */ +sbit P50 = P5^0; +sbit P51 = P5^1; +sbit P52 = P5^2; +sbit P53 = P5^3; +sbit P54 = P5^4; +sbit P55 = P5^5; +sbit P56 = P5^6; +sbit P57 = P5^7; + +/* P6 */ +sbit P60 = P6^0; +sbit P61 = P6^1; +sbit P62 = P6^2; +sbit P63 = P6^3; +sbit P64 = P6^4; +sbit P65 = P6^5; +sbit P66 = P6^6; +sbit P67 = P6^7; + +/* P7 */ +sbit P70 = P7^0; +sbit P71 = P7^1; +sbit P72 = P7^2; +sbit P73 = P7^3; +sbit P74 = P7^4; +sbit P75 = P7^5; +sbit P76 = P7^6; +sbit P77 = P7^7; + + +/* SCON */ +sbit SM0 = SCON^7; //SM0/FE SM0 SM1 = 00 ~ 11: ʽ0~3 +sbit SM1 = SCON^6; // +sbit SM2 = SCON^5; //ͨѶ +sbit REN = SCON^4; // +sbit TB8 = SCON^3; //ݵ8λ +sbit RB8 = SCON^2; //ݵ8λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + +/* IE */ +sbit EA = IE^7; //жܿλ +sbit ELVD = IE^6; //ѹжλ +sbit EADC = IE^5; //ADC ж λ +sbit ES = IE^4; //ж λ +sbit ET1 = IE^3; //ʱж1λ +sbit EX1 = IE^2; //ⲿж1λ +sbit ET0 = IE^1; //ʱж0λ +sbit EX0 = IE^0; //ⲿж0λ + +sbit ACC0 = ACC^0; +sbit ACC1 = ACC^1; +sbit ACC2 = ACC^2; +sbit ACC3 = ACC^3; +sbit ACC4 = ACC^4; +sbit ACC5 = ACC^5; +sbit ACC6 = ACC^6; +sbit ACC7 = ACC^7; + +sbit B0 = B^0; +sbit B1 = B^1; +sbit B2 = B^2; +sbit B3 = B^3; +sbit B4 = B^4; +sbit B5 = B^5; +sbit B6 = B^6; +sbit B7 = B^7; + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IE2 = 0xAF; ETKSUI ET4 ET3 ES4 ES3 ET2 ESPI ES2 x000,0000B //Auxiliary Interrupt +#define SPI_INT_ENABLE() IE2 |= 2 /* SPIж */ +#define SPI_INT_DISABLE() IE2 &= ~2 /* SPIж */ +#define UART2_INT_ENABLE() IE2 |= 1 /* 2ж */ +#define UART2_INT_DISABLE() IE2 &= ~1 /* 2ж */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP2 = 0xB5; // PPWM2FD PI2C PCMP PX4 PPWM0FD PPWM0 PSPI PS2 0000,0000 +#define PUSB 0x80 +#define PPWM2FD 0x80 +#define PTKSU 0x80 +#define PI2C 0x40 +#define PCMP 0x20 +#define PX4 0x10 +#define PPWM0FD 0x08 +#define PPWM0 0x04 +#define PSPI 0x02 +#define PS2 0x01 +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP2H = 0xB6; // PPWM2FDH PI2CH PCMPH PX4H PPWM0FDH PPWM0H PSPIH PS2H 0000,0000 +#define PUSBH 0x80 +#define PPWM2FDH 0x80 +#define PTKSUH 0x80 +#define PI2CH 0x40 +#define PCMPH 0x20 +#define PX4H 0x10 +#define PPWM0FDH 0x08 +#define PPWM0H 0x04 +#define PSPIH 0x02 +#define PS2H 0x01 + +//2жȼ +#define UART2_Priority(n) do{if(n == 0) IP2H &= ~PS2H, IP2 &= ~PS2; \ + if(n == 1) IP2H &= ~PS2H, IP2 |= PS2; \ + if(n == 2) IP2H |= PS2H, IP2 &= ~PS2; \ + if(n == 3) IP2H |= PS2H, IP2 |= PS2; \ + }while(0) +//SPIжȼ +#define SPI_Priority(n) do{if(n == 0) IP2H &= ~PSPIH, IP2 &= ~PSPI; \ + if(n == 1) IP2H &= ~PSPIH, IP2 |= PSPI; \ + if(n == 2) IP2H |= PSPIH, IP2 &= ~PSPI; \ + if(n == 3) IP2H |= PSPIH, IP2 |= PSPI; \ + }while(0) +//ⲿж4жȼ +#define INT4_Priority(n) do{if(n == 0) IP2H &= ~PX4H, IP2 &= ~PX4; \ + if(n == 1) IP2H &= ~PX4H, IP2 |= PX4; \ + if(n == 2) IP2H |= PX4H, IP2 &= ~PX4; \ + if(n == 3) IP2H |= PX4H, IP2 |= PX4; \ + }while(0) +//Ƚжȼ +#define CMP_Priority(n) do{if(n == 0) IP2H &= ~PCMPH, IP2 &= ~PCMP; \ + if(n == 1) IP2H &= ~PCMPH, IP2 |= PCMP; \ + if(n == 2) IP2H |= PCMPH, IP2 &= ~PCMP; \ + if(n == 3) IP2H |= PCMPH, IP2 |= PCMP; \ + }while(0) +//I2Cжȼ +#define I2C_Priority(n) do{if(n == 0) IP2H &= ~PI2CH, IP2 &= ~PI2C; \ + if(n == 1) IP2H &= ~PI2CH, IP2 |= PI2C; \ + if(n == 2) IP2H |= PI2CH, IP2 &= ~PI2C; \ + if(n == 3) IP2H |= PI2CH, IP2 |= PI2C; \ + }while(0) +//ǿPWM0жȼ +#define PWM0_Priority(n) do{if(n == 0) IP2H &= ~PPWM0H, IP2 &= ~PPWM0; \ + if(n == 1) IP2H &= ~PPWM0H, IP2 |= PPWM0; \ + if(n == 2) IP2H |= PPWM0H, IP2 &= ~PPWM0; \ + if(n == 3) IP2H |= PPWM0H, IP2 |= PPWM0; \ + }while(0) +//ǿPWM0쳣жȼ +#define PWM0FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM0FDH, IP2 &= ~PPWM0FD; \ + if(n == 1) IP2H &= ~PPWM0FDH, IP2 |= PPWM0FD; \ + if(n == 2) IP2H |= PPWM0FDH, IP2 &= ~PPWM0FD; \ + if(n == 3) IP2H |= PPWM0FDH, IP2 |= PPWM0FD; \ + }while(0) +//ǿPWM2쳣жȼ +#define PWM2FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM2FDH, IP2 &= ~PPWM2FD; \ + if(n == 1) IP2H &= ~PPWM2FDH, IP2 |= PPWM2FD; \ + if(n == 2) IP2H |= PPWM2FDH, IP2 &= ~PPWM2FD; \ + if(n == 3) IP2H |= PPWM2FDH, IP2 |= PPWM2FD; \ + }while(0) +//жȼ +#define PTKSU_Priority(n) do{if(n == 0) IP2H &= ~PTKSUH, IP2 &= ~PTKSU; \ + if(n == 1) IP2H &= ~PTKSUH, IP2 |= PTKSU; \ + if(n == 2) IP2H |= PTKSUH, IP2 &= ~PTKSU; \ + if(n == 3) IP2H |= PTKSUH, IP2 |= PTKSU; \ + }while(0) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP3 = 0xDF; // PPWM4FD PPWM5 PPWM4 PPWM3 PPWM2 PPWM1 PS4 PS3 0000,0000 +#define PPWM4FD 0x80 +#define PPWM5 0x40 +#define PPWM4 0x20 +#define PPWM3 0x10 +#define PPWM2 0x08 +#define PPWM1 0x04 +#define PRTC 0x04 +#define PS4 0x02 +#define PS3 0x01 +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP3H = 0xEE; // PPWM4FDH PPWM5H PPWM4H PPWM3H PPWM2H PPWM1H PS4H PS3H 0000,0000 +#define PPWM4FDH 0x80 +#define PPWM5H 0x40 +#define PPWM4H 0x20 +#define PPWM3H 0x10 +#define PPWM2H 0x08 +#define PPWM1H 0x04 +#define PRTCH 0x04 +#define PS4H 0x02 +#define PS3H 0x01 + +#ifdef STC8Hxx + +//ǿPWM1жȼ +#define PWM1_Priority(n) do{if(n == 0) IP2H &= ~PPWM1H, IP2 &= ~PPWM1; \ + if(n == 1) IP2H &= ~PPWM1H, IP2 |= PPWM1; \ + if(n == 2) IP2H |= PPWM1H, IP2 &= ~PPWM1; \ + if(n == 3) IP2H |= PPWM1H, IP2 |= PPWM1; \ + }while(0) +//ǿPWM2жȼ +#define PWM2_Priority(n) do{if(n == 0) IP2H &= ~PPWM2H, IP2 &= ~PPWM2; \ + if(n == 1) IP2H &= ~PPWM2H, IP2 |= PPWM2; \ + if(n == 2) IP2H |= PPWM2H, IP2 &= ~PPWM2; \ + if(n == 3) IP2H |= PPWM2H, IP2 |= PPWM2; \ + }while(0) +//USBжȼ +#define USB_Priority(n) do{if(n == 0) IP2H &= ~PUSBH, IP2 &= ~PUSB; \ + if(n == 1) IP2H &= ~PUSBH, IP2 |= PUSB; \ + if(n == 2) IP2H |= PUSBH, IP2 &= ~PUSB; \ + if(n == 3) IP2H |= PUSBH, IP2 |= PUSB; \ + }while(0) +//RTCжȼ +#define RTC_Priority(n) do{if(n == 0) IP3H &= ~PRTCH, IP3 &= ~PRTC; \ + if(n == 1) IP3H &= ~PRTCH, IP3 |= PRTC; \ + if(n == 2) IP3H |= PRTCH, IP3 &= ~PRTC; \ + if(n == 3) IP3H |= PRTCH, IP3 |= PRTC; \ + }while(0) +#else + +//ǿPWM1жȼ +#define PWM1_Priority(n) do{if(n == 0) IP3H &= ~PPWM1H, IP3 &= ~PPWM1; \ + if(n == 1) IP3H &= ~PPWM1H, IP3 |= PPWM1; \ + if(n == 2) IP3H |= PPWM1H, IP3 &= ~PPWM1; \ + if(n == 3) IP3H |= PPWM1H, IP3 |= PPWM1; \ + }while(0) +//ǿPWM2жȼ +#define PWM2_Priority(n) do{if(n == 0) IP3H &= ~PPWM2H, IP3 &= ~PPWM2; \ + if(n == 1) IP3H &= ~PPWM2H, IP3 |= PPWM2; \ + if(n == 2) IP3H |= PPWM2H, IP3 &= ~PPWM2; \ + if(n == 3) IP3H |= PPWM2H, IP3 |= PPWM2; \ + }while(0) + +#endif + +//ǿPWM3жȼ +#define PWM3_Priority(n) do{if(n == 0) IP3H &= ~PPWM3H, IP3 &= ~PPWM3; \ + if(n == 1) IP3H &= ~PPWM3H, IP3 |= PPWM3; \ + if(n == 2) IP3H |= PPWM3H, IP3 &= ~PPWM3; \ + if(n == 3) IP3H |= PPWM3H, IP3 |= PPWM3; \ + }while(0) +//ǿPWM4жȼ +#define PWM4_Priority(n) do{if(n == 0) IP3H &= ~PPWM4H, IP3 &= ~PPWM4; \ + if(n == 1) IP3H &= ~PPWM4H, IP3 |= PPWM4; \ + if(n == 2) IP3H |= PPWM4H, IP3 &= ~PPWM4; \ + if(n == 3) IP3H |= PPWM4H, IP3 |= PPWM4; \ + }while(0) +//ǿPWM5жȼ +#define PWM5_Priority(n) do{if(n == 0) IP3H &= ~PPWM5H, IP3 &= ~PPWM5; \ + if(n == 1) IP3H &= ~PPWM5H, IP3 |= PPWM5; \ + if(n == 2) IP3H |= PPWM5H, IP3 &= ~PPWM5; \ + if(n == 3) IP3H |= PPWM5H, IP3 |= PPWM5; \ + }while(0) +//ǿPWM4쳣жȼ +#define PWM4FD_Priority(n) do{if(n == 0) IP3H &= ~PPWM4FDH, IP3 &= ~PPWM4FD; \ + if(n == 1) IP3H &= ~PPWM4FDH, IP3 |= PPWM4FD; \ + if(n == 2) IP3H |= PPWM4FDH, IP3 &= ~PPWM4FD; \ + if(n == 3) IP3H |= PPWM4FDH, IP3 |= PPWM4FD; \ + }while(0) +//3жȼ +#define UART3_Priority(n) do{if(n == 0) IP3H &= ~PS3H, IP3 &= ~PS3; \ + if(n == 1) IP3H &= ~PS3H, IP3 |= PS3; \ + if(n == 2) IP3H |= PS3H, IP3 &= ~PS3; \ + if(n == 3) IP3H |= PS3H, IP3 |= PS3; \ + }while(0) +//4жȼ +#define UART4_Priority(n) do{if(n == 0) IP3H &= ~PS4H, IP3 &= ~PS4; \ + if(n == 1) IP3H &= ~PS4H, IP3 |= PS4; \ + if(n == 2) IP3H |= PS4H, IP3 &= ~PS4; \ + if(n == 3) IP3H |= PS4H, IP3 |= PS4; \ + }while(0) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP = 0xB8; //жȼλ PPCA PLVD PADC PS PT1 PX1 PT0 PX0 0000,0000 +//-------- +sbit PPCA = IP^7; //PCA ģжȼ +sbit PLVD = IP^6; //ѹжȼ +sbit PADC = IP^5; //ADC жȼ +sbit PS = IP^4; //ж0ȼ趨λ +sbit PT1 = IP^3; //ʱж1ȼ趨λ +sbit PX1 = IP^2; //ⲿж1ȼ趨λ +sbit PT0 = IP^1; //ʱж0ȼ趨λ +sbit PX0 = IP^0; //ⲿж0ȼ趨λ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IPH = 0xB7; //жȼλ PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 0000,0000 +#define PPCAH 0x80 +#define PLVDH 0x40 +#define PADCH 0x20 +#define PSH 0x10 +#define PT1H 0x08 +#define PX1H 0x04 +#define PT0H 0x02 +#define PX0H 0x01 + +//ⲿж0жȼ +#define INT0_Priority(n) do{if(n == 0) IPH &= ~PX0H, PX0 = 0; \ + if(n == 1) IPH &= ~PX0H, PX0 = 1; \ + if(n == 2) IPH |= PX0H, PX0 = 0; \ + if(n == 3) IPH |= PX0H, PX0 = 1; \ + }while(0) +//ⲿж1жȼ +#define INT1_Priority(n) do{if(n == 0) IPH &= ~PX1H, PX1 = 0; \ + if(n == 1) IPH &= ~PX1H, PX1 = 1; \ + if(n == 2) IPH |= PX1H, PX1 = 0; \ + if(n == 3) IPH |= PX1H, PX1 = 1; \ + }while(0) +//ʱ0жȼ +#define Timer0_Priority(n) do{if(n == 0) IPH &= ~PT0H, PT0 = 0; \ + if(n == 1) IPH &= ~PT0H, PT0 = 1; \ + if(n == 2) IPH |= PT0H, PT0 = 0; \ + if(n == 3) IPH |= PT0H, PT0 = 1; \ + }while(0) +//ʱ1жȼ +#define Timer1_Priority(n) do{if(n == 0) IPH &= ~PT1H, PT1 = 0; \ + if(n == 1) IPH &= ~PT1H, PT1 = 1; \ + if(n == 2) IPH |= PT1H, PT1 = 0; \ + if(n == 3) IPH |= PT1H, PT1 = 1; \ + }while(0) +//1жȼ +#define UART1_Priority(n) do{if(n == 0) IPH &= ~PSH, PS = 0; \ + if(n == 1) IPH &= ~PSH, PS = 1; \ + if(n == 2) IPH |= PSH, PS = 0; \ + if(n == 3) IPH |= PSH, PS = 1; \ + }while(0) +//ADCжȼ +#define ADC_Priority(n) do{if(n == 0) IPH &= ~PADCH, PADC = 0; \ + if(n == 1) IPH &= ~PADCH, PADC = 1; \ + if(n == 2) IPH |= PADCH, PADC = 0; \ + if(n == 3) IPH |= PADCH, PADC = 1; \ + }while(0) +//ѹжȼ +#define LVD_Priority(n) do{if(n == 0) IPH &= ~PLVDH, PADC = 0; \ + if(n == 1) IPH &= ~PLVDH, PADC = 1; \ + if(n == 2) IPH |= PLVDH, PADC = 0; \ + if(n == 3) IPH |= PLVDH, PADC = 1; \ + }while(0) +//CCP/PCA/PWMжȼ +#define PCA_Priority(n) do{if(n == 0) IPH &= ~PPCAH, PPCA = 0; \ + if(n == 1) IPH &= ~PPCAH, PPCA = 1; \ + if(n == 2) IPH |= PPCAH, PPCA = 0; \ + if(n == 3) IPH |= PPCAH, PPCA = 1; \ + }while(0) + +//#define PCA_InterruptFirst() PPCA = 1 +//#define LVD_InterruptFirst() PLVD = 1 +//#define ADC_InterruptFirst() PADC = 1 +//#define UART1_InterruptFirst() PS = 1 +//#define Timer1_InterruptFirst() PT1 = 1 +//#define INT1_InterruptFirst() PX1 = 1 +//#define Timer0_InterruptFirst() PT0 = 1 +//#define INT0_InterruptFirst() PX0 = 1 + + +/*************************************************************************************************/ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMPCR1 = 0xE6; CMPEN CMPIF PIE NIE PIS NIS CMPOE CMPRES 00000000B +#define CMPEN 0x80 //1: Ƚ, 0: ֹ,رձȽԴ +#define CMPIF 0x40 //Ƚжϱ־, ػ½ж, 0 +#define PIE 0x20 //1: ȽϽ01, ж +#define NIE 0x10 //1: ȽϽ10, ½ж +#define PIS 0x08 //ѡ, 0: ѡڲP3.7, 1: ADC_CHS[3:0]ѡADC. +#define NIS 0x04 //븺ѡ, 0: ѡڲBandGapѹBGv, 1: ѡⲿP3.6. +#define CMPOE 0x02 //1: ȽϽ, 0: ֹ. +#define CMPRES 0x01 //ȽϽ, 1: CMP+ƽCMP-, 0: CMP+ƽCMP-, ֻ + +#define CMP_P_P37 0x00 //ѡ, 0: ѡڲP3.7 +#define CMP_P_ADC 0x08 //ѡ, 1: ADC_CHS[3:0]ѡADC. +#define CMP_N_GAP 0x00 //븺ѡ, 0: ѡڲBandGapѹBGv. +#define CMP_N_P36 0x04 //븺ѡ, 1: ѡⲿP3.6. + +#define CMPO_P34() P_SW2 &= ~0x08 //P3.4. +#define CMPO_P41() P_SW2 |= 0x08 //P4.1. + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMPCR2 = 0xE7; INVCMPO DISFLT LCDTY[5:0] 00001001B +#define INVCMPO 0x80 //1: ȽIOȡ, 0: ȡ +#define DISFLT 0x40 //1: ر0.1uF˲, 0: +#define LCDTY 0x00 //0~63, ȽϽ仯ʱ + + + +/*************************************************************************************************/ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr SCON = 0x98; SM0 SM1 SM2 REN TB8 RB8 TI RI 00000000B //S1 Control + +#define S1_DoubleRate() PCON |= 0x80 +#define S1_SHIFT() SCON &= 0x3f + +#define S1_8bit() SCON = (SCON & 0x3f) | 0x40 +#define S1_9bit() SCON = (SCON & 0x3f) | 0xc0 +#define S1_RX_Enable() SCON |= 0x10 +#define S1_RX_Disable() SCON &= ~0x10 +#define TI1 TI /* жTI1Ƿ */ +#define RI1 RI /* жRI1Ƿ */ +#define SET_TI1() TI = 1 /* TI1(ж) */ +#define CLR_TI1() TI = 0 /* TI1 */ +#define CLR_RI1() RI = 0 /* RI1 */ +#define S1TB8_SET() TB8 = 1 /* TB8 */ +#define S1TB8_CLR() TB8 = 0 /* TB8 */ +#define S1_Int_Enable() ES = 1 /* 1ж */ +#define S1_Int_Disable() ES = 0 /* 1ֹж */ +#define S1_BRT_UseTimer1() AUXR &= ~1 +#define S1_BRT_UseTimer2() AUXR |= 1 +#define S1_USE_P30P31() P_SW1 &= ~0xc0 //UART1 ʹP30 P31 Ĭ +#define S1_USE_P36P37() P_SW1 = (P_SW1 & ~0xc0) | 0x40 //UART1 ʹP36 P37 +#define S1_USE_P16P17() P_SW1 = (P_SW1 & ~0xc0) | 0x80 //UART1 ʹP16 P17 +#define S1_USE_P43P44() P_SW1 |= 0xc0 //UART1 ʹP43 P44 +//#define S1_TXD_RXD_SHORT() PCON2 |= (1<<4) //TXDRXDм +//#define S1_TXD_RXD_OPEN() PCON2 &= ~(1<<4) //TXDRXDм̶Ͽ Ĭ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S2CON = 0x9A; S2SM0 - S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B //S2 Control + +#define S2_MODE0() S2CON &= ~(1<<7) /* 2ģʽ08λUART = ʱ2 / 4 */ +#define S2_MODE1() S2CON |= (1<<7) /* 2ģʽ19λUART = ʱ2 / 4 */ +#define S2_8bit() S2CON &= ~(1<<7) /* 2ģʽ08λUART = ʱ2 / 4 */ +#define S2_9bit() S2CON |= (1<<7) /* 2ģʽ19λUART = ʱ2 / 4 */ +#define S2_RX_Enable() S2CON |= (1<<4) /* 2 */ +#define S2_RX_Disable() S2CON &= ~(1<<4) /* ֹ2 */ +#define TI2 (S2CON & 2) /* жTI2Ƿ */ +#define RI2 (S2CON & 1) /* жRI2Ƿ */ +#define SET_TI2() S2CON |= (1<<1) /* TI2(ж) */ +#define CLR_TI2() S2CON &= ~(1<<1) /* TI2 */ +#define CLR_RI2() S2CON &= ~1 /* RI2 */ +#define S2TB8_SET() S2CON |= (1<<3) /* TB8 */ +#define S2TB8_CLR() S2CON &= ~(1<<3) /* TB8 */ +#define S2_Int_Enable() IE2 |= 1 /* 2ж */ +#define S2_Int_Disable() IE2 &= ~1 /* 2ֹж */ +#define S2_USE_P10P11() P_SW2 &= ~1 /* UART2 ʹP1 Ĭ */ +#define S2_USE_P46P47() P_SW2 |= 1 /* UART2 ʹP4 */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S3CON = 0xAC; S3SM0 S3ST3 S3SM2 S3REN S3TB8 S3RB8 S3TI S3RI 00000000B //S3 Control + +#define S3_MODE0() S3CON &= ~(1<<7) /* 3ģʽ08λUART = ʱ / 4 */ +#define S3_MODE1() S3CON |= (1<<7) /* 3ģʽ19λUART = ʱ / 4 */ +#define S3_8bit() S3CON &= ~(1<<7) /* 3ģʽ08λUART = ʱ / 4 */ +#define S3_9bit() S3CON |= (1<<7) /* 3ģʽ19λUART = ʱ / 4 */ +#define S3_RX_Enable() S3CON |= (1<<4) /* 3 */ +#define S3_RX_Disable() S3CON &= ~(1<<4) /* ֹ3 */ +#define TI3 (S3CON & 2) != 0 /* жTI3Ƿ */ +#define RI3 (S3CON & 1) != 0 /* жRI3Ƿ */ +#define SET_TI3() S3CON |= (1<<1) /* TI3(ж) */ +#define CLR_TI3() S3CON &= ~(1<<1) /* TI3 */ +#define CLR_RI3() S3CON &= ~1 /* RI3 */ +#define S3TB8_SET() S3CON |= (1<<3) /* TB8 */ +#define S3TB8_CLR() S3CON &= ~(1<<3) /* TB8 */ +#define S3_Int_Enable() IE2 |= (1<<3) /* 3ж */ +#define S3_Int_Disable() IE2 &= ~(1<<3) /* 3ֹж */ +#define S3_BRT_UseTimer3() S3CON |= (1<<6) /* BRT select Timer3 */ +#define S3_BRT_UseTimer2() S3CON &= ~(1<<6) /* BRT select Timer2 */ +#define S3_USE_P00P01() P_SW2 &= ~2 /* UART3 ʹP0 Ĭ */ +#define S3_USE_P50P51() P_SW2 |= 2 /* UART3 ʹP5 */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S4CON = 0x84; S4SM0 S4ST4 S4SM2 S4REN S4TB8 S4RB8 S4TI S4RI 00000000B //S4 Control + +#define S4_MODE0() S4CON &= ~(1<<7) /* 4ģʽ08λUART = ʱ / 4 */ +#define S4_MODE1() S4CON |= (1<<7) /* 4ģʽ19λUART = ʱ / 4 */ +#define S4_8bit() S4CON &= ~(1<<7) /* 4ģʽ08λUART = ʱ / 4 */ +#define S4_9bit() S4CON |= (1<<7) /* 4ģʽ19λUART = ʱ / 4 */ +#define S4_RX_Enable() S4CON |= (1<<4) /* 4 */ +#define S4_RX_Disable() S4CON &= ~(1<<4) /* ֹ4 */ +#define TI4 (S4CON & 2) != 0 /* жTI3Ƿ */ +#define RI4 (S4CON & 1) != 0 /* жRI3Ƿ */ +#define SET_TI4() S4CON |= 2 /* TI3(ж) */ +#define CLR_TI4() S4CON &= ~2 /* TI3 */ +#define CLR_RI4() S4CON &= ~1 /* RI3 */ +#define S4TB8_SET() S4CON |= 8 /* TB8 */ +#define S4TB8_CLR() S4CON &= ~8 /* TB8 */ +#define S4_Int_Enable() IE2 |= (1<<4) /* 4ж */ +#define S4_Int_Disable() IE2 &= ~(1<<4) /* 4ֹж */ +#define S4_BRT_UseTimer4() S4CON |= (1<<6) /* BRT select Timer4 */ +#define S4_BRT_UseTimer2() S4CON &= ~(1<<6) /* BRT select Timer2 */ +#define S4_USE_P02P03() P_SW2 &= ~4 /* UART4 ʹP0 Ĭ */ +#define S4_USE_P52P53() P_SW2 |= 4 /* UART4 ʹP5 */ + + + +/**********************************************************/ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr AUXR = 0x8E; T0x12 T1x12 UART_M0x6 T2R T2_C/T T2x12 EXTRAM S1ST2 0000,0000 //Auxiliary Register + +#define InternalXdata_Disable() AUXR |= 2 /* ֹʹڲxdata, зxdataǷⲿxdata */ +#define InternalXdata_Enable() AUXR &= ~2 /* ʹڲxdata, ʵĵַڲxdataΧʱ, ڲxadta, ַڲxdataʱ, ⲿxdata */ +#define S1_M0x6() AUXR |= (1<<5) /* UART Mode0 Speed is 6x Standard */ +#define S1_M0x1() AUXR &= ~(1<<5) /* default, UART Mode0 Speed is Standard */ + +//==================================== +#define Timer0_16bitAutoReload() TMOD &= ~0x03 /* 16λԶװ */ +#define Timer0_16bit() TMOD = (TMOD & ~0x03) | 0x01 /* 16λ */ +#define Timer0_8bitAutoReload() TMOD = (TMOD & ~0x03) | 0x02 /* 8λԶװ */ +#define Timer0_16bitAutoRL_NoMask() TMOD |= 0x03 /* 16λԶװж */ +#define Timer0_Run() TR0 = 1 /* ʱ0 */ +#define Timer0_Stop() TR0 = 0 /* ֹʱ0 */ +#define Timer0_Gate_INT0_P32() TMOD |= (1<<3) /* ʱ0ⲿINT0ߵƽʱ */ +#define Timer0_AsTimer() TMOD &= ~(1<<2) /* ʱ0ʱ */ +#define Timer0_AsCounter() TMOD |= (1<<2) /* ʱ0 */ +#define Timer0_AsCounterP34() TMOD |= (1<<2) /* ʱ0 */ +#define Timer0_1T() AUXR |= (1<<7) /* Timer0 clodk = fo */ +#define Timer0_12T() AUXR &= ~(1<<7) /* Timer0 clodk = fo/12 12Ƶ, default */ +#define Timer0_CLKO_Enable() INT_CLKO |= 1 /* T0 T0(P3.5)Fck0 = 1/2 T0 ʣT01T12T */ +#define Timer0_CLKO_Disable() INT_CLKO &= ~1 +#define Timer0_CLKO_Enable_P34() INT_CLKO |= 1 /* T0 T0(P3.5)Fck0 = 1/2 T0 ʣT01T12T */ +#define Timer0_CLKO_Disable_P34() INT_CLKO &= ~1 +#define Timer0_InterruptEnable() ET0 = 1 /* Timer1ж.*/ +#define Timer0_InterruptDisable() ET0 = 0 /* ֹTimer1ж.*/ + +#define T0_Load(n) TH0 = (n) / 256, TL0 = (n) % 256 +#define T0_Load_us_1T(n) Timer0_AsTimer(),Timer0_1T(), Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL0=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T0_Load_us_12T(n) Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL0=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T0_Frequency_1T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_1T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T0_Frequency_12T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer1_16bitAutoReload() TMOD &= ~0x30 /* 16λԶװ */ +#define Timer1_16bit() TMOD = (TMOD & ~0x30) | 0x10 /* 16λ */ +#define Timer1_8bitAutoReload() TMOD = (TMOD & ~0x30) | 0x20 /* 8λԶװ */ +#define Timer1_Run() TR1 = 1 /* ʱ1 */ +#define Timer1_Stop() TR1 = 0 /* ֹʱ1 */ +#define Timer1_Gate_INT1_P33() TMOD |= (1<<7) /* ʱ1ⲿINT1ߵƽʱ */ +#define Timer1_AsTimer() TMOD &= ~(1<<6) /* ʱ1ʱ */ +#define Timer1_AsCounter() TMOD |= (1<<6) /* ʱ1 */ +#define Timer1_AsCounterP35() TMOD |= (1<<6) /* ʱ1 */ +#define Timer1_1T() AUXR |= (1<<6) /* Timer1 clodk = fo */ +#define Timer1_12T() AUXR &= ~(1<<6) /* Timer1 clodk = fo/12 12Ƶ, default */ +#define Timer1_CLKO_Enable() INT_CLKO |= 2 /* T1 T1(P3.4)Fck1 = 1/2 T1 ʣT11T12T */ +#define Timer1_CLKO_Disable() INT_CLKO &= ~2 +#define Timer1_CLKO_Enable_P35() INT_CLKO |= 2 /* T1 T1(P3.4)Fck1 = 1/2 T1 ʣT11T12T */ +#define Timer1_CLKO_Disable_P35() INT_CLKO &= ~2 +#define Timer1_InterruptEnable() ET1 = 1 /* Timer1ж. */ +#define Timer1_InterruptDisable() ET1 = 0 /* ֹTimer1ж. */ + +#define T1_Load(n) TH1 = (n) / 256, TL1 = (n) % 256 +#define T1_Load_us_1T(n) Timer1_AsTimer(),Timer1_1T(), Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T1_Load_us_12T(n) Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T1_Frequency_1T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_1T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T1_Frequency_12T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer2_Run() AUXR |= (1<<4) /* ʱ2 */ +#define Timer2_Stop() AUXR &= ~(1<<4) /* ֹʱ2 */ +#define Timer2_AsTimer() AUXR &= ~(1<<3) /* ʱ2ʱ */ +#define Timer2_AsCounter() AUXR |= (1<<3) /* ʱ2 */ +#define Timer2_AsCounterP31() AUXR |= (1<<3) /* ʱ2 */ +#define Timer2_1T() AUXR |= (1<<2) /* Timer0 clock = fo */ +#define Timer2_12T() AUXR &= ~(1<<2) /* Timer0 clock = fo/12 12Ƶ, default */ +#define Timer2_CLKO_Enable() INT_CLKO |= 4 /* T2 P1.3Fck2 = 1/2 T2 ʣT21T12T */ +#define Timer2_CLKO_Disable() INT_CLKO &= ~4 +#define Timer2_CLKO_Enable_P13() INT_CLKO |= 4 /* T2 P1.3Fck2 = 1/2 T2 ʣT21T12T */ +#define Timer2_CLKO_Disable_P13() INT_CLKO &= ~4 +#define Timer2_InterruptEnable() IE2 |= (1<<2) /* Timer2ж. */ +#define Timer2_InterruptDisable() IE2 &= ~(1<<2) /* ֹTimer2ж. */ + +#define T2_Load(n) TH2 = (n) / 256, TL2 = (n) % 256 +#define T2_Load_us_1T(n) Timer2_AsTimer(),Timer2_1T(), TH2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T2_Load_us_12T(n) Timer2_AsTimer(),Timer2_12T(),TH2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T2_Frequency_1T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_1T(), TH2=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL2=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T2_Frequency_12T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_12T(),TH2=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL2=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer3_Run() T4T3M |= (1<<3) /* ʱ3 */ +#define Timer3_Stop() T4T3M &= ~(1<<3) /* ֹʱ3 */ +#define Timer3_AsTimer() T4T3M &= ~(1<<2) /* ʱ3ʱ */ +#define Timer3_AsCounter() T4T3M |= (1<<2) /* ʱ3, P0.5Ϊⲿ */ +#define Timer3_AsCounterP05() T4T3M |= (1<<2) /* ʱ3, P0.5Ϊⲿ */ +#define Timer3_1T() T4T3M |= (1<<1) /* 1Tģʽ */ +#define Timer3_12T() T4T3M &= ~(1<<1) /* 12Tģʽ, default */ +#define Timer3_CLKO_Enable() T4T3M |= 1 /* T3T3(P0.4)Fck = 1/2 T2 ʣT21T12T */ +#define Timer3_CLKO_Disable() T4T3M &= ~1 /* ֹT3T3(P0.4) */ +#define Timer3_CLKO_Enable_P04() T4T3M |= 1 /* T3T3(P0.4)Fck = 1/2 T2 ʣT21T12T */ +#define Timer3_CLKO_Disable_P04() T4T3M &= ~1 /* ֹT3T3(P0.4) */ +#define Timer3_InterruptEnable() IE2 |= (1<<5) /* Timer3ж. */ +#define Timer3_InterruptDisable() IE2 &= ~(1<<5) /* ֹTimer3ж. */ + +#define T3_Load(n) TH3 = (n) / 256, TL3 = (n) % 256 +#define T3_Load_us_1T(n) Timer3_AsTimer(),Timer3_1T(), TH3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T3_Load_us_12T(n) Timer3_AsTimer(),Timer3_12T(),TH3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T3_Frequency_1T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_1T(), TH3=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL3=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T3_Frequency_12T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_12T(),TH3=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL3=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer4_Run() T4T3M |= (1<<7) /* ʱ4 */ +#define Timer4_Stop() T4T3M &= ~(1<<7) /* ֹʱ4 */ +#define Timer4_AsTimer() T4T3M &= ~(1<<6) /* ʱ4ʱ */ +#define Timer4_AsCounter() T4T3M |= (1<<6) /* ʱ4, P0.7Ϊⲿ */ +#define Timer4_AsCounterP07() T4T3M |= (1<<6) /* ʱ4, P0.7Ϊⲿ */ +#define Timer4_1T() T4T3M |= (1<<5) /* 1Tģʽ */ +#define Timer4_12T() T4T3M &= ~(1<<5) /* 12Tģʽ, default */ +#define Timer4_CLKO_Enable() T4T3M |= (1<<4) /* T4T4(P0.6)Fck = 1/2 T2 ʣT21T12T */ +#define Timer4_CLKO_Disable() T4T3M &= ~(1<<4) /* ֹT4T4(P0.6) */ +#define Timer4_CLKO_Enable_P06() T4T3M |= (1<<4) /* T4T4(P0.6)Fck = 1/2 T2 ʣT21T12T */ +#define Timer4_CLKO_Disable_P06() T4T3M &= ~(1<<4) /* ֹT4T4(P0.6) */ +#define Timer4_InterruptEnable() IE2 |= (1<<6) /* Timer4ж. */ +#define Timer4_InterruptDisable() IE2 &= ~(1<<6) /* ֹTimer4ж. */ + +#define T4_Load(n) TH4 = (n) / 256, TL4 = (n) % 256 +#define T4_Load_us_1T(n) Timer4_AsTimer(),Timer4_1T(), TH4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T4_Load_us_12T(n) Timer4_AsTimer(),Timer4_12T(),TH4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T4_Frequency_1T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_1T(), TH4=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL4=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T4_Frequency_12T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_12T(),TH4=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL4=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +//==================================================================================================================== + +//sfr WDT_CONTR = 0xC1; //Watch-Dog-Timer Control register +// 7 6 5 4 3 2 1 0 Reset Value +// WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0 xx00,0000 +#define D_WDT_FLAG (1<<7) +#define D_EN_WDT (1<<5) +#define D_CLR_WDT (1<<4) /* auto clear */ +#define D_IDLE_WDT (1<<3) /* WDT counter when Idle */ +#define D_WDT_SCALE_2 0 +#define D_WDT_SCALE_4 1 +#define D_WDT_SCALE_8 2 /* T=393216*N/fo */ +#define D_WDT_SCALE_16 3 +#define D_WDT_SCALE_32 4 +#define D_WDT_SCALE_64 5 +#define D_WDT_SCALE_128 6 +#define D_WDT_SCALE_256 7 + +#define WDT_PS_Set(n) WDT_CONTR = (WDT_CONTR & ~0x07) | (n & 0x07) /* ŹʱʱӷƵϵ */ +#define WDT_reset(n) WDT_CONTR = D_EN_WDT + D_CLR_WDT + D_IDLE_WDT + (n) /* ʼWDTι */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PCON = 0x87; SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0001,0000 //Power Control +//SMOD //˫ +//SMOD0 +#define LVDF (1<<5) /* P4.6ѹ־ */ +#define POF (1<<4) /* ѹ־λ */ +//POF +//GF1 +//GF0 +//#define D_PD 2 /* set 1, power down mode */ +//#define D_IDLE 1 /* set 1, idle mode */ +#define MCU_IDLE() PCON |= 1 /* MCU IDLE ģʽ */ +#define MCU_POWER_DOWN() PCON |= 2 /* MCU ˯ ģʽ */ + + +//sfr IAP_CMD = 0xC5; +#define IAP_STANDBY() IAP_CMD = 0 //IAPֹ +#define IAP_READ() IAP_CMD = 1 //IAP +#define IAP_WRITE() IAP_CMD = 2 //IAPд +#define IAP_ERASE() IAP_CMD = 3 //IAP + +//sfr IAP_TRIG = 0xC6; +#define IAP_TRIG() IAP_TRIG = 0x5A, IAP_TRIG = 0xA5 /* IAP */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IAP_CONTR = 0xC7; IAPEN SWBS SWRST CFAIL - - - - 0000,x000 //IAP Control Register + +#define IAP_EN (1<<7) +#define IAP_SWBS (1<<6) +#define IAP_SWRST (1<<5) +#define IAP_CMD_FAIL (1<<4) + +#define IAP_ENABLE() IAP_CONTR = IAP_EN; IAP_TPS = MAIN_Fosc / 1000000 +#define IAP_DISABLE() IAP_CONTR = 0; IAP_CMD = 0; IAP_TRIG = 0; IAP_ADDRH = 0xff; IAP_ADDRL = 0xff + + +/* ADC Register */ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr ADC_CONTR = 0xBC; ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000 /* AD תƼĴ */ +//sfr ADC_RES = 0xBD; ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 0000,0000 /* A/D ת8λ */ +//sfr ADC_RESL = 0xBE; ADCV.1 ADCV.0 0000,0000 /* A/D ת2λ */ +//sfr ADC_CONTR = 0xBC; //ֱMOVҪ + + +//sfr SPCTL = 0xCE; SPIƼĴ +// 7 6 5 4 3 2 1 0 Reset Value +// SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0x00 + +#define SPI_SSIG_None() SPCTL |= (1<<7) /* 1: SS */ +#define SPI_SSIG_Enable() SPCTL &= ~(1<<7) /* 0: SSھӻ */ +#define SPI_Enable() SPCTL |= (1<<6) /* 1: SPI */ +#define SPI_Disable() SPCTL &= ~(1<<6) /* 0: ֹSPI */ +#define SPI_LSB_First() SPCTL |= (1<<5) /* 1: LSBȷ */ +#define SPI_MSB_First() SPCTL &= ~(1<<5) /* 0: MSBȷ */ +#define SPI_Master() SPCTL |= (1<<4) /* 1: Ϊ */ +#define SPI_Slave() SPCTL &= ~(1<<4) /* 0: Ϊӻ */ +#define SPI_SCLK_NormalH() SPCTL |= (1<<3) /* 1: ʱSCLKΪߵƽ */ +#define SPI_SCLK_NormalL() SPCTL &= ~(1<<3) /* 0: ʱSCLKΪ͵ƽ */ +#define SPI_PhaseH() SPCTL |= (1<<2) /* 1: */ +#define SPI_PhaseL() SPCTL &= ~(1<<2) /* 0: */ +#define SPI_Speed(n) SPCTL = (SPCTL & ~3) | (n) /*ٶ, 0 -- fosc/4, 1 -- fosc/8, 2 -- fosc/16, 3 -- fosc/32 */ + +//sfr SPDAT = 0xCF; //SPI Data Register 0000,0000 +//sfr SPSTAT = 0xCD; //SPI״̬Ĵ +// 7 6 5 4 3 2 1 0 Reset Value +// SPIF WCOL - - - - - - +#define SPIF 0x80 /* SPIɱ־д10*/ +#define WCOL 0x40 /* SPIдͻ־д10 */ + +#define SPI_USE_P12P13P14P15() P_SW1 &= ~0x0c /* SPIлP12(SS) P13(MOSI) P14(MISO) P15(SCLK)(ϵĬ)*/ +#define SPI_USE_P22P23P24P25() P_SW1 = (P_SW1 & ~0x0c) | 0x04 /* SPIлP22(SS) P23(MOSI) P24(MISO) P25(SCLK)*/ +#define SPI_USE_P74P75P76P77() P_SW1 = (P_SW1 & ~0x0c) | 0x08 /* SPIлP74(SS) P75(MOSI) P76(MISO) P77(SCLK)*/ +#define SPI_USE_P35P34P33P32() P_SW1 = P_SW1 | 0x0C /* SPIлP35(SS) P34(MOSI) P33(MISO) P32(SCLK)*/ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CCFG = 0xFE80H; ENI2C MSSL MSSPEED[5:0] 0000,0000 /* I2CüĴ */ +#define I2C_Function(n) (n==0?(I2CCFG &= ~0x80):(I2CCFG |= 0x80)) //0ֹ I2C ܣ1ʹ I2C +#define I2C_ENABLE() I2CCFG |= 0x80 /* ʹ I2C */ +#define I2C_DISABLE() I2CCFG &= ~0x80 /* ֹ I2C */ +#define I2C_Master() I2CCFG |= 0x40 /* 1: Ϊ */ +#define I2C_Slave() I2CCFG &= ~0x40 /* 0: Ϊӻ */ +#define I2C_SetSpeed(n) I2CCFG = (I2CCFG & ~0x3f) | (n & 0x3f) /* ٶ=Fosc/2/(Speed*2+4) */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSCR = 0xFE81H; EMSI - - - MSCMD[3:0] 0000,0000 /* I2CüĴ */ +#define I2C_Master_Inturrupt(n) (n==0?(I2CMSCR &= ~0x80):(I2CMSCR |= 0x80)) //0ֹ I2C ܣ1ʹ I2C + +#define I2C_CMD_None 0 +#define I2C_CMD_Start 1 +#define I2C_CMD_Send 2 +#define I2C_CMD_RACK 3 +#define I2C_CMD_Read 4 +#define I2C_CMD_SACK 5 +#define I2C_CMD_Stop 6 +#define I2C_CMD_RFU1 7 +#define I2C_CMD_RFU2 8 +#define I2C_CMD_Start_Send_RACK 9 +#define I2C_CMD_Send_RACK 10 +#define I2C_CMD_Read_SACK 11 +#define I2C_CMD_Read_SNAK 12 + +#define I2C_Command(n) I2CMSCR = (I2CMSCR & ~0x0f) | (n & 0x0f) /* */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSST = 0xFE82H; MSBUSY MSIF - - - - MSACKI MSACKO 0000,0000 /* I2C״̬Ĵ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSAUX = 0xFE88H; - - - - - - - WDTA 0000,0000 /* I2CƼĴ */ +#define I2C_WDTA_EN() I2CMSAUX |= 0x01 /* ʹԶ */ +#define I2C_WDTA_DIS() I2CMSAUX &= ~0x01 /* ֹԶ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLCR = 0xFE83H; - ESTAI ERXI ETXI ESTOI - - SLRET 0000,0000 /* I2CӻƼĴ */ +#define I2C_ESTAI_EN() I2CSLCR |= 0x40 /* ʹܴӻSTARTźж */ +#define I2C_ESTAI_DIS() I2CSLCR &= ~0x40 /* ֹӻSTARTźж */ +#define I2C_ERXI_EN() I2CSLCR |= 0x20 /* ʹܴӻ1ֽж */ +#define I2C_ERXI_DIS() I2CSLCR &= ~0x20 /* ֹӻ1ֽж */ +#define I2C_ETXI_EN() I2CSLCR |= 0x10 /* ʹܴӻ1ֽж */ +#define I2C_ETXI_DIS() I2CSLCR &= ~0x10 /* ֹӻ1ֽж */ +#define I2C_ESTOI_EN() I2CSLCR |= 0x08 /* ʹܴӻSTOPźж */ +#define I2C_ESTOI_DIS() I2CSLCR &= ~0x08 /* ֹӻSTOPźж */ +#define I2C_SLRET() I2CSLCR |= 0x01 /* λӻģʽ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLST = 0xFE84H; SLBUSY STAIF RXIF TXIF STOIF - SLACKI SLACKO 0000,0000 /* I2Cӻ״̬Ĵ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLADR = 0xFE85H; I2CSLADR[7:1] MA 0000,0000 /* I2CӻַĴ */ +#define I2C_Address(n) I2CSLADR = (I2CSLADR & 0x01) | (n << 1) /* ӻַ */ +#define I2C_MATCH_EN() I2CSLADR &= ~0x01 /* ʹܴӻַȽϹܣֻƥַ */ +#define I2C_MATCH_DIS() I2CSLADR |= 0x01 /* ֹӻַȽϹܣ豸ַ */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ENO = 0xFEB1H; ENO4N ENO4P ENO3N ENO3P ENO2N ENO2P ENO1N ENO1P 0000,0000 /* ʹܼĴ */ +//sfr PWMB_ENO = 0xFEB5H; - ENO8P - ENO7P - ENO6P - ENO5P 0000,0000 /* ʹܼĴ */ +#define PWM1P_OUT_EN() PWMA_ENO |= 0x01 /* ʹ PWM1P */ +#define PWM1P_OUT_DIS() PWMA_ENO &= ~0x01 /* ֹ PWM1P */ +#define PWM1N_OUT_EN() PWMA_ENO |= 0x02 /* ʹ PWM1N */ +#define PWM1N_OUT_DIS() PWMA_ENO &= ~0x02 /* ֹ PWM1N */ +#define PWM2P_OUT_EN() PWMA_ENO |= 0x04 /* ʹ PWM2P */ +#define PWM2P_OUT_DIS() PWMA_ENO &= ~0x04 /* ֹ PWM2P */ +#define PWM2N_OUT_EN() PWMA_ENO |= 0x08 /* ʹ PWM2N */ +#define PWM2N_OUT_DIS() PWMA_ENO &= ~0x08 /* ֹ PWM2N */ +#define PWM3P_OUT_EN() PWMA_ENO |= 0x10 /* ʹ PWM3P */ +#define PWM3P_OUT_DIS() PWMA_ENO &= ~0x10 /* ֹ PWM3P */ +#define PWM3N_OUT_EN() PWMA_ENO |= 0x20 /* ʹ PWM3N */ +#define PWM3N_OUT_DIS() PWMA_ENO &= ~0x20 /* ֹ PWM3N */ +#define PWM4P_OUT_EN() PWMA_ENO |= 0x40 /* ʹ PWM3P */ +#define PWM4P_OUT_DIS() PWMA_ENO &= ~0x40 /* ֹ PWM3P */ +#define PWM4N_OUT_EN() PWMA_ENO |= 0x80 /* ʹ PWM3N */ +#define PWM4N_OUT_DIS() PWMA_ENO &= ~0x80 /* ֹ PWM3N */ + +#define PWM5P_OUT_EN() PWMB_ENO |= 0x01 /* ʹ PWM5P */ +#define PWM5P_OUT_DIS() PWMB_ENO &= ~0x01 /* ֹ PWM5P */ +#define PWM6P_OUT_EN() PWMB_ENO |= 0x04 /* ʹ PWM6P */ +#define PWM6P_OUT_DIS() PWMB_ENO &= ~0x04 /* ֹ PWM6P */ +#define PWM7P_OUT_EN() PWMB_ENO |= 0x10 /* ʹ PWM7P */ +#define PWM7P_OUT_DIS() PWMB_ENO &= ~0x10 /* ֹ PWM7P */ +#define PWM8P_OUT_EN() PWMB_ENO |= 0x40 /* ʹ PWM8P */ +#define PWM8P_OUT_DIS() PWMB_ENO &= ~0x40 /* ֹ PWM8P */ + +#define PWMA_OutChannelSel(n) PWMA_ENO = n //ѡͨ +#define PWMB_OutChannelSel(n) PWMB_ENO = n //ѡͨ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_PS = 0xFEB2H; C4PS1 C4PS0 C3PS1 C3PS0 C2PS1 C2PS0 C1PS1 C1PS0 0000,0000 /* ʹܼĴ */ +//sfr PWMB_PS = 0xFEB6H; C8PS1 C8PS0 C7PS1 C7PS0 C6PS1 C6PS0 C5PS1 C5PS0 0000,0000 /* ʹܼĴ */ + +#define PWM1_USE_P10P11() PWMA_PS = (PWMA_PS & ~0x03) /* PWM ͨ 1 лP10(PWM1P) P11(PWM1N) */ +#define PWM1_USE_P20P21() PWMA_PS = (PWMA_PS & ~0x03) | 0x01 /* PWM ͨ 1 лP20(PWM1P) P21(PWM1N) */ +#define PWM1_USE_P60P61() PWMA_PS = (PWMA_PS & ~0x03) | 0x02 /* PWM ͨ 1 лP60(PWM1P) P61(PWM1N) */ + +#define PWM2_USE_P12P13() PWMA_PS = (PWMA_PS & ~0x0C) /* PWM ͨ 2 лP12/P54(PWM2P) P13(PWM2N) */ +#define PWM2_USE_P22P23() PWMA_PS = (PWMA_PS & ~0x0C) | 0x04 /* PWM ͨ 2 лP22(PWM2P) P23(PWM2N) */ +#define PWM2_USE_P62P63() PWMA_PS = (PWMA_PS & ~0x0C) | 0x08 /* PWM ͨ 2 лP62(PWM2P) P63(PWM2N) */ + +#define PWM3_USE_P14P15() PWMA_PS = (PWMA_PS & ~0x30) /* PWM ͨ 3 лP14(PWM3P) P15(PWM3N) */ +#define PWM3_USE_P24P25() PWMA_PS = (PWMA_PS & ~0x30) | 0x10 /* PWM ͨ 3 лP24(PWM3P) P25(PWM3N) */ +#define PWM3_USE_P64P65() PWMA_PS = (PWMA_PS & ~0x30) | 0x20 /* PWM ͨ 3 лP64(PWM3P) P65(PWM3N) */ + +#define PWM4_USE_P16P17() PWMA_PS = (PWMA_PS & ~0xC0) /* PWM ͨ 4 лP16(PWM4P) P17(PWM4N) */ +#define PWM4_USE_P26P27() PWMA_PS = (PWMA_PS & ~0xC0) | 0x40 /* PWM ͨ 4 лP26(PWM4P) P27(PWM4N) */ +#define PWM4_USE_P66P67() PWMA_PS = (PWMA_PS & ~0xC0) | 0x80 /* PWM ͨ 4 лP66(PWM4P) P67(PWM4N) */ +#define PWM4_USE_P34P33() PWMA_PS = (PWMA_PS | 0xC0) /* PWM ͨ 4 лP34(PWM4P) P33(PWM4N) */ + +#define PWM5_USE_P20() PWMB_PS = (PWMB_PS & ~0x03) /* PWM ͨ 5 лP20(PWM5) */ +#define PWM5_USE_P17() PWMB_PS = (PWMB_PS & ~0x03) | 0x01 /* PWM ͨ 5 лP17(PWM5) */ +#define PWM5_USE_P00() PWMB_PS = (PWMB_PS & ~0x03) | 0x02 /* PWM ͨ 5 лP00(PWM5) */ +#define PWM5_USE_P74() PWMB_PS = (PWMB_PS | 0x03) /* PWM ͨ 5 лP74(PWM5) */ + +#define PWM6_USE_P21() PWMB_PS = (PWMB_PS & ~0x0C) /* PWM ͨ 6 лP21(PWM6) */ +#define PWM6_USE_P54() PWMB_PS = (PWMB_PS & ~0x0C) | 0x04 /* PWM ͨ 6 лP54(PWM6) */ +#define PWM6_USE_P01() PWMB_PS = (PWMB_PS & ~0x0C) | 0x08 /* PWM ͨ 6 лP01(PWM6) */ +#define PWM6_USE_P75() PWMB_PS = (PWMB_PS | 0x0C) /* PWM ͨ 6 лP75(PWM6) */ + +#define PWM7_USE_P22() PWMB_PS = (PWMB_PS & ~0x30) /* PWM ͨ 7 лP22(PWM7) */ +#define PWM7_USE_P33() PWMB_PS = (PWMB_PS & ~0x30) | 0x10 /* PWM ͨ 7 лP33(PWM7) */ +#define PWM7_USE_P02() PWMB_PS = (PWMB_PS & ~0x30) | 0x20 /* PWM ͨ 7 лP02(PWM7) */ +#define PWM7_USE_P76() PWMB_PS = (PWMB_PS | 0x30) /* PWM ͨ 7 лP76(PWM7) */ + +#define PWM8_USE_P23() PWMB_PS = (PWMB_PS & ~0xC0) /* PWM ͨ 8 лP23(PWM8) */ +#define PWM8_USE_P34() PWMB_PS = (PWMB_PS & ~0xC0) | 0x40 /* PWM ͨ 8 лP34(PWM8) */ +#define PWM8_USE_P03() PWMB_PS = (PWMB_PS & ~0xC0) | 0x80 /* PWM ͨ 8 лP03(PWM8) */ +#define PWM8_USE_P77() PWMB_PS = (PWMB_PS | 0xC0) /* PWM ͨ 8 лP77(PWM8) */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_IOAUX = 0xFEB3H; AUX4N AUX4P AUX3N AUX3P AUX2N AUX2P AUX1N AUX1P 0000,0000 /* ʹܼĴ */ +//sfr PWMB_IOAUX = 0xFEB7H; - AUX8P - AUX7P - AUX6P - AUX5P 0000,0000 /* ʹܼĴ */ +#define AUX4N (1<<7) +#define AUX4P (1<<6) +#define AUX3N (1<<5) +#define AUX3P (1<<4) +#define AUX2N (1<<3) +#define AUX2P (1<<2) +#define AUX1N (1<<1) +#define AUX1P (1) + +#define AUX8P (1<<6) +#define AUX7P (1<<4) +#define AUX6P (1<<2) +#define AUX5P (1) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CR1 = 0xFEC0H; ARPEA CMSA1 CMSA0 DIRA OPMA URSA UDISA CENA 0000,0000 /* ƼĴ 1 */ +//sfr PWMB_CR1 = 0xFEE0H; ARPEB CMSB1 CMSB0 DIRB OPMB URSB UDISB CENB 0000,0000 /* ƼĴ 1 */ +#define ARPE1 (1<<7) +#define ARPE2 (1<<7) +#define PWMA_AlignMode_Edge() PWMA_CR1 = (PWMA_CR1 & ~0x60) +#define PWMA_AlignMode_Mid1() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x20 +#define PWMA_AlignMode_Mid2() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x40 +#define PWMA_AlignMode_Mid3() PWMA_CR1 = (PWMA_CR1 | 0x60) +#define PWMA_DIR_UP() PWMA_CR1 &= ~0x10 +#define PWMA_DIR_DN() PWMA_CR1 |= 0x10 +#define PWMA_OPMA(n) (n==0?(PWMA_CR1 &= ~0x08):(PWMA_CR1 |= 0x08)) //ģʽ 0ڷ¼ʱֹͣ1ڷһθ¼ʱ CEN λֹͣ +#define PWMA_URSA(n) (n==0?(PWMA_CR1 &= ~0x04):(PWMA_CR1 |= 0x04)) //Դ +#define PWMA_UDISA(n) (n==0?(PWMA_CR1 &= ~0x02):(PWMA_CR1 |= 0x02)) //ֹ 0£UEV¼1¼ +#define PWMA_CEN_Enable() PWMA_CR1 |= 0x01 //1ʹܼ +#define PWMA_CEN_Disable() PWMA_CR1 &= ~0x01 //0ֹ + +#define PWMB_AlignMode_Edge() PWMB_CR1 = (PWMB_CR1 & ~0x60) +#define PWMB_AlignMode_Mid1() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x20 +#define PWMB_AlignMode_Mid2() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x40 +#define PWMB_AlignMode_Mid3() PWMB_CR1 = (PWMB_CR1 | 0x60) +#define PWMB_DIR_UP() PWMB_CR1 &= ~0x10 +#define PWMB_DIR_DN() PWMB_CR1 |= 0x10 +#define PWMB_OPMB(n) (n==0?(PWMB_CR1 &= ~0x08):(PWMB_CR1 |= 0x08)) //ģʽ 0ڷ¼ʱֹͣ1ڷһθ¼ʱ CEN λֹͣ +#define PWMB_URSB(n) (n==0?(PWMB_CR1 &= ~0x04):(PWMB_CR1 |= 0x04)) //Դ +#define PWMB_UDISB(n) (n==0?(PWMB_CR1 &= ~0x02):(PWMB_CR1 |= 0x02)) //ֹ 0£UEV¼1¼ +#define PWMB_CEN_Enable() PWMB_CR1 |= 0x01 //1ʹܼ +#define PWMB_CEN_Disable() PWMB_CR1 &= ~0x01 //0ֹ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CR2 = 0xFEC1H; TI1S MMSA2 MMSA1 MMSA0 - COMSA - CCPCA 0000,x0x0 /* ƼĴ 2 */ +//sfr PWMB_CR2 = 0xFEE1H; TI5S MMSB2 MMSB1 MMSB0 - COMSB - CCPCB 0000,x0xx /* ƼĴ 2 */ +#define PWM1P_TI1() PWMA_CR2 &= ~0x80 +#define PWM1P2P3P_XOR_TI1() PWMA_CR2 |= 0x80 +#define PWM5P_TI2() PWMB_CR2 &= ~0x80 +#define PWM5P6P7P_XOR_TI2() PWMB_CR2 |= 0x80 + +#define MMSn_RESET 0 //λ +#define MMSn_ENABLE 1 //ʹ +#define MMSn_UPDATE 2 // +#define MMSn_COMP_TRGO 3 //Ƚ +#define MMSn_OC1REF_TRGO 4 //Ƚ +#define MMSn_OC2REF_TRGO 5 //Ƚ +#define MMSn_OC3REF_TRGO 6 //Ƚ +#define MMSn_OC4REF_TRGO 7 //Ƚ + +#define PWMA_MainModeSel(n) PWMA_CR2 = (PWMA_CR2 & ~0x70) | (n<<4) //ģʽѡ +#define PWMB_MainModeSel(n) PWMB_CR2 = (PWMB_CR2 & ~0x70) | (n<<4) //ģʽѡ + +//0 CCPC=1 ʱֻ COMG λ 1 ʱЩλű +//1 CCPC=1 ʱֻ COMG λ 1 TRGI صʱЩλű +#define PWMA_COMSUpdateCtrl(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x04):(PWMA_CR2 |= 0x04)) ///ȽϿλĸ¿ѡ +#define PWMB_COMSUpdateCtrl(n) PWMB_CR2 = (n==0?(PWMB_CR2 &= ~0x04):(PWMB_CR2 |= 0x04)) ///ȽϿλĸ¿ѡ +//0 CCIE CCINE CCiP CCiNP OCIM λԤװص +//1 CCIE CCINE CCiP CCiNP OCIM λԤװصģøλֻ COMGλ󱻸¡ +#define PWMA_CCPCAPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) ///ȽԤװؿλ(λֻԾлͨ) +#define PWMB_CCPCBPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) ///ȽԤװؿλ(λֻԾлͨ) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SMCR = 0xFEC2H; MSMA TSA2 TSA1 TSA0 - SMSA2 SMSA1 SMSA0 0000,x000 /* ģʽƼĴ */ +//sfr PWMB_SMCR = 0xFEE2H; MSMB TSB2 TSB1 TSB0 - SMSB2 SMSB1 SMSB0 0000,x000 /* ģʽƼĴ */ +#define SMCR_TSn_ITR2 2 +#define SMCR_TSn_EDGE 4 +#define SMCR_TSn_TIMER1 5 +#define SMCR_TSn_TIMER2 6 +#define SMCR_TSn_ETRF 7 + +#define PWMA_SMCR_Source(n) PWMA_SMCR = (PWMA_SMCR & ~0x70) | (n<<4) //Դѡ +#define PWMB_SMCR_Source(n) PWMB_SMCR = (PWMB_SMCR & ~0x70) | (n<<4) //Դѡ + +#define SMCR_SMSA_INSIDE_CLK 0 +#define SMCR_SMSA_ENCODER_M1 1 +#define SMCR_SMSA_ENCODER_M2 2 +#define SMCR_SMSA_ENCODER_M3 3 +#define SMCR_SMSA_RESET 4 +#define SMCR_SMSA_GATE 5 +#define SMCR_SMSA_TRIG 6 +#define SMCR_SMSA_EXT_CLK 7 + +#define PWMA_SMCR_SMS(n) PWMA_SMCR = (PWMA_SMCR & ~0x07) | (n & 7) //ʱ//ģʽѡ +#define PWMB_SMCR_SMS(n) PWMB_SMCR = (PWMB_SMCR & ~0x07) | (n & 7) //ʱ//ģʽѡ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ETR = 0xFEC3H; ETP1 ECE1 ETPS11 ETPS10 ETF13 ETF12 ETF11 ETF10 0000,0000 /* ⲿĴ */ +//sfr PWMB_ETR = 0xFEE3H; ETP2 ECE2 ETPS21 ETPS20 ETF23 ETF22 ETF21 ETF20 0000,0000 /* ⲿĴ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_IER = 0xFEC4H; BIEA TIEA COMIEA CC4IE CC3IE CC2IE CC1IE UIEA 0000,0000 /* жʹܼĴ */ +//sfr PWMB_IER = 0xFEE4H; BIEB TIEB COMIEB CC8IE CC7IE CC6IE CC5IE UIEB 0000,0000 /* жʹܼĴ */ +#define PWMA_UIEA_Enable() PWMA_IER |= 0x01 //1ж +#define PWMA_UIEA_Disable() PWMA_IER &= ~0x01 //0ֹж +#define PWMA_CC1IE_Enable() PWMA_IER |= 0x02 //1/Ƚж +#define PWMA_CC1IE_Disable() PWMA_IER &= ~0x02 //0ֹ/Ƚж +#define PWMA_CC2IE_Enable() PWMA_IER |= 0x04 //1/Ƚж +#define PWMA_CC2IE_Disable() PWMA_IER &= ~0x04 //0ֹ/Ƚж +#define PWMA_CC3IE_Enable() PWMA_IER |= 0x08 //1/Ƚж +#define PWMA_CC3IE_Disable() PWMA_IER &= ~0x08 //0ֹ/Ƚж +#define PWMA_CC4IE_Enable() PWMA_IER |= 0x10 //1/Ƚж +#define PWMA_CC4IE_Disable() PWMA_IER &= ~0x10 //0ֹ/Ƚж +#define PWMA_COMIEA_Enable() PWMA_IER |= 0x20 //1COMж +#define PWMA_COMIEA_Disable() PWMA_IER &= ~0x20 //0ֹCOMж +#define PWMA_TIEA_Enable() PWMA_IER |= 0x40 //1ж +#define PWMA_TIEA_Disable() PWMA_IER &= ~0x40 //0ֹж +#define PWMA_BIEA_Enable() PWMA_IER |= 0x80 //1ɲж +#define PWMA_BIEA_Disable() PWMA_IER &= ~0x80 //0ֹɲж + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SR1 = 0xFEC5H; BIF1 TIF1 COMIF1 CC4IF CC3IF CC2IF CC1IF UIF1 0000,0000 /* ״̬Ĵ 1 */ +//sfr PWMB_SR1 = 0xFEE5H; BIF2 TIF2 COMIF2 CC8IF CC7IF CC6IF CC5IF UIF2 0000,0000 /* ״̬Ĵ 1 */ +#define UIF1 1 +#define CC1IF (1<<1) +#define CC2IF (1<<2) +#define CC3IF (1<<3) +#define CC4IF (1<<4) +#define COMIF1 (1<<5) +#define TIF1 (1<<6) +#define BIF1 (1<<7) + +#define UIF2 1 +#define CC5IF (1<<1) +#define CC6IF (1<<2) +#define CC7IF (1<<3) +#define CC8IF (1<<4) +#define COMIF2 (1<<5) +#define TIF2 (1<<6) +#define BIF2 (1<<7) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SR2 = 0xFEC6H; - - - CC4OF CC3OF CC2OF CC1OF - xxx0,000x /* ״̬Ĵ 2 */ +//sfr PWMB_SR2 = 0xFEE6H; - - - CC8OF CC7OF CC6OF CC5OF - xxx0,000x /* ״̬Ĵ 2 */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_EGR = 0xFEC7H; BG1 TG1 COMG1 CC4G CC3G CC2G CC1G UG1 0000,0000 /* ¼Ĵ */ +//sfr PWMB_EGR = 0xFEE7H; BG2 TG2 COMG2 CC8G CC7G CC6G CC5G UG2 0000,0000 /* ¼Ĵ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR1 = 0xFEC8H; OC1CE OC1M2 OC1M1 OC1M0 OC1PE OC1FE CC1S1 CC1S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪȽģʽ */ +//sfr PWMB_CCMR1 = 0xFEE8H; OC5CE OC5M2 OC5M1 OC5M0 OC5PE OC5FE CC5S1 CC5S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪȽģʽ */ +#define OCnCE (1<<7) + +#define CCMRn_FREEZE 0x00 // +#define CCMRn_MATCH_VALID 0x10 //ƥʱͨ n ΪЧƽ +#define CCMRn_MATCH_INVALID 0x20 //ƥʱͨ n ΪЧƽ +#define CCMRn_ROLLOVER 0x30 //ת +#define CCMRn_FORCE_INVALID 0x40 //ǿΪЧƽ +#define CCMRn_FORCE_VALID 0x50 //ǿΪЧƽ +#define CCMRn_PWM_MODE1 0x60 //PWM ģʽ 1 +#define CCMRn_PWM_MODE2 0x70 //PWM ģʽ 2 + +#define PWMA_OC1ModeSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x70) | (n) //Ƚģʽ +#define PWMB_OC5ModeSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x70) | (n) //Ƚģʽ + +#define PWMA_OC1_ReloadEnable() PWMA_CCMR1 |= 0x08 //1 OC1PE ȽϵԤװع +#define PWMA_OC1_RelosdDisable() PWMA_CCMR1 &= ~0x08 //0ֹ OC1PE ȽϵԤװع +#define PWMB_OC5_ReloadEnable() PWMB_CCMR1 |= 0x08 //1 OC5PE ȽϵԤװع +#define PWMB_OC5_RelosdDisable() PWMB_CCMR1 &= ~0x08 //0ֹ OC5PE ȽϵԤװع + +#define PWMA_OC1_FastEnable() PWMA_CCMR1 |= 0x04 //1 OC1FE ȽϿٹ +#define PWMA_OC1_FastDisable() PWMA_CCMR1 &= ~0x04 //0ֹ OC1FE ȽϿٹ +#define PWMB_OC5_FastEnable() PWMB_CCMR1 |= 0x04 //1 OC5FE ȽϿٹ +#define PWMB_OC5_FastDisable() PWMB_CCMR1 &= ~0x04 //0ֹ OC5FE ȽϿٹ + +#define CCAS_OUTPUT 0x00 // +#define CCAS_IUTPUT_TI1FP1 0x01 //룬IC1/IC2/IC3/IC4 ӳ TI1FP1 +#define CCAS_IUTPUT_TI2FP1 0x02 //룬IC1/IC2/IC3/IC4 ӳ TI2FP1 +#define CCAS_IUTPUT_TRC 0x03 //룬IC1/IC2/IC3/IC4 ӳ TRC +#define CCBS_OUTPUT 0x00 // +#define CCBS_IUTPUT_TI5FP5 0x01 //룬IC5/IC6/IC7/IC8 ӳ TI5FP5 +#define CCBS_IUTPUT_TI6FP5 0x02 //룬IC5/IC6/IC7/IC8 ӳ TI6FP5 +#define CCBS_IUTPUT_TRC 0x03 //룬IC5/IC6/IC7/IC8 ӳ TRC + +#define PWMA_CC1S_Direction(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x03) | (n) ///Ƚ 1 ѡλͨķ/ŵѡ +#define PWMB_CC5S_Direction(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x03) | (n) ///Ƚ 5 ѡλͨķ/ŵѡ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR1 = 0xFEC8H; IC1F3 IC1F2 IC1F1 IC1F0 IC1PSC1 IC1PSC0 CC1S1 CC1S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪģʽ */ +//sfr PWMB_CCMR1 = 0xFEE8H; IC5F3 IC5F2 IC5F1 IC5F0 IC5PSC1 IC5PSC0 CC5S1 CC5S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪģʽ */ + +#define ICnF_01_Clock 0 +#define ICnF_02_Clock 1 +#define ICnF_04_Clock 2 +#define ICnF_08_Clock 3 +#define ICnF_12_Clock 4 +#define ICnF_16_Clock 5 +#define ICnF_24_Clock 6 +#define ICnF_32_Clock 7 +#define ICnF_48_Clock 8 +#define ICnF_64_Clock 9 +#define ICnF_80_Clock 10 +#define ICnF_96_Clock 11 +#define ICnF_128_Clock 12 +#define ICnF_160_Clock 13 +#define ICnF_192_Clock 14 +#define ICnF_256_Clock 15 + +#define PWMA_IC1F_FilterClock(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0x0F) | (n<<4) //벶 1 ˲ѡ񣬸λ TIn IJƵʼ˲ +#define PWMB_IC5F_FilterClock(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0x0F) | (n<<4) //벶 5 ˲ѡ񣬸λ TIn IJƵʼ˲ + +#define PWMA_IC1PSC_PrescalerSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0xF3) | ((n&3)<<2) /// 1 ԤƵ0~3 +#define PWMB_IC5PSC_PrescalerSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0xF3) | ((n&3)<<2) /// 5 ԤƵ0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR2 = 0xFEC9H; OC2CE OC2M2 OC2M1 OC2M0 OC2PE OC2FE CC2S1 CC2S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪȽģʽ */ +//sfr PWMB_CCMR2 = 0xFEE9H; OC6CE OC6M2 OC6M1 OC6M0 OC6PE OC6FE CC6S1 CC6S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪȽģʽ */ + +#define PWMA_OC2ModeSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x70) | (n) //Ƚģʽ +#define PWMB_OC6ModeSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x70) | (n) //Ƚģʽ + +#define PWMA_OC2_ReloadEnable() PWMA_CCMR2 |= 0x08 //1 OC2PE ȽϵԤװع +#define PWMA_OC2_RelosdDisable() PWMA_CCMR2 &= ~0x08 //0ֹ OC2PE ȽϵԤװع +#define PWMB_OC6_ReloadEnable() PWMB_CCMR2 |= 0x08 //1 OC6PE ȽϵԤװع +#define PWMB_OC6_RelosdDisable() PWMB_CCMR2 &= ~0x08 //0ֹ OC6PE ȽϵԤװع + +#define PWMA_OC2_FastEnable() PWMA_CCMR2 |= 0x04 //1 OC2FE ȽϿٹ +#define PWMA_OC2_FastDisable() PWMA_CCMR2 &= ~0x04 //0ֹ OC2FE ȽϿٹ +#define PWMB_OC6_FastEnable() PWMB_CCMR2 |= 0x04 //1 OC6FE ȽϿٹ +#define PWMB_OC6_FastDisable() PWMB_CCMR2 &= ~0x04 //0ֹ OC6FE ȽϿٹ + +#define PWMA_CC2S_Direction(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x03) | (n) ///Ƚ 2 ѡλͨķ/ŵѡ +#define PWMB_CC6S_Direction(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x03) | (n) ///Ƚ 6 ѡλͨķ/ŵѡ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR2 = 0xFEC9H; IC2F3 IC2F2 IC2F1 IC2F0 IC2PSC1 IC2PSC0 CC2S1 CC2S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪģʽ */ +//sfr PWMB_CCMR2 = 0xFEE9H; IC6F3 IC6F2 IC6F1 IC6F0 IC6PSC1 IC6PSC0 CC6S1 CC6S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪģʽ */ + +#define PWMA_IC2F_FilterClock(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0x0F) | (n<<4) //벶 2 ˲ѡ񣬸λ TIn IJƵʼ˲ +#define PWMB_IC6F_FilterClock(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0x0F) | (n<<4) //벶 6 ˲ѡ񣬸λ TIn IJƵʼ˲ + +#define PWMA_IC2PSC_PrescalerSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0xF3) | ((n&3)<<2) /// 2 ԤƵ0~3 +#define PWMB_IC6PSC_PrescalerSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0xF3) | ((n&3)<<2) /// 6 ԤƵ0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR3 = 0xFECAH; OC3CE OC3M2 OC3M1 OC3M0 OC3PE OC3FE CC3S1 CC3S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪȽģʽ */ +//sfr PWMB_CCMR3 = 0xFEEAH; OC7CE OC7M2 OC7M1 OC7M0 OC7PE OC7FE CC7S1 CC7S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪȽģʽ */ + +#define PWMA_OC3ModeSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x70) | (n) //Ƚģʽ +#define PWMB_OC7ModeSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x70) | (n) //Ƚģʽ + +#define PWMA_OC3_ReloadEnable() PWMA_CCMR3 |= 0x08 //1 OC3PE ȽϵԤװع +#define PWMA_OC3_RelosdDisable() PWMA_CCMR3 &= ~0x08 //0ֹ OC3PE ȽϵԤװع +#define PWMB_OC7_ReloadEnable() PWMB_CCMR3 |= 0x08 //1 OC7PE ȽϵԤװع +#define PWMB_OC7_RelosdDisable() PWMB_CCMR3 &= ~0x08 //0ֹ OC7PE ȽϵԤװع + +#define PWMA_OC3_FastEnable() PWMA_CCMR3 |= 0x04 //1 OC3FE ȽϿٹ +#define PWMA_OC3_FastDisable() PWMA_CCMR3 &= ~0x04 //0ֹ OC3FE ȽϿٹ +#define PWMB_OC7_FastEnable() PWMB_CCMR3 |= 0x04 //1 OC7FE ȽϿٹ +#define PWMB_OC7_FastDisable() PWMB_CCMR3 &= ~0x04 //0ֹ OC7FE ȽϿٹ + +#define PWMA_CC3S_Direction(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x03) | (n) ///Ƚ 3 ѡλͨķ/ŵѡ +#define PWMB_CC7S_Direction(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x03) | (n) ///Ƚ 7 ѡλͨķ/ŵѡ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR3 = 0xFECAH; IC3F3 IC3F2 IC3F1 IC3F0 IC3PSC1 IC3PSC0 CC3S1 CC3S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪģʽ */ +//sfr PWMB_CCMR3 = 0xFEEAH; IC7F3 IC7F2 IC7F1 IC7F0 IC7PSC1 IC7PSC0 CC7S1 CC7S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪģʽ */ + +#define PWMA_IC3F_FilterClock(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0x0F) | (n<<4) //벶 3 ˲ѡ񣬸λ TIn IJƵʼ˲ +#define PWMB_IC7F_FilterClock(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0x0F) | (n<<4) //벶 7 ˲ѡ񣬸λ TIn IJƵʼ˲ + +#define PWMA_IC3PSC_PrescalerSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0xF3) | ((n&3)<<2) /// 3 ԤƵ0~3 +#define PWMB_IC7PSC_PrescalerSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0xF3) | ((n&3)<<2) /// 7 ԤƵ0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR4 = 0xFECBH; OC4CE OC4M2 OC4M1 OC4M0 OC4PE OC4FE CC4S1 CC4S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪȽģʽ */ +//sfr PWMB_CCMR4 = 0xFEEBH; OC8CE OC8M2 OC8M1 OC8M0 OC8PE OC8FE CC8S1 CC8S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪȽģʽ */ + +#define PWMA_OC4ModeSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x70) | (n) //Ƚģʽ +#define PWMB_OC8ModeSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x70) | (n) //Ƚģʽ + +#define PWMA_OC4_ReloadEnable() PWMA_CCMR4 |= 0x08 //1 OC4PE ȽϵԤװع +#define PWMA_OC4_RelosdDisable() PWMA_CCMR4 &= ~0x08 //0ֹ OC4PE ȽϵԤװع +#define PWMB_OC8_ReloadEnable() PWMB_CCMR4 |= 0x08 //1 OC8PE ȽϵԤװع +#define PWMB_OC8_RelosdDisable() PWMB_CCMR4 &= ~0x08 //0ֹ OC8PE ȽϵԤװع + +#define PWMA_OC4_FastEnable() PWMA_CCMR4 |= 0x04 //1 OC4FE ȽϿٹ +#define PWMA_OC4_FastDisable() PWMA_CCMR4 &= ~0x04 //0ֹ OC4FE ȽϿٹ +#define PWMB_OC8_FastEnable() PWMB_CCMR4 |= 0x04 //1 OC8FE ȽϿٹ +#define PWMB_OC8_FastDisable() PWMB_CCMR4 &= ~0x04 //0ֹ OC8FE ȽϿٹ + +#define PWMA_CC4S_Direction(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x03) | (n) ///Ƚ 4 ѡλͨķ/ŵѡ +#define PWMB_CC8S_Direction(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x03) | (n) ///Ƚ 8 ѡλͨķ/ŵѡ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR4 = 0xFECBH; IC4F3 IC4F2 IC4F1 IC4F0 IC4PSC1 IC4PSC0 CC4S1 CC4S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪģʽ */ +//sfr PWMB_CCMR4 = 0xFEEBH; IC8F3 IC8F2 IC8F1 IC8F0 IC8PSC1 IC8PSC0 CC8S1 CC8S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪģʽ */ + +#define PWMA_IC4F_FilterClock(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0x0F) | (n<<4) //벶 4 ˲ѡ񣬸λ TIn IJƵʼ˲ +#define PWMB_IC8F_FilterClock(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0x0F) | (n<<4) //벶 8 ˲ѡ񣬸λ TIn IJƵʼ˲ + +#define PWMA_IC4PSC_PrescalerSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0xF3) | ((n&3)<<2) /// 4 ԤƵ0~3 +#define PWMB_IC8PSC_PrescalerSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0xF3) | ((n&3)<<2) /// 8 ԤƵ0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCER1 = 0xFECCH; CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 0000,0000 /* /ȽʹܼĴ 1 */ +//sfr PWMB_CCER1 = 0xFEECH; - - CC6P CC6E - - CC5P CC5E 0000,0000 /* /ȽʹܼĴ 1 */ + +#define PWMA_CCER1_Disable() PWMA_CCER1 = 0x00 //ر벶/Ƚ +#define PWMA_CC1E_Enable() PWMA_CCER1 |= 0x01 //1벶/Ƚ +#define PWMA_CC1E_Disable() PWMA_CCER1 &= ~0x01 //0ر벶/Ƚ +#define PWMA_CC1P_LowValid() PWMA_CCER1 |= 0x02 //1͵ƽЧ +#define PWMA_CC1P_HighValid() PWMA_CCER1 &= ~0x02 //0ߵƽЧ +#define PWMA_CC1P_CaptureRise() PWMA_CCER1 |= 0x02 //1 TI1F TI2F ½ +#define PWMA_CC1P_CaptureFall() PWMA_CCER1 &= ~0x02 //0 TI1F TI2F +#define PWMA_CC1NE_Enable() PWMA_CCER1 |= 0x04 //1Ƚ +#define PWMA_CC1NE_Disable() PWMA_CCER1 &= ~0x04 //0رձȽ +#define PWMA_CC1NP_LowValid() PWMA_CCER1 |= 0x08 //1͵ƽЧ +#define PWMA_CC1NP_HighValid() PWMA_CCER1 &= ~0x08 //0ߵƽЧ + +#define PWMA_CC2E_Enable() PWMA_CCER1 |= 0x10 //1벶/Ƚ +#define PWMA_CC2E_Disable() PWMA_CCER1 &= ~0x10 //0ر벶/Ƚ +#define PWMA_CC2P_LowValid() PWMA_CCER1 |= 0x20 //1͵ƽЧ +#define PWMA_CC2P_HighValid() PWMA_CCER1 &= ~0x20 //0ߵƽЧ +#define PWMA_CC2P_CaptureRise() PWMA_CCER1 |= 0x20 //1 TI1F TI2F ½ +#define PWMA_CC2P_CaptureFall() PWMA_CCER1 &= ~0x20 //0 TI1F TI2F +#define PWMA_CC2NE_Enable() PWMA_CCER1 |= 0x40 //1Ƚ +#define PWMA_CC2NE_Disable() PWMA_CCER1 &= ~0x40 //0رձȽ +#define PWMA_CC2NP_LowValid() PWMA_CCER1 |= 0x80 //1͵ƽЧ +#define PWMA_CC2NP_HighValid() PWMA_CCER1 &= ~0x80 //0ߵƽЧ + +#define PWMB_CCER1_Disable() PWMB_CCER1 = 0x00 //ر벶/Ƚ +#define PWMB_CC5E_Enable() PWMB_CCER1 |= 0x01 //1벶/Ƚ +#define PWMB_CC5E_Disable() PWMB_CCER1 &= ~0x01 //0ر벶/Ƚ +#define PWMB_CC5P_LowValid() PWMB_CCER1 |= 0x02 //1͵ƽЧ +#define PWMB_CC5P_HighValid() PWMB_CCER1 &= ~0x02 //0ߵƽЧ +#define PWMB_CC5P_CaptureRise() PWMB_CCER1 |= 0x02 //1 TI1F TI2F ½ +#define PWMB_CC5P_CaptureFall() PWMB_CCER1 &= ~0x02 //0 TI1F TI2F + +#define PWMB_CC6E_Enable() PWMB_CCER1 |= 0x10 //1벶/Ƚ +#define PWMB_CC6E_Disable() PWMB_CCER1 &= ~0x10 //0ر벶/Ƚ +#define PWMB_CC6P_LowValid() PWMB_CCER1 |= 0x20 //1͵ƽЧ +#define PWMB_CC6P_HighValid() PWMB_CCER1 &= ~0x20 //0ߵƽЧ +#define PWMB_CC6P_CaptureRise() PWMB_CCER1 |= 0x20 //1 TI1F TI2F ½ +#define PWMB_CC6P_CaptureFall() PWMB_CCER1 &= ~0x20 //0 TI1F TI2F + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCER2 = 0xFECDH; CC4NP CC4NE CC4P CC4E CC3NP CC3NE CC3P CC3E 0000,0000 /* /ȽʹܼĴ 2 */ +//sfr PWMB_CCER2 = 0xFEEDH; - - CC8P CC8E - - CC7P CC7E 0000,0000 /* /ȽʹܼĴ 2 */ + +#define PWMA_CCER2_Disable() PWMA_CCER2 = 0x00 //ر벶/Ƚ +#define PWMA_CC3E_Enable() PWMA_CCER2 |= 0x01 //1벶/Ƚ +#define PWMA_CC3E_Disable() PWMA_CCER2 &= ~0x01 //0ر벶/Ƚ +#define PWMA_CC3P_LowValid() PWMA_CCER2 |= 0x02 //1͵ƽЧ +#define PWMA_CC3P_HighValid() PWMA_CCER2 &= ~0x02 //0ߵƽЧ +#define PWMA_CC3P_CaptureRise() PWMA_CCER2 |= 0x02 //1 TI1F TI2F ½ +#define PWMA_CC3P_CaptureFall() PWMA_CCER2 &= ~0x02 //0 TI1F TI2F +#define PWMA_CC3NE_Enable() PWMA_CCER2 |= 0x04 //1Ƚ +#define PWMA_CC3NE_Disable() PWMA_CCER2 &= ~0x04 //0رձȽ +#define PWMA_CC3NP_LowValid() PWMA_CCER2 |= 0x08 //1͵ƽЧ +#define PWMA_CC3NP_HighValid() PWMA_CCER2 &= ~0x08 //0ߵƽЧ + +#define PWMA_CC4E_Enable() PWMA_CCER2 |= 0x10 //1벶/Ƚ +#define PWMA_CC4E_Disable() PWMA_CCER2 &= ~0x10 //0ر벶/Ƚ +#define PWMA_CC4P_LowValid() PWMA_CCER2 |= 0x20 //1͵ƽЧ +#define PWMA_CC4P_HighValid() PWMA_CCER2 &= ~0x20 //0ߵƽЧ +#define PWMA_CC4P_CaptureRise() PWMA_CCER2 |= 0x20 //1 TI1F TI2F ½ +#define PWMA_CC4P_CaptureFall() PWMA_CCER2 &= ~0x20 //0 TI1F TI2F +#define PWMA_CC4NE_Enable() PWMA_CCER2 |= 0x40 //1Ƚ +#define PWMA_CC4NE_Disable() PWMA_CCER2 &= ~0x40 //0رձȽ +#define PWMA_CC4NP_LowValid() PWMA_CCER2 |= 0x80 //1͵ƽЧ +#define PWMA_CC4NP_HighValid() PWMA_CCER2 &= ~0x80 //0ߵƽЧ + +#define PWMB_CCER2_Disable() PWMB_CCER2 = 0x00 //ر벶/Ƚ +#define PWMB_CC7E_Enable() PWMB_CCER2 |= 0x01 //1벶/Ƚ +#define PWMB_CC7E_Disable() PWMB_CCER2 &= ~0x01 //0ر벶/Ƚ +#define PWMB_CC7P_LowValid() PWMB_CCER2 |= 0x02 //1͵ƽЧ +#define PWMB_CC7P_HighValid() PWMB_CCER2 &= ~0x02 //0ߵƽЧ +#define PWMB_CC7P_CaptureRise() PWMB_CCER2 |= 0x02 //1 TI1F TI2F ½ +#define PWMB_CC7P_CaptureFall() PWMB_CCER2 &= ~0x02 //0 TI1F TI2F + +#define PWMB_CC8E_Enable() PWMB_CCER2 |= 0x10 //1벶/Ƚ +#define PWMB_CC8E_Disable() PWMB_CCER2 &= ~0x10 //0ر벶/Ƚ +#define PWMB_CC8P_LowValid() PWMB_CCER2 |= 0x20 //1͵ƽЧ +#define PWMB_CC8P_HighValid() PWMB_CCER2 &= ~0x20 //0ߵƽЧ +#define PWMB_CC8P_CaptureRise() PWMB_CCER2 |= 0x20 //1 TI1F TI2F ½ +#define PWMB_CC8P_CaptureFall() PWMB_CCER2 &= ~0x20 //0 TI1F TI2F + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CNTRH = 0xFECEH; CNT1[15:8] 0000,0000 /* 8 λ */ +//sfr PWMB_CNTRH = 0xFEEEH; CNT2[15:8] 0000,0000 /* 8 λ */ +//sfr PWMA_CNTRL = 0xFECFH; CNT1[7:0] 0000,0000 /* 8 λ */ +//sfr PWMB_CNTRL = 0xFEEFH; CNT2[7:0] 0000,0000 /* 8 λ */ + +#define PWMA_Counter(n) PWMA_CNTR = n // +#define PWMB_Counter(n) PWMB_CNTR = n // + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_PSCRH = 0xFED0H; PSC1[15:8] 0000,0000 /* ԤƵ 8 λ */ +//sfr PWMB_PSCRH = 0xFEF0H; PSC2[15:8] 0000,0000 /* ԤƵ 8 λ */ +//sfr PWMA_PSCRL = 0xFED1H; PSC1[7:0] 0000,0000 /* ԤƵ 8 λ */ +//sfr PWMB_PSCRL = 0xFEF1H; PSC2[7:0] 0000,0000 /* ԤƵ 8 λ */ + +#define PWMA_Prescaler(n) PWMA_PSCR = n //ԤƵ +#define PWMB_Prescaler(n) PWMB_PSCR = n //ԤƵ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ARRH = 0xFED2H; ARR1[15:8] 0000,0000 /* ԶװؼĴ 8 λ */ +//sfr PWMB_ARRH = 0xFEF2H; ARR2[15:8] 0000,0000 /* ԶװؼĴ 8 λ */ +//sfr PWMA_ARRL = 0xFED3H; ARR1[7:0] 0000,0000 /* ԶװؼĴ 8 λ */ +//sfr PWMB_ARRL = 0xFEF3H; ARR2[7:0] 0000,0000 /* ԶװؼĴ 8 λ */ + +#define PWMA_AutoReload(n) PWMA_ARR = n //ԶװؼĴ +#define PWMB_AutoReload(n) PWMB_ARR = n //ԶװؼĴ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_RCR = 0xFED4H; REP1[7:0] 0000,0000 /* ظĴ */ +//sfr PWMB_RCR = 0xFEF4H; REP2[7:0] 0000,0000 /* ظĴ */ + +#define PWMA_ReCounter(n) PWMA_RCR = n //ظĴ +#define PWMB_ReCounter(n) PWMB_RCR = n //ظĴ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR1H = 0xFED5H; CCR1[15:8] 0000,0000 /* /ȽϼĴ 1 8 λ */ +//sfr PWMB_CCR5H = 0xFEF5H; CCR5[15:8] 0000,0000 /* /ȽϼĴ 1 8 λ */ +//sfr PWMA_CCR1L = 0xFED6H; CCR1[7:0] 0000,0000 /* /ȽϼĴ 1 8 λ */ +//sfr PWMB_CCR5L = 0xFEF6H; CCR5[7:0] 0000,0000 /* /ȽϼĴ 1 8 λ */ + +#define PWMA_Duty1(n) PWMA_CCR1 = n ///ȽϼĴ 1 +#define PWMB_Duty5(n) PWMB_CCR5 = n ///ȽϼĴ 1 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR2H = 0xFED7H; CCR2[15:8] 0000,0000 /* /ȽϼĴ 2 8 λ */ +//sfr PWMB_CCR6H = 0xFEF7H; CCR6[15:8] 0000,0000 /* /ȽϼĴ 2 8 λ */ +//sfr PWMA_CCR2L = 0xFED8H; CCR2[7:0] 0000,0000 /* /ȽϼĴ 2 8 λ */ +//sfr PWMB_CCR6L = 0xFEF8H; CCR6[7:0] 0000,0000 /* /ȽϼĴ 2 8 λ */ + +#define PWMA_Duty2(n) PWMA_CCR2 = n ///ȽϼĴ 2 +#define PWMB_Duty6(n) PWMB_CCR6 = n ///ȽϼĴ 2 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR3H = 0xFED9H; CCR3[15:8] 0000,0000 /* /ȽϼĴ 3 8 λ */ +//sfr PWMB_CCR7H = 0xFEF9H; CCR7[15:8] 0000,0000 /* /ȽϼĴ 3 8 λ */ +//sfr PWMA_CCR3L = 0xFEDAH; CCR3[7:0] 0000,0000 /* /ȽϼĴ 3 8 λ */ +//sfr PWMB_CCR7L = 0xFEFAH; CCR7[7:0] 0000,0000 /* /ȽϼĴ 3 8 λ */ + +#define PWMA_Duty3(n) PWMA_CCR3 = n ///ȽϼĴ 3 +#define PWMB_Duty7(n) PWMB_CCR7 = n ///ȽϼĴ 3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR4H = 0xFEDBH; CCR4[15:8] 0000,0000 /* /ȽϼĴ 4 8 λ */ +//sfr PWMB_CCR8H = 0xFEFBH; CCR8[15:8] 0000,0000 /* /ȽϼĴ 4 8 λ */ +//sfr PWMA_CCR4L = 0xFEDCH; CCR4[7:0] 0000,0000 /* /ȽϼĴ 4 8 λ */ +//sfr PWMB_CCR8L = 0xFEFCH; CCR8[7:0] 0000,0000 /* /ȽϼĴ 4 8 λ */ + +#define PWMA_Duty4(n) PWMA_CCR4 = n ///ȽϼĴ 4 +#define PWMB_Duty8(n) PWMB_CCR8 = n ///ȽϼĴ 4 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_BRK = 0xFEDDH; MOE1 AOE1 BKP1 BKE1 OSSR1 OSSI1 LOCK11 LOCK10 0000,0000 /* ɲĴ */ +//sfr PWMB_BRK = 0xFEFDH; MOE2 AOE2 BKP2 BKE2 OSSR2 OSSI2 LOCK21 LOCK20 0000,0000 /* ɲĴ */ + +#define PWMA_BrakeOutputEnable() PWMA_BRK |= 0x80 //1ʹ +#define PWMA_BrakeOutputDisable() PWMA_BRK &= ~0x80 //0ֹ +#define PWMB_BrakeOutputEnable() PWMB_BRK |= 0x80 //1ʹ +#define PWMB_BrakeOutputDisable() PWMB_BRK &= ~0x80 //0ֹ + +#define PWMA_BrakeAutoOutputEnable() PWMA_BRK |= 0x40 //1Զʹ +#define PWMA_BrakeAutoOutputDisable() PWMA_BRK &= ~0x40 //0Զֹ +#define PWMB_BrakeAutoOutputEnable() PWMB_BRK |= 0x40 //1Զʹ +#define PWMB_BrakeAutoOutputDisable() PWMB_BRK &= ~0x40 //0Զֹ + +#define PWMA_BrakeHighValid() PWMA_BRK |= 0x20 //1ɲߵƽЧ +#define PWMA_BrakeLowValid() PWMA_BRK &= ~0x20 //0ɲ͵ƽЧ +#define PWMB_BrakeHighValid() PWMB_BRK |= 0x20 //1ɲߵƽЧ +#define PWMB_BrakeLowValid() PWMB_BRK &= ~0x20 //0ɲ͵ƽЧ + +#define PWMA_BrakeEnable() PWMA_BRK |= 0x10 //1ɲ +#define PWMA_BrakeDisable() PWMA_BRK &= ~0x10 //0ֹɲ +#define PWMB_BrakeEnable() PWMB_BRK |= 0x10 //1ɲ +#define PWMB_BrakeDisable() PWMB_BRK &= ~0x10 //0ֹɲ + +//ģʽ¡ر״̬ѡ +#define PWMA_OSSRnEnable() PWMA_BRK |= 0x08 //1 PWM ʱһ CCiE=1 CCiNE=1ȿ OC/OCN ЧƽȻOC/OCN ʹź=1 +#define PWMA_OSSRnDisable() PWMA_BRK &= ~0x08 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0 +#define PWMB_OSSRnEnable() PWMB_BRK |= 0x08 //1 PWM ʱһ CCiE=1 CCiNE=1ȿ OC/OCN ЧƽȻOC/OCN ʹź=1 +#define PWMB_OSSRnDisable() PWMB_BRK &= ~0x08 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0 +//ģʽ¡ر״̬ѡ +#define PWMA_OSSInEnable() PWMA_BRK |= 0x04 //1 PWM ʱһ CCiE=1 CCiNE=1OC/OCN еƽȻ OC/OCNʹź=1 +#define PWMA_OSSInDisable() PWMA_BRK &= ~0x04 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0 +#define PWMB_OSSInEnable() PWMB_BRK |= 0x04 //1 PWM ʱһ CCiE=1 CCiNE=1OC/OCN еƽȻ OC/OCNʹź=1 +#define PWMB_OSSInDisable() PWMB_BRK &= ~0x04 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0 + +#define PWMn_lock_L0 0 //Ĵд +#define PWMn_lock_L1 1 // 1д PWMn_BKR Ĵ BKEBKPAOE λPWMn_OISR Ĵ OISI λ +#define PWMn_lock_L2 2 // 2д 1 еĸλҲд CC λԼ OSSR/OSSI λ +#define PWMn_lock_L3 3 // 3д 2 еĸλҲд CC λ + +#define PWMA_LockLevelSet(n) PWMA_BRK = (PWMA_BRK & ~0x03) | (n&3) //áλΪֹṩдʩ +#define PWMB_LockLevelSet(n) PWMB_BRK = (PWMB_BRK & ~0x03) | (n&3) //áλΪֹṩдʩ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_DTR = 0xFEDEH; DTG1[7:0] 0000,0000 /* Ĵ */ +//sfr PWMB_DTR = 0xFEFEH; DTG2[7:0] 0000,0000 /* Ĵ */ + +//DTGn[7:5] = 000~011: ʱ = DTGn[7:0] * tCK_PSC +//DTGn[7:5] = 100~101: ʱ = (64 + DTGn[6:0]) * 2 * tCK_PSC +//DTGn[7:5] = 110: ʱ = (32 + DTGn[5:0]) * 8 * tCK_PSC +//DTGn[7:5] = 111: ʱ = (32 + DTGn[4:0]) * 16 * tCK_PSC + +#define PWMA_DeadTime(n) PWMA_DTR = n // +#define PWMB_DeadTime(n) PWMB_DTR = n // + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_OISR = 0xFEDFH; OIS4N OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 0000,0000 /* ״̬Ĵ */ +//sfr PWMB_OISR = 0xFEFFH; - OIS8 - OIS7 - OIS6 - OIS5 x0x0,x0x0 /* ״̬Ĵ */ + +#define PWMA_OC1_OUT_0() PWMA_OISR &= ~0x01 /* MOE=0 ʱ OC1N ʹܣһOC1=0 */ +#define PWMA_OC1_OUT_1() PWMA_OISR |= 0x01 /* MOE=0 ʱ OC1N ʹܣһOC1=1 */ +#define PWMA_OC1N_OUT_0() PWMA_OISR &= ~0x02 /* MOE=0 ʱһOC1N=0 */ +#define PWMA_OC1N_OUT_1() PWMA_OISR |= 0x02 /* MOE=0 ʱһOC1N=1 */ +#define PWMA_OC2_OUT_0() PWMA_OISR &= ~0x04 /* MOE=0 ʱ OC2N ʹܣһOC2=0 */ +#define PWMA_OC2_OUT_1() PWMA_OISR |= 0x04 /* MOE=0 ʱ OC2N ʹܣһOC2=1 */ +#define PWMA_OC2N_OUT_0() PWMA_OISR &= ~0x08 /* MOE=0 ʱһOC2N=0 */ +#define PWMA_OC2N_OUT_1() PWMA_OISR |= 0x08 /* MOE=0 ʱһOC2N=1 */ +#define PWMA_OC3_OUT_0() PWMA_OISR &= ~0x10 /* MOE=0 ʱ OC3N ʹܣһOC3=0 */ +#define PWMA_OC3_OUT_1() PWMA_OISR |= 0x10 /* MOE=0 ʱ OC3N ʹܣһOC3=1 */ +#define PWMA_OC3N_OUT_0() PWMA_OISR &= ~0x20 /* MOE=0 ʱһOC3N=0 */ +#define PWMA_OC3N_OUT_1() PWMA_OISR |= 0x20 /* MOE=0 ʱһOC3N=1 */ +#define PWMA_OC4_OUT_0() PWMA_OISR &= ~0x40 /* MOE=0 ʱ OC4N ʹܣһOC4=0 */ +#define PWMA_OC4_OUT_1() PWMA_OISR |= 0x40 /* MOE=0 ʱ OC4N ʹܣһOC4=1 */ +#define PWMA_OC4N_OUT_0() PWMA_OISR &= ~0x80 /* MOE=0 ʱһOC4N=0 */ +#define PWMA_OC4N_OUT_1() PWMA_OISR |= 0x80 /* MOE=0 ʱһOC4N=1 */ + +#define PWMB_OC5_OUT_0() PWMB_OISR &= ~0x01 /* MOE=0 ʱһOC5=0 */ +#define PWMB_OC5_OUT_1() PWMB_OISR |= 0x01 /* MOE=0 ʱһOC5=1 */ +#define PWMB_OC6_OUT_0() PWMB_OISR &= ~0x04 /* MOE=0 ʱһOC6=0 */ +#define PWMB_OC6_OUT_1() PWMB_OISR |= 0x04 /* MOE=0 ʱһOC6=1 */ +#define PWMB_OC7_OUT_0() PWMB_OISR &= ~0x10 /* MOE=0 ʱһOC7=0 */ +#define PWMB_OC7_OUT_1() PWMB_OISR |= 0x10 /* MOE=0 ʱһOC7=1 */ +#define PWMB_OC8_OUT_0() PWMB_OISR &= ~0x40 /* MOE=0 ʱһOC8=0 */ +#define PWMB_OC8_OUT_1() PWMB_OISR |= 0x40 /* MOE=0 ʱһOC8=1 */ + + + + +/* +;PCA_PWMn: 7 6 5 4 3 2 1 0 +; EBSn_1 EBSn_0 - - - - EPCnH EPCnL +;B5-B2: +;B1(EPCnH): PWMģʽ£CCAPnH9λ +;B0(EPCnL): PWMģʽ£CCAPnL9λ +*/ +#define PWM0_NORMAL() PCA_PWM0 &= ~3 /* PWM0(Ĭ) */ +#define PWM0_OUT_0() PCA_PWM0 |= 3, CCAP0H = 0xff /* PWM0һֱ0 */ +#define PWM0_OUT_1() PCA_PWM0 &= 0xc0, CCAP0H = 0 /* PWM0һֱ1 */ + +#define PWM1_NORMAL() PCA_PWM1 &= ~3 /* PWM1(Ĭ) */ +#define PWM1_OUT_0() PCA_PWM1 |= 3, CCAP1H = 0xff /* PWM1һֱ0 */ +#define PWM1_OUT_1() PCA_PWM1 &= 0xc0, CCAP1H = 0 /* PWM1һֱ1 */ + +#define PWM2_NORMAL() PCA_PWM2 &= ~3 /* PWM2(Ĭ) */ +#define PWM2_OUT_0() PCA_PWM2 |= 3, CCAP2H = 0xff /* PWM2һֱ0 */ +#define PWM2_OUT_1() PCA_PWM2 &= 0xc0, CCAP2H = 0 /* PWM2һֱ1 */ + +//#define PWM3_NORMAL() PCA_PWM3 &= ~3 /* PWM3(Ĭ) */ +//#define PWM3_OUT_0() PCA_PWM3 |= 3, CCAP3H = 0xff /* PWM3һֱ0 */ +//#define PWM3_OUT_1() PCA_PWM3 &= 0xc0, CCAP3H = 0 /* PWM3һֱ1 */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CCON = 0xD8; CF CR - - CCF3 CCF2 CCF1 CCF0 00xx,xx00 //PCA ƼĴ +sbit CCF0 = CCON^0; /* PCA ģ0жϱ־Ӳλ0 */ +sbit CCF1 = CCON^1; /* PCA ģ1жϱ־Ӳλ0 */ +sbit CCF2 = CCON^2; /* PCA ģ2жϱ־Ӳλ0 */ +//sbit CCF3 = CCON^3; /* PCA ģ3жϱ־Ӳλ0 */ +sbit CR = CCON^6; /* 1: PCA0*/ +sbit CF = CCON^7; /* PCACHCLFFFFHΪ0000H־PCAӲλ0*/ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMOD = 0xD9; CIDL - - - CPS2 CPS1 CPS0 ECF 0xxx,0000 //PCA ģʽĴ +#define PCA_IDLE_OFF() CMOD |= (1<<7) /* IDLE״̬PCAֹͣ */ +#define PCA_IDLE_ON() CMOD &= ~(1<<7) /* IDLE״̬PCA */ +#define PCA_CLK_12T() CMOD &= ~0x0E /* PCAѡ fosc/12 */ +#define PCA_CLK_2T() CMOD = (CMOD & ~0x0E) + 2 /* PCAѡ fosc/2 */ +#define PCA_CLK_T0() CMOD = (CMOD & ~0x0E) + 4 /* PCAѡTimer0жϣTimer0ͨAUXRĴóɹ12T1Tģʽ */ +#define PCA_CLK_ECI() CMOD = (CMOD & ~0x0E) + 6 /* PCAѡECI/P3.4ⲿʱӣ fosc/2 */ +#define PCA_CLK_1T() CMOD = (CMOD & ~0x0E) + 8 /* PCAѡ Fosc */ +#define PCA_CLK_4T() CMOD = (CMOD & ~0x0E) + 10 /* PCAѡ Fosc/4 */ +#define PCA_CLK_6T() CMOD = (CMOD & ~0x0E) + 12 /* PCAѡ Fosc/6 */ +#define PCA_CLK_8T() CMOD = (CMOD & ~0x0E) + 14 /* PCAѡ Fosc/8 */ +#define PCA_INT_ENABLE() CMOD |= 1 /* PCAжλ1---CFCCON.7жϡ */ +#define PCA_INT_DISABLE() CMOD &= ~1 /* PCAжϽֹ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr P_SW1 = 0xA2; S1_S1 S1_S0 CCP_S1 CCP_S0 SPI_S1 SPI_S0 0 - nn00,000x //Auxiliary Register 1 +#define PCA_USE_P12P11P10P37() P_SW1 &= ~0x30 /* PCA/PWMлP12(ECI) P11(CCP0) P10(CCP1) P37(CCP2)(ϵĬ) */ +#define PCA_USE_P34P35P36P37() P_SW1 = (P_SW1 & ~0x30) | 0x10 /* PCA/PWMлP34(ECI) P35(CCP0) P36(CCP1) P37(CCP2) */ +#define PCA_USE_P24P25P26P27() P_SW1 = (P_SW1 & ~0x30) | 0x20 /* PCA/PWMлP24(ECI) P25(CCP0) P26(CCP1) P27(CCP2) */ + + +/* 7 6 5 4 3 2 1 0 Reset Value +//sfr CCAPM0 = 0xDA; PWM Ĵ - ECOM0 CCAPP0 CCAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000 //PCA ģ0 +//sfr CCAPM1 = 0xDB; PWM Ĵ - ECOM1 CCAPP1 CCAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000 //PCA ģ1 +//sfr CCAPM2 = 0xDC; PWM Ĵ - ECOM2 CCAPP2 CCAPN2 MAT2 TOG2 PWM2 ECCF2 x000,0000 //PCA ģ2 +//sfr CCAPM3 = 0xDD; PWM Ĵ - ECOM3 CCAPP3 CCAPN3 MAT3 TOG3 PWM3 ECCF3 x000,0000 //PCA ģ3 +;ECOMn = 1: ȽϹܡ +;CAPPn = 1: ش׽ܡ +;CAPNn = 1: ½ش׽ܡ +;MATn = 1: ƥʱCCONеCCFnλ +;TOGn = 1: ƥʱCEXnת(CEX0/PCA0/PWM0/P3.7,CEX1/PCA1/PWM1/P3.5) +;PWMn = 1: CEXnΪPWM +;ECCFn = 1: CCONеCCFnжϡ +;ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +; 0 0 0 0 0 0 0 00H δκιܡ +; x 1 0 0 0 0 x 20H 16λCEXnش׽ܡ +; x 0 1 0 0 0 x 10H 16λCEXn½ش׽ܡ +; x 1 1 0 0 0 x 30H 16λCEXn/PCAnأϡأ׽ܡ +; 1 0 0 1 0 0 x 48H 16λʱ +; 1 0 0 1 1 0 x 4CH 16λ +; 1 0 0 0 0 1 0 42H 8λPWMж +; 1 1 0 0 0 1 1 63H 8λPWMͱ߿ɲж +; 1 0 1 0 0 1 1 53H 8λPWM߱Ϳɲж +; 1 1 1 0 0 1 1 73H 8λPWMͱ߻߱;ɲж +;******************************************************************* +;*******************************************************************/ + +#define PCA0_none() CCAPM0 = 0 +#define PCA0_PWM(nbit) CCAPM0 = 0x42,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_rise_int(nbit) CCAPM0 = 0x63,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_fall_int(nbit) CCAPM0 = 0x53,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_edge_int(nbit) CCAPM0 = 0x73,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_capture_rise() CCAPM0 = (0x20 + 1) +#define PCA0_capture_fall() CCAPM0 = (0x10 + 1) +#define PCA0_capture_edge() CCAPM0 = (0x30 + 1) +#define PCA0_16bit_Timer() CCAPM0 = (0x48 + 1) +#define PCA0_High_PulseEnable() CCAPM0 |= 0x04 + +#define PCA1_none() CCAPM1 = 0 +#define PCA1_PWM(nbit) CCAPM1 = 0x42,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_rise_int(nbit) CCAPM1 = 0x63,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_fall_int(nbit) CCAPM1 = 0x53,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_edge_int(nbit) CCAPM1 = 0x73,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_capture_rise() CCAPM1 = (0x20 + 1) +#define PCA1_capture_fall() CCAPM1 = (0x10 + 1) +#define PCA1_capture_edge() CCAPM1 = (0x30 + 1) +#define PCA1_16bit_Timer() CCAPM1 = (0x48 + 1) +#define PCA1_High_PulseEnable() CCAPM1 |= 0x04 + +#define PCA2_none() CCAPM2 = 0 +#define PCA2_PWM(nbit) CCAPM2 = 0x42,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_rise_int(nbit) CCAPM2 = 0x63,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_fall_int(nbit) CCAPM2 = 0x53,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_edge_int(nbit) CCAPM2 = 0x73,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_capture_rise() CCAPM2 = (0x20 + 1) +#define PCA2_capture_fall() CCAPM2 = (0x10 + 1) +#define PCA2_capture_edge() CCAPM2 = (0x30 + 1) +#define PCA2_16bit_Timer() CCAPM2 = (0x48 + 1) +#define PCA2_High_PulseEnable() CCAPM2 |= 0x04 + +//#define PCA3_none() CCAPM3 = 0 +//#define PCA3_PWM(nbit) CCAPM3 = 0x42,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_rise_int(nbit) CCAPM3 = 0x63,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_fall_int(nbit) CCAPM3 = 0x53,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_edge_int(nbit) CCAPM3 = 0x73,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_capture_rise() CCAPM3 = (0x20 + 1) +//#define PCA3_capture_fall() CCAPM3 = (0x10 + 1) +//#define PCA3_capture_edge() CCAPM3 = (0x30 + 1) +//#define PCA3_16bit_Timer() CCAPM3 = (0x48 + 1) +//#define PCA3_High_PulseEnable() CCAPM3 |= 0x04 + +/**********************************************************/ +typedef unsigned char u8; +typedef unsigned int u16; +typedef unsigned long u32; + +/**********************************************************/ +#define NOP1() _nop_() +#define NOP2() NOP1(),NOP1() +#define NOP3() NOP2(),NOP1() +#define NOP4() NOP3(),NOP1() +#define NOP5() NOP4(),NOP1() +#define NOP6() NOP5(),NOP1() +#define NOP7() NOP6(),NOP1() +#define NOP8() NOP7(),NOP1() +#define NOP9() NOP8(),NOP1() +#define NOP10() NOP9(),NOP1() +#define NOP11() NOP10(),NOP1() +#define NOP12() NOP11(),NOP1() +#define NOP13() NOP12(),NOP1() +#define NOP14() NOP13(),NOP1() +#define NOP15() NOP14(),NOP1() +#define NOP16() NOP15(),NOP1() +#define NOP17() NOP16(),NOP1() +#define NOP18() NOP17(),NOP1() +#define NOP19() NOP18(),NOP1() +#define NOP20() NOP19(),NOP1() +#define NOP21() NOP20(),NOP1() +#define NOP22() NOP21(),NOP1() +#define NOP23() NOP22(),NOP1() +#define NOP24() NOP23(),NOP1() +#define NOP25() NOP24(),NOP1() +#define NOP26() NOP25(),NOP1() +#define NOP27() NOP26(),NOP1() +#define NOP28() NOP27(),NOP1() +#define NOP29() NOP28(),NOP1() +#define NOP30() NOP29(),NOP1() +#define NOP31() NOP30(),NOP1() +#define NOP32() NOP31(),NOP1() +#define NOP33() NOP32(),NOP1() +#define NOP34() NOP33(),NOP1() +#define NOP35() NOP34(),NOP1() +#define NOP36() NOP35(),NOP1() +#define NOP37() NOP36(),NOP1() +#define NOP38() NOP37(),NOP1() +#define NOP39() NOP38(),NOP1() +#define NOP40() NOP39(),NOP1() +#define NOP(N) NOP##N() + + +/**********************************************/ +#define Pin0 0x01 //IO Px.0 +#define Pin1 0x02 //IO Px.1 +#define Pin2 0x04 //IO Px.2 +#define Pin3 0x08 //IO Px.3 +#define Pin4 0x10 //IO Px.4 +#define Pin5 0x20 //IO Px.5 +#define Pin6 0x40 //IO Px.6 +#define Pin7 0x80 //IO Px.7 +#define PinAll 0xFF //IO + +#define P0n_standard(bitn) P0M1 &= ~(bitn), P0M0 &= ~(bitn) /* 00 */ +#define P0n_push_pull(bitn) P0M1 &= ~(bitn), P0M0 |= (bitn) /* 01 */ +#define P0n_pure_input(bitn) P0M1 |= (bitn), P0M0 &= ~(bitn) /* 10 */ +#define P0n_open_drain(bitn) P0M1 |= (bitn), P0M0 |= (bitn) /* 11 */ + +#define P1n_standard(bitn) P1M1 &= ~(bitn), P1M0 &= ~(bitn) +#define P1n_push_pull(bitn) P1M1 &= ~(bitn), P1M0 |= (bitn) +#define P1n_pure_input(bitn) P1M1 |= (bitn), P1M0 &= ~(bitn) +#define P1n_open_drain(bitn) P1M1 |= (bitn), P1M0 |= (bitn) + +#define P2n_standard(bitn) P2M1 &= ~(bitn), P2M0 &= ~(bitn) +#define P2n_push_pull(bitn) P2M1 &= ~(bitn), P2M0 |= (bitn) +#define P2n_pure_input(bitn) P2M1 |= (bitn), P2M0 &= ~(bitn) +#define P2n_open_drain(bitn) P2M1 |= (bitn), P2M0 |= (bitn) + +#define P3n_standard(bitn) P3M1 &= ~(bitn), P3M0 &= ~(bitn) +#define P3n_push_pull(bitn) P3M1 &= ~(bitn), P3M0 |= (bitn) +#define P3n_pure_input(bitn) P3M1 |= (bitn), P3M0 &= ~(bitn) +#define P3n_open_drain(bitn) P3M1 |= (bitn), P3M0 |= (bitn) + +#define P4n_standard(bitn) P4M1 &= ~(bitn), P4M0 &= ~(bitn) +#define P4n_push_pull(bitn) P4M1 &= ~(bitn), P4M0 |= (bitn) +#define P4n_pure_input(bitn) P4M1 |= (bitn), P4M0 &= ~(bitn) +#define P4n_open_drain(bitn) P4M1 |= (bitn), P4M0 |= (bitn) + +#define P5n_standard(bitn) P5M1 &= ~(bitn), P5M0 &= ~(bitn) +#define P5n_push_pull(bitn) P5M1 &= ~(bitn), P5M0 |= (bitn) +#define P5n_pure_input(bitn) P5M1 |= (bitn), P5M0 &= ~(bitn) +#define P5n_open_drain(bitn) P5M1 |= (bitn), P5M0 |= (bitn) + +#define P6n_standard(bitn) P6M1 &= ~(bitn), P6M0 &= ~(bitn) +#define P6n_push_pull(bitn) P6M1 &= ~(bitn), P6M0 |= (bitn) +#define P6n_pure_input(bitn) P6M1 |= (bitn), P6M0 &= ~(bitn) +#define P6n_open_drain(bitn) P6M1 |= (bitn), P6M0 |= (bitn) + +#define P7n_standard(bitn) P7M1 &= ~(bitn), P7M0 &= ~(bitn) +#define P7n_push_pull(bitn) P7M1 &= ~(bitn), P7M0 |= (bitn) +#define P7n_pure_input(bitn) P7M1 |= (bitn), P7M0 &= ~(bitn) +#define P7n_open_drain(bitn) P7M1 |= (bitn), P7M0 |= (bitn) + + +/****************************************************************/ + + +//sfr INT_CLKO = 0x8F; //ӵ SFR WAKE_CLKO (ַ0x8F) +/* + 7 6 5 4 3 2 1 0 Reset Value + - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000B +b6 - EX4 : жINT4 +b5 - EX3 : жINT3 +b4 - EX2 : жINT2 +b2 - T1CLKO : T2 P3.0Fck1 = 1/2 T1 +b1 - T1CLKO : T1 P3.4Fck1 = 1/2 T1 +b0 - T0CLKO : T0 P3.5Fck0 = 1/2 T0 +*/ + +#define LVD_InterruptEnable() ELVD = 1 +#define LVD_InterruptDisable() ELVD = 0 + + +//sfr WKTCL = 0xAA; //Ѷʱֽ +//sfr WKTCH = 0xAB; //Ѷʱֽ +// B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 +// WKTEN S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 n * 560us +#define WakeTimerDisable() WKTCH &= 0x7f /* WKTEN = 0 ֹ˯߻Ѷʱ */ +#define WakeTimerSet(scale) WKTCL = (scale) % 256,WKTCH = (scale) / 256 | 0x80 /* WKTEN = 1 ˯߻Ѷʱ */ + + + +//sfr BUS_SPEED = 0xA1; //Stretch register - - - - - - EXRTS1 EXRTSS0 xxxx,xx10 +#define BUS_SPEED_1T() BUS_SPEED = BUS_SPEED & ~3 +#define BUS_SPEED_2T() BUS_SPEED = (BUS_SPEED & ~3) | 1 +#define BUS_SPEED_4T() BUS_SPEED = (BUS_SPEED & ~3) | 2 +#define BUS_SPEED_8T() BUS_SPEED = (BUS_SPEED & ~3) | 3 + +#define BUS_RD_WR_P44_P43() BUS_SPEED = BUS_SPEED & 0x3f +#define BUS_RD_WR_P37_P36() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x40 +#define BUS_RD_WR_P42_P40() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x80 + + +/* interrupt vector */ +#define INT0_VECTOR 0 +#define TIMER0_VECTOR 1 +#define INT1_VECTOR 2 +#define TIMER1_VECTOR 3 +#define UART1_VECTOR 4 +#define ADC_VECTOR 5 +#define LVD_VECTOR 6 +#define PCA_VECTOR 7 +#define UART2_VECTOR 8 +#define SPI_VECTOR 9 +#define INT2_VECTOR 10 +#define INT3_VECTOR 11 +#define TIMER2_VECTOR 12 +#define INT4_VECTOR 16 +#define UART3_VECTOR 17 +#define UART4_VECTOR 18 +#define TIMER3_VECTOR 19 +#define TIMER4_VECTOR 20 +#define CMP_VECTOR 21 +#define PWM0_VECTOR 22 +#define PWMFD_VECTOR 23 +#define I2C_VECTOR 24 +#define USB_VECTOR 25 +#define PWMA_VECTOR 26 +#define PWMB_VECTOR 27 +#define PWM1_VECTOR 28 +#define PWM2_VECTOR 29 +#define PWM3_VECTOR 30 +#define PWM4_VECTOR 31 +#define PWM5_VECTOR 32 + + +#define TRUE 1 +#define FALSE 0 + +//============================================================= + +//======================================== + +#define Priority_0 0 //жȼΪ 0 ͼ +#define Priority_1 1 //жȼΪ 1 ϵͼ +#define Priority_2 2 //жȼΪ 2 ϸ߼ +#define Priority_3 3 //жȼΪ 3 ߼ + +//======================================== + +#define ENABLE 1 +#define DISABLE 0 + +#endif diff --git a/Start_Init.c b/Start_Init.c new file mode 100644 index 0000000..c1c35cc --- /dev/null +++ b/Start_Init.c @@ -0,0 +1,39 @@ +#include "STC8xxxx.h" +#include "Start_Init.h" +#include "string.h" +#include "UART_Set.h" +#include "timer.h" +#include "pwm_control.h" + +void Start_Init(void) +{ + u8 i; + memset(&g_Usart,0,sizeof(g_Usart)); + memset(&s_recv, 0, sizeof(s_recv)); + memset(&g_answer,0,sizeof(g_answer)); + g_Usart.lastsn=0xFF; + s_recv.B_min = 0; + s_recv.B_max = 100; + s_recv.global_brightness = 100; + + for(i=0;i<12;i++) + { + s_recv.pwm_step[i] = 1; + s_recv.key_status[i] = 1; + s_recv.gradual_time[i] = 300; + } +} + +//ʱ21msʱ +void Timer2_Init_1ms(void) +{ + TIM_InitTypeDef TIM_InitStructure; //ṹ + TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload; //ָģʽ, TIM_16BitAutoReload,TIM_16Bit,TIM_8BitAutoReload,TIM_16BitAutoReloadNoMask + TIM_InitStructure.TIM_Priority = Priority_3; //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + TIM_InitStructure.TIM_Interrupt = ENABLE; //жǷ, ENABLEDISABLE. (ע: Timer2̶Ϊ16λԶװ, жϹ̶Ϊȼ) + TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_12T; //ָʱԴ, TIM_CLOCK_1T,TIM_CLOCK_12T,TIM_CLOCK_Ext + TIM_InitStructure.TIM_ClkOut = DISABLE; //Ƿ, ENABLEDISABLE + TIM_InitStructure.TIM_Value = 63693UL; //ֵ,ʱΪ1ms + TIM_InitStructure.TIM_Run = ENABLE; //Ƿʼʱ, ENABLEDISABLE + Timer_Inilize(Timer2,&TIM_InitStructure); //ʼTimer2 Timer0,Timer1,Timer2,Timer3,Timer4 +} \ No newline at end of file diff --git a/Start_Init.h b/Start_Init.h new file mode 100644 index 0000000..695ce75 --- /dev/null +++ b/Start_Init.h @@ -0,0 +1,6 @@ +#ifndef START_INIT_H +#define START_INIT_H + +void Start_Init(void); +void Timer2_Init_1ms(void); +#endif \ No newline at end of file diff --git a/UART.C b/UART.C new file mode 100644 index 0000000..62daa3a --- /dev/null +++ b/UART.C @@ -0,0 +1,484 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#include "UART.h" +#include "timer.h" + +#ifdef UART1 +COMx_Define COM1; +u8 xdata TX1_Buffer[COM_TX1_Lenth]; //ͻ +u8 xdata RX1_Buffer[COM_RX1_Lenth]; //ջ +#endif +#ifdef UART2 +COMx_Define COM2; +u8 xdata TX2_Buffer[COM_TX2_Lenth]; //ͻ +u8 xdata RX2_Buffer[COM_RX2_Lenth]; //ջ +#endif +#ifdef UART3 +COMx_Define COM3; +u8 xdata TX3_Buffer[COM_TX3_Lenth]; //ͻ +u8 xdata RX3_Buffer[COM_RX3_Lenth]; //ջ +#endif +#ifdef UART4 +COMx_Define COM4; +u8 xdata TX4_Buffer[COM_TX4_Lenth]; //ͻ +u8 xdata RX4_Buffer[COM_RX4_Lenth]; //ջ +#endif + +u8 UART_Configuration(u8 UARTx, COMx_InitDefine *COMx) +{ + u8 i; + u32 j; + +#ifdef UART1 + if(UARTx == UART1) + { + COM1.id = 1; + COM1.TX_read = 0; + COM1.TX_write = 0; + COM1.B_TX_busy = 0; + COM1.RX_Cnt = 0; + COM1.RX_TimeOut = 0; + COM1.B_RX_OK = 0; + for(i=0; iUART_Priority > Priority_3) return 2; // + UART1_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + if(COMx->UART_Mode > UART_9bit_BRTx) return 2; //ģʽ + SCON = (SCON & 0x3f) | COMx->UART_Mode; + if((COMx->UART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + if(COMx->UART_BRT_Use == BRT_Timer1) + { + TR1 = 0; + AUXR &= ~0x01; //S1 BRT Use Timer1; + TMOD &= ~(1<<6); //Timer1 set As Timer + TMOD &= ~0x30; //Timer1_16bitAutoReload; + AUXR |= (1<<6); //Timer1 set as 1T mode + TH1 = (u8)(j>>8); + TL1 = (u8)j; + ET1 = 0; //ֹж + TMOD &= ~0x40; //ʱ + INT_CLKO &= ~0x02; //ʱ + TR1 = 1; + } + else if(COMx->UART_BRT_Use == BRT_Timer2) + { + AUXR &= ~(1<<4); //Timer stop + AUXR |= 0x01; //S1 BRT Use Timer2; + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; // + } + else if(COMx->UART_Mode == UART_ShiftRight) + { + if(COMx->BaudRateDouble == ENABLE) AUXR |= (1<<5); //̶SysClk/2 + else AUXR &= ~(1<<5); //̶SysClk/12 + } + else if(COMx->UART_Mode == UART_9bit) //̶SysClk*2^SMOD/64 + { + if(COMx->BaudRateDouble == ENABLE) PCON |= (1<<7); //̶SysClk/32 + else PCON &= ~(1<<7); //̶SysClk/64 + } + if(COMx->UART_Interrupt == ENABLE) ES = 1; //ж + else ES = 0; //ֹж + if(COMx->UART_RxEnable == ENABLE) REN = 1; // + else REN = 0; //ֹ + P_SW1 = (P_SW1 & 0x3f) | (COMx->UART_P_SW & 0xc0); //лIO + return 0; + } +#endif +#ifdef UART2 + if(UARTx == UART2) + { + COM2.id = 2; + COM2.TX_read = 0; + COM2.TX_write = 0; + COM2.B_TX_busy = 0; + COM2.RX_Cnt = 0; + COM2.RX_TimeOut = 0; + COM2.B_RX_OK = 0; + for(i=0; iUART_Mode == UART_9bit_BRTx) ||(COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + if(COMx->UART_Priority > Priority_3) return 2; // + UART2_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + if(COMx->UART_Mode == UART_9bit_BRTx) S2CON |= (1<<7); //9bit + else S2CON &= ~(1<<7); //8bit + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + AUXR &= ~(1<<4); //Timer stop + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; //ģʽ + if(COMx->UART_Interrupt == ENABLE) IE2 |= 1; //ж + else IE2 &= ~1; //ֹж + if(COMx->UART_RxEnable == ENABLE) S2CON |= (1<<4); // + else S2CON &= ~(1<<4); //ֹ + P_SW2 = (P_SW2 & ~1) | (COMx->UART_P_SW & 0x01); //лIO + return 0; + } +#endif +#ifdef UART3 + if(UARTx == UART3) + { + COM3.id = 3; + COM3.TX_read = 0; + COM3.TX_write = 0; + COM3.B_TX_busy = 0; + COM3.RX_Cnt = 0; + COM3.RX_TimeOut = 0; + COM3.B_RX_OK = 0; + for(i=0; iUART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + if(COMx->UART_Priority > Priority_3) return 2; // + UART3_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + if(COMx->UART_Mode == UART_9bit_BRTx) S3_9bit(); //9bit + else S3_8bit(); //8bit + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + if(COMx->UART_BRT_Use == BRT_Timer3) + { + S3_BRT_UseTimer3(); //S3 BRT Use Timer3; + TH3 = (u8)(j>>8); + TL3 = (u8)j; + T4T3M &= 0xf0; + T4T3M |= 0x0a; //Timer3 set As Timer, 1T mode, Start timer3 + } + else if(COMx->UART_BRT_Use == BRT_Timer2) + { + AUXR &= ~(1<<4); //Timer stop + S3_BRT_UseTimer2(); //S3 BRT Use Timer2; + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; // + } + else return 2; //ģʽ + if(COMx->UART_Interrupt == ENABLE) S3_Int_Enable(); //ж + else S3_Int_Disable(); //ֹж + if(COMx->UART_RxEnable == ENABLE) S3_RX_Enable(); // + else S3_RX_Disable(); //ֹ + P_SW2 = (P_SW2 & ~2) | (COMx->UART_P_SW & 0x02); //лIO + return 0; + } +#endif +#ifdef UART4 + if(UARTx == UART4) + { + COM4.id = 3; + COM4.TX_read = 0; + COM4.TX_write = 0; + COM4.B_TX_busy = 0; + COM4.RX_Cnt = 0; + COM4.RX_TimeOut = 0; + COM4.B_RX_OK = 0; + for(i=0; iUART_Mode == UART_9bit_BRTx) || (COMx->UART_Mode == UART_8bit_BRTx)) //ɱ䲨 + { + if(COMx->UART_Priority > Priority_3) return 2; // + UART4_Priority(COMx->UART_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + if(COMx->UART_Mode == UART_9bit_BRTx) S4_9bit(); //9bit + else S4_8bit(); //8bit + j = (MAIN_Fosc / 4) / COMx->UART_BaudRate; //1T + if(j >= 65536UL) return 2; // + j = 65536UL - j; + if(COMx->UART_BRT_Use == BRT_Timer4) + { + S4_BRT_UseTimer4(); //S4 BRT Use Timer4; + TH4 = (u8)(j>>8); + TL4 = (u8)j; + T4T3M &= 0x0f; + T4T3M |= 0xa0; //Timer4 set As Timer, 1T mode, Start timer4 + } + else if(COMx->UART_BRT_Use == BRT_Timer2) + { + AUXR &= ~(1<<4); //Timer stop + S4_BRT_UseTimer2(); //S4 BRT Use Timer2; + AUXR &= ~(1<<3); //Timer2 set As Timer + AUXR |= (1<<2); //Timer2 set as 1T mode + TH2 = (u8)(j>>8); + TL2 = (u8)j; + IE2 &= ~(1<<2); //ֹж + AUXR |= (1<<4); //Timer run enable + } + else return 2; // + } + else return 2; //ģʽ + if(COMx->UART_Interrupt == ENABLE) S4_Int_Enable(); //ж + else S4_Int_Disable(); //ֹж + if(COMx->UART_RxEnable == ENABLE) S4_RX_Enable(); // + else S4_RX_Disable(); //ֹ + P_SW2 = (P_SW2 & ~4) | (COMx->UART_P_SW & 0x04); //лIO + return 0; + } +#endif + return 2; // +} + +/*********************************************************/ + +/********************* UART1 ************************/ +#ifdef UART1 +void TX1_write2buff(u8 dat) //д뷢ͻ壬ָ+1 +{ + TX1_Buffer[COM1.TX_write] = dat; //װͻ + if(++COM1.TX_write >= COM_TX1_Lenth) COM1.TX_write = 0; + + if(COM1.B_TX_busy == 0) // + { + COM1.B_TX_busy = 1; //־æ + TI = 1; //ж + } +} + +void PrintString1(u8 *puts) +{ + for (; *puts != 0; puts++) TX1_write2buff(*puts); //ֹͣ0 +} +void Printbuffer1(u8 *puts,u8 len) +{ + u8 i; + for (i=0; i= COM_RX1_Lenth) COM1.RX_Cnt = 0; + if(dat=='D') //10'D',ϵͳ + { + stage++; + } + else + { + stage=0; + } + if(stage==10) + { + IAP_CONTR=0x60; + } + RX1_Buffer[COM1.RX_Cnt++] = SBUF; + COM1.RX_TimeOut = TimeOutSet1; + } + } + + if(TI) + { + TI = 0; + if(COM1.TX_read != COM1.TX_write) + { + SBUF = TX1_Buffer[COM1.TX_read]; + if(++COM1.TX_read >= COM_TX1_Lenth) COM1.TX_read = 0; + } + else COM1.B_TX_busy = 0; + } +} +#endif + +/********************* UART2 ************************/ +#ifdef UART2 +void TX2_write2buff(u8 dat) //д뷢ͻ壬ָ+1 +{ + TX2_Buffer[COM2.TX_write] = dat; //װͻ + if(++COM2.TX_write >= COM_TX2_Lenth) COM2.TX_write = 0; + + if(COM2.B_TX_busy == 0) // + { + COM2.B_TX_busy = 1; //־æ + SET_TI2(); //ж + } +} + +void PrintString2(u8 *puts) +{ + for (; *puts != 0; puts++) TX2_write2buff(*puts); //ֹͣ0 +} + +void UART2_int (void) interrupt UART2_VECTOR +{ + if(RI2) + { + CLR_RI2(); + if(COM2.B_RX_OK == 0) + { + if(COM2.RX_Cnt >= COM_RX2_Lenth) COM2.RX_Cnt = 0; + RX2_Buffer[COM2.RX_Cnt++] = S2BUF; + COM2.RX_TimeOut = TimeOutSet2; + } + } + + if(TI2) + { + CLR_TI2(); + if(COM2.TX_read != COM2.TX_write) + { + S2BUF = TX2_Buffer[COM2.TX_read]; + if(++COM2.TX_read >= COM_TX2_Lenth) COM2.TX_read = 0; + } + else COM2.B_TX_busy = 0; + } +} +#endif + +/********************* UART3 ************************/ +#ifdef UART3 +void TX3_write2buff(u8 dat) //д뷢ͻ壬ָ+1 +{ + TX3_Buffer[COM3.TX_write] = dat; //װͻ + if(++COM3.TX_write >= COM_TX3_Lenth) COM3.TX_write = 0; + + if(COM3.B_TX_busy == 0) // + { + COM3.B_TX_busy = 1; //־æ + SET_TI3(); //ж + } +} + +void PrintString3(u8 *puts) +{ + for (; *puts != 0; puts++) TX3_write2buff(*puts); //ֹͣ0 +} + +void Printbuffer3(u8 *puts,u8 len) +{ + u8 i; + for (i=0; i= COM_RX3_Lenth) COM3.RX_Cnt = 0; + RX3_Buffer[COM3.RX_Cnt++] = S3BUF; + COM3.RX_TimeOut = TimeOutSet3; + } + } + + if(TI3) //ɱ־λ + { + CLR_TI3(); + if(COM3.TX_read != COM3.TX_write) + { + S3BUF = TX3_Buffer[COM3.TX_read]; + if(++COM3.TX_read >= COM_TX3_Lenth) COM3.TX_read = 0; + } + else COM3.B_TX_busy = 0; + } +} +#endif + +/********************* UART4 ************************/ +#ifdef UART4 +void TX4_write2buff(u8 dat) //д뷢ͻ壬ָ+1 +{ + TX4_Buffer[COM4.TX_write] = dat; //װͻ + if(++COM4.TX_write >= COM_TX4_Lenth) COM4.TX_write = 0; + + if(COM4.B_TX_busy == 0) // + { + COM4.B_TX_busy = 1; //־æ + SET_TI4(); //ж + } +} + +void PrintString4(u8 *puts) +{ + for (; *puts != 0; puts++) TX4_write2buff(*puts); //ֹͣ0 +} + +void UART4_int (void) interrupt UART4_VECTOR +{ + if(RI4) + { + CLR_RI4(); + if(COM4.B_RX_OK == 0) + { + if(COM4.RX_Cnt >= COM_RX4_Lenth) COM4.RX_Cnt = 0; + RX4_Buffer[COM4.RX_Cnt++] = S4BUF; + COM4.RX_TimeOut = TimeOutSet4; + } + } + + if(TI4) + { + CLR_TI4(); + if(COM4.TX_read != COM4.TX_write) + { + S4BUF = TX4_Buffer[COM4.TX_read]; + if(++COM4.TX_read >= COM_TX4_Lenth) COM4.TX_read = 0; + } + else COM4.B_TX_busy = 0; + } +} +#endif + +/*************** ڳʼ *****************/ +void UART3_config(void) +{ + COMx_InitDefine COMx_InitStructure; //ṹ + COMx_InitStructure.UART_Mode = UART_8bit_BRTx; //ģʽ, UART_ShiftRight,UART_8bit_BRTx,UART_9bit,UART_9bit_BRTx + COMx_InitStructure.UART_BRT_Use = BRT_Timer3; //ʹò, BRT_Timer2, BRT_Timer3 (ע: 2̶ʹBRT_Timer2) + COMx_InitStructure.UART_BaudRate = 115200; //, 110 ~ 115200 + COMx_InitStructure.UART_RxEnable = ENABLE; //, ENABLEDISABLE + COMx_InitStructure.UART_Interrupt = ENABLE; //ж, ENABLEDISABLE + COMx_InitStructure.UART_Priority = Priority_0; //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + COMx_InitStructure.UART_P_SW = UART3_SW_P50_P51; //л˿, UART3_SW_P00_P01,UART3_SW_P50_P51 + UART_Configuration(UART3, &COMx_InitStructure); //ʼ3 UART1,UART2,UART3,UART4 + + //PrintString3("STC8 UART3 Test Programme!\r\n"); //UART3һַ +} \ No newline at end of file diff --git a/UART.h b/UART.h new file mode 100644 index 0000000..8699a53 --- /dev/null +++ b/UART.h @@ -0,0 +1,138 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#ifndef __UART_H +#define __UART_H + +#include "config.h" + +#define UART1 1 +//#define UART2 2 +#define UART3 3 +//#define UART4 4 + +#ifdef UART1 +#define COM_TX1_Lenth 32 +#define COM_RX1_Lenth 32 +#endif +#ifdef UART2 +#define COM_TX2_Lenth 128 +#define COM_RX2_Lenth 128 +#endif +#ifdef UART3 +#define COM_TX3_Lenth 32 //32ַ +#define COM_RX3_Lenth 32 +#endif +#ifdef UART4 +#define COM_TX4_Lenth 128 +#define COM_RX4_Lenth 128 +#endif + +#define UART_ShiftRight 0 //ͬλ +#define UART_8bit_BRTx (1<<6) //8λ,ɱ䲨 +#define UART_9bit (2<<6) //9λ,̶ +#define UART_9bit_BRTx (3<<6) //9λ,ɱ䲨 + +#define UART1_SW_P30_P31 0 +#define UART1_SW_P36_P37 (1<<6) +#define UART1_SW_P16_P17 (2<<6) +#define UART1_SW_P43_P44 (3<<6) +#define UART2_SW_P10_P11 0 +#define UART2_SW_P46_P47 1 +#define UART3_SW_P00_P01 0 +#define UART3_SW_P50_P51 2 +#define UART4_SW_P02_P03 0 +#define UART4_SW_P52_P53 4 + + +#define TimeOutSet1 5 +#define TimeOutSet2 5 +#define TimeOutSet3 5 +#define TimeOutSet4 5 + +#define BRT_Timer1 1 +#define BRT_Timer2 2 +#define BRT_Timer3 3 +#define BRT_Timer4 4 + +typedef struct +{ + u8 id; //ں + + u8 TX_read; //Ͷָ + u8 TX_write; //дָ + u8 B_TX_busy; //æ־ + + u8 RX_Cnt; //ֽڼ + u8 RX_TimeOut; //ճʱ + u8 B_RX_OK; //տ +} COMx_Define; + +typedef struct +{ + u8 UART_Mode; //ģʽ, UART_ShiftRight,UART_8bit_BRTx,UART_9bit,UART_9bit_BRTx + u8 UART_BRT_Use; //ʹò, BRT_Timer1,BRT_Timer2 + u32 UART_BaudRate; //, ENABLE,DISABLE + u8 Morecommunicate; //ͨѶ, ENABLE,DISABLE + u8 UART_RxEnable; //, ENABLE,DISABLE + u8 BaudRateDouble; //ʼӱ, ENABLE,DISABLE + u8 UART_Interrupt; //жϿ, ENABLE,DISABLE + u8 UART_Priority; //ȼ, Priority_0,Priority_1,Priority_2,Priority_3 + u8 UART_P_SW; //л˿, UART1_SW_P30_P31,UART1_SW_P36_P37,UART1_SW_P16_P17,UART1_SW_P43_P44 +} COMx_InitDefine; + +#ifdef UART1 +extern COMx_Define COM1; +extern u8 xdata TX1_Buffer[COM_TX1_Lenth]; //ͻ +extern u8 xdata RX1_Buffer[COM_RX1_Lenth]; //ջ +#endif +#ifdef UART2 +extern COMx_Define COM2; +extern u8 xdata TX2_Buffer[COM_TX2_Lenth]; //ͻ +extern u8 xdata RX2_Buffer[COM_RX2_Lenth]; //ջ +#endif +#ifdef UART3 +extern COMx_Define COM3; +extern u8 xdata TX3_Buffer[COM_TX3_Lenth]; //ͻ +extern u8 xdata RX3_Buffer[COM_RX3_Lenth]; //ջ +#endif +#ifdef UART4 +extern COMx_Define COM4; +extern u8 xdata TX4_Buffer[COM_TX4_Lenth]; //ͻ +extern u8 xdata RX4_Buffer[COM_RX4_Lenth]; //ջ +#endif + +u8 UART_Configuration(u8 UARTx, COMx_InitDefine *COMx); +#ifdef UART1 +void TX1_write2buff(u8 dat); //д뷢ͻ壬ָ+1 +void PrintString1(u8 *puts); +void Printbuffer1(u8 *puts,u8 len); +#endif +#ifdef UART2 +void TX2_write2buff(u8 dat); //д뷢ͻ壬ָ+1 +void PrintString2(u8 *puts); +#endif +#ifdef UART3 +void TX3_write2buff(u8 dat); //д뷢ͻ壬ָ+1 +void PrintString3(u8 *puts); +void Printbuffer3(u8 *puts,u8 len); +#endif +#ifdef UART4 +void TX4_write2buff(u8 dat); //д뷢ͻ壬ָ+1 +void PrintString4(u8 *puts); +#endif + +void UART3_config(void); +extern u8 recv_start_flag; +extern u32 recv_time; +#endif + diff --git a/UART_Set.c b/UART_Set.c new file mode 100644 index 0000000..4b60c76 --- /dev/null +++ b/UART_Set.c @@ -0,0 +1,601 @@ +#include "UART_Set.h" +#include "UART.h" +#include "pwm_control.h" +#include "string.h" +#include "config.h" +#include "timer.h" +#include "STC8xxxx.h" +#include "PWM15bit.h" + +G_Usart g_Usart; +G_answer g_answer; +S_recv s_recv; + +u8 debug = 0x00; + + +/* +жϽյָǷϷ +*/ +void Usart_judge_Data(void) +{ + u8 len = 0; + u8 i, sum; + sum = 0; + g_Usart.ok_flag = 0; + + if((recv_start_flag==1)&&(systick_1ms-recv_time>8)) + { + recv_start_flag=0; + #if DEBUG_ + { + for(i=0;i s_recv.B_max) + { + s_recv.B_Ch[i] = s_recv.B_max; + } + + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_Ch[i] * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + + s_recv.gradual_time[i] = g_Usart.recv_buffer[9] * 10; /*յĽʱ*/ + /* + Ϊ + */ + if (s_recv.gradual_time[i] == 0) + { + s_recv.gradual_time[i] = 1; + } + + /*10mspwmֵ*/ + if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + { + s_pwm.every_change_10ms[i] = (float)(s_pwm.wanttopwm[i] - s_pwm.currpwm[i]) / s_recv.gradual_time[i]; + if (s_pwm.every_change_10ms[i] < 1) + { + s_pwm.every_change_10ms[i] = 1; + } + } + + if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + { + s_pwm.every_change_10ms[i] = (float)(s_pwm.currpwm[i] - s_pwm.wanttopwm[i]) / s_recv.gradual_time[i]; + if (s_pwm.every_change_10ms[i] < 1) + { + s_pwm.every_change_10ms[i] = 1; + } + } + } + } + + //ڶʹλ + for (i = 0; i < 4; i++) + { + if (g_Usart.recv_buffer[8] & (1 << i)) + { + s_recv.flag1[i+8] = 1; + s_recv.flag2[i+8] = 0; + s_recv.B_Ch[i+8] = g_Usart.recv_buffer[13 - i]; + + if (s_recv.B_Ch[i+8] < s_recv.B_min) + { + s_recv.B_Ch[i+8] = s_recv.B_min; + } + + if (s_recv.B_Ch[i+8] > s_recv.B_max) + { + s_recv.B_Ch[i+8] = s_recv.B_max; + } + + s_pwm.wanttopwm[i+8] = PWM_MAX_VALUE - s_recv.B_Ch[i+8] * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i+8]; + s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + + s_recv.gradual_time[i+8] = g_Usart.recv_buffer[9] * 10; /*յĽʱ*/ + + /* + Ϊ + */ + if (s_recv.gradual_time[i+8] == 0) + { + s_recv.gradual_time[i+8] = 1; + } + + /*10mspwmֵ*/ + if (s_pwm.wanttopwm[i+8] > s_pwm.currpwm[i+8]) + { + s_pwm.every_change_10ms[i+8] = (float)(s_pwm.wanttopwm[i+8] - s_pwm.currpwm[i+8]) / s_recv.gradual_time[i+8]; + if (s_pwm.every_change_10ms[i+8] < 1) + { + s_pwm.every_change_10ms[i+8] = 1; + } + } + + + if (s_pwm.wanttopwm[i+8] < s_pwm.currpwm[i+8]) + { + s_pwm.every_change_10ms[i+8] = (float)(s_pwm.currpwm[i+8] - s_pwm.wanttopwm[i+8]) / s_recv.gradual_time[i+8]; + if (s_pwm.every_change_10ms[i+8] < 1) + { + s_pwm.every_change_10ms[i+8] = 1; + } + } + } + } + + g_answer.short_answer_flag=0x01; + break; + + + //ģʽݼѭ + case USART_CMD_SET_MODE: + g_answer.short_answer[UART_FMT_CMD]=USART_CMD_SET_MODE_A; + if(debug) + { + PrintString1("change light"); + } + + for (i = 0; i < 8; i++) + { + if (g_Usart.recv_buffer[7] & (1 << i)) + { + s_recv.flag1[i] = 0; + s_recv.flag2[i] = 1; + s_recv.mode[i] = g_Usart.recv_buffer[9]; + s_recv.pwm_step[i] = g_Usart.recv_buffer[11]; + + if (s_recv.mode[i] == 0x00) + { + if (g_Usart.recv_buffer[10] == 0x00) + { + s_recv.forward[i] = 0; + } + + if (g_Usart.recv_buffer[10] == 0x01) + { + s_recv.forward[i] = 1; + } + + if (g_Usart.recv_buffer[10] == 0x02) //ת + { + if (s_recv.forward[i] == 0x01) + { + s_recv.forward[i] = 0x00; + continue; // Ϊֹתֱ֮ӽһ״̬ + } + + if (s_recv.forward[i] == 0x00) + { + s_recv.forward[i] = 0x01; + continue; + } + } + } + } + } + + + for (i = 0; i < 4; i++) + { + if (g_Usart.recv_buffer[8] & (1 << i)) + { + s_recv.flag1[i+8] = 0; + s_recv.flag2[i+8] = 1; + s_recv.mode[i+8] = g_Usart.recv_buffer[9]; + s_recv.pwm_step[i+8] = g_Usart.recv_buffer[11]; + + if (s_recv.mode[i+8] == 0x00) + { + if (g_Usart.recv_buffer[10] == 0x00) + { + s_recv.forward[i+8] = 0; + } + + if (g_Usart.recv_buffer[10] == 0x01) + { + s_recv.forward[i+8] = 1; + } + + if (g_Usart.recv_buffer[10] == 0x02) //ת + { + if (s_recv.forward[i+8] == 0x01) + { + s_recv.forward[i+8] = 0x00; + continue; // Ϊֹתֱ֮ӽһ״̬ + } + + if (s_recv.forward[i+8] == 0x00) + { + s_recv.forward[i+8] = 0x01; + continue; + } + } + } + } + } + g_answer.short_answer_flag=0x01; + break; + + + // + case USART_CMD_ALL_BRIGHTNESS: + g_answer.short_answer[UART_FMT_CMD]=USART_CMD_ALL_BRIGHTNESS_A; + + if(debug) + { + PrintString1("global light"); + } + +// s_recv.changeflag = 1; + if (g_Usart.recv_buffer[7] & (1 << 5)) //ȫֿɵ + { + s_recv.B_min = g_Usart.recv_buffer[10]; + for (i = 0; i < 12; i++) + { + if ( s_pwm.currvalue[i] < s_recv.B_min) + { + s_pwm.currvalue[i] = s_recv.B_min; + } + } + } + + if (g_Usart.recv_buffer[7] & (1 << 6)) //ȫֿɵ + { + s_recv.B_max = g_Usart.recv_buffer[9]; + for (i = 0; i < 12; i++) + { + if ( s_pwm.currvalue[i] > s_recv.B_max) + { + s_pwm.currvalue[i] = s_recv.B_max; + } + } + } + + if (g_Usart.recv_buffer[7] & (1 << 7)) //ȫ + { + s_recv.global_brightness = g_Usart.recv_buffer[8]; + + for (i = 0; i < 12; i++) + { +// s_pwm.wanttopwmflash[i] = PWM_MAX_VALUE - s_pwm.currvalue[i] * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + + s_recv.flag1[i] = 1; + s_recv.flag2[i] = 0; + + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_Ch[i] * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; //µʼ + if(s_pwm.wanttopwm[i] > PWM_MAX_VALUE) + { + s_pwm.wanttopwm[i] = PWM_MAX_VALUE; + } + + /*10mspwmֵ*/ + if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + { + s_pwm.every_change_10ms[i] = (float)(s_pwm.wanttopwm[i] - s_pwm.currpwm[i]) / s_recv.gradual_time[i]; + if (s_pwm.every_change_10ms[i] < 1) + { + s_pwm.every_change_10ms[i] = 1; + } + } + + if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + { + s_pwm.every_change_10ms[i] = (float)(s_pwm.currpwm[i] - s_pwm.wanttopwm[i]) / s_recv.gradual_time[i]; + if (s_pwm.every_change_10ms[i] < 1) + { + s_pwm.every_change_10ms[i] = 1; + } + } + } + } + + + g_answer.short_answer_flag=0x01; + break; + + + //ÿ״̬ + case USART_CMD_SWITCH_STATUS: + g_answer.short_answer[UART_FMT_CMD]=USART_CMD_SWITCH_STATUS_A; + if(debug) + { + PrintString1("switch state"); + } + + for (i = 0; i < 8; i++) + { + if (g_Usart.recv_buffer[7] & (1 << i)) + { + if (g_Usart.recv_buffer[9 + i] == 0x01) + { + s_recv.key_status[i] = 0x01; + //s_pwm.currvalue[i] = s_pwm.thenvalue[i]; + Open_Light(i); + } + + if (g_Usart.recv_buffer[9 + i] == 0x00) + { + //s_pwm.thenvalue[i] = s_pwm.currvalue[i]; + Close_Light(i); + s_recv.flag1[i] = 0; + s_recv.flag2[i] = 0; + s_recv.mode[i] = 2; + s_recv.key_status[i] = 0x00; + } + + if (g_Usart.recv_buffer[9 + i] == 0x02) + { + if (s_recv.key_status[i] == 0x00) + { + s_recv.key_status[i] = 0x01; + //s_pwm.currvalue[i] = s_pwm.thenvalue[i]; + Open_Light(i); + continue; + } + + if (s_recv.key_status[i] == 0x01) + { + //s_pwm.thenvalue[i] = s_pwm.currvalue[i]; + Close_Light(i); + s_recv.flag1[i] = 0; + s_recv.flag2[i] = 0; + s_recv.mode[i] = 2; + s_recv.key_status[i] = 0x00; + continue; + } + } + } + } + + + for (i = 0; i < 4; i++) + { + if (g_Usart.recv_buffer[8] & (1 << i)) + { + if (g_Usart.recv_buffer[9 + 8 + i] == 0x01) + { + s_recv.key_status[i+8] = 0x01; + //s_pwm.currvalue[i+8] = s_pwm.thenvalue[i]; + Open_Light(i+8); + } + + if (g_Usart.recv_buffer[9 +8 + i] == 0x00) + { + //s_pwm.thenvalue[i+8] = s_pwm.currvalue[i+8]; + Close_Light(i+8); + s_recv.flag1[i+8] = 0; + s_recv.flag2[i+8] = 0; + s_recv.mode[i+8] = 2; + s_recv.key_status[i+8] = 0x00; + } + + if (g_Usart.recv_buffer[9 + 8 + i] == 0x02) + { + if (s_recv.key_status[i+8] == 0x00) + { + s_recv.key_status[i+8] = 0x01; + //s_pwm.currvalue[i+8] = s_pwm.thenvalue[i]; + Open_Light(i+8); + continue; + } + + + if (s_recv.key_status[i+8] == 0x01) + { + //s_pwm.thenvalue[i+8] = s_pwm.currvalue[i+8]; + Close_Light(i+8); + s_recv.flag1[i+8] = 0; + s_recv.flag2[i+8] = 0; + s_recv.mode[i+8] = 2; + s_recv.key_status[i+8] = 0x00; + continue; + } + } + } + } + g_answer.short_answer_flag=0x01; + break; + case USART_CMD_DEBUG_SET: + g_answer.short_answer[UART_FMT_CMD]=USART_CMD_DEBUG_SET_A; + if(debug) + { + PrintString1("debug"); + } + debug = g_Usart.recv_buffer[7]; + g_answer.short_answer_flag=0x01; + break; + case Usart_CMD_Version: + g_answer.version_answer[UART_FMT_CMD]=Usart_CMD_Version_A; + g_answer.version_answer_flag=0x01; + if(debug) + { + PrintString1("version"); + } + break; + } + g_Usart.ok_flag=0; + } +} + +void Usart_answer(void) +{ + u8 i=0; + u8 checksum=0; + if(g_answer.long_answer_flag) + { + g_answer.long_answer[UART_FMT_ADDR_TX]=ADDR_RX; + g_answer.long_answer[UART_FMT_TYPE]=g_Usart.Sn; + g_answer.long_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + g_answer.long_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + g_answer.long_answer[UART_FMT_LEN]=0x14; + g_answer.long_answer[7] = s_recv.global_brightness; + for(i=0;i<12;i++) + { + g_answer.long_answer[8+i] = s_pwm.currvalue[11-i]; + if(s_recv.key_status[i] == 0x01) + { + g_answer.long_answer[8+i] |= 0x80; + } + } + checksum=sumfunc(g_answer.long_answer,0x14); + g_answer.long_answer[UART_FMT_CKS]=checksum; + + Printbuffer3(g_answer.long_answer,0x14); //3ӡ + + if(debug) + { +// PrintString1("long answer"); + } + g_answer.long_answer_flag=0; + memset(g_Usart.recv_buffer,0,32); + } + if(g_answer.short_answer_flag) + { + g_answer.short_answer[UART_FMT_ADDR_TX]=ADDR_RX; + g_answer.short_answer[UART_FMT_TYPE]=g_Usart.Sn; + g_answer.short_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + g_answer.short_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + g_answer.short_answer[UART_FMT_LEN]=0x07; + checksum=sumfunc(g_answer.short_answer,0x07); + g_answer.short_answer[UART_FMT_CKS]=checksum; + Printbuffer3(g_answer.short_answer,0x07); + if(debug) + { + PrintString1("short answer"); + } + + + g_answer.short_answer_flag=0; + memset(g_Usart.recv_buffer,0,32); + } + + if(g_answer.version_answer_flag) + { + g_answer.version_answer[UART_FMT_ADDR_TX]=ADDR_RX; + g_answer.version_answer[UART_FMT_TYPE]=g_Usart.Sn; + g_answer.version_answer[UART_FMT_DEV_TYPE]=DEV_TYPE; + g_answer.version_answer[UART_FMT_ADDR_RX]=g_Usart.recv_buffer[UART_FMT_ADDR_TX]; + g_answer.version_answer[UART_FMT_LEN]=0x09; + g_answer.version_answer[UART_FMT_CMD+1]=Version_High; + g_answer.version_answer[UART_FMT_CMD+2]=Version_Low; + + checksum=sumfunc(g_answer.version_answer,0x09); + g_answer.version_answer[UART_FMT_CKS]=checksum; + Printbuffer3(g_answer.version_answer,0x09); + if(debug) + { + PrintString1("version_answer"); + } + g_answer.version_answer_flag=0; + memset(g_Usart.recv_buffer,0,32); + } + memset(&g_answer,0,sizeof(g_answer)); +} + +u8 sumfunc(u8* answer,u8 len) +{ + u8 m = 0; + u8 j; + for (j = 0; j < len; j++) + { + if (5 == j) continue; + m += *(answer+j); + } + return ~m; +} \ No newline at end of file diff --git a/UART_Set.h b/UART_Set.h new file mode 100644 index 0000000..8a1bfe2 --- /dev/null +++ b/UART_Set.h @@ -0,0 +1,100 @@ +#ifndef _UART_SET_H +#define _UART_SET_H +#include "STC8xxxx.h" +#define USART_CMD_QUEST 0x20 +#define USART_CMD_SET_BRIGHTNESS 0x21 +#define USART_CMD_SET_MODE 0x22 +#define USART_CMD_ALL_BRIGHTNESS 0x23 +#define USART_CMD_SWITCH_STATUS 0x24 +#define USART_CMD_DEBUG_SET 0x25 //Դ㹻ҲÿƣĬΪ +#define Usart_CMD_Version 0x26 + +#define USART_TEST_MODE 0xE0 +#define USART_TEST_DATA 0xE1 + +#define USART_CMD_QUEST_A 0x30 +#define USART_CMD_SET_BRIGHTNESS_A 0x31 +#define USART_CMD_SET_MODE_A 0x32 +#define USART_CMD_ALL_BRIGHTNESS_A 0x33 +#define USART_CMD_SWITCH_STATUS_A 0x34 +#define USART_CMD_DEBUG_SET_A 0x35 +#define Usart_CMD_Version_A 0x36 + +#define USART_TEST_MODE_A 0xF0 +#define USART_TEST_DATA_A 0xF1 + +#define ADDR_RX 0x01 //C12_CH12ĵַ +#define DEV_TYPE 0x03 + +#define Version_High 0x13 //汾 +#define Version_Low 0x00 + +typedef enum +{ + UART_FMT_ADDR_TX = 0x00, + UART_FMT_TYPE, + UART_FMT_DEV_TYPE, + UART_FMT_ADDR_RX, + UART_FMT_LEN, + UART_FMT_CKS, + UART_FMT_CMD, +} UART_FMT_e; + +typedef struct Usart +{ + u8 lastsn; + u8 Sn; + u8 ok_flag; + u8 recv_buffer[32]; +}xdata G_Usart; + +typedef struct answer +{ + u8 short_answer[7]; + u8 long_answer[20]; + u8 long_answer_flag; + u8 short_answer_flag; + u8 version_answer_flag; + u8 version_answer[9]; +}xdata G_answer; + +//յЧݵĽṹ + /* + * ĸͨǷʹܱ־λ + * flag1ָյ0x21 + * flag2ָյ0x22 + * ߻⣬յ + */ +typedef struct +{ + u16 flag1[12]; + u16 flag2[12]; + + //0x21 + u16 gradual_time[12]; + u16 B_Ch[12]; + + //0x22 + u16 mode[12]; + u16 forward[12]; + u16 pwm_step[12]; + + //0x23 + u16 global_brightness; + u16 B_max; + u16 B_min; +// u16 changeflag; + + //0x24 + u16 key_status[12]; +}xdata S_recv; + +extern S_recv s_recv; +extern G_answer g_answer; +extern G_Usart g_Usart; +void Usart_Deal_Data(void); +void Usart_judge_Data(void); +void Usart_answer(void); +u8 sumfunc(u8* answer,u8 len); +extern u8 debug; +#endif \ No newline at end of file diff --git a/WDT.c b/WDT.c new file mode 100644 index 0000000..1625f12 --- /dev/null +++ b/WDT.c @@ -0,0 +1,35 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#include "WDT.h" + +//======================================================================== +// : void WDT_Inilize(WDT_InitTypeDef *WDT) +// : Źʼ. +// : WDT: ṹ,οWDT.hĶ. +// : none. +// 汾: V1.0, 2020-09-16 +//======================================================================== +void WDT_Inilize(WDT_InitTypeDef *WDT) +{ + if(WDT->WDT_Enable == ENABLE) WDT_CONTR = D_EN_WDT; //ʹܿŹ + + WDT_PS_Set(WDT->WDT_PS); //ŹʱʱӷƵϵ WDT_SCALE_2,WDT_SCALE_4,WDT_SCALE_8,WDT_SCALE_16,WDT_SCALE_32,WDT_SCALE_64,WDT_SCALE_128,WDT_SCALE_256 + if(WDT->WDT_IDLE_Mode == WDT_IDLE_STOP) WDT_CONTR &= ~0x08; //IDLEģʽֹͣ + else WDT_CONTR |= 0x08; //IDLEģʽ +} + +/********************* Ź *************************/ +void WDT_Clear (void) +{ + WDT_CONTR |= D_CLR_WDT; // ι +} diff --git a/WDT.h b/WDT.h new file mode 100644 index 0000000..ebc5c42 --- /dev/null +++ b/WDT.h @@ -0,0 +1,40 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#ifndef __WDT_H +#define __WDT_H + +#include "config.h" + +#define WDT_IDLE_STOP 0 +#define WDT_IDLE_RUN 1 + +#define WDT_SCALE_2 0 /* WDT Timeout=(12*32768*SCALE)/SYSclk */ +#define WDT_SCALE_4 1 +#define WDT_SCALE_8 2 +#define WDT_SCALE_16 3 +#define WDT_SCALE_32 4 +#define WDT_SCALE_64 5 +#define WDT_SCALE_128 6 +#define WDT_SCALE_256 7 + +typedef struct +{ + u8 WDT_Enable; //Źʹ ENABLE,DISABLE + u8 WDT_IDLE_Mode; //IDLEģʽֹͣ WDT_IDLE_STOP,WDT_IDLE_RUN + u8 WDT_PS; //ŹʱʱӷƵϵ WDT_SCALE_2,WDT_SCALE_4,WDT_SCALE_8,WDT_SCALE_16,WDT_SCALE_32,WDT_SCALE_64,WDT_SCALE_128,WDT_SCALE_256 +} WDT_InitTypeDef; + +void WDT_Inilize(WDT_InitTypeDef *WDT); +void WDT_Clear (void); + +#endif diff --git a/config.h b/config.h new file mode 100644 index 0000000..934b182 --- /dev/null +++ b/config.h @@ -0,0 +1,19 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************/ + +#define MAIN_Fosc 22118400L //ʱ +//#define MAIN_Fosc 12000000L //ʱ +//#define MAIN_Fosc 11059200L //ʱ +//#define MAIN_Fosc 5529600L //ʱ +//#define MAIN_Fosc 24000000L //ʱ + +#define STC8Gxx //STC8Gϵ + +/*********************************************************/ +#define DEBUG_ 0 +#include "STC8xxxx.H" + + +#endif diff --git a/key.c b/key.c new file mode 100644 index 0000000..52172e0 --- /dev/null +++ b/key.c @@ -0,0 +1,155 @@ +#include "key.h" +#include "GPIO.h" +#include "timer.h" +#include "string.h" +#include "pwm_control.h" +KEY_t g_Key; + +void Key_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure1; //ṹ + /***********************************1*******************************************/ + GPIO_InitStructure1.Pin = GPIO_Pin_4; //ָҪʼIO 4 + GPIO_InitStructure1.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp + GPIO_Inilize(GPIO_P4,&GPIO_InitStructure1); //ʼ + memset(&g_Key, 0, sizeof(g_Key)); +} + +void Key_ScanTask(void) +{ + u8 i; + static u32 update_10ms = 0; + + if (systick_1ms - update_10ms > 10) + { + update_10ms = systick_1ms; + + for (i = 0; i < KEY_CHN_MAX; i++) + { + switch (g_Key.KEY_STA[i]) + { + case KEY_STA_S0: + if ( P44 == KEY_PRESS ) + { + if (g_Key.delayCnt[i] < KEY_DELAY_COUNT) + { + g_Key.delayCnt[i]++; + } + else + { + g_Key.KEY_STA[i] = KEY_STA_S1; // + g_Key.key_time[i] = 0; + g_Key.delayCnt[i] = 0; + } + } + else + { + g_Key.delayCnt[i] = 0; + g_Key.KEY_STA[i] = KEY_STA_S0; + g_Key.key_val[i] = KEY_VAL_NOT; + } + break; + case KEY_STA_S1: + g_Key.key_time[i] ++; + if ( g_Key.key_time[i] < KEY_DELAY_COUNT_LONG ) + { + if ( P44 == KEY_LOOSEN ) //ɿ + { + g_Key.key_val[i] = KEY_VAL_SHORT_PRESS; //̰ɿ + g_Key.key_time[i] = 0; + g_Key.KEY_STA[i] = KEY_STA_S0; + } + } + else + { + g_Key.KEY_STA[i] = KEY_STA_S2; + g_Key.key_time[i] = 0; + g_Key.key_longPress[i] = KEY_VAL_SINGLE_LONG_PRESS; // + g_Key.key_val[i] = KEY_VAL_CONT_LONG_PRESS; // + } + break; + + case KEY_STA_S2: + g_Key.key_longPress[i] = KEY_VAL_NOT; + if ( P44 == KEY_LOOSEN ) + { + g_Key.KEY_STA[i] = KEY_STA_S0; + g_Key.key_val[i] = KEY_VAL_LONG_PRESS_LOOSEN; //ɿ + } + break; + } + } + } +} + + +void KEY_TEST(void) +{ + u8 flag; + if (g_Key.key_val[KEY_CH1] == KEY_VAL_SHORT_PRESS) + { + g_Key.key_val[KEY_CH1] = KEY_VAL_NOT; + s_pwm.key_value++; + switch (s_pwm.key_value) + { + case 1: + s_pwm.currpwm[0] = 2000ul; //90% + s_pwm.currvalue[0]=0x5A; + break; + case 2: + s_pwm.currpwm[1] = 2000ul; + s_pwm.currvalue[1]=0x5A; + break; + case 3: + s_pwm.currpwm[2] = 2000ul; + s_pwm.currvalue[2]=0x5A; + break; + case 4: + s_pwm.currpwm[3] = 2000ul; + s_pwm.currvalue[3]=0x5A; + break; + case 5: + s_pwm.currpwm[4] = 2000ul; + s_pwm.currvalue[4]=0x5A; + break; + case 6: + s_pwm.currpwm[5] = 2000ul; + s_pwm.currvalue[5]=0x5A; + break; + case 7: + s_pwm.currpwm[6] = 2000ul; + s_pwm.currvalue[6]=0x5A; + break; + case 8: + s_pwm.currpwm[7] = 2000ul; + s_pwm.currvalue[7]=0x5A; + break; + case 9: + s_pwm.currpwm[8] = 2000ul; + s_pwm.currvalue[8]=0x5A; + break; + case 10: + s_pwm.currpwm[9] = 2000ul; + s_pwm.currvalue[9]=0x5A; + break; + case 11: + s_pwm.currpwm[10] = 2000ul; + s_pwm.currvalue[10]=0x5A; + break; + case 12: + s_pwm.currpwm[11] = 2000ul; + s_pwm.currvalue[11]=0x5A; + break; + case 13: + for(flag=0;flag<12;flag++) + { + s_pwm.currpwm[flag] = PWM_MAX_VALUE; + s_pwm.currvalue[flag]=0x00; + } + s_pwm.key_value = 0; + break; + default: + break; + } + } +} \ No newline at end of file diff --git a/key.h b/key.h new file mode 100644 index 0000000..51ace0a --- /dev/null +++ b/key.h @@ -0,0 +1,50 @@ +#ifndef KEY_H +#define KEY_H +#include "STC8xxxx.h" +#define DELAY_TIME 10 + +#define KEY_DELAY_COUNT 2 +#define KEY_DELAY_COUNT_LONG 100 +#define KEY_PRESS 0 +#define KEY_LOOSEN 1 + +typedef enum +{ + KEY_CH1, + KEY_CHN_MAX, +}KEY_CHN_e; + +typedef enum +{ + KEY_STA_S0 = 0, + KEY_STA_S1 = 1, + KEY_STA_S2 = 2, +}KEY_STA_e; + +typedef enum +{ + KEY_VAL_NOT, //û + KEY_VAL_SHORT_PRESS, // + KEY_VAL_CONT_LONG_PRESS, // + KEY_VAL_SINGLE_LONG_PRESS, // + KEY_VAL_LONG_PRESS_LOOSEN, //ɿ +}KEY_VAL_e; + +typedef struct +{ + u8 Key_pin[KEY_CHN_MAX]; + u8 KEY_STA[KEY_CHN_MAX]; + u8 key_val[KEY_CHN_MAX]; //0:û, 1:̰ɿ, 2:, 3:ɿ + u8 key_longPress[KEY_CHN_MAX]; //0:û, 1: + u8 key_time[KEY_CHN_MAX]; + u8 delayCnt[KEY_CHN_MAX]; +}KEY_t; + + +void Key_Init(void); +void Key_ScanTask(void); +void KEY_TEST(void); + +extern KEY_t g_Key; + +#endif \ No newline at end of file diff --git a/light_V19.uvgui.cc b/light_V19.uvgui.cc new file mode 100644 index 0000000..c86c1ab --- /dev/null +++ b/light_V19.uvgui.cc @@ -0,0 +1,1923 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 2560 + 1440 + + + + + + 1 + 0 + + 100 + 5 + + .\main.c + 21 + 67 + 108 + 1 + + 0 + + + CONFIG.H + 0 + 1 + 1 + 1 + + 0 + + + START_INIT.H + 0 + 1 + 1 + 1 + + 0 + + + UART_SET.H + 45 + 1 + 29 + 1 + + 0 + + + .\pwm_control.c + 63 + 69 + 105 + 1 + + 0 + + + .\UART_Set.c + 22 + 103 + 121 + 1 + + 0 + + + + + diff --git a/light_V19.uvopt b/light_V19.uvopt new file mode 100644 index 0000000..5d3ed5e --- /dev/null +++ b/light_V19.uvopt @@ -0,0 +1,293 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x0 + MCS-51 + + 35000000 + + 1 + 1 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 9 + + + + + + + + + + + BIN\STCMON51.DLL + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\GPIO.c + GPIO.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\UART.C + UART.C + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\UART_Set.c + UART_Set.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\pwm_control.c + pwm_control.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + .\Start_Init.c + Start_Init.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + .\PWM15bit.c + PWM15bit.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + .\timer.c + timer.c + 0 + 0 + + + 1 + 9 + 1 + 0 + 0 + 0 + .\key.c + key.c + 0 + 0 + + + 1 + 10 + 1 + 0 + 0 + 0 + .\WDT.c + WDT.c + 0 + 0 + + + + diff --git a/light_V19.uvproj b/light_V19.uvproj new file mode 100644 index 0000000..96ee75c --- /dev/null +++ b/light_V19.uvproj @@ -0,0 +1,435 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x0 + MCS-51 + 0 + + + STC8G2K64S4 Series + STC + IRAM(0-0xFF) XRAM(0-0x07FF) IROM(0-0xFFF8) CLOCK(35000000) MODP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 63332 + STC8.H + + + + + + + + + + + 0 + 0 + D:\keil_v5\C51\BIN\ + + + + STC\ + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + BLV_C12_Dimm_V19 + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pDP8051 + S8051.DLL + + TP51.DLL + -p51 + + + + 0 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 9 + + + + + + + + + + + + + + BIN\STCMON51.DLL + + + + + 1 + 0 + 0 + 0 + 0 + -1 + + 0 + + "" () + + + + + 0 + + + + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0xfff9 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + + + + + + + 0 + 1 + 0 + 0 + + + + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Source Group 1 + + + GPIO.c + 1 + .\GPIO.c + + + main.c + 1 + .\main.c + + + UART.C + 1 + .\UART.C + + + UART_Set.c + 1 + .\UART_Set.c + + + pwm_control.c + 1 + .\pwm_control.c + + + Start_Init.c + 1 + .\Start_Init.c + + + PWM15bit.c + 1 + .\PWM15bit.c + + + timer.c + 1 + .\timer.c + + + key.c + 1 + .\key.c + + + WDT.c + 1 + .\WDT.c + + + + + + + + diff --git a/main.c b/main.c new file mode 100644 index 0000000..65d905c --- /dev/null +++ b/main.c @@ -0,0 +1,128 @@ +#include "config.h" +#include "gpio.h" +#include "UART.h" +#include "string.h" +#include "UART_Set.h" +#include "pwm_control.h" +#include "Start_Init.h" +#include "key.h" +#include "WDT.h" +/************* ˵ ************** + +̻STC8H8K64UΪоƬʵ8бдԣSTC8GSTC8HϵоƬͨòο. + +˫ȫ˫жϷʽշͨѶ + +ͨPCMCU, MCUյͨڰյԭ, Ĭϲʣ115200,N,8,1. + +ͨ UART.h ͷļ UART1~UART4 壬ͬͨĴͨš + +öʱʷʹ1Tģʽ(ǵͲ12T)ѡɱʱƵʣ߾ȡ + +ʱ, ѡʱ 22.1184MHz (ļ"config.h"޸). + + +/******************* IOú *******************/ + + +void GPIO1_config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; //ṹ + + GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + GPIO_InitStructure.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P3,&GPIO_InitStructure); //ʼ +} + +/*************** ڳʼ *****************/ +void UART1_config(void) +{ + COMx_InitDefine COMx_InitStructure; //ṹ + COMx_InitStructure.UART_Mode = UART_8bit_BRTx; //ģʽ, UART_ShiftRight,UART_8bit_BRTx,UART_9bit,UART_9bit_BRTx + COMx_InitStructure.UART_BRT_Use = BRT_Timer1; //ʹò, BRT_Timer1, BRT_Timer2 (ע: 2̶ʹBRT_Timer2) + COMx_InitStructure.UART_BaudRate = 115200; //, һ 110 ~ 115200 + COMx_InitStructure.UART_RxEnable = ENABLE; //, ENABLEDISABLE + COMx_InitStructure.BaudRateDouble = DISABLE; //ʼӱ, ENABLEDISABLE + COMx_InitStructure.UART_Interrupt = ENABLE; //ж, ENABLEDISABLE + COMx_InitStructure.UART_Priority = Priority_0; //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + COMx_InitStructure.UART_P_SW = UART1_SW_P30_P31; //л˿, UART1_SW_P30_P31,UART1_SW_P36_P37,UART1_SW_P16_P17,UART1_SW_P43_P44 + UART_Configuration(UART1, &COMx_InitStructure); //ʼ1 UART1,UART2,UART3,UART4 + + //PrintString1("STC8H8K64U UART1 Test Programme!\r\n"); //UART1һַ +} + +/********************WDT INT ********************/ +void WDT_config(void) +{ + WDT_InitTypeDef WDT_InitStructure; //ṹ + + WDT_InitStructure.WDT_Enable = ENABLE; //жʹ ENABLEDISABLE + WDT_InitStructure.WDT_IDLE_Mode = WDT_IDLE_STOP; //IDLEģʽǷֹͣ WDT_IDLE_STOP,WDT_IDLE_RUN + WDT_InitStructure.WDT_PS = WDT_SCALE_32; //ŹʱʱӷƵϵ WDT_SCALE_2,WDT_SCALE_4,WDT_SCALE_8,WDT_SCALE_16,WDT_SCALE_32,WDT_SCALE_64,WDT_SCALE_128,WDT_SCALE_256 + WDT_Inilize(&WDT_InitStructure); //ʼ +} + +u8 count_flag=0; +void main(void) +{ + GPIO_config(); + UART3_config(); + Start_Init(); + pwm_config(); + Timer2_Init_1ms(); + Key_Init(); + GPIO1_config(); + UART1_config(); + WDT_config(); //Ź629msλ + + PCON &= ~POF; //LVDжϱ־λ + RSTCFG = 0x41; //LVD:2.4Vѹλ + EA = 1; + + if(debug) + { + PrintString1("MCU Start"); + } + + while (1) + { + WDT_Clear(); //幷 + count_flag++; + + //Ϊ˱֤ijѹ2.2V + if(count_flag==1) + { + P10=1; + } + if(count_flag==8) + { + P10=0; + } + if(count_flag==10) + { + count_flag=0; + } + + Usart_judge_Data(); + + Usart_Deal_Data(); + + deal_command1(); + + deal_command2(); + +// checkpwm(); + + show_light(); + + Usart_answer(); + + Key_ScanTask(); + + KEY_TEST(); + + } +} + + + diff --git a/pwm_control.c b/pwm_control.c new file mode 100644 index 0000000..9b9fdf1 --- /dev/null +++ b/pwm_control.c @@ -0,0 +1,358 @@ +#include "pwm_control.h" +#include "GPIO.h" +#include "STC8xxxx.h" +#include "PWM15bit.h" +#include "timer.h" +#include "UART_Set.h" +#include "string.h" +S_PWM s_pwm; +/* +*1.5.0/5.1ijʼ +*2.ʼPWM +*3.LED_DRV_12V_ENõƬ +*/ +/******************* IOú *******************/ +void GPIO_config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; //ṹ + /***********************************1*******************************************/ + GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + GPIO_InitStructure.Mode = GPIO_PullUp; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P5,&GPIO_InitStructure); //ʼ + + /***********************************2*******************************************/ + GPIO_InitStructure.Pin = GPIO_Pin_All; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P0,&GPIO_InitStructure); //ʼ + + GPIO_InitStructure.Pin = GPIO_Pin_Left; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P2,&GPIO_InitStructure); //ʼ + + /***********************************3*******************************************/ + GPIO_InitStructure.Pin = GPIO_Pin_0; //ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7 + GPIO_InitStructure.Mode = GPIO_OUT_PP; //ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P1,&GPIO_InitStructure); //ʼ +} + +void pwm_config(void) +{ + u8 i; + PWM15_InitTypeDef PWM15_InitStructure; + + PWM15_InitStructure.PWM_Enable = ENABLE; //PWMʹ, ENABLE, DISABLE + PWM15_InitStructure.PWM_Period = 0x04E2; //PWM, 1250,ƵΪ16khz + PWM15_InitStructure.PWM_Clock_Sel = PWMn_CLK_SYS; //ʱԴѡ, PWMn_CLK_SYS, PWMn_CLK_TM2 + PWM15_InitStructure.PWM_Clock_PS = 0; //ϵͳʱӷƵ(PS+1Ƶ), 0~15 + PWM15_InitStructure.PWM_Counter = ENABLE; //ʹ, ENABLE, DISABLE + + PWM15_Init(PWM0,&PWM15_InitStructure); //ʼPWM0 + PWM15_Init(PWM2,&PWM15_InitStructure); //ʼPWM2 + + PWM15Duty(PWM00,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + PWM15Duty(PWM01,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + PWM15Duty(PWM02,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + PWM15Duty(PWM03,initial_Val); //PWM_ID, ͵ƽλ, ߵƽλ + PWM15Duty(PWM04,initial_Val); + PWM15Duty(PWM05,initial_Val); + PWM15Duty(PWM06,initial_Val); + PWM15Duty(PWM07,initial_Val); + + PWM15Duty(PWM20,initial_Val); + PWM15Duty(PWM21,initial_Val); + PWM15Duty(PWM22,initial_Val); + PWM15Duty(PWM23,initial_Val); + + memset(&s_pwm,0,sizeof(s_pwm)); + for(i=0;i<12;i++) + { + s_pwm.currpwm[i]=initial_Val; + } + PWMChannelCtrl(PWM00,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM01,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM02,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM03,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM04,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM05,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM06,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM07,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + + PWMChannelCtrl(PWM20,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM21,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM22,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + PWMChannelCtrl(PWM23,ENABLE,1,DISABLE,DISABLE,DISABLE); //PWM_ID, ʹ, ʼƽ, PWMж, ڶж, һж + +} + + +//10msһ +void deal_command1(void) +{ + int i=0; + static u32 systick_command1 = 0; + + if (systick_1ms - systick_command1 >= 10) + { + systick_command1 = systick_1ms; + for (i = 0; i < 12; i++) + { + if (s_recv.flag1[i]) + { + if (s_pwm.wanttopwm[i] > s_pwm.currpwm[i]) + { + //s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; + s_pwm.doublecurrpwm[i] += s_pwm.every_change_10ms[i]; + s_pwm.currpwm[i] = (u16)s_pwm.doublecurrpwm[i]; + + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + + if ( s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + { + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + } + } + + + //Ҫȴڵǰֵʱ + if (s_pwm.wanttopwm[i] < s_pwm.currpwm[i]) + { + //s_pwm.doublecurrpwm[i] = s_pwm.currpwm[i]; + s_pwm.doublecurrpwm[i] -= s_pwm.every_change_10ms[i]; + s_pwm.currpwm[i] = (u16)s_pwm.doublecurrpwm[i]; + + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + + if (s_pwm.currpwm[i] < s_pwm.wanttopwm[i] + s_pwm.every_change_10ms[i]) + { + s_pwm.currpwm[i] = 0; + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + } + } + + + if (s_pwm.wanttopwm[i] == s_pwm.currpwm[i]) + { + s_pwm.currvalue[i] = s_recv.B_Ch[i]; + s_recv.flag1[i] = 0; + } + } + } + } +} + +void deal_command2(void) +{ + int i=0; + static u32 systick_command2 = 0; + if (systick_1ms - systick_command2 >= 10) + { + systick_command2 = systick_1ms; + for (i = 0; i < 12; i++) + { + if (s_recv.flag2[i]) + { + switch (s_recv.mode[i]) + { + //ֹͣģʽ + case 0x00: + //Ƚ + if (s_recv.forward[i] == 0x00) + { + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_min * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + s_pwm.currpwm[i] += s_recv.pwm_step[i]; + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + if (s_pwm.currpwm[i] >= s_pwm.wanttopwm[i]) + { + s_recv.flag2[i] = 0; + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + s_pwm.currvalue[i] = s_recv.B_min; //ڻظ + } + } + // + if (s_recv.forward[i] == 0x01) + { + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_max * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + if (s_pwm.currpwm[i] <= s_pwm.wanttopwm[i] + s_recv.pwm_step[i]) + { + s_recv.flag2[i] = 0; + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + s_pwm.currvalue[i] = s_recv.B_max; + } + else + { + s_pwm.currpwm[i] -= s_recv.pwm_step[i]; + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + } + } + break; + + //˫ѭģʽ + case 0x01: + //ݼ + if (s_recv.forward[i] == 0x00) + { + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_min * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + s_pwm.currpwm[i] += s_recv.pwm_step[i]; + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + if (s_pwm.currpwm[i] >= s_pwm.wanttopwm[i]) + { + s_recv.forward[i] = 0x01; + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + s_pwm.currvalue[i] = s_recv.B_min; //ڻظ + } + } + // + if (s_recv.forward[i] == 0x01) + { + s_pwm.wanttopwm[i] = PWM_MAX_VALUE - s_recv.B_max * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100 * s_recv.key_status[i]; + if (s_pwm.currpwm[i] <= s_pwm.wanttopwm[i] + s_recv.pwm_step[i]) + { + s_recv.forward[i] = 0x00; + s_pwm.currpwm[i] = s_pwm.wanttopwm[i]; + s_pwm.currvalue[i] = s_recv.B_max; + } + else + { + s_pwm.currpwm[i] -= s_recv.pwm_step[i]; + if(s_recv.global_brightness==0) + { + s_pwm.currvalue[i]=0; + } + else + { + s_pwm.currvalue[i] = (PWM_MAX_VALUE - s_pwm.currpwm[i]) * 100 * 100 / PWM_MAX_VALUE / s_recv.global_brightness; + } + } + } + break; + case 0x02: + //ֹͣ + s_recv.flag2[i] = 0; + break; + } + } + } + } +} + + +//ֱӹص,¼״̬ +void Close_Light(u8 i) +{ + s_pwm.currpwm[i]=20001ul; //ߵƽdz⣬ +} + +//򿪵ʱظԭ +void Open_Light(u8 pin) +{ + s_pwm.currpwm[pin] = PWM_MAX_VALUE - s_pwm.currvalue[pin] * PWM_MAX_VALUE * s_recv.global_brightness / 100 / 100; +} + +void PWM_write(u8 i, u16 Val) +{ + switch (i) + { + case 0: + PWM15Duty(PWM07,Val); + break; + case 1: + PWM15Duty(PWM06,Val); + break; + case 2: + PWM15Duty(PWM05,Val); + break; + case 3: + PWM15Duty(PWM04,Val); + break; + case 4: + PWM15Duty(PWM03,Val); + break; + case 5: + PWM15Duty(PWM02,Val); + break; + case 6: + PWM15Duty(PWM01,Val); + break; + case 7: + PWM15Duty(PWM00,Val); + break; + case 8: + PWM15Duty(PWM23,Val); + break; + case 9: + PWM15Duty(PWM22,Val); + break; + case 10: + PWM15Duty(PWM21,Val); + break; + case 11: + PWM15Duty(PWM20,Val); + break; + } +} +void show_light(void) +{ + int i; + for (i = 0; i < 12; i++) + { + if(s_pwm.currpwm[i]==20000ul) + { + Close_Light(i); + } + else + { + PWM_write(i, s_pwm.currpwm[i]); + } + } +} + +//void checkpwm(void) +//{ +// int i; +// for (i = 0; i < 12; i++) +// { +// if ((s_recv.flag1[i] == 0) && (s_recv.flag2[i] == 0) && (s_recv.changeflag == 1)) +// { +// if (s_pwm.wanttopwmflash[i] != s_pwm.currpwm[i]) +// { +// s_pwm.currpwm[i] = s_pwm.wanttopwmflash[i]; +// } +// } +// } +// s_recv.changeflag = 0; +//} diff --git a/pwm_control.h b/pwm_control.h new file mode 100644 index 0000000..9a43492 --- /dev/null +++ b/pwm_control.h @@ -0,0 +1,51 @@ +#ifndef PWM_CONTROL_H +#define PWM_CONTROL_H + +#include "STC8xxxx.h" + +#define PWM_MAX_VALUE 1250ul +#define initial_Val 1251ul +/* +#define LED_DRV_CH1 P07 +#define LED_DRV_CH2 P06 +#define LED_DRV_CH3 P05 +#define LED_DRV_CH4 P04 +#define LED_DRV_CH5 P03 +#define LED_DRV_CH6 P02 +#define LED_DRV_CH7 P01 +#define LED_DRV_CH8 P00 +#define LED_DRV_CH9 P23 +#define LED_DRV_CH10 P22 +#define LED_DRV_CH11 P21 +#define LED_DRV_CH12 P20 +*/ +#define LED_DRV_12V_EN P10 + +typedef struct +{ + u16 currpwm[12]; + u16 thenvalue[12]; + float doublecurrpwm[12]; + u16 wanttopwm[12]; + u16 currvalue[12]; //ǰٷֱֵ + u16 changetime[12]; + u16 wanttovalue[12]; + float every_change_10ms[12]; +// u16 wanttopwmflash[12]; + u8 key_value; +}xdata S_PWM; + +extern S_PWM s_pwm; + +void Close_Light(u8 pin); +void Open_Light(u8 pin); +void PWM_write(u8 i, u16 pwm); +void deal_command1(void); +void deal_command2(void); +void show_light(void); +void checkpwm(void); + +void GPIO_config(void); +void pwm_config(void); + +#endif \ No newline at end of file diff --git a/timer.c b/timer.c new file mode 100644 index 0000000..ab3f578 --- /dev/null +++ b/timer.c @@ -0,0 +1,160 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +/************* ˵ ************** + +ļΪSTC8ϵеĶʱʼжϳ,ûļ޸ԼҪжϳ. + +******************************************/ + +#include "timer.h" +u32 systick_1ms=0; +/********************* Timer0жϺ************************/ +void timer0_int (void) interrupt TIMER0_VECTOR +{ + P67 = ~P67; +} + +/********************* Timer1жϺ************************/ +void timer1_int (void) interrupt TIMER1_VECTOR +{ + P66 = ~P66; +} + +/********************* Timer2жϺ************************/ +void timer2_int (void) interrupt TIMER2_VECTOR +{ + systick_1ms++; +} + +/********************* Timer3жϺ************************/ +void timer3_int (void) interrupt TIMER3_VECTOR +{ + +} + +/********************* Timer4жϺ************************/ +void timer4_int (void) interrupt TIMER4_VECTOR +{ + P63 = ~P63; +} + + +//======================================================================== +// : u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) +// : ʱʼ. +// : TIMx: ṹ,οtimer.hĶ. +// : ɹ0, ղ1,󷵻2. +// 汾: V1.0, 2012-10-22 +//======================================================================== +u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) +{ + if(TIM > Timer4) return 1; //ղ + + if(TIM == Timer0) + { + Timer0_Stop(); //ֹͣ + if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ж + else Timer0_InterruptDisable(); //ֹж + if(TIMx->TIM_Priority > Priority_3) return 2; // + Timer0_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + + if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; // + TMOD = (TMOD & ~0x30) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //Ƶ + else Timer0_AsTimer(); //ʱ + if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //ʱ + else Timer0_CLKO_Disable(); //ʱ + + T0_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //ʼ + return 0; //ɹ + } + + if(TIM == Timer1) + { + Timer1_Stop(); //ֹͣ + if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ж + else Timer1_InterruptDisable(); //ֹж + if(TIMx->TIM_Priority > Priority_3) return 2; // + Timer1_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3 + if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; // + TMOD = (TMOD & ~0x30) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //Ƶ + else Timer1_AsTimer(); //ʱ + if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //ʱ + else Timer1_CLKO_Disable(); //ʱ + + T1_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //ʼ + return 0; //ɹ + } + + if(TIM == Timer2) //Timer2,̶Ϊ16λԶװ, жȼ + { + Timer2_Stop(); //ֹͣ + if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ж + else Timer2_InterruptDisable(); //ֹж + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //Ƶ + else Timer2_AsTimer(); //ʱ + if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //ʱ + else Timer2_CLKO_Disable(); //ʱ + + T2_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //ʼ + return 0; //ɹ + } + + if(TIM == Timer3) //Timer3,̶Ϊ16λԶװ, жȼ + { + Timer3_Stop(); //ֹͣ + if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ж + else Timer3_InterruptDisable(); //ֹж + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //Ƶ + else Timer3_AsTimer(); //ʱ + if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //ʱ + else Timer3_CLKO_Disable(); //ʱ + + T3_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //ʼ + return 0; //ɹ + } + + if(TIM == Timer4) //Timer3,̶Ϊ16λԶװ, жȼ + { + Timer4_Stop(); //ֹͣ + if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ж + else Timer4_InterruptDisable(); //ֹж + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //Ƶ + else Timer4_AsTimer(); //ʱ + if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //ʱ + else Timer4_CLKO_Disable(); //ʱ + + T4_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //ʼ + return 0; //ɹ + } + return 2; // +} diff --git a/timer.h b/timer.h new file mode 100644 index 0000000..c760f94 --- /dev/null +++ b/timer.h @@ -0,0 +1,47 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Ҫڳʹô˴,ڳעʹSTCϼ */ +/*---------------------------------------------------------------------*/ + +#ifndef __TIMER_H +#define __TIMER_H + +#include "config.h" + +#define Timer0 0 +#define Timer1 1 +#define Timer2 2 +#define Timer3 3 +#define Timer4 4 + +#define TIM_16BitAutoReload 0 +#define TIM_16Bit 1 +#define TIM_8BitAutoReload 2 +#define TIM_16BitAutoReloadNoMask 3 + +#define TIM_CLOCK_1T 0 +#define TIM_CLOCK_12T 1 +#define TIM_CLOCK_Ext 2 + +typedef struct +{ + u8 TIM_Mode; //ģʽ, TIM_16BitAutoReload,TIM_16Bit,TIM_8BitAutoReload,TIM_16BitAutoReloadNoMask + u8 TIM_Priority; //ȼ Priority_0,Priority_1,Priority_2,Priority_3 + u8 TIM_Interrupt; //ж ENABLE,DISABLE + u8 TIM_ClkSource; //ʱԴ TIM_CLOCK_1T,TIM_CLOCK_12T,TIM_CLOCK_Ext + u8 TIM_ClkOut; //ɱʱ, ENABLE,DISABLE + u16 TIM_Value; //װسֵ + u8 TIM_Run; //Ƿ ENABLE,DISABLE +} TIM_InitTypeDef; + +extern u32 systick_1ms; +u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx); + +#endif