2026-01-05 09:40:42 +08:00
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/*
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* uart.c
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*
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* Created on: May 14, 2025
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* Author: cc
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*
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* Ŀǰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> RS485<EFBFBD><EFBFBD>
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*
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* Uart1 -> <EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD>
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* Uart0 -> U1 -> RS485 1
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* UART2 -> U2 -> RS485 2
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* Uart3 -> U3 -> BUS
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*
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*/
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#include "includes.h"
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#include <string.h>
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2026-01-19 16:39:22 +08:00
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/* Bootload <20>й滮<D0B9><E6BBAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2026-02-10 17:48:22 +08:00
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* 1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD>1
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2026-01-19 16:39:22 +08:00
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* 2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
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* - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD>
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*/
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2026-02-10 17:48:22 +08:00
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UART_t g_uart_1;
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2026-01-19 16:39:22 +08:00
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UART_t g_uart_2;
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2026-01-05 09:40:42 +08:00
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void UART0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void UART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void UART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void UART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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/*********************************************************************
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* @fn UARTx_Init
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* @brief UART<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD><EFBFBD>2ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PB22,PB23 - Boot,RST<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* @param uart_id - <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ID
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* @param buad - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* @param prt_cf - <EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><EFBFBD>ջص<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* @return none
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*/
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void UARTx_Init(UART_IDX uart_id, uint32_t buad) {
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switch (uart_id) {
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case UART_0:
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//RS485ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
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GPIOD_ModeCfg(GPIO_Pin_21, GPIO_ModeOut_PP);
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MCU485_EN1_L;
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UART0_Reset();
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GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE);
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GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP);
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GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating);
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UART0_BaudRateCfg(buad);
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2026-02-10 17:48:22 +08:00
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R8_UART0_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
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// FIFO open, trigger point 1 bytes
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2026-01-05 09:40:42 +08:00
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R8_UART0_LCR = RB_LCR_WORD_SZ;
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R8_UART0_IER = RB_IER_TXD_EN;
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UART0_CLR_RXFIFO();
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UART0_CLR_TXFIFO();
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UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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NVIC_EnableIRQ(UART0_IRQn);
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break;
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case UART_1:
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UART1_Reset();
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GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE);
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GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP);
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GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating);
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UART1_BaudRateCfg(buad);
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2026-02-10 17:48:22 +08:00
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R8_UART1_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
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// FIFO open, trigger point 1 bytes
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2026-01-05 09:40:42 +08:00
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R8_UART1_LCR = RB_LCR_WORD_SZ;
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R8_UART1_IER = RB_IER_TXD_EN;
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UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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NVIC_EnableIRQ(UART1_IRQn);
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2026-02-10 17:48:22 +08:00
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memset(&g_uart_1,0,sizeof(UART_t));
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Set_Uart_recvTimeout(&g_uart_1,buad);
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g_uart_1.send_data_cf = MCU485_SendString_1;
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g_uart_1.set_baud_cf = UART1_ChangeBaud;
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2026-01-05 09:40:42 +08:00
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break;
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case UART_2:
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//RS485ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
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2026-02-10 17:48:22 +08:00
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GPIOB_ModeCfg(GPIO_Pin_15, GPIO_ModeOut_PP); //RS485<38><35><EFBFBD>ų<EFBFBD>ʼ<EFBFBD><CABC> - <20><><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD> RS485 ʹ<><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2026-01-05 09:40:42 +08:00
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MCU485_EN2_L;
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UART2_Reset();
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GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE);
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GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP);
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GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating);
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2026-02-10 17:48:22 +08:00
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2026-01-05 09:40:42 +08:00
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UART2_BaudRateCfg(buad);
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2026-02-10 17:48:22 +08:00
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R8_UART2_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
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// FIFO open, trigger point 1 bytes
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2026-01-05 09:40:42 +08:00
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R8_UART2_LCR = RB_LCR_WORD_SZ;
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R8_UART2_IER = RB_IER_TXD_EN;
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UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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NVIC_EnableIRQ(UART2_IRQn);
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2026-01-19 16:39:22 +08:00
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memset(&g_uart_2,0,sizeof(UART_t));
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2026-02-10 17:48:22 +08:00
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g_uart_2.CommBaud = buad;
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2026-01-19 16:39:22 +08:00
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Set_Uart_recvTimeout(&g_uart_2,buad);
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2026-01-05 09:40:42 +08:00
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2026-01-19 16:39:22 +08:00
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g_uart_2.send_data_cf = MCU485_SendString_2;
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g_uart_2.set_baud_cf = UART2_ChangeBaud;
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2026-01-05 09:40:42 +08:00
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break;
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case UART_3:
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UART3_Reset();
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GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE);
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GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP);
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GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating);
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UART3_BaudRateCfg(buad);
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2026-02-10 17:48:22 +08:00
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R8_UART3_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
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// FIFO open, trigger point 1 bytes
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2026-01-05 09:40:42 +08:00
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R8_UART3_LCR = RB_LCR_WORD_SZ;
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R8_UART3_IER = RB_IER_TXD_EN;
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UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
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NVIC_EnableIRQ(UART3_IRQn);
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break;
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}
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}
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void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud)
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{
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if(baud == 115200)
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{
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set_uart->RecvTimeout = Recv_115200_TimeOut;
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}else if(baud == 9600)
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{
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set_uart->RecvTimeout = Recv_9600_TimeOut;
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}else if(baud == 2400)
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{
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set_uart->RecvTimeout = Recv_2400_TimeOut;
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}else if(baud == 512000)
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{
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set_uart->RecvTimeout = Recv_512000_TimeOut;
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}else
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{
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set_uart->RecvTimeout = 20;
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}
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}
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/*********************************************************************
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* @fn USART1_IRQHandler
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*
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* @brief USART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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void UART0_IRQHandler(void)
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{
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switch( UART0_GetITFlag() )
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{
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case UART_II_THR_EMPTY:
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break;
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case UART_II_RECV_RDY:
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case UART_II_RECV_TOUT:
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break;
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}
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}
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/*********************************************************************
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* @fn USART1_IRQHandler
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*
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* @brief USART1<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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void UART1_IRQHandler(void)
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{
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switch( UART1_GetITFlag() )
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{
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case UART_II_THR_EMPTY:
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break;
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case UART_II_RECV_RDY:
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case UART_II_RECV_TOUT:
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2026-02-10 17:48:22 +08:00
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if( (g_uart_1.RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart_1.RecvLen = 0x00;
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g_uart_1.RecvBuffer[g_uart_1.RecvLen] = UART1_RecvByte();
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g_uart_1.RecvLen += 1;
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g_uart_1.Receiving = 0x01;
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g_uart_1.RecvIdleTiming = SysTick_1ms;
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2026-01-05 09:40:42 +08:00
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break;
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}
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}
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/*********************************************************************
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* @fn UART2_IRQHandler
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*
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* @brief USART2<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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void UART2_IRQHandler(void)
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{
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switch( UART2_GetITFlag() )
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{
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case UART_II_THR_EMPTY:
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break;
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case UART_II_RECV_RDY:
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case UART_II_RECV_TOUT:
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2026-01-19 16:39:22 +08:00
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if( (g_uart_2.RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart_2.RecvLen = 0x00;
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g_uart_2.RecvBuffer[g_uart_2.RecvLen] = UART2_RecvByte();
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g_uart_2.RecvLen += 1;
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g_uart_2.Receiving = 0x01;
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g_uart_2.RecvIdleTiming = SysTick_1ms;
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2026-01-05 09:40:42 +08:00
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break;
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}
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}
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/*********************************************************************
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* @fn USART3_IRQHandler
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*
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* @brief USART3<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD>
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*
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* @return none
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*/
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void UART3_IRQHandler(void)
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{
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switch( UART3_GetITFlag() )
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{
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case UART_II_THR_EMPTY:
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break;
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case UART_II_RECV_RDY:
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case UART_II_RECV_TOUT:
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2026-02-10 17:48:22 +08:00
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2026-01-05 09:40:42 +08:00
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break;
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}
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|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn USART1_RECEIVE
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief USART1
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
void UART0_RECEIVE(void)
|
|
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if(g_uart_0.Receiving == 0x01)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if(SysTick_1ms - g_uart_0.RecvIdleTiming >= g_uart_0.RecvTimeout)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
g_uart_0.RecvIdleTiming = SysTick_1ms;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
DBG_SYS_Printf("UART0_RECEIVE");
|
|
|
|
|
|
Launcher_Uart_Upgrade_Process(&g_uart_0);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
g_uart_0.RecvLen = 0;
|
|
|
|
|
|
g_uart_0.Receiving = 0;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn USART1_RECEIVE
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief USART1
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
void UART1_RECEIVE(void)
|
|
|
|
|
|
{
|
2026-02-10 17:48:22 +08:00
|
|
|
|
if(g_uart_1.Receiving == 0x01)
|
|
|
|
|
|
{
|
|
|
|
|
|
if(SysTick_1ms - g_uart_1.RecvIdleTiming >= g_uart_1.RecvTimeout)
|
|
|
|
|
|
{
|
|
|
|
|
|
g_uart_1.RecvIdleTiming = SysTick_1ms;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
DBG_SYS_Printf("UART1_RECEIVE");
|
|
|
|
|
|
Launcher_Uart_Upgrade_Process(&g_uart_1);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
g_uart_1.RecvLen = 0;
|
|
|
|
|
|
g_uart_1.Receiving = 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn UART2_RECEIVE
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief USART2
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
void UART2_RECEIVE(void)
|
|
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if(g_uart_2.Receiving == 1)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if(SysTick_1ms - g_uart_2.RecvIdleTiming > g_uart_2.RecvTimeout)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
g_uart_2.RecvIdleTiming = SysTick_1ms;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
DBG_SYS_Printf("UART2_RECEIVE");
|
|
|
|
|
|
Launcher_Uart_Upgrade_Process(&g_uart_2);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
g_uart_2.RecvLen = 0;
|
|
|
|
|
|
g_uart_2.Receiving = 0;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn USART3_RECEIVE
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief UART3
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
void UART3_RECEIVE(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn UART0_ChangeBaud
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief UART0<EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
uint8_t UART0_ChangeBaud(uint32_t baudrate)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint16_t delay_num = 0;
|
|
|
|
|
|
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
|
|
|
|
|
if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
|
|
|
|
|
{
|
|
|
|
|
|
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
|
|
|
|
|
__disable_irq();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
// UART0_Reset();
|
|
|
|
|
|
//
|
|
|
|
|
|
// GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE);
|
|
|
|
|
|
// GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP);
|
|
|
|
|
|
// GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
UART0_BaudRateCfg(baudrate);
|
2026-02-10 17:48:22 +08:00
|
|
|
|
// R8_UART0_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
|
|
|
|
|
// // FIFO open, trigger point 14 bytes
|
|
|
|
|
|
// R8_UART0_LCR = RB_LCR_WORD_SZ;
|
|
|
|
|
|
// R8_UART0_IER = RB_IER_TXD_EN;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
UART0_CLR_RXFIFO();
|
|
|
|
|
|
UART0_CLR_TXFIFO();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
// UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
|
|
|
|
|
// NVIC_EnableIRQ(UART0_IRQn);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
Set_Uart_recvTimeout(&g_uart_0,baudrate);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
__enable_irq();
|
|
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Delay_Us(100);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 500) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn UART1_ChangeBaud
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief UART1<EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
uint8_t UART1_ChangeBaud(uint32_t baudrate)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint16_t delay_num = 0;
|
|
|
|
|
|
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( UART1_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
|
|
|
|
|
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
|
|
|
|
|
__disable_irq();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
NVIC_DisableIRQ(UART1_IRQn);
|
|
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
UART1_Reset();
|
|
|
|
|
|
|
|
|
|
|
|
GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating);
|
|
|
|
|
|
|
|
|
|
|
|
UART1_BaudRateCfg(baudrate);
|
2026-02-10 17:48:22 +08:00
|
|
|
|
R8_UART1_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
|
|
|
|
|
// FIFO open, trigger point 1 bytes
|
2026-01-05 09:40:42 +08:00
|
|
|
|
R8_UART1_LCR = RB_LCR_WORD_SZ;
|
|
|
|
|
|
R8_UART1_IER = RB_IER_TXD_EN;
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
UART1_CLR_RXFIFO();
|
|
|
|
|
|
UART1_CLR_TXFIFO();
|
|
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
|
|
|
|
|
NVIC_EnableIRQ(UART1_IRQn);
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
Set_Uart_recvTimeout(&g_uart_1,baudrate);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
__enable_irq();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Delay_Us(100);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 500) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn UART2_ChangeBaud
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief UART2<EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
uint8_t UART2_ChangeBaud(uint32_t baudrate)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint16_t delay_num = 0;
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
DBG_SYS_Printf("%s - %d",__func__,baudrate);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( UART2_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
|
|
|
|
|
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
|
|
|
|
|
__disable_irq();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
NVIC_DisableIRQ(UART2_IRQn);
|
|
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
UART2_Reset();
|
|
|
|
|
|
|
|
|
|
|
|
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating);
|
|
|
|
|
|
|
|
|
|
|
|
UART2_BaudRateCfg(baudrate);
|
2026-02-10 17:48:22 +08:00
|
|
|
|
R8_UART2_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
|
|
|
|
|
// FIFO open, trigger point 1 bytes
|
2026-01-05 09:40:42 +08:00
|
|
|
|
R8_UART2_LCR = RB_LCR_WORD_SZ;
|
|
|
|
|
|
R8_UART2_IER = RB_IER_TXD_EN;
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
UART2_CLR_RXFIFO();
|
|
|
|
|
|
UART2_CLR_TXFIFO();
|
|
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
2026-02-10 17:48:22 +08:00
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
NVIC_EnableIRQ(UART2_IRQn);
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
Set_Uart_recvTimeout(&g_uart_2,baudrate);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
__enable_irq();
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
DBG_SYS_Printf("%s - SUCC",__func__);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Delay_Us(100);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 500) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
|
|
* @fn UART3_ChangeBaud
|
|
|
|
|
|
*
|
|
|
|
|
|
* @brief UART3<EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return none
|
|
|
|
|
|
*/
|
|
|
|
|
|
uint8_t UART3_ChangeBaud(uint32_t baudrate)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint16_t delay_num = 0;
|
|
|
|
|
|
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( UART3_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
|
|
|
|
|
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
|
|
|
|
|
__disable_irq();
|
|
|
|
|
|
|
|
|
|
|
|
UART3_Reset();
|
|
|
|
|
|
|
|
|
|
|
|
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP);
|
|
|
|
|
|
GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating);
|
|
|
|
|
|
|
|
|
|
|
|
UART3_BaudRateCfg(baudrate);
|
2026-02-10 17:48:22 +08:00
|
|
|
|
R8_UART3_FCR = RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
|
|
|
|
|
// FIFO open, trigger point 1 bytes
|
2026-01-05 09:40:42 +08:00
|
|
|
|
R8_UART3_LCR = RB_LCR_WORD_SZ;
|
|
|
|
|
|
R8_UART3_IER = RB_IER_TXD_EN;
|
|
|
|
|
|
|
|
|
|
|
|
UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
|
|
|
|
|
NVIC_EnableIRQ(UART3_IRQn);
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
//Set_Uart_recvTimeout(&g_uart[UART_3],baudrate);
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
__enable_irq();
|
|
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
Delay_Us(100);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 500) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* RS485ͨѶ<EFBFBD><EFBFBD><EFBFBD>ϼ<EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* 1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݺȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><EFBFBD><EFBFBD>(<EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD>ͬ<EFBFBD>IJ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD><EFBFBD>ȴ<EFBFBD>ʱ<EFBFBD>䲻ͬ),<EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* 2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݺȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
|
|
|
|
|
|
* 3<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><EFBFBD>пɽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><EFBFBD>ͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>߷<EFBFBD>æ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* 4<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD><EFBFBD>ͣ<EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>¼<EFBFBD><EFBFBD>ǰʱ<EFBFBD>䣬<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD>ں<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ㲻<EFBFBD>ڷ<EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* 5<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* - 1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>æ״̬
|
|
|
|
|
|
* - 2<EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* - 3<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<EFBFBD><EFBFBD>
|
|
|
|
|
|
*
|
|
|
|
|
|
* */
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uint8_t MCU485_SendString_0(uint8_t *buff, uint16_t len)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
|
|
|
|
|
uint32_t delay_num = 0;
|
|
|
|
|
|
|
|
|
|
|
|
UART0_SendString(buff,len);
|
|
|
|
|
|
|
|
|
|
|
|
//<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 50ms
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
|
|
|
|
|
if((R8_UART0_LSR & RB_LSR_TX_ALL_EMP)) break;
|
|
|
|
|
|
Delay_Us(1);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 50000) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-02-10 17:48:22 +08:00
|
|
|
|
uint8_t MCU485_SendString_1(uint8_t *buff, uint16_t len)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint32_t delay_num = 0;
|
|
|
|
|
|
|
|
|
|
|
|
UART1_SendString(buff,len);
|
|
|
|
|
|
|
|
|
|
|
|
//<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 50ms
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
|
|
|
|
|
if((R8_UART1_LSR & RB_LSR_TX_ALL_EMP)) break;
|
|
|
|
|
|
Delay_Us(1);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 50000) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-01-05 09:40:42 +08:00
|
|
|
|
uint8_t MCU485_SendString_2(uint8_t *buff, uint16_t len)
|
|
|
|
|
|
{
|
|
|
|
|
|
uint32_t delay_num = 0;
|
|
|
|
|
|
MCU485_EN2_H;
|
|
|
|
|
|
|
|
|
|
|
|
UART2_SendString(buff,len);
|
|
|
|
|
|
|
|
|
|
|
|
//<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 50ms
|
|
|
|
|
|
while(1)
|
|
|
|
|
|
{
|
|
|
|
|
|
if((R8_UART2_LSR & RB_LSR_TX_ALL_EMP)) break;
|
|
|
|
|
|
Delay_Us(1);
|
|
|
|
|
|
delay_num++;
|
|
|
|
|
|
if(delay_num > 50000) break;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MCU485_EN2_L;
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
|
|
* Function Name : Uart0_Add_Data_To_SendBuff
|
|
|
|
|
|
* Description : Uart0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뷢<EFBFBD>ͻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* Input :
|
2026-01-19 16:39:22 +08:00
|
|
|
|
* uart_info<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2026-01-05 09:40:42 +08:00
|
|
|
|
buff<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
len<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
sendCount <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
ValidDuration <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<EFBFBD>䣬<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>ms
|
|
|
|
|
|
sendInterval <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͼ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>䣬<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>ms
|
|
|
|
|
|
*******************************************************************************/
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uint8_t Uartx_Add_Data_To_SendBuff(
|
|
|
|
|
|
UART_t *uart_info,
|
|
|
|
|
|
uint8_t *buff,
|
|
|
|
|
|
uint16_t len,
|
|
|
|
|
|
uint8_t sendCount,
|
|
|
|
|
|
uint32_t ValidDuration,
|
|
|
|
|
|
uint32_t sendInterval)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info == NULL ) return 0x01;
|
|
|
|
|
|
if( buff == NULL ) return 0x01;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
if( len > USART_BUFFER_SIZE ) return 0x02;
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
memset(uart_info->SendBuffer,0,USART_BUFFER_SIZE);
|
|
|
|
|
|
memcpy(uart_info->SendBuffer,buff,len);
|
|
|
|
|
|
uart_info->SendLen = len;
|
|
|
|
|
|
uart_info->SendCount = sendCount;
|
|
|
|
|
|
uart_info->SendCnt = 0;
|
|
|
|
|
|
uart_info->SendValidDuration = ValidDuration;
|
|
|
|
|
|
uart_info->SendInterval = sendInterval;
|
|
|
|
|
|
uart_info->SendValidTick = SysTick_1ms;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
|
|
* Function Name : Uart0_Clear_SendBuff
|
|
|
|
|
|
* Description : Uart0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱȡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*******************************************************************************/
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uint8_t Uartx_Clear_SendBuff(UART_t *uart_info)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info == NULL ) return 0x01;
|
|
|
|
|
|
|
|
|
|
|
|
memset(uart_info->SendBuffer,0,USART_BUFFER_SIZE);
|
|
|
|
|
|
uart_info->SendLen = 0x00;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
|
|
* Function Name : Uart0_Avoid_Conflict_Send_Task
|
|
|
|
|
|
* Description : Uart0 <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
*******************************************************************************/
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uint8_t Uartx_Avoid_Conflict_Send_Task(UART_t *uart_info)
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info == NULL ) return 0x01;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( (uart_info->SendLen == 0x00) || (uart_info->SendLen > USART_BUFFER_SIZE) ) return 0x01;
|
|
|
|
|
|
|
|
|
|
|
|
if( uart_info->SendCnt >= uart_info->SendCount ) {
|
2026-01-05 09:40:42 +08:00
|
|
|
|
//<2F><><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﵽ<EFBFBD><EFB5BD><EFBFBD>ޣ<EFBFBD><DEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uart_info->SendLen = 0x00;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
return 0x02;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( SysTick_1ms - uart_info->SendValidTick >= uart_info->SendInterval ){
|
2026-01-05 09:40:42 +08:00
|
|
|
|
//<2F><><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>Ч<EFBFBD>ڣ<EFBFBD><DAA3>㲻<EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uart_info->SendLen = 0x00;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
return 0x03;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info->CommBusy != UART_COMMBUSY_IDLE_Flag ) return 0x04; //ͨѶ<CDA8><D1B6><EFBFBD>ڷ<EFBFBD>æ״̬
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
//<2F><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( ( uart_info->SendCnt == 0x00 ) || ( SysTick_1ms - uart_info->SendTick >= uart_info->SendInterval ) )
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
|
|
|
|
|
__disable_irq(); //<2F>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
2026-01-19 16:39:22 +08:00
|
|
|
|
uart_info->CommBusy |= UART_COMMBUSY_SEND_Flag;
|
|
|
|
|
|
uart_info->SendIdleTick = SysTick_1ms;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
__enable_irq(); //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info->send_data_cf != NULL ){
|
|
|
|
|
|
uart_info->send_data_cf(uart_info->SendBuffer, uart_info->SendLen);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uart_info->SendTick = SysTick_1ms;
|
|
|
|
|
|
uart_info->SendCnt++;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
if( uart_info->SendCnt >= uart_info->SendCount )
|
2026-01-05 09:40:42 +08:00
|
|
|
|
{
|
2026-01-19 16:39:22 +08:00
|
|
|
|
memset(uart_info->SendBuffer,0,USART_BUFFER_SIZE);
|
|
|
|
|
|
uart_info->SendLen = 0x00;
|
2026-01-05 09:40:42 +08:00
|
|
|
|
|
|
|
|
|
|
return 0x05; //ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return 0x00;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2026-01-19 16:39:22 +08:00
|
|
|
|
/*******************************************************************************
|
|
|
|
|
|
* Function Name : Uartx_IDLE_State_Determination
|
|
|
|
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* Description : Uartx <EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD>ж<EFBFBD>
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*******************************************************************************/
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void Uartx_IDLE_State_Determination(UART_t *uart_info)
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2026-01-05 09:40:42 +08:00
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{
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2026-01-19 16:39:22 +08:00
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if( uart_info->CommBusy == UART_COMMBUSY_IDLE_Flag )
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2026-01-05 09:40:42 +08:00
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{
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/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>״̬ - <20><><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʲ<EFBFBD><CAB2><EFBFBD>*/
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2026-01-19 16:39:22 +08:00
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if( uart_info->ChangeBaudFlag == 0x01 )
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2026-01-05 09:40:42 +08:00
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{
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2026-01-19 16:39:22 +08:00
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uart_info->set_baud_cf(uart_info->CommBaud);
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uart_info->ChangeBaudFlag = 0x00;
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2026-01-05 09:40:42 +08:00
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}
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}else {
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/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD>ڷ<EFBFBD><DAB7>ͷ<EFBFBD>æ״̬<D7B4><CCAC><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>״̬ - <20>ж<EFBFBD>ʹ<EFBFBD>ó<EFBFBD>ʱʱ<CAB1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD>ʱʱ<CAB1><CAB1>һ<EFBFBD><D2BB>*/
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2026-01-19 16:39:22 +08:00
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if( ((uart_info->CommBusy & UART_COMMBUSY_SEND_Flag) != 0x00 ) && ( SysTick_1ms - uart_info->SendIdleTick >= uart_info->RecvTimeout ) )
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2026-01-05 09:40:42 +08:00
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{
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2026-01-19 16:39:22 +08:00
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uart_info->SendIdleTick = SysTick_1ms;
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2026-01-05 09:40:42 +08:00
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__disable_irq(); //<2F>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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2026-01-19 16:39:22 +08:00
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uart_info->CommBusy &= ~(UART_COMMBUSY_SEND_Flag);
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uart_info->SendIdleTick = SysTick_1ms;
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2026-01-05 09:40:42 +08:00
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__enable_irq(); //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
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}
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}
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2026-01-19 16:39:22 +08:00
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}
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void Uart0_Task(void)
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{
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2026-02-10 17:48:22 +08:00
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// UART0_RECEIVE();
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//
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// Uartx_Avoid_Conflict_Send_Task(&g_uart_0);
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//
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// Uartx_IDLE_State_Determination(&g_uart_0);
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}
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void Uart1_Task(void)
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{
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UART1_RECEIVE();
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2026-01-05 09:40:42 +08:00
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2026-02-10 17:48:22 +08:00
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Uartx_Avoid_Conflict_Send_Task(&g_uart_1);
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2026-01-19 16:39:22 +08:00
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2026-02-10 17:48:22 +08:00
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Uartx_IDLE_State_Determination(&g_uart_1);
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2026-01-05 09:40:42 +08:00
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}
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2026-01-19 16:39:22 +08:00
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void Uart2_Task(void)
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{
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UART2_RECEIVE();
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Uartx_Avoid_Conflict_Send_Task(&g_uart_2);
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2026-01-05 09:40:42 +08:00
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2026-01-19 16:39:22 +08:00
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Uartx_IDLE_State_Determination(&g_uart_2);
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}
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2026-01-05 09:40:42 +08:00
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