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169
.cproject
Normal file
169
.cproject
Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
|
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<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
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||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
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<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release" postbuildStep=" ${cross_prefix}${cross_objcopy}${cross_suffix} -O ihex "${ProjName}.elf" "${ProjName}.hex" && ${cross_prefix}${cross_objcopy}${cross_suffix} -O binary "${ProjName}.elf" "${ProjName}.bin"">
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<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074." name="/" resourcePath="">
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<toolChain id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release.231146001" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release">
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash.1311852988" name="Create flash image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting.1983282875" name="Create extended listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize.1000761142" name="Print size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.514997414" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.size" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.1008570639" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.467272439" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections.2047756949" name="Function sections (-ffunction-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections.207613650" name="Data sections (-fdata-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.1204865254" name="Debug level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level" useByScannerDiscovery="true"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format.867779652" name="Debug format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format" useByScannerDiscovery="true"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1900297968" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv32i" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.387605487" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.ilp32" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1509705449" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1038505275" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name.1218760634" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name" useByScannerDiscovery="false" value="GNU MCU RISC-V GCC" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix.103341323" name="Prefix" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix" useByScannerDiscovery="false" value="riscv-none-embed-" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c.487601824" name="C compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp.1062130429" name="C++ compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.ar.1194282993" name="Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy.1529355265" name="Hex/Bin converter" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump.1053750745" name="Listing generator" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size.1441326233" name="Size command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make.550105535" name="Build command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.719280496" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id.226017994" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.id" useByScannerDiscovery="false" value="512258282" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialized)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.1225539165" name="No common unitialized (-fno-common)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.944577914" name="Extra Compressed extension (RVXW)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.smalldatalimit.1567611014" name="Small data limit" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.smalldatalimit" useByScannerDiscovery="false" value="8" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.1020286369" name="Small prologue/epilogue (-msave-restore)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc.733884889" name="RISC-V Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc.12" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.highcode.651455843" name="Optimize unused sections declared as high code (--param=highcode-gen-section-name=1)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.highcode" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.PIC.853226312" name="Position independent code (-fPIC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.PIC" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nomoveloopinvariants.931029403" name="Disable loop invariant move (-fno-move-loop-invariants)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nomoveloopinvariants" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.lto.38424313" name="Link-time optimizer (-flto)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.lto" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.spconstant.1831210356" name="Single precision constants (-fsingle-precision-constant)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.spconstant" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin.1585310233" name="Disable builtin (-fno-builtin)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding.1883148798" name="Assume freestanding environment (-ffreestanding)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions.627431310" name="Do not inline functions (-fno-inline-functions)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.caret.1777244869" name="show caret indicating the column (-fno-diagnostics-show-caret)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.caret" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.pipe.289879429" name="pipelines to replace temporary files (-pipe)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.pipe" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.asmsoftlib.344969940" name="Code generation library that does not use floating-point variables for compatibility with hardware floating-point extensions (-Xassembler -wchsoftlib)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.asmsoftlib" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.1944008784" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
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||||
<builder buildPath="${workspace_loc:/${ProjName}}/obj" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1421508906" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1692176068" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.1034038285" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
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||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Startup}""/>
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||||
</option>
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||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.126366858" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
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||||
</tool>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
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||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.1567947810" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Flashlib}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Core}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/User}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Peripheral/inc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/MCU_Driver/inc}""/>
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</option>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.2020844713" name="Language standard" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.std.gnu99" valueType="enumerated"/>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs.177116515" name="Defined symbols (-D)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
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<listOptionValue builtIn="false" value="DEBUG=1"/>
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</option>
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<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input"/>
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</tool>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.1610882921" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1620074387" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections.194760422" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.2057340378" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Flashlib}""/>
|
||||
</option>
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||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1390103472" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
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||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Ld/Link.ld}""/>
|
||||
</option>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.913830613" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.239404511" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys.351964161" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnosys" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs.16994550" name="Other objects" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.otherobjs" useByScannerDiscovery="false" valueType="userObjs"/>
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||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags.1125808200" name="Linker flags (-Xlinker [option])" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.flags" useByScannerDiscovery="false" valueType="stringList"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.iqmath.514344306" name="Use iqmath(-lIQmath_RV32)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.iqmath" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.printf.1018325233" name="Use wchprintf(-lprintf)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.printf" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.836070313" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
|
||||
<listOptionValue builtIn="false" value="ISP564"/>
|
||||
</option>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.printfloat.1577261781" name="Use wchprintfloat(-lprintfloat)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.printfloat" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.2039248139" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--print-memory-usage" valueType="string"/>
|
||||
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1859223768" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.1947503520" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths.1029177148" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""../LD""/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="Link.ld"/>
|
||||
</option>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.other.406870191" name="Other flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.other" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.1719943455" name="Output file format (-O)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.ihexAndbinary" valueType="enumerated"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.other.251302860" name="Other flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.other" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
|
||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="paradict.txt|NetLib|Ld|Debug|Startup" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
|
||||
<entry excluding="startup_ch564_ram_128k.S|startup_ch564_ram_96k.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
</cproject>
|
||||
1
.gitignore
vendored
Normal file
1
.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
obj
|
||||
37
.project
Normal file
37
.project
Normal file
@@ -0,0 +1,37 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<projectDescription>
|
||||
<name>BLV_C1P_Bootload</name>
|
||||
<comment/>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<id>1692846627047</id>
|
||||
<name/>
|
||||
<type>22</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
</projectDescription>
|
||||
14
.settings/language.settings.xml
Normal file
14
.settings/language.settings.xml
Normal file
@@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-973562663347761187" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
11
.settings/org.eclipse.cdt.managedbuilder.core.prefs
Normal file
11
.settings/org.eclipse.cdt.managedbuilder.core.prefs
Normal file
@@ -0,0 +1,11 @@
|
||||
eclipse.preferences.version=1
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/CPATH/delimiter=;
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/CPATH/operation=remove
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/C_INCLUDE_PATH/delimiter=;
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/C_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/append=true
|
||||
environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/appendContributed=true
|
||||
environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/LIBRARY_PATH/delimiter=;
|
||||
environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/LIBRARY_PATH/operation=remove
|
||||
environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/append=true
|
||||
environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/appendContributed=true
|
||||
3
.settings/org.eclipse.core.resources.prefs
Normal file
3
.settings/org.eclipse.core.resources.prefs
Normal file
@@ -0,0 +1,3 @@
|
||||
eclipse.preferences.version=1
|
||||
encoding/.cproject=GBK
|
||||
encoding//Peripheral/inc/ch564.h=UTF-8
|
||||
18
.template
Normal file
18
.template
Normal file
@@ -0,0 +1,18 @@
|
||||
Vendor=WCH
|
||||
Toolchain=RISC-V
|
||||
Series=CH564
|
||||
RTOS=NoneOS
|
||||
MCU=CH564F
|
||||
Link=WCH-Link
|
||||
PeripheralVersion=====1.2
|
||||
Description=====CH564 is an industrial-grade microcontroller based on barley RISC-V core design. CH564 built-in USBHS PHY and PD PHY, support for USB Host host and USB Device device functions, PDUSB and Type-C fast charging; built-in Ethernet controller MAC and 10 megabits/100 megabits physical layer transceiver; provides an external bus interface XBUS, 8-bit passive parallel port SLV, 12-bit analogue-to-digital converter ADC, multi-group timer, 4-group UART serial port, I2C interface, 2 SPI interface and other rich peripheral resources.
|
||||
Mcu Type=CH564
|
||||
Address=0x00000000
|
||||
Target Path=obj\BLV_C1P_20250514.hex
|
||||
CLKSpeed=1
|
||||
DebugInterfaceMode=1
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=true
|
||||
Reset=true
|
||||
SDIPrintf=false
|
||||
1
BLV_C1P_Bootload.wvproj
Normal file
1
BLV_C1P_Bootload.wvproj
Normal file
@@ -0,0 +1 @@
|
||||
?6`O b9Kt<4B><74><EFBFBD><EFBFBD>!6;$ X <1D><><EFBFBD><EFBFBD>A<A\N{1H<31>nÿ<6E> W%L8s7}1&FN<46><4E>& (|i<>Uu<55>eX<65>y<EFBFBD><79><EFBFBD>G<EFBFBD>F<EFBFBD>N+<2B>RuD"<22><08> `8<>V*<05><>i<EFBFBD><69>2H~<7E>zH<7A>VZbW <0B><><EFBFBD>S?<3F><>*<2A><> t~<7E><>8Ex<45>o] h<><68>z<>~<7E><><EFBFBD>yn-#<23><10>`"}<7D><><EFBFBD>V<><56><EFBFBD><EFBFBD><03>S<EFBFBD><53><EFBFBD>,NG<4E>4<EFBFBD>\<5C>$T^~<7E>Z<EFBFBD>{(Q<> <1C>g<EFBFBD><67>C=<3D>H
|
||||
317
Core/core_riscv.c
Normal file
317
Core/core_riscv.c
Normal file
@@ -0,0 +1,317 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : RISC-V V4J Core Peripheral Access Layer Source File for CH564
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "stdint.h"
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined(__CC_ARM)
|
||||
#define __ASM __asm /* asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /* inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#define __ASM __asm /* asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
#define __ASM __asm /* asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /* inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#define __ASM __asm /* asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /* inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSTATUS
|
||||
*
|
||||
* @brief Return the Machine Status Register
|
||||
*
|
||||
* @return mstatus value
|
||||
*/
|
||||
uint32_t __get_MSTATUS(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mstatus" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSTATUS
|
||||
*
|
||||
* @brief Set the Machine Status Register
|
||||
*
|
||||
* @param value - set mstatus value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSTATUS(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mstatus, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MISA
|
||||
*
|
||||
* @brief Return the Machine ISA Register
|
||||
*
|
||||
* @return misa value
|
||||
*/
|
||||
uint32_t __get_MISA(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""misa" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MISA
|
||||
*
|
||||
* @brief Set the Machine ISA Register
|
||||
*
|
||||
* @param value - set misa value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MISA(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw misa, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVEC
|
||||
*
|
||||
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @return mtvec value
|
||||
*/
|
||||
uint32_t __get_MTVEC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mtvec" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVEC
|
||||
*
|
||||
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @param value - set mtvec value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MTVEC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mtvec, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSCRATCH
|
||||
*
|
||||
* @brief Return the Machine Seratch Register
|
||||
*
|
||||
* @return mscratch value
|
||||
*/
|
||||
uint32_t __get_MSCRATCH(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mscratch" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSCRATCH
|
||||
*
|
||||
* @brief Set the Machine Seratch Register
|
||||
*
|
||||
* @param value - set mscratch value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSCRATCH(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mscratch, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MEPC
|
||||
*
|
||||
* @brief Return the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
uint32_t __get_MEPC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mepc" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
void __set_MEPC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mepc, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MCAUSE
|
||||
*
|
||||
* @brief Return the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
uint32_t __get_MCAUSE(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mcause" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
void __set_MCAUSE(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mcause, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVAL
|
||||
*
|
||||
* @brief Return the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
uint32_t __get_MTVAL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mtval" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVAL
|
||||
*
|
||||
* @brief Set the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
void __set_MTVAL(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mtval, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MVENDORID
|
||||
*
|
||||
* @brief Return Vendor ID Register
|
||||
*
|
||||
* @return mvendorid value
|
||||
*/
|
||||
uint32_t __get_MVENDORID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mvendorid" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MARCHID
|
||||
*
|
||||
* @brief Return Machine Architecture ID Register
|
||||
*
|
||||
* @return marchid value
|
||||
*/
|
||||
uint32_t __get_MARCHID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""marchid" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MIMPID
|
||||
*
|
||||
* @brief Return Machine Implementation ID Register
|
||||
*
|
||||
* @return mimpid value
|
||||
*/
|
||||
uint32_t __get_MIMPID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mimpid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MHARTID
|
||||
*
|
||||
* @brief Return Hart ID Register
|
||||
*
|
||||
* @return mhartid value
|
||||
*/
|
||||
uint32_t __get_MHARTID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mhartid" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_SP
|
||||
*
|
||||
* @brief Return SP Register
|
||||
*
|
||||
* @return SP value
|
||||
*/
|
||||
uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("mv %0,""sp" : "=r"(result):);
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((noinline)) void NVIC_SystemReset(void)
|
||||
{
|
||||
asm("li t0, 0xa8");
|
||||
asm("jr t0");
|
||||
}
|
||||
|
||||
687
Core/core_riscv.h
Normal file
687
Core/core_riscv.h
Normal file
@@ -0,0 +1,687 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : RISC-V V4J Core Peripheral Access Layer Header File for CH564
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /* defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /* defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /* defines 'write only' permissions */
|
||||
#define __IO volatile /* defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint64_t vuc64; /* Read Only */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint64_t uc64; /* Read Only */
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int64_t vsc64; /* Read Only */
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int64_t sc64; /* Read Only */
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint64_t vu64;
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint64_t u64;
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int64_t vs64;
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int64_t s64;
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NoREADY = 0,
|
||||
READY = !NoREADY
|
||||
} ErrorStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t RESERVED;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
__IO uint8_t VTFIDR[4];
|
||||
uint8_t RESERVED0[12];
|
||||
__IO uint32_t VTFADDR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
} PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint32_t SR;
|
||||
__IO uint64_t CNT;
|
||||
__IO uint64_t CMP;
|
||||
} SysTick_Type;
|
||||
|
||||
#define PFIC ((PFIC_Type *)0xE000E000)
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
#define SysTick ((SysTick_Type *)0xE000F000)
|
||||
|
||||
/* CSR_Operation_Function */
|
||||
#define READ_CSR(reg) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
__asm volatile("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define WRITE_CSR(reg, val) \
|
||||
({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
__asm volatile("csrw " #reg ", %0" ::"i"(val)); \
|
||||
else \
|
||||
__asm volatile("csrw " #reg ", %0" ::"r"(val)); \
|
||||
})
|
||||
|
||||
#define SWAP_CSR(reg, val) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
__asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
|
||||
else \
|
||||
__asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define SET_CSR(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
__asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
__asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define CLEAR_CSR(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
__asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
__asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __enable_irq()
|
||||
{
|
||||
__asm volatile("csrs 0x800, %0" : : "r"(0x88));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __disable_irq()
|
||||
{
|
||||
__asm volatile("csrc 0x800, %0" : : "r"(0x88));
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6:5] - Sub priority
|
||||
* bit[4:0] - Reserve
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* priority - bit[7:5] - Sub priority
|
||||
* bit[4:0] - Reserve
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1 << 3); // wfi
|
||||
__asm volatile("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _SEV
|
||||
*
|
||||
* @brief Set Event
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void _SEV(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1 << 3) | (1 << 5);
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1 << 5)) | (t & (1 << 5));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void _WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1 << 3);
|
||||
__asm volatile("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
_SEV();
|
||||
_WFE();
|
||||
_WFE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetVTFIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param addr - VTF interrupt service function base address.
|
||||
* IRQn - Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* NewState - DISABLE or ENABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
if (num > 3)
|
||||
return;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) | 0x1);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) & (~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheEnable
|
||||
*
|
||||
* @brief Enable ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheEnable(void)
|
||||
{
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
CLEAR_CSR(0xBC2, 0x2);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheDisable
|
||||
*
|
||||
* @brief Disable ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheDisable(void)
|
||||
{
|
||||
SET_CSR(0xBC2, 0x2);
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheInvalidate
|
||||
*
|
||||
* @brief Invalidate ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate(void)
|
||||
{
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheInvalidate_By_Address
|
||||
*
|
||||
* @brief Invalidate ICache By Address
|
||||
*
|
||||
* @param addr - operation address(addr%4 = 0)
|
||||
* size - operation size(unit 4Byte)
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate_By_Address(uint32_t *addr, uint32_t size)
|
||||
{
|
||||
uint32_t t;
|
||||
uint32_t temp;
|
||||
|
||||
for (t = 0; t < size; t++)
|
||||
{
|
||||
temp = (uint32_t)(addr + t);
|
||||
WRITE_CSR(0xBD0, (temp & 0xFFFFFFF8));
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOADD_W
|
||||
*
|
||||
* @brief Atomic Add with 32bit value
|
||||
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ADDed
|
||||
*
|
||||
* @return return memory value + add value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOAND_W
|
||||
*
|
||||
* @brief Atomic And with 32bit value
|
||||
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ANDed
|
||||
*
|
||||
* @return return memory value & and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAX_W
|
||||
*
|
||||
* @brief Atomic signed MAX with 32bit value
|
||||
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the bigger value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAXU_W
|
||||
*
|
||||
* @brief Atomic unsigned MAX with 32bit value
|
||||
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMIN_W
|
||||
*
|
||||
* @brief Atomic signed MIN with 32bit value
|
||||
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMINU_W
|
||||
*
|
||||
* @brief Atomic unsigned MIN with 32bit value
|
||||
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOOR_W
|
||||
*
|
||||
* @brief Atomic OR with 32bit value
|
||||
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ORed
|
||||
*
|
||||
* @return return memory value | and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOSWAP_W
|
||||
*
|
||||
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* newval - New value to be stored into the address
|
||||
*
|
||||
* @return return the original value in memory
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOXOR_W
|
||||
*
|
||||
* @brief Atomic XOR with 32bit value
|
||||
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be XORed
|
||||
*
|
||||
* @return return memory value ^ and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
extern void NVIC_SystemReset(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
263
Flashlib/ISP564.h
Normal file
263
Flashlib/ISP564.h
Normal file
@@ -0,0 +1,263 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ISP564.h
|
||||
* Author : WCH
|
||||
* Version : V1.1.0
|
||||
* Date : 2024/07/17
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* FLASH firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __ISP564_H
|
||||
#define __ISP564_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
/* FLASH Status */
|
||||
typedef enum
|
||||
{
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT,
|
||||
FLASH_VERIFY_ERROR,
|
||||
FLASH_ADR_RANGE_ERROR,
|
||||
FLASH_UNLOCK_ERROR,
|
||||
}FLASH_Status;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_Unlock
|
||||
*
|
||||
* @brief Unlocks the FLASH Program and Erase Controller.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
extern void FLASH_Unlock(void);
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_Lock
|
||||
*
|
||||
* @brief Locks the FLASH Program and Erase Controller.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
extern void FLASH_Lock(void);
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GetMACAddress
|
||||
*
|
||||
* @brief Get MAC address(6Bytes)
|
||||
*
|
||||
* @param Buffer - Pointer to the buffer where data should be stored,
|
||||
* Must be aligned to 4 bytes.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT.
|
||||
*/
|
||||
extern FLASH_Status GetMACAddress( void *Buffer );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GET_UNIQUE_ID
|
||||
*
|
||||
* @brief Get unique ID(8Bytes)
|
||||
*
|
||||
* @param Buffer - Pointer to the buffer where data should be stored,
|
||||
* Must be aligned to 4 bytes.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT.
|
||||
*/
|
||||
extern FLASH_Status GET_UNIQUE_ID( void *Buffer );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GetCHIPID
|
||||
*
|
||||
* @brief Get chip ID(4Bytes)
|
||||
*
|
||||
* @param Buffer - Pointer to the buffer where data should be stored,
|
||||
* Must be aligned to 4 bytes.
|
||||
* ChipID List-
|
||||
* CH564L-0x564005x8
|
||||
* CH564Q-0x564105x8
|
||||
* CH564F-0x564305x8
|
||||
* CH564C-0x564205x8
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT.
|
||||
*/
|
||||
extern FLASH_Status GetCHIPID( void *Buffer );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Get_Flash_Size
|
||||
*
|
||||
* @brief Get FLASH Size(1Bytes)
|
||||
*
|
||||
* @param Buffer - Pointer to the buffer where data should be stored.
|
||||
* 0 - FLASH-256K
|
||||
* ROMA(UserFLASH)
|
||||
* - Size(192K)
|
||||
* - Address range(0x0 -- 0x2FFFF)
|
||||
* EEPROM(DataFLASH)
|
||||
* - Size(32K)
|
||||
* - Address range(0x30000 -- 0x37FFF)
|
||||
* 1 - FLASH-512K
|
||||
* ROMA(UserFLASH)
|
||||
* - Size(448K)
|
||||
* - Address range(0x0 -- 0x6FFFF)
|
||||
* EEPROM(DataFLASH)
|
||||
* - Size(32K)
|
||||
* - Address range(0x70000 -- 0x77FFF)
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT.
|
||||
*/
|
||||
extern FLASH_Status Get_Flash_Size( void *Buffer );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_EnableCodeProtection
|
||||
*
|
||||
* @brief Enables the code protection.
|
||||
*
|
||||
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
|
||||
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
extern FLASH_Status FLASH_EnableCodeProtection( void );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROM_PWR_UP
|
||||
*
|
||||
* @brief The function `FLASH_ROM_PWR_DOWN` sends a command to put
|
||||
* the SPI flash memory into power down mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
extern void FLASH_ROM_PWR_DOWN( void );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROM_PWR_UP
|
||||
*
|
||||
* @brief The function `FLASH_ROM_PWR_UP` sets up the SPI flash
|
||||
* control register to power up the flash memory
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
extern void FLASH_ROM_PWR_UP( void );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EEPROM_READ
|
||||
*
|
||||
* @brief (DataFLASH) - The EEPROM_READ function reads data from a specified address
|
||||
* in flash memory with error handling for address range checks.
|
||||
*
|
||||
* @param StartAddr - Read the starting address of the DataFLASH.
|
||||
* Buffer - Read the value of the DataFLASH.
|
||||
* Length - Read the length of the DataFLASH.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR.
|
||||
*/
|
||||
extern FLASH_Status EEPROM_READ( uint32_t StartAddr, void *Buffer, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EEPROM_ERASE
|
||||
*
|
||||
* @brief (DataFLASH) - The function EEPROM_ERASE checks the flash size and address
|
||||
* range before erasing a specified portion of flash memory.
|
||||
*
|
||||
* @param StartAddr - Erases the starting address of the DataFLASH(StartAddr%4096 == 0).
|
||||
* Length - Erases the length of the DataFLASH(Length%4096 == 0).
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR.
|
||||
*/
|
||||
extern FLASH_Status EEPROM_ERASE( uint32_t StartAddr, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EEPROM_WRITE
|
||||
*
|
||||
* @brief (DataFLASH) - The function EEPROM_WRITE writes data to EEPROM memory
|
||||
* based on specified address and length, performing address
|
||||
* range and unlock checks.
|
||||
*
|
||||
* @param StartAddr - Writes the starting address of the DataFLASH.
|
||||
* Buffer - Writes the value of the DataFLASH.
|
||||
* Length - Writes the length of the DataFLASH.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR.
|
||||
*/
|
||||
extern FLASH_Status EEPROM_WRITE( uint32_t StartAddr, void *Buffer, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROMA_ERASE
|
||||
*
|
||||
* @brief (UserFLASH) - The function `FLASH_ROMA_ERASE` checks the flash size and
|
||||
* address range before erasing a specified portion of flash
|
||||
* memory.
|
||||
*
|
||||
* @param StartAddr - Erases the starting address of the UserFLASH(StartAddr%4096 == 0).
|
||||
* Length - Erases the length of the UserFLASH(Length%4096 == 0).
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR.
|
||||
*/
|
||||
extern FLASH_Status FLASH_ROMA_ERASE( uint32_t StartAddr, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROMA_WRITE
|
||||
*
|
||||
* @brief (UserFLASH) - The function FLASH_ROMA_WRITE writes data to a specific
|
||||
* flash memory address after performing size and unlock checks.
|
||||
*
|
||||
* @param StartAddr - Writes the starting address of the UserFLASH.
|
||||
* Buffer - Writes the value of the UserFLASH.
|
||||
* Length - Writes the length of the UserFLASH.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR.
|
||||
*/
|
||||
extern FLASH_Status FLASH_ROMA_WRITE( uint32_t StartAddr, void *Buffer, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROMA_VERIFY
|
||||
*
|
||||
* @brief (UserFLASH) - The function `FLASH_ROMA_VERIFY` verifies the contents of
|
||||
* a specified flash memory region against a provided buffer.
|
||||
*
|
||||
* @param StartAddr - Verify the starting address of the UserFLASH.
|
||||
* Buffer - Verify the value of the UserFLASH.
|
||||
* Length - Verify the length of the UserFLASH.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_VERIFY_ERROR.
|
||||
*/
|
||||
extern FLASH_Status FLASH_ROMA_VERIFY( uint32_t StartAddr, void *Buffer, uint32_t Length );
|
||||
|
||||
/*********************************************************************
|
||||
* @fn FLASH_ROMA_READ
|
||||
*
|
||||
* @brief (UserFLASH) - The function `FLASH_ROMA_READ` reads data from a specific
|
||||
* flash memory address with error handling for different flash
|
||||
* size
|
||||
*
|
||||
* @param StartAddr - Read the starting address of the UserFLASH.
|
||||
* Buffer - Read the value of the UserFLASH.
|
||||
* Length - Read the length of the UserFLASH.
|
||||
*
|
||||
* @return FLASH_Status -The returned value can be: FLASH_COMPLETE,
|
||||
* FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR.
|
||||
*/
|
||||
extern FLASH_Status FLASH_ROMA_READ( uint32_t StartAddr, void *Buffer, uint32_t Length );
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
BIN
Flashlib/libISP564.a
Normal file
BIN
Flashlib/libISP564.a
Normal file
Binary file not shown.
222
Ld/Link.ld
Normal file
222
Ld/Link.ld
Normal file
@@ -0,0 +1,222 @@
|
||||
ENTRY( _start )
|
||||
|
||||
__stack_size = 4096;
|
||||
|
||||
PROVIDE( _stack_size = __stack_size );
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* FLASH + RAM supports the following configuration
|
||||
FLASH-80K + RAM-64K
|
||||
FLASH-48K + RAM-96K
|
||||
FLASH-16K + RAM-128K
|
||||
*/
|
||||
|
||||
/* FLASH-16K + RAM-128K */
|
||||
/*
|
||||
FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 16K
|
||||
FLASH1 (rx) : ORIGIN = 0x00004000 , LENGTH = 448K - 16K
|
||||
RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 128K
|
||||
*/
|
||||
/*
|
||||
FLASH (rx) : ORIGIN = 0x20000000 , LENGTH = 28K
|
||||
FLASH1 (rx) : ORIGIN = 0x00028000 , LENGTH = 448K - 160K
|
||||
RAM (xrw) : ORIGIN = 0x20007000 , LENGTH = 64K - 28K
|
||||
*/
|
||||
/* FLASH-48K + RAM-96K */
|
||||
/*
|
||||
FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 48K
|
||||
FLASH1 (rx) : ORIGIN = 0x0000C000 , LENGTH = 448K - 48K
|
||||
RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 96K
|
||||
*/
|
||||
|
||||
/* FLASH-80K + RAM-64K */
|
||||
/*
|
||||
FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 80K
|
||||
FLASH1 (rx) : ORIGIN = 0x00014000 , LENGTH = 448K - 80K
|
||||
RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K
|
||||
*/
|
||||
|
||||
FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 80K
|
||||
FLASH1 (rx) : ORIGIN = 0x00014000 , LENGTH = 448K - 80K
|
||||
RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.init :
|
||||
{
|
||||
_sinit = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(SORT_NONE(.init)))
|
||||
. = ALIGN(4);
|
||||
_einit = .;
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.vector :
|
||||
{
|
||||
*(.vector);
|
||||
_endof_Vector = .;
|
||||
ASSERT(_endof_Vector < ORIGIN(FLASH1), "The vector must maintain in 0-wait zone");
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _cache_beg = __cache_beg );
|
||||
PROVIDE( _cache_end = __cache_end );
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*libISP564.a:(.text))
|
||||
KEEP(*libISP564.a:(.text.*))
|
||||
KEEP(*libISP564.a:(.rodata))
|
||||
KEEP(*libISP564.a:(.rodata.*))
|
||||
_endof_Flashlib = .;
|
||||
ASSERT(_endof_Flashlib < ORIGIN(FLASH1), "The Flash lib must maintain in 0-wait zone");
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.text1 :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( __cache_beg = .);
|
||||
*(.cache);
|
||||
*(.cache.*);
|
||||
PROVIDE( __cache_end = .);
|
||||
*(.non_0_wait);
|
||||
*(.non_0_wait.*);
|
||||
. = ALIGN(4);
|
||||
} >FLASH1 AT>FLASH1
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(SORT_NONE(.fini)))
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _etext = . );
|
||||
PROVIDE( _eitcm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_vma = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.dlalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _sbss = .);
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ebss = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
PROVIDE( _end = _ebss);
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_susrstack = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _eusrstack = .);
|
||||
} >RAM
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
1149
MCU_Driver/bootload_fun.c
Normal file
1149
MCU_Driver/bootload_fun.c
Normal file
File diff suppressed because it is too large
Load Diff
368
MCU_Driver/debug.c
Normal file
368
MCU_Driver/debug.c
Normal file
@@ -0,0 +1,368 @@
|
||||
/*
|
||||
* debug.c
|
||||
*
|
||||
* Created on: May 14, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "debug.h"
|
||||
#include <stddef.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
|
||||
volatile uint32_t SysTick_100us = 0;
|
||||
volatile uint32_t SysTick_1ms = 0;
|
||||
volatile uint32_t SysTick_1s = 0;
|
||||
|
||||
void Systick_Init(void)
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ȼ<EFBFBD>*/
|
||||
NVIC_SetPriority(SysTick_IRQn, 0x00);
|
||||
NVIC_EnableIRQ(SysTick_IRQn);
|
||||
|
||||
/*<2A><><EFBFBD>ö<EFBFBD>ʱ<EFBFBD><CAB1>*/
|
||||
SysTick->CTLR= 0;
|
||||
SysTick->SR = 0;
|
||||
SysTick->CNT = 0;
|
||||
SysTick->CMP = SystemCoreClock/10000; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1000<30><30><EFBFBD><EFBFBD>1000HZ(<28>Ǿ<EFBFBD><C7BE><EFBFBD>1ms<6D><73>һ<EFBFBD><D2BB><EFBFBD>ж<EFBFBD>)
|
||||
SysTick->CTLR= 0xf;
|
||||
}
|
||||
|
||||
void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
static uint8_t NUM = 0;
|
||||
static uint16_t NUM_S = 0;
|
||||
|
||||
SysTick->SR = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
|
||||
|
||||
SysTick_100us++;
|
||||
NUM++;
|
||||
|
||||
if(NUM >= 10){
|
||||
NUM = 0;
|
||||
SysTick_1ms++;
|
||||
NUM_S++;
|
||||
|
||||
if(NUM_S >= 1000)
|
||||
{
|
||||
NUM_S = 0;
|
||||
SysTick_1s++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Us
|
||||
*
|
||||
* @brief Microsecond Delay Time.
|
||||
*
|
||||
* @param n - Microsecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Us(uint32_t n)
|
||||
{
|
||||
for(uint32_t i=0;i<n;i++){
|
||||
for(uint32_t j=0;j<30;j++){
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Ms
|
||||
*
|
||||
* @brief Millisecond Delay Time.
|
||||
*
|
||||
* @param n - Millisecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Ms(uint32_t n)
|
||||
{
|
||||
for(uint32_t i=0;i<n;i++){
|
||||
Delay_Us(1000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _write
|
||||
*
|
||||
* @brief Support Printf Function
|
||||
*
|
||||
* @param *buf - UART send Data.
|
||||
* size - Data length.
|
||||
*
|
||||
* @return size - Data length
|
||||
*/
|
||||
__attribute__((used)) int _write(int fd, char *buf, int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
#if (DEBUG) == DEBUG_UART0
|
||||
while ((R8_UART0_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART0_THR = *(buf++);
|
||||
#elif (DEBUG) == DEBUG_UART1
|
||||
while ((R8_UART1_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART1_THR = *(buf++);
|
||||
#elif (DEBUG) == DEBUG_UART2
|
||||
while ((R8_UART2_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART2_THR = *(buf++);
|
||||
#elif (DEBUG) == DEBUG_UART3
|
||||
while ((R8_UART3_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART3_THR = *(buf++);
|
||||
#endif
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _sbrk
|
||||
*
|
||||
* @brief Change the spatial position of data segment.
|
||||
*
|
||||
* @return size: Data length
|
||||
*/
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||
return NULL - 1;
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
|
||||
|
||||
uint32_t SysTick_Now = 0, SysTick_Last = 0, SysTick_Diff = 0;
|
||||
char Dbg_Buffer[100];
|
||||
|
||||
uint32_t Dbg_Switch = (DBG_OPT_ActCond_STATUS << DBG_BIT_ActCond_STATUS_bit) + \
|
||||
(DBG_OPT_MQTT_STATUS << DBG_BIT_MQTT_STATUS_bit) + \
|
||||
(DBG_OPT_Debug_STATUS << DBG_BIT_Debug_STATUS_bit) + \
|
||||
(DBG_OPT_LOGIC_STATUS << DBG_BIT_LOGIC_STATUS_bit) + \
|
||||
(DBG_OPT_DEVICE_STATUS << DBG_BIT_DEVICE_STATUS_bit) + \
|
||||
(DBG_OPT_NET_STATUS << DBG_BIT_NET_STATUS_bit) + \
|
||||
(DBG_OPT_SYS_STATUS << DBG_BIT_SYS_STATUS_bit);
|
||||
|
||||
//<2F>÷<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD>ٴ<EFBFBD><D9B4><EFBFBD><EFBFBD>ռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
void __putchar__ (char ch)
|
||||
{
|
||||
#if 1
|
||||
|
||||
#if (DEBUG) == DEBUG_UART0
|
||||
while ((R8_UART0_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART0_THR = ch;
|
||||
#elif (DEBUG) == DEBUG_UART1
|
||||
while ((R8_UART1_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART1_THR = ch;
|
||||
#elif (DEBUG) == DEBUG_UART2
|
||||
while ((R8_UART2_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART2_THR = ch;
|
||||
#elif (DEBUG) == DEBUG_UART3
|
||||
while ((R8_UART3_LSR & RB_LSR_TX_FIFO_EMP) == 0);
|
||||
R8_UART3_THR = ch;
|
||||
#endif
|
||||
|
||||
#else
|
||||
//select debug serial Pane
|
||||
volatile unsigned int *pdata = (unsigned int *)LDCC_DATA_P;
|
||||
while (*pdata & LDCC_BIT_STATUS); //Waiting for data read.
|
||||
*pdata = ch;
|
||||
#endif
|
||||
}
|
||||
|
||||
int *myitoa(int value, int* string, int radix)
|
||||
{
|
||||
int tmp[33];
|
||||
int* tp = tmp;
|
||||
int i;
|
||||
unsigned v;
|
||||
int sign;
|
||||
int* sp;
|
||||
|
||||
if (radix > 36 || radix <= 1)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
sign = (radix == 10 && value < 0);
|
||||
if (sign)
|
||||
v = -value;
|
||||
else
|
||||
v = (unsigned)value;
|
||||
while (v || tp == tmp)
|
||||
{
|
||||
i = v % radix;
|
||||
v = v / radix;
|
||||
if (i < 10) {
|
||||
*tp++ = i+'0';
|
||||
|
||||
} else {
|
||||
*tp++ = i + 'a' - 10;
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
sp = string;
|
||||
|
||||
if (sign)
|
||||
*sp++ = '-';
|
||||
while (tp > tmp)
|
||||
*sp++ = *--tp;
|
||||
*sp = 0;
|
||||
return string;
|
||||
}
|
||||
|
||||
|
||||
void my_printf(const char *fmt, ...)
|
||||
{
|
||||
const int *s;
|
||||
int d;
|
||||
|
||||
char ch, *pbuf;
|
||||
int buf[16];
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
while (*fmt) {
|
||||
if (*fmt != '%') {
|
||||
__putchar__(*fmt++);
|
||||
continue;
|
||||
}
|
||||
switch (*++fmt) {
|
||||
case 's':
|
||||
s = va_arg(ap, const int *);
|
||||
for ( ; *s; s++) {
|
||||
__putchar__(*s);
|
||||
}
|
||||
break;
|
||||
case 'd':
|
||||
d = va_arg(ap, int);
|
||||
myitoa(d, buf, 10);
|
||||
for (s = buf; *s; s++) {
|
||||
__putchar__(*s);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'x':
|
||||
case 'X':
|
||||
d = va_arg(ap, int);
|
||||
myitoa(d, buf, 16);
|
||||
for (s = buf; *s; s++) {
|
||||
__putchar__(*s);
|
||||
}
|
||||
break;
|
||||
// Add other specifiers here...
|
||||
case 'c':
|
||||
case 'C':
|
||||
ch = (unsigned char)va_arg(ap, int);
|
||||
pbuf = &ch;
|
||||
__putchar__(*pbuf);
|
||||
break;
|
||||
default:
|
||||
__putchar__(*fmt);
|
||||
break;
|
||||
}
|
||||
fmt++;
|
||||
}
|
||||
va_end(ap);
|
||||
}
|
||||
|
||||
void Dbg_Println(int DbgOptBit ,const char *fmt, ...)
|
||||
{
|
||||
|
||||
char ch;
|
||||
|
||||
va_list ap;
|
||||
|
||||
if ( (DBG_LOG_EN & DBG_BIT_SYS_STATUS) != 0x00 )
|
||||
{
|
||||
SysTick_Now = SysTick_1ms;
|
||||
SysTick_Diff = SysTick_Now - SysTick_Last; //<2F><>һ<EFBFBD>δ<EFBFBD>ӡʱ<D3A1><CAB1><EFBFBD><EFBFBD>
|
||||
SysTick_Last = SysTick_Now;
|
||||
|
||||
printf("%8d [%6d]: ",SysTick_Now,SysTick_Diff);
|
||||
|
||||
va_start(ap, fmt);
|
||||
while (*fmt) {
|
||||
if (*fmt != '%') {
|
||||
__putchar__(*fmt++);
|
||||
continue;
|
||||
}
|
||||
switch (*++fmt) {
|
||||
case 's':
|
||||
{
|
||||
char *str = va_arg(ap, char *);
|
||||
printf("%s",str);
|
||||
}
|
||||
break;
|
||||
case 'd':
|
||||
{
|
||||
int num = va_arg(ap, int);
|
||||
printf("%d", num);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'x':
|
||||
case 'X':
|
||||
{
|
||||
int num = va_arg(ap, unsigned int);
|
||||
printf("%x", num);
|
||||
}
|
||||
break;
|
||||
// Add other specifiers here...
|
||||
case 'c':
|
||||
case 'C':
|
||||
ch = (unsigned char)va_arg(ap, int);
|
||||
printf("%c", ch);
|
||||
break;
|
||||
default:
|
||||
__putchar__(*fmt);
|
||||
break;
|
||||
}
|
||||
fmt++;
|
||||
}
|
||||
va_end(ap);
|
||||
printf("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Dbg_Print_Buff
|
||||
* Description : DEBUG<55><47><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD>Buff<66>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
* Return :
|
||||
*******************************************************************************/
|
||||
void Dbg_Print_Buff(int DbgOptBit ,const char *cmd ,uint8_t *buff,uint32_t len)
|
||||
{
|
||||
#if DBG_LOG_EN
|
||||
if ( (Dbg_Switch & DbgOptBit ) != 0x00 )
|
||||
{
|
||||
SysTick_Now = SysTick_1ms;
|
||||
SysTick_Diff = SysTick_Now - SysTick_Last; //<2F><>һ<EFBFBD>δ<EFBFBD>ӡʱ<D3A1><CAB1><EFBFBD><EFBFBD>
|
||||
SysTick_Last = SysTick_Now;
|
||||
|
||||
printf("%8d [%6d]: %s",SysTick_Now,SysTick_Diff,cmd);
|
||||
for(uint32_t i=0;i<len;i++)
|
||||
{
|
||||
printf("%02X ",buff[i]);
|
||||
}
|
||||
printf("\n\r");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
84
MCU_Driver/inc/bootload_fun.h
Normal file
84
MCU_Driver/inc/bootload_fun.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* launcher_fun.h
|
||||
*
|
||||
* Created on: Jul 28, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef _BOOTLOAD_FUN_H_
|
||||
#define _BOOTLOAD_FUN_H_
|
||||
|
||||
#include "ch564.h"
|
||||
#include "uart.h"
|
||||
#include "mcu_flash.h"
|
||||
|
||||
|
||||
|
||||
#define BCOMM_CMD_Handshake 0xC0
|
||||
#define BCOMM_CMD_Jump 0xC1
|
||||
#define BCOMM_CMD_SetInfo 0xC2
|
||||
#define BCOMM_CMD_WriteFlash 0xC3
|
||||
#define BCOMM_CMD_ReadFlash 0xC4
|
||||
#define BCOMM_CMD_EraseFlash 0xC5
|
||||
#define BCOMM_CMD_WriteEEPROM 0xC6
|
||||
#define BCOMM_CMD_ReadEEPROM 0xC7
|
||||
#define BCOMM_CMD_EraseEEPROM 0xC8
|
||||
#define BCOMM_CMD_CheckData 0xC9
|
||||
|
||||
#define BCOMM_CMD_ReplySUCC 0x00
|
||||
#define BCOMM_CMD_ReplyFAIL 0x01
|
||||
|
||||
#define BCOMM_ParaSize 4096
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BCOMM_FMT_TXAddr,
|
||||
BCOMM_FMT_SN,
|
||||
BCOMM_FMT_TYPE,
|
||||
BCOMM_FMT_RXAddr,
|
||||
BCOMM_FMT_LEN_L,
|
||||
BCOMM_FMT_LEN_H,
|
||||
BCOMM_FMT_CKS,
|
||||
BCOMM_FMT_CMD,
|
||||
BCOMM_FMT_PARAM,
|
||||
}BOOTLOAD_COMM_FMT_e;
|
||||
|
||||
#define UPDATE_RECORD_INFO_Size 0x28
|
||||
|
||||
typedef struct {
|
||||
|
||||
uint32_t spiflash_fw_count; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t spiflash_fw_succ; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t spiflash_fw_fail; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
|
||||
uint32_t spiflash_logic_count; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t spiflash_logic_succ; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t spiflash_logic_fail; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
|
||||
uint32_t mcuflash_fw_count; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t mcuflash_fw_succ; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t mcuflash_fw_fail; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
|
||||
uint32_t mcuflash_fw_failcount; //MCU flash <20>̼<EFBFBD><CCBC><EFBFBD>ǰд<C7B0><D0B4>ʧ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD>θ<EFBFBD><CEB8>¹̼<C2B9><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ü<EFBFBD><C3BC><EFBFBD>
|
||||
|
||||
}UPDATE_RECORD_T;
|
||||
|
||||
extern G_SYS_FEATURE_T g_app_feature;
|
||||
extern G_SYS_FEATURE_T g_mcu_app_feature;
|
||||
extern UPDATE_RECORD_T g_update_recode; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
|
||||
|
||||
extern uint8_t g_jump_flag; //<2F><>ת<EFBFBD><D7AA>־λ
|
||||
extern uint32_t g_Boot_Tick; //Bootʱ<74><CAB1><EFBFBD><EFBFBD> <20><>λ<EFBFBD><CEBB>ms
|
||||
extern uint32_t g_Boot_Time; //Bootʱ<74><CAB1> <20><>λ<EFBFBD><CEBB>ms
|
||||
|
||||
uint16_t CRC16_Check(uint8_t * aStr, uint16_t len);
|
||||
uint8_t Launcher_Uart_Upgrade_Process(UART_t *g_rev);
|
||||
|
||||
uint8_t Read_APP_Feature(void);
|
||||
uint8_t MCU_APP_Write(void);
|
||||
uint8_t SPIFLASH_Read_Update_Recode(UPDATE_RECORD_T *info);
|
||||
uint8_t SPIFLASH_Write_Update_Recode(UPDATE_RECORD_T *info);
|
||||
|
||||
void Jump_APP(uint32_t addr);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_LAUNCHER_FUN_H_ */
|
||||
107
MCU_Driver/inc/debug.h
Normal file
107
MCU_Driver/inc/debug.h
Normal file
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* debug.h
|
||||
*
|
||||
* Created on: May 14, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_DEBUG_H_
|
||||
#define MCU_DRIVER_DEBUG_H_
|
||||
|
||||
#include "ch564.h"
|
||||
#include <stdio.h>
|
||||
|
||||
/* UART Printf Definition */
|
||||
#define DEBUG_UART0 1
|
||||
#define DEBUG_UART1 2
|
||||
#define DEBUG_UART2 3
|
||||
#define DEBUG_UART3 4
|
||||
|
||||
/* DEBUG log function. DEBUG printf() <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>*/
|
||||
#ifndef DBG_LOG_EN
|
||||
#define DBG_LOG_EN 1 //DEBUG LOG <20><><EFBFBD><EFBFBD><EFBFBD>ܿ<EFBFBD><DCBF><EFBFBD>
|
||||
#endif
|
||||
|
||||
#define DBG_Particular_EN 1 //<2F><>ϸ<EFBFBD><CFB8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD> -- <20><><EFBFBD>嵽<EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
|
||||
#define DBG_NET_LOG_EN 1 //<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ʼ״̬*/
|
||||
#define DBG_OPT_ActCond_STATUS 1 //<2F><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_MQTT_STATUS 1 //MQTT<54><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_Debug_STATUS 1 //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_LOGIC_STATUS 1 //<2F><EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_DEVICE_STATUS 1 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_NET_STATUS 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
#define DBG_OPT_SYS_STATUS 1 //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ*/
|
||||
#define DBG_BIT_ActCond_STATUS_bit 6
|
||||
#define DBG_BIT_MQTT_STATUS_bit 5
|
||||
#define DBG_BIT_Debug_STATUS_bit 4
|
||||
#define DBG_BIT_LOGIC_STATUS_bit 3
|
||||
#define DBG_BIT_DEVICE_STATUS_bit 2
|
||||
#define DBG_BIT_NET_STATUS_bit 1
|
||||
#define DBG_BIT_SYS_STATUS_bit 0
|
||||
|
||||
#define DBG_BIT_ActCond_STATUS 0x00000040
|
||||
#define DBG_BIT_MQTT_STATUS 0x00000020
|
||||
#define DBG_BIT_Debug_STATUS 0x00000010
|
||||
#define DBG_BIT_LOGIC_STATUS 0x00000008
|
||||
#define DBG_BIT_DEVICE_STATUS 0x00000004
|
||||
#define DBG_BIT_NET_STATUS 0x00000002
|
||||
#define DBG_BIT_SYS_STATUS 0x00000001
|
||||
|
||||
extern uint32_t Dbg_Switch;
|
||||
extern uint32_t SysTick_Now, SysTick_Last, SysTick_Diff;
|
||||
|
||||
void Dbg_Println(int DbgOptBit ,const char *fmt, ...);
|
||||
|
||||
#if DBG_LOG_EN
|
||||
|
||||
#define DBG_Printf(...) printf(__VA_ARGS__)
|
||||
|
||||
#define DBG_SYS_Printf(...) Dbg_Println(DBG_BIT_SYS_STATUS,__VA_ARGS__)
|
||||
|
||||
//#define DBG_SYS_Printf(...) { \
|
||||
// if(Dbg_Switch & DBG_BIT_SYS_STATUS){ \
|
||||
// SysTick_Now = SysTick_1ms; \
|
||||
// SysTick_Diff = SysTick_Now - SysTick_Last; \
|
||||
// SysTick_Last = SysTick_Now; \
|
||||
// printf("%8d [%6d]:",SysTick_Now,SysTick_Diff); \
|
||||
// printf(__VA_ARGS__);printf("\r\n");}}
|
||||
|
||||
#define DBG_Debug_Printf(...) { \
|
||||
if(Dbg_Switch & DBG_BIT_Debug_STATUS){ \
|
||||
SysTick_Now = SysTick_1ms; \
|
||||
SysTick_Diff = SysTick_Now - SysTick_Last; \
|
||||
SysTick_Last = SysTick_Now; \
|
||||
printf("%8d [%6d]:",SysTick_Now,SysTick_Diff); \
|
||||
printf(__VA_ARGS__);printf("\r\n");}}
|
||||
|
||||
#define DBG_log(...) {DBG_Printf("%s %s-%d :",__FILE__,__func__,__LINE__);DBG_Printf(__VA_ARGS__);}
|
||||
|
||||
#else
|
||||
|
||||
#define DBG_Printf(...)
|
||||
#define DBG_SYS_Printf(...)
|
||||
#define DBG_Debug_Printf(...)
|
||||
|
||||
#define DBG_log(...)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
extern volatile uint32_t SysTick_100us;
|
||||
extern volatile uint32_t SysTick_1ms;
|
||||
extern volatile uint32_t SysTick_1s;
|
||||
|
||||
void Systick_Init(void);
|
||||
void Delay_Us(uint32_t n);
|
||||
void Delay_Ms(uint32_t n);
|
||||
|
||||
void my_printf(const char *fmt, ...);
|
||||
void Dbg_Print_Buff(int DbgOptBit ,const char *cmd ,uint8_t *buff,uint32_t len);
|
||||
|
||||
#endif /* MCU_DRIVER_DEBUG_H_ */
|
||||
34
MCU_Driver/inc/flash_mem_addr.h
Normal file
34
MCU_Driver/inc/flash_mem_addr.h
Normal file
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* flash_mem_addr.h
|
||||
* Description : <20><><EFBFBD>ļ<EFBFBD>Ϊ<EFBFBD>ⲿFlash <20><>ַӳ<D6B7><D3B3><EFBFBD><EFBFBD> Size: 0x00200000
|
||||
*
|
||||
* Created on: Jul 31, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef _FLASH_MEM_ADDR_H_
|
||||
#define _FLASH_MEM_ADDR_H_
|
||||
|
||||
/*APP<50><50><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
#define SPIFLASH_APP_Start_Addr 0x00000000
|
||||
|
||||
#define SPIFLASH_APP_FEATURE_Addr 0x00000000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 512Byte
|
||||
|
||||
|
||||
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000200 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ - 512Byte
|
||||
|
||||
#define SPIFLASH_APP_Data_Start_Addr 0x00004000
|
||||
#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF
|
||||
|
||||
#define SPIFLASH_APP_End_Addr 0x0006FFFF
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
#define SPIFLASH_LOGIC_FILE_Start_Addr 0x00070000
|
||||
#define SPIFLASH_LOGIC_DataFlag_ADDRESS 0x00070000 //<2F>ļ<EFBFBD><C4BC><EFBFBD>־λ - 4Byte
|
||||
#define SPIFLASH_LOGIC_DataSize_ADDRESS 0x00070004 //<2F>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> - 4Byte
|
||||
#define SPIFLASH_LOGIC_DataMD5_ADDRESS 0x00070008 //<2F>ļ<EFBFBD>MD5У<35><D0A3>ֵ - 16Byte
|
||||
#define SPIFLASH_LOGIC_DataStart_ADDRESS 0x00070200 //<2F>ļ<EFBFBD><C4BC><EFBFBD>ʼ<EFBFBD><CABC>ַ
|
||||
#define SPIFLASH_LOGIC_FILE_End_Addr 0x000FFFFF
|
||||
|
||||
|
||||
#endif /* MCU_DRIVER_INC_FLASH_MEM_ADDR_H_ */
|
||||
20
MCU_Driver/inc/led.h
Normal file
20
MCU_Driver/inc/led.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* led.h
|
||||
*
|
||||
* Created on: May 15, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_LED_H_
|
||||
#define MCU_DRIVER_INC_LED_H_
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
#define SYS_LED_ON GPIOB_ResetBits(GPIO_Pin_12)
|
||||
#define SYS_LED_OFF GPIOA_SetBits(GPIO_Pin_12)
|
||||
#define SYS_LED_FLIP GPIOA_InverseBits(GPIO_Pin_12)
|
||||
|
||||
void SYS_LED_Init(void);
|
||||
void SYS_LED_Task(void);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_LED_H_ */
|
||||
86
MCU_Driver/inc/log_api.h
Normal file
86
MCU_Driver/inc/log_api.h
Normal file
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* log_api.h
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef _LOG_API_H_
|
||||
#define _LOG_API_H_
|
||||
|
||||
#include "ch564.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define LogType_Enable 1 //LOGʹ<47><CAB9>
|
||||
|
||||
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD>Ͷ<EFBFBD><CDB6><EFBFBD>*/
|
||||
#define LogType_Launcher 0x01 //Launcher<65><72>Ϣ<EFBFBD><CFA2>¼
|
||||
#define LogType_SYS_Record 0x02 //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>¼
|
||||
#define LogType_Device_COMM 0x03 //<2F>豸ͨѶ<CDA8><D1B6>¼
|
||||
#define LogType_Device_Online 0x04 //<2F>豸ͨѶ״̬<D7B4><CCAC>¼
|
||||
#define LogType_Global_Parameters 0x05 //<2F><><EFBFBD><EFBFBD><EFBFBD>豸״̬<D7B4><CCAC><EFBFBD>ڼ<EFBFBD>¼
|
||||
#define LogType_Net_COMM 0x06 //<2F><><EFBFBD><EFBFBD>ͨѶ<CDA8><D1B6>¼
|
||||
#define LogType_Logic_Record 0x07 //<2F><EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼
|
||||
|
||||
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD> - <20><>ʼ״̬*/
|
||||
#define LogType_Launcher_SWITCH 1
|
||||
#define LogType_SYS_Record_SWITCH 1
|
||||
#define LogType_Device_COMM_SWITCH 1
|
||||
#define LogType_Device_Online_SWITCH 1
|
||||
#define LogType_Global_Parameters_SWITCH 1
|
||||
#define LogType_Net_COMM_SWITCH 1
|
||||
#define LogType_Logic_Record_SWITCH 1
|
||||
|
||||
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD>λ*/
|
||||
#define LogType_Launcher_bit 0
|
||||
#define LogType_SYS_Record_bit 1
|
||||
#define LogType_Device_COMM_bit 2
|
||||
#define LogType_Device_Online_bit 3
|
||||
#define LogType_Global_Parameters_bit 4
|
||||
#define LogType_Net_COMM_bit 5
|
||||
#define LogType_Logic_Record_bit 6
|
||||
|
||||
/*<2A><>־<EFBFBD><D6BE><EFBFBD>ز<EFBFBD><D8B2><EFBFBD>*/
|
||||
#define LogInfo_Device_Online 0x01 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
#define LogInfo_Device_Offline 0x02 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
|
||||
typedef enum{
|
||||
LLauncher_App_Check = 0x01, //У<><D0A3>APP
|
||||
LLauncher_Read_App, //<2F><>ȡAPP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50><50><EFBFBD><EFBFBD>д<EFBFBD>뵽MCU FLash<73><68>
|
||||
LLauncher_Write_Flash, //дFlash
|
||||
LLauncher_Factory_Reset, //<2F>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LLauncher_Reset_Source, //<2F><>λԴ
|
||||
LLauncher_RCUKey_State, //RCU<43><55><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>¼
|
||||
}LOGTYPE_Launcher_E;
|
||||
|
||||
typedef enum {
|
||||
LSYS_PHY_Change = 0x01, //PHY״̬<D7B4>仯<EFBFBD><E4BBAF>¼
|
||||
LSYS_DevInfo_Error, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
LSYS_API_State, //<2F><><EFBFBD><EFBFBD>״̬
|
||||
LSYS_NET_ARGC, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LSYS_MQTT_ARGC, //MQTT<54><54><EFBFBD><EFBFBD>
|
||||
LSYS_Server_Comm_State, //<2F>ƶ<EFBFBD>ͨѶ״̬<D7B4><CCAC>¼
|
||||
LSYS_NET_DefaultARGC, //<2F><><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD>
|
||||
LSYS_RCUKey_State, //RCU<43><55><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>¼
|
||||
}LOGTYPR_SYSRecord;
|
||||
|
||||
typedef enum{
|
||||
LCOMM_ASK_TO_Reply = 0x01, //<2F><>ѯ<EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>
|
||||
LCOMM_Send_Control, //RCU<43>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LCOMM_Control_Reply, //RCU<43><55><EFBFBD>ƻظ<C6BB><D8B8><EFBFBD><EFBFBD><EFBFBD>
|
||||
LCOMM_Adjust_Baud, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}LOGTYPE_DEV_COMM;
|
||||
|
||||
typedef enum{
|
||||
LGlobal_Para = 0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
LGlobal_Dev, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
}LOGTYPE_Global_E;
|
||||
|
||||
void LOG_Launcher_APP_Check_Record(uint8_t state);
|
||||
void LOG_Launcher_Read_App_Record(uint8_t state);
|
||||
void LOG_Launcher_Write_Flash_Record(uint32_t addr,uint16_t len);
|
||||
void LOG_Launcher_Factory_Reset_Record(uint8_t state);
|
||||
void LOG_Launcher_Reset_Source_Record(uint8_t sour);
|
||||
void LOG_Launcher_RCU_Key_State_Record(uint8_t state);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_LOG_API_H_ */
|
||||
123
MCU_Driver/inc/mcu_flash.h
Normal file
123
MCU_Driver/inc/mcu_flash.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* mcu_flash.h
|
||||
*
|
||||
* Created on: Aug 2, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_MCU_FLASH_H_
|
||||
#define MCU_DRIVER_INC_MCU_FLASH_H_
|
||||
|
||||
#include "ch564.h"
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#define MCU_APP_Flash_PageSize 0x00001000 //MCU FlashҳΪ4096Byte
|
||||
#define APP_Flash_WriteNum 0x05 //APPд<50><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
#define App_Procedure_Ready 0x66 //APP<50><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
|
||||
#define App_Procedure_Not_Ready 0x44 //Appδ<CEB4><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
|
||||
|
||||
//MCU Flash Address range(0x0 -- 0x6FFFF) Size(448K)
|
||||
#define MCU_APP_Flash_Start_Addr 0x00007000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
|
||||
#define MCU_APP_Data_Start_Addr 0x00007000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
|
||||
#define MCU_APP_Data_End_Addr 0x00027DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
#define MCU_APP_Feature_Addr 0x00027E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
#define MCU_APP_Flash_End_Addr 0x00027FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
|
||||
#define MCU_APP_Feature_PageAddr 0x00027000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
|
||||
#define MCU_APP_Feature_PageOffset 0x00000E00 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
|
||||
#define APP_FEATURE_SIZE 0x0200 //512Byte
|
||||
|
||||
//EEPROM Address range(0x70000 -- 0x77FFF) Size(32K)
|
||||
#define MCU_EEPROM_Start_Addr 0x00070000
|
||||
#define MCU_EEPROM_MCUDevInfo_Address 0x00070000 //MCU <20>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2>ַ<EFBFBD>̶<EFBFBD>Ϊ0x00070000<30><30><EFBFBD><EFBFBD>СΪ4096 <20><><EFBFBD><EFBFBD><EFBFBD>ɸĶ<C9B8>
|
||||
#define MCU_EEPROM_End_Addr 0x00078000
|
||||
|
||||
|
||||
|
||||
/* EEPROM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD>
|
||||
* FLAG - 1Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
|
||||
* LEN - 2Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||||
* CHECK - 1Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>
|
||||
* DATA - nByte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* */
|
||||
#define EEPROM_SVAE_FLAG 0xAE
|
||||
#define EEPROM_DATA_Size_Max 0x40 //Ŀǰ<C4BF><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ100Byte
|
||||
#define EEPROM_PARA_Size 50
|
||||
#define EEPROM_DEV_NAME_Size 32
|
||||
|
||||
#define EEPROM_Offset_SaveFlag 0x00
|
||||
#define EEPROM_Offset_Datalen 0x01
|
||||
#define EEPROM_Offset_Check 0x03
|
||||
#define EEPROM_Offset_Data 0x04
|
||||
|
||||
|
||||
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽṹ<DDBD><E1B9B9>
|
||||
* ע<>⣺<EFBFBD><E2A3BA><EFBFBD><EFBFBD>risc-v<><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD>ֽڶ<D6BD><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* <20><><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD>Flash/MCU Flash<73>е<EFBFBD>˳<EFBFBD><CBB3><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD>嶨<EFBFBD><E5B6A8>˳<EFBFBD><CBB3><EFBFBD><EFBFBD>һ<EFBFBD>£<EFBFBD>ʹ<EFBFBD><CAB9>ʱ<EFBFBD><CAB1>ע<EFBFBD><D7A2>
|
||||
* */
|
||||
typedef enum{
|
||||
Feature_Check = 0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 512Byte <20><>CRCУ<43><D0A3> - 2Byte
|
||||
Feature_AppFlag = 0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50>־λ - 1Byte
|
||||
Feature_AppStart = 0x03, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50>ʼ<EFBFBD><CABC>ַ - 4Byte
|
||||
Feature_AppEnd = 0x07, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 4Byte
|
||||
Feature_AppCrcSize = 0x0B, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRC<52>ij<EFBFBD><C4B3><EFBFBD> - 2Byte
|
||||
Feature_AppCrcLen = 0x0D, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С - 2Byte
|
||||
Feature_AppFlashCrc = 0x0F, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRC
|
||||
}FEATURE_E;
|
||||
|
||||
#define APP_Feature_CRC_Size 497
|
||||
|
||||
typedef struct{
|
||||
uint8_t app_flag; //APP <20><>־λ
|
||||
uint8_t app_crc[APP_Feature_CRC_Size]; //APP CRCУ<43><D0A3>ֵ
|
||||
|
||||
uint16_t app_crc_size; //APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
|
||||
uint16_t app_crc_len; //APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||||
uint16_t crc_check; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRCֵ - <20><><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7>Ϸ<EFBFBD>
|
||||
|
||||
uint32_t app_start_addr; //APP<50><50>ʼ<EFBFBD><CABC>ַ
|
||||
uint32_t app_end_addr; //APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
}G_SYS_FEATURE_T;
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU EEPROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
typedef struct{
|
||||
|
||||
uint8_t dev_addr; //<2F>豸<EFBFBD><E8B1B8>ַ
|
||||
uint8_t dev_type; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
uint8_t dev_boot_ver; //<2F>豸Boot<6F><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
|
||||
uint8_t dev_app_ver; //<2F>豸APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
|
||||
uint8_t dev_name_len; //<2F>豸<EFBFBD><E8B1B8><EFBFBD>Ƶij<C6B5><C4B3><EFBFBD>
|
||||
uint8_t dev_name[EEPROM_DEV_NAME_Size]; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
|
||||
}E_MCU_DEV_INFO;
|
||||
|
||||
|
||||
|
||||
extern E_MCU_DEV_INFO g_mcu_dev;
|
||||
extern uint8_t g_read_buff[4100];
|
||||
extern uint8_t g_flash_buff[4100];
|
||||
|
||||
void EEPROM_Init(void);
|
||||
uint8_t MCU_APP_Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
|
||||
uint8_t MCU_APP_Flash_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr);
|
||||
uint8_t MCU_APP_Flash_Erase(uint32_t readAddr,uint16_t NumByteToWrite);
|
||||
uint8_t MCU_APP_Flash_ALLErase(void);
|
||||
uint8_t MCU_EEPROM_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
|
||||
uint8_t MCU_EEPROM_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr);
|
||||
uint8_t MCU_EEPROM_Erase(uint32_t readAddr,uint16_t NumByteToWrite);
|
||||
uint8_t MCU_EEPROM_ALLErase(void);
|
||||
|
||||
uint8_t EEPROM_CheckSum(uint8_t *data,uint16_t len);
|
||||
uint8_t EEPROM_ReadMCUDevInfo(E_MCU_DEV_INFO *info);
|
||||
uint8_t EEPROM_WriteMCUDevInfo(E_MCU_DEV_INFO *info);
|
||||
void EEPROM_Default_MCUDevInfo(E_MCU_DEV_INFO *info);
|
||||
void EEPROM_Validate_MCUDevInfo(E_MCU_DEV_INFO *info);
|
||||
|
||||
uint8_t Read_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info);
|
||||
uint8_t Write_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info);
|
||||
void APP_Feature_Info_Printf(G_SYS_FEATURE_T *feature_info);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_MCU_FLASH_H_ */
|
||||
42
MCU_Driver/inc/rtc.h
Normal file
42
MCU_Driver/inc/rtc.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* rtc.h
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_RTC_H_
|
||||
#define MCU_DRIVER_INC_RTC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ch564.h"
|
||||
|
||||
typedef struct{
|
||||
uint8_t second;
|
||||
uint8_t minute;
|
||||
uint8_t hour;
|
||||
uint8_t week;
|
||||
uint8_t day;
|
||||
uint8_t month;
|
||||
uint8_t year;
|
||||
}S_RTC;
|
||||
|
||||
typedef struct{
|
||||
uint32_t hour;
|
||||
uint16_t minute;
|
||||
uint16_t second;
|
||||
}G_CORE_RTC;
|
||||
|
||||
extern S_RTC RTC_Raw_Data;
|
||||
extern uint32_t Log_Time_ms;
|
||||
|
||||
void RTC_Init(void);
|
||||
uint8_t HEX_Conversion_To_DEC(uint8_t c_num);
|
||||
uint8_t DEV_Conversion_To_HEX(uint8_t c_num);
|
||||
uint32_t RTC_Conversion_To_Unix(S_RTC *rtc_time);
|
||||
void Unix_Conversion_To_RTC(S_RTC *rtc_time,uint32_t utc_tick);
|
||||
uint8_t RTC_ReadDate(S_RTC *psRTC);
|
||||
uint8_t RTC_WriteDate(S_RTC SetRTC);
|
||||
void RTC_TASK(void);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_RTC_H_ */
|
||||
41
MCU_Driver/inc/rw_logging.h
Normal file
41
MCU_Driver/inc/rw_logging.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* rw_logging.h
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_RW_LOGGING_H_
|
||||
#define MCU_DRIVER_INC_RW_LOGGING_H_
|
||||
|
||||
#include "ch564.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define APPFlag_UartUpgrade_Reset 0xBBC1 //APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
|
||||
|
||||
//<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
|
||||
#define LOG_Data_Hand 0xA5 //LOG<4F><47><EFBFBD><EFBFBD>ͷ
|
||||
#define Log_Data_End 0x5A //LOG<4F><47><EFBFBD><EFBFBD>β
|
||||
#define Log_Data_Len_MAX 512 //<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>512Byte
|
||||
|
||||
/*<2A><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ*/
|
||||
typedef enum{
|
||||
S_Log_Hand,
|
||||
S_Log_SN, //<2F><>־ÿ<D6BE><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
|
||||
S_Log_Len,
|
||||
S_Log_Len_8,
|
||||
S_Log_Check,
|
||||
S_Log_Date_H, //<2F>꣺5bit <20>£<EFBFBD>5bit <20>գ<EFBFBD>5bit
|
||||
S_Log_Date_L,
|
||||
S_Log_Type,
|
||||
S_Log_Time8B, //Сʱʱ<CAB1><CAB1><EFBFBD><EFBFBD>
|
||||
S_Log_Time16B,
|
||||
S_Log_Time24B,
|
||||
S_Log_Time32B,
|
||||
S_Log_Data,
|
||||
}Sram_Log_Data_Format;
|
||||
|
||||
uint8_t Data_CheckSum(uint8_t* data,uint16_t len);
|
||||
uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_RW_LOGGING_H_ */
|
||||
65
MCU_Driver/inc/spi_flash.h
Normal file
65
MCU_Driver/inc/spi_flash.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* spi_flash.h
|
||||
*
|
||||
* Created on: May 20, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_SPI_FLASH_H_
|
||||
#define MCU_DRIVER_INC_SPI_FLASH_H_
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
#define Flash_CS_H GPIOA_SetBits(GPIO_Pin_11)
|
||||
#define Flash_CS_L GPIOA_ResetBits(GPIO_Pin_11)
|
||||
|
||||
#define Flash_ADDRESS_MAX 0x00200000
|
||||
|
||||
/***********ָ<><D6B8><EFBFBD><EFBFBD>**********/
|
||||
//Read
|
||||
#define P24Q40H_ReadData 0x03
|
||||
#define P24Q40H_FastReadData 0x0B
|
||||
#define P24Q40H_FastReadDual 0x3B
|
||||
//Program and Erase
|
||||
#define P24Q40H_PageErase 0x81
|
||||
#define P24Q40H_SectorErase 0x20
|
||||
#define P24Q40H_BlockErase 0xD8
|
||||
#define P24Q40H_ChipErase 0xC7
|
||||
#define P24Q40H_PageProgram 0x02
|
||||
//Protection
|
||||
#define P24Q40H_WriteEnable 0x06
|
||||
#define P24Q40H_WriteDisable 0x04
|
||||
//Status Register
|
||||
#define P24Q40H_ReadStatusReg 0x05
|
||||
#define P24Q40H_WriteStatusReg 0x01
|
||||
//Other Commands
|
||||
#define P24Q40H_PowerDown 0xB9
|
||||
#define P24Q40H_ReleasePowerDown 0xAB
|
||||
#define P24Q40H_ReadManufactureID 0x90
|
||||
#define P24Q40H_ReadDeviceID 0x9F
|
||||
#define P24Q40H_ResetEnable 0x66
|
||||
#define P24Q40H_Reset 0x99
|
||||
|
||||
extern uint8_t Flash_Buffer[4150];
|
||||
|
||||
void SPI_FLASH_Init(void);
|
||||
uint8_t Flash_ReadSR(void);
|
||||
void Flash_WriteSR(uint8_t sr_val);
|
||||
void Flash_Write_Enable(void);
|
||||
void Flash_Write_Disable(void);
|
||||
uint16_t Flash_ReadID(void);
|
||||
uint8_t Flash_Wait_Busy(void);
|
||||
void Flash_PowerDown(void);
|
||||
void Flash_Wakeup(void);
|
||||
void Flash_Erase_Chip(void);
|
||||
void Flash_Erase_Block(uint32_t BLK_ID);
|
||||
void Flash_Erase_Sector(uint32_t DST_ID);
|
||||
void Flash_Erase_Page(uint32_t Page_ID);
|
||||
void Flash_Erase_Pageaddr(uint32_t Page_addr);
|
||||
void Flash_Read(uint8_t* pBuffer,uint16_t NumByteToRead,uint32_t ReadAddr);
|
||||
void Flash_Write_Page(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
|
||||
void Flash_Write_NoCheck(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
|
||||
void Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t WriteAddr);
|
||||
|
||||
|
||||
#endif /* MCU_DRIVER_INC_SPI_FLASH_H_ */
|
||||
46
MCU_Driver/inc/spi_sram.h
Normal file
46
MCU_Driver/inc/spi_sram.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* spi_sram.h
|
||||
*
|
||||
* Created on: May 16, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_SPI_SRAM_H_
|
||||
#define MCU_DRIVER_INC_SPI_SRAM_H_
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
#define SRAM_CE_H GPIOA_ResetBits(GPIO_Pin_11)
|
||||
#define SRAM_CE_L GPIOA_SetBits(GPIO_Pin_11)
|
||||
|
||||
#define SRAM_CMD_Read 0x03
|
||||
#define SRAM_CMD_Fast_Read 0x0B
|
||||
#define SRAM_CMD_Fast_Read_Quad 0xEB
|
||||
#define SRAM_CMD_Write 0x02
|
||||
#define SRAM_CMD_Quad_Write 0x38
|
||||
#define SRAM_CMD_Enter_Quad_Mode 0x35
|
||||
#define SRAM_CMD_Exit_Quad_Mode 0xF5
|
||||
#define SRAM_CMD_Reset_Enable 0x66
|
||||
#define SRAM_CMD_Reset 0x99
|
||||
#define SRAM_CMD_Wrap_Boundary_Toggle 0xC0
|
||||
#define SRAM_CMD_Read_ID 0x9F
|
||||
|
||||
#define SRAM_ADDRESS_MAX 0x00800000
|
||||
|
||||
|
||||
void SPI_SRAM_Init(void);
|
||||
void SRAM_Write_Byte(uint8_t wdate,uint32_t add);
|
||||
uint8_t SRAM_Read_Byte(uint32_t add);
|
||||
void SRAM_Write_Word(uint16_t wdate,uint32_t add);
|
||||
uint16_t SRAM_Read_Word(uint32_t add);
|
||||
void SRAM_Write_DW(uint32_t wdate,uint32_t add);
|
||||
uint32_t SRAM_Read_DW(uint32_t add);
|
||||
uint8_t SRAM_Read_ID_Opeartion(void);
|
||||
void SRAM_Reset_Operation(void);
|
||||
|
||||
void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add);
|
||||
void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add);
|
||||
|
||||
|
||||
|
||||
#endif /* MCU_DRIVER_INC_SPI_SRAM_H_ */
|
||||
33
MCU_Driver/inc/sram_mem_addr.h
Normal file
33
MCU_Driver/inc/sram_mem_addr.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* sram_virt_mem_addr.h
|
||||
* <20>ⲿSRAM<41><4D>ַ<EFBFBD>ռ<EFBFBD><D5BC>滮 0x00000000 ~ 0x00800000
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef _SRAM_MEM_ADDR_H_
|
||||
#define _SRAM_MEM_ADDR_H_
|
||||
|
||||
|
||||
/*
|
||||
* 2025-07-29 <20><EFBFBD>SRAM<41>洢<EFBFBD><E6B4A2>ַ 0x00400000 ~ 0x007FFFFF SIZE:4MByte
|
||||
* 1<><31><EFBFBD>ĶԿռ<D4BF><D5BC><EFBFBD>ַУ<D6B7>飬<EFBFBD><E9A3AC>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD>쳣
|
||||
* 2<><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȥ<EFBFBD><C8A5>û<EFBFBD><C3BB>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD>
|
||||
*
|
||||
* */
|
||||
#define SRAM_LOG_WRITE_Address 0x00400000 //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>ʼ<EFBFBD><CABC>ַ - <20><>ǰSRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ - 4Byte
|
||||
#define SRAM_LOG_READ_Address 0x00400004 //<2F><>־<EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>ȡ<EFBFBD><C8A1>ַ - 4Byte
|
||||
#define SRAM_LOG_Serial_Number 0x00400008 //<2F><>־<EFBFBD><D6BE><EFBFBD>ű<EFBFBD><C5B1><EFBFBD><EFBFBD><EFBFBD>ַ - 2Byte Ŀǰֻʹ<D6BB><CAB9>1Byte
|
||||
#define SRAM_LOGFlag_Reset_Source 0x0040000A //Launcher<65><72><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> - <20><>APPʹ<50><CAB9> - 1Byte
|
||||
#define SRAM_LOGFlag_Addr_INIT 0x0040000B //Launcher<65><72>¼<EFBFBD><C2BC>ַ<EFBFBD><D6B7>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>־λ - <20><>APPʹ<50><CAB9> - 1Byte
|
||||
#define SRAM_LOGFlag_Debug_Switch 0x0040000C //Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ 4Byte - <20><>APPʹ<50><CAB9>
|
||||
#define SRAM_APPFlag_Reset_Source 0x00400010 //App<70><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ 2Byte - <20><>Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣʹ<CFA2><CAB9> 0xBBC1
|
||||
#define SRAM_LOG_DATA_Address 0x00400100 //<2F><>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>ַ
|
||||
#define SRAM_LOG_End_Address 0x007FFFFF //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 0x007FFFFF
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* MCU_DRIVER_INC_SRAM_MEM_ADDR_H_ */
|
||||
20
MCU_Driver/inc/timer.h
Normal file
20
MCU_Driver/inc/timer.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* timer.h
|
||||
*
|
||||
* Created on: May 16, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_TIMER_H_
|
||||
#define MCU_DRIVER_INC_TIMER_H_
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
|
||||
extern volatile uint32_t Time0_100us;
|
||||
extern volatile uint32_t Time0_1ms;
|
||||
|
||||
void TIMER0_Init(void);
|
||||
void Timer0_Task(void);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_TIMER_H_ */
|
||||
100
MCU_Driver/inc/uart.h
Normal file
100
MCU_Driver/inc/uart.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* uart.h
|
||||
*
|
||||
* Created on: May 14, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef MCU_DRIVER_INC_UART_H_
|
||||
#define MCU_DRIVER_INC_UART_H_
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
|
||||
#define MCU485_EN1_H GPIOD_SetBits(GPIO_Pin_21)
|
||||
#define MCU485_EN1_L GPIOD_ResetBits(GPIO_Pin_21)
|
||||
#define MCU485_EN2_H GPIOB_SetBits(GPIO_Pin_15)
|
||||
#define MCU485_EN2_L GPIOB_ResetBits(GPIO_Pin_15)
|
||||
|
||||
#define UART_COMMBUSY_IDLE_Flag 0x00
|
||||
#define UART_COMMBUSY_RECV_Flag 0x01
|
||||
#define UART_COMMBUSY_SEND_Flag 0x02
|
||||
|
||||
#define Recv_2400_TimeOut 10 //ms
|
||||
#define Recv_9600_TimeOut 5 //ms
|
||||
#define Recv_115200_TimeOut 3 //ms
|
||||
#define Recv_512000_TimeOut 3 //ms
|
||||
|
||||
#define USART_BUFFER_SIZE 512
|
||||
|
||||
|
||||
typedef void (*Uart_prt)(uint8_t * ,uint16_t );
|
||||
typedef uint8_t (*Uart_set_prt)(uint32_t );
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UART_0,
|
||||
UART_1,
|
||||
UART_2,
|
||||
UART_3,
|
||||
UART_MAX,
|
||||
}UART_IDX;
|
||||
|
||||
typedef struct{
|
||||
|
||||
uint8_t RecvBuffer[USART_BUFFER_SIZE];
|
||||
uint8_t deal_buff[USART_BUFFER_SIZE];
|
||||
uint8_t ackBuffer[USART_BUFFER_SIZE];
|
||||
uint8_t SendBuffer[USART_BUFFER_SIZE];
|
||||
|
||||
uint8_t SendCount; //<2F>ܷ<EFBFBD><DCB7>ʹ<EFBFBD><CDB4><EFBFBD>
|
||||
uint8_t SendCnt; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD>
|
||||
uint8_t CommBusy; //ͨѶ<CDA8><D1B6>æ״̬
|
||||
|
||||
uint8_t Receiving;
|
||||
uint8_t sn;
|
||||
uint8_t pc_addr;
|
||||
uint8_t cmd;
|
||||
|
||||
uint8_t appFlag;
|
||||
uint8_t writeFlag;
|
||||
uint8_t ChangeBaudFlag; //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>־λ
|
||||
|
||||
uint16_t RecvLen;
|
||||
uint16_t deal_len;
|
||||
uint16_t ackLen;
|
||||
uint16_t SendLen; //<2F><><EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD>
|
||||
|
||||
uint32_t CommBaud; //ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʹ<CAB1><CAB9>
|
||||
uint32_t ackValidity; //<2F><><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>Ч<EFBFBD><D0A7>
|
||||
uint32_t SendValidDuration; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1>
|
||||
uint32_t SendValidTick; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1><EFBFBD><EFBFBD>
|
||||
uint32_t SendInterval; //<2F><><EFBFBD>ͼ<EFBFBD><CDBC><EFBFBD>
|
||||
uint32_t SendTick; //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||||
|
||||
uint32_t RecvTimeout;
|
||||
uint32_t RecvIdleTiming;
|
||||
uint32_t SendIdleTick; //<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||||
|
||||
Uart_prt send_data_cf;
|
||||
Uart_set_prt set_baud_cf;
|
||||
}UART_t;
|
||||
|
||||
extern UART_t g_uart[UART_MAX];
|
||||
|
||||
void UARTx_Init(UART_IDX uart_id, uint32_t buad);
|
||||
void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud);
|
||||
|
||||
void UART0_RECEIVE(void);
|
||||
void UART1_RECEIVE(void);
|
||||
void UART2_RECEIVE(void);
|
||||
void UART3_RECEIVE(void);
|
||||
|
||||
uint8_t UART0_ChangeBaud(uint32_t baudrate);
|
||||
uint8_t UART1_ChangeBaud(uint32_t baudrate);
|
||||
uint8_t UART2_ChangeBaud(uint32_t baudrate);
|
||||
uint8_t UART3_ChangeBaud(uint32_t baudrate);
|
||||
|
||||
void Uart0_Task(void);
|
||||
|
||||
#endif /* MCU_DRIVER_INC_UART_H_ */
|
||||
33
MCU_Driver/led.c
Normal file
33
MCU_Driver/led.c
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* led.c
|
||||
*
|
||||
* Created on: 2025<32><35>5<EFBFBD><35>15<31><35>
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#include "led.h"
|
||||
#include "debug.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
void SYS_LED_Init(void)
|
||||
{
|
||||
GPIOA_ModeCfg(GPIO_Pin_12,GPIO_ModeOut_PP); //LED
|
||||
|
||||
SYS_LED_ON;
|
||||
}
|
||||
|
||||
void SYS_LED_Task(void)
|
||||
{
|
||||
static uint32_t led_tick = 0;
|
||||
|
||||
if(SysTick_1ms - led_tick >= 1000 ){
|
||||
led_tick = SysTick_1ms;
|
||||
|
||||
SYS_LED_FLIP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
175
MCU_Driver/log_api.c
Normal file
175
MCU_Driver/log_api.c
Normal file
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* log_api.c
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#include "rw_logging.h"
|
||||
#include "SPI_SRAM.h"
|
||||
#include "Log_api.h"
|
||||
#include "string.h"
|
||||
|
||||
uint32_t SYS_Log_Switch = (LogType_Launcher_SWITCH << LogType_Launcher_bit) + \
|
||||
(LogType_SYS_Record_SWITCH << LogType_SYS_Record_bit) + \
|
||||
(LogType_Device_COMM_SWITCH << LogType_Device_COMM_bit) + \
|
||||
(LogType_Device_Online_SWITCH << LogType_Device_Online_bit) + \
|
||||
(LogType_Global_Parameters_SWITCH << LogType_Global_Parameters_bit) + \
|
||||
(LogType_Net_COMM_SWITCH << LogType_Net_COMM_bit) + \
|
||||
(LogType_Logic_Record_SWITCH << LogType_Logic_Record_bit);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_APP_Check_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - У<><D0A3>APP
|
||||
* Input :
|
||||
state :״̬
|
||||
0x00:<3A><>ͬ<EFBFBD><CDAC>
|
||||
0x01:<3A>汾<EFBFBD>Ų<EFBFBD>ͬ<EFBFBD><CDAC>
|
||||
0x02:CRCУ<43>鲻ͬ<E9B2BB><CDAC>
|
||||
0x03:Flash<73><68>APP<50><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x04:Flash APP<50><50><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x05:Flash<73><68>APP<50><50>־δ<D6BE><CEB4>λ<EFBFBD><CEBB>
|
||||
0x06:Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x07:MCU Flash<73><68><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x08:MCU Flash<73><68>APP<50><50>־δ<D6BE><CEB4>λ<EFBFBD><CEBB>
|
||||
0x09:MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_APP_Check_Record(uint8_t state)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[3] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_App_Check;
|
||||
temp_buff[1] = state;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,2);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_APP_Check_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - У<><D0A3>APP
|
||||
* Input :
|
||||
state :״̬
|
||||
0x00:<3A>ɹ<EFBFBD>
|
||||
0x01:ʧ<><CAA7>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_Read_App_Record(uint8_t state)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[3] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_Read_App;
|
||||
temp_buff[1] = state;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,2);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_Write_Flash_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - Flashд<68><D0B4>
|
||||
* Input :
|
||||
addr :д<><D0B4><EFBFBD><EFBFBD>ַ
|
||||
len :д<>볤<EFBFBD><EBB3A4>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_Write_Flash_Record(uint32_t addr,uint16_t len)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[7] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_Write_Flash;
|
||||
temp_buff[1] = addr & 0xFF;
|
||||
temp_buff[2] = (addr >> 8) & 0xFF;
|
||||
temp_buff[3] = (addr >> 16) & 0xFF;
|
||||
temp_buff[4] = (addr >> 24) & 0xFF;
|
||||
temp_buff[5] = len & 0xFF;
|
||||
temp_buff[6] = (len >> 8) & 0xFF;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,7);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_Factory_Reset_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - <20>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
state<74><65>
|
||||
0x01:д<><D0B4><EFBFBD>ɹ<EFBFBD>
|
||||
0x02:д<><D0B4>ʧ<EFBFBD><CAA7> - û<>г<EFBFBD><D0B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x03:д<><D0B4>ʧ<EFBFBD><CAA7> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_Factory_Reset_Record(uint8_t state)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[3] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_Factory_Reset;
|
||||
temp_buff[1] = state;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,2);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_Factory_Reset_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - <20><>λԴ
|
||||
* Input :
|
||||
sour<75><72><EFBFBD><EFBFBD>λ<EFBFBD>ź<EFBFBD>ֵ
|
||||
0x00<30><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
|
||||
0x01<30><31><EFBFBD>ϵ縴λ
|
||||
0x02<30><32><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD><C5B9><EFBFBD>λ
|
||||
0x03<30><33><EFBFBD>ⲿ<EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>λ
|
||||
0x05<30><35><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʱ<EFBFBD>ĸ<EFBFBD>λ - ͨ<><CDA8>WCHISPTool<6F><6C>¼<EFBFBD><C2BC><EFBFBD>ĸ<EFBFBD>λ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_Reset_Source_Record(uint8_t sour)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[3] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_Reset_Source;
|
||||
temp_buff[1] = sour;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,2);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : LOG_Launcher_Factory_Reset_Record
|
||||
* Description : Launcher<65><72><EFBFBD><EFBFBD> - RCU<43><55><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>
|
||||
* Input :
|
||||
state<74><65>״̬
|
||||
0x01<30><31><EFBFBD>㰴
|
||||
0x02<30><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
0x03<30><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿ<EFBFBD>
|
||||
0x04<30><34><EFBFBD>ﵽ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void LOG_Launcher_RCU_Key_State_Record(uint8_t state)
|
||||
{
|
||||
if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) )
|
||||
{
|
||||
uint8_t temp_buff[3] = {0};
|
||||
|
||||
temp_buff[0] = LLauncher_RCUKey_State;
|
||||
temp_buff[1] = state;
|
||||
|
||||
Log_write_sram(LogType_Launcher,temp_buff,2);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
638
MCU_Driver/mcu_flash.c
Normal file
638
MCU_Driver/mcu_flash.c
Normal file
@@ -0,0 +1,638 @@
|
||||
/*
|
||||
* mcu_flash.c
|
||||
*
|
||||
* Created on: Aug 2, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "includes.h"
|
||||
#include <string.h>
|
||||
|
||||
E_MCU_DEV_INFO g_mcu_dev;
|
||||
|
||||
uint8_t g_read_buff[4100] = {0};
|
||||
uint8_t g_flash_buff[4100] = {0};
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_Init
|
||||
* Description : EEPROM <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
void EEPROM_Init(void)
|
||||
{
|
||||
uint8_t rev = 0;
|
||||
|
||||
rev = EEPROM_ReadMCUDevInfo(&g_mcu_dev);
|
||||
if(rev == 0x00){
|
||||
//<2F><>ȡ<EFBFBD>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD>ʼУ<CABC><D0A3><EFBFBD><EFBFBD><EFBFBD>²<EFBFBD><C2B2><EFBFBD>
|
||||
EEPROM_Validate_MCUDevInfo(&g_mcu_dev);
|
||||
}else{
|
||||
//<2F><>ȡʧ<C8A1>ܣ<EFBFBD><DCA3>ָ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD>
|
||||
DBG_SYS_Printf("EE Use Defalut Para");
|
||||
EEPROM_Default_MCUDevInfo(&g_mcu_dev);
|
||||
|
||||
//DBG_SYS_Printf("EE Use Defalut Para");
|
||||
DBG_SYS_Printf("EE DevBootVer:%d",g_mcu_dev.dev_boot_ver);
|
||||
DBG_SYS_Printf("EE DevNameLen:%d",g_mcu_dev.dev_name_len);
|
||||
DBG_SYS_Printf("EE DevName:%s",g_mcu_dev.dev_name);
|
||||
}
|
||||
|
||||
//EEPROM_Default_MCUDevInfo(&g_mcu_dev);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_Flash_Write
|
||||
* Description : MCU Flash<73><68><EFBFBD><EFBFBD>д<EFBFBD>뺯<EFBFBD><EBBAAF>
|
||||
* Input :
|
||||
pBuffer<65><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
NumByteToWrite<74><65>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> -- д<>볤<EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD>Ϊ4<CEAA>ı<EFBFBD><C4B1><EFBFBD>
|
||||
writeAddr<64><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ 0x00004000 ~ 0x0006FFFF 432KB
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_APP_Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - д<><D0B4><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7><EFBFBD>Լ<EFBFBD>д<EFBFBD>볤<EFBFBD><EBB3A4><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>4Byte<74><65><EFBFBD><EFBFBD>*/
|
||||
if( ( writeAddr < MCU_APP_Flash_Start_Addr ) || ( ( writeAddr + NumByteToWrite ) > MCU_EEPROM_Start_Addr ) || ((NumByteToWrite % 4) != 0x00) ) {
|
||||
DBG_SYS_Printf("MCU APP Flash Addr Error:%x - %x\r\n", writeAddr, NumByteToWrite);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
FLASH_Unlock();
|
||||
sta = FLASH_ROMA_WRITE(writeAddr, pBuffer, NumByteToWrite);
|
||||
FLASH_Lock();
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_SYS_Printf("Operation FLASH_ROMA_WRITE failed %#x!! Err Code %x\r\n", writeAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
sta = FLASH_ROMA_VERIFY(writeAddr, pBuffer, NumByteToWrite);
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_SYS_Printf("Operation FLASH_ROMA_VERIFY failed %#x!! Err Code %x\r\n", writeAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_Flash_Read
|
||||
* Description : MCU Flash<73><68><EFBFBD>ݶ<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
pBuffer<65><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
NumByteToWrite<74><65>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> -- д<>볤<EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD>Ϊ4<CEAA>ı<EFBFBD><C4B1><EFBFBD>
|
||||
readAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ 0x00004000 ~ 0x0006FFFF 432KB
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_APP_Flash_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><>ȡ<EFBFBD><C8A1>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7>*/
|
||||
if( ( readAddr < MCU_APP_Flash_Start_Addr ) || ( ( readAddr + NumByteToWrite ) > MCU_EEPROM_Start_Addr ) ) {
|
||||
DBG_SYS_Printf("MCU APP Flash Addr Error:%x - %x\r\n", readAddr, NumByteToWrite);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
sta = FLASH_ROMA_READ(readAddr, pBuffer, NumByteToWrite);
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation FLASH_ROMA_READ failed %x!! Err Code %x\r\n", readAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_APP_Flash_Erase
|
||||
* Description : MCU Flash<73><68><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
pBuffer<65><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
NumByteToWrite<74><65>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> -- д<>볤<EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD>Ϊ4<CEAA>ı<EFBFBD><C4B1><EFBFBD>
|
||||
readAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ 0x00004000 ~ 0x0006FFFF 432KB
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_APP_Flash_Erase(uint32_t readAddr,uint16_t NumByteToWrite)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><>ȡ<EFBFBD><C8A1>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7>*/
|
||||
if( ( readAddr < MCU_APP_Flash_Start_Addr ) || ( ( readAddr + NumByteToWrite ) > MCU_EEPROM_Start_Addr ) ) {
|
||||
DBG_SYS_Printf("MCU EEPROM Addr Error:%x - %x\r\n", readAddr, NumByteToWrite);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
FLASH_Unlock();
|
||||
sta = FLASH_ROMA_ERASE(readAddr, NumByteToWrite);
|
||||
FLASH_Lock();
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation FLASH_ROMA_ERASE failed %x!! Err Code %x\r\n", readAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_APP_Flash_ALLErase
|
||||
* Description : MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD><EFBFBD>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_APP_Flash_ALLErase(void)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
for(uint32_t i=MCU_APP_Flash_Start_Addr;i<MCU_APP_Flash_End_Addr;i+=MCU_APP_Flash_PageSize)
|
||||
{
|
||||
DBG_Printf("Operation FLASH_ROMA_ERASE - %x!! \r\n", i);
|
||||
FLASH_Unlock();
|
||||
sta = FLASH_ROMA_ERASE(i, MCU_APP_Flash_PageSize);
|
||||
FLASH_Lock();
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation FLASH_ROMA_ERASE failed %x!! Err Code %x\r\n", i, sta);
|
||||
return 0x01;
|
||||
}
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_EEPROM_Write
|
||||
* Description : MCU EEPROM<4F><4D><EFBFBD><EFBFBD>д<EFBFBD>뺯<EFBFBD><EBBAAF>
|
||||
* Input :
|
||||
pBuffer<65><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
NumByteToWrite<74><65>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> -- д<>볤<EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD>Ϊ4<CEAA>ı<EFBFBD><C4B1><EFBFBD>
|
||||
writeAddr<64><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ 0x00004000 ~ 0x0006FFFF 432KB
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_EEPROM_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - д<><D0B4><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7><EFBFBD>Լ<EFBFBD>д<EFBFBD>볤<EFBFBD><EBB3A4><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>4Byte<74><65><EFBFBD><EFBFBD>*/
|
||||
if( ( writeAddr < MCU_EEPROM_Start_Addr ) || ( ( writeAddr + NumByteToWrite ) > MCU_EEPROM_End_Addr ) || ((NumByteToWrite % 4) != 0x00)) {
|
||||
DBG_SYS_Printf("MCU EEPROM Addr Error:%x - %x\r\n", writeAddr, NumByteToWrite);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
FLASH_Unlock();
|
||||
sta = EEPROM_WRITE(writeAddr, pBuffer, NumByteToWrite);
|
||||
FLASH_Lock();
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_SYS_Printf("Operation FLASH_ROMA_WRITE failed %x!! Err Code %x\r\n", writeAddr, sta);
|
||||
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_EEPROM_Read
|
||||
* Description : MCU EEPROM<4F><4D><EFBFBD>ݶ<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
pBuffer<65><72>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
NumByteToWrite<74><65>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> -- д<>볤<EFBFBD>ȱ<EFBFBD><C8B1><EFBFBD>Ϊ4<CEAA>ı<EFBFBD><C4B1><EFBFBD>
|
||||
readAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ 0x00004000 ~ 0x0006FFFF 432KB
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_EEPROM_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><>ȡ<EFBFBD><C8A1>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7>*/
|
||||
if( ( readAddr < MCU_EEPROM_Start_Addr ) || ( ( readAddr + NumByteToWrite ) > MCU_EEPROM_End_Addr ) ) {
|
||||
DBG_SYS_Printf("MCU EEPROM Addr Error:%x - %x\r\n", readAddr, NumByteToWrite);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
sta = EEPROM_READ(readAddr, pBuffer, NumByteToWrite);
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation FLASH_ROMA_READ failed %x!! Err Code %x\r\n", readAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_EEPROM_Erase
|
||||
* Description : MCU EEPROM<4F><4D><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
eraseAddr<64><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ 0x70000 -- 0x77FFF
|
||||
length<74><68>ֻ<EFBFBD>ܰ<EFBFBD><DCB0>տ<EFBFBD><D5BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>СΪ4096
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_EEPROM_Erase(uint32_t eraseAddr,uint16_t length)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
/* У<><D0A3><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20><>ȡ<EFBFBD><C8A1>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>APP Flash<73><68>Χ<EFBFBD><CEA7> */
|
||||
if( ( eraseAddr < MCU_EEPROM_Start_Addr ) || ( ( eraseAddr + length ) > MCU_EEPROM_End_Addr ) ) {
|
||||
DBG_SYS_Printf("MCU EEPROM Addr Error:%x - %x\r\n", eraseAddr, length);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
FLASH_Unlock();
|
||||
sta = EEPROM_ERASE(eraseAddr, length);
|
||||
FLASH_Lock();
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation MCU_EEPROM_Erase failed %x!! Err Code %x\r\n", eraseAddr, sta);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : MCU_EEPROM_ALLErase
|
||||
* Description : MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - EEPROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t MCU_EEPROM_ALLErase(void)
|
||||
{
|
||||
FLASH_Status sta;
|
||||
|
||||
for(uint32_t i=MCU_EEPROM_Start_Addr;i<MCU_EEPROM_End_Addr;i+=MCU_APP_Flash_PageSize)
|
||||
{
|
||||
FLASH_Unlock();
|
||||
sta = EEPROM_ERASE(i, MCU_APP_Flash_PageSize);
|
||||
FLASH_Lock();
|
||||
|
||||
if (sta != FLASH_COMPLETE){
|
||||
DBG_Printf("Operation FLASH_ROMA_ERASE failed %x!! Err Code %x\r\n", i, sta);
|
||||
return 0x01;
|
||||
}
|
||||
}
|
||||
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_CheckSum
|
||||
* Description : EEPROM У<>麯<EFBFBD><E9BAAF>
|
||||
*******************************************************************************/
|
||||
uint8_t EEPROM_CheckSum(uint8_t *data,uint16_t len)
|
||||
{
|
||||
uint8_t data_sum = 0;
|
||||
|
||||
for(uint16_t i = 0;i<len;i++)
|
||||
{
|
||||
data_sum += data[i];
|
||||
}
|
||||
return data_sum;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_ReadMCUDevInfo
|
||||
* Description : <20><>EEPROM<4F>ж<EFBFBD>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ
|
||||
*******************************************************************************/
|
||||
uint8_t EEPROM_ReadMCUDevInfo(E_MCU_DEV_INFO *info)
|
||||
{
|
||||
uint16_t read_len = 0;
|
||||
uint32_t read_addr = MCU_EEPROM_MCUDevInfo_Address;
|
||||
|
||||
memset(g_read_buff,0,sizeof(g_read_buff));
|
||||
|
||||
DBG_SYS_Printf("EEPROM_READ : %x ",read_addr);
|
||||
|
||||
DBG_Printf("EEPROM_READ 1\r\n");
|
||||
|
||||
FLASH_Unlock();
|
||||
EEPROM_ERASE(read_addr , 0x1000);
|
||||
FLASH_Lock();
|
||||
|
||||
DBG_Printf("EEPROM_READ 2\r\n");
|
||||
|
||||
EEPROM_READ(read_addr,g_read_buff,1024);
|
||||
|
||||
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"Dev Info:",g_read_buff,4);
|
||||
|
||||
if(g_read_buff[0] == EEPROM_SVAE_FLAG){
|
||||
read_len = g_read_buff[2];
|
||||
read_len <<= 8;
|
||||
read_len |= g_read_buff[1];
|
||||
|
||||
DBG_SYS_Printf("read_len : %d ",read_len);
|
||||
|
||||
if(read_len <= EEPROM_DATA_Size_Max){
|
||||
DBG_SYS_Printf("read_para %0x%x\r\n",MCU_EEPROM_MCUDevInfo_Address);
|
||||
|
||||
//EEPROM_READ(MCU_EEPROM_MCUDevInfo_Address,g_read_buff,1024);
|
||||
|
||||
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"Dev Info Para:",&g_read_buff[4],read_len);
|
||||
|
||||
if(EEPROM_CheckSum(&g_read_buff[4],sizeof(E_MCU_DEV_INFO)) == g_read_buff[3]){
|
||||
//У<><D0A3><EFBFBD>ɹ<EFBFBD>
|
||||
memcpy((uint8_t *)info,g_read_buff,sizeof(E_MCU_DEV_INFO));
|
||||
|
||||
DBG_SYS_Printf("EE DevAddr:%d",info->dev_addr);
|
||||
DBG_SYS_Printf("EE DevType:%d",info->dev_type);
|
||||
DBG_SYS_Printf("EE DevBootVer:%d",info->dev_boot_ver);
|
||||
DBG_SYS_Printf("EE DevAppVer:%d",info->dev_app_ver);
|
||||
DBG_SYS_Printf("EE DevNameLen:%d",info->dev_name_len);
|
||||
DBG_SYS_Printf("EE DevName:%s",info->dev_name);
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_WriteMCUDevInfo
|
||||
* Description : <20><><EFBFBD>豸<EFBFBD><E8B1B8>Ϣд<CFA2>뵽EEPROM<4F><4D>
|
||||
*******************************************************************************/
|
||||
uint8_t EEPROM_WriteMCUDevInfo(E_MCU_DEV_INFO *info)
|
||||
{
|
||||
uint8_t save_data[EEPROM_DATA_Size_Max + 6];
|
||||
uint16_t save_len = sizeof(E_MCU_DEV_INFO);
|
||||
|
||||
if(save_len >= EEPROM_DATA_Size_Max) save_len = EEPROM_DATA_Size_Max;
|
||||
|
||||
save_data[0] = EEPROM_SVAE_FLAG;
|
||||
save_data[1] = save_len & 0xFF;
|
||||
save_data[2] = (save_len >> 8) & 0xFF;
|
||||
|
||||
memcpy(&save_data[4],(uint8_t *)info,save_len);
|
||||
|
||||
save_data[3] = EEPROM_CheckSum(&save_data[4],save_len);
|
||||
|
||||
save_len+=4;
|
||||
|
||||
MCU_EEPROM_Write(save_data,save_len,MCU_EEPROM_MCUDevInfo_Address);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_Default_MCUDevInfo
|
||||
* Description : EEPROM<4F>в<EFBFBD><D0B2><EFBFBD><EFBFBD>ָ<EFBFBD>Ĭ<EFBFBD><C4AC>ֵ<EFBFBD><D6B5><EFBFBD>ҽ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EEPROM<4F><4D>
|
||||
*******************************************************************************/
|
||||
void EEPROM_Default_MCUDevInfo(E_MCU_DEV_INFO *info)
|
||||
{
|
||||
#if (Project_Area == 0x01)
|
||||
/*Boot <20><><EFBFBD><EFBFBD>*/
|
||||
info->dev_addr = 0x00;
|
||||
info->dev_type = 0x00;
|
||||
info->dev_app_ver = 0x00;
|
||||
info->dev_boot_ver = Project_FW_Version;
|
||||
info->dev_name_len = sizeof(Peoject_Name);
|
||||
|
||||
memset((char *)info->dev_name,0,EEPROM_DEV_NAME_Size);
|
||||
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
|
||||
|
||||
//EEPROM_WriteMCUDevInfo(info);
|
||||
#elif (Project_Area == 0x02)
|
||||
/*APP <20><><EFBFBD><EFBFBD>*/
|
||||
info->dev_addr = 0x00;
|
||||
info->dev_type = Project_Type;
|
||||
info->dev_app_ver = Project_FW_Version;
|
||||
info->dev_name_len = sizeof(Peoject_Name);
|
||||
|
||||
memset((char *)info->dev_name,0,EEPROM_DEV_NAME_Size);
|
||||
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
|
||||
|
||||
EEPROM_WriteMCUDevInfo(info);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : EEPROM_Validate_MCUDevInfo
|
||||
* Description : У<><D0A3><EFBFBD><EFBFBD>EEPROM <20>ж<EFBFBD>ȡ<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD>㽫<EFBFBD><E3BDAB>ǰ<EFBFBD><C7B0>ȷ<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD>д<EFBFBD><D0B4>
|
||||
APP<50><50><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ж<EFBFBD>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EEPROM<4F>м<EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ƿ<EFBFBD>һ<EFBFBD><D2BB>
|
||||
Boot<6F><74><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ж<EFBFBD>Boot<6F><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EEPROM<4F>м<EFBFBD>¼<EFBFBD><C2BC><EFBFBD>Ƿ<EFBFBD>һ<EFBFBD><D2BB>
|
||||
*******************************************************************************/
|
||||
void EEPROM_Validate_MCUDevInfo(E_MCU_DEV_INFO *info)
|
||||
{
|
||||
#if (Project_Area == 0x01)
|
||||
/*Boot <20><><EFBFBD><EFBFBD>*/
|
||||
uint8_t save_flag = 0;
|
||||
|
||||
if(info->dev_boot_ver != Project_FW_Version)
|
||||
{
|
||||
info->dev_boot_ver = Project_FW_Version;
|
||||
save_flag = 0x01;
|
||||
}
|
||||
|
||||
if(save_flag == 0x01)
|
||||
{
|
||||
EEPROM_WriteMCUDevInfo(info);
|
||||
}
|
||||
#elif (Project_Area == 0x02)
|
||||
/*APP <20><><EFBFBD><EFBFBD>*/
|
||||
U8_T save_flag = 0;
|
||||
|
||||
if(info->dev_app_ver != Project_FW_Version)
|
||||
{
|
||||
info->dev_app_ver = Project_FW_Version;
|
||||
save_flag = 0x01;
|
||||
}
|
||||
|
||||
if(info->dev_type != Project_Type)
|
||||
{
|
||||
info->dev_type = Project_Type;
|
||||
save_flag = 0x01;
|
||||
}
|
||||
|
||||
if(info->dev_name_len != sizeof(Peoject_Name))
|
||||
{
|
||||
info->dev_name_len = sizeof(Peoject_Name);
|
||||
save_flag = 0x01;
|
||||
}
|
||||
|
||||
if(strncmp((char *)info->dev_name,(char *)Peoject_Name,sizeof(Peoject_Name)))
|
||||
{
|
||||
memcpy((char *)info->dev_name,(char *)Peoject_Name,info->dev_name_len);
|
||||
save_flag = 0x01;
|
||||
}
|
||||
|
||||
if(save_flag == 0x01)
|
||||
{
|
||||
EEPROM_WriteMCUDevInfo(info);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Read_APP_Feature_Info
|
||||
* Description : <20><>ȡAPP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t Read_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info)
|
||||
{
|
||||
uint16_t crc_val = 0,crc_val2 = 0;
|
||||
uint32_t temp_val = 0;
|
||||
memset(g_read_buff,0,sizeof(g_read_buff));
|
||||
|
||||
if(option == 0x01){
|
||||
//<2F><>ȡMCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
MCU_APP_Flash_Read(g_read_buff,APP_FEATURE_SIZE,MCU_APP_Feature_Addr);
|
||||
}else if(option == 0x02){
|
||||
//<2F><>ȡ<EFBFBD>ⲿ Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Flash_Read(g_read_buff,APP_FEATURE_SIZE,SPIFLASH_APP_FEATURE_Addr);
|
||||
}
|
||||
|
||||
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"APP Feature :",g_read_buff,APP_FEATURE_SIZE);
|
||||
|
||||
crc_val = g_read_buff[1];
|
||||
crc_val <<= 0x08;
|
||||
crc_val |= g_read_buff[0];
|
||||
|
||||
crc_val2 = CRC16_Check(&g_read_buff[2],510);
|
||||
DBG_SYS_Printf("%s CRC: %x - %x",__func__,crc_val,crc_val2);
|
||||
|
||||
if(crc_val == crc_val2)
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ͨ<EFBFBD><CDA8>*/
|
||||
feature_info->app_flag = g_read_buff[Feature_AppFlag];
|
||||
|
||||
temp_val = g_read_buff[Feature_AppStart + 3];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppStart + 2];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppStart + 1];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppStart];
|
||||
feature_info->app_start_addr = temp_val;
|
||||
|
||||
temp_val = g_read_buff[Feature_AppEnd + 3];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppEnd + 2];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppEnd + 1];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppEnd];
|
||||
feature_info->app_end_addr = temp_val;
|
||||
|
||||
temp_val = g_read_buff[Feature_AppCrcSize + 1];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppCrcSize];
|
||||
feature_info->app_crc_size = temp_val;
|
||||
|
||||
temp_val = g_read_buff[Feature_AppCrcLen + 1];
|
||||
temp_val <<= 8;
|
||||
temp_val |= g_read_buff[Feature_AppCrcLen];
|
||||
feature_info->app_crc_len = temp_val;
|
||||
|
||||
memcpy(feature_info->app_crc,&g_read_buff[Feature_AppFlashCrc],APP_Feature_CRC_Size);
|
||||
|
||||
/*У<><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Χ*/
|
||||
if( ( feature_info->app_start_addr < MCU_APP_Flash_Start_Addr ) || ( feature_info->app_start_addr > MCU_APP_Data_End_Addr ) ){
|
||||
DBG_SYS_Printf("%s app_start_addr:0x%x Error",__func__, feature_info->app_start_addr);
|
||||
return 0x02;
|
||||
}
|
||||
|
||||
if( ( feature_info->app_end_addr > MCU_APP_Data_End_Addr ) || ( feature_info->app_start_addr > feature_info->app_end_addr ) ){
|
||||
DBG_SYS_Printf("%s app_end_addr:0x%x - 0x%x Error",__func__,feature_info->app_start_addr,feature_info->app_end_addr);
|
||||
return 0x02;
|
||||
}
|
||||
|
||||
if( feature_info->app_crc_size != MCU_APP_Flash_PageSize ){
|
||||
DBG_SYS_Printf("%s app_crc_size:%#x Error",__func__,feature_info->app_crc_size);
|
||||
return 0x02;
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Write_APP_Feature_Info
|
||||
* Description : д<><D0B4>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t Write_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info)
|
||||
{
|
||||
uint8_t rev = 0;
|
||||
|
||||
memset(g_read_buff,0,sizeof(g_read_buff));
|
||||
memset(g_flash_buff,0,sizeof(g_flash_buff));
|
||||
|
||||
g_flash_buff[Feature_AppFlag] = feature_info->app_flag;
|
||||
|
||||
g_flash_buff[Feature_AppStart] = feature_info->app_start_addr & 0xFF;
|
||||
g_flash_buff[Feature_AppStart + 1] = ( feature_info->app_start_addr >> 8 ) & 0xFF;
|
||||
g_flash_buff[Feature_AppStart + 2] = ( feature_info->app_start_addr >> 16 ) & 0xFF;
|
||||
g_flash_buff[Feature_AppStart + 3] = ( feature_info->app_start_addr >> 24 ) & 0xFF;
|
||||
|
||||
g_flash_buff[Feature_AppEnd] = feature_info->app_end_addr & 0xFF;
|
||||
g_flash_buff[Feature_AppEnd + 1] = ( feature_info->app_end_addr >> 8 ) & 0xFF;
|
||||
g_flash_buff[Feature_AppEnd + 2] = ( feature_info->app_end_addr >> 16 ) & 0xFF;
|
||||
g_flash_buff[Feature_AppEnd + 3] = ( feature_info->app_end_addr >> 24 ) & 0xFF;
|
||||
|
||||
g_flash_buff[Feature_AppCrcSize] = feature_info->app_crc_size & 0xFF;
|
||||
g_flash_buff[Feature_AppCrcSize + 1] = ( feature_info->app_crc_size >> 8 ) & 0xFF;
|
||||
|
||||
g_flash_buff[Feature_AppCrcLen] = feature_info->app_crc_len & 0xFF;
|
||||
g_flash_buff[Feature_AppCrcLen + 1] = ( feature_info->app_crc_len >> 8 ) & 0xFF;
|
||||
|
||||
memcpy(&g_flash_buff[Feature_AppFlashCrc],feature_info->app_crc,APP_Feature_CRC_Size);
|
||||
|
||||
feature_info->crc_check = CRC16_Check(&g_flash_buff[2], 510);
|
||||
|
||||
g_flash_buff[Feature_Check] = feature_info->crc_check & 0xFF;
|
||||
g_flash_buff[Feature_Check + 1] = ( feature_info->crc_check >> 8 ) & 0xFF;
|
||||
|
||||
if(option == 0x01){
|
||||
//<2F><>ȡMCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>СΪ512Byte<74><65>mcu flash ÿ<><C3BF>д<EFBFBD>붼<EFBFBD><EBB6BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 4096byte
|
||||
/*д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1<><31><EFBFBD>ȶ<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
|
||||
MCU_APP_Flash_Read(g_read_buff,MCU_APP_Flash_PageSize,MCU_APP_Feature_PageAddr);
|
||||
|
||||
memcpy(&g_read_buff[MCU_APP_Feature_PageOffset],g_flash_buff,512);
|
||||
|
||||
/*д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 2<><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
rev = MCU_APP_Flash_Erase(MCU_APP_Feature_PageAddr,MCU_APP_Flash_PageSize);
|
||||
|
||||
if(rev != 0x00) {
|
||||
DBG_SYS_Printf("MCU_APP_Flash_Erase Fail:%d %x - %x",rev,MCU_APP_Feature_PageAddr,MCU_APP_Flash_PageSize);
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
/*д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 3<><33>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
rev = MCU_APP_Flash_Write(g_read_buff,MCU_APP_Flash_PageSize,MCU_APP_Feature_PageAddr);
|
||||
|
||||
if(rev != 0x00) {
|
||||
DBG_SYS_Printf("MCU_APP_Flash_Write Fail:%d %#x - %#x",rev,MCU_APP_Feature_PageAddr,MCU_APP_Flash_PageSize);
|
||||
return 0x02;
|
||||
}
|
||||
|
||||
/*д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 4<><34>У<EFBFBD><D0A3>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
rev = FLASH_ROMA_VERIFY(MCU_APP_Feature_PageAddr,g_read_buff,MCU_APP_Flash_PageSize);
|
||||
if(rev != 0x00) {
|
||||
DBG_SYS_Printf("FLASH_ROMA_VERIFY Fail:%d %#x - %#x",rev,MCU_APP_Feature_PageAddr,MCU_APP_Flash_PageSize);
|
||||
return 0x03;
|
||||
}
|
||||
|
||||
}else if(option == 0x02){
|
||||
//<2F><>ȡ<EFBFBD>ⲿ Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"SPI Flash Para:",g_flash_buff,APP_FEATURE_SIZE);
|
||||
|
||||
Flash_Write(g_flash_buff,APP_FEATURE_SIZE,SPIFLASH_APP_FEATURE_Addr);
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : APP_Feature_Info_Printf
|
||||
* Description : APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ӡ
|
||||
*******************************************************************************/
|
||||
void APP_Feature_Info_Printf(G_SYS_FEATURE_T *feature_info)
|
||||
{
|
||||
DBG_SYS_Printf("Feature crc_check: %x \r\n",feature_info->crc_check);
|
||||
DBG_SYS_Printf("Feature app_flag: %x \r\n",feature_info->app_flag);
|
||||
|
||||
|
||||
DBG_SYS_Printf("Feature app_start_addr: %x \r\n",feature_info->app_start_addr);
|
||||
DBG_SYS_Printf("Feature app_end_addr: %x \r\n",feature_info->app_end_addr);
|
||||
DBG_SYS_Printf("Feature app_crc_len: %d \r\n",feature_info->app_crc_len);
|
||||
Dbg_Print_Buff(DBG_BIT_SYS_STATUS,"Feature app_crc:",feature_info->app_crc,471);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
221
MCU_Driver/rtc.c
Normal file
221
MCU_Driver/rtc.c
Normal file
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* rtc.c
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "includes.h"
|
||||
#include <string.h>
|
||||
|
||||
S_RTC RTC_Raw_Data = {
|
||||
.year = 0,
|
||||
.month = 1,
|
||||
.day = 1,
|
||||
.week = 0,
|
||||
.hour = 0,
|
||||
.minute = 0,
|
||||
.second = 0,
|
||||
};
|
||||
|
||||
S_RTC MCU_RTC_Data = {
|
||||
.year = 0,
|
||||
.month = 1,
|
||||
.day = 1,
|
||||
.week = 0,
|
||||
.hour = 0,
|
||||
.minute = 0,
|
||||
.second = 0,
|
||||
};
|
||||
|
||||
uint32_t Mcu_GetTime_tick = 0;
|
||||
uint32_t Log_Time_ms = 0;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_Init
|
||||
* Description : RTC<54><43>ʼ<EFBFBD><CABC> - ע<><D7A2>BLV-C1Pû<50><C3BB>RTC<54><43><EFBFBD>ܣ<EFBFBD>ֻ<EFBFBD><D6BB>ʹ<EFBFBD><CAB9>ϵͳ<CFB5><CDB3>ʱ<EFBFBD><CAB1>ģ<EFBFBD><C4A3>RTC<54><43>ʱ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void RTC_Init(void)
|
||||
{
|
||||
memset(&RTC_Raw_Data,0,sizeof(S_RTC));
|
||||
memset(&MCU_RTC_Data,0,sizeof(S_RTC));
|
||||
|
||||
RTC_Raw_Data.year = 0x00;
|
||||
RTC_Raw_Data.month = 0x01;
|
||||
RTC_Raw_Data.day = 0x01;
|
||||
RTC_Raw_Data.week = 0x00;
|
||||
RTC_Raw_Data.hour = 0x00;
|
||||
RTC_Raw_Data.minute = 0x00;
|
||||
RTC_Raw_Data.second = 0x00;
|
||||
|
||||
MCU_RTC_Data.year = 0x00;
|
||||
MCU_RTC_Data.month = 0x01;
|
||||
MCU_RTC_Data.day = 0x01;
|
||||
MCU_RTC_Data.week = 0x00;
|
||||
MCU_RTC_Data.hour = 0x00;
|
||||
MCU_RTC_Data.minute = 0x00;
|
||||
MCU_RTC_Data.second = 0x00;
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : HEX_data_conversion_to_DEC
|
||||
* Description : <20><>ʮ<EFBFBD><CAAE><EFBFBD><EFBFBD><EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ʮ<EFBFBD><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊʵ<CEAA>ʵ<EFBFBD>ʮ<EFBFBD><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0x20 -> 20
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
uint8_t HEX_Conversion_To_DEC(uint8_t c_num)
|
||||
{
|
||||
uint8_t rev_num = 0;
|
||||
|
||||
rev_num = (c_num/16)*10 + (c_num%16);
|
||||
|
||||
return rev_num;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : HEX_data_conversion_to_DEC
|
||||
* Description : <20><>ʮ<EFBFBD><CAAE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>Ϊʮ<CEAA><CAAE><EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 20 -> 0x20
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
uint8_t DEV_Conversion_To_HEX(uint8_t c_num)
|
||||
{
|
||||
uint8_t rev_num = 0;
|
||||
|
||||
rev_num = (c_num/10)*16 + (c_num%10);
|
||||
|
||||
return rev_num;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_Conversion_To_UTC
|
||||
* Description : <20><>RTCʱ<43><CAB1>ת<EFBFBD><D7AA>ΪUTCʱ<43><CAB1>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
uint32_t RTC_Conversion_To_Unix(S_RTC *rtc_time)
|
||||
{
|
||||
// uint32_t timestamp = 0;
|
||||
// struct tm test_time;
|
||||
//
|
||||
// test_time.tm_year = HEX_Conversion_To_DEC(rtc_time->year) + 2000 - 1900;
|
||||
// if(rtc_time->month != 0x00)
|
||||
// {
|
||||
// test_time.tm_mon = HEX_Conversion_To_DEC(rtc_time->month) - 1;
|
||||
// }else {
|
||||
// test_time.tm_mon = 1;
|
||||
// }
|
||||
//
|
||||
// test_time.tm_mday = HEX_Conversion_To_DEC(rtc_time->day);
|
||||
// test_time.tm_hour = HEX_Conversion_To_DEC(rtc_time->hour);
|
||||
// test_time.tm_min = HEX_Conversion_To_DEC(rtc_time->minute);
|
||||
// test_time.tm_sec = HEX_Conversion_To_DEC(rtc_time->second);
|
||||
// test_time.tm_isdst = -1;
|
||||
//
|
||||
// timestamp = mktime(&test_time); //<2F><>ת<EFBFBD><D7AA><EFBFBD>ı<EFBFBD>־<EFBFBD><D6BE>UTCʱ<43><CAB1><EFBFBD><EFBFBD>
|
||||
//
|
||||
// /*<2A><><EFBFBD><EFBFBD>ʱ<EFBFBD>仹<EFBFBD><E4BBB9>Ҫ<EFBFBD><D2AA>ȥ8Сʱ*/
|
||||
// timestamp -= 8*3600;
|
||||
//
|
||||
// return timestamp;
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : UTC_Conversion_To_RTC
|
||||
* Description : <20><>UTCʱ<43><CAB1>ת<EFBFBD><D7AA>ΪRTCʱ<43><CAB1>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Unix_Conversion_To_RTC(S_RTC *rtc_time,uint32_t utc_tick)
|
||||
{
|
||||
// uint8_t temp = 0;
|
||||
// time_t temp_tick = utc_tick + 8*3600; /*<2A><><EFBFBD><EFBFBD>ʱ<EFBFBD>任<EFBFBD><E4BBBB><EFBFBD>ɱ<EFBFBD><EFBFBD><D7BC><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>8Сʱ*/
|
||||
// struct tm *test_time;
|
||||
//
|
||||
// test_time = localtime(&temp_tick);
|
||||
//
|
||||
// temp = ( 1900 + test_time->tm_year ) - 2000;
|
||||
// rtc_time->year = DEV_Conversion_To_HEX(temp);
|
||||
// temp = 1 + test_time->tm_mon;
|
||||
// rtc_time->month = DEV_Conversion_To_HEX(temp);
|
||||
// temp = test_time->tm_mday;
|
||||
// rtc_time->day = DEV_Conversion_To_HEX(temp);
|
||||
//
|
||||
// temp = test_time->tm_hour;
|
||||
// rtc_time->hour = DEV_Conversion_To_HEX(temp);
|
||||
// temp = test_time->tm_min;
|
||||
// rtc_time->minute = DEV_Conversion_To_HEX(temp);
|
||||
// temp = test_time->tm_sec;
|
||||
// rtc_time->second = DEV_Conversion_To_HEX(temp);
|
||||
//
|
||||
// temp = test_time->tm_wday;
|
||||
// rtc_time->week = DEV_Conversion_To_HEX(temp);
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_ReadDate
|
||||
* Description : RTCʱ<43><CAB1><EFBFBD><EFBFBD>ȡ - BLV_C1P<31><50>û<EFBFBD><C3BB>RTC<54><43><EFBFBD>ܣ<EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>ʱ<EFBFBD><CAB1>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
uint8_t RTC_ReadDate(S_RTC *psRTC)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>ǰʱ<C7B0><CAB1>+<2B><><EFBFBD>ؼ<EFBFBD><D8BC><EFBFBD>
|
||||
uint32_t rtc_tick = 0;
|
||||
|
||||
rtc_tick = RTC_Conversion_To_Unix(&MCU_RTC_Data);
|
||||
//rtc_tick += rtc_hour*3600+rtc_min*60+rtc_sec;
|
||||
rtc_tick += SysTick_1s - Mcu_GetTime_tick;
|
||||
Unix_Conversion_To_RTC(psRTC,rtc_tick);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_WriteDate
|
||||
* Description : RTCʱ<43><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - BLV_C1P<31><50>û<EFBFBD><C3BB>RTC<54><43><EFBFBD>ܣ<EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>ʱ<EFBFBD><CAB1>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
uint8_t RTC_WriteDate(S_RTC SetRTC)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>Сʱ<D0A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD>ʵĵ<CAB5>ǰʱ<C7B0>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD><EFBFBD>ؼ<EFBFBD><D8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
MCU_RTC_Data.year = SetRTC.year;
|
||||
MCU_RTC_Data.month = SetRTC.month;
|
||||
MCU_RTC_Data.day = SetRTC.day;
|
||||
MCU_RTC_Data.hour = SetRTC.hour;
|
||||
MCU_RTC_Data.minute = SetRTC.minute;
|
||||
MCU_RTC_Data.second = SetRTC.second;
|
||||
|
||||
Mcu_GetTime_tick = SysTick_1s; //<2F><>¼<EFBFBD><C2BC>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : RTC_TASK
|
||||
* Description : RTC<54><43><EFBFBD><EFBFBD> - BLV_C1P<31><50>û<EFBFBD><C3BB>RTC<54><43><EFBFBD>ܣ<EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD>ֶ<EFBFBD><D6B6><EFBFBD>ʱ<EFBFBD><CAB1>
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void RTC_TASK(void)
|
||||
{
|
||||
static uint32_t RTC_Tick = 0;
|
||||
uint8_t r_minute = 0;
|
||||
if(SysTick_1ms - RTC_Tick >= 1000)
|
||||
{
|
||||
r_minute = RTC_Raw_Data.minute;
|
||||
RTC_Tick = SysTick_1ms;
|
||||
RTC_ReadDate(&RTC_Raw_Data);
|
||||
|
||||
if(r_minute != RTC_Raw_Data.minute)
|
||||
{
|
||||
Log_Time_ms = SysTick_1ms; //ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
202
MCU_Driver/rw_logging.c
Normal file
202
MCU_Driver/rw_logging.c
Normal file
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* rw_logging.c
|
||||
*
|
||||
* Created on: Jul 29, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "includes.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Log_CheckSum
|
||||
* Description : <20><>У<EFBFBD><D0A3>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>SRAM<41>ж<EFBFBD>ȡ
|
||||
*******************************************************************************/
|
||||
uint8_t Log_CheckSum(uint32_t addr,uint8_t len)
|
||||
{
|
||||
uint8_t data_sum = 0;
|
||||
for(uint8_t i = 0;i<len;i++)
|
||||
{
|
||||
data_sum += SRAM_Read_Byte(addr+i);
|
||||
}
|
||||
return ~data_sum;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Data_CheckSum
|
||||
* Description : <20><>У<EFBFBD><D0A3>ȡ<EFBFBD><C8A1>
|
||||
*******************************************************************************/
|
||||
uint8_t Data_CheckSum(uint8_t* data,uint16_t len)
|
||||
{
|
||||
uint8_t data_sum = 0;
|
||||
for(uint16_t i = 0;i<len;i++)
|
||||
{
|
||||
data_sum += data[i];
|
||||
}
|
||||
return ~data_sum;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Get_Log_Current_Address
|
||||
* Description : <20><>ȡSRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE>ǰд<C7B0><D0B4><EFBFBD><EFBFBD>ַ
|
||||
*******************************************************************************/
|
||||
uint32_t Get_Log_Current_Address(void)
|
||||
{
|
||||
uint32_t rev = 0;
|
||||
uint8_t read_buff[4] = {0};
|
||||
|
||||
SRAM_DMA_Read_Buff(read_buff,0x04,SRAM_LOG_WRITE_Address);
|
||||
|
||||
rev = read_buff[3];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[2];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[1];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[0];
|
||||
|
||||
if((rev < SRAM_LOG_DATA_Address) || (rev > SRAM_LOG_End_Address)) rev = SRAM_LOG_DATA_Address;
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Set_Log_Current_Address
|
||||
* Description : <20><><EFBFBD><EFBFBD>SRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE>ǰд<C7B0><D0B4><EFBFBD><EFBFBD>ַ
|
||||
*******************************************************************************/
|
||||
void Set_Log_Current_Address(uint32_t W_addr)
|
||||
{
|
||||
uint32_t Last_addr = W_addr;
|
||||
uint8_t write_buff[4] = {0};
|
||||
|
||||
if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address;
|
||||
|
||||
write_buff[0] = (uint8_t)(Last_addr & 0xFF);
|
||||
write_buff[1] = (uint8_t)((Last_addr >> 8) & 0xFF);
|
||||
write_buff[2] = (uint8_t)((Last_addr >> 16) & 0xFF);
|
||||
write_buff[3] = (uint8_t)((Last_addr >> 24) & 0xFF);
|
||||
|
||||
SRAM_DMA_Write_Buff(write_buff,0x04,SRAM_LOG_WRITE_Address);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Get_READ_Log_Address
|
||||
* Description : <20><>ȡSRAM<41>е<EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>־<EFBFBD><D6BE>ַ
|
||||
*******************************************************************************/
|
||||
uint32_t SRAM_Get_READ_Log_Address(void)
|
||||
{
|
||||
uint32_t rev = 0;
|
||||
uint8_t read_buff[4] = {0};
|
||||
|
||||
SRAM_DMA_Read_Buff(read_buff,0x04,SRAM_LOG_READ_Address);
|
||||
|
||||
rev = read_buff[3];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[2];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[1];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[0];
|
||||
|
||||
if((rev < SRAM_LOG_DATA_Address) || (rev > SRAM_LOG_End_Address)) rev = SRAM_LOG_DATA_Address;
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Set_READ_LOG_Address
|
||||
* Description : <20><><EFBFBD><EFBFBD>SRAM<41>е<EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>־<EFBFBD><D6BE>ַ
|
||||
*******************************************************************************/
|
||||
void SRAM_Set_READ_LOG_Address(uint32_t r_addr)
|
||||
{
|
||||
uint32_t Last_addr = r_addr;
|
||||
uint8_t write_buff[4] = {0};
|
||||
|
||||
if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address;
|
||||
|
||||
write_buff[0] = (uint8_t)(Last_addr & 0xFF);
|
||||
write_buff[1] = (uint8_t)((Last_addr >> 8) & 0xFF);
|
||||
write_buff[2] = (uint8_t)((Last_addr >> 16) & 0xFF);
|
||||
write_buff[3] = (uint8_t)((Last_addr >> 24) & 0xFF);
|
||||
|
||||
SRAM_DMA_Write_Buff(write_buff,0x04,SRAM_LOG_READ_Address);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : <20><>־<EFBFBD><D6BE><EFBFBD>湦<EFBFBD><E6B9A6>
|
||||
* Description : <20><>־ÿһ<C3BF><D2BB>Сʱ<D0A1><CAB1>SRAM<41>е<EFBFBD><D0B5><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ݽ<EFBFBD><DDBD>з<EFBFBD>װ<EFBFBD><D7B0>
|
||||
<20><>װ<EFBFBD><D7B0>ֻ<EFBFBD>Ǽ<EFBFBD><C7BC>ϰ<EFBFBD>ͷ<EFBFBD><CDB7>β<EFBFBD><CEB2><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
|
||||
*******************************************************************************/
|
||||
uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len)
|
||||
{
|
||||
uint32_t Last_add = 0;
|
||||
uint8_t temp = 0,temp_len = 0,temp_number = 0;
|
||||
uint8_t temp_buff[20] = {0};
|
||||
uint16_t data_len = len,temp_date = 0,write_len = 0;
|
||||
uint32_t Log_Hour_Tick = SysTick_1ms - Log_Time_ms; //2021-09-23 Log_Time_ms<6D>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>н<EFBFBD><D0BD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹȫ<D6B9>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>while<6C><65>ͬʱ<CDAC><CAB1>д
|
||||
|
||||
Log_Hour_Tick += (uint32_t)HEX_Conversion_To_DEC(RTC_Raw_Data.minute)*60000;
|
||||
Log_Hour_Tick += (uint32_t)HEX_Conversion_To_DEC(RTC_Raw_Data.hour)*3600000;
|
||||
|
||||
if(data_len >= Log_Data_Len_MAX) data_len = Log_Data_Len_MAX; //<2F><EFBFBD><DEB6><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||||
write_len = S_Log_Data + data_len + 1;
|
||||
|
||||
/*<2A><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>־д<D6BE><D0B4><EFBFBD><EFBFBD>ַ <20><> <20><>־<EFBFBD><D6BE><EFBFBD><EFBFBD>*/
|
||||
SRAM_DMA_Read_Buff(temp_buff,0x0A,SRAM_LOG_WRITE_Address);
|
||||
|
||||
Last_add = temp_buff[3]; //<2F><>ȡ<EFBFBD><C8A1>־д<D6BE><D0B4><EFBFBD><EFBFBD>ַ
|
||||
Last_add <<= 8;
|
||||
Last_add |= temp_buff[2];
|
||||
Last_add <<= 8;
|
||||
Last_add |= temp_buff[1];
|
||||
Last_add <<= 8;
|
||||
Last_add |= temp_buff[0];
|
||||
|
||||
temp_number = temp_buff[8]; //<2F><>ȡ<EFBFBD><C8A1>־<EFBFBD><D6BE><EFBFBD><EFBFBD>
|
||||
|
||||
//<2F><>ǰ<EFBFBD><C7B0>ַ<EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD>ҿ<EFBFBD><D2BF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD>
|
||||
if((Last_add + write_len) >= SRAM_LOG_End_Address)
|
||||
{
|
||||
Last_add = SRAM_LOG_DATA_Address;
|
||||
}
|
||||
|
||||
/*<2A>ڶ<EFBFBD><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־*/
|
||||
temp_buff[temp_len++] = LOG_Data_Hand; //<2F><><EFBFBD><EFBFBD>ͷ
|
||||
temp_buff[temp_len++] = temp_buff[8]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
|
||||
temp_buff[temp_len++] = write_len; //<2F><><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD> 2Byte
|
||||
temp_buff[temp_len++] = (write_len >> 8) & 0xFF;
|
||||
temp_buff[temp_len++] = 0x00;
|
||||
temp_date = (HEX_Conversion_To_DEC(RTC_Raw_Data.year) << 10) + (HEX_Conversion_To_DEC(RTC_Raw_Data.month) << 5) + HEX_Conversion_To_DEC(RTC_Raw_Data.day);
|
||||
temp_buff[temp_len++] = (temp_date >> 8) & 0xFF;
|
||||
temp_buff[temp_len++] = temp_date & 0xFF;
|
||||
temp_buff[temp_len++] = data_type;
|
||||
temp_buff[temp_len++] = Log_Hour_Tick & 0xFF;
|
||||
temp_buff[temp_len++] = (Log_Hour_Tick >> 8) & 0xFF;
|
||||
temp_buff[temp_len++] = (Log_Hour_Tick >> 16) & 0xFF;
|
||||
temp_buff[temp_len++] = (Log_Hour_Tick >> 24) & 0xFF;
|
||||
|
||||
SRAM_DMA_Write_Buff(temp_buff,S_Log_Data,Last_add); //<2F><><EFBFBD><EFBFBD>
|
||||
SRAM_DMA_Write_Buff(buff,data_len,Last_add + S_Log_Data); //<2F><><EFBFBD><EFBFBD>
|
||||
SRAM_Write_Byte(Log_Data_End,Last_add + S_Log_Data + data_len); //<2F><><EFBFBD><EFBFBD>β
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>*/
|
||||
temp = Log_CheckSum(Last_add,write_len);
|
||||
SRAM_Write_Byte(temp,Last_add + S_Log_Check); //У<><D0A3>ֵ
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˢ<EFBFBD><CBA2><EFBFBD><EFBFBD>־д<D6BE><D0B4><EFBFBD><EFBFBD>ַ <20>Լ<EFBFBD><D4BC><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD>*/
|
||||
Last_add = Last_add + write_len;
|
||||
Set_Log_Current_Address(Last_add);
|
||||
if(temp_number >= 0xFF)
|
||||
{
|
||||
temp_number = 0x00;
|
||||
}else {
|
||||
temp_number++;
|
||||
}
|
||||
SRAM_Write_Byte(temp_number,SRAM_LOG_Serial_Number); //<2F><><EFBFBD><EFBFBD>β
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
495
MCU_Driver/spi_flash.c
Normal file
495
MCU_Driver/spi_flash.c
Normal file
@@ -0,0 +1,495 @@
|
||||
/*
|
||||
* spi_flash.c
|
||||
*
|
||||
* Created on: May 20, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#include "spi_flash.h"
|
||||
#include "debug.h"
|
||||
|
||||
uint8_t Flash_Buffer[4150]; //FLash д<>뻺<EFBFBD><EBBBBA>BUFF
|
||||
|
||||
void SPI_FLASH_Init(void)
|
||||
{
|
||||
/* SPI Flash <20><> SPI SRAM <20><><EFBFBD><EFBFBD>SPI<50><49><EFBFBD><EFBFBD>
|
||||
* <20><><EFBFBD><EFBFBD> SPI Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ų<EFBFBD>ʼ<EFBFBD><CABC>
|
||||
* */
|
||||
|
||||
DBG_SYS_Printf("SPI Flash ID:0x%x\r\n",Flash_ReadID());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_ReadSR
|
||||
* Description : P25Q40H Flash<73><68>ȡ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
|
||||
* Input : None
|
||||
* Return : P25Q40H Flash״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>ֵ
|
||||
BIT7 6 5 4 3 2 1 0
|
||||
SPR0 BP4 BP3 BP2 BP1 BP0 WEL WIP
|
||||
SPR:Ĭ<><C4AC>0,״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ,<2C><><EFBFBD><EFBFBD>WPʹ<50><CAB9>
|
||||
BP4,BP3,BP2,BP1,BP0:FLASH<53><48><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
WEL:дʹ<D0B4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
BUSY:æ<><C3A6><EFBFBD><EFBFBD>λ(1,æ;0,<2C><><EFBFBD><EFBFBD>)
|
||||
Ĭ<><C4AC>:0x00
|
||||
*******************************************************************************/
|
||||
uint8_t Flash_ReadSR(void)
|
||||
{
|
||||
uint8_t byte = 0;
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_ReadStatusReg); //<2F><><EFBFBD>Ͷ<EFBFBD>ȡ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
byte = SPI0_MasterRecvByte();
|
||||
Flash_CS_H;
|
||||
return byte;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_WriteSR
|
||||
* Description : P25Q40H Flashд״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
|
||||
* Input :
|
||||
sr_val:д<><D0B4>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>ֵ
|
||||
BIT7 6 5 4 3 2 1 0
|
||||
SPR0 BP4 BP3 BP2 BP1 BP0 WEL WIP
|
||||
|
||||
ֻ<><D6BB>SPR0,BP3,BP2,BP1,BP0(bit 7,5,4,3,2)<29><><EFBFBD><EFBFBD>д!!!
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_WriteSR(uint8_t sr_val)
|
||||
{
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_WriteStatusReg);
|
||||
SPI0_MasterSendByte(sr_val);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Write_Enable
|
||||
* Description : P25Q40H дʹ<D0B4><CAB9> -- <20><>WEL<45><4C>λ
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Write_Enable(void)
|
||||
{
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_WriteEnable);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Write_Disable
|
||||
* Description : P25Q40H д<><D0B4>ֹ -- <20><>WEL<45><4C><EFBFBD><EFBFBD>
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Write_Disable(void)
|
||||
{
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_WriteDisable);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_ReadID
|
||||
* Description : P25Q40H Flash <20><>ȡоƬID
|
||||
* Input : None
|
||||
* Return : <20><><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>£<EFBFBD>
|
||||
0x8512:<3A><>ʾоƬ<D0BE>ͺ<EFBFBD>ΪP25Q40H
|
||||
0x8511:<3A><>ʾоƬ<D0BE>ͺ<EFBFBD>ΪP25Q20H
|
||||
0x8510:<3A><>ʾоƬ<D0BE>ͺ<EFBFBD>ΪP25Q10H
|
||||
0x8509:<3A><>ʾоƬ<D0BE>ͺ<EFBFBD>ΪP25Q05H
|
||||
*******************************************************************************/
|
||||
uint16_t Flash_ReadID(void)
|
||||
{
|
||||
uint16_t temp=0;
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_ReadManufactureID);
|
||||
SPI0_MasterRecvByte();
|
||||
SPI0_MasterRecvByte();
|
||||
SPI0_MasterRecvByte();
|
||||
temp |= SPI0_MasterRecvByte()<<8;
|
||||
temp |= SPI0_MasterRecvByte();
|
||||
Flash_CS_H;
|
||||
return temp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Wait_Busy
|
||||
* Description : <20>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input : None
|
||||
* Return : 1<><31><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD>æ״̬
|
||||
0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
|
||||
*******************************************************************************/
|
||||
uint8_t Flash_Wait_Busy(void)
|
||||
{
|
||||
uint8_t temp=0;
|
||||
uint16_t i=0;
|
||||
temp = Flash_ReadSR();
|
||||
while((temp&0x01)==0x01)
|
||||
{
|
||||
FEED_DOG(); //ι<><CEB9>
|
||||
Delay_Us(100);
|
||||
temp = Flash_ReadSR();
|
||||
i++;
|
||||
if(i>3000) return 1;
|
||||
};
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_PowerDown
|
||||
* Description : Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_PowerDown(void)
|
||||
{
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_PowerDown);
|
||||
Delay_Us(3);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_PowerDown
|
||||
* Description : Flash <20><><EFBFBD>ѵ<EFBFBD><D1B5><EFBFBD>ģʽ
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Wakeup(void)
|
||||
{
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_ReleasePowerDown);
|
||||
Delay_Us(3);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Erase_Chip
|
||||
* Description : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>оƬ
|
||||
* Input : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Erase_Chip(void)
|
||||
{
|
||||
Flash_Write_Enable();
|
||||
Flash_Wait_Busy();
|
||||
Flash_CS_L;
|
||||
SPI0_MasterSendByte(P24Q40H_ChipErase);
|
||||
Flash_CS_H;
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Erase_Block
|
||||
* Description : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input : BLK_ID<49><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(0~31) 2M
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Erase_Block(uint32_t BLK_ID)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
BLK_ID*=0x10000; //64K
|
||||
flash_buff[0] = P24Q40H_BlockErase;
|
||||
flash_buff[1] = (uint8_t)((BLK_ID >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((BLK_ID >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((BLK_ID) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_Write_Enable();
|
||||
Flash_Wait_Busy();
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
Flash_CS_H;
|
||||
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Erase_Sector
|
||||
* Description : <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input : DST_Addr<64><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(0~511) 2M
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Erase_Sector(uint32_t DST_ID)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
DST_ID*=4096;
|
||||
flash_buff[0] = P24Q40H_SectorErase;
|
||||
flash_buff[1] = (uint8_t)((DST_ID >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((DST_ID >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((DST_ID) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_Write_Enable();
|
||||
Flash_Wait_Busy();
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
Flash_CS_H;
|
||||
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Erase_Page
|
||||
* Description : <20><><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
* Input : Page_ID<49><44>ҳ<EFBFBD><D2B3>(0~8191)
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Erase_Page(uint32_t Page_ID)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
Page_ID*=256;
|
||||
flash_buff[0] = P24Q40H_PageErase;
|
||||
flash_buff[1] = (uint8_t)((Page_ID >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((Page_ID >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((Page_ID) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_Write_Enable();
|
||||
Flash_Wait_Busy();
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
Flash_CS_H;
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Erase_Page
|
||||
* Description : <20><><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
* Input : Page_addr:<3A><>ַ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Erase_Pageaddr(uint32_t Page_addr)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
flash_buff[0] = P24Q40H_PageErase;
|
||||
flash_buff[1] = (uint8_t)((Page_addr >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((Page_addr >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((Page_addr) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_Write_Enable();
|
||||
Flash_Wait_Busy();
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
Flash_CS_H;
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Read
|
||||
* Description : P25Q40H Flash ָ<><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʼ<EFBFBD><CABC>ȡָ<C8A1><D6B8><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
pBuffer<65><72><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>
|
||||
NumByteToRead<61><64>Ҫ<EFBFBD><D2AA>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>(<28><><EFBFBD><EFBFBD>65535)
|
||||
ReadAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ʼ<EFBFBD><CABC>ַ(24bit)
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Read(uint8_t* pBuffer,uint16_t NumByteToRead,uint32_t ReadAddr)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
flash_buff[0] = P24Q40H_ReadData;
|
||||
flash_buff[1] = (uint8_t)((ReadAddr >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((ReadAddr >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((ReadAddr) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
SPI0_DMARecv(pBuffer,NumByteToRead);
|
||||
Flash_CS_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Write_Page
|
||||
* Description : P25Q40H Flash ָ<><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʼдָ<D0B4><D6B8><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
pBuffer<65><72><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>
|
||||
NumByteToRead<61><64>Ҫд<D2AA><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>(<28><><EFBFBD><EFBFBD>256),<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ó<EFBFBD><C3B3><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>ʣ<EFBFBD><CAA3><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>!!!
|
||||
ReadAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ʼ<EFBFBD><CABC>ַ(24bit)
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Write_Page(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr)
|
||||
{
|
||||
uint8_t flash_buff[5];
|
||||
|
||||
flash_buff[0] = P24Q40H_PageProgram;
|
||||
flash_buff[1] = (uint8_t)((writeAddr >> 16) & 0xFF);
|
||||
flash_buff[2] = (uint8_t)((writeAddr >> 8) & 0xFF);
|
||||
flash_buff[3] = (uint8_t)((writeAddr) & 0xFF);
|
||||
flash_buff[4] = 0x00;
|
||||
|
||||
Flash_Write_Enable();
|
||||
Flash_CS_L;
|
||||
SPI0_DMATrans(flash_buff,0x04);
|
||||
SPI0_DMATrans(pBuffer,NumByteToWrite);
|
||||
Flash_CS_H;
|
||||
Flash_Wait_Busy();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Write_NoCheck
|
||||
* Description : <20><EFBFBD><DEBC><EFBFBD>дP25Q40H FLASH
|
||||
ע<EFBFBD>⣺<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><EFBFBD>Χ<EFBFBD>ڵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD>Ϊ0XFF,<2C><><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD>0XFF<46><46>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD>ʧ<EFBFBD><CAA7>!
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>
|
||||
<20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʼд<CABC><D0B4>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>Ҫȷ<D2AA><C8B7><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Խ<EFBFBD><D4BD>!
|
||||
* Input :
|
||||
pBuffer<65><72><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>
|
||||
NumByteToRead<61><64>Ҫд<D2AA><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>(<28><><EFBFBD><EFBFBD>65535)
|
||||
ReadAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ʼ<EFBFBD><CABC>ַ(24bit)
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Write_NoCheck(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr)
|
||||
{
|
||||
uint16_t pageremain;
|
||||
pageremain=256-writeAddr%256; //<2F><>ҳʣ<D2B3><CAA3><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
|
||||
if(NumByteToWrite<=pageremain) pageremain=NumByteToWrite;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>256<35><36><EFBFBD>ֽ<EFBFBD>
|
||||
while(1)
|
||||
{
|
||||
FEED_DOG(); //ι<><CEB9>
|
||||
|
||||
Flash_Write_Page(pBuffer,pageremain,writeAddr);
|
||||
if(pageremain == NumByteToWrite) break; //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
else {
|
||||
pBuffer+=pageremain;
|
||||
writeAddr+=pageremain;
|
||||
|
||||
NumByteToWrite-=pageremain;
|
||||
if(NumByteToWrite>256) pageremain=256;
|
||||
else pageremain=NumByteToWrite;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Flash_Write
|
||||
* Description : <20><EFBFBD><DEBC><EFBFBD>дP25Q40H FLASH
|
||||
ע<EFBFBD>⣺<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><EFBFBD>Χ<EFBFBD>ڵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD>Ϊ0XFF,<2C><><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD>0XFF<46><46>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD>ʧ<EFBFBD><CAA7>!
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>
|
||||
<20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʼд<CABC><D0B4>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>Ҫȷ<D2AA><C8B7><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Խ<EFBFBD><D4BD>!
|
||||
* Input :
|
||||
pBuffer<65><72><EFBFBD><EFBFBD><EFBFBD>ݴ洢<DDB4><E6B4A2>
|
||||
NumByteToRead<61><64>Ҫд<D2AA><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>(<28><><EFBFBD><EFBFBD>65535)
|
||||
ReadAddr<64><72><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ʼ<EFBFBD><CABC>ַ(24bit)
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t WriteAddr)
|
||||
{
|
||||
uint32_t secpos;
|
||||
uint16_t secoff,secremain,i;
|
||||
uint8_t* Write_Buff;
|
||||
|
||||
if(NumByteToWrite <= 256*2)
|
||||
{
|
||||
Write_Buff = Flash_Buffer;
|
||||
|
||||
secpos = WriteAddr/256; //ҳ<><D2B3><EFBFBD><EFBFBD>ַ
|
||||
secoff = WriteAddr%256; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD>ƫ<EFBFBD><C6AB>
|
||||
secremain = 256 - secoff; //<2F><><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD>
|
||||
|
||||
if(NumByteToWrite<=secremain) secremain = NumByteToWrite; //<2F><>ǰҳ<C7B0><D2B3>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>
|
||||
|
||||
while(1)
|
||||
{
|
||||
FEED_DOG(); //ι<><CEB9>
|
||||
|
||||
Flash_Read(Write_Buff,256,secpos*256); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
for(i=0;i<secremain;i++) //У<><D0A3><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
{
|
||||
if(Write_Buff[secoff+i]!=0xFF) break;
|
||||
}
|
||||
|
||||
if(i<secremain) //<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
{
|
||||
Flash_Erase_Page(secpos); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
for(i=0;i<secremain;i++) //<2F><><EFBFBD><EFBFBD>
|
||||
{
|
||||
Write_Buff[i+secoff]=pBuffer[i];
|
||||
}
|
||||
Flash_Write_NoCheck(Write_Buff,256,secpos*256); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
}else {
|
||||
if(secremain == 256)
|
||||
{
|
||||
Flash_Write_NoCheck(pBuffer,256,secpos*256); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
|
||||
}else if(secremain < 256){
|
||||
Flash_Write_NoCheck(pBuffer,secremain,WriteAddr); //<2F><><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>ӣ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>
|
||||
}
|
||||
}
|
||||
if(NumByteToWrite == secremain) break; //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
else //д<><D0B4>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>
|
||||
{
|
||||
secpos++; //ҳ<><D2B3><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>1
|
||||
secoff = 0; //ҳ<><D2B3>ƫ<EFBFBD><C6AB>λ<EFBFBD>ù<EFBFBD><C3B9><EFBFBD>
|
||||
pBuffer += secremain; //<2F><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>ƫ<EFBFBD><C6AB>
|
||||
WriteAddr += secremain; //<2F><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>
|
||||
NumByteToWrite -= secremain; //ʣ<><CAA3>д<EFBFBD><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD>ݼ<EFBFBD>
|
||||
if(NumByteToWrite > 256) secremain = 256; //<2F><>һ<EFBFBD><D2BB>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
|
||||
else secremain = NumByteToWrite; //<2F><>һ<EFBFBD><D2BB>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Write_Buff = Flash_Buffer;
|
||||
|
||||
secpos = WriteAddr/4096; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
|
||||
secoff = WriteAddr%4096; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD>ƫ<EFBFBD><C6AB>
|
||||
secremain = 4096 - secoff; //<2F><><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD>
|
||||
|
||||
if(NumByteToWrite<=secremain) secremain = NumByteToWrite; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>
|
||||
|
||||
while(1)
|
||||
{
|
||||
FEED_DOG(); //ι<><CEB9>
|
||||
|
||||
Flash_Read(Write_Buff,2048,secpos*4096); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Flash_Read(Write_Buff+2048,2048,secpos*4096+2048); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
for(i=0;i<secremain;i++) //У<><D0A3><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
{
|
||||
if(Write_Buff[secoff+i]!=0xFF)break;
|
||||
}
|
||||
|
||||
if(i<secremain) //<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
{
|
||||
Flash_Erase_Sector(secpos); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
for(i=0;i<secremain;i++) //<2F><><EFBFBD><EFBFBD>
|
||||
{
|
||||
Write_Buff[i+secoff]=pBuffer[i];
|
||||
}
|
||||
Flash_Write_NoCheck(Write_Buff,2048,secpos*4096); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Flash_Write_NoCheck(Write_Buff+2048,2048,secpos*4096+2048); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}else {
|
||||
if(secremain == 4096)
|
||||
{
|
||||
Flash_Write_NoCheck(pBuffer,2048,secpos*4096); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Flash_Write_NoCheck(pBuffer+2048,2048,secpos*4096+2048); //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}else if(secremain < 4096){
|
||||
Flash_Write_NoCheck(pBuffer,secremain,WriteAddr); //<2F><><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>ӣ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
}
|
||||
if(NumByteToWrite == secremain) break; //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
else //д<><D0B4>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>
|
||||
{
|
||||
secpos++; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>1
|
||||
secoff = 0; //<2F><><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB>λ<EFBFBD>ù<EFBFBD><C3B9><EFBFBD>
|
||||
pBuffer += secremain; //<2F><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>ƫ<EFBFBD><C6AB>
|
||||
WriteAddr += secremain; //<2F><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>
|
||||
NumByteToWrite -= secremain; //ʣ<><CAA3>д<EFBFBD><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD>ݼ<EFBFBD>
|
||||
if(NumByteToWrite > 4096) secremain = 4096; //<2F><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>
|
||||
else secremain = NumByteToWrite; //<2F><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
266
MCU_Driver/spi_sram.c
Normal file
266
MCU_Driver/spi_sram.c
Normal file
@@ -0,0 +1,266 @@
|
||||
/*
|
||||
* spi.c
|
||||
*
|
||||
* Created on: May 16, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "spi_sram.h"
|
||||
#include "debug.h"
|
||||
#include <string.h>
|
||||
|
||||
void SPI_SRAM_Init(void)
|
||||
{
|
||||
GPIOA_ModeCfg(GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_11, GPIO_ModeOut_PP);
|
||||
GPIOA_ModeCfg(GPIO_Pin_5, GPIO_ModeIN_Floating);
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap2_SPI0,ENABLE);
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD>Եó<D4B5><C3B3><EFBFBD><EFBFBD><EFBFBD> SPI<50><49><EFBFBD>߲<EFBFBD><DFB2><EFBFBD><EFBFBD><EFBFBD>30MHZ <20>ֲ<EFBFBD><D6B2><EFBFBD>д<EFBFBD><D0B4>SPI<50><49><EFBFBD><EFBFBD>ͨѶΪ50MHZ 24MHZ*/
|
||||
SPI0_MasterInit(24000000);
|
||||
SPI0_DataMode(Mode0_HighBitINFront);
|
||||
|
||||
SRAM_CE_H;
|
||||
|
||||
/*<2A><>ȡSRAMоƬID*/
|
||||
//SRAM_Read_ID_Opeartion();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Write_Byte
|
||||
* Description : SRAMд<4D>ֽ<EFBFBD>
|
||||
* Input :
|
||||
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
|
||||
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SRAM_Write_Byte(uint8_t wdate,uint32_t add)
|
||||
{
|
||||
uint8_t Hadd16=0x00,Hadd8=0x00,Ladd=0x00;
|
||||
Ladd=add;
|
||||
Hadd8=add>>8;
|
||||
Hadd16=add>>16;
|
||||
|
||||
if(add >= SRAM_ADDRESS_MAX) return ;
|
||||
|
||||
SRAM_CE_L;
|
||||
SPI0_MasterSendByte(SRAM_CMD_Write);
|
||||
SPI0_MasterSendByte(Hadd16);
|
||||
SPI0_MasterSendByte(Hadd8);
|
||||
SPI0_MasterSendByte(Ladd);
|
||||
SPI0_MasterSendByte(wdate);
|
||||
|
||||
SRAM_CE_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Read_Byte
|
||||
* Description : SRAM<41><4D><EFBFBD>ֽ<EFBFBD>
|
||||
* Input :
|
||||
add <20><><EFBFBD><EFBFBD>ȡ<EFBFBD>ֽڵĵ<DAB5>ַ
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD>ֽ<EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t SRAM_Read_Byte(uint32_t add)
|
||||
{
|
||||
uint8_t Hadd8=0x00,Hadd16=0x00,Ladd=0x00,rdate=0x00;
|
||||
Ladd=add;
|
||||
Hadd8=add>>8;
|
||||
Hadd16=add>>16;
|
||||
|
||||
if(add >= SRAM_ADDRESS_MAX) return 0x00;
|
||||
|
||||
SRAM_CE_L;
|
||||
SPI0_MasterSendByte(SRAM_CMD_Read);
|
||||
SPI0_MasterSendByte(Hadd16);
|
||||
SPI0_MasterSendByte(Hadd8);
|
||||
SPI0_MasterSendByte(Ladd);
|
||||
rdate = SPI0_MasterRecvByte();
|
||||
SRAM_CE_H;
|
||||
|
||||
return rdate;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Write_Word
|
||||
* Description : SRAMдuint16_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
|
||||
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD>ֽ<EFBFBD>
|
||||
*******************************************************************************/
|
||||
void SRAM_Write_Word(uint16_t wdate,uint32_t add)
|
||||
{
|
||||
SRAM_Write_Byte((uint8_t)(wdate & 0xFF),add);
|
||||
SRAM_Write_Byte((uint8_t)((wdate >> 8) & 0xFF),add + 1);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Read_Word
|
||||
* Description : SRAMдuint16_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
add <20><><EFBFBD><EFBFBD>ȡ<EFBFBD>ֵĵ<D6B5>ַ
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD><C8A1>
|
||||
*******************************************************************************/
|
||||
uint16_t SRAM_Read_Word(uint32_t add)
|
||||
{
|
||||
uint16_t rev = 0;
|
||||
rev = SRAM_Read_Byte(add + 1);
|
||||
rev <<= 8;
|
||||
rev |= SRAM_Read_Byte(add);
|
||||
return rev;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Write_DW
|
||||
* Description : SRAMдuint32_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD>˫<EFBFBD><CBAB>
|
||||
add <20><>˫<EFBFBD><CBAB>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ˫<C8A1><CBAB>
|
||||
*******************************************************************************/
|
||||
void SRAM_Write_DW(uint32_t wdate,uint32_t add)
|
||||
{
|
||||
uint8_t write_buff[4] = {0};
|
||||
|
||||
write_buff[0] = (uint8_t)(wdate & 0xFF);
|
||||
write_buff[1] = (uint8_t)((wdate >> 8) & 0xFF);
|
||||
write_buff[2] = (uint8_t)((wdate >> 16) & 0xFF);
|
||||
write_buff[3] = (uint8_t)((wdate >> 24) & 0xFF);
|
||||
|
||||
SRAM_DMA_Write_Buff(write_buff,0x04,add);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Read_DW
|
||||
* Description : SRAMдuint32_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
add <20><><EFBFBD><EFBFBD>ȡ˫<C8A1>ֵĵ<D6B5>ַ
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ˫<C8A1><CBAB>
|
||||
*******************************************************************************/
|
||||
uint32_t SRAM_Read_DW(uint32_t add)
|
||||
{
|
||||
uint32_t rev = 0;
|
||||
uint8_t read_buff[4] = {0};
|
||||
|
||||
SRAM_DMA_Read_Buff(read_buff,0x04,add);
|
||||
|
||||
rev = read_buff[3];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[2];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[1];
|
||||
rev <<= 8;
|
||||
rev |= read_buff[0];
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Read_ID_Opeartion
|
||||
* Description : SRAM <20><>ȡоƬID
|
||||
* Input : NULL
|
||||
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t SRAM_Read_ID_Opeartion(void)
|
||||
{
|
||||
uint8_t spi_addr[5];
|
||||
uint8_t read_id[9];
|
||||
|
||||
memset(spi_addr,0,0x05);
|
||||
memset(read_id,0,0x04);
|
||||
|
||||
spi_addr[0] = SRAM_CMD_Read_ID;
|
||||
spi_addr[1] = 0x00 ;
|
||||
spi_addr[2] = 0x00 ;
|
||||
spi_addr[3] = 0x00 ;
|
||||
|
||||
SRAM_CE_L;
|
||||
SPI0_DMATrans(spi_addr,0x04);
|
||||
SPI0_DMARecv(read_id,0x08);
|
||||
SRAM_CE_H;
|
||||
|
||||
// Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM MFID:%X",read_id[0]);
|
||||
// if(read_id[1] == 0x5D)
|
||||
// {
|
||||
// Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%X - Known Good Die PASS",read_id[1]);
|
||||
// }else {
|
||||
// Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%X - Known Good Die FAIL",read_id[1]);
|
||||
// }
|
||||
// Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit, "SRAM EID:",&read_id[2],0x06);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_Reset_Operation
|
||||
* Description : SRAM <20><>λ - ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>λ
|
||||
* Input : NULL
|
||||
* Return : NULL
|
||||
*******************************************************************************/
|
||||
void SRAM_Reset_Operation(void)
|
||||
{
|
||||
SRAM_CE_L;
|
||||
SPI0_MasterSendByte(SRAM_CMD_Reset_Enable);
|
||||
SRAM_CE_H;
|
||||
//Delay_Ms(2);
|
||||
SRAM_CE_L;
|
||||
SPI0_MasterSendByte(SRAM_CMD_Reset);
|
||||
SRAM_CE_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_DMA_Write_Buff
|
||||
* Description : SRAM DMA<4D><41>ʽд<CABD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
wbuff : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
len : д<><D0B4><EFBFBD><EFBFBD><EFBFBD>ݵij<DDB5><C4B3><EFBFBD> -- <20><><EFBFBD><EFBFBD>4095<39>ֽڳ<D6BD><DAB3><EFBFBD>
|
||||
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add)
|
||||
{
|
||||
uint8_t spi_addr[5];
|
||||
|
||||
if(add + len >= SRAM_ADDRESS_MAX) return ;
|
||||
|
||||
memset(spi_addr,0,0x05);
|
||||
|
||||
spi_addr[0] = SRAM_CMD_Write;
|
||||
spi_addr[1] = (add >> 16) & 0xFF ;
|
||||
spi_addr[2] = (add >> 8) & 0xFF ;
|
||||
spi_addr[3] = (add) & 0xFF ;
|
||||
|
||||
SRAM_CE_L;
|
||||
SPI0_DMATrans(spi_addr,0x04);
|
||||
SPI0_DMATrans(wbuff,len);
|
||||
SRAM_CE_H;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SRAM_DMA_Read_Buff
|
||||
* Description : SRAM DMA<4D><41>ʽ<EFBFBD><CABD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
rbuff : <20><>Ҫ<EFBFBD><D2AA>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
len : <20><>ȡ<EFBFBD><C8A1><EFBFBD>ݵij<DDB5><C4B3><EFBFBD> -- <20><><EFBFBD><EFBFBD>4095<39>ֽڳ<D6BD><DAB3><EFBFBD>
|
||||
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add)
|
||||
{
|
||||
uint8_t spi_addr[5];
|
||||
|
||||
if(add + len >= SRAM_ADDRESS_MAX) return ;
|
||||
|
||||
memset(spi_addr,0,0x05);
|
||||
|
||||
spi_addr[0] = SRAM_CMD_Read;
|
||||
spi_addr[1] = (add >> 16) & 0xFF ;
|
||||
spi_addr[2] = (add >> 8) & 0xFF ;
|
||||
spi_addr[3] = (add) & 0xFF ;
|
||||
|
||||
SRAM_CE_L;
|
||||
SPI0_DMATrans(spi_addr,0x04);
|
||||
SPI0_DMARecv(rbuff,len);
|
||||
SRAM_CE_H;
|
||||
}
|
||||
|
||||
|
||||
51
MCU_Driver/timer.c
Normal file
51
MCU_Driver/timer.c
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* timer.c
|
||||
*
|
||||
* Created on: May 16, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
#include "timer.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
|
||||
void TIMER0_Init(void)
|
||||
{
|
||||
TMR0_DeInit();
|
||||
TMR0_TimerInit(SystemCoreClock / 10000);
|
||||
TMR0_ITCfg(RB_TMR_IF_CYC_END, ENABLE);
|
||||
NVIC_EnableIRQ(TIM0_IRQn);
|
||||
TMR0_Enable();
|
||||
}
|
||||
|
||||
volatile uint32_t Time0_100us = 0;
|
||||
volatile uint32_t Time0_1ms = 0;
|
||||
|
||||
void __attribute__((interrupt("WCH-Interrupt-fast"))) TIM0_IRQHandler()
|
||||
{
|
||||
static uint8_t NUM_1 = 0;
|
||||
|
||||
TMR0_ClearITFlag(RB_TMR_IF_CYC_END);
|
||||
|
||||
Time0_100us++;
|
||||
NUM_1++;
|
||||
|
||||
if(NUM_1 >= 10){
|
||||
NUM_1 = 0;
|
||||
Time0_1ms++;
|
||||
}
|
||||
}
|
||||
|
||||
void Timer0_Task(void)
|
||||
{
|
||||
static uint32_t timer0_tick = 0;
|
||||
|
||||
if(Time0_1ms - timer0_tick >= 1000 ){
|
||||
timer0_tick = Time0_1ms;
|
||||
|
||||
printf("Run:%d ..",timer0_tick);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
732
MCU_Driver/uart.c
Normal file
732
MCU_Driver/uart.c
Normal file
@@ -0,0 +1,732 @@
|
||||
/*
|
||||
* uart.c
|
||||
*
|
||||
* Created on: May 14, 2025
|
||||
* Author: cc
|
||||
*
|
||||
* Ŀǰ<C4BF><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD> RS485<38><35>
|
||||
*
|
||||
* Uart1 -> <20><><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>
|
||||
* Uart0 -> U1 -> RS485 1
|
||||
* UART2 -> U2 -> RS485 2
|
||||
* Uart3 -> U3 -> BUS
|
||||
*
|
||||
*/
|
||||
|
||||
#include "includes.h"
|
||||
|
||||
#include <string.h>
|
||||
|
||||
UART_t g_uart[UART_MAX];
|
||||
|
||||
void UART0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void UART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void UART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void UART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UARTx_Init
|
||||
* @brief UART<52><54>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><EFBFBD><E2B4AE>2ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PB22,PB23 - Boot,RST<53><54><EFBFBD><EFBFBD>
|
||||
* @param uart_id - <20><><EFBFBD><EFBFBD>ID
|
||||
* @param buad - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @param prt_cf - <20><><EFBFBD>ڽ<EFBFBD><DABD>ջص<D5BB><D8B5><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @return none
|
||||
*/
|
||||
void UARTx_Init(UART_IDX uart_id, uint32_t buad) {
|
||||
|
||||
switch (uart_id) {
|
||||
case UART_0:
|
||||
//RS485ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
|
||||
GPIOD_ModeCfg(GPIO_Pin_21, GPIO_ModeOut_PP);
|
||||
MCU485_EN1_L;
|
||||
|
||||
UART0_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating);
|
||||
|
||||
UART0_BaudRateCfg(buad);
|
||||
R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART0_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART0_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART0_CLR_RXFIFO();
|
||||
UART0_CLR_TXFIFO();
|
||||
|
||||
UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
|
||||
memset(&g_uart[UART_0],0,sizeof(UART_t));
|
||||
Set_Uart_recvTimeout(&g_uart[UART_0],buad);
|
||||
|
||||
g_uart[UART_0].send_data_cf = UART0_SendString;
|
||||
g_uart[UART_0].set_baud_cf = UART0_ChangeBaud;
|
||||
break;
|
||||
case UART_1:
|
||||
UART1_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating);
|
||||
|
||||
UART1_BaudRateCfg(buad);
|
||||
R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART1_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART1_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART1_IRQn);
|
||||
|
||||
memset(&g_uart[UART_1],0,sizeof(UART_t));
|
||||
Set_Uart_recvTimeout(&g_uart[UART_1],buad);
|
||||
|
||||
g_uart[UART_1].send_data_cf = UART1_SendString;
|
||||
g_uart[UART_1].set_baud_cf = UART1_ChangeBaud;
|
||||
break;
|
||||
case UART_2:
|
||||
//RS485ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
|
||||
GPIOB_ModeCfg(GPIO_Pin_15, GPIO_ModeOut_PP);
|
||||
MCU485_EN2_L;
|
||||
|
||||
UART2_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating);
|
||||
|
||||
UART2_BaudRateCfg(buad);
|
||||
R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART2_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART2_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART2_IRQn);
|
||||
|
||||
memset(&g_uart[UART_2],0,sizeof(UART_t));
|
||||
Set_Uart_recvTimeout(&g_uart[UART_2],buad);
|
||||
|
||||
g_uart[UART_2].send_data_cf = UART2_SendString;
|
||||
g_uart[UART_2].set_baud_cf = UART2_ChangeBaud;
|
||||
break;
|
||||
case UART_3:
|
||||
UART3_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating);
|
||||
|
||||
UART3_BaudRateCfg(buad);
|
||||
R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART3_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART3_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART3_IRQn);
|
||||
|
||||
memset(&g_uart[UART_3],0,sizeof(UART_t));
|
||||
Set_Uart_recvTimeout(&g_uart[UART_3],buad);
|
||||
|
||||
g_uart[UART_3].send_data_cf = UART3_SendString;
|
||||
g_uart[UART_3].set_baud_cf = UART3_ChangeBaud;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud)
|
||||
{
|
||||
if(baud == 115200)
|
||||
{
|
||||
set_uart->RecvTimeout = Recv_115200_TimeOut;
|
||||
}else if(baud == 9600)
|
||||
{
|
||||
set_uart->RecvTimeout = Recv_9600_TimeOut;
|
||||
}else if(baud == 2400)
|
||||
{
|
||||
set_uart->RecvTimeout = Recv_2400_TimeOut;
|
||||
}else if(baud == 512000)
|
||||
{
|
||||
set_uart->RecvTimeout = Recv_512000_TimeOut;
|
||||
}else
|
||||
{
|
||||
set_uart->RecvTimeout = 20;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART1_IRQHandler
|
||||
*
|
||||
* @brief USART1<54>жϺ<D0B6><CFBA><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
switch( UART0_GetITFlag() )
|
||||
{
|
||||
case UART_II_THR_EMPTY:
|
||||
|
||||
break;
|
||||
case UART_II_RECV_RDY:
|
||||
case UART_II_RECV_TOUT:
|
||||
if( (g_uart[UART_0].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_0].RecvLen = 0x00;
|
||||
g_uart[UART_0].RecvBuffer[g_uart[UART_0].RecvLen] = UART0_RecvByte();
|
||||
g_uart[UART_0].RecvLen += 1;
|
||||
g_uart[UART_0].Receiving = 0x01;
|
||||
g_uart[UART_0].RecvIdleTiming = SysTick_1ms;
|
||||
|
||||
//<2F><>ǰ<EFBFBD><C7B0><EFBFBD>ڷ<EFBFBD>æ״̬
|
||||
g_uart[UART_0].CommBusy |= UART_COMMBUSY_RECV_Flag;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART1_IRQHandler
|
||||
*
|
||||
* @brief USART1<54>жϺ<D0B6><CFBA><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART1_IRQHandler(void)
|
||||
{
|
||||
switch( UART1_GetITFlag() )
|
||||
{
|
||||
case UART_II_THR_EMPTY:
|
||||
|
||||
break;
|
||||
case UART_II_RECV_RDY:
|
||||
case UART_II_RECV_TOUT:
|
||||
if( (g_uart[UART_1].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_1].RecvLen = 0x00;
|
||||
g_uart[UART_1].RecvBuffer[g_uart[UART_1].RecvLen] = UART1_RecvByte();
|
||||
g_uart[UART_1].RecvLen += 1;
|
||||
g_uart[UART_1].Receiving = 0x01;
|
||||
g_uart[UART_1].RecvIdleTiming = SysTick_1ms;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART2_IRQHandler
|
||||
*
|
||||
* @brief USART2<54>жϺ<D0B6><CFBA><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
switch( UART2_GetITFlag() )
|
||||
{
|
||||
case UART_II_THR_EMPTY:
|
||||
|
||||
break;
|
||||
case UART_II_RECV_RDY:
|
||||
case UART_II_RECV_TOUT:
|
||||
if( (g_uart[UART_2].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_2].RecvLen = 0x00;
|
||||
g_uart[UART_2].RecvBuffer[g_uart[UART_2].RecvLen] = UART2_RecvByte();
|
||||
g_uart[UART_2].RecvLen += 1;
|
||||
g_uart[UART_2].Receiving = 0x01;
|
||||
g_uart[UART_2].RecvIdleTiming = SysTick_1ms;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART3_IRQHandler
|
||||
*
|
||||
* @brief USART3<54>жϺ<D0B6><CFBA><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART3_IRQHandler(void)
|
||||
{
|
||||
switch( UART3_GetITFlag() )
|
||||
{
|
||||
case UART_II_THR_EMPTY:
|
||||
|
||||
break;
|
||||
case UART_II_RECV_RDY:
|
||||
case UART_II_RECV_TOUT:
|
||||
if( (g_uart[UART_3].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_3].RecvLen = 0x00;
|
||||
g_uart[UART_3].RecvBuffer[g_uart[UART_3].RecvLen] = UART3_RecvByte();
|
||||
g_uart[UART_3].RecvLen += 1;
|
||||
g_uart[UART_3].Receiving = 0x01;
|
||||
g_uart[UART_3].RecvIdleTiming = SysTick_1ms;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART1_RECEIVE
|
||||
*
|
||||
* @brief USART1
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_RECEIVE(void)
|
||||
{
|
||||
if(g_uart[UART_0].Receiving == 0x01)
|
||||
{
|
||||
if(SysTick_1ms - g_uart[UART_0].RecvIdleTiming >= g_uart[UART_0].RecvTimeout)
|
||||
{
|
||||
g_uart[UART_0].RecvIdleTiming = SysTick_1ms;
|
||||
|
||||
DBG_SYS_Printf("--UART0_RECEIVE--\r\n");
|
||||
Launcher_Uart_Upgrade_Process(&g_uart[UART_0]);
|
||||
|
||||
g_uart[UART_0].RecvLen = 0;
|
||||
g_uart[UART_0].Receiving = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART1_RECEIVE
|
||||
*
|
||||
* @brief USART1
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART1_RECEIVE(void)
|
||||
{
|
||||
if(g_uart[UART_1].Receiving == 0x01)
|
||||
{
|
||||
if(SysTick_1ms - g_uart[UART_1].RecvIdleTiming >= g_uart[UART_1].RecvTimeout)
|
||||
{
|
||||
g_uart[UART_1].RecvIdleTiming = SysTick_1ms;
|
||||
|
||||
DBG_SYS_Printf("--UART1_RECEIVE--\r\n");
|
||||
Launcher_Uart_Upgrade_Process(&g_uart[UART_1]);
|
||||
|
||||
g_uart[UART_1].RecvLen = 0;
|
||||
g_uart[UART_1].Receiving = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART2_RECEIVE
|
||||
*
|
||||
* @brief USART2
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART2_RECEIVE(void)
|
||||
{
|
||||
if(g_uart[UART_2].Receiving == 1)
|
||||
{
|
||||
if(SysTick_1ms - g_uart[UART_2].RecvIdleTiming > g_uart[UART_2].RecvTimeout)
|
||||
{
|
||||
g_uart[UART_2].RecvIdleTiming = SysTick_1ms;
|
||||
|
||||
DBG_SYS_Printf("--UART2_RECEIVE--\r\n");
|
||||
Launcher_Uart_Upgrade_Process(&g_uart[UART_2]);
|
||||
|
||||
g_uart[UART_2].RecvLen = 0;
|
||||
g_uart[UART_2].Receiving = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART3_RECEIVE
|
||||
*
|
||||
* @brief UART3
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART3_RECEIVE(void)
|
||||
{
|
||||
if(g_uart[UART_3].Receiving == 1)
|
||||
{
|
||||
if(SysTick_1ms - g_uart[UART_3].RecvIdleTiming > g_uart[UART_3].RecvTimeout)
|
||||
{
|
||||
g_uart[UART_3].RecvIdleTiming = SysTick_1ms;
|
||||
|
||||
DBG_SYS_Printf("--UART3_RECEIVE--\r\n");
|
||||
Launcher_Uart_Upgrade_Process(&g_uart[UART_3]);
|
||||
|
||||
g_uart[UART_3].RecvLen = 0;
|
||||
g_uart[UART_3].Receiving = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART0_ChangeBaud
|
||||
*
|
||||
* @brief UART0<54>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t UART0_ChangeBaud(uint32_t baudrate)
|
||||
{
|
||||
uint16_t delay_num = 0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
||||
__disable_irq();
|
||||
|
||||
UART0_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating);
|
||||
|
||||
UART0_BaudRateCfg(baudrate);
|
||||
R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART0_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART0_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART0_CLR_RXFIFO();
|
||||
UART0_CLR_TXFIFO();
|
||||
|
||||
UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
|
||||
Set_Uart_recvTimeout(&g_uart[UART_0],baudrate);
|
||||
|
||||
__enable_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Delay_Us(100);
|
||||
delay_num++;
|
||||
if(delay_num > 500) break;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART1_ChangeBaud
|
||||
*
|
||||
* @brief UART1<54>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t UART1_ChangeBaud(uint32_t baudrate)
|
||||
{
|
||||
uint16_t delay_num = 0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
||||
__disable_irq();
|
||||
|
||||
UART1_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating);
|
||||
|
||||
UART1_BaudRateCfg(baudrate);
|
||||
R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART1_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART1_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART1_IRQn);
|
||||
|
||||
Set_Uart_recvTimeout(&g_uart[UART_1],baudrate);
|
||||
|
||||
__enable_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Delay_Us(100);
|
||||
delay_num++;
|
||||
if(delay_num > 500) break;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART2_ChangeBaud
|
||||
*
|
||||
* @brief UART2<54>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t UART2_ChangeBaud(uint32_t baudrate)
|
||||
{
|
||||
uint16_t delay_num = 0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
||||
__disable_irq();
|
||||
|
||||
UART2_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating);
|
||||
|
||||
UART2_BaudRateCfg(baudrate);
|
||||
R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART2_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART2_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART2_IRQn);
|
||||
|
||||
Set_Uart_recvTimeout(&g_uart[UART_2],baudrate);
|
||||
|
||||
__enable_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Delay_Us(100);
|
||||
delay_num++;
|
||||
if(delay_num > 500) break;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn UART3_ChangeBaud
|
||||
*
|
||||
* @brief UART3<54>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t UART3_ChangeBaud(uint32_t baudrate)
|
||||
{
|
||||
uint16_t delay_num = 0;
|
||||
|
||||
while(1)
|
||||
{
|
||||
if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP )
|
||||
{
|
||||
/*<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>*/
|
||||
__disable_irq();
|
||||
|
||||
UART3_Reset();
|
||||
|
||||
GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE);
|
||||
GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP);
|
||||
GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating);
|
||||
|
||||
UART3_BaudRateCfg(baudrate);
|
||||
R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART3_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART3_IER = RB_IER_TXD_EN;
|
||||
|
||||
UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY);
|
||||
NVIC_EnableIRQ(UART3_IRQn);
|
||||
|
||||
Set_Uart_recvTimeout(&g_uart[UART_3],baudrate);
|
||||
|
||||
__enable_irq();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Delay_Us(100);
|
||||
delay_num++;
|
||||
if(delay_num > 500) break;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* RS485ͨѶ<CDA8><D1B6><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD>
|
||||
* 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݺȴ<F3A3ACB5><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>(<28><><EFBFBD>ݲ<EFBFBD>ͬ<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3>ȴ<EFBFBD>ʱ<EFBFBD>䲻ͬ),<2C>ȴ<EFBFBD><C8B4><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>
|
||||
* 2<><32><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ݺȴ<F3A3ACB5><C8B4><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>״̬
|
||||
* 3<><33><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><DFBF>пɽ<D0BF><C9BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>߷<EFBFBD>æ<EFBFBD><C3A6><EFBFBD><EFBFBD><EFBFBD>ɷ<EFBFBD><C9B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* 4<><34><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD>ڷ<EFBFBD><DAB7>ͣ<EFBFBD>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>¼<EFBFBD><C2BC>ǰʱ<C7B0>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD>ں<DABA><F3A3ACB8><EFBFBD><EFBFBD>ݱ㲻<DDB1>ڷ<EFBFBD><DAB7><EFBFBD>
|
||||
* 5<><35><EFBFBD><EFBFBD>ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD><EFBFBD>л<EFBFBD>ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* - 1<><31><EFBFBD><EFBFBD>æ״̬
|
||||
* - 2<><32><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||||
* - 3<><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1>
|
||||
*
|
||||
* */
|
||||
|
||||
uint8_t MCU485_SendString_1(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
uint32_t delay_num = 0;
|
||||
MCU485_EN1_H;
|
||||
|
||||
UART0_SendString(buff,len);
|
||||
|
||||
//<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 50ms
|
||||
while(1)
|
||||
{
|
||||
if((R8_UART0_LSR & RB_LSR_TX_ALL_EMP)) break;
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 50000) break;
|
||||
}
|
||||
|
||||
MCU485_EN1_L;
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
uint8_t MCU485_SendString_2(uint8_t *buff, uint16_t len)
|
||||
{
|
||||
uint32_t delay_num = 0;
|
||||
MCU485_EN2_H;
|
||||
|
||||
UART2_SendString(buff,len);
|
||||
|
||||
//<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 50ms
|
||||
while(1)
|
||||
{
|
||||
if((R8_UART2_LSR & RB_LSR_TX_ALL_EMP)) break;
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 50000) break;
|
||||
}
|
||||
|
||||
MCU485_EN2_L;
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Uart0_Add_Data_To_SendBuff
|
||||
* Description : Uart0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뷢<EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>
|
||||
* Input :
|
||||
buff<66><66><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
len<65><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
|
||||
sendCount <20><><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD>
|
||||
ValidDuration <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7>䣬<EFBFBD><E4A3AC>λ<EFBFBD><CEBB>ms
|
||||
sendInterval <20><><EFBFBD><EFBFBD><EFBFBD>ͼ<EFBFBD><CDBC><EFBFBD>ʱ<EFBFBD>䣬<EFBFBD><E4A3AC>λ<EFBFBD><CEBB>ms
|
||||
*******************************************************************************/
|
||||
uint8_t Uart0_Add_Data_To_SendBuff(uint8_t *buff,uint16_t len,uint8_t sendCount,uint32_t ValidDuration,uint32_t sendInterval)
|
||||
{
|
||||
if( buff == NULL) return 0x01;
|
||||
if( len > USART_BUFFER_SIZE ) return 0x02;
|
||||
|
||||
memset(g_uart[UART_0].SendBuffer,0,USART_BUFFER_SIZE);
|
||||
memcpy(g_uart[UART_0].SendBuffer,buff,len);
|
||||
g_uart[UART_0].SendLen = len;
|
||||
g_uart[UART_0].SendCount = sendCount;
|
||||
g_uart[UART_0].SendCnt = 0;
|
||||
g_uart[UART_0].SendValidDuration = ValidDuration;
|
||||
g_uart[UART_0].SendInterval = sendInterval;
|
||||
g_uart[UART_0].SendValidTick = SysTick_1ms;
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Uart0_Clear_SendBuff
|
||||
* Description : Uart0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱȡ<CAB1><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t Uart0_Clear_SendBuff(void)
|
||||
{
|
||||
memset(g_uart[UART_0].SendBuffer,0,USART_BUFFER_SIZE);
|
||||
g_uart[UART_0].SendLen = 0x00;
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : Uart0_Avoid_Conflict_Send_Task
|
||||
* Description : Uart0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*******************************************************************************/
|
||||
uint8_t Uart0_Avoid_Conflict_Send_Task(void)
|
||||
{
|
||||
if( (g_uart[UART_0].SendLen == 0x00) || (g_uart[UART_0].SendLen > USART_BUFFER_SIZE) ) return 0x01;
|
||||
|
||||
if( g_uart[UART_0].SendCnt >= g_uart[UART_0].SendCount ) {
|
||||
//<2F><><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﵽ<EFBFBD><EFB5BD><EFBFBD>ޣ<EFBFBD><DEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
||||
g_uart[UART_0].SendLen = 0x00;
|
||||
return 0x02;
|
||||
}
|
||||
|
||||
if( SysTick_1ms - g_uart[UART_0].SendValidTick >= g_uart[UART_0].SendInterval ){
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>Ч<EFBFBD>ڣ<EFBFBD><DAA3>㲻<EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
||||
g_uart[UART_0].SendLen = 0x00;
|
||||
return 0x03;
|
||||
}
|
||||
|
||||
if( g_uart[UART_0].CommBusy != UART_COMMBUSY_IDLE_Flag ) return 0x04; //ͨѶ<CDA8><D1B6><EFBFBD>ڷ<EFBFBD>æ״̬
|
||||
|
||||
//<2F><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>
|
||||
if( ( g_uart[UART_0].SendCnt == 0x00 ) || ( SysTick_1ms - g_uart[UART_0].SendTick >= g_uart[UART_0].SendInterval ) )
|
||||
{
|
||||
__disable_irq(); //<2F>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
||||
g_uart[UART_0].CommBusy |= UART_COMMBUSY_SEND_Flag;
|
||||
g_uart[UART_0].SendIdleTick = SysTick_1ms;
|
||||
__enable_irq(); //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
||||
|
||||
UART0_SendString(g_uart[UART_0].SendBuffer, g_uart[UART_0].SendLen);
|
||||
g_uart[UART_0].SendTick = SysTick_1ms;
|
||||
g_uart[UART_0].SendCnt++;
|
||||
|
||||
if( g_uart[UART_0].SendCnt >= g_uart[UART_0].SendCount )
|
||||
{
|
||||
memset(g_uart[UART_0].SendBuffer,0,USART_BUFFER_SIZE);
|
||||
g_uart[UART_0].SendLen = 0x00;
|
||||
|
||||
return 0x05; //ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>
|
||||
}
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void Uart0_Task(void)
|
||||
{
|
||||
UART0_RECEIVE();
|
||||
|
||||
Uart0_Avoid_Conflict_Send_Task();
|
||||
|
||||
if( g_uart[UART_0].CommBusy == UART_COMMBUSY_IDLE_Flag )
|
||||
{
|
||||
/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>״̬ - <20><><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʲ<EFBFBD><CAB2><EFBFBD>*/
|
||||
if( g_uart[UART_0].ChangeBaudFlag == 0x01 )
|
||||
{
|
||||
g_uart[UART_0].set_baud_cf(g_uart[UART_0].CommBaud);
|
||||
g_uart[UART_0].ChangeBaudFlag = 0x00;
|
||||
}
|
||||
|
||||
}else {
|
||||
/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD>ڷ<EFBFBD><DAB7>ͷ<EFBFBD>æ״̬<D7B4><CCAC><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF><EFBFBD>״̬ - <20>ж<EFBFBD>ʹ<EFBFBD>ó<EFBFBD>ʱʱ<CAB1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD>ʱʱ<CAB1><CAB1>һ<EFBFBD><D2BB>*/
|
||||
if( ((g_uart[UART_0].CommBusy & UART_COMMBUSY_SEND_Flag) != 0x00 ) && ( SysTick_1ms - g_uart[UART_0].SendIdleTick >= g_uart[UART_0].RecvTimeout ) )
|
||||
{
|
||||
g_uart[UART_0].SendIdleTick = SysTick_1ms;
|
||||
|
||||
__disable_irq(); //<2F>ر<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
||||
g_uart[UART_0].CommBusy &= ~(UART_COMMBUSY_SEND_Flag);
|
||||
g_uart[UART_0].SendIdleTick = SysTick_1ms;
|
||||
__enable_irq(); //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>ж<EFBFBD>
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
1864
Peripheral/inc/ch564.h
Normal file
1864
Peripheral/inc/ch564.h
Normal file
File diff suppressed because it is too large
Load Diff
283
Peripheral/inc/ch564_adc.h
Normal file
283
Peripheral/inc/ch564_adc.h
Normal file
@@ -0,0 +1,283 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_adc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* ADC firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_ADC_H
|
||||
#define __CH564_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ADC_Channel0 = 0x00,
|
||||
ADC_Channel1,
|
||||
ADC_Channel2,
|
||||
ADC_Channel0_1,
|
||||
ADC_Channel3,
|
||||
ADC_Channel4,
|
||||
ADC_Channel5,
|
||||
ADC_Channel6,
|
||||
ADC_ChannelREF,
|
||||
ADC_ChannelCN
|
||||
} ADCChannelTypedef;
|
||||
/***********************************************************************************
|
||||
* @fn ADC_CMD
|
||||
*
|
||||
* @brief ADC Enable/Disable
|
||||
*
|
||||
* @param en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
*/
|
||||
#define ADC_CMD(en) \
|
||||
{ \
|
||||
(en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_POWER_ON) : (R8_ADC_CTRL_MOD &= ~RB_ADC_POWER_ON); \
|
||||
}
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_SAMPLE_WIDTH_2CLK
|
||||
*
|
||||
* @brief ADC Sample time 2clk enable
|
||||
*
|
||||
* @param en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_SAMPLE_WIDTH_2CLK(en) \
|
||||
{ \
|
||||
(en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_SAMPLE_WID) : (R8_ADC_CTRL_MOD &= RB_ADC_SAMPLE_WID); \
|
||||
}
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_SAMPLE_CYCLE
|
||||
*
|
||||
* @brief Config ADC sample cycle.
|
||||
*
|
||||
* @param val
|
||||
* - val = 0:Manual Control
|
||||
* - val = 0b000001 - 0b111111:Sampling every val clock
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_SAMPLE_CYCLE(val) \
|
||||
({ \
|
||||
R8_ADC_CTRL_MOD &= ~RB_ADC_CYCLE_CLK; \
|
||||
R8_ADC_CTRL_MOD |= (val) & RB_ADC_CYCLE_CLK; \
|
||||
R32_ADC_CTRL &= ~MASK_ADC_CYCLE_BIT_4_6; \
|
||||
R32_ADC_CTRL |= (((val) >> 4) << 25) & MASK_ADC_CYCLE_BIT_4_6; \
|
||||
})
|
||||
/***********************************************************************************
|
||||
* @fn ADC_DMA_CMD
|
||||
*
|
||||
* @brief Config the ADC DMA control and etc.
|
||||
*
|
||||
* @param RB_ADC_IE
|
||||
* - RB_ADC_IE_ADC_CMP
|
||||
* - RB_ADC_DMA_ENABLE
|
||||
* - RB_ADC_DMA_BURST
|
||||
* - RB_ADC_DMA_LOOP
|
||||
* - RB_ADC_CHAN_OE
|
||||
* - RB_ADC_MAN_SAMPLE
|
||||
*
|
||||
* en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_DMA_CMD(RB_ADC_DMA, en) \
|
||||
({ (en) == ENABLE ? (R8_ADC_CTRL_DMA |= (RB_ADC_DMA)) : (R8_ADC_CTRL_DMA &= ~(RB_ADC_DMA)); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_IT_CONFIG
|
||||
*
|
||||
* @brief ADC interrupt enable
|
||||
*
|
||||
* @param RB_ADC_IE
|
||||
* - RB_ADC_IE_ADC_CMP
|
||||
* - RB_ADC_IE_ADC_END
|
||||
* - RB_ADC_IE_FIFO_HF
|
||||
* - RB_ADC_IE_DMA_END
|
||||
* - RB_ADC_IE_FIFO_OV
|
||||
* - RB_ADC_IE_DMA_ERR
|
||||
* - RB_ADC_CMP_MOD_EQ
|
||||
* - RB_ADC_CMP_MOD_GT
|
||||
* en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_IT_CONFIG(RB_ADC_IE, en) \
|
||||
({ (en) == ENABLE ? (R8_ADC_INTER_EN |= (RB_ADC_IE)) : (R8_ADC_INTER_EN &= ~(RB_ADC_IE)); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_12BITRESOLUTION
|
||||
*
|
||||
* @brief ADC 12bit resolution enable
|
||||
*
|
||||
* @param en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_12BITRESOLUTION(en) \
|
||||
({ (en) == ENABLE ? (R32_ADC_CTRL |= MASK_ADC_BIT_MODE) : (R32_ADC_CTRL &= ~MASK_ADC_BIT_MODE); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_SAMPLE_TIME
|
||||
*
|
||||
* @brief Config ADC sample calibration time.
|
||||
*
|
||||
* @param val
|
||||
* - ADC sample calibration time
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_SAMPLE_TIME(val) \
|
||||
({ \
|
||||
R32_ADC_CTRL &= ~MASK_ADC_SMAPLE_TIME; \
|
||||
R32_ADC_CTRL |= MASK_ADC_SMAPLE_TIME & ((val) << 4); \
|
||||
})
|
||||
/***********************************************************************************
|
||||
* @fn ADC_DMA_SET_RANGE
|
||||
*
|
||||
* @brief Config ADC DMA transport range
|
||||
*
|
||||
* @param startAddress
|
||||
* - ADC DMA Handling Start Address
|
||||
* endAddress
|
||||
* - ADC DMA Handling End Address
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_DMA_SET_RANGE(startAddress, endAddress) \
|
||||
({ \
|
||||
R32_ADC_DMA_BEG = (uint32_t)(startAddress) & MASK_ADC_DMA_ADDR; \
|
||||
R32_ADC_DMA_END = (uint32_t)(endAddress) & MASK_ADC_DMA_ADDR; \
|
||||
})
|
||||
/***********************************************************************************
|
||||
* @fn ADC_DMA_GET_CURRENT
|
||||
*
|
||||
* @brief Get ADC DMA current transport address
|
||||
*
|
||||
* @return R32_ADC_DMA_NOW
|
||||
*/
|
||||
#define ADC_DMA_GET_CURRENT() (R32_ADC_DMA_NOW & MASK_ADC_DMA_ADDR)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_DMA_GET_BEGIN
|
||||
*
|
||||
* @brief Get ADC DMA start transport address
|
||||
*
|
||||
* @return R32_ADC_DMA_BEG
|
||||
*/
|
||||
#define ADC_DMA_GET_BEGIN() (R32_ADC_DMA_BEG & MASK_ADC_DMA_ADDR)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_DMA_GET_END
|
||||
*
|
||||
* @brief Get ADC DMA end transport address
|
||||
*
|
||||
* @return R32_ADC_DMA_END
|
||||
*/
|
||||
#define ADC_DMA_GET_END() (R32_ADC_DMA_END & MASK_ADC_DMA_ADDR)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_GET_FIFO
|
||||
*
|
||||
* @brief Get ADC's FIFO content
|
||||
*
|
||||
* @return R16_ADC_FIFO
|
||||
*/
|
||||
#define ADC_GET_FIFO() (R16_ADC_FIFO)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_COMPARE_VAL
|
||||
*
|
||||
* @brief Config ADC comparison reference value
|
||||
*
|
||||
* @param val
|
||||
* - ADC comparison reference value
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_COMPARE_VAL(val) ({ R16_ADC_CMP_VALUE = ADC_CMP_VALUE & (val); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_GET_FIFO_CNT
|
||||
*
|
||||
* @brief Get ADC's FIFO count
|
||||
*
|
||||
* @return R8_ADC_FIFO_COUNT
|
||||
*/
|
||||
#define ADC_GET_FIFO_CNT() (R8_ADC_FIFO_COUNT)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_GET_VAL
|
||||
*
|
||||
* @brief Get ADC's converted value
|
||||
*
|
||||
* @return R16_ADC_DATA
|
||||
*/
|
||||
#define ADC_GET_VAL() (R16_ADC_DATA)
|
||||
/***********************************************************************************
|
||||
* @fn ADC_SET_DIV
|
||||
*
|
||||
* @brief Config ADC crossover coefficients
|
||||
*
|
||||
* @param val
|
||||
* - ADC crossover coefficients
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_SET_DIV(value) ({ R8_ADC_CLOCK_DIV = (value); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_CLEAR_IT
|
||||
*
|
||||
* @brief Config ADC crossover coefficients
|
||||
*
|
||||
* @param RB_ADC_IF
|
||||
* - RB_ADC_IF_ADC_CMP
|
||||
* - RB_ADC_IF_ADC_END
|
||||
* - RB_ADC_IF_FIFO_HF
|
||||
* - RB_ADC_IF_DMA_END
|
||||
* - RB_ADC_IF_FIFO_OV
|
||||
* - RB_ADC_IF_DMA_ERR
|
||||
* - RB_ADC_EOC_FLAG
|
||||
* - RB_ADC_CHAN_INDEX
|
||||
* en
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
*/
|
||||
#define ADC_CLEAR_IT(RB_ADC_IF) ({ R8_ADC_INT_FLAG |= (RB_ADC_IF); })
|
||||
/***********************************************************************************
|
||||
* @fn ADC_GET_IT
|
||||
*
|
||||
* @brief Config ADC crossover coefficients
|
||||
*
|
||||
* @param RB_ADC_IF
|
||||
* - RB_ADC_IF_ADC_CMP
|
||||
* - RB_ADC_IF_ADC_END
|
||||
* - RB_ADC_IF_FIFO_HF
|
||||
* - RB_ADC_IF_DMA_END
|
||||
* - RB_ADC_IF_FIFO_OV
|
||||
* - RB_ADC_IF_DMA_ERR
|
||||
* - RB_ADC_EOC_FLAG
|
||||
* - RB_ADC_CHAN_INDEX
|
||||
* @return 0:No Interrupt or interrupt flag
|
||||
*
|
||||
*/
|
||||
#define ADC_GET_IT(RB_ADC_IF) (R8_ADC_INT_FLAG & (RB_ADC_IF))
|
||||
/***********************************************************************************
|
||||
* @fn ADC_MEASURE
|
||||
*
|
||||
* @brief Manually initiated measurements
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
#define ADC_MEASURE() ({ R8_ADC_CTRL_DMA |= RB_ADC_MAN_SAMPLE; })
|
||||
|
||||
void ADC_SelectChannel(ADCChannelTypedef adcChannel);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1446
Peripheral/inc/ch564_eth.h
Normal file
1446
Peripheral/inc/ch564_eth.h
Normal file
File diff suppressed because it is too large
Load Diff
237
Peripheral/inc/ch564_gpio.h
Normal file
237
Peripheral/inc/ch564_gpio.h
Normal file
@@ -0,0 +1,237 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_gpio.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_GPIO_H
|
||||
#define __CH564_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
#define GPIO_Pin_0 (0x00000001)/*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 (0x00000002)/*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 (0x00000004)/*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 (0x00000008)/*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 (0x00000010)/*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 (0x00000020)/*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 (0x00000040)/*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 (0x00000080)/*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 (0x00000100)/*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 (0x00000200)/*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 (0x00000400)/*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 (0x00000800)/*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 (0x00001000)/*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 (0x00002000)/*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 (0x00004000)/*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 (0x00008000)/*!< Pin 15 selected */
|
||||
#define GPIO_Pin_16 (0x00010000)/*!< Pin 16 selected */
|
||||
#define GPIO_Pin_17 (0x00020000)/*!< Pin 17 selected */
|
||||
#define GPIO_Pin_18 (0x00040000)/*!< Pin 18 selected */
|
||||
#define GPIO_Pin_19 (0x00080000)/*!< Pin 19 selected */
|
||||
#define GPIO_Pin_20 (0x00100000)/*!< Pin 20 selected */
|
||||
#define GPIO_Pin_21 (0x00200000)/*!< Pin 21 selected */
|
||||
#define GPIO_Pin_22 (0x00400000)/*!< Pin 22 selected */
|
||||
#define GPIO_Pin_23 (0x00800000)/*!< Pin 23 selected */
|
||||
#define GPIO_Pin_24 (0x01000000)/*!< Pin 24 selected */
|
||||
#define GPIO_Pin_25 (0x02000000)/*!< Pin 25 selected */
|
||||
#define GPIO_Pin_26 (0x04000000)/*!< Pin 26 selected */
|
||||
#define GPIO_Pin_27 (0x08000000)/*!< Pin 27 selected */
|
||||
#define GPIO_Pin_28 (0x10000000)/*!< Pin 28 selected */
|
||||
#define GPIO_Pin_29 (0x20000000)/*!< Pin 29 selected */
|
||||
#define GPIO_Pin_30 (0x40000000)/*!< Pin 30 selected */
|
||||
#define GPIO_Pin_31 (0x80000000)/*!< Pin 31 selected */
|
||||
#define GPIO_Pin_All (0xFFFFFFFF)/*!< All pins selected */
|
||||
|
||||
#define GPIO_NoRemap_SPI0 (0x00020000)
|
||||
#define GPIO_PartialRemap1_SPI0 (0x00020001)
|
||||
#define GPIO_PartialRemap2_SPI0 (0x00020002)
|
||||
#define GPIO_FullRemap_SPI0 (0x00020003)
|
||||
|
||||
#define GPIO_NoRemap_UART0 (0x00220000)
|
||||
#define GPIO_PartialRemap2_UART0 (0x00220002)
|
||||
#define GPIO_FullRemap_UART0 (0x00220003)
|
||||
|
||||
#define GPIO_NoRemap_UART1 (0x00420000)
|
||||
#define GPIO_PartialRemap1_UART1 (0x00420001)
|
||||
#define GPIO_FullRemap_UART1 (0x00420003)
|
||||
|
||||
#define GPIO_NoRemap_UART2 (0x00620000)
|
||||
#define GPIO_PartialRemap1_UART2 (0x00620001)
|
||||
#define GPIO_PartialRemap2_UART2 (0x00620002)
|
||||
#define GPIO_FullRemap_UART2 (0x00620003)
|
||||
|
||||
#define GPIO_NoRemap_UART3 (0x00820000)
|
||||
#define GPIO_PartialRemap1_UART3 (0x00820001)
|
||||
#define GPIO_FullRemap_UART3 (0x00820003)
|
||||
|
||||
#define GPIO_NoRemap_UART0_MODEM (0x00a20000)
|
||||
#define GPIO_PartialRemap1_UART0_MODEM (0x00a20001)
|
||||
#define GPIO_PartialRemap2_UART0_MODEM (0x00a20002)
|
||||
#define GPIO_FullRemap_UART0_MODEM (0x00a20003)
|
||||
|
||||
#define GPIO_NoRemap_UART1_MODEM (0x00c20000)
|
||||
#define GPIO_PartialRemap1_UART1_MODEM (0x00c20001)
|
||||
#define GPIO_PartialRemap2_UART1_MODEM (0x00c20002)
|
||||
#define GPIO_FullRemap_UART1_MODEM (0x00c20003)
|
||||
|
||||
#define GPIO_NoRemap_UART2_MODEM (0x00e20000)
|
||||
#define GPIO_PartialRemap2_UART2_MODEM (0x00e20002)
|
||||
#define GPIO_FullRemap_UART2_MODEM (0x00e20003)
|
||||
|
||||
#define GPIO_NoRemap_I2C (0x01020000)
|
||||
#define GPIO_PartialRemap1_I2C (0x01020001)
|
||||
|
||||
#define GPIO_NoRemap_SLV_INTERUPT (0x01220000)
|
||||
#define GPIO_PartialRemap1_SLV_INTERUPT (0x01220001)
|
||||
#define GPIO_PartialRemap2_SLV_INTERUPT (0x01220002)
|
||||
#define GPIO_FullRemap_SLV_INTERUPT (0x01220003)
|
||||
|
||||
#define GPIO_NoRemap_SLV_CS (0x01420000)
|
||||
#define GPIO_PartialRemap1_SLV_CS (0x01420001)
|
||||
|
||||
#define GPIO_NoRemap_SLV_ADDR (0x01620000)
|
||||
#define GPIO_PartialRemap1_SLV_ADDR (0x01620001)
|
||||
#define GPIO_PartialRemap2_SLV_ADDR (0x01620002)
|
||||
|
||||
#define GPIO_NoRemap_SLV_ADDR1 (0x01820000)
|
||||
#define GPIO_PartialRemap2_SLV_ADDR1 (0x01820002)
|
||||
#define GPIO_FullRemap_SLV_ADDR1 (0x01820003)
|
||||
|
||||
#define GPIO_NoRemap_SLV_DATA (0x01a20000)
|
||||
#define GPIO_PartialRemap1_SLV_DATA (0x01a20001)
|
||||
|
||||
#define GPIO_NoRemap_SLV_RW (0x01c20000)
|
||||
#define GPIO_NolRemap_SLV_RW GPIO_NoRemap_SLV_RW
|
||||
#define GPIO_PartialRemap1_SLV_RW (0x01c20001)
|
||||
|
||||
#define GPIO_NoRemap_LINK_LED (0x01e20000)
|
||||
#define GPIO_PartialRemap1_LINK_LED (0x01e20001)
|
||||
#define GPIO_PartialRemap2_LINK_LED (0x01e20002)
|
||||
#define GPIO_FullRemap_LINK_LED (0x01e20003)
|
||||
|
||||
#define GPIO_NoRemap_ACT_LED (0x80020000)
|
||||
#define GPIO_PartialRemap1_ACT_LED (0x80020001)
|
||||
#define GPIO_PartialRemap2_ACT_LED (0x80020002)
|
||||
#define GPIO_FullRemap_ACT_LED (0x80020003)
|
||||
|
||||
#define GPIO_NoRemap_RST (0x80220000)
|
||||
#define GPIO_PartialRemap1_RST (0x80220001)
|
||||
#define GPIO_PartialRemap2_RST (0x80220002)
|
||||
#define GPIO_FullRemap_RST (0x80220003)
|
||||
|
||||
#define GPIO_NoRemap_TIMER0 (0x80410000)
|
||||
#define GPIO_FullRemap_TIMER0 (0x80410001)
|
||||
|
||||
#define GPIO_NoRemap_TIMER1 (0x80510000)
|
||||
#define GPIO_FullRemap_TIMER1 (0x80510001)
|
||||
|
||||
#define GPIO_NoRemap_BUSY (0x80610000)
|
||||
#define GPIO_FullRemap_BUSY (0x80610001)
|
||||
|
||||
#define GPIO_NoRemap_SPI1 (0x80820000)
|
||||
#define GPIO_FullRemap_SPI1 (0x80820003)
|
||||
|
||||
#define GPIO_NoRemap_TNOW0 (0x80a20000)
|
||||
#define GPIO_FullRemap_TNOW0 (0x80a20003)
|
||||
|
||||
#define GPIO_NoRemap_TNOW1 (0x80c20000)
|
||||
#define GPIO_FullRemap_TNOW1 (0x80c20003)
|
||||
|
||||
#define GPIO_NoRemap_TNOW2 (0x80e20000)
|
||||
#define GPIO_FullRemap_TNOW2 (0x80e20003)
|
||||
|
||||
#define GPIO_NoRemap_TNOW3 (0x81020000)
|
||||
#define GPIO_FullRemap_TNOW3 (0x81020003)
|
||||
|
||||
#define GPIO_NoRemap_UART3_MODEM (0x81220000)
|
||||
#define GPIO_FullRemap_UART3_MODEM (0x81220003)
|
||||
|
||||
/**
|
||||
* @brief GPIO mode structure configuration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_ModeIN_Floating = 0,
|
||||
GPIO_ModeIN_PU,
|
||||
GPIO_ModeIN_PD,
|
||||
GPIO_ModeOut_PP,
|
||||
GPIO_ModeOut_OP
|
||||
} GPIOModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO interrupt structure configuration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_ITMode_LowLevel = 0, // Low level trigger
|
||||
GPIO_ITMode_HighLevel, // High level trigger
|
||||
GPIO_ITMode_FallEdge, // Falling edge trigger
|
||||
GPIO_ITMode_RiseEdge, // Rising edge trigger
|
||||
GPIO_ITMode_None
|
||||
} GPIOITModeTpDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO MCO structure configuration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
MCO_125 = 0,
|
||||
MCO_25 = 4,
|
||||
MCO_2d5 = 0xC,
|
||||
} MCOMode;
|
||||
|
||||
void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOA port pin mode configuration */
|
||||
void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */
|
||||
void GPIOD_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */
|
||||
#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin) /* GPIOA port pin output set low */
|
||||
#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin) /* GPIOA port pin output set high */
|
||||
#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin) /* GPIOB port pin output set low */
|
||||
#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin) /* GPIOB port pin output set high */
|
||||
#define GPIOD_ResetBits(pin) (R32_PD_OUT &= ~pin) /* GPIOA port pin output set low */
|
||||
#define GPIOD_SetBits(pin) (R32_PD_OUT |= pin) /* GPIOA port pin output set high */
|
||||
#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin) /* GPIOA port pin output level flip */
|
||||
#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin) /* GPIOB port pin output level flip */
|
||||
#define GPIOD_InverseBits(pin) (R32_PD_OUT ^= pin) /* GPIOB port pin output level flip */
|
||||
#define GPIOA_ReadPort() (R32_PA_PIN) /* The 32-bit data returned by the GPIOA port, the lower 16 bits are valid */
|
||||
#define GPIOB_ReadPort() (R32_PB_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */
|
||||
#define GPIOD_ReadPort() (R32_PD_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */
|
||||
#define GPIOA_ReadPortPin(pin) (R32_PA_PIN & pin) /* GPIOA port pin status, 0-pin low level, (!0)-pin high level */
|
||||
#define GPIOB_ReadPortPin(pin) (R32_PB_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */
|
||||
#define GPIOD_ReadPortPin(pin) (R32_PD_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */
|
||||
void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOA pin interrupt mode configuration */
|
||||
void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */
|
||||
void GPIOD_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */
|
||||
#define GPIOA_ReadITFlagPort() (R32_INT_STATUS_PA) /* Read GPIOA port interrupt flag status */
|
||||
#define GPIOB_ReadITFlagPort() (R32_INT_STATUS_PB) /* Read GPIOB port interrupt flag status */
|
||||
#define GPIOD_ReadITFlagPort() (R32_INT_STATUS_PD) /* Read GPIOD port interrupt flag status */
|
||||
|
||||
/*************************************Read Interrupt Bit Flag************************************/
|
||||
#define GPIOA_ReadITFLAGBit(pin) (R32_INT_STATUS_PA & pin)
|
||||
#define GPIOB_ReadITFLAGBit(pin) (R32_INT_STATUS_PB & pin)
|
||||
#define GPIOD_ReadITFLAGBit(pin) (R32_INT_STATUS_PD & pin)
|
||||
|
||||
/*************************************Clear Interrupt Bit Flag************************************/
|
||||
#define GPIOA_ClearITFlagbit(pin) (R32_INT_STATUS_PA |= pin)
|
||||
#define GPIOB_ClearITFlagbit(pin) (R32_INT_STATUS_PB |= pin)
|
||||
#define GPIOD_ClearITFlagbit(pin) (R32_INT_STATUS_PD |= pin)
|
||||
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewSTA);
|
||||
void GPIO_IPD_Unused(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
188
Peripheral/inc/ch564_i2c.h
Normal file
188
Peripheral/inc/ch564_i2c.h
Normal file
@@ -0,0 +1,188 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_i2c.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* I2C firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_I2C_H
|
||||
#define __CH564_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
/* I2C Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /* Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/* I2C_mode */
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_duty_cycle_in_fast_mode */
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
|
||||
|
||||
/* I2C_acknowledgement */
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_transfer_direction */
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
|
||||
/* I2C_acknowledged_address */
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
|
||||
/* I2C_registers */
|
||||
#define I2C_Register_CTLR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CTLR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OADDR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DATAR ((uint8_t)0x10)
|
||||
#define I2C_Register_STAR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_STAR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
|
||||
|
||||
/* I2C_PEC_position */
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_NACK_position */
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
/* STAR2 register flags */
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/* STAR1 register flags */
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
/****************I2C Master Events (Events grouped in order of communication)********************/
|
||||
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
/******************I2C Slave Events (Events grouped in order of communication)******************/
|
||||
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
void I2C_DeInit(I2C_Typedef *I2Cx);
|
||||
void I2C_Init(I2C_Typedef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMACmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_Typedef *I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_Typedef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_SendData(I2C_Typedef *I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_Typedef *I2Cx);
|
||||
void I2C_Send7bitAddress(I2C_Typedef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_ReadRegister(I2C_Typedef *I2Cx, uint8_t I2C_Register);
|
||||
void I2C_SoftwareResetCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_NACKPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_TransmitPEC(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_Typedef *I2Cx);
|
||||
void I2C_ARPCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_Typedef *I2Cx, uint16_t I2C_DutyCycle);
|
||||
|
||||
/****************************************************************************************
|
||||
* I2C State Monitoring Functions
|
||||
****************************************************************************************/
|
||||
|
||||
ErrorStatus I2C_CheckEvent(I2C_Typedef *I2Cx, uint32_t I2C_EVENT);
|
||||
uint32_t I2C_GetLastEvent(I2C_Typedef *I2Cx);
|
||||
FlagStatus I2C_GetFlagStatus(I2C_Typedef *I2Cx, uint32_t I2C_FLAG);
|
||||
|
||||
void I2C_ClearFlag(I2C_Typedef *I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_Typedef *I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_Typedef *I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
67
Peripheral/inc/ch564_pwr.h
Normal file
67
Peripheral/inc/ch564_pwr.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_pwr.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* PWR firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_PWR_H
|
||||
#define __CH564_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
/* STOP_mode_entry */
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
|
||||
#define WDOG_ENABLE() \
|
||||
{ \
|
||||
R8_SAFE_ACCESS_SIG = 0x57; \
|
||||
R8_SAFE_ACCESS_SIG = 0xA8; \
|
||||
R8_GLOB_RST_CFG |= (0x40 | RB_GLOB_WDOG_EN); \
|
||||
R8_SAFE_ACCESS_SIG = 0x00; \
|
||||
}
|
||||
#define WDOG_DISABLE() \
|
||||
{ \
|
||||
R8_SAFE_ACCESS_SIG = 0x57; \
|
||||
R8_SAFE_ACCESS_SIG = 0xA8; \
|
||||
R8_GLOB_RST_CFG = 0x40; \
|
||||
R8_SAFE_ACCESS_SIG = 0x00; \
|
||||
}
|
||||
#define FEED_DOG() (R8_WDOG_CLEAR = 0)
|
||||
#define VIO_PWN_INT_CMD(cmd) \
|
||||
{ \
|
||||
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_INT_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_INT_EN); \
|
||||
}
|
||||
#define VIO_PWN_RST_CMD(cmd) \
|
||||
{ \
|
||||
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_RST_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_RST_EN); \
|
||||
}
|
||||
#define VIO_PWN_IO_CMD(cmd) \
|
||||
{ \
|
||||
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_IO_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_IO_EN); \
|
||||
}
|
||||
#define LDO_DORMENCY_EN(cmd) \
|
||||
{ \
|
||||
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_LDO_SLP_EN) : (R32_EXTEN_CTLR1 &= ~RB_LDO_SLP_EN); \
|
||||
}
|
||||
|
||||
|
||||
|
||||
void PWR_Sleep(uint8_t PWR_STOPEntry);
|
||||
void PWR_DeepSleep(uint8_t PWR_STOPEntry);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
133
Peripheral/inc/ch564_rcc.h
Normal file
133
Peripheral/inc/ch564_rcc.h
Normal file
@@ -0,0 +1,133 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_rcc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* RCC firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_RCC_H
|
||||
#define __CH564_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
#define RCC_UNLOCK_SAFE_ACCESS() \
|
||||
({ \
|
||||
R8_SAFE_ACCESS_SIG = 0x57; \
|
||||
R8_SAFE_ACCESS_SIG = 0xA8; \
|
||||
__NOP(); \
|
||||
})
|
||||
|
||||
#define RCC_LOCK_SAFE_ACCESS() ({ R8_SAFE_ACCESS_SIG = 0x0; })
|
||||
#define RCC_GET_ID_SAFELY() (R8_SAFE_ACCESS_ID)
|
||||
#define RCC_CLEAR_WDOG() ({ R8_WDOG_CLEAR = 0; })
|
||||
|
||||
#define HSI_ON() (R32_EXTEN_CTLR1 |= RB_HSION)
|
||||
#define HSE_ON() (R32_EXTEN_CTLR1 |= RB_HSEON)
|
||||
#define HSE_GET_STTATEUS() ((R32_EXTEN_CTLR1 & 0x8000) != 0 ? 1 : 0)
|
||||
#define HSI_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSION)
|
||||
#define HSE_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSEON)
|
||||
#define USB_PLL_ON() \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 |= (RB_USBPLLON); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
#define USB_PLL_OFF() \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
#define USB_PLL_MUL_15 0x0000c000
|
||||
#define USB_PLL_MUL_16 0x00008000
|
||||
#define USB_PLL_MUL_20 0x00004000
|
||||
#define USB_PLL_MUL_24 0x00000000
|
||||
#define USB_PLL_MUL_SELECT(USB_PLL_MUL) \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 &= ~USB_PLL_MUL_15; \
|
||||
R32_EXTEN_CTLR0 |= (USB_PLL_MUL); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
#define USB_PLL_SOURCE_HSI 0x00000060
|
||||
#define USB_PLL_SOURCE_HSE 0x00000020
|
||||
#define USB_PLL_SOURCE_ETH_PLL_OUT 0x00000040
|
||||
#define USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE) \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 &= ~USB_PLL_SOURCE_HSI; \
|
||||
R32_EXTEN_CTLR0 |= (USB_PLL_SOURCE); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
|
||||
#define CLKSEL_HSI() \
|
||||
{ \
|
||||
R32_EXTEN_CTLR1 &= ~(RB_CLKSEL); \
|
||||
}
|
||||
#define CLKSEL_HSE() \
|
||||
{ \
|
||||
R32_EXTEN_CTLR1 |= (RB_CLKSEL); \
|
||||
}
|
||||
#define USB_PLL_ON() \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 |= (RB_USBPLLON); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
#define USB_PLL_OFF() \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
#define SYSCLK_SOURCE_USBPLL 0
|
||||
#define SYSCLK_SOURCE_HSI_HSE 1
|
||||
#define SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE) \
|
||||
{ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
((SYSCLK_SOURCE) == SYSCLK_SOURCE_HSI_HSE) ? (R32_EXTEN_CTLR0 |= (RB_SW)) : (R32_EXTEN_CTLR0 &= ~(RB_SW)); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
}
|
||||
|
||||
#define RCC_GET_GLOB_RST_KEEP() (R8_GLOB_RESET_KEEP)
|
||||
#define RCC_SET_GLOB_RST_KEEP(val) {R8_GLOB_RESET_KEEP = (val);}
|
||||
#define RCC_SET_PLL_SYS_OUT_DIV(val) \
|
||||
({ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
R8_PLL_OUT_DIV = 0x04 | ((val) << 4); \
|
||||
RCC_LOCK_SAFE_ACCESS(); \
|
||||
})
|
||||
#define RCC_FLASH_CLK_PRE_DIV(sta) \
|
||||
({ \
|
||||
RCC_UNLOCK_SAFE_ACCESS(); \
|
||||
((sta) == ENABLE) ? (R32_EXTEN_CTLR0 |= 0x00200000) : (R32_EXTEN_CTLR0 &= ~0x00200000) RCC_LOCK_SAFE_ACCESS(); \
|
||||
})
|
||||
|
||||
typedef enum
|
||||
{
|
||||
Code16k_Data128k = 0x0,
|
||||
Code48k_Data96k = 0x1,
|
||||
Code80k_Data64k = 0x2
|
||||
} GlobMem_Cfg;
|
||||
|
||||
void RCC_SetGlobalMemCFG(GlobMem_Cfg Cfg);
|
||||
void RCC_LockPort(uint8_t globport, FunctionalState NewSTA);
|
||||
void RCC_GlobleRstCFG(uint8_t cfg, FunctionalState NewSTA);
|
||||
void RCC_SlpClkOff(volatile uint8_t *reg, uint8_t slpclk, FunctionalState NewSTA);
|
||||
void RCC_SlpWakeCtrl(uint8_t slpwake, FunctionalState NewSTA);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
69
Peripheral/inc/ch564_slv.h
Normal file
69
Peripheral/inc/ch564_slv.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_slv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* SLV firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_SLV_H
|
||||
#define __CH564_SLV_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
slv_data,
|
||||
slv_cmd,
|
||||
slv_timeout
|
||||
} SLV_STA;
|
||||
|
||||
#define SLV_CFG(cfglist, en) (BITS_CFG(R8_SLV_CONFIG, cfglist, en))
|
||||
#define SLV_SEND_DATA(data) (R8_SLV_DOUT = (data))
|
||||
#define SLV_SEND_STA(status) (R8_SLV_STATUS = (status))
|
||||
#define SLV_GET_IF(RB_IF_SLV) (R8_INT_FLAG_SLV & (RB_IF_SLV))
|
||||
#define SLV_CLEAR_IF(RB_IF_SLV) (R8_INT_FLAG_SLV |= (RB_IF_SLV))
|
||||
#define SLV_GET_DATA() (R8_INT_SLV_DIN)
|
||||
#define SLV_DMA_CFG(cfglist, en) (BITS_CFG(R8_DMA_EN_SLV, cfglist, en))
|
||||
#define SLV_SET_MODE_CTRL(cfglist, en) (BITS_CFG(R8_DMA_MODE_CTRL_SLV, cfglist, en))
|
||||
#define SLV_SET_MODE_EN(cfglist, en) (BITS_CFG(R8_DMA_MODE_EN_SLV, cfglist, en))
|
||||
|
||||
#define SLV_DMA_GET_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV & (slv_dma_if))
|
||||
#define SLV_DMA_CLEAR_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV |= (slv_dma_if))
|
||||
#define SLV_DMA_START_ADDR_RD(address) (R32_RD_DMA_START_ADDR_SLV = (uint32_t)(address))
|
||||
|
||||
#define SLV_DMA_END_ADDR_RD(address) (R32_RD_DMA_END_ADDR_SLV = (uint32_t)(address))
|
||||
|
||||
#define SLV_DMA_START_ADDR_WR(address) (R32_WR_DMA_START_ADDR_SLV = (uint32_t)(address))
|
||||
|
||||
#define SLV_DMA_END_ADDR_WR(address) (R32_WR_DMA_END_ADDR_SLV = (uint32_t)(address))
|
||||
|
||||
#define SLV_DMA_GET_NOW_ADDR() (R32_DMA_END_NOW_SLV)
|
||||
|
||||
#define SLV_SET_DMA_CMD0(cmd) (R8_DMA_CMD0_SLV = (cmd))
|
||||
|
||||
#define SLV_SET_DMA_CMD1(cmd) (R8_DMA_CMD1_SLV = (cmd))
|
||||
#define SLV_SET_RST_CMD(cmd) (R8_SLV_RESET_CMD = (cmd))
|
||||
|
||||
#define SLV_GET_OTHER_DATA() (R8_OTHER_DATA)
|
||||
#define SLV_GET_DMA_DEC_LEN() (R16_DMA_DEC_LEN)
|
||||
#define SLV_GET_DMA_DEC_OFFSET() (R16_DMA_DEC_OFFSET)
|
||||
|
||||
SLV_STA SLV_Read(uint8_t *dataAddress, uint16_t dataSize, uint16_t timeout);
|
||||
ErrorStatus SLV_SendDATA(uint8_t *data, uint16_t datasize);
|
||||
ErrorStatus SLV_SendSTA(uint8_t *sta, uint16_t datasize);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
141
Peripheral/inc/ch564_spi.h
Normal file
141
Peripheral/inc/ch564_spi.h
Normal file
@@ -0,0 +1,141 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_spi.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* SPI firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_SPI_H
|
||||
#define __CH564_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
/**
|
||||
* @brief SPI0 interrupt bit define
|
||||
*/
|
||||
#define SPI0_IT_FST_BYTE RB_SPI_IE_FST_BYTE
|
||||
#define SPI0_IT_FIFO_OV RB_SPI_IE_FIFO_OV
|
||||
#define SPI0_IT_DMA_END RB_SPI_IE_DMA_END
|
||||
#define SPI0_IT_FIFO_HF RB_SPI_IE_FIFO_HF
|
||||
#define SPI0_IT_BYTE_END RB_SPI_IE_BYTE_END
|
||||
#define SPI0_IT_CNT_END RB_SPI_IE_CNT_END
|
||||
|
||||
#define SPI_MAX_DELAY 0xffff
|
||||
|
||||
/**
|
||||
* @brief Configuration data mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Mode0_HighBitINFront,
|
||||
Mode3_HighBitINFront,
|
||||
} ModeBitOrderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Configuration SPI slave mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Mode_DataStream = 0,
|
||||
Mose_FirstCmd,
|
||||
} Slave_ModeTypeDef;
|
||||
|
||||
/**************** SPI0 */
|
||||
void SPI0_MasterInit(uint32_t clockRate);
|
||||
void SPI0_DataMode(ModeBitOrderTypeDef mode);
|
||||
|
||||
void SPI0_MasterSendByte(uint8_t data);
|
||||
uint8_t SPI0_MasterRecvByte(void);
|
||||
|
||||
void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len);
|
||||
void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len);
|
||||
|
||||
void SPI0_DMATrans(uint8_t *pbuf, uint32_t len);
|
||||
void SPI0_DMARecv(uint8_t *pbuf, uint32_t len);
|
||||
void SPI0_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len);
|
||||
|
||||
void SPI0_SlaveInit();
|
||||
#define SetFirst0Data(data) (R8_SPI0_SLAVE_PRE = (data))
|
||||
void SPI0_SlaveSendByte(uint8_t data);
|
||||
uint8_t SPI0_SlaveRecvByte(void);
|
||||
|
||||
uint8_t SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
|
||||
uint8_t SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
|
||||
|
||||
// refer to SPI0 interrupt bit define
|
||||
#define SPI0_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI0_CTRL_MOD, cfglist, en)
|
||||
#define SPI0_ITCfg(cfglist, en) BITS_CFG(R8_SPI0_INTER_EN, cfglist, en)
|
||||
#define SPI0_SET_CLOCK_DIV(div) (R8_SPI0_CLOCK_DIV = (div))
|
||||
#define SPI0_GetITFlag(f) (R8_SPI0_INT_FLAG & (f))
|
||||
#define SPI0_ClearITFlag(f) (R8_SPI0_INT_FLAG = (f))
|
||||
#define SPI0_SET_RST(dat) (R8_SPI0_RESET_CMD = (dat))
|
||||
#define SPI0_GET_RST() (R8_SPI0_RESET_CMD)
|
||||
#define SPI0_GET_BUSY() (R8_SPI0_BUSY)
|
||||
#define SPI0_GET_BUFFER() (R8_SPI0_BUFFER)
|
||||
#define SPI0_SET_BUFFER(dat) (R8_SPI0_BUFFER = (dat))
|
||||
#define SPI0_CLEAR_FIFO() (R8_SPI0_CTRL_MOD |= RB_SPI_ALL_CLEAR);
|
||||
#define SPI0_GET_FIFO() (R8_SPI0_FIFO)
|
||||
#define SPI0_SET_FIFO(dat) (R8_SPI0_FIFO = (dat))
|
||||
#define SPI0_SET_FIFO_CNT(cnt) (R8_SPI0_FIFO_COUNT = (cnt))
|
||||
#define SPI0_GET_FIFO_CNT() (R8_SPI0_FIFO_COUNT)
|
||||
#define SPI0_SET_TOTAL_CNT(cnt) (R16_SPI0_TOTAL_CNT = (cnt) )
|
||||
#define SPI0_GET_TOTAL_CNT() (R16_SPI0_TOTAL_CNT)
|
||||
|
||||
#define SPI0_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI0_CTRL_DMA, cfglist, en)
|
||||
#define SPI0_SET_DMA_RANGE(start, end) \
|
||||
({ \
|
||||
R32_SPI0_DMA_BEG = (uint32_t)(start) & MASK_SPI0_DMA_ADDR; \
|
||||
R32_SPI0_DMA_END = (uint32_t)(end) & MASK_SPI0_DMA_ADDR; \
|
||||
})
|
||||
|
||||
/**************** SPI1 */
|
||||
void SPI1_MasterInit(uint32_t clockRate);
|
||||
void SPI1_DataMode(ModeBitOrderTypeDef mode);
|
||||
|
||||
void SPI1_MasterSendByte(uint8_t data);
|
||||
uint8_t SPI1_MasterRecvByte(void);
|
||||
|
||||
void SPI1_MasterTrans(uint8_t *pbuf, uint16_t len);
|
||||
void SPI1_MasterRecv(uint8_t *pbuf, uint16_t len);
|
||||
|
||||
void SPI1_SlaveInit();
|
||||
#define SetFirst1Data(data) (R8_SPI1_SLAVE_PRE = (data))
|
||||
void SPI1_SlaveSendByte(uint8_t data);
|
||||
uint8_t SPI1_SlaveRecvByte(void);
|
||||
|
||||
uint8_t SPI1_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
|
||||
uint8_t SPI1_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
|
||||
|
||||
// refer to SPI1 interrupt bit define
|
||||
#define SPI1_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI1_CTRL_MOD, cfglist, en)
|
||||
#define SPI1_ITCfg(cfglist, en) BITS_CFG(R8_SPI1_INTER_EN, cfglist, en)
|
||||
#define SPI1_SET_CLOCK_DIV(div) (R8_SPI1_CLOCK_DIV = (div))
|
||||
#define SPI1_GetITFlag(f) (R8_SPI1_INT_FLAG & (f))
|
||||
#define SPI1_ClearITFlag(f) (R8_SPI1_INT_FLAG = (f))
|
||||
#define SPI1_GET_BUFFER() (R8_SPI1_BUFFER)
|
||||
#define SPI1_SET_BUFFER(dat) (R8_SPI1_BUFFER = (dat))
|
||||
#define SPI1_CLEAR_FIFO() (R8_SPI1_CTRL_MOD |= RB_SPI_ALL_CLEAR);
|
||||
#define SPI1_GET_FIFO() (R8_SPI1_FIFO)
|
||||
#define SPI1_SET_FIFO(dat) (R8_SPI1_FIFO = (dat))
|
||||
#define SPI1_SET_FIFO_CNT(cnt) (R8_SPI1_FIFO_COUNT = (cnt))
|
||||
#define SPI1_GET_FIFO_CNT() (R8_SPI1_FIFO_COUNT)
|
||||
#define SPI1_SET_TOTAL_CNT(cnt) (R16_SPI1_TOTAL_CNT = (cnt))
|
||||
#define SPI1_GET_TOTAL_CNT() (R16_SPI1_TOTAL_CNT)
|
||||
|
||||
#define SPI1_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI1_CTRL_DMA, (cfglist), (en))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
231
Peripheral/inc/ch564_tim.h
Normal file
231
Peripheral/inc/ch564_tim.h
Normal file
@@ -0,0 +1,231 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_tim.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* TIM firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_TIM_H
|
||||
#define __CH564_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
/**
|
||||
* @brief Pulse Width Modulation Effective Output Words
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWM_Times_1 = 0, // PWM effective output repeats 1 times
|
||||
PWM_Times_4 = 1, // PWM effective output repeats 4 times
|
||||
PWM_Times_8 = 2, // PWM effective output repeats 8 times
|
||||
PWM_Times_16 = 3, // PWM effective output repeats 16 times
|
||||
} PWM_RepeatTsTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Input Capture Edge Mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAP_NULL = 0, // not capture
|
||||
Edge_To_Edge = 1, // between any edge
|
||||
FallEdge_To_FallEdge = 2, // falling edge to falling edge
|
||||
RiseEdge_To_RiseEdge = 3, // rising edge to rising edge
|
||||
} CapModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Input Capture Edge Mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
clock16 = 0,
|
||||
clock8
|
||||
} CapWidthTypedef;
|
||||
|
||||
/**
|
||||
* @brief Direct access memory loop mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Mode_Single = 0, // single mode
|
||||
Mode_LOOP = 1, // cycle mode
|
||||
Mode_Burst = 2,
|
||||
Mode_Burst_Loop = 3
|
||||
} DMAModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PWM output polarity
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
high_on_low = 0, // Default low level, high level is active
|
||||
low_on_high = 1, // Default high level, low level active
|
||||
} PWM_PolarTypeDef;
|
||||
|
||||
/****************** TMR0 */
|
||||
// Timing and counting
|
||||
void TMR0_TimerInit(uint32_t arr); /* Timing function initialization */
|
||||
#define TMR0_DeInit() (R8_TMR0_CTRL_MOD = 0)
|
||||
#define TMR0_GetCurrentCount() R32_TMR0_COUNT /* Get the current count value, 67108864 */
|
||||
#define TMR0_ClrCurrentCount() {R8_TMR0_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR0_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
|
||||
#define TMR0_SET_CNT_END(cnt_end) ({R32_TMR0_CNT_END = (cnt_end);})
|
||||
|
||||
// Pulse Width Modulation Function
|
||||
#define TMR0_PWMCycleCfg(cyc) \
|
||||
(R32_TMR0_CNT_END = (cyc)) /* PWM0 channel output waveform period configuration, maximum 67108864 */
|
||||
void TMR0_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM0 output initialization */
|
||||
#define TMR0_PWMActDataWidth(d) (R32_TMR0_FIFO = (d)) /* PWM0 effective data pulse width, maximum 67108864 */
|
||||
|
||||
// Catch pulse width
|
||||
#define TMR0_CAPTimeoutCfg(cyc) \
|
||||
(R32_TMR0_CNT_END = (cyc)) /* CAP0 capture level timeout configuration, maximum 33554432 */
|
||||
void TMR0_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
|
||||
#define TMR0_CAPGetData() R32_TMR0_FIFO /* Get pulse data */
|
||||
#define TMR0_CAPDataCounter() R8_TMR0_FIFO_COUNT /* Get the number of currently captured data */
|
||||
void TMR0_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
|
||||
|
||||
#define TMR0_Disable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR0 */
|
||||
#define TMR0_Enable() (R8_TMR0_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR0 */
|
||||
// refer to TMR0 interrupt bit define
|
||||
#define TMR0_ITCfg(cfglist, en) \
|
||||
BITS_CFG(R8_TMR0_INTER_EN, (cfglist), (en)) /* TMR0 corresponding interrupt bit on and off */
|
||||
// refer to TMR0 interrupt bit define
|
||||
#define TMR0_ClearITFlag(f) (R8_TMR0_INT_FLAG = (f)) /* Clear interrupt flag */
|
||||
#define TMR0_GetITFlag(f) (R8_TMR0_INT_FLAG & (f)) /* Query interrupt flag status */
|
||||
|
||||
#define TMR0_DMA_SET_RANGE(start, end) \
|
||||
({ \
|
||||
R32_TMR0_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
|
||||
R32_TMR0_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
|
||||
})
|
||||
#define TMR0_DMA_GET_BEG() (R32_TMR0_DMA_BEG)
|
||||
#define TMR0_DMA_GET_END() (R32_TMR0_DMA_END)
|
||||
#define TMR0_DMA_GET_NOW() (R32_TMR0_DMA_NOW)
|
||||
|
||||
/****************** TMR1 */
|
||||
// Timing and counting
|
||||
void TMR1_TimerInit(uint32_t arr); /* Timing function initialization */
|
||||
#define TMR1_DeInit() (R8_TMR1_CTRL_MOD = 0)
|
||||
#define TMR1_GetCurrentCount() R32_TMR1_COUNT /* Get the current count value, 67108864 */
|
||||
#define TMR1_ClrCurrentCount() {R8_TMR1_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR1_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
|
||||
#define TMR1_SET_CNT_END(cnt_end) ({R32_TMR1_CNT_END = (cnt_end);})
|
||||
|
||||
// Pulse Width Modulation Function
|
||||
#define TMR1_PWMCycleCfg(cyc) \
|
||||
(R32_TMR1_CNT_END = (cyc)) /* PWM1 channel output waveform period configuration, maximum 67108864 */
|
||||
void TMR1_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM1 output initialization */
|
||||
#define TMR1_PWMActDataWidth(d) (R32_TMR1_FIFO = (d)) /* PWM1 effective data pulse width, maximum 67108864 */
|
||||
|
||||
// Catch pulse width
|
||||
#define TMR1_CAPTimeoutCfg(cyc) \
|
||||
(R32_TMR1_CNT_END = (cyc)) /* CAP1 capture level timeout configuration, maximum 33554432 */
|
||||
void TMR1_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
|
||||
#define TMR1_CAPGetData() R32_TMR1_FIFO /* Get pulse data */
|
||||
#define TMR1_CAPDataCounter() R8_TMR1_FIFO_COUNT /* Get the number of currently captured data */
|
||||
|
||||
void TMR1_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
|
||||
|
||||
#define TMR1_Disable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR1 */
|
||||
#define TMR1_Enable() (R8_TMR1_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR1 */
|
||||
// refer to TMR1 interrupt bit define
|
||||
#define TMR1_ITCfg(cfglist, en) \
|
||||
BITS_CFG(R8_TMR1_INTER_EN, (cfglist), (en)) /* TMR1 corresponding interrupt bit on and off */
|
||||
// refer to TMR1 interrupt bit define
|
||||
#define TMR1_ClearITFlag(f) (R8_TMR1_INT_FLAG = (f)) /* Clear interrupt flag */
|
||||
#define TMR1_GetITFlag(f) (R8_TMR1_INT_FLAG & (f)) /* Query interrupt flag status */
|
||||
|
||||
#define TMR1_DMA_SET_RANGE(start, end) \
|
||||
({ \
|
||||
R32_TMR1_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
|
||||
R32_TMR1_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
|
||||
})
|
||||
#define TMR1_DMA_GET_BEG() (R32_TMR1_DMA_BEG)
|
||||
#define TMR1_DMA_GET_END() (R32_TMR1_DMA_END)
|
||||
#define TMR1_DMA_GET_NOW() (R32_TMR1_DMA_NOW)
|
||||
/****************** TMR2 */
|
||||
// Timing and counting
|
||||
void TMR2_TimerInit(uint32_t arr); /* Timing function initialization */
|
||||
#define TMR2_DeInit() (R8_TMR2_CTRL_MOD = 0)
|
||||
#define TMR2_GetCurrentCount() R32_TMR2_COUNT /* Get the current count value, 67108864 */
|
||||
#define TMR2_ClrCurrentCount() {R8_TMR2_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR2_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
|
||||
#define TMR2_SET_CNT_END(cnt_end) ({R32_TMR2_CNT_END = (cnt_end);})
|
||||
|
||||
// Pulse Width Modulation Function
|
||||
#define TMR2_PWMCycleCfg(cyc) \
|
||||
(R32_TMR2_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */
|
||||
void TMR2_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */
|
||||
#define TMR2_PWMActDataWidth(d) (R32_TMR2_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */
|
||||
|
||||
// Catch pulse width
|
||||
#define TMR2_CAPTimeoutCfg(cyc) \
|
||||
(R32_TMR2_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */
|
||||
void TMR2_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
|
||||
#define TMR2_CAPGetData() R32_TMR2_FIFO /* Get pulse data */
|
||||
#define TMR2_CAPDataCounter() R8_TMR2_FIFO_COUNT /* Get the number of currently captured data */
|
||||
|
||||
void TMR2_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
|
||||
|
||||
#define TMR2_Disable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR2 */
|
||||
#define TMR2_Enable() (R8_TMR2_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR2 */
|
||||
// refer to TMR2 interrupt bit define
|
||||
#define TMR2_ITCfg(cfglist, en) \
|
||||
BITS_CFG(R8_TMR2_INTER_EN, (cfglist), (en)) /* TMR2 corresponding interrupt bit on and off */
|
||||
// refer to TMR2 interrupt bit define
|
||||
#define TMR2_ClearITFlag(f) (R8_TMR2_INT_FLAG = (f)) /* Clear interrupt flag */
|
||||
#define TMR2_GetITFlag(f) (R8_TMR2_INT_FLAG & (f)) /* Query interrupt flag status */
|
||||
|
||||
#define TMR2_DMA_SET_RANGE(start, end) \
|
||||
({ \
|
||||
R32_TMR2_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
|
||||
R32_TMR2_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
|
||||
})
|
||||
#define TMR2_DMA_GET_BEG() (R32_TMR2_DMA_BEG)
|
||||
#define TMR2_DMA_GET_END() (R32_TMR2_DMA_END)
|
||||
#define TMR2_DMA_GET_NOW() (R32_TMR2_DMA_NOW)
|
||||
/****************** TMR3 */
|
||||
// Timing and counting
|
||||
void TMR3_TimerInit(uint32_t arr); /* Timing function initialization */
|
||||
#define TMR3_DeInit() (R8_TMR3_CTRL_MOD = 0)
|
||||
void TMR3_EXTSignalCounterInit(uint32_t arr, CapModeTypeDef capedge,
|
||||
CapWidthTypedef capwidth); /* External signal counting function initialization */
|
||||
#define TMR3_GetCurrentCount() R32_TMR3_COUNT /* Get the current count value, 67108864 */
|
||||
#define TMR3_ClrCurrentCount() {R8_TMR3_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR3_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
|
||||
|
||||
#define TMR3_SET_CNT_END(cnt_end) ({R32_TMR3_CNT_END = (cnt_end);})
|
||||
|
||||
// Pulse Width Modulation Function
|
||||
#define TMR3_PWMCycleCfg(cyc) \
|
||||
(R32_TMR3_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */
|
||||
void TMR3_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */
|
||||
#define TMR3_PWMActDataWidth(d) (R32_TMR3_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */
|
||||
|
||||
// Catch pulse width
|
||||
#define TMR3_CAPTimeoutCfg(cyc) \
|
||||
(R32_TMR3_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */
|
||||
void TMR3_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
|
||||
#define TMR3_CAPGetData() R32_TMR3_FIFO /* Get pulse data */
|
||||
#define TMR3_CAPDataCounter() R8_TMR3_FIFO_COUNT /* Get the number of currently captured data */
|
||||
|
||||
#define TMR3_Disable() (R8_TMR3_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR3 */
|
||||
#define TMR3_Enable() (R8_TMR3_CTRL_MOD |= RB_TMR_COUNT_EN) /* Close TMR3 */
|
||||
// refer to TMR3 interrupt bit define
|
||||
#define TMR3_ITCfg(cfglist, en) \
|
||||
BITS_CFG(R8_TMR3_INTER_EN, (cfglist), (en)) /* TMR3 corresponding interrupt bit on and off */
|
||||
// refer to TMR3 interrupt bit define
|
||||
#define TMR3_ClearITFlag(f) (R8_TMR3_INT_FLAG = (f)) /* Clear interrupt flag */
|
||||
#define TMR3_GetITFlag(f) (R8_TMR3_INT_FLAG & (f)) /* Query interrupt flag status */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
259
Peripheral/inc/ch564_uart.h
Normal file
259
Peripheral/inc/ch564_uart.h
Normal file
@@ -0,0 +1,259 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_uart.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* UART firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_UART_H
|
||||
#define __CH564_UART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
/**
|
||||
* @brief Line Error Status Definition
|
||||
*/
|
||||
#define STA_ERR_BREAK RB_LSR_BREAK_ERR // Data Interval Error
|
||||
#define STA_ERR_FRAME RB_LSR_FRAME_ERR // DataFrame error
|
||||
#define STA_ERR_PAR RB_LSR_PAR_ERR // Parity bit error
|
||||
#define STA_ERR_FIFOOV RB_LSR_OVER_ERR // Receive Data Overflow
|
||||
|
||||
#define STA_TXFIFO_EMP RB_LSR_TX_FIFO_EMP // The current send FIFO is empty, you can continue to fill the send data
|
||||
#define STA_TXALL_EMP RB_LSR_TX_ALL_EMP // All currently sent data has been sent
|
||||
#define STA_RECV_DATA RB_LSR_DATA_RDY // Data is currently received
|
||||
|
||||
/**
|
||||
* @brief Serial port byte trigger configuration
|
||||
*/
|
||||
typedef enum {
|
||||
UART_1BYTE_TRIG = 0, // 1 byte trigger
|
||||
UART_2BYTE_TRIG = 1, // 2 byte trigger
|
||||
UART_4BYTE_TRIG = 2, // 4 byte trigger
|
||||
UART_7BYTE_TRIG = 3, // 7 byte trigger
|
||||
|
||||
} UARTByteTRIGTypeDef;
|
||||
|
||||
/****************** UART0 */
|
||||
void UART0_DefInit (void); /* Serial port default initialization configuration */
|
||||
void UART0_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
|
||||
void UART0_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
|
||||
void UART0_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
|
||||
void UART0_Reset (void); /* Serial port software reset */
|
||||
|
||||
#define UART0_SET_DLV(dlv) ({ R8_UART0_DIV = (dlv); })
|
||||
|
||||
#define UART0_CLR_RXFIFO() (R8_UART0_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
|
||||
#define UART0_CLR_TXFIFO() (R8_UART0_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
|
||||
|
||||
#define UART0_GetITFlag() (R8_UART0_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
|
||||
|
||||
#define UART0_SET_FCR(cfglist, en) BITS_CFG (R8_UART0_FCR, (cfglist), (en))
|
||||
#define UART0_SET_LCR(cfglist, en) BITS_CFG (R8_UART0_LCR, (cfglist), (en))
|
||||
#define UART0_SET_MCR(cfglist, en) BITS_CFG (R8_UART0_MCR, (cfglist), (en))
|
||||
|
||||
#define UART0_SET_RTS() UART0_SET_MCR(RB_MCR_RTS,ENABLE)
|
||||
#define UART0_SET_DTR() UART0_SET_MCR(RB_MCR_DTR,ENABLE)
|
||||
#define UART0_RESET_RTS() UART0_SET_MCR(RB_MCR_RTS,DISABLE)
|
||||
#define UART0_RESET_DTR() UART0_SET_MCR(RB_MCR_DTR,DISABLE)
|
||||
|
||||
// please refer to LINE error and status define
|
||||
#define UART0_GetLinSTA() (R8_UART0_LSR) /* Get the current communication status */
|
||||
#define UART0_GetMSRSTA() (R8_UART0_MSR) /* Get the current flow control status, only applicable to UART0 */
|
||||
|
||||
#define UART0_DMACFG(cfglist, en) BITS_CFG (R8_UART0_DMA_CTRL, (cfglist), (en))
|
||||
#define UART0_DMA_SET_RD_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART0_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART0_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART0_DMA_GET_RD_CURRENT_ADDR() (R32_UART0_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_GET_RD_BEG_ADDR() (R32_UART0_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_GET_RD_END_ADDR() (R32_UART0_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_SET_WR_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART0_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART0_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART0_DMA_GET_WR_CURRENT_ADDR() (R32_UART0_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_GET_WR_BEG_ADDR() (R32_UART0_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_GET_WR_END_ADDR() (R32_UART0_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART0_DMA_GET_IT_FLAG(dmaif) (R8_UART0_DMA_IF & (dmaif))
|
||||
|
||||
#define UART0_SendByte(b) (R8_UART0_THR = (b)) /* Serial port single byte transmission */
|
||||
void UART0_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
|
||||
void UART0_Send_DMA (uint8_t *buf, uint32_t lenth);
|
||||
void UART0_Recv_DMA (uint8_t *buf, uint32_t lenth);
|
||||
#define UART0_RecvByte() (R8_UART0_RBR) /* Serial port read single byte */
|
||||
uint16_t UART0_RecvString (uint8_t *buf); /* Serial port read multibyte */
|
||||
void UART0_DTRDSR_Cfg(FunctionalState en);
|
||||
void UART0_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
|
||||
|
||||
/****************** UART1 */
|
||||
void UART1_DefInit (void); /* Serial port default initialization configuration */
|
||||
void UART1_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
|
||||
void UART1_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
|
||||
void UART1_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
|
||||
void UART1_Reset (void); /* Serial port software reset */
|
||||
|
||||
#define UART1_SET_DLV(dlv) ({ R8_UART1_DIV = dlv; })
|
||||
|
||||
#define UART1_CLR_RXFIFO() (R8_UART1_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
|
||||
#define UART1_CLR_TXFIFO() (R8_UART1_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
|
||||
|
||||
#define UART1_GetITFlag() (R8_UART1_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
|
||||
|
||||
#define UART1_SET_FCR(cfglist, en) BITS_CFG (R8_UART1_FCR, (cfglist), (en))
|
||||
#define UART1_SET_LCR(cfglist, en) BITS_CFG (R8_UART1_LCR, (cfglist), (en))
|
||||
#define UART1_SET_MCR(cfglist, en) BITS_CFG (R8_UART1_MCR, (cfglist), (en))
|
||||
|
||||
#define UART1_SET_RTS() UART1_SET_MCR(RB_MCR_RTS,ENABLE)
|
||||
#define UART1_RESET_RTS() UART1_SET_MCR(RB_MCR_RTS,DISABLE)
|
||||
|
||||
// please refer to LINE error and status define
|
||||
#define UART1_GetLinSTA() (R8_UART1_LSR) /* Get the current communication status */
|
||||
#define UART1_GetMSRSTA() (R8_UART1_MSR) /* Get the current flow control status, only applicable to UART1 */
|
||||
|
||||
#define UART1_DMACFG(cfglist, en) BITS_CFG (R8_UART1_DMA_CTRL, (cfglist), (en))
|
||||
#define UART1_DMA_SET_RD_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART1_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART1_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART1_DMA_GET_RD_CURRENT_ADDR() (R32_UART1_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_GET_RD_BEG_ADDR() (R32_UART1_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_GET_RD_END_ADDR() (R32_UART1_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_SET_WR_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART1_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART1_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART1_DMA_GET_WR_CURRENT_ADDR() (R32_UART1_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_GET_WR_BEG_ADDR() (R32_UART1_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_GET_WR_END_ADDR() (R32_UART1_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART1_DMA_GET_IT_FLAG(dmaif) (R8_UART1_DMA_IF & (dmaif))
|
||||
|
||||
#define UART1_SendByte(b) (R8_UART1_THR = (b)) /* Serial port single byte transmission */
|
||||
void UART1_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
|
||||
void UART1_Send_DMA (uint8_t *buf, uint32_t lenth);
|
||||
void UART1_Recv_DMA (uint8_t *buf, uint32_t lenth);
|
||||
#define UART1_RecvByte() (R8_UART1_RBR) /* Serial port read single byte */
|
||||
uint16_t UART1_RecvString (uint8_t *buf); /* Serial port read multibyte */
|
||||
void UART1_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
|
||||
|
||||
/****************** UART2 */
|
||||
void UART2_DefInit (void); /* Serial port default initialization configuration */
|
||||
void UART2_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
|
||||
void UART2_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
|
||||
void UART2_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
|
||||
void UART2_Reset (void); /* Serial port software reset */
|
||||
|
||||
#define UART2_SET_DLV(dlv) ({ R8_UART2_DIV = (dlv); })
|
||||
|
||||
#define UART2_CLR_RXFIFO() (R8_UART2_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
|
||||
#define UART2_CLR_TXFIFO() (R8_UART2_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
|
||||
|
||||
#define UART2_GetITFlag() (R8_UART2_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
|
||||
|
||||
#define UART2_SET_FCR(cfglist, en) BITS_CFG (R8_UART2_FCR, (cfglist), (en))
|
||||
#define UART2_SET_LCR(cfglist, en) BITS_CFG (R8_UART2_LCR, (cfglist), (en))
|
||||
#define UART2_SET_MCR(cfglist, en) BITS_CFG (R8_UART2_MCR, (cfglist), (en))
|
||||
|
||||
#define UART2_SET_RTS() UART2_SET_MCR(RB_MCR_RTS,ENABLE)
|
||||
#define UART2_RESET_RTS() UART2_SET_MCR(RB_MCR_RTS,DISABLE)
|
||||
|
||||
// please refer to LINE error and status define
|
||||
#define UART2_GetLinSTA() (R8_UART2_LSR) /* Get the current communication status */
|
||||
#define UART2_GetMSRSTA() (R8_UART2_MSR) /* Get the current flow control status, only applicable to UART2 */
|
||||
|
||||
#define UART2_DMACFG(cfglist, en) BITS_CFG (R8_UART2_DMA_CTRL, (cfglist), (en))
|
||||
#define UART2_DMA_SET_RD_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART2_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART2_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART2_DMA_GET_RD_CURRENT_ADDR() (R32_UART2_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_GET_RD_BEG_ADDR() (R32_UART2_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_GET_RD_END_ADDR() (R32_UART2_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_SET_WR_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART2_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART2_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART2_DMA_GET_WR_CURRENT_ADDR() (R32_UART2_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_GET_WR_BEG_ADDR() (R32_UART2_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_GET_WR_END_ADDR() (R32_UART2_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART2_DMA_GET_IT_FLAG(dmaif) (R8_UART2_DMA_IF & (dmaif))
|
||||
|
||||
#define UART2_SendByte(b) (R8_UART2_THR = (b)) /* Serial port single byte transmission */
|
||||
void UART2_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
|
||||
void UART2_Send_DMA (uint8_t *buf, uint32_t lenth);
|
||||
void UART2_Recv_DMA (uint8_t *buf, uint32_t lenth);
|
||||
#define UART2_RecvByte() (R8_UART2_RBR) /* Serial port read single byte */
|
||||
uint16_t UART2_RecvString (uint8_t *buf); /* Serial port read multibyte */
|
||||
void UART2_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
|
||||
|
||||
/****************** UART3 */
|
||||
void UART3_DefInit (void); /* Serial port default initialization configuration */
|
||||
void UART3_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
|
||||
void UART3_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
|
||||
void UART3_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
|
||||
void UART3_Reset (void); /* Serial port software reset */
|
||||
|
||||
#define UART3_SET_DLV(dlv) ({ R8_UART3_DIV = dlv; })
|
||||
|
||||
#define UART3_CLR_RXFIFO() (R8_UART3_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
|
||||
#define UART3_CLR_TXFIFO() (R8_UART3_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
|
||||
|
||||
#define UART3_GetITFlag() (R8_UART3_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
|
||||
|
||||
#define UART3_SET_FCR(cfglist, en) BITS_CFG (R8_UART3_FCR, (cfglist), (en))
|
||||
#define UART3_SET_LCR(cfglist, en) BITS_CFG (R8_UART3_LCR, (cfglist), (en))
|
||||
#define UART3_SET_MCR(cfglist, en) BITS_CFG (R8_UART3_MCR, (cfglist), (en))
|
||||
|
||||
#define UART3_SET_RTS() UART3_SET_MCR(RB_MCR_RTS,ENABLE)
|
||||
#define UART3_RESET_RTS() UART3_SET_MCR(RB_MCR_RTS,DISABLE)
|
||||
|
||||
// please refer to LINE error and status define
|
||||
#define UART3_GetLinSTA() (R8_UART3_LSR) /* Get the current communication status */
|
||||
#define UART3_GetMSRSTA() (R8_UART3_MSR) /* Get the current flow control status, only applicable to UART3 */
|
||||
|
||||
#define UART3_DMACFG(cfglist, en) BITS_CFG (R8_UART3_DMA_CTRL, (cfglist), (en))
|
||||
#define UART3_DMA_SET_RD_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART3_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART3_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART3_DMA_GET_RD_CURRENT_ADDR() (R32_UART3_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_GET_RD_BEG_ADDR() (R32_UART3_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_GET_RD_END_ADDR() (R32_UART3_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_SET_WR_RANGE(start, end) \
|
||||
({ \
|
||||
R32_UART3_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
|
||||
R32_UART3_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
|
||||
})
|
||||
#define UART3_DMA_GET_WR_CURRENT_ADDR() (R32_UART3_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_GET_WR_BEG_ADDR() (R32_UART3_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_GET_WR_END_ADDR() (R32_UART3_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
|
||||
#define UART3_DMA_GET_IT_FLAG(dmaif) (R8_UART3_DMA_IF & (dmaif))
|
||||
|
||||
#define UART3_SendByte(b) (R8_UART3_THR = (b)) /* Serial port single byte transmission */
|
||||
void UART3_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
|
||||
void UART3_Send_DMA (uint8_t *buf, uint32_t lenth);
|
||||
void UART3_Recv_DMA (uint8_t *buf, uint32_t lenth);
|
||||
#define UART3_RecvByte() (R8_UART3_RBR) /* Serial port read single byte */
|
||||
uint16_t UART3_RecvString (uint8_t *buf); /* Serial port read multibyte */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
659
Peripheral/inc/ch564_usb.h
Normal file
659
Peripheral/inc/ch564_usb.h
Normal file
@@ -0,0 +1,659 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_usb.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* USB firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_USB_H
|
||||
#define __CH564_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
|
||||
/* USB standard device request code */
|
||||
#ifndef USB_GET_DESCRIPTOR
|
||||
#define USB_GET_STATUS 0x00
|
||||
#define USB_CLEAR_FEATURE 0x01
|
||||
#define USB_SET_FEATURE 0x03
|
||||
#define USB_SET_ADDRESS 0x05
|
||||
#define USB_GET_DESCRIPTOR 0x06
|
||||
#define USB_SET_DESCRIPTOR 0x07
|
||||
#define USB_GET_CONFIGURATION 0x08
|
||||
#define USB_SET_CONFIGURATION 0x09
|
||||
#define USB_GET_INTERFACE 0x0A
|
||||
#define USB_SET_INTERFACE 0x0B
|
||||
#define USB_SYNCH_FRAME 0x0C
|
||||
#endif
|
||||
|
||||
#define DEF_STRING_DESC_LANG 0x00
|
||||
#define DEF_STRING_DESC_MANU 0x01
|
||||
#define DEF_STRING_DESC_PROD 0x02
|
||||
#define DEF_STRING_DESC_SERN 0x03
|
||||
|
||||
/* USB hub class request code */
|
||||
#ifndef HUB_GET_DESCRIPTOR
|
||||
#define HUB_GET_STATUS 0x00
|
||||
#define HUB_CLEAR_FEATURE 0x01
|
||||
#define HUB_GET_STATE 0x02
|
||||
#define HUB_SET_FEATURE 0x03
|
||||
#define HUB_GET_DESCRIPTOR 0x06
|
||||
#define HUB_SET_DESCRIPTOR 0x07
|
||||
#endif
|
||||
|
||||
/* USB HID class request code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* USB CDC Class request code */
|
||||
#ifndef CDC_GET_LINE_CODING
|
||||
#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */
|
||||
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
|
||||
#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */
|
||||
#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */
|
||||
#endif
|
||||
|
||||
/* Bit Define for USB Request Type */
|
||||
#ifndef USB_REQ_TYP_MASK
|
||||
#define USB_REQ_TYP_IN 0x80
|
||||
#define USB_REQ_TYP_OUT 0x00
|
||||
#define USB_REQ_TYP_READ 0x80
|
||||
#define USB_REQ_TYP_WRITE 0x00
|
||||
#define USB_REQ_TYP_MASK 0x60
|
||||
#define USB_REQ_TYP_STANDARD 0x00
|
||||
#define USB_REQ_TYP_CLASS 0x20
|
||||
#define USB_REQ_TYP_VENDOR 0x40
|
||||
#define USB_REQ_TYP_RESERVED 0x60
|
||||
#define USB_REQ_RECIP_MASK 0x1F
|
||||
#define USB_REQ_RECIP_DEVICE 0x00
|
||||
#define USB_REQ_RECIP_INTERF 0x01
|
||||
#define USB_REQ_RECIP_ENDP 0x02
|
||||
#define USB_REQ_RECIP_OTHER 0x03
|
||||
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
|
||||
#define USB_REQ_FEAT_ENDP_HALT 0x00
|
||||
#endif
|
||||
|
||||
/* USB Descriptor Type */
|
||||
#ifndef USB_DESCR_TYP_DEVICE
|
||||
#define USB_DESCR_TYP_DEVICE 0x01
|
||||
#define USB_DESCR_TYP_CONFIG 0x02
|
||||
#define USB_DESCR_TYP_STRING 0x03
|
||||
#define USB_DESCR_TYP_INTERF 0x04
|
||||
#define USB_DESCR_TYP_ENDP 0x05
|
||||
#define USB_DESCR_TYP_QUALIF 0x06
|
||||
#define USB_DESCR_TYP_SPEED 0x07
|
||||
#define USB_DESCR_TYP_OTG 0x09
|
||||
#define USB_DESCR_TYP_BOS 0X0F
|
||||
#define USB_DESCR_TYP_HID 0x21
|
||||
#define USB_DESCR_TYP_REPORT 0x22
|
||||
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||
#define USB_DESCR_TYP_HUB 0x29
|
||||
#endif
|
||||
|
||||
/* USB Device Class */
|
||||
#ifndef USB_DEV_CLASS_HUB
|
||||
#define USB_DEV_CLASS_RESERVED 0x00
|
||||
#define USB_DEV_CLASS_AUDIO 0x01
|
||||
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||
#define USB_DEV_CLASS_HID 0x03
|
||||
#define USB_DEV_CLASS_MONITOR 0x04
|
||||
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||
#define USB_DEV_CLASS_POWER 0x06
|
||||
#define USB_DEV_CLASS_IMAGE 0x06
|
||||
#define USB_DEV_CLASS_PRINTER 0x07
|
||||
#define USB_DEV_CLASS_STORAGE 0x08
|
||||
#define USB_DEV_CLASS_HUB 0x09
|
||||
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||
#endif
|
||||
|
||||
/* USB Hub Class Request */
|
||||
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||
#define HUB_CLEAR_PORT_FEATURE 0x23
|
||||
#define HUB_GET_BUS_STATE 0xA3
|
||||
#define HUB_GET_HUB_DESCRIPTOR 0xA0
|
||||
#define HUB_GET_HUB_STATUS 0xA0
|
||||
#define HUB_GET_PORT_STATUS 0xA3
|
||||
#define HUB_SET_HUB_DESCRIPTOR 0x20
|
||||
#define HUB_SET_HUB_FEATURE 0x20
|
||||
#define HUB_SET_PORT_FEATURE 0x23
|
||||
#endif
|
||||
|
||||
/* Hub Class Feature Selectors */
|
||||
#ifndef HUB_PORT_RESET
|
||||
#define HUB_C_HUB_LOCAL_POWER 0
|
||||
#define HUB_C_HUB_OVER_CURRENT 1
|
||||
#define HUB_PORT_CONNECTION 0
|
||||
#define HUB_PORT_ENABLE 1
|
||||
#define HUB_PORT_SUSPEND 2
|
||||
#define HUB_PORT_OVER_CURRENT 3
|
||||
#define HUB_PORT_RESET 4
|
||||
#define HUB_PORT_POWER 8
|
||||
#define HUB_PORT_LOW_SPEED 9
|
||||
#define HUB_C_PORT_CONNECTION 16
|
||||
#define HUB_C_PORT_ENABLE 17
|
||||
#define HUB_C_PORT_SUSPEND 18
|
||||
#define HUB_C_PORT_OVER_CURRENT 19
|
||||
#define HUB_C_PORT_RESET 20
|
||||
#endif
|
||||
|
||||
/* USB UDisk */
|
||||
#ifndef USB_BO_CBW_SIZE
|
||||
#define USB_BO_CBW_SIZE 0x1F
|
||||
#define USB_BO_CSW_SIZE 0x0D
|
||||
#endif
|
||||
#ifndef USB_BO_CBW_SIG0
|
||||
#define USB_BO_CBW_SIG0 0x55
|
||||
#define USB_BO_CBW_SIG1 0x53
|
||||
#define USB_BO_CBW_SIG2 0x42
|
||||
#define USB_BO_CBW_SIG3 0x43
|
||||
#define USB_BO_CSW_SIG0 0x55
|
||||
#define USB_BO_CSW_SIG1 0x53
|
||||
#define USB_BO_CSW_SIG2 0x42
|
||||
#define USB_BO_CSW_SIG3 0x53
|
||||
#endif
|
||||
|
||||
/*******************************************************************************/
|
||||
/* USBHS Related Register Macro Definition */
|
||||
|
||||
/* USBHS Device Register Definition */
|
||||
/* Bit definition for USB_CTRL register */
|
||||
#define DEV_LPM_EN 0x80 /* LPM enable */
|
||||
#define DEV_EN 0x20 /* USB device enabled */
|
||||
#define DEV_DMA_EN 0x10 /* DMA transfer enabled */
|
||||
#define PHY_SUSPENDM 0x08 /* USB PHY suspend */
|
||||
#define USB_ALL_CLR 0x04 /* clear all interrupt flags */
|
||||
#define SIE_RESET 0x02 /* USB protocol processor reset */
|
||||
#define LINK_RESET 0x01
|
||||
|
||||
/* Bit definition for usb_BASE_MODE register */
|
||||
#define EXP_SPD_MASK 0x03 /* bit[0:1] controls the desired device speed */
|
||||
#define EXP_FS_SPD 0x00 /* Full-speed mode */
|
||||
#define EXP_HS_SPD 0x01 /* High-speed mode */
|
||||
#define EXP_LOW_SPD 0x02 /* Low-speed mode */
|
||||
|
||||
/* Bit definition for USB_INT_EN register */
|
||||
#define FIFO_OVER_IE 0x80 /* USB Overflow interrupt enable */
|
||||
#define LINK_RDY_IE 0x40 /* USB connection interrupt enable */
|
||||
#define RX_SOF_IE 0x20 /* Receive SOF packet interrupt enable */
|
||||
#define RTX_ACT_IE 0x10 /* USB transfer end interrupt enabled */
|
||||
#define LPM_ACT_IE 0x08 /* LMP transfer end interrupt enabled */
|
||||
#define BUS_SLEEP_IE 0x04 /* USB bus sleep interrupt enabled */
|
||||
#define BUS_SUSP_IE 0x02 /* USB bus pause interrupt enabled */
|
||||
#define BUS_REST_IE 0x01 /* USB bus reset interrupt enabled */
|
||||
|
||||
/* Bit definition for USB_DEV_AD register */
|
||||
#define MASK_USB_ADDR 0x7f
|
||||
|
||||
/* Bit definition for USB_WAKE_CR register */
|
||||
#define RB_RMT_WAKE 0x01 /* remote wake up */
|
||||
|
||||
/* Bit definition for USB_TEST_MODE register */
|
||||
#define RB_TEST_EN 0x80 /* test mode enable */
|
||||
#define RB_TEST_SE0NAK 0x08 /* test mode,output SEO */
|
||||
#define RB_TEST_PKT 0x04 /* test mode,output a packet */
|
||||
#define RB_TEST_K 0x02 /* test mode,output K */
|
||||
#define RB_TEST_J 0x01 /* test mode,output J */
|
||||
|
||||
/* Bit definition for USB_LPM_DATA register */
|
||||
#define LPM_BUSY 0x8000
|
||||
#define LPM_DATA 0x07ff /* read-only power management data */
|
||||
|
||||
/* Bit definition for USB_INT_FG register */
|
||||
#define FIFO_OVER_IF 0x80 /* read-write USB Overflow interrupt flag */
|
||||
#define LINK_RDY_IF 0x40 /* read-write USB connection interrupt flag */
|
||||
#define RX_SOF_IF 0x20 /* read-write Receive SOF packet interrupt flag */
|
||||
#define RTX_ACT_IF 0x10 /* read-only USB transmission end interrupt flag */
|
||||
#define LPM_ACT_IF 0x08 /* read-write LPM transmission end interrupt flag */
|
||||
#define BUS_SLEEP_IF 0x04 /* read-write USB bus sleep interrupt flag */
|
||||
#define BUS_SUSP_IF 0x02 /* read-write USB bus suspend interrupt flag */
|
||||
#define BUS_REST_IF 0x01 /* read-write USB bus reset interrupt flag */
|
||||
|
||||
/* Bit definition for USB_INT_ST register */
|
||||
#define RB_UIS_EP_DIR 0x10 /* Endpoint data transmission direction */
|
||||
#define RB_UIS_EP_ID_MASK 0x07 /* The endpoint number at which the data transfer occurs */
|
||||
|
||||
/* Bit definition for USB_MIS_ST register */
|
||||
#define RB_UMS_HS_MOD 0x80 /* whether the host is high-speed */
|
||||
#define RB_UMS_SUSP_REQ 0x10 /* USB suspends the request */
|
||||
#define RB_UMS_FREE 0x08 /* USB free status */
|
||||
#define RB_UMS_SLEEP 0x04 /* USB sleep status */
|
||||
#define RB_UMS_SUSPEND 0x02 /* USB suspend status */
|
||||
#define RB_UMS_READY 0x01 /* USB connection status */
|
||||
|
||||
/* Bit definition for USB_FRAMME_NO register */
|
||||
#define MICRO_FRAME 0xe000 /* Received micro frame number */
|
||||
#define FRAME_NO 0x07ff /* Received frame number */
|
||||
|
||||
/* Bit definition for USB_BUS register */
|
||||
#define USB_DM_ST 0x0008 /* read-only UDM status */
|
||||
#define USB_DP_ST 0x0004 /* read-only UDP status */
|
||||
#define USB_WAKEUP 0x0001 /* read-only USB wakeup */
|
||||
|
||||
/* Bit definition for DEV_UEP_TX_EN & DEV_UEP_RX_EN register */
|
||||
#define RB_EP0_EN 0x0001
|
||||
#define RB_EP1_EN 0x0002
|
||||
#define RB_EP2_EN 0x0004
|
||||
#define RB_EP3_EN 0x0008
|
||||
#define RB_EP4_EN 0x0010
|
||||
#define RB_EP5_EN 0x0020
|
||||
#define RB_EP6_EN 0x0040
|
||||
#define RB_EP7_EN 0x0080
|
||||
#define RB_EP8_EN 0x0100
|
||||
#define RB_EP9_EN 0x0200
|
||||
#define RB_EP10_EN 0x0400
|
||||
#define RB_EP11_EN 0x0800
|
||||
#define RB_EP12_EN 0x1000
|
||||
#define RB_EP13_EN 0x2000
|
||||
#define RB_EP14_EN 0x4000
|
||||
#define RB_EP15_EN 0x8000
|
||||
|
||||
/* Bit definition for DEV_UEP_T_TOG_AUTO register */
|
||||
#define EP0_T_TOG_AUTO 0x01
|
||||
#define EP1_T_TOG_AUTO 0x02
|
||||
#define EP2_T_TOG_AUTO 0x04
|
||||
#define EP3_T_TOG_AUTO 0x08
|
||||
#define EP4_T_TOG_AUTO 0x10
|
||||
#define EP5_T_TOG_AUTO 0x20
|
||||
#define EP6_T_TOG_AUTO 0x40
|
||||
#define EP7_T_TOG_AUTO 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_R_TOG_AUTO register */
|
||||
#define EP0_R_TOG_AUTO 0x01
|
||||
#define EP1_R_TOG_AUTO 0x02
|
||||
#define EP2_R_TOG_AUTO 0x04
|
||||
#define EP3_R_TOG_AUTO 0x08
|
||||
#define EP4_R_TOG_AUTO 0x10
|
||||
#define EP5_R_TOG_AUTO 0x20
|
||||
#define EP6_R_TOG_AUTO 0x40
|
||||
#define EP7_R_TOG_AUTO 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_T_BURST register */
|
||||
#define EP0_T_BURST_EN 0x01
|
||||
#define EP1_T_BURST_EN 0x02
|
||||
#define EP2_T_BURST_EN 0x04
|
||||
#define EP3_T_BURST_EN 0x08
|
||||
#define EP4_T_BURST_EN 0x10
|
||||
#define EP5_T_BURST_EN 0x20
|
||||
#define EP6_T_BURST_EN 0x40
|
||||
#define EP7_T_BURST_EN 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_T_BURST_MODE register */
|
||||
#define EP0_T_BURST_MODE 0x01
|
||||
#define EP1_T_BURST_MODE 0x02
|
||||
#define EP2_T_BURST_MODE 0x04
|
||||
#define EP3_T_BURST_MODE 0x08
|
||||
#define EP4_T_BURST_MODE 0x10
|
||||
#define EP5_T_BURST_MODE 0x20
|
||||
#define EP6_T_BURST_MODE 0x40
|
||||
#define EP7_T_BURST_MODE 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_R_BURST register */
|
||||
#define EP0_R_BURST_EN 0x01
|
||||
#define EP1_R_BURST_EN 0x02
|
||||
#define EP2_R_BURST_EN 0x04
|
||||
#define EP3_R_BURST_EN 0x08
|
||||
#define EP4_R_BURST_EN 0x10
|
||||
#define EP5_R_BURST_EN 0x20
|
||||
#define EP6_R_BURST_EN 0x40
|
||||
#define EP7_R_BURST_EN 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_R_RES_MODE register */
|
||||
#define EP0_R_RES_MODE 0x01
|
||||
#define EP1_R_RES_MODE 0x02
|
||||
#define EP2_R_RES_MODE 0x04
|
||||
#define EP3_R_RES_MODE 0x08
|
||||
#define EP4_R_RES_MODE 0x10
|
||||
#define EP5_R_RES_MODE 0x20
|
||||
#define EP6_R_RES_MODE 0x40
|
||||
#define EP7_R_RES_MODE 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_AF_MODE register */
|
||||
#define EP1_T_AF 0x02
|
||||
#define EP2_T_AF 0x04
|
||||
#define EP3_T_AF 0x08
|
||||
#define EP4_T_AF 0x10
|
||||
#define EP5_T_AF 0x20
|
||||
#define EP6_T_AF 0x40
|
||||
#define EP7_T_AF 0x80
|
||||
|
||||
/* Bit definition for UEPx_TX_CTRL register */
|
||||
#define USBHS_UEP_T_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */
|
||||
#define USBHS_UEP_T_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */
|
||||
#define USBHS_UEP_T_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */
|
||||
#define USBHS_UEP_T_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */
|
||||
#define USBHS_UEP_T_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */
|
||||
#define USBHS_UEP_T_TOG_MASK 0x0C /* Synchronization trigger bit mask */
|
||||
#define USBHS_UEP_T_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */
|
||||
#define USBHS_UEP_T_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */
|
||||
#define USBHS_UEP_T_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */
|
||||
#define USBHS_UEP_T_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */
|
||||
#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */
|
||||
|
||||
/* Bit definition for UEPx_RX_CTRL register */
|
||||
#define USBHS_UEP_R_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */
|
||||
#define USBHS_UEP_R_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */
|
||||
#define USBHS_UEP_R_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */
|
||||
#define USBHS_UEP_R_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */
|
||||
#define USBHS_UEP_R_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */
|
||||
#define USBHS_UEP_R_TOG_MASK 0x0C /* Synchronization trigger bit mask */
|
||||
#define USBHS_UEP_R_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */
|
||||
#define USBHS_UEP_R_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */
|
||||
#define USBHS_UEP_R_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */
|
||||
#define USBHS_UEP_R_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */
|
||||
#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */
|
||||
#define USBHS_UEP_ENDP_R_DONE 0x80 /* Writing 0 clears the interrupt */
|
||||
#define USBHS_RB_SETUP_IS 0x08 /* Indicates whether the reception of endpoint 0 is a Setup transaction */
|
||||
#define USBHS_ENDP_R_TOG_MATCH 0x10
|
||||
|
||||
/* Bit definition for DEV_UEP_T_ISO register */
|
||||
#define EP1_T_ISO 0x02
|
||||
#define EP2_T_ISO 0x04
|
||||
#define EP3_T_ISO 0x08
|
||||
#define EP4_T_ISO 0x10
|
||||
#define EP5_T_ISO 0x20
|
||||
#define EP6_T_ISO 0x40
|
||||
#define EP7_T_ISO 0x80
|
||||
|
||||
/* Bit definition for DEV_UEP_R_ISO register */
|
||||
#define EP1_R_ISO 0x02
|
||||
#define EP2_R_ISO 0x04
|
||||
#define EP3_R_ISO 0x08
|
||||
#define EP4_R_ISO 0x10
|
||||
#define EP5_R_ISO 0x20
|
||||
#define EP6_R_ISO 0x40
|
||||
#define EP7_R_ISO 0x80
|
||||
|
||||
/* USBHS Host Register Definition */
|
||||
/* Bit definition for UHOST_CTRL register */
|
||||
#define root_LPM_EN (1<<7)
|
||||
#define ROOT_FORCE_FS (1<<6)
|
||||
#define ROOT_SOF_EN (1<<5)
|
||||
#define ROOT_DMA_EN (1<<4)
|
||||
#define ROOT_PHY_SUSPENDM (1<<3)
|
||||
#define ROOT_ALL_CLR (1<<2)
|
||||
#define ROOT_SIE_RESET (1<<1)
|
||||
#define ROOT_LINK_RESET (1<<0)
|
||||
|
||||
/* Bit definition for UH_INT_EN register */
|
||||
#define FIFO_OV_IE (1<<7)
|
||||
#define TX_HALT_IE (1<<6)
|
||||
#define SOF_ACT_IE (1<<5)
|
||||
#define USB_ACT_IE (1<<4)
|
||||
#define RESUME_ACT_IE (1<<3)
|
||||
#define WKUP_ACT_IE (1<<2)
|
||||
|
||||
/* Bit definition for UH_CONTROL register */
|
||||
#define RX_NO_RES (1<<23)
|
||||
#define TX_NO_RES (1<<22)
|
||||
#define RX_NO_DATA (1<<21)
|
||||
#define TX_NO_DATA (1<<20)
|
||||
#define TX_LOW_SPD (1<<19)
|
||||
#define SPLIT_VALID (1<<18)
|
||||
#define LPM_VALID (1<<17)
|
||||
#define HOST_ACTION (1<<16)
|
||||
#define BUF_MODE (1<<10)
|
||||
#define TOG_MASK (3<<8)
|
||||
#define TOG_MDATA (3<<8)
|
||||
#define TOG_DATA2 (2<<8)
|
||||
#define TOG_DATA1 (1<<8)
|
||||
#define TOG_DATA0 (0<<8)
|
||||
|
||||
/* Bit definition for UH_INT_FLAG register */
|
||||
#define RB_FIFO_OV_IF (1<<7)
|
||||
#define RB_TX_HALT_IF (1<<6)
|
||||
#define RB_SOF_ACT_IF (1<<5)
|
||||
#define RB_USB_ACT_IF (1<<4)
|
||||
#define RB_RESUME_ACT_IF (1<<3)
|
||||
#define RB_WKUP_IF (1<<2)
|
||||
|
||||
/* Bit definition for UH_INT_ST register */
|
||||
#define PORT_RX_RESUME (1<<4)
|
||||
#define USB_PID_MASK 0x0f
|
||||
#define USB_PID_TOUT 0x0
|
||||
#define USB_PID_ACK 0x2
|
||||
#define USB_PID_NAK 0xa
|
||||
#define USB_PID_STALL 0xe
|
||||
#define USB_PID_NYET 0x6
|
||||
#define USB_PID_DATA0 0x3
|
||||
#define USB_PID_DATA1 0xb
|
||||
#define USB_PID_DATA2 0x7
|
||||
#define USB_PID_MDATA 0xf
|
||||
|
||||
#define USB_PID_PRE 0xc
|
||||
#define USB_PID_ERR 0xc
|
||||
#define USB_PID_SPLIT 0x8
|
||||
#define USB_PID_PING 0x4
|
||||
#define USB_PID_SOF 0x5
|
||||
#define USB_PID_SETUP 0xd
|
||||
#define USB_PID_IN 0x9
|
||||
#define USB_PID_OUT 0x1
|
||||
|
||||
/* Bit definition for UH_MIS_ST register */
|
||||
#define RB_BUS_SE0 (1<<7)
|
||||
#define RB_BUS_J (1<<6)
|
||||
#define RB_LINESTATE_MASK (0x3<<4)
|
||||
#define RB_USB_WAKEUP (1<<3)
|
||||
#define RB_SOF_ST (1<<2)
|
||||
#define RB_SOF_PRE (1<<1)
|
||||
#define RB_SOF_FREE (1<<0)
|
||||
|
||||
/* Bit definition for UH_FRAME register */
|
||||
#define SOF_CNT_CLR (1<<25)
|
||||
#define SOF_CNT_EN (1<<24)
|
||||
|
||||
/* Bit definition for PORT_CTRL register */
|
||||
#define BUS_RST_LONG (1<<16)
|
||||
#define PORT_SLEEP_BESL (0xf<<12)
|
||||
#define CLR_PORT_SLEEP (1<<8)
|
||||
#define CLR_PORT_CONNECT (1<<5)
|
||||
#define CLR_PORT_EN (1<<4)
|
||||
#define SET_PORT_SLEEP (1<<3)
|
||||
#define CLR_PORT_SUSP (1<<2)
|
||||
#define SET_PORT_SUSP (1<<1)
|
||||
#define SET_PORT_RESET (1<<0)
|
||||
|
||||
/* Bit definition for PORT_CFG register */
|
||||
#define PORT_15K_RPD (1<<7)
|
||||
#define PORT_HOST_MODE (1<<0)//1: HOST function
|
||||
#define PORT_DEVICE_MODE (0<<0)//0: DEVICE function
|
||||
|
||||
/* Bit definition for PORT_INT_EN register */
|
||||
#define PORT_SLP_IE (1<<5)
|
||||
#define PORT_RESET_IE (1<<4)
|
||||
#define PORT_SUSP_IE (1<<2)
|
||||
#define PORT_EN_IE (1<<1)
|
||||
#define PORT_CONNECT_IE (1<<0)
|
||||
|
||||
/* Bit definition for PORT_TEST_CT register */
|
||||
#define TEST_FORCE_EN (1<<2)
|
||||
#define TEST_K (1<<1)
|
||||
#define TEST_J (1<<0)
|
||||
|
||||
/* Bit definition for PORT_STATUS register */
|
||||
#define PORT_TEST (1<<11)
|
||||
#define PORT_SPD_MASK (3<<9)
|
||||
#define PORT_HIGH_SPD (1<<10)
|
||||
#define PORT_LOW_SPD (1<<9)
|
||||
#define PORT_FULL_SPD (0<<9)
|
||||
#define PORT_SLP (1<<5)
|
||||
#define PORT_RESETTING (1<<4)
|
||||
#define PORT_OVC (1<<3)
|
||||
#define PORT_SUSP (1<<2)
|
||||
#define PORT_EN (1<<1)
|
||||
#define PORT_CONNECT (1<<0)
|
||||
|
||||
/* Bit definition for PORT_STATUS_CHG register */
|
||||
#define PORT_SLP_IF (1<<5)
|
||||
#define PORT_RESET_IF (1<<4)
|
||||
#define PORT_SUSP_IF (1<<2)
|
||||
#define PORT_EN_IF (1<<1)
|
||||
#define PORT_CONNECT_IF (1<<0)
|
||||
|
||||
/* Bit definition for ROOT_BC_CR register */
|
||||
#define UDM_VSRC_ACT (1<<10)
|
||||
#define UDM_BC_CMPE (1<<9)
|
||||
#define UDP_BC_CMPE (1<<8)
|
||||
#define BC_AUTO_MODE (1<<6)
|
||||
#define UDM_BC_VSRC (1<<5)
|
||||
#define UDP_BC_VSRC (1<<4)
|
||||
#define UDM_BC_CMPO (1<<1)
|
||||
#define UDP_BC_CMPO (1<<0)
|
||||
|
||||
/* Bit definition for HSI_CAL_CR register */
|
||||
#define CLK_SEL (1<<21)
|
||||
#define SOF_FREE (1<<3)
|
||||
#define SFT_RST (1<<2)
|
||||
#define CAL_EN (1<<1)
|
||||
#define CAL_RST (1<<0)
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Struct Definition */
|
||||
|
||||
/* USB Setup Request */
|
||||
typedef struct __attribute__((packed)) _USB_SETUP_REQ
|
||||
{
|
||||
uint8_t bRequestType;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||
|
||||
/* USB Device Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdUSB;
|
||||
uint8_t bDeviceClass;
|
||||
uint8_t bDeviceSubClass;
|
||||
uint8_t bDeviceProtocol;
|
||||
uint8_t bMaxPacketSize0;
|
||||
uint16_t idVendor;
|
||||
uint16_t idProduct;
|
||||
uint16_t bcdDevice;
|
||||
uint8_t iManufacturer;
|
||||
uint8_t iProduct;
|
||||
uint8_t iSerialNumber;
|
||||
uint8_t bNumConfigurations;
|
||||
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wTotalLength;
|
||||
uint8_t bNumInterfaces;
|
||||
uint8_t bConfigurationValue;
|
||||
uint8_t iConfiguration;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t MaxPower;
|
||||
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||
|
||||
/* USB Interface Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bInterfaceNumber;
|
||||
uint8_t bAlternateSetting;
|
||||
uint8_t bNumEndpoints;
|
||||
uint8_t bInterfaceClass;
|
||||
uint8_t bInterfaceSubClass;
|
||||
uint8_t bInterfaceProtocol;
|
||||
uint8_t iInterface;
|
||||
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||
|
||||
/* USB Endpoint Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t wMaxPacketSizeL;
|
||||
uint8_t wMaxPacketSizeH;
|
||||
uint8_t bInterval;
|
||||
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor Set */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
|
||||
{
|
||||
USB_CFG_DESCR cfg_descr;
|
||||
USB_ITF_DESCR itf_descr;
|
||||
USB_ENDP_DESCR endp_descr[ 1 ];
|
||||
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||
|
||||
/* USB HUB Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HUB_DESCR
|
||||
{
|
||||
uint8_t bDescLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bNbrPorts;
|
||||
uint8_t wHubCharacteristicsL;
|
||||
uint8_t wHubCharacteristicsH;
|
||||
uint8_t bPwrOn2PwrGood;
|
||||
uint8_t bHubContrCurrent;
|
||||
uint8_t DeviceRemovable;
|
||||
uint8_t PortPwrCtrlMask;
|
||||
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||
|
||||
/* USB HID Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HID_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdHID;
|
||||
uint8_t bCountryCode;
|
||||
uint8_t bNumDescriptors;
|
||||
uint8_t bDescriptorTypeX;
|
||||
uint8_t wDescriptorLengthL;
|
||||
uint8_t wDescriptorLengthH;
|
||||
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCBW_DataLen;
|
||||
uint8_t mCBW_Flag;
|
||||
uint8_t mCBW_LUN;
|
||||
uint8_t mCBW_CB_Len;
|
||||
uint8_t mCBW_CB_Buf[ 16 ];
|
||||
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCSW_Residue;
|
||||
uint8_t mCSW_Status;
|
||||
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
321
Peripheral/inc/ch564_usbpd.h
Normal file
321
Peripheral/inc/ch564_usbpd.h
Normal file
@@ -0,0 +1,321 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_usbpd.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* USBPD firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_USBPD_H
|
||||
#define __CH564_USBPD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
/* Register Bit Definition */
|
||||
/* USBPD->CONFIG */
|
||||
#define PD_FILT_ED (1<<0) /* PD pin input filter enable */
|
||||
#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */
|
||||
#define CC_SEL (1<<2) /* Select PD communication port */
|
||||
#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */
|
||||
#define PD_RST_EN (1<<4) /* PD mode reset command enable */
|
||||
#define WAKE_POLAR (1<<5) /* PD port wake-up level */
|
||||
#define IE_PD_IO (1<<10) /* PD IO interrupt enable */
|
||||
#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */
|
||||
#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */
|
||||
#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */
|
||||
#define IE_RX_RESET (1<<14) /* Reset interrupt enable */
|
||||
#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */
|
||||
|
||||
/* USBPD->CONTROL */
|
||||
#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */
|
||||
#define BMC_START (1<<1) /* BMC send start signal */
|
||||
#define RX_STATE_0 (1<<2) /* PD received state bit 0 */
|
||||
#define RX_STATE_1 (1<<3) /* PD received state bit 1 */
|
||||
#define RX_STATE_2 (1<<4) /* PD received state bit 2 */
|
||||
#define DATA_FLAG (1<<5) /* Cache data valid flag bit */
|
||||
#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */
|
||||
#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */
|
||||
|
||||
/* USBPD->TX_SEL */
|
||||
#define TX_SEL1 (0<<0)
|
||||
#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */
|
||||
#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */
|
||||
#define TX_SEL2_Mask (3<<2)
|
||||
#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */
|
||||
#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */
|
||||
#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */
|
||||
#define TX_SEL3_Mask (3<<4)
|
||||
#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */
|
||||
#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */
|
||||
#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */
|
||||
#define TX_SEL4_Mask (3<<6)
|
||||
#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */
|
||||
#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */
|
||||
#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */
|
||||
|
||||
/* USBPD->STATUS */
|
||||
#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */
|
||||
#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */
|
||||
#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */
|
||||
#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */
|
||||
#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */
|
||||
#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */
|
||||
#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */
|
||||
#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */
|
||||
#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */
|
||||
#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */
|
||||
#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */
|
||||
|
||||
/* USBPD->PORT_CC1 */
|
||||
/* USBPD->PORT_CC2 */
|
||||
#define PA_CC_AI (1<<0) /* CC port comparator analogue input */
|
||||
#define CC_PD (1<<1) /* CC port pull-down resistor enable */
|
||||
#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */
|
||||
#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */
|
||||
#define CC_PU_330 (1<<2) /* 01-330uA */
|
||||
#define CC_PU_180 (2<<2) /* 10-180uA */
|
||||
#define CC_PU_80 (3<<2) /* 11-80uA */
|
||||
#define CC_LVE (1<<4) /* CC port output low voltage enable */
|
||||
#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/
|
||||
#define CC_NO_CMP (0<<5) /* 000-closed */
|
||||
#define CC_CMP_22 (2<<5) /* 010-0.22V */
|
||||
#define CC_CMP_45 (3<<5) /* 011-0.45V */
|
||||
#define CC_CMP_55 (4<<5) /* 100-0.55V */
|
||||
#define CC_CMP_66 (5<<5) /* 101-0.66V */
|
||||
#define CC_CMP_95 (6<<5) /* 110-0.95V */
|
||||
#define CC_CMP_123 (7<<5) /* 111-1.23V */
|
||||
|
||||
/*********************************************************
|
||||
* PD pin PC14/PC15 high threshold input mode:
|
||||
* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication
|
||||
* 0-Normal GPIO threshold input
|
||||
* *******************************************************/
|
||||
#define USBPD_PHY_V33 (1<<8)
|
||||
/**********************************************************
|
||||
* PD transceiver PHY pull-up limit configuration bits:
|
||||
* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V
|
||||
* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V
|
||||
* ********************************************************/
|
||||
|
||||
/* Control Message Types */
|
||||
#define DEF_TYPE_RESERVED 0x00
|
||||
#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */
|
||||
#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_PING 0x05 /* Send By: Source */
|
||||
#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */
|
||||
#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */
|
||||
#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */
|
||||
#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */
|
||||
#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */
|
||||
#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */
|
||||
|
||||
/* Data Message Types */
|
||||
#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */
|
||||
#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */
|
||||
#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */
|
||||
#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */
|
||||
#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */
|
||||
#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */
|
||||
#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */
|
||||
#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */
|
||||
|
||||
/* Vendor Define Message Command */
|
||||
#define DEF_VDM_DISC_IDENT 0x01
|
||||
#define DEF_VDM_DISC_SVID 0x02
|
||||
#define DEF_VDM_DISC_MODE 0x03
|
||||
#define DEF_VDM_ENTER_MODE 0x04
|
||||
#define DEF_VDM_EXIT_MODE 0x05
|
||||
#define DEF_VDM_ATTENTION 0x06
|
||||
#define DEF_VDM_DP_S_UPDATE 0x10
|
||||
#define DEF_VDM_DP_CONFIG 0x11
|
||||
|
||||
/* PD Revision */
|
||||
#define DEF_PD_REVISION_10 0x00
|
||||
#define DEF_PD_REVISION_20 0x01
|
||||
#define DEF_PD_REVISION_30 0x02
|
||||
|
||||
|
||||
/* PD PHY Channel */
|
||||
#define DEF_PD_CC1 0x00
|
||||
#define DEF_PD_CC2 0x01
|
||||
|
||||
#define PIN_CC1 GPIO_Pin_18
|
||||
#define PIN_CC2 GPIO_Pin_19
|
||||
|
||||
/* PD Tx Status */
|
||||
#define DEF_PD_TX_OK 0x00
|
||||
#define DEF_PD_TX_FAIL 0x01
|
||||
|
||||
/* PDO INDEX */
|
||||
#define PDO_INDEX_1 1
|
||||
#define PDO_INDEX_2 2
|
||||
#define PDO_INDEX_3 3
|
||||
#define PDO_INDEX_4 4
|
||||
#define PDO_INDEX_5 5
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */
|
||||
#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */
|
||||
#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */
|
||||
#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */
|
||||
#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */
|
||||
#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */
|
||||
|
||||
#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */
|
||||
#define PD_RX_SOP0 0x01 /* SOP0 received */
|
||||
#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */
|
||||
#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */
|
||||
|
||||
#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */
|
||||
#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */
|
||||
#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */
|
||||
#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/
|
||||
#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/
|
||||
|
||||
|
||||
#define bCC_CMP_22 0X01
|
||||
#define bCC_CMP_45 0X02
|
||||
#define bCC_CMP_55 0X04
|
||||
#define bCC_CMP_66 0X08
|
||||
#define bCC_CMP_95 0X10
|
||||
#define bCC_CMP_123 0X20
|
||||
#define bCC_CMP_220 0X40
|
||||
|
||||
/******************************************************************************/
|
||||
/* PD State Machine */
|
||||
typedef enum
|
||||
{
|
||||
STA_IDLE = 0, /* 0: No task status */
|
||||
STA_DISCONNECT, /* 1: Disconnection */
|
||||
STA_SRC_CONNECT, /* 2: SRC connect */
|
||||
STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */
|
||||
STA_RX_SRC_CAP, /* 4: SRC_CAP received */
|
||||
STA_TX_REQ, /* 5: Send REQUEST */
|
||||
STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */
|
||||
STA_RX_ACCEPT, /* 7: ACCEPT received */
|
||||
STA_RX_REJECT, /* 8: REJECT received */
|
||||
STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */
|
||||
STA_RX_PS_RDY, /* 10: PS_RDY received */
|
||||
STA_SINK_CONNECT, /* 11: SNK access */
|
||||
STA_TX_SRC_CAP, /* 12: Send SRC_CAP */
|
||||
STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */
|
||||
STA_RX_REQ, /* 14: REQUEST received */
|
||||
STA_TX_ACCEPT, /* 15: Send ACCEPT */
|
||||
STA_TX_REJECT, /* 16: Send REJECT */
|
||||
STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */
|
||||
STA_TX_PS_RDY, /* 18: Send PS_RDY */
|
||||
STA_TX_DR_SWAP, /* 19: Send DR_SWAP */
|
||||
STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */
|
||||
STA_TX_PR_SWAP, /* 21: Send PR_SWAP */
|
||||
STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */
|
||||
STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */
|
||||
STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */
|
||||
STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */
|
||||
STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */
|
||||
STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */
|
||||
STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */
|
||||
STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */
|
||||
STA_MODE_SWITCH, /* 30: Mode switching */
|
||||
STA_TX_SOFTRST, /* 31: Sending a software reset */
|
||||
STA_TX_HRST, /* 32: Send hardware reset */
|
||||
STA_PHY_RST, /* 33: PHY reset */
|
||||
STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */
|
||||
} CC_STATUS;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PD Message Header Struct */
|
||||
typedef union
|
||||
{
|
||||
struct _Message_Header
|
||||
{
|
||||
UINT8 MsgType: 5; /* Message Type */
|
||||
UINT8 PDRole: 1; /* 0-UFP; 1-DFP */
|
||||
UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */
|
||||
UINT8 PRRole: 1; /* 0-Sink; 1-Source */
|
||||
UINT8 MsgID: 3;
|
||||
UINT8 NumDO: 3;
|
||||
UINT8 Ext: 1;
|
||||
}Message_Header;
|
||||
UINT16 Data;
|
||||
}_Message_Header;
|
||||
|
||||
/******************************************************************************/
|
||||
/* Bit definition */
|
||||
typedef union
|
||||
{
|
||||
struct _BITS_
|
||||
{
|
||||
UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */
|
||||
UINT8 Connected: 1; /* PD Physical Layer Connected Flag */
|
||||
UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */
|
||||
UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */
|
||||
UINT8 PR_Role: 1; /* 0-Sink; 1-Source */
|
||||
UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */
|
||||
UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */
|
||||
UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */
|
||||
UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */
|
||||
UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */
|
||||
UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */
|
||||
UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */
|
||||
UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */
|
||||
UINT8 Recv: 3;
|
||||
}Bit;
|
||||
UINT16 Bit_Flag;
|
||||
}_BIT_FLAG;
|
||||
|
||||
/* PD control-related structures */
|
||||
typedef struct _PD_CONTROL
|
||||
{
|
||||
CC_STATUS PD_State; /* PD communication status machine */
|
||||
CC_STATUS PD_State_Last; /* PD communication status machine (last value) */
|
||||
UINT8 Msg_ID; /* ID of the message sent */
|
||||
UINT8 Det_Timer; /* PD connection status detection timing */
|
||||
UINT8 Det_Cnt; /* Number of PD connection status detections */
|
||||
UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */
|
||||
UINT8 HPD_Det_Timer; /* HPD connection detection timing */
|
||||
UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */
|
||||
UINT16 PD_Comm_Timer; /* PD shared timing variables */
|
||||
UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */
|
||||
UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */
|
||||
UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */
|
||||
UINT8 Err_Op_Cnt; /* Exception operation count */
|
||||
UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */
|
||||
_BIT_FLAG Flag; /* Flag byte bit definition */
|
||||
}PD_CONTROL, *pPD_CONTROL;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
46
Peripheral/inc/ch564_xbus.h
Normal file
46
Peripheral/inc/ch564_xbus.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_xbus.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* XBUS firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH564_XBUS_H
|
||||
#define __CH564_XBUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "ch564.h"
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NoOutput = 0x0,
|
||||
AddrNum_6bit,
|
||||
AddrNum_12bit,
|
||||
AddrNum_ALL
|
||||
} XbusOutputADDrBit;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
Setuptime_1clk,
|
||||
Setuptime_2clk,
|
||||
} XbusSetupTime;
|
||||
|
||||
#define SET_XBUS_CYCLE(val) (R8_XBUS_CYCLE = XBUS_CYCLE_VALUE_MASK & (val))
|
||||
|
||||
void XbusInit(XbusOutputADDrBit AddrBit, FunctionalState Bit32En, FunctionalState Stat);
|
||||
void XbusHoldInit(XbusSetupTime setuptm, uint8_t holdtm);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
37
Peripheral/src/ch564_adc.c
Normal file
37
Peripheral/src/ch564_adc.c
Normal file
@@ -0,0 +1,37 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_adc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the ADC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_adc.h"
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ADC_SelectChannel
|
||||
*
|
||||
* @brief The function sets the ADC channel for conversion.
|
||||
*
|
||||
* @param adcChannel The adcChannel parameter is of type ADCChannelTypedef, which is likely an
|
||||
* enumeration or a typedef for an integer value representing the desired ADC channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ADC_SelectChannel(ADCChannelTypedef adcChannel)
|
||||
{
|
||||
if (adcChannel <= ADC_Channel0_1)
|
||||
{
|
||||
R32_ADC_CTRL &= ~MASK_ADC_CTL_MOD1;
|
||||
R8_ADC_CTRL_MOD &= ~RB_ADC_CHAN_MOD;
|
||||
R8_ADC_CTRL_MOD |= adcChannel << 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
R32_ADC_CTRL &= ~MASK_ADC_CTL_MOD1;
|
||||
R32_ADC_CTRL |= adcChannel - 1;
|
||||
}
|
||||
}
|
||||
2487
Peripheral/src/ch564_eth.c
Normal file
2487
Peripheral/src/ch564_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
409
Peripheral/src/ch564_gpio.c
Normal file
409
Peripheral/src/ch564_gpio.c
Normal file
@@ -0,0 +1,409 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_gpio.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the GPIO firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_gpio.h"
|
||||
#include "ISP564.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOA_ModeCfg
|
||||
*
|
||||
* @brief GPIOA port pin mode configuration
|
||||
*
|
||||
* @param pin - PA0-PA15
|
||||
* GPIO_Pin_0 - GPIO_Pin_15
|
||||
* mode -
|
||||
* GPIO_ModeIN_Floating - Floating input/high impedance input
|
||||
* GPIO_ModeIN_PU - input with pull-up resistor
|
||||
* GPIO_ModeIN_PD - input with pull-down resistor
|
||||
* GPIO_ModeOut_OP - Drain output
|
||||
* GPIO_ModeOut_PP - Push-pull output
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
|
||||
void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode)
|
||||
{
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ModeIN_Floating:
|
||||
R32_PA_PD &= ~pin;
|
||||
R32_PA_PU &= ~pin;
|
||||
R32_PA_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PU:
|
||||
R32_PA_PD &= ~pin;
|
||||
R32_PA_PU |= pin;
|
||||
R32_PA_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PD:
|
||||
R32_PA_PD |= pin;
|
||||
R32_PA_PU &= ~pin;
|
||||
R32_PA_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_OP:
|
||||
R32_PA_PD |= pin;
|
||||
R32_PA_DIR |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_PP:
|
||||
R32_PA_DIR |= pin;
|
||||
R32_PA_PU &= ~pin;
|
||||
R32_PA_PD &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOB_ModeCfg
|
||||
*
|
||||
* @brief GPIOB port pin mode configuration
|
||||
*
|
||||
* @param pin - PB0-PB15
|
||||
* GPIO_Pin_0 - GPIO_Pin_15
|
||||
* mode -
|
||||
* GPIO_ModeIN_Floating - Floating input/high impedance input
|
||||
* GPIO_ModeIN_PU - input with pull-up resistor
|
||||
* GPIO_ModeIN_PD - input with pull-down resistor
|
||||
* GPIO_ModeOut_OP - Drain output
|
||||
* GPIO_ModeOut_PP - Push-pull output
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
|
||||
void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ModeIN_Floating:
|
||||
R32_PB_PD &= ~pin;
|
||||
R32_PB_PU &= ~pin;
|
||||
R32_PB_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PU:
|
||||
R32_PB_PD &= ~pin;
|
||||
R32_PB_PU |= pin;
|
||||
R32_PB_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PD:
|
||||
R32_PB_PD |= pin;
|
||||
R32_PB_PU &= ~pin;
|
||||
R32_PB_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_OP:
|
||||
R32_PB_PD |= pin;
|
||||
R32_PB_DIR |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_PP:
|
||||
R32_PB_DIR |= pin;
|
||||
R32_PB_PU &= ~pin;
|
||||
R32_PB_PD &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOD_ModeCfg
|
||||
*
|
||||
* @brief GPIOD port pin mode configuration
|
||||
*
|
||||
* @param pin - PD0-PD15
|
||||
* GPIO_Pin_0 - GPIO_Pin_15
|
||||
* mode -
|
||||
* GPIO_ModeIN_Floating - Floating input/high impedance input
|
||||
* GPIO_ModeIN_PU - input with pull-up resistor
|
||||
* GPIO_ModeIN_PD - input with pull-down resistor
|
||||
* GPIO_ModeOut_OP - Drain output
|
||||
* GPIO_ModeOut_PP - Push-pull output
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
|
||||
void GPIOD_ModeCfg(uint32_t pin, GPIOModeTypeDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ModeIN_Floating:
|
||||
R32_PD_PD &= ~pin;
|
||||
R32_PD_PU &= ~pin;
|
||||
R32_PD_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PU:
|
||||
R32_PD_PD &= ~pin;
|
||||
R32_PD_PU |= pin;
|
||||
R32_PD_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeIN_PD:
|
||||
R32_PD_PD |= pin;
|
||||
R32_PD_PU &= ~pin;
|
||||
R32_PD_DIR &= ~pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_OP:
|
||||
R32_PD_PD |= pin;
|
||||
R32_PD_DIR |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ModeOut_PP:
|
||||
R32_PD_DIR |= pin;
|
||||
R32_PD_PU &= ~pin;
|
||||
R32_PD_PD &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOA_ITModeCfg
|
||||
*
|
||||
* @brief GPIOA pin interrupt mode configuration
|
||||
*
|
||||
* @param pin - PAx
|
||||
* mode -
|
||||
* GPIO_ITMode_LowLevel - Low level trigger
|
||||
* GPIO_ITMode_HighLevel - High level trigger
|
||||
* GPIO_ITMode_FallEdge - Falling edge trigger
|
||||
* GPIO_ITMode_RiseEdge - Rising edge trigger
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ITMode_FallEdge:
|
||||
R32_INT_MODE_PA |= pin;
|
||||
R32_INT_POLAR_PA &= ~pin;
|
||||
R32_INT_ENABLE_PA |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_RiseEdge:
|
||||
R32_INT_MODE_PA |= pin;
|
||||
R32_INT_POLAR_PA |= pin;
|
||||
R32_INT_ENABLE_PA |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_HighLevel:
|
||||
R32_INT_MODE_PA &= ~pin;
|
||||
R32_INT_POLAR_PA |= pin;
|
||||
R32_INT_ENABLE_PA |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_LowLevel:
|
||||
R32_INT_MODE_PA &= ~pin;
|
||||
R32_INT_POLAR_PA &= ~pin;
|
||||
R32_INT_ENABLE_PA |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_None:
|
||||
R32_INT_ENABLE_PA |= pin;
|
||||
R32_INT_ENABLE_PA &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
R32_INT_STATUS_PA = pin;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOB_ITModeCfg
|
||||
*
|
||||
* @brief GPIOB pin interrupt mode configuration
|
||||
*
|
||||
* @param pin - PBx
|
||||
* mode -
|
||||
* GPIO_ITMode_LowLevel - Low level trigger
|
||||
* GPIO_ITMode_HighLevel - High level trigger
|
||||
* GPIO_ITMode_FallEdge - Falling edge trigger
|
||||
* GPIO_ITMode_RiseEdge - Rising edge trigger
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ITMode_FallEdge:
|
||||
R32_INT_MODE_PB |= pin;
|
||||
R32_INT_POLAR_PB &= ~pin;
|
||||
R32_INT_ENABLE_PB |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_RiseEdge:
|
||||
R32_INT_MODE_PB |= pin;
|
||||
R32_INT_POLAR_PB |= pin;
|
||||
R32_INT_ENABLE_PB |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_HighLevel:
|
||||
R32_INT_MODE_PB &= ~pin;
|
||||
R32_INT_POLAR_PB |= pin;
|
||||
R32_INT_ENABLE_PB |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_LowLevel:
|
||||
R32_INT_MODE_PB &= ~pin;
|
||||
R32_INT_POLAR_PB &= ~pin;
|
||||
R32_INT_ENABLE_PB |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_None:
|
||||
R32_INT_ENABLE_PB |= pin;
|
||||
R32_INT_ENABLE_PB &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
R32_INT_STATUS_PB = pin;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIOD_ITModeCfg
|
||||
*
|
||||
* @brief GPIOD pin interrupt mode configuration
|
||||
*
|
||||
* @param pin - PDx
|
||||
* mode -
|
||||
* GPIO_ITMode_LowLevel - Low level trigger
|
||||
* GPIO_ITMode_HighLevel - High level trigger
|
||||
* GPIO_ITMode_FallEdge - Falling edge trigger
|
||||
* GPIO_ITMode_RiseEdge - Rising edge trigger
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIOD_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_ITMode_FallEdge:
|
||||
R32_INT_MODE_PD |= pin;
|
||||
R32_INT_POLAR_PD &= ~pin;
|
||||
R32_INT_ENABLE_PD |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_RiseEdge:
|
||||
R32_INT_MODE_PD |= pin;
|
||||
R32_INT_POLAR_PD |= pin;
|
||||
R32_INT_ENABLE_PD |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_HighLevel:
|
||||
R32_INT_MODE_PD &= ~pin;
|
||||
R32_INT_POLAR_PD |= pin;
|
||||
R32_INT_ENABLE_PD |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_LowLevel:
|
||||
R32_INT_MODE_PD &= ~pin;
|
||||
R32_INT_POLAR_PD &= ~pin;
|
||||
R32_INT_ENABLE_PD |= pin;
|
||||
break;
|
||||
|
||||
case GPIO_ITMode_None:
|
||||
R32_INT_ENABLE_PD |= pin;
|
||||
R32_INT_ENABLE_PD &= ~pin;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
R32_INT_STATUS_PD = pin;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn GPIO_PinRemapConfig
|
||||
*
|
||||
* @brief Remap GPIO function
|
||||
*
|
||||
* @param GPIO_Remap - GPIO_Remap_x
|
||||
* NewSTA - ENABLE
|
||||
* - DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewSTA)
|
||||
{
|
||||
uint32_t tempr = R32_AFIO_PCFR1;
|
||||
/*GPIO_Remap fomat:
|
||||
bit[31]: Choose register R32_AFIO_PCFR1(0x0) or R32_AFIO_PCFR2(0x80000000) to be write
|
||||
bit[24:20]: Position of bits low anchor
|
||||
bit[19:16]: Size of bits
|
||||
bit[15:0]: Specific value of remap
|
||||
*/
|
||||
if (GPIO_Remap & 0x80000000)
|
||||
{
|
||||
tempr = R32_AFIO_PCFR2;
|
||||
}
|
||||
/*Clear bits*/
|
||||
tempr &= ~((~(0xffffffff << ((GPIO_Remap >> 16) & 0xf))) << ((GPIO_Remap >> 20) & 0x1f));
|
||||
/*Write bits*/
|
||||
if (NewSTA == ENABLE)
|
||||
{
|
||||
tempr |= (GPIO_Remap & (~(0xffffffff << ((GPIO_Remap >> 16) & 0xf)))) << ((GPIO_Remap >> 20) & 0x1f);
|
||||
}
|
||||
if (GPIO_Remap & 0x80000000)
|
||||
R32_AFIO_PCFR2 = tempr;
|
||||
else
|
||||
R32_AFIO_PCFR1 = tempr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_IPD_Unused
|
||||
*
|
||||
* @brief Configure unused GPIO as input pull-down.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_IPD_Unused(void)
|
||||
{
|
||||
uint32_t ChipID;
|
||||
GetCHIPID(&ChipID);
|
||||
switch (ChipID & 0xffffff0f)
|
||||
{
|
||||
case 0x56410508:
|
||||
GPIOD_ModeCfg(0xFFFFFFFF, GPIO_ModeIN_PD);
|
||||
GPIOB_ModeCfg(GPIO_Pin_22, GPIO_ModeIN_PD);
|
||||
GPIOA_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_7 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_17 |
|
||||
GPIO_Pin_18 | GPIO_Pin_19),
|
||||
GPIO_ModeIN_PD);
|
||||
break;
|
||||
|
||||
case 0x56430508:
|
||||
GPIOD_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_20), GPIO_ModeIN_PD);
|
||||
GPIOB_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_6 | GPIO_Pin_17 | GPIO_Pin_18 | GPIO_Pin_19 | 0xFF00), GPIO_ModeIN_PD);
|
||||
GPIOA_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_7 | GPIO_Pin_12 | GPIO_Pin_11), GPIO_ModeIN_PD);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
930
Peripheral/src/ch564_i2c.c
Normal file
930
Peripheral/src/ch564_i2c.c
Normal file
@@ -0,0 +1,930 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_i2c.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the I2C firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_i2c.h"
|
||||
|
||||
/* I2C SPE mask */
|
||||
#define CTLR1_PE_Set ((uint16_t)0x0001)
|
||||
#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C START mask */
|
||||
#define CTLR1_START_Set ((uint16_t)0x0100)
|
||||
#define CTLR1_START_Reset ((uint16_t)0xFEFF)
|
||||
|
||||
/* I2C STOP mask */
|
||||
#define CTLR1_STOP_Set ((uint16_t)0x0200)
|
||||
#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
|
||||
|
||||
/* I2C ACK mask */
|
||||
#define CTLR1_ACK_Set ((uint16_t)0x0400)
|
||||
#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
|
||||
|
||||
/* I2C ENGC mask */
|
||||
#define CTLR1_ENGC_Set ((uint16_t)0x0040)
|
||||
#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2C SWRST mask */
|
||||
#define CTLR1_SWRST_Set ((uint16_t)0x8000)
|
||||
#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
|
||||
|
||||
/* I2C PEC mask */
|
||||
#define CTLR1_PEC_Set ((uint16_t)0x1000)
|
||||
#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
|
||||
|
||||
/* I2C ENPEC mask */
|
||||
#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
|
||||
#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
|
||||
|
||||
/* I2C ENARP mask */
|
||||
#define CTLR1_ENARP_Set ((uint16_t)0x0010)
|
||||
#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
|
||||
|
||||
/* I2C NOSTRETCH mask */
|
||||
#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
|
||||
#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
|
||||
|
||||
/* I2C registers Masks */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
|
||||
|
||||
/* I2C DMAEN mask */
|
||||
#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
|
||||
#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C LAST mask */
|
||||
#define CTLR2_LAST_Set ((uint16_t)0x1000)
|
||||
#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
|
||||
|
||||
/* I2C FREQ mask */
|
||||
#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
|
||||
|
||||
/* I2C ADD0 mask */
|
||||
#define OADDR1_ADD0_Set ((uint16_t)0x0001)
|
||||
#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C ENDUAL mask */
|
||||
#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
|
||||
#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C ADD2 mask */
|
||||
#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
|
||||
|
||||
/* I2C F/S mask */
|
||||
#define CKCFGR_FS_Set ((uint16_t)0x8000)
|
||||
|
||||
/* I2C CCR mask */
|
||||
#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
|
||||
|
||||
/* I2C FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x00FFFFFF)
|
||||
|
||||
/* I2C Interrupt Enable mask */
|
||||
#define ITEN_Mask ((uint32_t)0x07000000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DeInit
|
||||
*
|
||||
* @brief Deinitializes the I2Cx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DeInit(I2C_Typedef *I2Cx)
|
||||
{
|
||||
if (I2Cx == I2C)
|
||||
{
|
||||
R8_SLP_CLK_OFF1 &= ~RB_SLP_CLK_I2C;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Init
|
||||
*
|
||||
* @brief Initializes the I2Cx peripheral according to the specified
|
||||
* parameters in the I2C_InitStruct.
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
|
||||
* contains the configuration information for the specified I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Init(I2C_Typedef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0, freqrange = 0;
|
||||
uint16_t result = 0x04;
|
||||
uint32_t pclk1 = 8000000;
|
||||
|
||||
pclk1 = SystemCoreClock;
|
||||
tmpreg = I2Cx->CTLR2;
|
||||
tmpreg &= CTLR2_FREQ_Reset;
|
||||
|
||||
freqrange = (uint16_t)(pclk1 / 1000000);
|
||||
tmpreg |= freqrange;
|
||||
I2Cx->CTLR2 = tmpreg;
|
||||
|
||||
I2Cx->CTLR1 &= CTLR1_PE_Reset;
|
||||
tmpreg = 0;
|
||||
|
||||
if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
|
||||
|
||||
if (result < 0x04)
|
||||
{
|
||||
result = 0x04;
|
||||
}
|
||||
|
||||
tmpreg |= result;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
|
||||
result |= I2C_DutyCycle_16_9;
|
||||
}
|
||||
|
||||
if ((result & CKCFGR_CCR_Set) == 0)
|
||||
{
|
||||
result |= (uint16_t)0x0001;
|
||||
}
|
||||
|
||||
tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
|
||||
}
|
||||
|
||||
I2Cx->CKCFGR = tmpreg;
|
||||
I2Cx->CTLR1 |= CTLR1_PE_Set;
|
||||
|
||||
tmpreg = I2Cx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
|
||||
I2Cx->CTLR1 = tmpreg;
|
||||
|
||||
I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_StructInit
|
||||
*
|
||||
* @brief Fills each I2C_InitStruct member with its default value.
|
||||
*
|
||||
* @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
I2C_InitStruct->I2C_ClockSpeed = 5000;
|
||||
I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
|
||||
I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
|
||||
I2C_InitStruct->I2C_OwnAddress1 = 0;
|
||||
I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
|
||||
I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Cmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_PE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_PE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C DMA requests.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DMACmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DMALastTransferCmd
|
||||
*
|
||||
* @brief Specifies if the next DMA transfer will be the last one.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DMALastTransferCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= CTLR2_LAST_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= CTLR2_LAST_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GenerateSTART
|
||||
*
|
||||
* @brief Generates I2Cx communication START condition.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GenerateSTART(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_START_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_START_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GenerateSTOP
|
||||
*
|
||||
* @brief Generates I2Cx communication STOP condition.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GenerateSTOP(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_STOP_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_STOP_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_AcknowledgeConfig
|
||||
*
|
||||
* @brief Enables or disables the specified I2C acknowledge feature.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_AcknowledgeConfig(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ACK_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ACK_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_OwnAddress2Config
|
||||
*
|
||||
* @brief Configures the specified I2C own address2.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Address - specifies the 7bit I2C own address2.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_OwnAddress2Config(I2C_Typedef *I2Cx, uint8_t Address)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
tmpreg = I2Cx->OADDR2;
|
||||
tmpreg &= OADDR2_ADD2_Reset;
|
||||
tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
|
||||
I2Cx->OADDR2 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DualAddressCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C dual addressing mode.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DualAddressCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GeneralCallCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C general call feature.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GeneralCallCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENGC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified I2C interrupts.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
|
||||
* I2C_IT_BUF - Buffer interrupt mask.
|
||||
* I2C_IT_EVT - Event interrupt mask.
|
||||
* I2C_IT_ERR - Error interrupt mask.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ITConfig(I2C_Typedef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= I2C_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_SendData
|
||||
*
|
||||
* @brief Sends a data byte through the I2Cx peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Data - Byte to be transmitted.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SendData(I2C_Typedef *I2Cx, uint8_t Data)
|
||||
{
|
||||
I2Cx->DATAR = Data;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the I2Cx peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return The value of the received data.
|
||||
*/
|
||||
uint8_t I2C_ReceiveData(I2C_Typedef *I2Cx)
|
||||
{
|
||||
return (uint8_t)I2Cx->DATAR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Send7bitAddress
|
||||
*
|
||||
* @brief Transmits the address byte to select the slave device.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Address - specifies the slave address which will be transmitted.
|
||||
* I2C_Direction - specifies whether the I2C device will be a
|
||||
* Transmitter or a Receiver.
|
||||
* I2C_Direction_Transmitter - Transmitter mode.
|
||||
* I2C_Direction_Receiver - Receiver mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Send7bitAddress(I2C_Typedef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
|
||||
{
|
||||
if (I2C_Direction != I2C_Direction_Transmitter)
|
||||
{
|
||||
Address |= OADDR1_ADD0_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
Address &= OADDR1_ADD0_Reset;
|
||||
}
|
||||
|
||||
I2Cx->DATAR = Address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ReadRegister
|
||||
*
|
||||
* @brief Reads the specified I2C register and returns its value.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_Register - specifies the register to read.
|
||||
* I2C_Register_CTLR1.
|
||||
* I2C_Register_CTLR2.
|
||||
* I2C_Register_OADDR1.
|
||||
* I2C_Register_OADDR2.
|
||||
* I2C_Register_DATAR.
|
||||
* I2C_Register_STAR1.
|
||||
* I2C_Register_STAR2.
|
||||
* I2C_Register_CKCFGR.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint16_t I2C_ReadRegister(I2C_Typedef *I2Cx, uint8_t I2C_Register)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
tmp = (uint32_t)I2Cx;
|
||||
tmp += I2C_Register;
|
||||
|
||||
return (*(__IO uint16_t *)tmp);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_SoftwareResetCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C software reset.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SoftwareResetCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_SWRST_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_NACKPositionConfig
|
||||
*
|
||||
* @brief Selects the specified I2C NACK position in master receiver mode.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_NACKPosition - specifies the NACK position.
|
||||
* I2C_NACKPosition_Next - indicates that the next byte will be
|
||||
* the last received byte.
|
||||
* I2C_NACKPosition_Current - indicates that current byte is the
|
||||
* last received byte.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_NACKPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_NACKPosition)
|
||||
{
|
||||
if (I2C_NACKPosition == I2C_NACKPosition_Next)
|
||||
{
|
||||
I2Cx->CTLR1 |= I2C_NACKPosition_Next;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= I2C_NACKPosition_Current;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_TransmitPEC
|
||||
*
|
||||
* @brief Enables or disables the specified I2C PEC transfer.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_TransmitPEC(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_PEC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_PEC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_PECPositionConfig
|
||||
*
|
||||
* @brief Selects the specified I2C PEC position.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_PECPosition - specifies the PEC position.
|
||||
* I2C_PECPosition_Next - indicates that the next byte is PEC.
|
||||
* I2C_PECPosition_Current - indicates that current byte is PEC.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_PECPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_PECPosition)
|
||||
{
|
||||
if (I2C_PECPosition == I2C_PECPosition_Next)
|
||||
{
|
||||
I2Cx->CTLR1 |= I2C_PECPosition_Next;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= I2C_PECPosition_Current;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_CalculatePEC
|
||||
*
|
||||
* @brief Enables or disables the PEC value calculation of the transferred bytes.
|
||||
*
|
||||
* @param I2Cx- where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_CalculatePEC(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetPEC
|
||||
*
|
||||
* @brief Returns the PEC value for the specified I2C.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return The PEC value.
|
||||
*/
|
||||
uint8_t I2C_GetPEC(I2C_Typedef *I2Cx)
|
||||
{
|
||||
return ((I2Cx->STAR2) >> 8);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ARPCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C ARP.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return The PEC value.
|
||||
*/
|
||||
void I2C_ARPCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENARP_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_StretchClockCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C Clock stretching.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_StretchClockCmd(I2C_Typedef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if (NewState == DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_FastModeDutyCycleConfig
|
||||
*
|
||||
* @brief Selects the specified I2C fast mode duty cycle.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_DutyCycle - specifies the fast mode duty cycle.
|
||||
* I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
|
||||
* I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_FastModeDutyCycleConfig(I2C_Typedef *I2Cx, uint16_t I2C_DutyCycle)
|
||||
{
|
||||
if (I2C_DutyCycle != I2C_DutyCycle_16_9)
|
||||
{
|
||||
I2Cx->CKCFGR &= I2C_DutyCycle_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_CheckEvent
|
||||
*
|
||||
* @brief Checks whether the last I2Cx Event is equal to the one passed
|
||||
* as parameter.
|
||||
*
|
||||
* @param I2Cx- where x can be 1 to select the I2C peripheral.
|
||||
* I2C_EVENT: specifies the event to be checked.
|
||||
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
|
||||
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
|
||||
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
|
||||
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
|
||||
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
|
||||
* I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
|
||||
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
|
||||
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
|
||||
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
|
||||
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
|
||||
* I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
|
||||
* I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
|
||||
* I2C_EVENT_MASTER_MODE_SELECT - EV5.
|
||||
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
|
||||
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
|
||||
* I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
|
||||
* I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
|
||||
* I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
|
||||
* I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_Typedef *I2Cx, uint32_t I2C_EVENT)
|
||||
{
|
||||
uint32_t lastevent = 0;
|
||||
uint32_t flag1 = 0, flag2 = 0;
|
||||
ErrorStatus status = NoREADY;
|
||||
|
||||
flag1 = I2Cx->STAR1;
|
||||
flag2 = I2Cx->STAR2;
|
||||
flag2 = flag2 << 16;
|
||||
|
||||
lastevent = (flag1 | flag2) & FLAG_Mask;
|
||||
|
||||
if ((lastevent & I2C_EVENT) == I2C_EVENT)
|
||||
{
|
||||
status = READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = NoREADY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetLastEvent
|
||||
*
|
||||
* @brief Returns the last I2Cx Event.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_Typedef *I2Cx)
|
||||
{
|
||||
uint32_t lastevent = 0;
|
||||
uint32_t flag1 = 0, flag2 = 0;
|
||||
|
||||
flag1 = I2Cx->STAR1;
|
||||
flag2 = I2Cx->STAR2;
|
||||
flag2 = flag2 << 16;
|
||||
lastevent = (flag1 | flag2) & FLAG_Mask;
|
||||
|
||||
return lastevent;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the last I2Cx Event is equal to the one passed
|
||||
* as parameter.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_FLAG - specifies the flag to check.
|
||||
* I2C_FLAG_DUALF - Dual flag (Slave mode).
|
||||
* I2C_FLAG_GENCALL - General call header flag (Slave mode).
|
||||
* I2C_FLAG_TRA - Transmitter/Receiver flag.
|
||||
* I2C_FLAG_BUSY - Bus busy flag.
|
||||
* I2C_FLAG_MSL - Master/Slave flag.
|
||||
* I2C_FLAG_PECERR - PEC error in reception flag.
|
||||
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_FLAG_AF - Acknowledge failure flag.
|
||||
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_FLAG_BERR - Bus error flag.
|
||||
* I2C_FLAG_TXE - Data register empty flag (Transmitter).
|
||||
* I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
|
||||
* I2C_FLAG_STOPF - Stop detection flag (Slave mode).
|
||||
* I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
|
||||
* I2C_FLAG_BTF - Byte transfer finished flag.
|
||||
* I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
|
||||
* Address matched flag (Slave mode)"ENDA".
|
||||
* I2C_FLAG_SB - Start bit flag (Master mode).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_Typedef *I2Cx, uint32_t I2C_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
__IO uint32_t i2creg = 0, i2cxbase = 0;
|
||||
|
||||
i2cxbase = (uint32_t)I2Cx;
|
||||
i2creg = I2C_FLAG >> 28;
|
||||
I2C_FLAG &= FLAG_Mask;
|
||||
|
||||
if (i2creg != 0)
|
||||
{
|
||||
i2cxbase += 0x14;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
|
||||
i2cxbase += 0x18;
|
||||
}
|
||||
|
||||
if (((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ClearFlag
|
||||
*
|
||||
* @brief Clears the I2Cx's pending flags.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_FLAG - specifies the flag to clear.
|
||||
* I2C_FLAG_SMBALERT - SMBus Alert flag.
|
||||
* I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
|
||||
* I2C_FLAG_PECERR - PEC error in reception flag.
|
||||
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_FLAG_AF - Acknowledge failure flag.
|
||||
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_FLAG_BERR - Bus error flag.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ClearFlag(I2C_Typedef *I2Cx, uint32_t I2C_FLAG)
|
||||
{
|
||||
uint32_t flagpos = 0;
|
||||
|
||||
flagpos = I2C_FLAG & FLAG_Mask;
|
||||
I2Cx->STAR1 = (uint16_t)~flagpos;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified I2C interrupt has occurred or not.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* II2C_IT - specifies the interrupt source to check.
|
||||
* I2C_IT_PECERR - PEC error in reception flag.
|
||||
* I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_IT_AF - Acknowledge failure flag.
|
||||
* I2C_IT_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_IT_BERR - Bus error flag.
|
||||
* I2C_IT_TXE - Data register empty flag (Transmitter).
|
||||
* I2C_IT_RXNE - Data register not empty (Receiver) flag.
|
||||
* I2C_IT_STOPF - Stop detection flag (Slave mode).
|
||||
* I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
|
||||
* I2C_IT_BTF - Byte transfer finished flag.
|
||||
* I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched
|
||||
* flag (Slave mode)"ENDAD".
|
||||
* I2C_IT_SB - Start bit flag (Master mode).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
ITStatus I2C_GetITStatus(I2C_Typedef *I2Cx, uint32_t I2C_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
|
||||
I2C_IT &= FLAG_Mask;
|
||||
|
||||
if (((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the I2Cx interrupt pending bits.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_IT - specifies the interrupt pending bit to clear.
|
||||
* I2C_IT_PECERR - PEC error in reception interrupt.
|
||||
* I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
|
||||
* I2C_IT_AF - Acknowledge failure interrupt.
|
||||
* I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
|
||||
* I2C_IT_BERR - Bus error interrupt.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ClearITPendingBit(I2C_Typedef *I2Cx, uint32_t I2C_IT)
|
||||
{
|
||||
uint32_t flagpos = 0;
|
||||
|
||||
flagpos = I2C_IT & FLAG_Mask;
|
||||
I2Cx->STAR1 = (uint16_t)~flagpos;
|
||||
}
|
||||
45
Peripheral/src/ch564_pwr.c
Normal file
45
Peripheral/src/ch564_pwr.c
Normal file
@@ -0,0 +1,45 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_pwr.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the PWR firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_pwr.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn LowPower_Idle
|
||||
*
|
||||
* @brief Low power consumption - Idle mode
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_Sleep(uint8_t PWR_STOPEntry)
|
||||
{
|
||||
PFIC->SCTLR &= ~(1 << 2); // Set the SleepDeep field of the core PFIC SCTLR register to 0
|
||||
if (PWR_STOPEntry == PWR_STOPEntry_WFE){
|
||||
__WFE(); // Execute __WFE() after setting the wake-up condition
|
||||
}
|
||||
else
|
||||
__WFI(); // Execute __WFI() after setting the wake-up condition
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn LowPower_Halt
|
||||
*
|
||||
* @brief Low power consumption - Halt mode
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_DeepSleep(uint8_t PWR_STOPEntry)
|
||||
{
|
||||
PFIC->SCTLR |= 1 << 2; // Set the SleepDeep field of the core PFIC SCTLR register to 1
|
||||
if (PWR_STOPEntry == PWR_STOPEntry_WFE)
|
||||
__WFE(); // Execute __WFE() after setting the wake-up condition
|
||||
else
|
||||
__WFI(); // Execute __WFI() after setting the wake-up condition
|
||||
}
|
||||
142
Peripheral/src/ch564_rcc.c
Normal file
142
Peripheral/src/ch564_rcc.c
Normal file
@@ -0,0 +1,142 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_rcc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_rcc.h"
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_SetGlobleMem
|
||||
*
|
||||
* @brief Config the different memory assignment
|
||||
*
|
||||
* @param Cfg - Three choice of memory assignment
|
||||
* Code16k_Data128k - assign 16k memory for code 128k memory for data
|
||||
* Code48k_Data96k - assign 48k memory for code 96k memory for data
|
||||
* Code80k_Data64k - assign 80k memory for code 64k memory for data
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_SetGlobalMemCFG(GlobMem_Cfg Cfg)
|
||||
{
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
R8_GLOB_MEM_CFG = Cfg;
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_LockPort
|
||||
*
|
||||
* @brief Choose a port and decide whether lock or not
|
||||
*
|
||||
* @param globport - choose port
|
||||
* - RB_GLOB_LOCK_PA
|
||||
* - RB_GLOB_LOCK_PB
|
||||
* - RB_GLOB_LOCK_PD
|
||||
* NewSTA - Enable or disable
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
void RCC_LockPort(uint8_t globport, FunctionalState NewSTA)
|
||||
{
|
||||
uint8_t temp = R8_GLOB_LOCK_PORT;
|
||||
NewSTA == ENABLE ? (temp |= globport) : (temp &= ~globport);
|
||||
R8_GLOB_LOCK_PORT = 0x3f & temp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GlobleRstCFG
|
||||
*
|
||||
* @brief Choose Reset function
|
||||
*
|
||||
* @param globrst - choose port
|
||||
* - RB_GLOB_FORCE_RST
|
||||
* - RB_GLOB_WDOG_EN
|
||||
* NewSTA - Enable or disable
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
void RCC_GlobleRstCFG(uint8_t globrst, FunctionalState NewSTA)
|
||||
{
|
||||
uint8_t temp = R8_GLOB_RST_CFG;
|
||||
NewSTA == ENABLE ? (temp = 0x40 | globrst) : (temp = (0x0F & (~globrst))|0x40);
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
R8_GLOB_RST_CFG = temp;
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_SlpClkOff
|
||||
*
|
||||
* @brief Choose peripherals' clock to be on or off
|
||||
*
|
||||
* @param reg - register pointer to write
|
||||
* - R8_SLP_CLK_OFF0
|
||||
* - R8_SLP_CLK_OFF1
|
||||
* - R8_SLP_CTRL_PLL
|
||||
* slpclk - choose periph clock
|
||||
* - RB_SLP_CLK_TMR0
|
||||
* - RB_SLP_CLK_TMR1
|
||||
* - RB_SLP_CLK_TMR2
|
||||
* - RB_SLP_CLK_TMR3
|
||||
* - RB_SLP_CLK_SPI0
|
||||
* - RB_SLP_CLK_SPI1
|
||||
* - RB_SLP_CLK_UART0
|
||||
* - RB_SLP_CLK_UART1
|
||||
*
|
||||
* - RB_SLP_CLK_UTMI
|
||||
* - RB_SLP_CLK_I2C
|
||||
* - RB_SLP_CLK_UDP
|
||||
* - RB_SLP_CLK_ADC
|
||||
* - RB_SLP_CLK_GPIO
|
||||
* - RB_SLP_CLK_USB
|
||||
* - RB_SLP_CLK_ETH
|
||||
*
|
||||
* - RB_SLP_CTRL_PLL_UART2
|
||||
* - RB_SLP_CTRL_PLL_UART3
|
||||
* NewSTA - Enable or disable
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
void RCC_SlpClkOff(volatile uint8_t *reg, uint8_t slpclk, FunctionalState NewSTA)
|
||||
{
|
||||
if (reg != &R8_SLP_CLK_OFF0 && reg != &R8_SLP_CLK_OFF1 && reg != &R8_SLP_CTRL_PLL)
|
||||
return;
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
NewSTA == ENABLE ? (*reg |= slpclk) : (*reg &= ~slpclk);
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_SlpWakeCtrl
|
||||
*
|
||||
* @brief Choose Reset function
|
||||
*
|
||||
* @param slpwake - choose periph to wake the device
|
||||
* - RB_SLP_PA_WAKE
|
||||
* - RB_SLP_PB_WAKE
|
||||
* - RB_SLP_PD_WAKE
|
||||
* - RB_SLP_USB_WAKE
|
||||
* - RB_SLP_AP_WAK_USB
|
||||
* - RB_SLP_WOL_WAKE
|
||||
* - RB_SLP_ETH_PWR_DN
|
||||
* NewSTA - Enable or disable
|
||||
* - ENABLE
|
||||
* - DISABLE
|
||||
* @return none
|
||||
*/
|
||||
void RCC_SlpWakeCtrl(uint8_t slpwake, FunctionalState NewSTA)
|
||||
{
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
NewSTA == ENABLE ? (R8_SLP_WAKE_CTRL |= slpwake) : (R8_SLP_WAKE_CTRL &= ~slpwake);
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
129
Peripheral/src/ch564_slv.c
Normal file
129
Peripheral/src/ch564_slv.c
Normal file
@@ -0,0 +1,129 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_slv.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the SLV firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_slv.h"
|
||||
|
||||
/**********************************************************************
|
||||
* @fn SLV_Read
|
||||
* @brief The function SLV_Read reads data from a slave device with a specified data size and timeout.
|
||||
*
|
||||
* @param dataAddress A pointer to the memory location where the received data will be stored.
|
||||
* dataSize The dataSize parameter represents the number of bytes to be read from the SLV
|
||||
* (slave) device.
|
||||
* timeout The "timeout" parameter is the maximum amount of time (in milliseconds) that the
|
||||
* function will wait for data to be received before returning with a timeout error.
|
||||
*
|
||||
* @return a value of type SLV_STA.
|
||||
* --slv_data data read right now is a data
|
||||
* --slv_cmd data read right now is a command
|
||||
* --slv_timeout read data timeout
|
||||
*/
|
||||
SLV_STA SLV_Read(uint8_t *dataAddress, uint16_t dataSize, uint16_t timeout)
|
||||
{
|
||||
SLV_STA SLV_TYPE;
|
||||
|
||||
SLV_TYPE = slv_data;
|
||||
|
||||
while (dataSize--)
|
||||
{
|
||||
uint16_t t = timeout;
|
||||
while (t--)
|
||||
{
|
||||
if (SLV_GET_IF(RB_IF_SLV_WR))
|
||||
{
|
||||
if (SLV_GET_IF(RB_IF_SLV_CMD))
|
||||
SLV_TYPE = slv_cmd;
|
||||
else
|
||||
SLV_TYPE = slv_data;
|
||||
}
|
||||
|
||||
*(dataAddress++) = SLV_GET_DATA();
|
||||
}
|
||||
if (t == 0)
|
||||
{
|
||||
SLV_TYPE = slv_timeout;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return SLV_TYPE;
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* @fn SLV_SendDATA
|
||||
*
|
||||
* @brief The function SLV_SendDATA sends data over a communication interface and returns the status of the
|
||||
* operation.
|
||||
*
|
||||
* @param data The "data" parameter is a pointer to an array of uint8_t (unsigned 8-bit integer)
|
||||
* values. It represents the data that needs to be sent.
|
||||
* datasize The parameter "datasize" is the size of the data array that is being sent. It
|
||||
* represents the number of elements in the array.
|
||||
*
|
||||
* @return ErrorStatus value. If the timeout value reaches 0 before the condition "R8_INT_FLAG_SLV &
|
||||
* RB_IF_SLV_RD" is true, the function will return NoREADY. Otherwise, it will return READY.
|
||||
*/
|
||||
ErrorStatus SLV_SendDATA(uint8_t *data, uint16_t datasize)
|
||||
{
|
||||
uint16_t timeout;
|
||||
|
||||
while (datasize--)
|
||||
{
|
||||
timeout = 100;
|
||||
SLV_SEND_DATA(*(data++));
|
||||
while (timeout--)
|
||||
{
|
||||
if (SLV_GET_IF(RB_IF_SLV_RD))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (timeout == 0)
|
||||
{
|
||||
return NoREADY;
|
||||
}
|
||||
}
|
||||
return READY;
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* @fn SLV_SendSTA
|
||||
*
|
||||
* @brief The function SLV_SendSTA sends a series of data bytes to a slave device and returns a status
|
||||
* indicating if the operation was successful or not.
|
||||
*
|
||||
* @param sta A pointer to an array of uint8_t values that represent the data to be sent.
|
||||
* datasize datasize is the number of bytes in the sta array that need to be sent.
|
||||
*
|
||||
* @return ErrorStatus.
|
||||
*/
|
||||
ErrorStatus SLV_SendSTA(uint8_t *sta, uint16_t datasize)
|
||||
{
|
||||
uint16_t timeout;
|
||||
|
||||
while (datasize--)
|
||||
{
|
||||
timeout = 100;
|
||||
SLV_SEND_STA(*(sta++));
|
||||
while (timeout--)
|
||||
{
|
||||
if (SLV_GET_IF(RB_IF_SLV_RD))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (timeout == 0)
|
||||
{
|
||||
return NoREADY;
|
||||
}
|
||||
}
|
||||
return READY;
|
||||
}
|
||||
678
Peripheral/src/ch564_spi.c
Normal file
678
Peripheral/src/ch564_spi.c
Normal file
@@ -0,0 +1,678 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_spi.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the SPI firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_spi.h"
|
||||
#include "debug.h"
|
||||
|
||||
uint32_t spi_comm_tick = 0;
|
||||
#define SPICOMM_TIMEOUT 10
|
||||
|
||||
static void delay()
|
||||
{
|
||||
for (uint16_t i = 0; i < (SystemCoreClock / 1000000) * 1000; i++);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterDefInit
|
||||
*
|
||||
* @brief Host mode default initialization
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_MasterInit(uint32_t clockRate)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_MODE_SLAVE, DISABLE);
|
||||
SPI0_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR | RB_SPI_FIFO_DIR, ENABLE);
|
||||
SPI0_MODE_CFG(RB_SPI_MISO_OE | RB_SPI_ALL_CLEAR, DISABLE);
|
||||
SPI0_SET_CLOCK_DIV((SystemCoreClock / clockRate) < 2 ? (2) : (SystemCoreClock / clockRate));
|
||||
SPI0_SET_DMA_MODE(0xff, DISABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_DataMode
|
||||
*
|
||||
* @brief Set data flow mode
|
||||
*
|
||||
* @param mode - data flow mode
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_DataMode(ModeBitOrderTypeDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case Mode0_HighBitINFront: // Mode 0, high bit first
|
||||
SPI0_MODE_CFG(RB_SPI_MST_SCK_MOD, DISABLE);
|
||||
break;
|
||||
case Mode3_HighBitINFront: // Mode 3, high bit first
|
||||
SPI0_MODE_CFG(RB_SPI_MST_SCK_MOD, ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterSendByte
|
||||
*
|
||||
* @brief Send a single byte (buffer)
|
||||
*
|
||||
* @param data - send bytes
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_MasterSendByte(uint8_t data)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE);
|
||||
SPI0_SET_TOTAL_CNT(1);
|
||||
SPI0_SET_FIFO(data);
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (SPI0_GET_TOTAL_CNT() != 0)
|
||||
{
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterRecvByte
|
||||
*
|
||||
* @brief Receive a single byte (buffer)
|
||||
*
|
||||
* @return bytes received
|
||||
*/
|
||||
uint8_t SPI0_MasterRecvByte(void)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE);
|
||||
SPI0_SET_TOTAL_CNT(1);
|
||||
SPI0_SET_BUFFER(0xff);
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (!SPI0_GET_FIFO_CNT())
|
||||
{
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
return (SPI0_GET_FIFO());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterTrans
|
||||
*
|
||||
* @brief Continuously send multiple bytes using FIFO
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI0_ClearITFlag(RB_SPI_IF_CNT_END);
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (sendlen)
|
||||
{
|
||||
if (SPI0_GET_FIFO_CNT() < SPI0_FIFO_SIZE)
|
||||
{
|
||||
SPI0_SET_FIFO(*pbuf);
|
||||
pbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (SPI0_GET_TOTAL_CNT() != 0) // Wait for all the data in the FIFO to be sent
|
||||
{
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterRecv
|
||||
*
|
||||
* @brief Receive multiple bytes continuously using FIFO
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len)
|
||||
{
|
||||
uint16_t readlen;
|
||||
|
||||
readlen = len;
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set data direction to input
|
||||
SPI0_SET_TOTAL_CNT(len); // Set the length of the data to be received, the FIFO direction will start the
|
||||
// transmission if the input length is not 0
|
||||
R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END;
|
||||
SPI0_SET_BUFFER(0xff);
|
||||
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (readlen)
|
||||
{
|
||||
if (SPI0_GET_FIFO_CNT())
|
||||
{
|
||||
*pbuf = SPI0_GET_FIFO();
|
||||
SPI0_SET_BUFFER(0xff);
|
||||
pbuf++;
|
||||
readlen--;
|
||||
}
|
||||
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_MasterTransRecv
|
||||
*
|
||||
* @brief Continuously send/receive multiple bytes
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI0_ClearITFlag(RB_SPI_IF_CNT_END);
|
||||
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (sendlen)
|
||||
{
|
||||
if (SPI0_GET_FIFO_CNT() == 0)
|
||||
{
|
||||
SPI0_SET_FIFO(*ptbuf);
|
||||
while (SPI0_GET_FIFO_CNT() != 0);
|
||||
ptbuf++;
|
||||
*prbuf = SPI0_GET_BUFFER();
|
||||
prbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_DMATrans
|
||||
*
|
||||
* @brief Continuously send data in DMA mode
|
||||
*
|
||||
* @param pbuf: The starting address of the data to be sent
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_DMATrans(uint8_t *pbuf, uint32_t len)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE);
|
||||
|
||||
SPI0_SET_DMA_RANGE(pbuf, pbuf + len);
|
||||
SPI0_SET_TOTAL_CNT(len);
|
||||
SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, ENABLE);
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (SPI0_GET_TOTAL_CNT())
|
||||
{
|
||||
if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break;
|
||||
}
|
||||
SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, DISABLE);
|
||||
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_DMARecv
|
||||
*
|
||||
* @brief Receive data continuously in DMA mode
|
||||
*
|
||||
* @param pbuf: The starting address for storing the data to be received
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void SPI0_DMARecv(uint8_t *pbuf, uint32_t len)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE);
|
||||
SPI0_SET_DMA_RANGE(pbuf, pbuf + len);
|
||||
SPI0_SET_TOTAL_CNT(len);
|
||||
SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, ENABLE);
|
||||
spi_comm_tick = SysTick_100us;
|
||||
while (SPI0_GET_TOTAL_CNT())
|
||||
{
|
||||
if(SysTick_100us - spi_comm_tick >= 1000) break;
|
||||
}
|
||||
SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, DISABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_SlaveInit
|
||||
*
|
||||
* @brief Device mode default initialization
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI0_SlaveInit(uint32_t clockRate)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_MODE_SLAVE | RB_SPI_ALL_CLEAR, ENABLE);
|
||||
SPI0_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_ALL_CLEAR | RB_SPI_SCK_OE, DISABLE);
|
||||
SPI0_MODE_CFG(RB_SPI_MISO_OE, ENABLE);
|
||||
|
||||
SPI0_SET_DMA_MODE(0xff, DISABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_SlaveRecvByte
|
||||
*
|
||||
* @brief Slave mode, receive one byte of data
|
||||
*
|
||||
* @return received data
|
||||
*/
|
||||
uint8_t SPI0_SlaveRecvByte(void)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data
|
||||
while (!SPI0_GET_FIFO_CNT());
|
||||
return SPI0_GET_FIFO();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_SlaveRecvByte
|
||||
*
|
||||
* @brief Slave mode, send one byte of data
|
||||
*
|
||||
* @param data: data will be sent
|
||||
*
|
||||
* @return received data
|
||||
**/
|
||||
void SPI0_SlaveSendByte(uint8_t data)
|
||||
{
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set to output mode, send data
|
||||
SPI0_SET_FIFO(data);
|
||||
SPI0_SET_TOTAL_CNT(1);
|
||||
while (SPI0_GET_FIFO_CNT());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_SlaveRecv
|
||||
*
|
||||
* @brief Slave mode, receive multi-byte data
|
||||
*
|
||||
* @param pbuf: Receive data storage starting address
|
||||
*
|
||||
* @return 0/1 0 means receive failed,1 means receive success.
|
||||
**/
|
||||
uint8_t SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len, uint16_t timeouts)
|
||||
{
|
||||
uint16_t revlen;
|
||||
|
||||
revlen = len;
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data
|
||||
SPI0_SET_TOTAL_CNT(revlen); // Assign a value to the SPI send and receive data total length register
|
||||
while (revlen && timeouts)
|
||||
{
|
||||
if (!(timeouts & SPI_MAX_DELAY))
|
||||
{
|
||||
delay();
|
||||
timeouts--;
|
||||
}
|
||||
if (SPI0_GET_FIFO_CNT()) // Byte count in the current FIFO
|
||||
{
|
||||
*pbuf = SPI0_GET_FIFO();
|
||||
pbuf++;
|
||||
revlen--;
|
||||
}
|
||||
}
|
||||
if (!revlen)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI0_SlaveTrans
|
||||
*
|
||||
* @brief Slave mode, send multi-byte data
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return 0/1 0 means receive failed,1 means receive success.
|
||||
*/
|
||||
uint8_t SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len, uint16_t timeouts)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
while (sendlen)
|
||||
{
|
||||
if (!(timeouts & SPI_MAX_DELAY))
|
||||
{
|
||||
delay();
|
||||
timeouts--;
|
||||
}
|
||||
if (SPI0_GET_FIFO_CNT() < SPI0_FIFO_SIZE) // Compare the byte count size in the current FIFO
|
||||
{
|
||||
SPI0_SET_FIFO(*pbuf);
|
||||
pbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
}
|
||||
if (!sendlen)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterDefInit
|
||||
*
|
||||
* @brief Host mode default initialization
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_MasterInit(uint32_t clockRate)
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_MODE_SLAVE, DISABLE);
|
||||
SPI1_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR, ENABLE);
|
||||
SPI1_MODE_CFG(RB_SPI_MISO_OE | RB_SPI_ALL_CLEAR, DISABLE);
|
||||
SPI1_SET_CLOCK_DIV((SystemCoreClock / clockRate) < 2 ? (2) : (SystemCoreClock / clockRate));
|
||||
SPI1_SET_DMA_MODE(0xff, DISABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_DataMode
|
||||
*
|
||||
* @brief Set data flow mode
|
||||
*
|
||||
* @param mode - data flow mode
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_DataMode(ModeBitOrderTypeDef mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case Mode0_HighBitINFront: // Mode 0, high bit first
|
||||
SPI1_MODE_CFG(RB_SPI_MST_SCK_MOD, DISABLE);
|
||||
break;
|
||||
case Mode3_HighBitINFront: // Mode 3, high bit first
|
||||
SPI1_MODE_CFG(RB_SPI_MST_SCK_MOD, ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterSendByte
|
||||
*
|
||||
* @brief Send a single byte (buffer)
|
||||
*
|
||||
* @param data - send bytes
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_MasterSendByte(uint8_t data)
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE);
|
||||
SPI1_SET_TOTAL_CNT(1);
|
||||
SPI1_SET_FIFO(data);
|
||||
|
||||
while (SPI1_GET_TOTAL_CNT() != 0);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterRecvByte
|
||||
*
|
||||
* @brief Receive a single byte (buffer)
|
||||
*
|
||||
* @return bytes received
|
||||
*/
|
||||
uint8_t SPI1_MasterRecvByte(void)
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE);
|
||||
SPI1_SET_TOTAL_CNT(1);
|
||||
SPI1_SET_FIFO(0xff);
|
||||
while (!SPI1_GET_FIFO_CNT());
|
||||
return (SPI1_GET_FIFO());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterTrans
|
||||
*
|
||||
* @brief Continuously send multiple bytes using FIFO
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_MasterTrans(uint8_t *pbuf, uint16_t len)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI1_ClearITFlag(RB_SPI_IF_CNT_END);
|
||||
while (sendlen)
|
||||
{
|
||||
if (SPI1_GET_FIFO_CNT() < SPI1_FIFO_SIZE)
|
||||
{
|
||||
SPI1_SET_FIFO(*pbuf);
|
||||
pbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
}
|
||||
while (SPI1_GET_TOTAL_CNT() != 0); // Wait for all the data in the FIFO to be sent
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterRecv
|
||||
*
|
||||
* @brief Receive multiple bytes continuously using FIFO
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void SPI1_MasterRecv(uint8_t *pbuf, uint16_t len)
|
||||
{
|
||||
uint16_t readlen;
|
||||
|
||||
readlen = len;
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set data direction to input
|
||||
SPI1_SET_TOTAL_CNT(len); // Set the length of the data to be received, the FIFO direction will start the
|
||||
// transmission if the input length is not 0
|
||||
R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END;
|
||||
SPI1_SET_FIFO(0xff);
|
||||
while (readlen)
|
||||
{
|
||||
if (SPI1_GET_FIFO_CNT())
|
||||
{
|
||||
*pbuf = SPI1_GET_FIFO();
|
||||
SPI1_SET_FIFO(0xff);
|
||||
pbuf++;
|
||||
readlen--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_MasterTransRecv
|
||||
*
|
||||
* @brief Continuously send/receive multiple bytes
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI1_ClearITFlag(RB_SPI_IF_CNT_END);
|
||||
while (sendlen)
|
||||
{
|
||||
if (SPI1_GET_FIFO_CNT() == 0)
|
||||
{
|
||||
SPI1_SET_FIFO(*ptbuf);
|
||||
while (SPI1_GET_FIFO_CNT() != 0);
|
||||
ptbuf++;
|
||||
*prbuf = SPI1_GET_BUFFER();
|
||||
prbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_SlaveInit
|
||||
*
|
||||
* @brief Device mode default initialization
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI1_SlaveInit()
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_MODE_SLAVE | RB_SPI_ALL_CLEAR, ENABLE);
|
||||
SPI1_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR, DISABLE);
|
||||
SPI1_MODE_CFG(RB_SPI_MISO_OE, ENABLE);
|
||||
|
||||
SPI1_SET_DMA_MODE(0xff, DISABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_SlaveRecvByte
|
||||
*
|
||||
* @brief Slave mode, receive one byte of data
|
||||
*
|
||||
* @return received data
|
||||
*/
|
||||
uint8_t SPI1_SlaveRecvByte(void)
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data
|
||||
while (!SPI1_GET_FIFO_CNT());
|
||||
return SPI1_GET_FIFO();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_SlaveRecvByte
|
||||
*
|
||||
* @brief Slave mode, send one byte of data
|
||||
*
|
||||
* @param data: data will be sent
|
||||
*
|
||||
* @return send data
|
||||
**/
|
||||
void SPI1_SlaveSendByte(uint8_t data)
|
||||
{
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set to output mode, send data
|
||||
SPI1_SET_FIFO(data);
|
||||
SPI1_SET_TOTAL_CNT(1);
|
||||
while (SPI1_GET_FIFO_CNT());
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_SlaveRecv
|
||||
*
|
||||
* @brief Slave mode, receive multi-byte data
|
||||
*
|
||||
* @param pbuf: Receive data storage starting address
|
||||
*
|
||||
* @return 0/1 0 means receive failed,1 means receive success.
|
||||
**/
|
||||
uint8_t SPI1_SlaveRecv(uint8_t *pbuf, uint16_t len, uint16_t timeouts)
|
||||
{
|
||||
uint16_t revlen;
|
||||
|
||||
revlen = len;
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data
|
||||
SPI1_SET_TOTAL_CNT(revlen); // Assign a value to the SPI send and receive data total length register
|
||||
while (revlen && timeouts)
|
||||
{
|
||||
if (!(timeouts & SPI_MAX_DELAY))
|
||||
{
|
||||
delay();
|
||||
timeouts--;
|
||||
}
|
||||
if (SPI1_GET_FIFO_CNT()) // Byte count in the current FIFO
|
||||
{
|
||||
*pbuf = SPI1_GET_FIFO();
|
||||
pbuf++;
|
||||
revlen--;
|
||||
}
|
||||
}
|
||||
if (!revlen)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn SPI1_SlaveTrans
|
||||
*
|
||||
* @brief Slave mode, send multi-byte data
|
||||
*
|
||||
* @param pbuf: The first address of the data content to be sent
|
||||
*
|
||||
* @return 0/1 0 means receive failed,1 means receive success.
|
||||
*/
|
||||
uint8_t SPI1_SlaveTrans(uint8_t *pbuf, uint16_t len, uint16_t timeouts)
|
||||
{
|
||||
uint16_t sendlen;
|
||||
|
||||
sendlen = len;
|
||||
SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output
|
||||
SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent
|
||||
while (sendlen)
|
||||
{
|
||||
if (!(timeouts & SPI_MAX_DELAY))
|
||||
{
|
||||
delay();
|
||||
timeouts--;
|
||||
}
|
||||
if (SPI1_GET_FIFO_CNT() < SPI1_FIFO_SIZE) // Compare the byte count size in the current FIFO
|
||||
{
|
||||
SPI1_SET_FIFO(*pbuf);
|
||||
pbuf++;
|
||||
sendlen--;
|
||||
}
|
||||
}
|
||||
if (!sendlen)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
377
Peripheral/src/ch564_tim.c
Normal file
377
Peripheral/src/ch564_tim.c
Normal file
@@ -0,0 +1,377 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_tim.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the TIM firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_tim.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR0_TimerInit
|
||||
*
|
||||
* @brief Counting Function on TIM PeriPheral
|
||||
*
|
||||
* @param arr - the Most End Value counting to
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR0_TimerInit(uint32_t arr)
|
||||
{
|
||||
R32_TMR0_CNT_END = arr;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR1_TimerInit
|
||||
*
|
||||
* @brief Counting Function on TIM PeriPheral
|
||||
*
|
||||
* @param arr - the Most End Value counting to
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR1_TimerInit(uint32_t arr)
|
||||
{
|
||||
R32_TMR1_CNT_END = arr;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR2_TimerInit
|
||||
*
|
||||
* @brief Counting Function on TIM PeriPheral
|
||||
*
|
||||
* @param arr - the Most End Value counting to
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR2_TimerInit(uint32_t arr)
|
||||
{
|
||||
R32_TMR2_CNT_END = arr;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR3_TimerInit
|
||||
*
|
||||
* @brief Counting Function on TIM PeriPheral
|
||||
*
|
||||
* @param arr - the Most End Value counting to
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR3_TimerInit(uint32_t arr)
|
||||
{
|
||||
R32_TMR3_CNT_END = arr;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR3_EXTSignalCounterInit
|
||||
*
|
||||
* @brief external signal count
|
||||
*
|
||||
* @param arr - the most end value contting to
|
||||
* capedge - capture edge
|
||||
* CAP_NULL
|
||||
* Edge_To_Edge
|
||||
* FallEdge_To_FallEdge
|
||||
* RiseEdge_To_RiseEdge
|
||||
* capwidth - the shortest width can be captured
|
||||
* clock16 = 0,
|
||||
* clock8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR3_EXTSignalCounterInit(uint32_t arr, CapModeTypeDef capedge, CapWidthTypedef capwidth)
|
||||
{
|
||||
R32_TMR3_CNT_END = arr;
|
||||
R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR;
|
||||
R8_TMR3_CTRL_MOD = RB_TMR3_MODE_COUNT;
|
||||
R8_TMR3_CTRL_MOD &= ~(0x03 << 6);
|
||||
R8_TMR3_CTRL_MOD |= (capedge << 6);
|
||||
R8_TMR3_CTRL_MOD &= ~(0x01 << 4);
|
||||
R8_TMR3_CTRL_MOD |= (capwidth << 4);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR0_PWMInit
|
||||
*
|
||||
* @brief PWM Output Init
|
||||
*
|
||||
* @param polarities - PWM output polarity
|
||||
* high_on_low
|
||||
* low_on_high
|
||||
* repeattime - Number of repetitions of PWM
|
||||
* PWM_Times_1
|
||||
* PWM_Times_4
|
||||
* PWM_Times_8
|
||||
* PWM_Times_16
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR0_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6);
|
||||
R8_TMR0_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/********** *********************************************************************
|
||||
* @fn TMR1_PWMInit
|
||||
*
|
||||
* @brief PWM Output Init
|
||||
*
|
||||
* @param polarities - PWM output polarity
|
||||
* high_on_low
|
||||
* low_on_high
|
||||
* repeattime - Number of repetitions of PWM
|
||||
* PWM_Times_1
|
||||
* PWM_Times_4
|
||||
* PWM_Times_8
|
||||
* PWM_Times_16
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR1_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6);
|
||||
R8_TMR1_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR2_PWMInit
|
||||
*
|
||||
* @brief PWM Output Init
|
||||
*
|
||||
* @param polarities - PWM output polarity
|
||||
* high_on_low
|
||||
* low_on_high
|
||||
* repeattime - Number of repetitions of PWM
|
||||
* PWM_Times_1
|
||||
* PWM_Times_4
|
||||
* PWM_Times_8
|
||||
* PWM_Times_16
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR2_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6);
|
||||
R8_TMR2_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/********** *********************************************************************
|
||||
* @fn TMR3_PWMInit
|
||||
*
|
||||
* @brief PWM Output Init
|
||||
*
|
||||
* @param polarities - PWM output polarity
|
||||
* high_on_low
|
||||
* low_on_high
|
||||
* repeattime - Number of repetitions of PWM
|
||||
* PWM_Times_1
|
||||
* PWM_Times_4
|
||||
* PWM_Times_8
|
||||
* PWM_Times_16
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR3_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6);
|
||||
R8_TMR3_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR0_CapInit
|
||||
*
|
||||
* @brief Timer capture function initialization
|
||||
*
|
||||
* @param capedge - capture edge
|
||||
* CAP_NULL
|
||||
* Edge_To_Edge
|
||||
* FallEdge_To_FallEdge
|
||||
* RiseEdge_To_RiseEdge
|
||||
* capwidth - the shortest width can be captured
|
||||
* clock16 = 0,
|
||||
* clock8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR0_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4);
|
||||
R8_TMR0_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR1_CapInit
|
||||
*
|
||||
* @brief Timer capture function initialization
|
||||
*
|
||||
* @param capedge - capture edge
|
||||
* CAP_NULL
|
||||
* Edge_To_Edge
|
||||
* FallEdge_To_FallEdge
|
||||
* RiseEdge_To_RiseEdge
|
||||
* capwidth - the shortest width can be captured
|
||||
* clock16 = 0,
|
||||
* clock8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR1_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4);
|
||||
R8_TMR1_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR2_CapInit
|
||||
*
|
||||
* @brief Timer capture function initialization
|
||||
*
|
||||
* @param capedge - capture edge
|
||||
* CAP_NULL
|
||||
* Edge_To_Edge
|
||||
* FallEdge_To_FallEdge
|
||||
* RiseEdge_To_RiseEdge
|
||||
* capwidth - the shortest width can be captured
|
||||
* clock16 = 0,
|
||||
* clock8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR2_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4);
|
||||
R8_TMR2_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR3_CapInit
|
||||
*
|
||||
* @brief Timer capture function initialization
|
||||
*
|
||||
* @param capedge - capture edge
|
||||
* CAP_NULL
|
||||
* Edge_To_Edge
|
||||
* FallEdge_To_FallEdge
|
||||
* RiseEdge_To_RiseEdge
|
||||
* capwidth - the shortest width can be captured
|
||||
* clock16 = 0,
|
||||
* clock8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void TMR3_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt)
|
||||
{
|
||||
uint8_t tmp = 0;
|
||||
tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4);
|
||||
R8_TMR3_CTRL_MOD = tmp;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR0_DMACfg
|
||||
*
|
||||
* @brief TMR DMA Configuration
|
||||
*
|
||||
* @param NewSTA
|
||||
* - ENABLE/DISABLE
|
||||
* startAddr
|
||||
* - DMA start address
|
||||
* endAddr
|
||||
* - DMA end address
|
||||
* DMAMode
|
||||
* - DMA mode
|
||||
* @return none
|
||||
**/
|
||||
void TMR0_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode)
|
||||
{
|
||||
if (NewSTA == DISABLE)
|
||||
{
|
||||
R8_TMR0_CTRL_DMA = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
TMR0_DMA_SET_RANGE(startAddr, endAddr);
|
||||
if (DMAMode & Mode_LOOP)
|
||||
R8_TMR0_CTRL_DMA |= RB_TMR_DMA_LOOP;
|
||||
if (DMAMode & Mode_Burst)
|
||||
R8_TMR0_CTRL_DMA |= RB_TMR_DMA_BURST;
|
||||
R8_TMR0_CTRL_DMA |= RB_TMR_DMA_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR1_DMACfg
|
||||
*
|
||||
* @brief TMR DMA Configuration
|
||||
*
|
||||
* @param NewSTA
|
||||
* - ENABLE/DISABLE
|
||||
* startAddr
|
||||
* - DMA start address
|
||||
* endAddr
|
||||
* - DMA end address
|
||||
* DMAMode
|
||||
* - DMA mode
|
||||
* @return none
|
||||
**/
|
||||
void TMR1_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode)
|
||||
{
|
||||
if (NewSTA == DISABLE)
|
||||
{
|
||||
R8_TMR1_CTRL_DMA = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
TMR1_DMA_SET_RANGE(startAddr, endAddr);
|
||||
if (DMAMode & Mode_LOOP)
|
||||
R8_TMR1_CTRL_DMA |= RB_TMR_DMA_LOOP;
|
||||
if (DMAMode & Mode_Burst)
|
||||
R8_TMR1_CTRL_DMA |= RB_TMR_DMA_BURST;
|
||||
R8_TMR1_CTRL_DMA |= RB_TMR_DMA_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn TMR2_DMACfg
|
||||
*
|
||||
* @brief TMR DMA Configuration
|
||||
*
|
||||
* @param NewSTA
|
||||
* - ENABLE/DISABLE
|
||||
* startAddr
|
||||
* - DMA start address
|
||||
* endAddr
|
||||
* - DMA end address
|
||||
* DMAMode
|
||||
* - DMA mode
|
||||
* @return none
|
||||
**/
|
||||
|
||||
void TMR2_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode)
|
||||
{
|
||||
if (NewSTA == DISABLE)
|
||||
{
|
||||
R8_TMR2_CTRL_DMA = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
TMR2_DMA_SET_RANGE(startAddr, endAddr);
|
||||
if (DMAMode & Mode_LOOP)
|
||||
R8_TMR2_CTRL_DMA |= RB_TMR_DMA_LOOP;
|
||||
if (DMAMode & Mode_Burst)
|
||||
R8_TMR2_CTRL_DMA |= RB_TMR_DMA_BURST;
|
||||
R8_TMR2_CTRL_DMA |= RB_TMR_DMA_ENABLE;
|
||||
}
|
||||
}
|
||||
843
Peripheral/src/ch564_uart.c
Normal file
843
Peripheral/src/ch564_uart.c
Normal file
@@ -0,0 +1,843 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_uart.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the UART firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_uart.h"
|
||||
#include "debug.h"
|
||||
|
||||
static uint8_t Best_DIV;
|
||||
/******************************************************************************
|
||||
* @fn Less_Loss_DIV_Calcu
|
||||
*
|
||||
* @brief Caculate the most fit DIV value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void Less_Loss_DIV_Calcu(uint64_t targetbaud)
|
||||
{
|
||||
uint64_t extranum, result_keeper = 1;
|
||||
extranum = targetbaud;
|
||||
for (unsigned int i = 1; i < 128; i++)
|
||||
{
|
||||
if (!((SystemCoreClock * 2 / 16 / i) * 2 / targetbaud))
|
||||
break;
|
||||
long tmpextra = (SystemCoreClock * 2 / 16 / i) % targetbaud;
|
||||
tmpextra = tmpextra > targetbaud / 2 ? targetbaud - tmpextra : tmpextra;
|
||||
|
||||
if (tmpextra < extranum)
|
||||
{
|
||||
result_keeper = i;
|
||||
extranum = tmpextra;
|
||||
}
|
||||
}
|
||||
Best_DIV = result_keeper;
|
||||
}
|
||||
/******************************************************************************
|
||||
* @fn UART0_DefInit
|
||||
*
|
||||
* @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data
|
||||
* length setting, baud rate and frequency division coefficient
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_DefInit(void)
|
||||
{
|
||||
|
||||
UART0_BaudRateCfg(115200);
|
||||
R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 14 bytes
|
||||
R8_UART0_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART0_IER = RB_IER_TXD_EN;
|
||||
R8_UART0_MCR = RB_MCR_OUT1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_DefInit
|
||||
*
|
||||
* @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data
|
||||
*length setting, baud rate and frequency division coefficient
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void UART1_DefInit(void)
|
||||
{
|
||||
UART1_BaudRateCfg(115200);
|
||||
R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART1_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART1_IER = RB_IER_TXD_EN;
|
||||
R8_UART1_MCR = RB_MCR_OUT1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_DefInit
|
||||
*
|
||||
* @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data
|
||||
* length setting, baud rate and frequency division coefficient
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART2_DefInit(void)
|
||||
{
|
||||
|
||||
UART2_BaudRateCfg(115200);
|
||||
R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART2_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART2_IER = RB_IER_TXD_EN;
|
||||
R8_UART2_MCR = RB_MCR_OUT1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_DefInit
|
||||
*
|
||||
* @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data
|
||||
* length setting, baud rate and frequency division coefficient
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART3_DefInit(void)
|
||||
{
|
||||
UART3_BaudRateCfg(115200);
|
||||
R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN;
|
||||
// FIFO open, trigger point 14 bytes
|
||||
R8_UART3_LCR = RB_LCR_WORD_SZ;
|
||||
R8_UART3_IER = RB_IER_TXD_EN;
|
||||
R8_UART3_MCR = RB_MCR_OUT1;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_BaudRateCfg
|
||||
*
|
||||
* @brief Serial port baud rate configuration
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_BaudRateCfg(uint32_t baudrate)
|
||||
{
|
||||
uint64_t x;
|
||||
Less_Loss_DIV_Calcu(baudrate);
|
||||
x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate;
|
||||
x += 5;
|
||||
x /= 10;
|
||||
x = x == 0 ? 1 : x;
|
||||
R8_UART0_LCR |= RB_LCR_DLAB;
|
||||
UART0_SET_DLV(Best_DIV);
|
||||
R8_UART0_DLM = x >> 8;
|
||||
R8_UART0_DLL = x;
|
||||
R8_UART0_LCR &= ~RB_LCR_DLAB;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_BaudRateCfg
|
||||
*
|
||||
* @brief Serial port baud rate configuration
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART1_BaudRateCfg(uint32_t baudrate)
|
||||
{
|
||||
uint64_t x;
|
||||
Less_Loss_DIV_Calcu(baudrate);
|
||||
x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate;
|
||||
x += 5;
|
||||
x /= 10;
|
||||
x = x == 0 ? 1 : x;
|
||||
R8_UART1_LCR |= RB_LCR_DLAB;
|
||||
UART1_SET_DLV(Best_DIV);
|
||||
R8_UART1_DLM = x >> 8;
|
||||
R8_UART1_DLL = x;
|
||||
R8_UART1_LCR &= ~RB_LCR_DLAB;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_BaudRateCfg
|
||||
*
|
||||
* @brief Serial port baud rate configuration
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART2_BaudRateCfg(uint32_t baudrate)
|
||||
{
|
||||
uint64_t x;
|
||||
Less_Loss_DIV_Calcu(baudrate);
|
||||
x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate;
|
||||
x += 5;
|
||||
x /= 10;
|
||||
x = x == 0 ? 1 : x;
|
||||
R8_UART2_LCR |= RB_LCR_DLAB;
|
||||
UART2_SET_DLV(Best_DIV);
|
||||
R8_UART2_DLM = x >> 8;
|
||||
R8_UART2_DLL = x;
|
||||
R8_UART2_LCR &= ~RB_LCR_DLAB;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_BaudRateCfg
|
||||
*
|
||||
* @brief Serial port baud rate configuration
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART3_BaudRateCfg(uint32_t baudrate)
|
||||
{
|
||||
uint64_t x;
|
||||
Less_Loss_DIV_Calcu(baudrate);
|
||||
x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate;
|
||||
x += 5;
|
||||
x /= 10;
|
||||
x = x == 0 ? 1 : x;
|
||||
R8_UART3_LCR |= RB_LCR_DLAB;
|
||||
UART3_SET_DLV(Best_DIV);
|
||||
R8_UART3_DLM = x >> 8;
|
||||
R8_UART3_DLL = x;
|
||||
R8_UART3_LCR &= ~RB_LCR_DLAB;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_ByteTrigCfg
|
||||
*
|
||||
* @brief Serial byte trigger interrupt configuration
|
||||
*
|
||||
* @param UARTByteTRIG - trigger bytes
|
||||
* refer to UARTByteTRIGTypeDef
|
||||
* @return none
|
||||
*/
|
||||
void UART0_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG)
|
||||
{
|
||||
R8_UART0_FCR = (R8_UART0_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_ByteTrigCfg
|
||||
*
|
||||
* @brief Serial byte trigger interrupt configuration
|
||||
*
|
||||
* @param UARTByteTRIG - trigger bytes
|
||||
* refer to UARTByteTRIGTypeDef
|
||||
* @return none
|
||||
**/
|
||||
void UART1_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG)
|
||||
{
|
||||
R8_UART1_FCR = (R8_UART1_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_ByteTrigCfg
|
||||
*
|
||||
* @brief Serial byte trigger interrupt configuration
|
||||
*
|
||||
* @param UARTByteTRIG - trigger bytes
|
||||
* refer to UARTByteTRIGTypeDef
|
||||
* @return none
|
||||
*/
|
||||
void UART2_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG)
|
||||
{
|
||||
R8_UART2_FCR = (R8_UART2_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_ByteTrigCfg
|
||||
*
|
||||
* @brief Serial byte trigger interrupt configuration
|
||||
*
|
||||
* @param UARTByteTRIG - trigger bytes
|
||||
* refer to UARTByteTRIGTypeDef
|
||||
* @return none
|
||||
***/
|
||||
void UART3_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG)
|
||||
{
|
||||
R8_UART3_FCR = (R8_UART3_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_INTCfg
|
||||
*
|
||||
* @brief Serial port interrupt configuration
|
||||
*
|
||||
* @param NewSTA - interrupt control status
|
||||
* ENABLE - Enable the corresponding interrupt
|
||||
* DISABLE - Disable the corresponding interrupt
|
||||
* @param RB_IER - interrupt type
|
||||
* RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only)
|
||||
* RB_IER_LINE_STAT - Receive Line Status Interrupt
|
||||
* RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt
|
||||
* RB_IER_RECV_RDY - receive data interrupt
|
||||
* @return none
|
||||
**/
|
||||
void UART0_INTCfg(FunctionalState NewSTA, uint8_t RB_IER)
|
||||
{
|
||||
if (NewSTA)
|
||||
{
|
||||
R8_UART0_IER |= RB_IER;
|
||||
|
||||
R8_UART0_MCR |= RB_MCR_OUT2;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_UART0_IER &= ~RB_IER;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_INTCfg
|
||||
*
|
||||
* @brief Serial port interrupt configuration
|
||||
*
|
||||
* @param NewSTA - interrupt control status
|
||||
* ENABLE - Enable the corresponding interrupt
|
||||
* DISABLE - Disable the corresponding interrupt
|
||||
* @param RB_IER - interrupt type
|
||||
* RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only)
|
||||
* RB_IER_LINE_STAT - Receive Line Status Interrupt
|
||||
* RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt
|
||||
* RB_IER_RECV_RDY - receive data interrupt
|
||||
* @return none
|
||||
**/
|
||||
void UART1_INTCfg(FunctionalState NewSTA, uint8_t RB_IER)
|
||||
{
|
||||
if (NewSTA)
|
||||
{
|
||||
R8_UART1_IER |= RB_IER;
|
||||
R8_UART1_MCR |= RB_MCR_OUT2;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_UART1_IER &= ~RB_IER;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_INTCfg
|
||||
*
|
||||
* @brief Serial port interrupt configuration
|
||||
*
|
||||
* @param NewSTA - interrupt control status
|
||||
* ENABLE - Enable the corresponding interrupt
|
||||
* DISABLE - Disable the corresponding interrupt
|
||||
* @param RB_IER - interrupt type
|
||||
* RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only)
|
||||
* RB_IER_LINE_STAT - Receive Line Status Interrupt
|
||||
* RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt
|
||||
* RB_IER_RECV_RDY - receive data interrupt
|
||||
* @return none
|
||||
**/
|
||||
void UART2_INTCfg(FunctionalState NewSTA, uint8_t RB_IER)
|
||||
{
|
||||
if (NewSTA)
|
||||
{
|
||||
R8_UART2_IER |= RB_IER;
|
||||
R8_UART2_MCR |= RB_MCR_OUT2;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_UART2_IER &= ~RB_IER;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_INTCfg
|
||||
*
|
||||
* @brief Serial port interrupt configuration
|
||||
*
|
||||
* @param NewSTA - interrupt control status
|
||||
* ENABLE - Enable the corresponding interrupt
|
||||
* DISABLE - Disable the corresponding interrupt
|
||||
* @param RB_IER - interrupt type
|
||||
* RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only)
|
||||
* RB_IER_LINE_STAT - Receive Line Status Interrupt
|
||||
* RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt
|
||||
* RB_IER_RECV_RDY - receive data interrupt
|
||||
* @return none
|
||||
**/
|
||||
void UART3_INTCfg(FunctionalState NewSTA, uint8_t RB_IER)
|
||||
{
|
||||
if (NewSTA)
|
||||
{
|
||||
R8_UART3_IER |= RB_IER;
|
||||
R8_UART3_MCR |= RB_MCR_OUT2;
|
||||
}
|
||||
else
|
||||
{
|
||||
R8_UART3_IER &= ~RB_IER;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_Reset
|
||||
*
|
||||
* @brief Serial port software reset
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void UART0_Reset(void)
|
||||
{
|
||||
R8_UART0_IER = RB_IER_RESET;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_Reset
|
||||
*
|
||||
* @brief Serial port software reset
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void UART1_Reset(void)
|
||||
{
|
||||
R8_UART1_IER = RB_IER_RESET;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_Reset
|
||||
*
|
||||
* @brief Serial port software reset
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void UART2_Reset(void)
|
||||
{
|
||||
R8_UART2_IER = RB_IER_RESET;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_Reset
|
||||
*
|
||||
* @brief Serial port software reset
|
||||
*
|
||||
* @return none
|
||||
**/
|
||||
void UART3_Reset(void)
|
||||
{
|
||||
R8_UART3_IER = RB_IER_RESET;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_SendString
|
||||
*
|
||||
* @brief Serial multi-byte transmission
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART0_SendString(uint8_t *buf, uint16_t length)
|
||||
{
|
||||
uint16_t len = length;
|
||||
uint32_t delay_num = 0;
|
||||
|
||||
while (len)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD>ι<EFBFBD><CEB9>
|
||||
|
||||
if ((R8_UART0_LSR & RB_LSR_TX_FIFO_EMP))
|
||||
{
|
||||
R8_UART0_THR = *buf++;
|
||||
len--;
|
||||
}
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 20000) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_SendString
|
||||
*
|
||||
* @brief Serial multi-byte transmission
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART1_SendString(uint8_t *buf, uint16_t length)
|
||||
{
|
||||
uint16_t len = length;
|
||||
uint32_t delay_num = 0;
|
||||
|
||||
while (len)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD>ι<EFBFBD><CEB9>
|
||||
|
||||
if ((R8_UART1_LSR & RB_LSR_TX_FIFO_EMP))
|
||||
{
|
||||
R8_UART1_THR = *buf++;
|
||||
len--;
|
||||
}
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 20000) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_SendString
|
||||
*
|
||||
* @brief Serial multi-byte transmission
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART2_SendString(uint8_t *buf, uint16_t length)
|
||||
{
|
||||
uint16_t len = length;
|
||||
uint32_t delay_num = 0;
|
||||
|
||||
while (len)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD>ι<EFBFBD><CEB9>
|
||||
|
||||
if ((R8_UART2_LSR & RB_LSR_TX_FIFO_EMP))
|
||||
{
|
||||
R8_UART2_THR = *buf++;
|
||||
len--;
|
||||
}
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 20000) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_SendString
|
||||
*
|
||||
* @brief Serial multi-byte transmission
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART3_SendString(uint8_t *buf, uint16_t length)
|
||||
{
|
||||
uint16_t len = length;
|
||||
uint32_t delay_num = 0;
|
||||
|
||||
while (len)
|
||||
{
|
||||
//<2F><><EFBFBD><EFBFBD>ι<EFBFBD><CEB9>
|
||||
|
||||
if ((R8_UART3_LSR & RB_LSR_TX_FIFO_EMP))
|
||||
{
|
||||
R8_UART3_THR = *buf++;
|
||||
len--;
|
||||
}
|
||||
Delay_Us(1);
|
||||
delay_num++;
|
||||
if(delay_num > 20000) break;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_RecvString
|
||||
*
|
||||
* @brief Serial port read multibyte
|
||||
*
|
||||
* @param buf - The first address of the read data storage buffer
|
||||
*
|
||||
* @return read data length
|
||||
*/
|
||||
uint16_t UART0_RecvString(uint8_t *buf)
|
||||
{
|
||||
uint16_t len = 0;
|
||||
|
||||
if (!((R8_UART0_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR)))
|
||||
{
|
||||
while ((R8_UART0_LSR & RB_LSR_DATA_RDY) == 0)
|
||||
;
|
||||
do
|
||||
{
|
||||
*buf++ = R8_UART0_RBR;
|
||||
len++;
|
||||
} while ((R8_UART0_LSR & RB_LSR_DATA_RDY));
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_RecvString
|
||||
*
|
||||
* @brief Serial port read multibyte
|
||||
*
|
||||
* @param buf - The first address of the read data storage buffer
|
||||
*
|
||||
* @return read data length
|
||||
*/
|
||||
|
||||
uint16_t UART1_RecvString(uint8_t *buf)
|
||||
{
|
||||
uint16_t len = 0;
|
||||
|
||||
if (!((R8_UART1_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR)))
|
||||
{
|
||||
while ((R8_UART1_LSR & RB_LSR_DATA_RDY) == 0)
|
||||
;
|
||||
do
|
||||
{
|
||||
*buf++ = R8_UART1_RBR;
|
||||
len++;
|
||||
} while ((R8_UART1_LSR & RB_LSR_DATA_RDY));
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_RecvString
|
||||
*
|
||||
* @brief Serial port read multibyte
|
||||
*
|
||||
* @param buf - The first address of the read data storage buffer
|
||||
*
|
||||
* @return read data length
|
||||
*/
|
||||
|
||||
uint16_t UART2_RecvString(uint8_t *buf)
|
||||
{
|
||||
uint16_t len = 0;
|
||||
|
||||
if (!((R8_UART2_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR)))
|
||||
{
|
||||
while ((R8_UART2_LSR & RB_LSR_DATA_RDY) == 0)
|
||||
;
|
||||
do
|
||||
{
|
||||
*buf++ = R8_UART2_RBR;
|
||||
len++;
|
||||
} while ((R8_UART2_LSR & RB_LSR_DATA_RDY));
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_RecvString
|
||||
*
|
||||
* @brief Serial port read multibyte
|
||||
*
|
||||
* @param buf - The first address of the read data storage buffer
|
||||
*
|
||||
* @return read data length
|
||||
*/
|
||||
|
||||
uint16_t UART3_RecvString(uint8_t *buf)
|
||||
{
|
||||
uint16_t len = 0;
|
||||
|
||||
if (!((R8_UART3_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR)))
|
||||
{
|
||||
while ((R8_UART3_LSR & RB_LSR_DATA_RDY) == 0)
|
||||
;
|
||||
do
|
||||
{
|
||||
*buf++ = R8_UART3_RBR;
|
||||
len++;
|
||||
} while ((R8_UART3_LSR & RB_LSR_DATA_RDY));
|
||||
}
|
||||
return (len);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_Send_DMA
|
||||
*
|
||||
* @brief Serial multi-byte transmission via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART0_Send_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART0_DMA_SET_RD_RANGE(buf, buf + lenth);
|
||||
UART0_DMACFG(RB_DMA_RD_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART1_Send_DMA
|
||||
*
|
||||
* @brief Serial multi-byte transmission via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART1_Send_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART1_DMA_SET_RD_RANGE(buf, buf + lenth);
|
||||
UART1_DMACFG(RB_DMA_RD_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART2_Send_DMA
|
||||
*
|
||||
* @brief Serial multi-byte transmission via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART2_Send_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART2_DMA_SET_RD_RANGE(buf, buf + lenth);
|
||||
UART2_DMACFG(RB_DMA_RD_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART3_Send_DMA
|
||||
*
|
||||
* @brief Serial multi-byte transmission via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART3_Send_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART3_DMA_SET_RD_RANGE(buf, buf + lenth);
|
||||
UART3_DMACFG(RB_DMA_RD_EN, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_Recv_DMA
|
||||
*
|
||||
* @brief Serial multi-byte receive via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART0_Recv_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART0_DMA_SET_WR_RANGE(buf, buf + lenth);
|
||||
UART0_DMACFG(RB_DMA_WR_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART1_Recv_DMA
|
||||
*
|
||||
* @brief Serial multi-byte receive via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART1_Recv_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART1_DMA_SET_WR_RANGE(buf, buf + lenth);
|
||||
UART1_DMACFG(RB_DMA_WR_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART2_Recv_DMA
|
||||
*
|
||||
* @brief Serial multi-byte receive via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART2_Recv_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART2_DMA_SET_WR_RANGE(buf, buf + lenth);
|
||||
UART2_DMACFG(RB_DMA_WR_EN, ENABLE);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @fn UART3_Recv_DMA
|
||||
*
|
||||
* @brief Serial multi-byte receive via DMA
|
||||
*
|
||||
* @param buf - The first address of the data content to be sent
|
||||
* length - length of data to be sent
|
||||
* @return none
|
||||
*/
|
||||
void UART3_Recv_DMA(uint8_t *buf, uint32_t lenth)
|
||||
{
|
||||
UART3_DMA_SET_WR_RANGE(buf, buf + lenth);
|
||||
UART3_DMACFG(RB_DMA_WR_EN, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_DTRDSR_Cfg
|
||||
*
|
||||
* @brief Enable or disable DTR/DSR function
|
||||
*
|
||||
* @param en - ENABLE/DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_DTRDSR_Cfg (FunctionalState en) {
|
||||
UART0_SET_MCR (RB_MCR_DTR, en);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART0_CTSRTS_Cfg
|
||||
*
|
||||
* @brief Enable or disable CTS/RTS function
|
||||
*
|
||||
* @param en - ENABLE/DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART0_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) {
|
||||
if(GPIOx == GPIOA)
|
||||
UART0_INTCfg (DISABLE, RB_IER_MODEM_IO);
|
||||
else if(GPIOx == GPIOB)
|
||||
UART0_INTCfg (ENABLE, RB_IER_MODEM_IO);
|
||||
UART0_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG);
|
||||
UART0_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART1_CTSRTS_Cfg
|
||||
*
|
||||
* @brief Enable or disable CTS/RTS function
|
||||
*
|
||||
* @param en - ENABLE/DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART1_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) {
|
||||
if(GPIOx == GPIOA)
|
||||
UART1_INTCfg (DISABLE, RB_IER_MODEM_IO);
|
||||
else if(GPIOx == GPIOB)
|
||||
UART1_INTCfg (ENABLE, RB_IER_MODEM_IO);
|
||||
UART1_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG);
|
||||
UART1_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART2_CTSRTS_Cfg
|
||||
*
|
||||
* @brief Enable or disable CTS/RTS function
|
||||
*
|
||||
* @param en - ENABLE/DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART2_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) {
|
||||
if(GPIOx == GPIOA)
|
||||
UART2_INTCfg (DISABLE, RB_IER_MODEM_IO);
|
||||
else if(GPIOx == GPIOB)
|
||||
UART2_INTCfg (ENABLE, RB_IER_MODEM_IO);
|
||||
UART2_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG);
|
||||
UART2_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @fn UART3_CTSRTS_Cfg
|
||||
*
|
||||
* @brief Enable or disable CTS/RTS function
|
||||
*
|
||||
* @param en - ENABLE/DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void UART3_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) {
|
||||
if(GPIOx == GPIOA)
|
||||
UART3_INTCfg (DISABLE, RB_IER_MODEM_IO);
|
||||
else if(GPIOx == GPIOB)
|
||||
UART3_INTCfg (ENABLE, RB_IER_MODEM_IO);
|
||||
UART3_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG);
|
||||
UART3_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE);
|
||||
}
|
||||
62
Peripheral/src/ch564_xbus.c
Normal file
62
Peripheral/src/ch564_xbus.c
Normal file
@@ -0,0 +1,62 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch564_xbus.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : This file provides all the XBUS firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch564_xbus.h"
|
||||
|
||||
/**********************************************************************
|
||||
* @fn XbusInit
|
||||
*
|
||||
* @brief The XbusInit function initializes the Xbus configuration by setting the address bit, enabling or
|
||||
* disabling 32-bit mode, and enabling or disabling the Xbus.
|
||||
*
|
||||
* @param AddrBit The AddrBit parameter is of type XbusOutputADDrBit, which is likely an enumeration or
|
||||
* a typedef for a specific type. It represents the address bit configuration for the Xbus module.
|
||||
* NoOutput No Xbus address output
|
||||
* - AddrNum_6bit PA[5:0] part of address output
|
||||
* - AddrNum_12bit PA[11:0] part of address output
|
||||
* - AddrNum_ALL PA[19:0] part of address output
|
||||
* Bit32En The Bit32En parameter is used to enable or disable the 32-bit mode of the Xbus. If
|
||||
* Bit32En is set to ENABLE, the 32-bit mode is enabled. If Bit32En is set to DISABLE, the 32-bit mode
|
||||
* is disabled.
|
||||
* Stat The "Stat" parameter is used to enable or disable the Xbus. If "Stat" is set to ENABLE,
|
||||
* the Xbus will be enabled. If "Stat" is set to DISABLE, the Xbus will be disabled.
|
||||
*/
|
||||
void XbusInit(XbusOutputADDrBit AddrBit, FunctionalState Bit32En, FunctionalState Stat)
|
||||
{
|
||||
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
R8_XBUS_CONFIG = AddrBit << 2;
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
R8_XBUS_CONFIG |= (Bit32En == ENABLE ? 0 : RB_XBUS_EN_32BIT);
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
R8_XBUS_CONFIG |= (Stat == ENABLE ? 0 : RB_XBUS_ENABLE);
|
||||
RCC_LOCK_SAFE_ACCESS(); /* lock, to prevent unexpected writing */
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* @fn XbusHoldInit
|
||||
*
|
||||
* @brief The function XbusHoldInit initializes the Xbus setup hold time and sets the hold time value based on
|
||||
* the input parameters.
|
||||
*
|
||||
* @param setuptm The parameter "setuptm" is of type XbusSetupTime, which is an enumeration type. It
|
||||
* represents the setup time for the XbusHoldInit function. The possible values for setuptm are:
|
||||
* - Setuptime_1clk 1 clock cycle
|
||||
* - Setuptime_2clk 2 clock cycle
|
||||
* holdtm The holdtm parameter is a uint8_t variable that represents the hold time for the Xbus
|
||||
* setup. It is used to set the R8_XBUS_SETUP_HOLD register.
|
||||
*/
|
||||
void XbusHoldInit(XbusSetupTime setuptm, uint8_t holdtm)
|
||||
{
|
||||
holdtm = holdtm > 0x1f ? 0x1f : holdtm;
|
||||
R8_XBUS_SETUP_HOLD = holdtm;
|
||||
R8_XBUS_SETUP_HOLD |= setuptm == Setuptime_1clk ? 0 : 0x80;
|
||||
}
|
||||
13
Readme.md
Normal file
13
Readme.md
Normal file
@@ -0,0 +1,13 @@
|
||||
BLV-C1P Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><CBB5>
|
||||
|
||||
|
||||
|
||||
<EFBFBD>״<EFBFBD><EFBFBD>ύ
|
||||
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Է<EFBFBD><EFBFBD>֣<EFBFBD>
|
||||
FLASH_ROMA_ERASE <20><> EEPROM_ERASE <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>СΪ4096
|
||||
|
||||
|
||||
2025-07-30
|
||||
Launcher<65><72>ַ <20><>0x00000000 ~ 0x00004000
|
||||
|
||||
240
Startup/startup_ch564_ram_128k.S
Normal file
240
Startup/startup_ch564_ram_128k.S
Normal file
@@ -0,0 +1,240 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_CH564.S
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.0
|
||||
;* Date : 2024/05/05
|
||||
;* Description : vector table for eclipse toolchain for CH564.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init, "ax", @progbits
|
||||
.globl _start
|
||||
.align 2
|
||||
|
||||
_start:
|
||||
.option norvc;
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 2
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0x40000000
|
||||
.word Ecall_M_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Handler
|
||||
.word BreakPoint_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler
|
||||
.word 0
|
||||
.word SW_Handler
|
||||
.word 0
|
||||
/*External Interrupts*/
|
||||
.word I2C_EV_IRQHandler
|
||||
.word I2C_ER_IRQHandler
|
||||
.word ETH_IRQHandler
|
||||
.word USBPD_IRQHandler
|
||||
.word TIM0_IRQHandler
|
||||
.word TIM1_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word SPI0_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word UART0_IRQHandler
|
||||
.word UART1_IRQHandler
|
||||
.word PA_IRQHandler
|
||||
.word PB_IRQHandler
|
||||
.word PD_IRQHandler
|
||||
.word ADC_IRQHandler
|
||||
.word SLV_IRQHandler
|
||||
.word USBHS_HOST_IRQHandler
|
||||
.word USBHS_DEV_IRQHandler
|
||||
.word UART2_IRQHandler
|
||||
.word UART3_IRQHandler
|
||||
.word ETHWakeUp_IRQHandler
|
||||
.word USBHSWakeUp_IRQHandler
|
||||
.word USBPDWakeUp_IRQHandler
|
||||
.word 0x08800513
|
||||
.word 0x80051073
|
||||
.word 0xe000f537
|
||||
.word 0xd1350513
|
||||
.word 0x08000593
|
||||
.word 0x0ff0000f
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler
|
||||
.weak HardFault_Handler
|
||||
.weak Ecall_M_Handler
|
||||
.weak Ecall_U_Handler
|
||||
.weak BreakPoint_Handler
|
||||
.weak SysTick_Handler
|
||||
.weak SW_Handler
|
||||
.weak I2C_EV_IRQHandler
|
||||
.weak I2C_ER_IRQHandler
|
||||
.weak ETH_IRQHandler
|
||||
.weak USBPD_IRQHandler
|
||||
.weak TIM0_IRQHandler
|
||||
.weak TIM1_IRQHandler
|
||||
.weak TIM2_IRQHandler
|
||||
.weak TIM3_IRQHandler
|
||||
.weak SPI0_IRQHandler
|
||||
.weak SPI1_IRQHandler
|
||||
.weak UART0_IRQHandler
|
||||
.weak UART1_IRQHandler
|
||||
.weak PA_IRQHandler
|
||||
.weak PB_IRQHandler
|
||||
.weak PD_IRQHandler
|
||||
.weak ADC_IRQHandler
|
||||
.weak SLV_IRQHandler
|
||||
.weak USBHS_HOST_IRQHandler
|
||||
.weak USBHS_DEV_IRQHandler
|
||||
.weak UART2_IRQHandler
|
||||
.weak UART3_IRQHandler
|
||||
.weak ETHWakeUp_IRQHandler
|
||||
.weak USBHSWakeUp_IRQHandler
|
||||
.weak USBPDWakeUp_IRQHandler
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Handler:
|
||||
Ecall_U_Handler:
|
||||
BreakPoint_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
I2C_EV_IRQHandler:
|
||||
I2C_ER_IRQHandler:
|
||||
ETH_IRQHandler:
|
||||
USBPD_IRQHandler:
|
||||
TIM0_IRQHandler:
|
||||
TIM1_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
SPI0_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
UART0_IRQHandler:
|
||||
UART1_IRQHandler:
|
||||
PA_IRQHandler:
|
||||
PB_IRQHandler:
|
||||
PD_IRQHandler:
|
||||
ADC_IRQHandler:
|
||||
SLV_IRQHandler:
|
||||
USBHS_HOST_IRQHandler:
|
||||
USBHS_DEV_IRQHandler:
|
||||
UART2_IRQHandler:
|
||||
UART3_IRQHandler:
|
||||
ETHWakeUp_IRQHandler:
|
||||
USBHSWakeUp_IRQHandler:
|
||||
USBPDWakeUp_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x1888
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
/*Enable the cache to cache the code from __cache_beg to _cache_end */
|
||||
/* PMP TOR(pmpaddr0 - pmpaddr1) */
|
||||
la t0, _cache_beg
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr0, t0
|
||||
|
||||
la t0, _cache_end
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr1, t0
|
||||
|
||||
li t0, 0x10
|
||||
csrw 0xbc3, t0
|
||||
|
||||
li t0, 0xAD00
|
||||
csrw 0x3a0, t0
|
||||
|
||||
/* Enable ICache */
|
||||
li t0, 0x4
|
||||
csrw 0xbd0, t0
|
||||
li t0, 0x03000002
|
||||
csrc 0xbc2, t0
|
||||
|
||||
/* Comfigure systemclock */
|
||||
jal SystemInit
|
||||
/* Jump main */
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
240
Startup/startup_ch564_ram_64k.S
Normal file
240
Startup/startup_ch564_ram_64k.S
Normal file
@@ -0,0 +1,240 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_CH564.S
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.0
|
||||
;* Date : 2024/05/05
|
||||
;* Description : vector table for eclipse toolchain for CH564.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init, "ax", @progbits
|
||||
.globl _start
|
||||
.align 2
|
||||
|
||||
_start:
|
||||
.option norvc;
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 2
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0x60000000
|
||||
.word Ecall_M_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Handler
|
||||
.word BreakPoint_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler
|
||||
.word 0
|
||||
.word SW_Handler
|
||||
.word 0
|
||||
/*External Interrupts*/
|
||||
.word I2C_EV_IRQHandler
|
||||
.word I2C_ER_IRQHandler
|
||||
.word ETH_IRQHandler
|
||||
.word USBPD_IRQHandler
|
||||
.word TIM0_IRQHandler
|
||||
.word TIM1_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word SPI0_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word UART0_IRQHandler
|
||||
.word UART1_IRQHandler
|
||||
.word PA_IRQHandler
|
||||
.word PB_IRQHandler
|
||||
.word PD_IRQHandler
|
||||
.word ADC_IRQHandler
|
||||
.word SLV_IRQHandler
|
||||
.word USBHS_HOST_IRQHandler
|
||||
.word USBHS_DEV_IRQHandler
|
||||
.word UART2_IRQHandler
|
||||
.word UART3_IRQHandler
|
||||
.word ETHWakeUp_IRQHandler
|
||||
.word USBHSWakeUp_IRQHandler
|
||||
.word USBPDWakeUp_IRQHandler
|
||||
.word 0x08800513
|
||||
.word 0x80051073
|
||||
.word 0xe000f537
|
||||
.word 0xd1350513
|
||||
.word 0x08000593
|
||||
.word 0x0ff0000f
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler
|
||||
.weak HardFault_Handler
|
||||
.weak Ecall_M_Handler
|
||||
.weak Ecall_U_Handler
|
||||
.weak BreakPoint_Handler
|
||||
.weak SysTick_Handler
|
||||
.weak SW_Handler
|
||||
.weak I2C_EV_IRQHandler
|
||||
.weak I2C_ER_IRQHandler
|
||||
.weak ETH_IRQHandler
|
||||
.weak USBPD_IRQHandler
|
||||
.weak TIM0_IRQHandler
|
||||
.weak TIM1_IRQHandler
|
||||
.weak TIM2_IRQHandler
|
||||
.weak TIM3_IRQHandler
|
||||
.weak SPI0_IRQHandler
|
||||
.weak SPI1_IRQHandler
|
||||
.weak UART0_IRQHandler
|
||||
.weak UART1_IRQHandler
|
||||
.weak PA_IRQHandler
|
||||
.weak PB_IRQHandler
|
||||
.weak PD_IRQHandler
|
||||
.weak ADC_IRQHandler
|
||||
.weak SLV_IRQHandler
|
||||
.weak USBHS_HOST_IRQHandler
|
||||
.weak USBHS_DEV_IRQHandler
|
||||
.weak UART2_IRQHandler
|
||||
.weak UART3_IRQHandler
|
||||
.weak ETHWakeUp_IRQHandler
|
||||
.weak USBHSWakeUp_IRQHandler
|
||||
.weak USBPDWakeUp_IRQHandler
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Handler:
|
||||
Ecall_U_Handler:
|
||||
BreakPoint_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
I2C_EV_IRQHandler:
|
||||
I2C_ER_IRQHandler:
|
||||
ETH_IRQHandler:
|
||||
USBPD_IRQHandler:
|
||||
TIM0_IRQHandler:
|
||||
TIM1_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
SPI0_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
UART0_IRQHandler:
|
||||
UART1_IRQHandler:
|
||||
PA_IRQHandler:
|
||||
PB_IRQHandler:
|
||||
PD_IRQHandler:
|
||||
ADC_IRQHandler:
|
||||
SLV_IRQHandler:
|
||||
USBHS_HOST_IRQHandler:
|
||||
USBHS_DEV_IRQHandler:
|
||||
UART2_IRQHandler:
|
||||
UART3_IRQHandler:
|
||||
ETHWakeUp_IRQHandler:
|
||||
USBHSWakeUp_IRQHandler:
|
||||
USBPDWakeUp_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x1888
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
/*Enable the cache to cache the code from __cache_beg to _cache_end */
|
||||
/* PMP TOR(pmpaddr0 - pmpaddr1) */
|
||||
la t0, _cache_beg
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr0, t0
|
||||
|
||||
la t0, _cache_end
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr1, t0
|
||||
|
||||
li t0, 0x10
|
||||
csrw 0xbc3, t0
|
||||
|
||||
li t0, 0xAD00
|
||||
csrw 0x3a0, t0
|
||||
|
||||
/* Enable ICache */
|
||||
li t0, 0x4
|
||||
csrw 0xbd0, t0
|
||||
li t0, 0x03000002
|
||||
csrc 0xbc2, t0
|
||||
|
||||
/* Comfigure systemclock */
|
||||
jal SystemInit
|
||||
/* Jump main */
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
240
Startup/startup_ch564_ram_96k.S
Normal file
240
Startup/startup_ch564_ram_96k.S
Normal file
@@ -0,0 +1,240 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_CH564.S
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.0
|
||||
;* Date : 2024/05/05
|
||||
;* Description : vector table for eclipse toolchain for CH564.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init, "ax", @progbits
|
||||
.globl _start
|
||||
.align 2
|
||||
|
||||
_start:
|
||||
.option norvc;
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 2
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0x50000000
|
||||
.word Ecall_M_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Handler
|
||||
.word BreakPoint_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler
|
||||
.word 0
|
||||
.word SW_Handler
|
||||
.word 0
|
||||
/*External Interrupts*/
|
||||
.word I2C_EV_IRQHandler
|
||||
.word I2C_ER_IRQHandler
|
||||
.word ETH_IRQHandler
|
||||
.word USBPD_IRQHandler
|
||||
.word TIM0_IRQHandler
|
||||
.word TIM1_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word SPI0_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word UART0_IRQHandler
|
||||
.word UART1_IRQHandler
|
||||
.word PA_IRQHandler
|
||||
.word PB_IRQHandler
|
||||
.word PD_IRQHandler
|
||||
.word ADC_IRQHandler
|
||||
.word SLV_IRQHandler
|
||||
.word USBHS_HOST_IRQHandler
|
||||
.word USBHS_DEV_IRQHandler
|
||||
.word UART2_IRQHandler
|
||||
.word UART3_IRQHandler
|
||||
.word ETHWakeUp_IRQHandler
|
||||
.word USBHSWakeUp_IRQHandler
|
||||
.word USBPDWakeUp_IRQHandler
|
||||
.word 0x08800513
|
||||
.word 0x80051073
|
||||
.word 0xe000f537
|
||||
.word 0xd1350513
|
||||
.word 0x08000593
|
||||
.word 0x0ff0000f
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
.word 0x00b50023
|
||||
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler
|
||||
.weak HardFault_Handler
|
||||
.weak Ecall_M_Handler
|
||||
.weak Ecall_U_Handler
|
||||
.weak BreakPoint_Handler
|
||||
.weak SysTick_Handler
|
||||
.weak SW_Handler
|
||||
.weak I2C_EV_IRQHandler
|
||||
.weak I2C_ER_IRQHandler
|
||||
.weak ETH_IRQHandler
|
||||
.weak USBPD_IRQHandler
|
||||
.weak TIM0_IRQHandler
|
||||
.weak TIM1_IRQHandler
|
||||
.weak TIM2_IRQHandler
|
||||
.weak TIM3_IRQHandler
|
||||
.weak SPI0_IRQHandler
|
||||
.weak SPI1_IRQHandler
|
||||
.weak UART0_IRQHandler
|
||||
.weak UART1_IRQHandler
|
||||
.weak PA_IRQHandler
|
||||
.weak PB_IRQHandler
|
||||
.weak PD_IRQHandler
|
||||
.weak ADC_IRQHandler
|
||||
.weak SLV_IRQHandler
|
||||
.weak USBHS_HOST_IRQHandler
|
||||
.weak USBHS_DEV_IRQHandler
|
||||
.weak UART2_IRQHandler
|
||||
.weak UART3_IRQHandler
|
||||
.weak ETHWakeUp_IRQHandler
|
||||
.weak USBHSWakeUp_IRQHandler
|
||||
.weak USBPDWakeUp_IRQHandler
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Handler:
|
||||
Ecall_U_Handler:
|
||||
BreakPoint_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
I2C_EV_IRQHandler:
|
||||
I2C_ER_IRQHandler:
|
||||
ETH_IRQHandler:
|
||||
USBPD_IRQHandler:
|
||||
TIM0_IRQHandler:
|
||||
TIM1_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
SPI0_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
UART0_IRQHandler:
|
||||
UART1_IRQHandler:
|
||||
PA_IRQHandler:
|
||||
PB_IRQHandler:
|
||||
PD_IRQHandler:
|
||||
ADC_IRQHandler:
|
||||
SLV_IRQHandler:
|
||||
USBHS_HOST_IRQHandler:
|
||||
USBHS_DEV_IRQHandler:
|
||||
UART2_IRQHandler:
|
||||
UART3_IRQHandler:
|
||||
ETHWakeUp_IRQHandler:
|
||||
USBHSWakeUp_IRQHandler:
|
||||
USBPDWakeUp_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x1888
|
||||
csrw mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
/*Enable the cache to cache the code from _cache_beg to _cache_end */
|
||||
/* PMP TOR(pmpaddr0 - pmpaddr1) */
|
||||
la t0, _cache_beg
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr0, t0
|
||||
|
||||
la t0, _cache_end
|
||||
srli t0, t0, 2
|
||||
csrw pmpaddr1, t0
|
||||
|
||||
li t0, 0x10
|
||||
csrw 0xbc3, t0
|
||||
|
||||
li t0, 0xAD00
|
||||
csrw 0x3a0, t0
|
||||
|
||||
/* Enable ICache */
|
||||
li t0, 0x4
|
||||
csrw 0xbd0, t0
|
||||
li t0, 0x03000002
|
||||
csrc 0xbc2, t0
|
||||
|
||||
/* Comfigure systemclock */
|
||||
jal SystemInit
|
||||
/* Jump main */
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
40
User/includes.h
Normal file
40
User/includes.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* includes.h
|
||||
*
|
||||
* Created on: May 14, 2025
|
||||
* Author: cc
|
||||
*/
|
||||
|
||||
#ifndef USER_INCLUDES_H_
|
||||
#define USER_INCLUDES_H_
|
||||
|
||||
#include <bootload_fun.h>
|
||||
#include "ch564.h"
|
||||
#include "system_ch564.h"
|
||||
|
||||
#include "debug.h"
|
||||
#include "uart.h"
|
||||
#include "led.h"
|
||||
#include "timer.h"
|
||||
#include "spi_sram.h"
|
||||
#include "spi_flash.h"
|
||||
#include "rw_logging.h"
|
||||
#include "log_api.h"
|
||||
#include "sram_mem_addr.h"
|
||||
#include "flash_mem_addr.h"
|
||||
#include "rtc.h"
|
||||
#include "mcu_flash.h"
|
||||
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƽ<EFBFBD><C6BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
|
||||
<20>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>б<EFBFBD><D0B1>붨<EFBFBD>壬<EFBFBD><E5A3AC><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>̶<EFBFBD>Ӧ<EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD>
|
||||
Boot<6F>л<EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ȡEEPROM<4F>б<EFBFBD><D0B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD>жϵ<D0B6>ǰ<EFBFBD><C7B0>ʲô<CAB2><C3B4><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>EEPROM <20><>û<EFBFBD>б<EFBFBD><D0B1><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ô<EFBFBD><C3B4>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>Boot<6F><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>ַΪ0x00<30><30><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ϊ0x00
|
||||
*/
|
||||
#define Project_Area 0x01 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪBoot<6F><74><EFBFBD><EFBFBD> 0x01:Boot<6F><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0x02:APP<50><50><EFBFBD><EFBFBD>
|
||||
#define Peoject_Name "BLV_C1P_Bootload" //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#define Project_FW_Version 0x01 //<2F><><EFBFBD>̶<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
|
||||
#define Project_Type 0x00 //<2F><><EFBFBD>̶<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD> BootĬ<74><C4AC><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
|
||||
#endif /* USER_INCLUDES_H_ */
|
||||
185
User/main.c
Normal file
185
User/main.c
Normal file
@@ -0,0 +1,185 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : main.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : Main program body.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "includes.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
uint32_t test_tick = 0;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn main
|
||||
*
|
||||
* @brief Main program.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
uint8_t sys_reset = 0;
|
||||
uint32_t wdt_reste_tick = 0;
|
||||
unsigned char Buffer;
|
||||
|
||||
unsigned long DATA_ROM_ADDR;
|
||||
|
||||
SystemCoreClockUpdate(); //ϵͳ<CFB5><CDB3>ʼ<EFBFBD><CABC>
|
||||
Systick_Init();
|
||||
|
||||
UARTx_Init(UART_0,512000);
|
||||
UARTx_Init(UART_1,512000);
|
||||
UARTx_Init(UART_2,512000);
|
||||
UARTx_Init(UART_3,512000);
|
||||
|
||||
SYS_LED_Init();
|
||||
|
||||
SPI_SRAM_Init();
|
||||
|
||||
SPI_FLASH_Init();
|
||||
|
||||
Get_Flash_Size(&Buffer);
|
||||
|
||||
if(Buffer){
|
||||
DATA_ROM_ADDR = 0x70000;
|
||||
}else {
|
||||
DATA_ROM_ADDR = 0x30000;
|
||||
}
|
||||
|
||||
DBG_SYS_Printf("RTC_Init \r\n");
|
||||
|
||||
RTC_Init();
|
||||
|
||||
DBG_SYS_Printf("EEPROM_Init - DATA_ROM_ADDR:%x\r\n",DATA_ROM_ADDR);
|
||||
|
||||
EEPROM_Init();
|
||||
|
||||
DBG_SYS_Printf("G PARA \r\n");
|
||||
|
||||
memset((uint8_t *)&g_app_feature,0,sizeof(G_SYS_FEATURE_T));
|
||||
memset((uint8_t *)&g_mcu_app_feature,0,sizeof(G_SYS_FEATURE_T));
|
||||
memset((uint8_t *)&g_update_recode,0,sizeof(UPDATE_RECORD_T));
|
||||
|
||||
DBG_SYS_Printf("G_SYS_FEATURE_T : %d \r\n",sizeof(G_SYS_FEATURE_T));
|
||||
|
||||
sys_reset = RCC_GET_GLOB_RST_KEEP();
|
||||
if(sys_reset == 0x00)
|
||||
{
|
||||
DBG_SYS_Printf("<EFBFBD>ϵ縴λ \r\n");
|
||||
}else if(sys_reset == 0x02){
|
||||
|
||||
DBG_SYS_Printf("<EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD><EFBFBD><EFBFBD>λ \r\n");
|
||||
}else {
|
||||
DBG_SYS_Printf("<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ \r\n");
|
||||
}
|
||||
|
||||
RCC_SET_GLOB_RST_KEEP(0x01);
|
||||
g_jump_flag = Read_APP_Feature();
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD>õ<EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
|
||||
if(g_jump_flag == 2) {
|
||||
MCU_APP_Write(); //MCU<43><55>Ҫд<D2AA><D0B4>
|
||||
g_jump_flag = 0;
|
||||
|
||||
// printf("Jump APP 1\r\n");
|
||||
//
|
||||
// Delay_Ms(1000);
|
||||
//
|
||||
// __disable_irq();
|
||||
// Jump_APP(g_mcu_app_feature.app_start_addr);
|
||||
|
||||
NVIC_EnableIRQ( Software_IRQn );
|
||||
Delay_Ms( 20 );
|
||||
NVIC_SetPendingIRQ( Software_IRQn );
|
||||
}
|
||||
|
||||
while (1)
|
||||
{
|
||||
SYS_LED_Task();
|
||||
|
||||
Uart0_Task();
|
||||
|
||||
UART1_RECEIVE();
|
||||
UART2_RECEIVE();
|
||||
UART3_RECEIVE();
|
||||
|
||||
RTC_TASK();
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD>õ<EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
|
||||
if(SysTick_1ms - g_Boot_Tick >= 5000)
|
||||
{
|
||||
g_Boot_Tick = SysTick_1ms;
|
||||
|
||||
if(g_jump_flag == 0x00) //APP У<><D0A3><EFBFBD>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD>תAPP
|
||||
{
|
||||
printf("Jump APP 2\r\n");
|
||||
|
||||
Delay_Ms(1000);
|
||||
|
||||
NVIC_EnableIRQ( Software_IRQn );
|
||||
Delay_Ms( 20 );
|
||||
NVIC_SetPendingIRQ( Software_IRQn );
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* MRS_<53><5F><EFBFBD><EFBFBD>HardFault<6C><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˼· : https://www.cnblogs.com/wchmcu/p/17545931.html */
|
||||
uint32_t v_mepc,v_mcause,v_mtval;
|
||||
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"hardfault\n");
|
||||
|
||||
v_mepc = __get_MEPC();
|
||||
v_mcause = __get_MCAUSE();
|
||||
v_mtval = __get_MTVAL();
|
||||
|
||||
printf("boot mepc:%x\n",v_mepc);
|
||||
printf("boot mcause:%x\n",v_mcause);
|
||||
printf("boot mtval:%x\n",v_mtval);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
void SW_Handler(void) {
|
||||
printf("SW_Handler Jump App\r\n");
|
||||
Delay_Ms( 100 );
|
||||
|
||||
__disable_irq();
|
||||
__asm volatile("li a6, 0x07000");
|
||||
__asm volatile("jr a6");
|
||||
while(1);
|
||||
|
||||
}
|
||||
|
||||
420
User/system_ch564.c
Normal file
420
User/system_ch564.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch564.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : CH564 Device Peripheral Access Layer System Source File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "ch564.h"
|
||||
#include "debug.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK)
|
||||
* frequency (after reset the HSI is used as SYSCLK source).
|
||||
*/
|
||||
|
||||
#define SYSCLK_FREQ_120MHz_HSI 120000000
|
||||
//#define SYSCLK_FREQ_80MHz_HSI 80000000
|
||||
//#define SYSCLK_FREQ_60MHz_HSI 60000000
|
||||
//#define SYSCLK_FREQ_40MHz_HSI 40000000
|
||||
//#define SYSCLK_FREQ_20MHz_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_120MHz_HSE 120000000
|
||||
//#define SYSCLK_FREQ_80MHz_HSE 80000000
|
||||
//#define SYSCLK_FREQ_60MHz_HSE 60000000
|
||||
//#define SYSCLK_FREQ_40MHz_HSE 40000000
|
||||
//#define SYSCLK_FREQ_25MHz_HSE HSE_VALUE
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_120MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_80MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_60MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_40MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_20MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_20MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_80MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_60MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_40MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_25MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_25MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#endif
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_120MHz_HSI
|
||||
static void SetSysClockTo120_HSI(void);
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSI
|
||||
static void SetSysClockTo80_HSI(void);
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSI
|
||||
static void SetSysClockTo60_HSI(void);
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSI
|
||||
static void SetSysClockTo40_HSI(void);
|
||||
#elif defined SYSCLK_FREQ_20MHz_HSI
|
||||
static void SetSysClockTo20_HSI(void);
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
static void SetSysClockTo120_HSE(void);
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSE
|
||||
static void SetSysClockTo80_HSE(void);
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSE
|
||||
static void SetSysClockTo60_HSE(void);
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSE
|
||||
static void SetSysClockTo40_HSE(void);
|
||||
#elif defined SYSCLK_FREQ_25MHz_HSE
|
||||
static void SetSysClockTo25_HSE(void);
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash
|
||||
* Interface, update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
if ( SystemCoreClock >= 60000000 )
|
||||
{
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
BITS_CFG( R32_EXTEN_CTLR0 , RB_FLASH_PRE_EN , ENABLE );
|
||||
BITS_CFG( R32_EXTEN_CTLR0 , RB_SW_CFG , DISABLE );
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_UNLOCK_SAFE_ACCESS();
|
||||
BITS_CFG( R32_EXTEN_CTLR0 , RB_FLASH_PRE_EN , DISABLE );
|
||||
BITS_CFG( R32_EXTEN_CTLR0 , RB_SW_CFG , DISABLE );
|
||||
RCC_LOCK_SAFE_ACCESS();
|
||||
}
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
HSI_ON();
|
||||
|
||||
/* Close ETH PHY */
|
||||
RCC_SlpWakeCtrl( RB_SLP_ETH_PWR_DN , DISABLE );
|
||||
Delay_Us( PLL_STARTUP_TIME );
|
||||
ETH->PHY_CR |= ( 1 << 31 );
|
||||
ETH->PHY_CR &= ~( 1 << 30 );
|
||||
ETH->PHY_CR |= ( 1 << 30 );
|
||||
Delay_Us( HSI_STARTUP_TIME );
|
||||
RCC_SlpWakeCtrl( RB_SLP_ETH_PWR_DN , ENABLE );
|
||||
|
||||
CLKSEL_HSI();
|
||||
SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_HSI_HSE );
|
||||
USB_PLL_OFF();
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
if ( R32_EXTEN_CTLR0 & RB_SW )
|
||||
{
|
||||
if ( R32_EXTEN_CTLR1 & RB_CLKSEL )
|
||||
{
|
||||
tmp = HSE_Value;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = HSI_Value;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch ( R32_EXTEN_CTLR0 & RB_USBPLLSRC )
|
||||
{
|
||||
case 0x60:
|
||||
tmp = HSI_Value;
|
||||
break;
|
||||
case 0x20:
|
||||
tmp = HSE_Value;
|
||||
break;
|
||||
default:
|
||||
tmp = HSE_Value * 20 / 25;
|
||||
break;
|
||||
}
|
||||
|
||||
switch ( R32_EXTEN_CTLR0 & RB_USBPLLCLK )
|
||||
{
|
||||
case 0x0:
|
||||
tmp *= 24;
|
||||
break;
|
||||
case 0x4000:
|
||||
tmp *= 20;
|
||||
break;
|
||||
case 0x8000:
|
||||
tmp *= 16;
|
||||
break;
|
||||
case 0xC000:
|
||||
tmp *= 15;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
tmp /= ( R8_PLL_OUT_DIV >> 4 ) + 1;
|
||||
}
|
||||
|
||||
SystemCoreClock = tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
GPIO_IPD_Unused();
|
||||
|
||||
#ifdef SYSCLK_FREQ_120MHz_HSI
|
||||
SetSysClockTo120_HSI();
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSI
|
||||
SetSysClockTo80_HSI();
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSI
|
||||
SetSysClockTo60_HSI();
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSI
|
||||
SetSysClockTo40_HSI();
|
||||
#elif defined SYSCLK_FREQ_20MHz_HSI
|
||||
SetSysClockTo20_HSI();
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
SetSysClockTo120_HSE();
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSE
|
||||
SetSysClockTo80_HSE();
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSE
|
||||
SetSysClockTo60_HSE();
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSE
|
||||
SetSysClockTo40_HSE();
|
||||
#elif defined SYSCLK_FREQ_25MHz_HSE
|
||||
SetSysClockTo25_HSE();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef SYSCLK_FREQ_120MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 120MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSI(void)
|
||||
{
|
||||
RCC_SET_PLL_SYS_OUT_DIV( 0x3 );
|
||||
USB_PLL_MUL_SELECT( USB_PLL_MUL_24 );
|
||||
USB_PLL_SOURCE_SELECT( USB_PLL_SOURCE_HSI );
|
||||
USB_PLL_ON();
|
||||
Delay_Us( PLL_STARTUP_TIME );
|
||||
SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_USBPLL );
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo80_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 80MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo80_HSI(void)
|
||||
{
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0x5);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_HSI);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo60_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 60MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo60_HSI(void)
|
||||
{
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0x7);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_HSI);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo8_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 40MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo40_HSI(void)
|
||||
{
|
||||
RCC_SET_PLL_SYS_OUT_DIV( 0xB );
|
||||
USB_PLL_MUL_SELECT( USB_PLL_MUL_24 );
|
||||
USB_PLL_SOURCE_SELECT( USB_PLL_SOURCE_HSI );
|
||||
USB_PLL_ON();
|
||||
Delay_Us( PLL_STARTUP_TIME );
|
||||
SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_USBPLL );
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_20MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo20_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 20MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo20_HSI(void)
|
||||
{
|
||||
CLKSEL_HSI();
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_HSI_HSE);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_120MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo120_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 24MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo120_HSE(void)
|
||||
{
|
||||
HSE_ON();
|
||||
Delay_Us(HSE_STARTUP_TIME);
|
||||
RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE);
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0x3);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_80MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo80_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 80MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo80_HSE(void)
|
||||
{
|
||||
HSE_ON();
|
||||
Delay_Us(HSE_STARTUP_TIME);
|
||||
RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE);
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0x5);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_60MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo60_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 60MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo60_HSE(void)
|
||||
{
|
||||
HSE_ON();
|
||||
Delay_Us(HSE_STARTUP_TIME);
|
||||
RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE);
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0x7);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_40MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo40_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 40MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo40_HSE(void)
|
||||
{
|
||||
HSE_ON();
|
||||
Delay_Us(HSE_STARTUP_TIME);
|
||||
RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE);
|
||||
RCC_SET_PLL_SYS_OUT_DIV(0xB);
|
||||
USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT);
|
||||
USB_PLL_MUL_SELECT(USB_PLL_MUL_24);
|
||||
USB_PLL_ON();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL);
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_25MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo25_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 25MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo25_HSE(void)
|
||||
{
|
||||
HSE_ON();
|
||||
Delay_Us(HSE_STARTUP_TIME);
|
||||
CLKSEL_HSE();
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
Delay_Init();
|
||||
Delay_Us(PLL_STARTUP_TIME);
|
||||
SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_HSI_HSE);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
30
User/system_ch564.h
Normal file
30
User/system_ch564.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch564.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/05/05
|
||||
* Description : CH564 Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_CH564_H
|
||||
#define __SYSTEM_CH564_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user