Boonlive_RD_Embedded/RCU_C1P_Launcher
7
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

新增：首次提交

Browse Source 
首次提交，上传Launcher工程
This commit is contained in:
caocong
2026-01-05 09:40:42 +08:00
commit 094fd76a72
70 changed files with 20365 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

84
MCU_Driver/inc/bootload_fun.h Normal file
View File

@@ -0,0 +1,84 @@
/*
* launcher_fun.h
*
* Created on: Jul 28, 2025
* Author: cc
*/
#ifndef _BOOTLOAD_FUN_H_
#define _BOOTLOAD_FUN_H_
#include "ch564.h"
#include "uart.h"
#include "mcu_flash.h"
#define BCOMM_CMD_Handshake 0xC0
#define BCOMM_CMD_Jump 0xC1
#define BCOMM_CMD_SetInfo 0xC2
#define BCOMM_CMD_WriteFlash 0xC3
#define BCOMM_CMD_ReadFlash 0xC4
#define BCOMM_CMD_EraseFlash 0xC5
#define BCOMM_CMD_WriteEEPROM 0xC6
#define BCOMM_CMD_ReadEEPROM 0xC7
#define BCOMM_CMD_EraseEEPROM 0xC8
#define BCOMM_CMD_CheckData 0xC9
#define BCOMM_CMD_ReplySUCC 0x00
#define BCOMM_CMD_ReplyFAIL 0x01
#define BCOMM_ParaSize 4096
typedef enum
{
BCOMM_FMT_TXAddr,
BCOMM_FMT_SN,
BCOMM_FMT_TYPE,
BCOMM_FMT_RXAddr,
BCOMM_FMT_LEN_L,
BCOMM_FMT_LEN_H,
BCOMM_FMT_CKS,
BCOMM_FMT_CMD,
BCOMM_FMT_PARAM,
}BOOTLOAD_COMM_FMT_e;
#define UPDATE_RECORD_INFO_Size 0x28
typedef struct {
uint32_t spiflash_fw_count; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_fw_succ; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_fw_fail; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_logic_count; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_logic_succ; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_logic_fail; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_count; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_succ; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_fail; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_failcount; //MCU flash <20>̼<EFBFBD><CCBC><EFBFBD>ǰд<C7B0><D0B4>ʧ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD>θ<EFBFBD><CEB8>¹̼<C2B9><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ü<EFBFBD><C3BC><EFBFBD>
}UPDATE_RECORD_T;
extern G_SYS_FEATURE_T g_app_feature;
extern G_SYS_FEATURE_T g_mcu_app_feature;
extern UPDATE_RECORD_T g_update_recode; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
extern uint8_t g_jump_flag; //<2F><>ת<EFBFBD><D7AA>־λ
extern uint32_t g_Boot_Tick; //Bootʱ<74><CAB1><EFBFBD><EFBFBD> <20><>λ<EFBFBD><CEBB>ms
extern uint32_t g_Boot_Time; //Bootʱ<74><CAB1> <20><>λ<EFBFBD><CEBB>ms
uint16_t CRC16_Check(uint8_t * aStr, uint16_t len);
uint8_t Launcher_Uart_Upgrade_Process(UART_t *g_rev);
uint8_t Read_APP_Feature(void);
uint8_t MCU_APP_Write(void);
uint8_t SPIFLASH_Read_Update_Recode(UPDATE_RECORD_T *info);
uint8_t SPIFLASH_Write_Update_Recode(UPDATE_RECORD_T *info);
void Jump_APP(uint32_t addr);
#endif /* MCU_DRIVER_INC_LAUNCHER_FUN_H_ */

107
MCU_Driver/inc/debug.h Normal file
View File

@@ -0,0 +1,107 @@
/*
* debug.h
*
* Created on: May 14, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_DEBUG_H_
#define MCU_DRIVER_DEBUG_H_
#include "ch564.h"
#include <stdio.h>
/* UART Printf Definition */
#define DEBUG_UART0 1
#define DEBUG_UART1 2
#define DEBUG_UART2 3
#define DEBUG_UART3 4
/* DEBUG log function. DEBUG printf() <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>*/
#ifndef DBG_LOG_EN
#define DBG_LOG_EN 1 //DEBUG LOG <20><><EFBFBD><EFBFBD><EFBFBD>ܿ<EFBFBD><DCBF><EFBFBD>
#endif
#define DBG_Particular_EN 1 //<2F><>ϸ<EFBFBD><CFB8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD> -- <20><><EFBFBD>嵽<EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
#define DBG_NET_LOG_EN 1 //<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ʼ״̬*/
#define DBG_OPT_ActCond_STATUS 1 //<2F><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_MQTT_STATUS 1 //MQTT<54><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_Debug_STATUS 1 //<2F><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_LOGIC_STATUS 1 //<2F>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_DEVICE_STATUS 1 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_NET_STATUS 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
#define DBG_OPT_SYS_STATUS 1 //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ*/
#define DBG_BIT_ActCond_STATUS_bit 6
#define DBG_BIT_MQTT_STATUS_bit 5
#define DBG_BIT_Debug_STATUS_bit 4
#define DBG_BIT_LOGIC_STATUS_bit 3
#define DBG_BIT_DEVICE_STATUS_bit 2
#define DBG_BIT_NET_STATUS_bit 1
#define DBG_BIT_SYS_STATUS_bit 0
#define DBG_BIT_ActCond_STATUS 0x00000040
#define DBG_BIT_MQTT_STATUS 0x00000020
#define DBG_BIT_Debug_STATUS 0x00000010
#define DBG_BIT_LOGIC_STATUS 0x00000008
#define DBG_BIT_DEVICE_STATUS 0x00000004
#define DBG_BIT_NET_STATUS 0x00000002
#define DBG_BIT_SYS_STATUS 0x00000001
extern uint32_t Dbg_Switch;
extern uint32_t SysTick_Now, SysTick_Last, SysTick_Diff;
void Dbg_Println(int DbgOptBit ,const char *fmt, ...);
#if DBG_LOG_EN
#define DBG_Printf(...) printf(__VA_ARGS__)
#define DBG_SYS_Printf(...) Dbg_Println(DBG_BIT_SYS_STATUS,__VA_ARGS__)
//#define DBG_SYS_Printf(...) { \
// if(Dbg_Switch & DBG_BIT_SYS_STATUS){ \
// SysTick_Now = SysTick_1ms; \
// SysTick_Diff = SysTick_Now - SysTick_Last; \
// SysTick_Last = SysTick_Now; \
// printf("%8d [%6d]:",SysTick_Now,SysTick_Diff); \
// printf(__VA_ARGS__);printf("\r\n");}}
#define DBG_Debug_Printf(...) { \
if(Dbg_Switch & DBG_BIT_Debug_STATUS){ \
SysTick_Now = SysTick_1ms; \
SysTick_Diff = SysTick_Now - SysTick_Last; \
SysTick_Last = SysTick_Now; \
printf("%8d [%6d]:",SysTick_Now,SysTick_Diff); \
printf(__VA_ARGS__);printf("\r\n");}}
#define DBG_log(...) {DBG_Printf("%s %s-%d :",__FILE__,__func__,__LINE__);DBG_Printf(__VA_ARGS__);}
#else
#define DBG_Printf(...)
#define DBG_SYS_Printf(...)
#define DBG_Debug_Printf(...)
#define DBG_log(...)
#endif
extern volatile uint32_t SysTick_100us;
extern volatile uint32_t SysTick_1ms;
extern volatile uint32_t SysTick_1s;
void Systick_Init(void);
void Delay_Us(uint32_t n);
void Delay_Ms(uint32_t n);
void my_printf(const char *fmt, ...);
void Dbg_Print_Buff(int DbgOptBit ,const char *cmd ,uint8_t *buff,uint32_t len);
#endif /* MCU_DRIVER_DEBUG_H_ */

34
MCU_Driver/inc/flash_mem_addr.h Normal file
View File

@@ -0,0 +1,34 @@
/*
* flash_mem_addr.h
* Description : <20><><EFBFBD>ļ<EFBFBD>Ϊ<EFBFBD>ⲿFlash <20><>ַӳ<D6B7><D3B3><EFBFBD><EFBFBD> Size: 0x00200000
*
* Created on: Jul 31, 2025
* Author: cc
*/
#ifndef _FLASH_MEM_ADDR_H_
#define _FLASH_MEM_ADDR_H_
/*APP<50><50><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
#define SPIFLASH_APP_Start_Addr 0x00000000
#define SPIFLASH_APP_FEATURE_Addr 0x00000000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 512Byte
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000200 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ - 512Byte
#define SPIFLASH_APP_Data_Start_Addr 0x00004000
#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF
#define SPIFLASH_APP_End_Addr 0x0006FFFF
/*<2A><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
#define SPIFLASH_LOGIC_FILE_Start_Addr 0x00070000
#define SPIFLASH_LOGIC_DataFlag_ADDRESS 0x00070000 //<2F>ļ<EFBFBD><C4BC><EFBFBD>־λ - 4Byte
#define SPIFLASH_LOGIC_DataSize_ADDRESS 0x00070004 //<2F>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> - 4Byte
#define SPIFLASH_LOGIC_DataMD5_ADDRESS 0x00070008 //<2F>ļ<EFBFBD>MD5У<35><D0A3>ֵ - 16Byte
#define SPIFLASH_LOGIC_DataStart_ADDRESS 0x00070200 //<2F>ļ<EFBFBD><C4BC><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define SPIFLASH_LOGIC_FILE_End_Addr 0x000FFFFF
#endif /* MCU_DRIVER_INC_FLASH_MEM_ADDR_H_ */

20
MCU_Driver/inc/led.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* led.h
*
* Created on: May 15, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_LED_H_
#define MCU_DRIVER_INC_LED_H_
#include "ch564.h"
#define SYS_LED_ON GPIOB_ResetBits(GPIO_Pin_12)
#define SYS_LED_OFF GPIOA_SetBits(GPIO_Pin_12)
#define SYS_LED_FLIP GPIOA_InverseBits(GPIO_Pin_12)
void SYS_LED_Init(void);
void SYS_LED_Task(void);
#endif /* MCU_DRIVER_INC_LED_H_ */

86
MCU_Driver/inc/log_api.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* log_api.h
*
* Created on: Jul 29, 2025
* Author: cc
*/
#ifndef _LOG_API_H_
#define _LOG_API_H_
#include "ch564.h"
#include <stdint.h>
#define LogType_Enable 1 //LOGʹ<47><CAB9>
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD>Ͷ<EFBFBD><CDB6><EFBFBD>*/
#define LogType_Launcher 0x01 //Launcher<65><72>Ϣ<EFBFBD><CFA2>¼
#define LogType_SYS_Record 0x02 //ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>¼
#define LogType_Device_COMM 0x03 //<2F>豸ͨѶ<CDA8><D1B6>¼
#define LogType_Device_Online 0x04 //<2F>豸ͨѶ״̬<D7B4><CCAC>¼
#define LogType_Global_Parameters 0x05 //<2F><><EFBFBD><EFBFBD><EFBFBD>豸״̬<D7B4><CCAC><EFBFBD>ڼ<EFBFBD>¼
#define LogType_Net_COMM 0x06 //<2F><><EFBFBD><EFBFBD>ͨѶ<CDA8><D1B6>¼
#define LogType_Logic_Record 0x07 //<2F>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD> - <20><>ʼ״̬*/
#define LogType_Launcher_SWITCH 1
#define LogType_SYS_Record_SWITCH 1
#define LogType_Device_COMM_SWITCH 1
#define LogType_Device_Online_SWITCH 1
#define LogType_Global_Parameters_SWITCH 1
#define LogType_Net_COMM_SWITCH 1
#define LogType_Logic_Record_SWITCH 1
/*<2A><>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD>λ*/
#define LogType_Launcher_bit 0
#define LogType_SYS_Record_bit 1
#define LogType_Device_COMM_bit 2
#define LogType_Device_Online_bit 3
#define LogType_Global_Parameters_bit 4
#define LogType_Net_COMM_bit 5
#define LogType_Logic_Record_bit 6
/*<2A><>־<EFBFBD><D6BE><EFBFBD>ز<EFBFBD><D8B2><EFBFBD>*/
#define LogInfo_Device_Online 0x01 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
#define LogInfo_Device_Offline 0x02 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
typedef enum{
LLauncher_App_Check = 0x01, //У<><D0A3>APP
LLauncher_Read_App, //<2F><>ȡAPP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50><50><EFBFBD><EFBFBD>д<EFBFBD>뵽MCU FLash<73><68>
LLauncher_Write_Flash, //дFlash
LLauncher_Factory_Reset, //<2F>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LLauncher_Reset_Source, //<2F><>λԴ
LLauncher_RCUKey_State, //RCU<43><55><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>¼
}LOGTYPE_Launcher_E;
typedef enum {
LSYS_PHY_Change = 0x01, //PHY״̬<D7B4>仯<EFBFBD><E4BBAF>¼
LSYS_DevInfo_Error, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
LSYS_API_State, //<2F><><EFBFBD><EFBFBD>״̬
LSYS_NET_ARGC, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LSYS_MQTT_ARGC, //MQTT<54><54><EFBFBD><EFBFBD>
LSYS_Server_Comm_State, //<2F>ƶ<EFBFBD>ͨѶ״̬<D7B4><CCAC>¼
LSYS_NET_DefaultARGC, //<2F><><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD>
LSYS_RCUKey_State, //RCU<43><55><EFBFBD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>¼
}LOGTYPR_SYSRecord;
typedef enum{
LCOMM_ASK_TO_Reply = 0x01, //<2F><>ѯ<EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD>
LCOMM_Send_Control, //RCU<43>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LCOMM_Control_Reply, //RCU<43><55><EFBFBD>ƻظ<C6BB><D8B8><EFBFBD><EFBFBD><EFBFBD>
LCOMM_Adjust_Baud, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}LOGTYPE_DEV_COMM;
typedef enum{
LGlobal_Para = 0x01, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
LGlobal_Dev, //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
}LOGTYPE_Global_E;
void LOG_Launcher_APP_Check_Record(uint8_t state);
void LOG_Launcher_Read_App_Record(uint8_t state);
void LOG_Launcher_Write_Flash_Record(uint32_t addr,uint16_t len);
void LOG_Launcher_Factory_Reset_Record(uint8_t state);
void LOG_Launcher_Reset_Source_Record(uint8_t sour);
void LOG_Launcher_RCU_Key_State_Record(uint8_t state);
#endif /* MCU_DRIVER_INC_LOG_API_H_ */

123
MCU_Driver/inc/mcu_flash.h Normal file
View File

@@ -0,0 +1,123 @@
/*
* mcu_flash.h
*
* Created on: Aug 2, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_MCU_FLASH_H_
#define MCU_DRIVER_INC_MCU_FLASH_H_
#include "ch564.h"
#include <stdint.h>
#define MCU_APP_Flash_PageSize 0x00001000 //MCU FlashҳΪ4096Byte
#define APP_Flash_WriteNum 0x05 //APPд<50><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define App_Procedure_Ready 0x66 //APP׼<50><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
#define App_Procedure_Not_Ready 0x44 //Appδ׼<CEB4><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
//MCU Flash Address range(0x0 -- 0x6FFFF) Size(448K)
#define MCU_APP_Flash_Start_Addr 0x00007000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_Start_Addr 0x00007000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_End_Addr 0x00027DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_Addr 0x00027E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_End_Addr 0x00027FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_PageAddr 0x00027000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
#define MCU_APP_Feature_PageOffset 0x00000E00 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
#define APP_FEATURE_SIZE 0x0200 //512Byte
//EEPROM Address range(0x70000 -- 0x77FFF) Size(32K)
#define MCU_EEPROM_Start_Addr 0x00070000
#define MCU_EEPROM_MCUDevInfo_Address 0x00070000 //MCU <20>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2>ַ<EFBFBD>̶<EFBFBD>Ϊ0x00070000<30><30><EFBFBD><EFBFBD>СΪ4096 <20><><EFBFBD><EFBFBD><EFBFBD>򲻿ɸĶ<C9B8>
#define MCU_EEPROM_End_Addr 0x00078000
/* EEPROM <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ<EFBFBD><CABD>
* FLAG - 1Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
* LEN - 2Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
* CHECK - 1Byte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>
* DATA - nByte <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* */
#define EEPROM_SVAE_FLAG 0xAE
#define EEPROM_DATA_Size_Max 0x40 //Ŀǰ<C4BF><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ100Byte
#define EEPROM_PARA_Size 50
#define EEPROM_DEV_NAME_Size 32
#define EEPROM_Offset_SaveFlag 0x00
#define EEPROM_Offset_Datalen 0x01
#define EEPROM_Offset_Check 0x03
#define EEPROM_Offset_Data 0x04
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽṹ<DDBD><E1B9B9>
* ע<>⣺<EFBFBD><E2A3BA><EFBFBD><EFBFBD>risc-v<><76><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD>ֽڶ<D6BD><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD><EFBFBD>Flash/MCU Flash<73>е<EFBFBD>˳<EFBFBD><CBB3><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD>嶨<EFBFBD><E5B6A8>˳<EFBFBD><CBB3><EFBFBD><EFBFBD>һ<EFBFBD>£<EFBFBD>ʹ<EFBFBD><CAB9>ʱ<EFBFBD><CAB1>ע<EFBFBD><D7A2>
* */
typedef enum{
Feature_Check = 0x00, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 512Byte <20><>CRCУ<43><D0A3> - 2Byte
Feature_AppFlag = 0x02, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50>־λ - 1Byte
Feature_AppStart = 0x03, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50>ʼ<EFBFBD><CABC>ַ - 4Byte
Feature_AppEnd = 0x07, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 4Byte
Feature_AppCrcSize = 0x0B, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRC<52>ij<EFBFBD><C4B3><EFBFBD> - 2Byte
Feature_AppCrcLen = 0x0D, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С - 2Byte
Feature_AppFlashCrc = 0x0F, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - APP CRC
}FEATURE_E;
#define APP_Feature_CRC_Size 497
typedef struct{
uint8_t app_flag; //APP <20><>־λ
uint8_t app_crc[APP_Feature_CRC_Size]; //APP CRCУ<43><D0A3>ֵ
uint16_t app_crc_size; //APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
uint16_t app_crc_len; //APP CRCУ<43><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
uint16_t crc_check; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRCֵ - <20><><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7>Ϸ<EFBFBD>
uint32_t app_start_addr; //APP<50><50>ʼ<EFBFBD><CABC>ַ
uint32_t app_end_addr; //APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
}G_SYS_FEATURE_T;
/*<2A><><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU EEPROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
typedef struct{
uint8_t dev_addr; //<2F>豸<EFBFBD><E8B1B8>ַ
uint8_t dev_type; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
uint8_t dev_boot_ver; //<2F>豸Boot<6F><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
uint8_t dev_app_ver; //<2F>豸APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
uint8_t dev_name_len; //<2F>豸<EFBFBD><E8B1B8><EFBFBD>Ƶij<C6B5><C4B3><EFBFBD>
uint8_t dev_name[EEPROM_DEV_NAME_Size]; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
}E_MCU_DEV_INFO;
extern E_MCU_DEV_INFO g_mcu_dev;
extern uint8_t g_read_buff[4100];
extern uint8_t g_flash_buff[4100];
void EEPROM_Init(void);
uint8_t MCU_APP_Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
uint8_t MCU_APP_Flash_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr);
uint8_t MCU_APP_Flash_Erase(uint32_t readAddr,uint16_t NumByteToWrite);
uint8_t MCU_APP_Flash_ALLErase(void);
uint8_t MCU_EEPROM_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
uint8_t MCU_EEPROM_Read(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t readAddr);
uint8_t MCU_EEPROM_Erase(uint32_t readAddr,uint16_t NumByteToWrite);
uint8_t MCU_EEPROM_ALLErase(void);
uint8_t EEPROM_CheckSum(uint8_t *data,uint16_t len);
uint8_t EEPROM_ReadMCUDevInfo(E_MCU_DEV_INFO *info);
uint8_t EEPROM_WriteMCUDevInfo(E_MCU_DEV_INFO *info);
void EEPROM_Default_MCUDevInfo(E_MCU_DEV_INFO *info);
void EEPROM_Validate_MCUDevInfo(E_MCU_DEV_INFO *info);
uint8_t Read_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info);
uint8_t Write_APP_Feature_Info(uint8_t option,G_SYS_FEATURE_T *feature_info);
void APP_Feature_Info_Printf(G_SYS_FEATURE_T *feature_info);
#endif /* MCU_DRIVER_INC_MCU_FLASH_H_ */

42
MCU_Driver/inc/rtc.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* rtc.h
*
* Created on: Jul 29, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_RTC_H_
#define MCU_DRIVER_INC_RTC_H_
#include <stdint.h>
#include "ch564.h"
typedef struct{
uint8_t second;
uint8_t minute;
uint8_t hour;
uint8_t week;
uint8_t day;
uint8_t month;
uint8_t year;
}S_RTC;
typedef struct{
uint32_t hour;
uint16_t minute;
uint16_t second;
}G_CORE_RTC;
extern S_RTC RTC_Raw_Data;
extern uint32_t Log_Time_ms;
void RTC_Init(void);
uint8_t HEX_Conversion_To_DEC(uint8_t c_num);
uint8_t DEV_Conversion_To_HEX(uint8_t c_num);
uint32_t RTC_Conversion_To_Unix(S_RTC *rtc_time);
void Unix_Conversion_To_RTC(S_RTC *rtc_time,uint32_t utc_tick);
uint8_t RTC_ReadDate(S_RTC *psRTC);
uint8_t RTC_WriteDate(S_RTC SetRTC);
void RTC_TASK(void);
#endif /* MCU_DRIVER_INC_RTC_H_ */

41
MCU_Driver/inc/rw_logging.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* rw_logging.h
*
* Created on: Jul 29, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_RW_LOGGING_H_
#define MCU_DRIVER_INC_RW_LOGGING_H_
#include "ch564.h"
#include <stdint.h>
#define APPFlag_UartUpgrade_Reset 0xBBC1 //APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
//<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
#define LOG_Data_Hand 0xA5 //LOG<4F><47><EFBFBD><EFBFBD>ͷ
#define Log_Data_End 0x5A //LOG<4F><47><EFBFBD><EFBFBD>β
#define Log_Data_Len_MAX 512 //<2F><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>512Byte
/*<2A><>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ*/
typedef enum{
S_Log_Hand,
S_Log_SN, //<2F><>־ÿ<D6BE><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>
S_Log_Len,
S_Log_Len_8,
S_Log_Check,
S_Log_Date_H, //<2F>꣺5bit <20>£<EFBFBD>5bit <20>գ<EFBFBD>5bit
S_Log_Date_L,
S_Log_Type,
S_Log_Time8B, //Сʱʱ<CAB1><CAB1><EFBFBD><EFBFBD>
S_Log_Time16B,
S_Log_Time24B,
S_Log_Time32B,
S_Log_Data,
}Sram_Log_Data_Format;
uint8_t Data_CheckSum(uint8_t* data,uint16_t len);
uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len);
#endif /* MCU_DRIVER_INC_RW_LOGGING_H_ */

65
MCU_Driver/inc/spi_flash.h Normal file
View File

@@ -0,0 +1,65 @@
/*
* spi_flash.h
*
* Created on: May 20, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_SPI_FLASH_H_
#define MCU_DRIVER_INC_SPI_FLASH_H_
#include "ch564.h"
#define Flash_CS_H GPIOA_SetBits(GPIO_Pin_11)
#define Flash_CS_L GPIOA_ResetBits(GPIO_Pin_11)
#define Flash_ADDRESS_MAX 0x00200000
/***********ָ<><D6B8><EFBFBD><EFBFBD>**********/
//Read
#define P24Q40H_ReadData 0x03
#define P24Q40H_FastReadData 0x0B
#define P24Q40H_FastReadDual 0x3B
//Program and Erase
#define P24Q40H_PageErase 0x81
#define P24Q40H_SectorErase 0x20
#define P24Q40H_BlockErase 0xD8
#define P24Q40H_ChipErase 0xC7
#define P24Q40H_PageProgram 0x02
//Protection
#define P24Q40H_WriteEnable 0x06
#define P24Q40H_WriteDisable 0x04
//Status Register
#define P24Q40H_ReadStatusReg 0x05
#define P24Q40H_WriteStatusReg 0x01
//Other Commands
#define P24Q40H_PowerDown 0xB9
#define P24Q40H_ReleasePowerDown 0xAB
#define P24Q40H_ReadManufactureID 0x90
#define P24Q40H_ReadDeviceID 0x9F
#define P24Q40H_ResetEnable 0x66
#define P24Q40H_Reset 0x99
extern uint8_t Flash_Buffer[4150];
void SPI_FLASH_Init(void);
uint8_t Flash_ReadSR(void);
void Flash_WriteSR(uint8_t sr_val);
void Flash_Write_Enable(void);
void Flash_Write_Disable(void);
uint16_t Flash_ReadID(void);
uint8_t Flash_Wait_Busy(void);
void Flash_PowerDown(void);
void Flash_Wakeup(void);
void Flash_Erase_Chip(void);
void Flash_Erase_Block(uint32_t BLK_ID);
void Flash_Erase_Sector(uint32_t DST_ID);
void Flash_Erase_Page(uint32_t Page_ID);
void Flash_Erase_Pageaddr(uint32_t Page_addr);
void Flash_Read(uint8_t* pBuffer,uint16_t NumByteToRead,uint32_t ReadAddr);
void Flash_Write_Page(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
void Flash_Write_NoCheck(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr);
void Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t WriteAddr);
#endif /* MCU_DRIVER_INC_SPI_FLASH_H_ */

46
MCU_Driver/inc/spi_sram.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* spi_sram.h
*
* Created on: May 16, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_SPI_SRAM_H_
#define MCU_DRIVER_INC_SPI_SRAM_H_
#include "ch564.h"
#define SRAM_CE_H GPIOA_ResetBits(GPIO_Pin_11)
#define SRAM_CE_L GPIOA_SetBits(GPIO_Pin_11)
#define SRAM_CMD_Read 0x03
#define SRAM_CMD_Fast_Read 0x0B
#define SRAM_CMD_Fast_Read_Quad 0xEB
#define SRAM_CMD_Write 0x02
#define SRAM_CMD_Quad_Write 0x38
#define SRAM_CMD_Enter_Quad_Mode 0x35
#define SRAM_CMD_Exit_Quad_Mode 0xF5
#define SRAM_CMD_Reset_Enable 0x66
#define SRAM_CMD_Reset 0x99
#define SRAM_CMD_Wrap_Boundary_Toggle 0xC0
#define SRAM_CMD_Read_ID 0x9F
#define SRAM_ADDRESS_MAX 0x00800000
void SPI_SRAM_Init(void);
void SRAM_Write_Byte(uint8_t wdate,uint32_t add);
uint8_t SRAM_Read_Byte(uint32_t add);
void SRAM_Write_Word(uint16_t wdate,uint32_t add);
uint16_t SRAM_Read_Word(uint32_t add);
void SRAM_Write_DW(uint32_t wdate,uint32_t add);
uint32_t SRAM_Read_DW(uint32_t add);
uint8_t SRAM_Read_ID_Opeartion(void);
void SRAM_Reset_Operation(void);
void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add);
void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add);
#endif /* MCU_DRIVER_INC_SPI_SRAM_H_ */

33
MCU_Driver/inc/sram_mem_addr.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* sram_virt_mem_addr.h
* <20>ⲿSRAM<41><4D>ַ<EFBFBD>ռ<EFBFBD><D5BC>滮 0x00000000 ~ 0x00800000
*
* Created on: Jul 29, 2025
* Author: cc
*/
#ifndef _SRAM_MEM_ADDR_H_
#define _SRAM_MEM_ADDR_H_
/*
* 2025-07-29 <20>޸<EFBFBD>SRAM<41>洢<EFBFBD><E6B4A2>ַ 0x00400000 ~ 0x007FFFFF SIZE:4MByte
* 1<><31><EFBFBD>޸ĶԿռ<D4BF><D5BC><EFBFBD>ַУ<D6B7>飬<EFBFBD><E9A3AC>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD><EFBFBD>쳣
* 2<><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȥ<EFBFBD><C8A5>û<EFBFBD><C3BB>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD>
*
* */
#define SRAM_LOG_WRITE_Address 0x00400000 //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>ʼ<EFBFBD><CABC>ַ - <20><>ǰSRAM<41><4D><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ - 4Byte
#define SRAM_LOG_READ_Address 0x00400004 //<2F><>־<EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD>ȡ<EFBFBD><C8A1>ַ - 4Byte
#define SRAM_LOG_Serial_Number 0x00400008 //<2F><>־<EFBFBD><D6BE><EFBFBD>ű<EFBFBD><C5B1><EFBFBD><EFBFBD><EFBFBD>ַ - 2Byte Ŀǰֻʹ<D6BB><CAB9>1Byte
#define SRAM_LOGFlag_Reset_Source 0x0040000A //Launcher<65><72><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> - <20><>APPʹ<50><CAB9> - 1Byte
#define SRAM_LOGFlag_Addr_INIT 0x0040000B //Launcher<65><72>¼<EFBFBD><C2BC>ַ<EFBFBD><D6B7>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>־λ - <20><>APPʹ<50><CAB9> - 1Byte
#define SRAM_LOGFlag_Debug_Switch 0x0040000C //Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ 4Byte - <20><>APPʹ<50><CAB9>
#define SRAM_APPFlag_Reset_Source 0x00400010 //App<70><70><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ 2Byte - <20><>Launcher<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣʹ<CFA2><CAB9> 0xBBC1
#define SRAM_LOG_DATA_Address 0x00400100 //<2F><>־<EFBFBD><D6BE><EFBFBD>ݵ<EFBFBD>ַ
#define SRAM_LOG_End_Address 0x007FFFFF //<2F><>־<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - 0x007FFFFF
#endif /* MCU_DRIVER_INC_SRAM_MEM_ADDR_H_ */

20
MCU_Driver/inc/timer.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* timer.h
*
* Created on: May 16, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_TIMER_H_
#define MCU_DRIVER_INC_TIMER_H_
#include "ch564.h"
extern volatile uint32_t Time0_100us;
extern volatile uint32_t Time0_1ms;
void TIMER0_Init(void);
void Timer0_Task(void);
#endif /* MCU_DRIVER_INC_TIMER_H_ */

100
MCU_Driver/inc/uart.h Normal file
View File

@@ -0,0 +1,100 @@
/*
* uart.h
*
* Created on: May 14, 2025
* Author: cc
*/
#ifndef MCU_DRIVER_INC_UART_H_
#define MCU_DRIVER_INC_UART_H_
#include "ch564.h"
#define MCU485_EN1_H GPIOD_SetBits(GPIO_Pin_21)
#define MCU485_EN1_L GPIOD_ResetBits(GPIO_Pin_21)
#define MCU485_EN2_H GPIOB_SetBits(GPIO_Pin_15)
#define MCU485_EN2_L GPIOB_ResetBits(GPIO_Pin_15)
#define UART_COMMBUSY_IDLE_Flag 0x00
#define UART_COMMBUSY_RECV_Flag 0x01
#define UART_COMMBUSY_SEND_Flag 0x02
#define Recv_2400_TimeOut 10 //ms
#define Recv_9600_TimeOut 5 //ms
#define Recv_115200_TimeOut 3 //ms
#define Recv_512000_TimeOut 3 //ms
#define USART_BUFFER_SIZE 512
typedef void (*Uart_prt)(uint8_t * ,uint16_t );
typedef uint8_t (*Uart_set_prt)(uint32_t );
typedef enum
{
UART_0,
UART_1,
UART_2,
UART_3,
UART_MAX,
}UART_IDX;
typedef struct{
uint8_t RecvBuffer[USART_BUFFER_SIZE];
uint8_t deal_buff[USART_BUFFER_SIZE];
uint8_t ackBuffer[USART_BUFFER_SIZE];
uint8_t SendBuffer[USART_BUFFER_SIZE];
uint8_t SendCount; //<2F>ܷ<EFBFBD><DCB7>ʹ<EFBFBD><CDB4><EFBFBD>
uint8_t SendCnt; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD>
uint8_t CommBusy; //ͨѶ<CDA8><D1B6>æ״̬
uint8_t Receiving;
uint8_t sn;
uint8_t pc_addr;
uint8_t cmd;
uint8_t appFlag;
uint8_t writeFlag;
uint8_t ChangeBaudFlag; //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>־λ
uint16_t RecvLen;
uint16_t deal_len;
uint16_t ackLen;
uint16_t SendLen; //<2F><><EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD>
uint32_t CommBaud; //ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <20>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʹ<CAB1><CAB9>
uint32_t ackValidity; //<2F><><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>Ч<EFBFBD><D0A7>
uint32_t SendValidDuration; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1>
uint32_t SendValidTick; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1><EFBFBD><EFBFBD>
uint32_t SendInterval; //<2F><><EFBFBD>ͼ<EFBFBD><CDBC><EFBFBD>
uint32_t SendTick; //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
uint32_t RecvTimeout;
uint32_t RecvIdleTiming;
uint32_t SendIdleTick; //<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
Uart_prt send_data_cf;
Uart_set_prt set_baud_cf;
}UART_t;
extern UART_t g_uart[UART_MAX];
void UARTx_Init(UART_IDX uart_id, uint32_t buad);
void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud);
void UART0_RECEIVE(void);
void UART1_RECEIVE(void);
void UART2_RECEIVE(void);
void UART3_RECEIVE(void);
uint8_t UART0_ChangeBaud(uint32_t baudrate);
uint8_t UART1_ChangeBaud(uint32_t baudrate);
uint8_t UART2_ChangeBaud(uint32_t baudrate);
uint8_t UART3_ChangeBaud(uint32_t baudrate);
void Uart0_Task(void);
#endif /* MCU_DRIVER_INC_UART_H_ */