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新增：串口通讯避障功能

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​ 1、Launcher中的串口只使用串口0(调试串口)、串口2(主动RS485端口)；串口1与串口3不使用，且不初始化。将串口通讯缓冲区修改为1100Byte。

​  目的：CH564由于将Launcher代码搬运到RAM中运行，因此可使用的变量大小只有32Kbyte。不使用的串口将不初始化，同时使用的通讯缓冲区将节约出来，否则RAM空间不够使用。

​ 2、串口2 - 增加RS485使能，同时通讯增加避障功能。
This commit is contained in:
caocong
2026-01-19 16:39:22 +08:00
parent 094fd76a72
commit 5e9338cee4
37 changed files with 37088 additions and 289 deletions
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26
MCU_Driver/inc/bootload_fun.h
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@@ -48,24 +48,25 @@ typedef enum
typedef struct {
uint32_t spiflash_fw_count; //<2F>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><EFBFBD><EFBFBD>
uint32_t spiflash_fw_succ; //<EFBFBD>ⲿflash <20>̼<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>ɹ<EFBFBD><EFBFBD>ܴ<EFBFBD><EFBFBD><EFBFBD>
uint32_t spiflash_fw_fail; //<EFBFBD>ⲿflash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><EFBFBD><EFBFBD>
uint32_t spiflash_logic_count; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_logic_succ; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t spiflash_logic_fail; //<2F>ⲿflash <20><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
/* - Ŀǰ<C4BF><C7B0>ϸ<EFBFBD><CFB8><EFBFBD><EFBFBD>һ<EFBFBD>£<EFBFBD><C2A3>ⲿ<EFBFBD><E2B2BF>Flashд<68><D0B4><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>¼<EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϼ<EFBFBD>¼<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* - Launcher<65>п<EFBFBD><D0BF><EFBFBD><EFBFBD><EFBFBD>MCU Flash д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>ƣ<EFBFBD><C6A3><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>ⲿFlash<EFBFBD>а<EFBFBD><EFBFBD>˵ĵ<EFBFBD>MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><EFBFBD>Launcher<EFBFBD>н<EFBFBD><EFBFBD>в<EFBFBD><EFBFBD><EFBFBD>
* - <20><><EFBFBD><EFBFBD><EFBFBD>ⲿFlash<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><EFBFBD> APP<50><50>Ҳ<EFBFBD>ǿ<EFBFBD><C7BF><EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>ġ<EFBFBD>
* - <20>ݲ<EFBFBD><DDB2><EFBFBD>Ҫ<EFBFBD>ⲿFlash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ͳ<EFBFBD><CDB3>
*
*
* */
uint32_t mcuflash_fw_count; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_succ; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ɹ<EFBFBD><C9B9>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_fail; //MCU flash <20>̼<EFBFBD>д<EFBFBD><D0B4>ʧ<EFBFBD><CAA7><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>
uint32_t mcuflash_fw_failcount; //MCU flash <20>̼<EFBFBD><CCBC><EFBFBD>ǰд<C7B0><D0B4>ʧ<EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD>θ<EFBFBD><CEB8>¹̼<C2B9><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ü<EFBFBD><C3BC><EFBFBD>
}UPDATE_RECORD_T;
extern G_SYS_FEATURE_T g_app_feature;
extern G_SYS_FEATURE_T g_mcu_app_feature;
extern UPDATE_RECORD_T g_update_recode; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
extern G_SYS_FEATURE_T g_app_feature; //SPI Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
extern G_SYS_FEATURE_T g_mcu_app_feature; //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
extern G_SYS_FEATURE_T g_update_flag; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
extern UPDATE_RECORD_T g_update_recode; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
extern uint8_t g_jump_flag; //<2F><>ת<EFBFBD><D7AA>־λ
extern uint32_t g_Boot_Tick; //Bootʱ<74><CAB1><EFBFBD><EFBFBD> <20><>λ<EFBFBD><CEBB>ms
@@ -78,7 +79,8 @@ uint8_t Read_APP_Feature(void);
uint8_t MCU_APP_Write(void);
uint8_t SPIFLASH_Read_Update_Recode(UPDATE_RECORD_T *info);
uint8_t SPIFLASH_Write_Update_Recode(UPDATE_RECORD_T *info);
uint8_t SPIFLASH_Read_APP_Update_Flag_Info(G_SYS_FEATURE_T *feature_info);
uint8_t SPIFLASH_Write_APP_Upate_Flag_Info(G_SYS_FEATURE_T *flag_info);
void Jump_APP(uint32_t addr);
#endif /* MCU_DRIVER_INC_LAUNCHER_FUN_H_ */

14
MCU_Driver/inc/flash_mem_addr.h
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@@ -9,16 +9,18 @@
#ifndef _FLASH_MEM_ADDR_H_
#define _FLASH_MEM_ADDR_H_
/*APP<50><50><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
/* - APP<EFBFBD><EFBFBD><EFBFBD>ݼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* - APP Data<74><61><EFBFBD>ݴ<EFBFBD>СΪ412KByte
* */
#define SPIFLASH_APP_Start_Addr 0x00000000
#define SPIFLASH_APP_FEATURE_Addr 0x00000000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 512Byte
#define SPIFLASH_APP_FEATURE_Addr 0x00000000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 512Byte
#define SPIFLASH_UPDATE_FLAG_Addr 0x00000200 //APP<50><50><EFBFBD>±<EFBFBD>־λ - 512Byte
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000400 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000200 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ - 512Byte
#define SPIFLASH_APP_Data_Start_Addr 0x00004000
#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF
#define SPIFLASH_APP_Data_Start_Addr 0x00001000
#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF //ʵ<><CAB5><EFBFBD><EFBFBD>SPI Flash д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַΪ0x00067FFF
#define SPIFLASH_APP_End_Addr 0x0006FFFF

16
MCU_Driver/inc/mcu_flash.h
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@@ -16,16 +16,16 @@
#define APP_Flash_WriteNum 0x05 //APPд<50><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define App_Procedure_Ready 0x66 //APP׼<50><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
#define App_Procedure_Not_Ready 0x44 //Appδ׼<CEB4><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
//MCU Flash Address range(0x0 -- 0x6FFFF) Size(448K)
#define MCU_APP_Flash_Start_Addr 0x00007000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_Start_Addr 0x00007000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_End_Addr 0x00027DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_Addr 0x00027E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_End_Addr 0x00027FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_Start_Addr 0x00001000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_Start_Addr 0x00001000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_End_Addr 0x00067DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_Addr 0x00067E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_End_Addr 0x00067FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_PageAddr 0x00027000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
#define MCU_APP_Feature_PageAddr 0x00067000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
#define MCU_APP_Feature_PageOffset 0x00000E00 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
#define APP_FEATURE_SIZE 0x0200 //512Byte
@@ -91,7 +91,7 @@ typedef struct{
uint8_t dev_app_ver; //<2F>豸APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE>
uint8_t dev_name_len; //<2F>豸<EFBFBD><E8B1B8><EFBFBD>Ƶij<C6B5><C4B3><EFBFBD>
uint8_t dev_name[EEPROM_DEV_NAME_Size]; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
uint8_t dev_retain[24]; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD> - <20><><EFBFBD><EFBFBD>24Byte
}E_MCU_DEV_INFO;

238
MCU_Driver/inc/sram_mem_addr.h
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@@ -9,6 +9,244 @@
#ifndef _SRAM_MEM_ADDR_H_
#define _SRAM_MEM_ADDR_H_
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ
***********************************************************
//SRAM<41>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD>洢<EFBFBD><E6B4A2>ַ -
<20>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ṹ -
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַΪ0x000100
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ洢<C8B4><E6B4A2><EFBFBD><EFBFBD>BUS<55>豸<EFBFBD><E8B1B8>ϢN<CFA2><4E> <20><>ַƫ<D6B7><C6AB>0x000200*N -> SRAM_BUS_Device_List_Addr
<20>ڴ<EFBFBD>֮<EFBFBD><D6AE><EFBFBD><EFBFBD><EFBFBD>Ǵ洢<C7B4><E6B4A2><EFBFBD><EFBFBD>ѯ<EFBFBD>豸<EFBFBD><E8B1B8>ϢN<CFA2><4E> <20><>ַƫ<D6B7><C6AB>0x000200*N -> SRAM_POLL_Device_List_Addr
Ȼ<><C8BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>ϢN<CFA2><4E> <20><>ַƫ<D6B7><C6AB>0x000200*N -> SRAM_ACTIVE_Device_List_Addr
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>豸<EFBFBD><E8B1B8>ϢN<CFA2><4E>
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>豸˳<E8B1B8><CBB3><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*****************************************************************************************
| | <20><>ʼ<EFBFBD><CABC>ַ | <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ |
| BUS<55>豸<EFBFBD><E8B1B8>Ϣ | SRAM_Device_List_Start_Addr | SRAM_BUS_Device_List_Addr |
| <20><>ѯ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ | SRAM_BUS_Device_List_Addr | SRAM_POLL_Device_List_Addr |
| <20><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>Ϣ | SRAM_POLL_Device_List_Addr | SRAM_ACTIVE_Device_List_Addr |
| <20><>ͨ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ | SRAM_ACTIVE_Device_List_Addr| SRAM_Device_List_End_Addr |
*****************************************************************************************
* */
#define SRAM_Device_List_Size 0x00000200 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>С - <20>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD>ܴ<EFBFBD>С
#define SRAM_BUS_Device_List_Addr 0x00000000 //BUS<55>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ - 4Byte
#define SRAM_POLL_Device_List_Addr 0x00000004 //<2F><>ѯ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
#define SRAM_ACTIVE_Device_List_Addr 0x00000008 //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
#define SRAM_NORMAL_Device_List_Addr 0x0000000C //<2F><>ͨ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
#define SRAM_Device_List_Start_Addr 0x00000100 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define SRAM_Device_List_End_Addr 0x00009FFF //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>*/
/*<2A>豸<EFBFBD><E8B1B8>Ϣ - LOGȫ<47><C8AB>
<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>0x00B000 - 0x00BFFF*/
#define SRAM_LOG_Device_C5IO_Relay_Status 0x0000B000 //<2F>̵<EFBFBD><CCB5><EFBFBD>״̬ - 3Byte
#define SRAM_LOG_Device_C5IO_DO_Status 0x0000B003 //DO״̬ - 1byte
#define SRAM_LOG_Device_C5IO_DI_Status 0x0000B004 //DI״̬ - 2Byte
#define SRAM_LOG_Device_C5MUSIC_Playback_Status 0x0000B006 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>״̬ - 1Byte
#define SRAM_LOG_Device_C5MUSIC_Volume_Status 0x0000B007 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1Bye
#define SRAM_LOG_Device_C5MUSIC_idx_Status 0x0000B008 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 2Byte
#define SRAM_LOG_Device_Card_Status 0x0000B00A //<2F>忨ȡ<E5BFA8><C8A1> - 1Byte 2025-09-03 <20><>ûʹ<C3BB><CAB9>
#define SRAM_LOG_Device_Temp_Status 0x0000B00B //<2F>¿<EFBFBD><C2BF><EFBFBD> - 2Byte
/**/
#define SRAM_LOG_Device_Switch_Type 0x0000B00D //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1Byte
#define SRAM_LOG_Device_Switch_Num 0x0000B00E //<2F><><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD> - 1Byte
#define SRAM_LOG_Device_Switch1_Status 0x0000B00F //<2F><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD> 2Byte һ<><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD><D5BC>2Byte<74><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_LOG_Device_Switch2_Status 0x0000B011 //<2F><><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD> 2Byte һ<><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD><D5BC>2Byte<74><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_LOG_Device_Switch3_Status 0x0000B013 //<2F><><EFBFBD><EFBFBD>3<EFBFBD><33><EFBFBD><EFBFBD> 2Byte һ<><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD><D5BC>2Byte<74><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_LOG_RCU_Reboot_Reason 0x0000B015 //RCU<43><55><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9> 2025-09-27
/*<2A>豸<EFBFBD><E8B1B8>Ϣ - UDPȫ<50><C8AB>
<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>0x00C000 - 0x00CFFF*/
#define SRAM_UDP_Device_C5IO_Relay_Status 0x0000C000 //<2F>̵<EFBFBD><CCB5><EFBFBD>״̬ - 3Byte
#define SRAM_UDP_Device_C5IO_DO_Status 0x0000C003 //DO״̬ - 1byte
#define SRAM_UDP_Device_C5IO_DI_Status 0x0000C004 //DI״̬ - 2Byte
#define SRAM_UDP_Device_C5MUSIC_Playback_Status 0x0000C006 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>״̬ - 1Byte
#define SRAM_UDP_Device_C5MUSIC_Volume_Status 0x0000C007 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1Bye
#define SRAM_UDP_Device_C5MUSIC_idx_Status 0x0000C008 //<2F><>Ƶ - <20><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 2Byte
#define SRAM_UDP_Device_Card_Status 0x0000C00A //<2F>忨ȡ<E5BFA8><C8A1> - 1Byte
#define SRAM_UDP_Device_Temp_Status 0x0000C00B //<2F>¿<EFBFBD><C2BF><EFBFBD> - 2Byte
/**/
#define SRAM_UDP_Device_Switch_Type 0x0000C00D //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1Byte
#define SRAM_UDP_Device_Switch_Num 0x0000C00E //<2F><><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD> - 1Byte
#define SRAM_UDP_Device_Switch1_Status 0x0000C00F //<2F><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD> 2Byte һ<><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD><D5BC>2Byte<74><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_UDP_ELEReport_Action 0x0000C011 //UDP ȡ<><C8A1><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
#define SRAM_UDP_ELEReport_EleState 0x0000C012 //UDP ȡ<><C8A1><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>ж<EFBFBD><D0B6>費<EFBFBD><E8B2BB>Ҫ<EFBFBD>ϱ<EFBFBD>
#define SRAM_UDP_ELEReport_EleState_Last 0x0000C013
#define SRAM_UDP_ELEReport_CardState 0x0000C014 //UDP ȡ<><C8A1><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD><D0A3>忨ȡ<E5BFA8><C8A1>״̬<D7B4>ж<EFBFBD><D0B6>費<EFBFBD><E8B2BB>Ҫ<EFBFBD>ϱ<EFBFBD>
#define SRAM_UDP_ELEReport_CardState_Last 0x0000C015
#define SRAM_UDP_ELEReport_CardType 0x0000C016 //UDP ȡ<><C8A1><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD><D0A3>忨ȡ<E5BFA8><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>費<EFBFBD><E8B2BB>Ҫ<EFBFBD>ϱ<EFBFBD>
#define SRAM_UDP_ELEReport_CardType_Last 0x0000C017
#define SRAM_UDP_ELEReport_VirtualCard 0x0000C018 //UDP ȡ<><C8A1><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD><D0A3>޿<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>¼<EFBFBD><C2BC>ж<EFBFBD><D0B6>費<EFBFBD><E8B2BB>Ҫ<EFBFBD>ϱ<EFBFBD>
#define SRAM_UDP_ELEReport_VirtualCard_Last 0x0000C019
#define SRAM_UDP_Report_CarbonSatet 0x0000C01A //UDP <20><><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1>У<EFBFBD>̼<EFBFBD><CCBC><EFBFBD>˵<EFBFBD>״̬
/*SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1>豸<EFBFBD>仯<EFBFBD><E4BBAF><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>ƻ<EFBFBD><C6BB><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>0x00D000 - 0x00DFFF*/
#define SRAM_UDP_SendData_Writeaddr 0x0000D000 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ
#define SRAM_UDP_SendData_Readaddr 0x0000D004 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>ȡ<EFBFBD><C8A1>ַ
#define SRAM_UDP_SendData_Tempaddr 0x0000D008 //
#define SRAM_UDP_SendData_Startaddr 0x0000D010 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define SRAM_UDP_SendData_Endaddr 0x0000D7EA //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define SRAM_UDP_SendData_Size 0x9C //һ<>η<EFBFBD><CEB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_UDP_RecvData_Writeaddr 0x0000D800 //<2F><><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD>ַ
#define SRAM_UDP_RecvData_Readaddr 0x0000D804 //<2F><><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>ݶ<EFBFBD>ȡ<EFBFBD><C8A1>ַ
#define SRAM_UDP_RecvData_Tempaddr 0x0000D808 //<2F><><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ַ
#define SRAM_UDP_RecvData_ControlNum 0x0000D80C //<2F><><EFBFBD>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>
#define SRAM_UDP_RecvData_Startaddr 0x0000D810 //<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define SRAM_UDP_RecvData_Endaddr 0x0000DFEA //<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
/*<2A>ϵ<EFBFBD><CFB5>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><>ַ<EFBFBD><D6B7>Χ:0x0x00E100 ~ 0x00E1FF */
#define SRAM_PowerOn_Restore_StartAddr 0x0000E100
#define SRAM_PowerOn_Restore_Flag 0x0000E100
#define SRAM_PowerOn_Restore_Len 0x0000E101
#define SRAM_PowerOn_Restore_Check 0x0000E102
#define SRAM_PowerOn_Restore_Param 0x0000E103
#define SRAM_PowerOn_Restore_EndAddr 0x0000E1FF
/*Launcherʹ<72><CAB9> <20><><EFBFBD>ڼ<EFBFBD>¼Boot<6F><74><EFBFBD><EFBFBD> дMCU Flash<73><68><EFBFBD><EFBFBD> <20><>С<EFBFBD><D0A1>0x200 2025-04-28*/
#define SRAM_APP_FEATURE_2_CHECK_Addr 0x0000E600
/*<2A><>¼Launcher<65>汾<EFBFBD><E6B1BE>Ϣ <20><>С<EFBFBD><D0A1>0x20 2025-07-07*/
#define SRAM_Launcher_SoftwareVer_Addr 0x0000E800
/*Launcherʹ<72><CAB9> <20><><EFBFBD>ڼ<EFBFBD>¼APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> <20><>С:0x10 2026-01-14*/
#define SRAM_APP_Write_Count_Addr 0x0000E900
/**********SRAM Uart<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_Uart_Buffer_Size 0x0400 //<2F><><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
#define SRAM_UART0_RecvBuffer_Start_Addr 0x00010000
#define SRAM_UART0_RecvBuffer_End_Addr 0x00010FFF
#define SRAM_UART0_SendBuffer_Start_Addr 0x00011000
#define SRAM_UART0_SendBuffer_End_Addr 0x00011FFF
#define SRAM_UART1_RecvBuffer_Start_Addr 0x00012000
#define SRAM_UART1_RecvBuffer_End_Addr 0x00012FFF
#define SRAM_UART1_SendBuffer_Start_Addr 0x00013000
#define SRAM_UART1_SendBuffer_End_Addr 0x00013FFF
#define SRAM_UART2_RecvBuffer_Start_Addr 0x00014000
#define SRAM_UART2_RecvBuffer_End_Addr 0x00014FFF
#define SRAM_UART2_SendBuffer_Start_Addr 0x00015000
#define SRAM_UART2_SendBuffer_End_Addr 0x00015FFF
#define SRAM_UART3_RecvBuffer_Start_Addr 0x00016000
#define SRAM_UART3_RecvBuffer_End_Addr 0x00016FFF
#define SRAM_UART3_SendBuffer_Start_Addr 0x00017000
#define SRAM_UART3_SendBuffer_End_Addr 0x00017FFF
/**********SRAM Uart<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/*2022.12.26 <20>ֿ<EFBFBD><D6BF><EFBFBD><EFBFBD>޸Ŀ<DEB8>ʼ -- <20><>Ҫ<EFBFBD>޸<EFBFBD> */
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4><CCAC>¼ 0x031400~0x031FFF 3K<33><4B>ÿ<EFBFBD><C3BF><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>6<EFBFBD>ֽڣ<D6BD>һ<EFBFBD><D2BB><EFBFBD>ܹ<EFBFBD><DCB9>ܴ<EFBFBD>509<30><39><EFBFBD>豸<EFBFBD><E8B1B8>*/
#define SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR 0x00031400 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬д<CCAC><D0B4><EFBFBD><EFBFBD>ַ
#define SRAM_DEVICE_ONLINE_STATE_READ_ADDR 0x00031404 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ȡ<EFBFBD><C8A1>ַ
#define SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR 0x00031408 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4>м<EFBFBD><D0BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7>
#define SRAM_DEVICE_ONLINE_STATE_START_ADDR 0x00031410 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ʼ<EFBFBD><CABC>ַ<EFBFBD><D6B7>ʵ<EFBFBD>ʿ<EFBFBD>ʼд<CABC><D0B4><EFBFBD>ݵ<EFBFBD>ַ<EFBFBD><D6B7>
//#define SRAM_DEVICE_ONLINE_STATE_END_ADDR 0x00031500 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʵ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ݵ<EFBFBD>ַ<EFBFBD><D6B7> - <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
#define SRAM_DEVICE_ONLINE_STATE_END_ADDR 0x00031FFE //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʵ<EFBFBD>ʽ<EFBFBD><CABD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>ݵ<EFBFBD>ַ<EFBFBD><D6B7>
/*2022.12.26 <20>ֿ<EFBFBD><D6BF><EFBFBD><EFBFBD>޸Ľ<DEB8><C4BD><EFBFBD>*/
#define SRAM_CheckMap_List_Start_Addr 0x0003A800 //Ѳ<><D1B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>10K
#define SRAM_CheckMap_List_End_Addr 0x0003CFFF //Ѳ<><D1B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_VCard_PortInf_Start_Addr 0x0003D000 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> ӳ<><D3B3><EFBFBD>˿<EFBFBD><CBBF><EFBFBD>Ϣ <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>2K
#define SRAM_VCard_PortInf_End_Addr 0x0003D7FF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> ӳ<><D3B3><EFBFBD>˿<EFBFBD><CBBF><EFBFBD>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
#define SRAM_VCard_ConNToS_Start_Addr 0x0003D800 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>1K
#define SRAM_VCard_ConNToS_End_Addr 0x0003DBFF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
#define SRAM_VCard_ConSToN_Start_Addr 0x0003DC00 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>1K
#define SRAM_VCard_Con_End_Addr 0x0003DFFF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
#define SRAM_VCard_DetectWin_Start_Addr 0x0003E000 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD>ⴰ<EFBFBD><E2B4B0>״̬ <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>60K
#define SRAM_VCard_DetectWin_End_Addr 0x0004CFFF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD>ⴰ<EFBFBD><E2B4B0>״̬ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
#define SRAM_VCard_Property_Start_Addr 0x0004D000 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>1K
#define SRAM_VCard_Property_End_Addr 0x0004D3FF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_IAP_APP_FILE_ADDRESS 0x00050000 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50>ļ<EFBFBD><C4BC>ĵ<EFBFBD>ַ - 218K
#define SRAM_IAP_IP_ADDRESS 0x0008E600 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>IP - 4Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_PORT_ADDRESS 0x0008E604 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>port - 2Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_NET_UPGRADE_Flag_ADDRESS 0x0008E606 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ - 1Byte
#define SRAM_IAP_UPGRADE_Reply_NUM_ADDRESS 0x0008E607 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD>APP<50><50>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD> - 1Byte
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/**********<2A><>Ŀӳ<C4BF><D3B3><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_Register_Start_ADDRESS 0x0008E900
#define SRAM_Register_End_ADDRESS 0x0008EFFF
#define Register_OFFSET_LEN 0x0400 //<2F><>ǰ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ռ䳤<D5BC><E4B3A4> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˣ<EFBFBD><CBA3>ⳤ<EFBFBD><E2B3A4>ҲӦ<D2B2>ñ仯
//<2F><>Ŀ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
#define Register_NetIP_OFFSET 0x0000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IP<49><50>ַ - DHCP<43><50><EFBFBD><EFBFBD><EFBFBD>ɹ<EFBFBD>֮<EFBFBD>󣬻<EFBFBD>DHCPʧ<50><CAA7>֮<EFBFBD><D6AE> ʹ<>õ<EFBFBD>IP<49><50>ַ - PC<50><43><EFBFBD><EFBFBD>MCUĬ<55><C4AC>IP
#define Register_NetPort_OFFSET 0x0004 //<2F><><EFBFBD><EFBFBD>ͨѶ<CDA8>˿<EFBFBD> - PC<50><43><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD>
#define Register_NetMask_OFFSET 0x0008 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - PC<50><43><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD>
#define Register_NetGateway_OFFSET 0x000C //<2F><><EFBFBD><EFBFBD> - PC<50><43><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD>
#define Register_DNSServerIP_OFFSET 0x0010 //DNS<4E><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ - PC<50><43><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD>
#define Register_NETMACKADDR_OFFSET 0x0014 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MACK<43><4B>ַ
#define Register_WebServerIP_OFFSET 0x0018 //<2F>ƶ˷<C6B6><CBB7><EFBFBD><EFBFBD><EFBFBD>IP<49><50>ַ - PC<50><43><EFBFBD>õ<EFBFBD><C3B5>ƶ<EFBFBD>IP<49><50>ַ
#define Register_WebServerPort_OFFSET 0x001C //<2F>ƶ˷<C6B6><CBB7><EFBFBD><EFBFBD><EFBFBD>ͨѶ<CDA8>˿<EFBFBD> - 2025-10-11 <20><><EFBFBD><EFBFBD>
#define Register_MandateExpiresTime_OFFSET 0x0020 //MCU<43><55>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> - <20><>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD>
#define Register_CurrentUsageTime_OFFSET 0x0024 //MCU<43><55>ǰʱ<C7B0><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define Register_MandateUTC_OFFSET 0x0028 //<2F><>Ȩʱ<C8A8><CAB1> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȩʱ<C8A8>ĵ<EFBFBD>ǰUTCʱ<43><CAB1>
#define Register_MandateLock_OFFSET 0x002C //<2F><>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD>
#define Register_NetInfo_EN_OFFSET 0x0030 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD>DHCPʹ<50><CAB9> - 1Byte<74><65><EFBFBD><EFBFBD>ʾDHCPʹ<50><CAB9> 1Byte<74>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IP<49><50>ΪĬ<CEAA><C4AC>IP<49><50>ַ - PC<50><43><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD>
#define Register_NetOfflineTime_OFFSET 0x0034 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1> - 4Byte <20><>λ<EFBFBD><CEBB>ms
#define Register_ProjectCode_OFFSET 0x0038 //<2F><>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD>
#define Register_SoftwareVersion_OFFSET 0x003C //<2F><><EFBFBD><EFBFBD><EFBFBD>汾<EFBFBD><E6B1BE> - <20>̼<EFBFBD><CCBC>汾<EFBFBD><E6B1BE>
#define Register_ConfigVersion_OFFSET 0x0040 //<2F><><EFBFBD>ð汾<C3B0><E6B1BE>
#define Register_RoomNumber_OFFSET 0x0044 //<2F><><EFBFBD><EFBFBD>
#define Register_HouseType_OFFSET 0x0048 //<2F><><EFBFBD><EFBFBD>
#define Register_RoomRent_OFFSET 0x004C //<2F><>̬<EFBFBD><CCAC>Ϣ - <20><><EFBFBD><EFBFBD>״̬
#define Register_SeasonStatus_OFFSET 0x0050 //<2F><><EFBFBD><EFBFBD>״̬
#define Register_TFTPStatus_OFFSET 0x0054 //TFTP<54><50>־<EFBFBD><D6BE><EFBFBD><EFBFBD> 4Byte
#define Register_TFTPUploadTime_OFFSET 0x0058 //TFTP<54><50>־<EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> 4Byte
#define Register_BLVServerDmLen_OFFSET 0x005C //BLV<4C><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 4Byte
#define Register_BLVServerDmName_OFFSET 0x0060 //BLV<4C><56><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 64Byte
#define Register_UDPPeriodicTime_OFFSET 0x00A0 //UDPͨѶ <20><><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 4Byte <20><>λ:ms
#define Register_RoomNumNote_OFFSET 0x0100 //<2F><><EFBFBD>ű<EFBFBD>ע<EFBFBD><D7A2>Ϣ<EFBFBD><CFA2><EFBFBD>ŵ<EFBFBD>ַ<EFBFBD>ռ<EFBFBD> - 16Byte
#define Register_RoomTypeNote_OFFSET 0x0110 //<2F><><EFBFBD>ͱ<EFBFBD>ע<EFBFBD><D7A2>Ϣ<EFBFBD><CFA2><EFBFBD>ŵ<EFBFBD>ַ<EFBFBD>ռ<EFBFBD> - 16Byte
#define Register_RoomNote_OFFSET 0x0120 //<2F><><EFBFBD>䱸ע<E4B1B8><D7A2>Ϣ<EFBFBD><CFA2><EFBFBD>ŵ<EFBFBD>ַ<EFBFBD>ռ<EFBFBD> - 96Byte
#define Register_TFTPLOGPort_OFFSET 0x0180 //TFTP<54><50>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD> - 2Byte
#define Register_TFTPLOGTime_OFFSET 0x0182 //TFTP<54><50>־<EFBFBD>ϴ<EFBFBD>ʱ<EFBFBD><CAB1> - 2Byte
#define Register_TFTPDmLens_OFFSET 0x0184 //TFTP<54><50>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 1Byte
#define Register_TFTPDmName_OFFSET 0x0185 //TFTP<54><50>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 64Byte
/**********<2A><>Ŀӳ<C4BF><D3B3><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>·<EFBFBD> <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_IAP_LOGIC_FILE_ADDRESS 0x00090000 //SRAM<41><4D><EFBFBD>߼<EFBFBD><DFBC>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ
#define SRAM_IAP_LOGIC_DataFlag_ADDRESS 0x00090000 //<2F>ļ<EFBFBD><C4BC><EFBFBD>־λ - 4Byte
#define SRAM_IAP_LOGIC_DataSize_ADDRESS 0x00090004 //<2F>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> - 4Byte
#define SRAM_IAP_LOGIC_DataMD5_ADDRESS 0x00090008 //<2F>ļ<EFBFBD>MD5У<35><D0A3>ֵ - 16Byte
#define SRAM_IAP_LOGIC_DataStart_ADDRESS 0x00090200
#define SRAM_IAP_LOGIC_DataEnd_ADDRESS 0x000FFFFF
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>·<EFBFBD> <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
#define SRAM_DevAction_List_Size 0x0400 //ÿ<><C3BF><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><DAB5>洢<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>С - <20><>ǰ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD>
#define SRAM_DevAction_List_Num 950
#define SRAM_DevAction_List_Start_Addr 0x00100000 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>960K
#define SRAM_DevAction_List_End_Addr 0x001EFFFF //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_BlwMap_List_Start_Addr 0x001F0000 //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>32K
#define SRAM_BlwMap_List_End_Addr 0x001F7FFF //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_DevDly_List_Start_Addr 0x001F8000 //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8>ʼ<EFBFBD><CABC>ַ һ<><D2BB>32K
#define SRAM_DevDly_List_End_Addr 0x001FFFFF //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
/*
* 2025-07-29 <20>޸<EFBFBD>SRAM<41>洢<EFBFBD><E6B4A2>ַ 0x00400000 ~ 0x007FFFFF SIZE:4MByte

13
MCU_Driver/inc/uart.h
View File

@@ -28,7 +28,7 @@
#define USART_BUFFER_SIZE 512
typedef void (*Uart_prt)(uint8_t * ,uint16_t );
typedef uint8_t (*Uart_prt)(uint8_t * ,uint16_t );
typedef uint8_t (*Uart_set_prt)(uint32_t );
typedef enum
@@ -80,7 +80,8 @@ typedef struct{
Uart_set_prt set_baud_cf;
}UART_t;
extern UART_t g_uart[UART_MAX];
extern UART_t g_uart_0;
extern UART_t g_uart_2;
void UARTx_Init(UART_IDX uart_id, uint32_t buad);
void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud);
@@ -95,6 +96,14 @@ uint8_t UART1_ChangeBaud(uint32_t baudrate);
uint8_t UART2_ChangeBaud(uint32_t baudrate);
uint8_t UART3_ChangeBaud(uint32_t baudrate);
uint8_t MCU485_SendString_0(uint8_t *buff, uint16_t len);
uint8_t MCU485_SendString_2(uint8_t *buff, uint16_t len);
uint8_t Uartx_Add_Data_To_SendBuff(UART_t *uart_info,uint8_t *buff,uint16_t len,uint8_t sendCount,uint32_t ValidDuration,uint32_t sendInterval);
uint8_t Uartx_Clear_SendBuff(UART_t *uart_info);
uint8_t Uartx_Avoid_Conflict_Send_Task(UART_t *uart_info);
void Uart0_Task(void);
void Uart2_Task(void);
#endif /* MCU_DRIVER_INC_UART_H_ */

18
MCU_Driver/inc/watchdog.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* watchdog.h
*
* Created on: Jan 9, 2026
* Author: cc
*/
#ifndef MCU_DRIVER_INC_WATCHDOG_H_
#define MCU_DRIVER_INC_WATCHDOG_H_
#include <stdint.h>
#include "ch564.h"
void WDT_Init(void);
void WDT_Feed(void);
void WDT_Reinit(void);
#endif /* MCU_DRIVER_INC_WATCHDOG_H_ */