241 lines
5.5 KiB
ArmAsm
241 lines
5.5 KiB
ArmAsm
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;/********************************** (C) COPYRIGHT *******************************
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;* File Name : startup_CH564.S
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;* Author : WCH
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;* Version : V1.0.0
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;* Date : 2024/05/05
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;* Description : vector table for eclipse toolchain for CH564.
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;*********************************************************************************
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;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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;* Attention: This software (modified or not) and binary are used for
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;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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.section .init, "ax", @progbits
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.globl _start
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.align 2
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_start:
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.option norvc;
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j handle_reset
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.section .vector,"ax",@progbits
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.align 2
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_vector_base:
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.option norvc;
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.word _start
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.word 0
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.word NMI_Handler
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.word HardFault_Handler
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.word 0x50000000
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.word Ecall_M_Handler
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.word 0
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.word 0
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.word Ecall_U_Handler
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.word BreakPoint_Handler
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.word 0
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.word 0
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.word SysTick_Handler
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.word 0
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.word SW_Handler
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.word 0
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/*External Interrupts*/
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.word I2C_EV_IRQHandler
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.word I2C_ER_IRQHandler
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.word ETH_IRQHandler
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.word USBPD_IRQHandler
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.word TIM0_IRQHandler
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.word TIM1_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word SPI0_IRQHandler
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.word SPI1_IRQHandler
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.word UART0_IRQHandler
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.word UART1_IRQHandler
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.word PA_IRQHandler
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.word PB_IRQHandler
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.word PD_IRQHandler
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.word ADC_IRQHandler
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.word SLV_IRQHandler
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.word USBHS_HOST_IRQHandler
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.word USBHS_DEV_IRQHandler
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.word UART2_IRQHandler
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.word UART3_IRQHandler
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.word ETHWakeUp_IRQHandler
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.word USBHSWakeUp_IRQHandler
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.word USBPDWakeUp_IRQHandler
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.word 0x08800513
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.word 0x80051073
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.word 0xe000f537
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.word 0xd1350513
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.word 0x08000593
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.word 0x0ff0000f
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.word 0x00b50023
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.option rvc;
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.section .text.vector_handler, "ax", @progbits
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.weak NMI_Handler
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.weak HardFault_Handler
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.weak Ecall_M_Handler
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.weak Ecall_U_Handler
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.weak BreakPoint_Handler
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.weak SysTick_Handler
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.weak SW_Handler
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.weak I2C_EV_IRQHandler
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.weak I2C_ER_IRQHandler
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.weak ETH_IRQHandler
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.weak USBPD_IRQHandler
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.weak TIM0_IRQHandler
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.weak TIM1_IRQHandler
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.weak TIM2_IRQHandler
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.weak TIM3_IRQHandler
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.weak SPI0_IRQHandler
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.weak SPI1_IRQHandler
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.weak UART0_IRQHandler
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.weak UART1_IRQHandler
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.weak PA_IRQHandler
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.weak PB_IRQHandler
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.weak PD_IRQHandler
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.weak ADC_IRQHandler
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.weak SLV_IRQHandler
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.weak USBHS_HOST_IRQHandler
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.weak USBHS_DEV_IRQHandler
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.weak UART2_IRQHandler
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.weak UART3_IRQHandler
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.weak ETHWakeUp_IRQHandler
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.weak USBHSWakeUp_IRQHandler
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.weak USBPDWakeUp_IRQHandler
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NMI_Handler:
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HardFault_Handler:
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Ecall_M_Handler:
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Ecall_U_Handler:
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BreakPoint_Handler:
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SysTick_Handler:
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SW_Handler:
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I2C_EV_IRQHandler:
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I2C_ER_IRQHandler:
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ETH_IRQHandler:
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USBPD_IRQHandler:
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TIM0_IRQHandler:
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TIM1_IRQHandler:
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TIM2_IRQHandler:
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TIM3_IRQHandler:
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SPI0_IRQHandler:
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SPI1_IRQHandler:
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UART0_IRQHandler:
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UART1_IRQHandler:
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PA_IRQHandler:
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PB_IRQHandler:
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PD_IRQHandler:
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ADC_IRQHandler:
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SLV_IRQHandler:
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USBHS_HOST_IRQHandler:
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USBHS_DEV_IRQHandler:
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UART2_IRQHandler:
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UART3_IRQHandler:
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ETHWakeUp_IRQHandler:
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USBHSWakeUp_IRQHandler:
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USBPDWakeUp_IRQHandler:
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1:
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j 1b
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.section .text.handle_reset,"ax",@progbits
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.weak handle_reset
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.align 1
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handle_reset:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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1:
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la sp, _eusrstack
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2:
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/* Load data section from flash to RAM */
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* Configure pipelining and instruction prediction */
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li t0, 0x1f
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csrw 0xbc0, t0
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/* Enable interrupt nesting and hardware stack */
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li t0, 0x3
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csrw 0x804, t0
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/* Enable global interrupt and configure privileged mode */
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li t0, 0x1888
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csrw mstatus, t0
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/* Configure the interrupt vector table recognition mode and entry address mode */
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la t0, _vector_base
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ori t0, t0, 3
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csrw mtvec, t0
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/*Enable the cache to cache the code from _cache_beg to _cache_end */
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/* PMP TOR(pmpaddr0 - pmpaddr1) */
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la t0, _cache_beg
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srli t0, t0, 2
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csrw pmpaddr0, t0
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la t0, _cache_end
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srli t0, t0, 2
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csrw pmpaddr1, t0
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li t0, 0x10
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csrw 0xbc3, t0
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li t0, 0xAD00
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csrw 0x3a0, t0
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/* Enable ICache */
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li t0, 0x4
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csrw 0xbd0, t0
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li t0, 0x03000002
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csrc 0xbc2, t0
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/* Comfigure systemclock */
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jal SystemInit
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/* Jump main */
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la t0, main
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csrw mepc, t0
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mret
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