Boonlive_RD_Embedded/RCU_C1P_Module
6
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
cc8783e9f8853d057f4b556a7e54c6a2579e6c69
RCU_C1P_Module/MCU_Driver/blv_rs485_protocol.c

1662 lines
70 KiB
C
Raw Normal View History

feat:新建项目文件 BLV主机C1P模块
2025-12-06 13:49:01 +08:00
/*
* blv_rs485_protocol.c
*
* Created on: Nov 10, 2025
* Author: cc
*/
#include "includes.h"
#include <string.h>
BLV_BUS_Manage_G BUS485_Info;
BLV_ACTIVE_Manage_G Act485_Info;
BLV_POLL_Manage_G Poll485_Info;
BLV_NORDEV_Manage_G NorDevInfoGlobal; /*<2A><>ͨ<EFBFBD>豸ȫ<E8B1B8>ֱ<EFBFBD><D6B1><EFBFBD>*/
uint8_t rs485_temp_buff[612];
/*******************************************************************************
* Function Name : Add_BUS_Device_To_List
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD>BUS<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
dev_info : <EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
dev_data : <EFBFBD>豸<EFBFBD><EFBFBD>˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
data_len <EFBFBD><EFBFBD><EFBFBD>豸˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Add_BUS_Device_To_List(
Device_Public_Information_G *dev_info,
uint8_t *dev_data,
uint16_t data_len)
{
/*<2A><><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BUS485<38>豸*/
dev_info->data_len = data_len + Dev_Privately; //<2F>豸˽<E8B1B8><CBBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3>ȼ<EFBFBD><C8BC>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint32_t list_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr); //<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
if((list_addr < SRAM_Device_List_Start_Addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = SRAM_Device_List_Start_Addr;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately);
memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len);
dev_info->check = 0x00;
dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len);
SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr);
// /*<2A><><EFBFBD>ӹ<EFBFBD><D3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_DMA_Write_Buff(rs485_temp_buff,Dev_Privately,list_addr);
//
// /*<2A><><EFBFBD><EFBFBD><EFBFBD>豸˽<E8B1B8>б<EFBFBD><D0B1><EFBFBD>*/
// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately);
//
// /*<2A><><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ֵ*/
// check_val = Dev_CheckSum(list_addr,dev_info->data_len);
// SRAM_Write_Byte(check_val,list_addr+Dev_Check); //У<><D0A3>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len);
// for(uint16_t i = 0;i < write_len;i++)
// {
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i));
// }
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n");
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>*/
list_addr += SRAM_Device_List_Size;
SRAM_Write_DW(list_addr,SRAM_BUS_Device_List_Addr);
}
/*******************************************************************************
* Function Name : Add_POLL_Device_To_List
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
dev_info : <EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
dev_data <EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
addr : <EFBFBD>豸˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Add_POLL_Device_To_List(
Device_Public_Information_G *dev_info,
uint8_t *dev_data,
uint16_t data_len)
{
/*<2A><><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>POLL485<38>豸*/
dev_info->data_len = data_len + Dev_Privately; //<2F>豸˽<E8B1B8><CBBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3>ȼ<EFBFBD><C8BC>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint32_t list_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr); //<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
uint32_t Start_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr); //<2F><>ȡ<EFBFBD><C8A1>ѯ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2>ʼ<EFBFBD><CABC>ַ
if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr))
{
Start_addr = SRAM_Device_List_Start_Addr;
SRAM_Write_DW(Start_addr,SRAM_BUS_Device_List_Addr);
}
if( (list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately);
memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len);
dev_info->check = 0x00;
dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len);
SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr);
// /*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// for(uint16_t i = 0;i<SRAM_Device_List_Size;i++)
// {
// SRAM_Write_Byte(0x00,list_addr+i);
// }
//
// /*<2A><><EFBFBD>ӹ<EFBFBD><D3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_DMA_Write_Buff((uint8_t *)dev_info,Dev_Privately,list_addr);
//
// /*<2A><><EFBFBD><EFBFBD>485<38>豸<EFBFBD>Ļص<C4BB><D8B5><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_Write_DW(dev_info->polling_cf,list_addr+Dev_Polling_CF);
//
// SRAM_Write_DW(dev_info->processing_cf,list_addr+Dev_Processing_CF);
//
// /*<2A><><EFBFBD><EFBFBD><EFBFBD>豸˽<E8B1B8>б<EFBFBD><D0B1><EFBFBD>*/
// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately);
//
// /*<2A><><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ֵ*/
// dev_info->check = Dev_CheckSum(list_addr,dev_info->data_len);
// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //У<><D0A3>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len);
// for(uint16_t i = 0;i < write_len;i++)
// {
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i));
// }
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n");
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>*/
list_addr += SRAM_Device_List_Size;
SRAM_Write_DW(list_addr,SRAM_POLL_Device_List_Addr);
}
/*******************************************************************************
* Function Name : Add_ACT_Device_To_List2
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
dev_info : <EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
dev_data <EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
addr : <EFBFBD>豸˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Add_ACT_Device_To_List(
Device_Public_Information_G *dev_info,
uint8_t *dev_data,
uint16_t data_len)
{
/*<2A><><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>POLL485<38>豸*/
dev_info->check = 0x00;
dev_info->data_len = data_len + Dev_Privately; //<2F>豸˽<E8B1B8><CBBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3>ȼ<EFBFBD><C8BC>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint32_t list_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
uint32_t Start_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr); //<2F><>ȡ<EFBFBD><C8A1>ѯ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2>ʼ<EFBFBD><CABC>ַ
if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr))
{
Start_addr = SRAM_Device_List_Start_Addr;
SRAM_Write_DW(Start_addr,SRAM_POLL_Device_List_Addr);
}
if((list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately);
memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len);
dev_info->check = 0x00;
dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len);
SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr);
// /*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// for(uint16_t i = 0;i<SRAM_Device_List_Size;i++)
// {
// SRAM_Write_Byte(0x00,list_addr+i);
// }
// /*<2A><><EFBFBD>ӹ<EFBFBD><D3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_DMA_Write_Buff((uint8_t *)dev_info,Dev_Privately,list_addr);
//
// /*<2A><><EFBFBD><EFBFBD>485<38>豸<EFBFBD>Ļص<C4BB><D8B5><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_Write_DW(dev_info->polling_cf,list_addr+Dev_Polling_CF);
//
// SRAM_Write_DW(dev_info->processing_cf,list_addr+Dev_Processing_CF);
//
// /*<2A><><EFBFBD><EFBFBD><EFBFBD>豸˽<E8B1B8>б<EFBFBD><D0B1><EFBFBD>*/
// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately);
//
// /*<2A><><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ֵ*/
// dev_info->check = Dev_CheckSum(list_addr,dev_info->data_len);
// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //У<><D0A3>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len);
// for(uint16_t i = 0;i < write_len;i++)
// {
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i));
// }
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n");
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>*/
list_addr += SRAM_Device_List_Size;
SRAM_Write_DW(list_addr,SRAM_ACTIVE_Device_List_Addr);
}
/*******************************************************************************
* Function Name : Add_Nor_Device_To_List2
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
Device_Public_Information_G *dev_info : <EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
dev_data <EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
data_len : <EFBFBD>豸˽<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Add_Nor_Device_To_List(
Device_Public_Information_G *dev_info,
uint8_t *dev_data,
uint16_t data_len)
{
/*<2A><><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>豸*/
dev_info->data_len = data_len + Dev_Privately; //<2F>豸˽<E8B1B8><CBBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3>ȼ<EFBFBD><C8BC>Ϲ<EFBFBD><CFB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵij<DDB5><C4B3><EFBFBD>
uint32_t list_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr); //<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
uint32_t Start_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>Ϣ<EFBFBD><CFA2>ʼ<EFBFBD><CABC>ַ
if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr))
{
Start_addr = SRAM_Device_List_Start_Addr;
SRAM_Write_DW(Start_addr,SRAM_ACTIVE_Device_List_Addr);
}
if((list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately);
memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len);
dev_info->check = 0x00;
dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len);
SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr);
// /*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// for(uint16_t i = 0;i<SRAM_Device_List_Size;i++)
// {
// SRAM_Write_Byte(0x00,list_addr+i);
// }
//
// /*<2A><><EFBFBD>ӹ<EFBFBD><D3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
// SRAM_DMA_Write_Buff((uint8_t *)dev_info,Dev_Privately,list_addr);
//
// /*<2A><><EFBFBD><EFBFBD><EFBFBD>豸˽<E8B1B8>б<EFBFBD><D0B1><EFBFBD>*/
// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately);
//
// /*<2A><><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ֵ*/
// dev_info->check = Dev_CheckSum(list_addr,dev_info->data_len);
// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //У<><D0A3>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len);
// for(uint16_t i = 0;i < write_len;i++)
// {
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i));
// }
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n");
/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>*/
list_addr += SRAM_Device_List_Size;
SRAM_Write_DW(list_addr,SRAM_NORMAL_Device_List_Addr);
}
/*******************************************************************************
* Function Name : BLV_Device_Info_Write_To_SRAM
* Description : <EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD>뵽SRAM<EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint8_t BLV_Device_Info_Write_To_SRAM(
uint32_t dev_addr,
Device_Public_Information_G *dev_info,
uint8_t *dev_data,
uint16_t data_len)
{
if(dev_info == NULL) return 1;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately);
memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len);
dev_info->check = 0x00;
dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len);
SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,dev_addr);
return 0x00;
}
/*******************************************************************************
* Function Name : Device_Data_Check
* Description : <EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint8_t Device_Data_Check(uint32_t sram_addr)
{
uint16_t data_len = SRAM_Read_Word(sram_addr + Dev_DataLen);
uint8_t data_sum = 0;
if(data_len > SRAM_Device_List_Size) return 1;
memset(rs485_temp_buff,0,sizeof(rs485_temp_buff));
SRAM_DMA_Read_Buff(rs485_temp_buff,data_len,sram_addr);
for(uint16_t i = 0;i<data_len;i++)
{
data_sum += rs485_temp_buff[i];
}
return ~data_sum;
}
/*******************************************************************************
* Function Name : BLV_BUS_Polling_Task
* Description : BUS<EFBFBD><EFBFBD>ѯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_BUS_Polling_Task(void)
{
static uint32_t BLV_BUS_Wait = 0;
uint16_t data_len = 0;
uint8_t rev = 0;
if(BUS485_Info.device_num == 0x00) return ;
switch(BUS485_Info.BUS_Start)
{
case B_IDLE:
BUS485_Info.BUS_Start = B_Polling;
break;
case B_Polling:
if(SRAM_Read_Byte(BUS485_Info.Last_list_addr + Dev_port) == Bus_port)
{
/*У<><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS Data_Check");
if(Device_Data_Check(BUS485_Info.Last_list_addr) == 0)
{
BUS485_Info.n_list_read_addr = BUS485_Info.Last_list_addr;
/*<2A><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ*/
Device_Public_Information_G dev_info;
SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),BUS485_Info.n_list_read_addr);
BUS485_Info.n_dev_type = dev_info.type;
BUS485_Info.n_dev_addr = dev_info.addr;
BUS485_Info.n_dev_datalen = dev_info.data_len;
BUS485_Info.n_polling_cf = dev_info.polling_cf;
BUS485_Info.n_processing_cf = dev_info.processing_cf;
BUS485_Info.n_dev_waittime = dev_info.wait_time;
BUS485_Info.n_retry_num = dev_info.retry_num;
BUS485_Info.Retry_Flag = 0x01;
/*<2A><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>ѯ<EFBFBD><D1AF><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>*/
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS_dev Polling");
if(BUS485_Info.baud != dev_info.baud) //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뵱ǰͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD>ʲ<EFBFBD><CAB2><EFBFBD>
{
/*<2A>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS_Port Baud:%ld,Change Baud:%ld\r\n",BUS485_Info.baud,dev_info.baud);
BUS485_Info.baud = dev_info.baud;
if(BUS485_Info.BaudRateCfg != NULL) BUS485_Info.BaudRateCfg(BUS485_Info.baud);
BUS485_Info.BUS_Start = Baud_Wait;
BUS485_Info.change_tick = SysTick_1ms;
}else{ //<2F><><EFBFBD><EFBFBD><EFBFBD>ʲ<EFBFBD><CAB2><EFBFBD><EFBFBD>л<EFBFBD>
if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) {
rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr);
}
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
BUS485_Info.BUS_Start = Change_Dev;
/*BUS485<38><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><D1AF><EFBFBD>ݵ<EFBFBD><DDB5>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD><D8B8>׶<EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD>л<EFBFBD><D0BB>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD><D8B7><EFBFBD>־λ<D6BE><CEBB><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>λ - 2022-05-04*/
BUS485_Info.Retry_Flag = 0x00;
BUS485_Info.n_retry_num = 0x00;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_BUS_Wait = SysTick_1ms;
BUS485_Info.BUS_Start = Wait_Reply;
}
}
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"[BLV_BUS_Polling_Task2]BLV_BUS_dev Check Fail:%08X",BUS485_Info.Last_list_addr);
BUS485_Info.BUS_Start = Change_Dev;
}
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS_dev Type Fail");
BUS485_Info.BUS_Start = Change_Dev;
}
break;
case Change_Dev:
BUS485_Info.Last_list_addr += SRAM_Device_List_Size; //<2F><>һ<EFBFBD><D2BB><EFBFBD>豸
if(BUS485_Info.Last_list_addr >= SRAM_Read_DW(SRAM_BUS_Device_List_Addr)) BUS485_Info.Last_list_addr = SRAM_Device_List_Start_Addr;
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS Change_Dev");
BUS485_Info.BUS_Start = B_Polling;
break;
case B_Retry:
if((BUS485_Info.Retry_Flag == 0x01) && (BUS485_Info.n_retry_num != 0x00)) //<2F>ط<EFBFBD><D8B7><EFBFBD>־δ<D6BE><CEB4><EFBFBD>㣬<EFBFBD><E3A3AC>ʾû<CABE><C3BB><EFBFBD>ͳɹ<CDB3>
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS Retransmitting Data:%d-%d-%08X...",BUS485_Info.n_dev_type,BUS485_Info.n_dev_addr,BUS485_Info.n_list_read_addr);
//<2F>޸<EFBFBD>ʱ<EFBFBD><CAB1>:2022-07-12
if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
BUS485_Info.BUS_Start = Change_Dev;
/*BUS485<38><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><D1AF><EFBFBD>ݵ<EFBFBD><DDB5>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD><D8B8>׶<EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD>л<EFBFBD><D0BB>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD><D8B7><EFBFBD>־λ<D6BE><CEBB><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>λ - 2022-05-04*/
BUS485_Info.Retry_Flag = 0x00;
BUS485_Info.n_retry_num = 0x00;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_BUS_Wait = SysTick_1ms; //<2F><><EFBFBD>¼<EFBFBD>ʱ
BUS485_Info.n_retry_num--;
BUS485_Info.BUS_Start = Wait_Reply;
}
}else if((BUS485_Info.Retry_Flag == 0x01) && (BUS485_Info.n_retry_num == 0x00))
{
BUS485_Info.BUS_Start = Change_Dev; //<2F><><EFBFBD><EFBFBD>ʧ<EFBFBD>ܣ<EFBFBD><DCA3>л<EFBFBD><D0BB>¸<EFBFBD><C2B8>豸
}else { //2021-06-29 <20><><EFBFBD><EFBFBD>
BUS485_Info.BUS_Start = Change_Dev; //<2F><><EFBFBD><EFBFBD>ʧ<EFBFBD>ܣ<EFBFBD><DCA3>л<EFBFBD><D0BB>¸<EFBFBD><C2B8>豸
}
break;
case Wait_Reply:
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr);
if((BUS485_Info.n_processing_cf!=0x00000000) && (BUS485_Info.n_processing_cf!=0xFFFFFFFF)) {
BUS485_Info.Retry_Flag = ((fun2_prt)BUS485_Info.n_processing_cf)(BUS485_Info.n_list_read_addr,g_uart[UART_3].RX_Buffer_ReadAddr + 2,data_len);
}
if(BUS485_Info.Retry_Flag == 0x00) {
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC\r\n");
BUS485_Info.send_wait = SysTick_1ms;
BUS485_Info.BUS_Start = B_Wait; //<2F>ظ<EFBFBD><D8B8>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF>У<EFBFBD><D0A3><EFBFBD><EFBFBD>л<EFBFBD>Ϊ<EFBFBD><CEAA>һ<EFBFBD><D2BB><EFBFBD>豸
}
if(BUS485_Info.port_mode == Port_Monitoring_mode) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>ģʽ<C4A3><CABD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>PC<50><43>
{
Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
}
g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) {
g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr;
}
}
/*<2A><><EFBFBD>ճ<EFBFBD>ʱ - <20><><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD>*/
if(SysTick_1ms - BLV_BUS_Wait > BUS485_Info.n_dev_waittime) BUS485_Info.BUS_Start = B_Retry;
break;
case B_Wait:
if(SysTick_1ms - BUS485_Info.send_wait > BLV_BUS485_WaitLdle_Time) {
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS B_Wait");
BUS485_Info.BUS_Start = Change_Dev;
}
//BUS485_Info.BUS_Start = Change_Dev;
break;
/*2021-11-24 : <20><><EFBFBD><EFBFBD>C5IO<49><4F><EFBFBD><EFBFBD><EFBFBD>ʲ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ݵ<EFBFBD>ǰ<EFBFBD>豸ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3>л<EFBFBD><D0BB><EFBFBD><EFBFBD>Ͳ<EFBFBD><CDB2><EFBFBD><EFBFBD>ʣ<EFBFBD><CAA3>л<EFBFBD><D0BB>겨<EFBFBD><EAB2A8><EFBFBD>ʺ󣬵ȴ<F3A3ACB5>10ms<6D>ڽ<EFBFBD><DABD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2022-07-19 : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨѶһ<EFBFBD>Σ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>Ӷ<EFBFBD><EFBFBD><EFBFBD>
*/
case Baud_Wait: //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵȴ<CAB5>ʱ<EFBFBD><CAB1>
if(SysTick_1ms - BUS485_Info.change_tick > BLV_BUS485_ChangeBaudWaitTime)
{
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Wait");
if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>
BUS485_Info.change_tick = SysTick_1ms;
BUS485_Info.BUS_Start = Baud_Comm;
}
break;
case Baud_Comm:
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr);
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm1");
if((BUS485_Info.n_processing_cf!=0x00000000) && (BUS485_Info.n_processing_cf!=0xFFFFFFFF)) {
BUS485_Info.Retry_Flag = ((fun2_prt)BUS485_Info.n_processing_cf)(BUS485_Info.n_list_read_addr,g_uart[UART_3].RX_Buffer_ReadAddr + 2,data_len);
}
if(BUS485_Info.Retry_Flag == 0x00) //<2F>ظ<EFBFBD><D8B8>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>һ<EFBFBD><D2BB>ͨѶ
{
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm3");
BUS485_Info.BUS_Start = Baud_SendWait;
BUS485_Info.change_tick = SysTick_1ms;
}
if(BUS485_Info.port_mode == Port_Monitoring_mode) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>ģʽ<C4A3><CABD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>PC<50><43>
{
Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
}
g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) {
g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr;
}
}
/*<2A><><EFBFBD>յȴ<D5B5><C8B4><EFBFBD>ʱ*/
if(SysTick_1ms - BUS485_Info.change_tick > BUS485_Info.n_dev_waittime) {
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm2");
BUS485_Info.change_tick = SysTick_1ms;
BUS485_Info.BUS_Start = Baud_SendWait;
}
break;
case Baud_SendWait:
if(SysTick_1ms - BUS485_Info.change_tick > BLV_BUS485_ChangeBaudSendWaitTime) {
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm2");
BUS485_Info.change_tick = SysTick_1ms;
BUS485_Info.BUS_Start = B_Send;
}
break;
case B_Send: //<2F><><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- send");
//if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) Convert_To_Fun_Prt(BUS485_Info.n_polling_cf,BUS485_Info.n_list_read_addr);
//<2F>޸<EFBFBD>ʱ<EFBFBD><CAB1>:2022-07-12
if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
BUS485_Info.BUS_Start = Change_Dev;
/*BUS485<38><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><D1AF><EFBFBD>ݵ<EFBFBD><DDB5>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD><D8B8>׶<EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD>л<EFBFBD><D0BB>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD><D8B7><EFBFBD>־λ<D6BE><CEBB><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>λ - 2022-05-04*/
BUS485_Info.Retry_Flag = 0x00;
BUS485_Info.n_retry_num = 0x00;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_BUS_Wait = SysTick_1ms; //<2F><><EFBFBD>¼<EFBFBD>ʱ
BUS485_Info.BUS_Start = Wait_Reply;
}
break;
default:
BUS485_Info.BUS_Start = Change_Dev;
break;
}
/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD>Ǵ<EFBFBD><C7B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>£<EFBFBD><C2A3><EFBFBD>ʱ<EFBFBD>ع<EFBFBD><D8B9><EFBFBD><EFBFBD><EFBFBD>ģʽ*/
if(BUS485_Info.port_mode != Port_Normal_Mode)
{
if(SysTick_1s - BUS485_Info.mode_tick > BUS485_Info.mode_outtime)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC");
BUS485_Info.mode_tick = SysTick_1s;
BUS485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
}
}
}
/*******************************************************************************
* Function Name : BUS485Port_Passthrough_Task
* Description : BUSPort BUS<EFBFBD>˿<EFBFBD>͸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BUS485Port_Passthrough_Task(void)
{
uint16_t data_len = 0;
switch(BUS485_Info.pass_state)
{
case B_IDLE: //<2F><><EFBFBD><EFBFBD>״̬ - <20>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD>·<EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len);
Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr;
}
if(g_uart[UART_3].TX_Buffer_WriteAddr != g_uart[UART_3].TX_Buffer_ReadAddr)
{
/*<2A><>ȡ<EFBFBD><C8A1><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD> - <20>·<EFBFBD>*/
data_len = SRAM_Read_Word(g_uart[UART_3].TX_Buffer_ReadAddr);
BUS485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_3].TX_Buffer_ReadAddr + 2); //<2F><>λ<EFBFBD><CEBB>S
if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
BUS485_Info.pass_tick = SysTick_1s;
MCU485_SendSRAMData(Bus_port,g_uart[UART_3].TX_Buffer_ReadAddr + 3,data_len); //<2F>·<EFBFBD>
BUS485_Info.pass_state = Wait_Reply;
g_uart[UART_3].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_3].TX_Buffer_ReadAddr > SRAM_UART3_SendBuffer_End_Addr) g_uart[UART_3].TX_Buffer_ReadAddr = SRAM_UART3_SendBuffer_Start_Addr;
}
if(SysTick_1s - BUS485_Info.mode_tick > BUS485_Info.mode_outtime)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS485_Info Port_Normal_Mode mode_outtime");
BUS485_Info.mode_tick = SysTick_1s;
BUS485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
BUS485_Info.baud = Bus_Baud;
}
break;
case Wait_Reply: //<2F>ȴ<EFBFBD><C8B4>ظ<EFBFBD> - <20>ظ<EFBFBD><D8B8><EFBFBD>ʱ<EFBFBD>Ļ<EFBFBD> - <20>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len);
Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr);
BUS485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr;
}
if(SysTick_1s - BUS485_Info.pass_tick > BUS485_Info.pass_outtime)
{
//<2F>ظ<EFBFBD><D8B8><EFBFBD>ʱ
Udp_Internal_SeriaNet_Response_Timeout();
BUS485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
}
break;
default:
BUS485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
break;
}
}
/*******************************************************************************
* Function Name : BLV_BUS485Port_ModeTask
* Description : BUS<EFBFBD>˿<EFBFBD>ģʽ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_BUS485Port_ModeTask(void)
{
switch(BUS485_Info.port_mode)
{
case Port_Passthrough_mode:
BUS485Port_Passthrough_Task(); //͸<><CDB8>ģʽ
break;
case Port_Normal_Mode:
case Port_Monitoring_mode:
BLV_BUS_Polling_Task(); //<2F><><EFBFBD><EFBFBD>ģʽ <20>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>¼<EFBFBD><C2BC><EFBFBD>ģʽ
break;
}
}
/*******************************************************************************
* Function Name : BLV_PollPort_Task
* Description : PollPort<EFBFBD><EFBFBD>ѯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_PollPort_Task(void)
{
static uint32_t BLV_POLL_Wait = 0;
uint16_t data_len = 0;
uint8_t rev = 0;
if(Poll485_Info.device_num == 0x00) return ;
switch(Poll485_Info.POLL_Start)
{
case B_IDLE:
Poll485_Info.POLL_Start = B_Polling;
break;
case B_Polling:
if(SRAM_Read_Byte(Poll485_Info.Last_list_addr + Dev_port) == Polling_Port)
{
/*У<><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
if(Device_Data_Check(Poll485_Info.Last_list_addr) == 0)
{
Poll485_Info.n_list_read_addr = Poll485_Info.Last_list_addr;
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>*/
if(Poll485_Info.baud != SRAM_Read_DW(Poll485_Info.n_list_read_addr + Dev_baud))
{
Poll485_Info.baud = SRAM_Read_DW(Poll485_Info.n_list_read_addr + Dev_baud);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev change baud:%08X",Poll485_Info.baud);
Poll485_Info.BaudRateCfg( Poll485_Info.baud );
Poll485_Info.POLL_Start = Baud_Wait;
Poll485_Info.change_tick = SysTick_1ms;
}else {
/*<2A><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ*/
Device_Public_Information_G dev_info;
SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Poll485_Info.n_list_read_addr);
Poll485_Info.n_dev_type = dev_info.type;
Poll485_Info.n_dev_addr = dev_info.addr;
Poll485_Info.n_dev_datalen = dev_info.data_len;
Poll485_Info.n_polling_cf = dev_info.polling_cf;
Poll485_Info.n_processing_cf = dev_info.processing_cf;
Poll485_Info.n_dev_waittime = dev_info.wait_time;
Poll485_Info.n_retry_num = dev_info.retry_num;
Poll485_Info.Retry_Flag = 0x01;
/*2021 09 17 <20><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD>ӷ<EFBFBD><D3B7>ͺ<EFBFBD><CDBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD>жϣ<D0B6>RS485OCCUPYNOTIME<4D><45>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>û<EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸*/
if((Poll485_Info.n_polling_cf!=0x00000000) && (Poll485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr);
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
Poll485_Info.POLL_Start = Change_Dev;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_POLL_Wait = SysTick_1ms;
Poll485_Info.POLL_Start = Wait_Reply;
}
}
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev Check Fail:%08X",Poll485_Info.Last_list_addr);
Poll485_Info.POLL_Start = Change_Dev;
}
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev Type Fail:%08X , %d",Poll485_Info.Last_list_addr,SRAM_Read_Byte(Poll485_Info.Last_list_addr + Dev_Type));
Poll485_Info.POLL_Start = Change_Dev;
}
break;
case Baud_Wait:
if(SysTick_1ms - Poll485_Info.change_tick > BLV_POLL485_ChangeBaudWaitTime)
{
/*<2A><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ*/
Device_Public_Information_G dev_info;
SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Poll485_Info.n_list_read_addr);
Poll485_Info.n_dev_type = dev_info.type;
Poll485_Info.n_dev_addr = dev_info.addr;
Poll485_Info.n_dev_datalen = dev_info.data_len;
Poll485_Info.n_polling_cf = dev_info.polling_cf;
Poll485_Info.n_processing_cf = dev_info.processing_cf;
Poll485_Info.n_dev_waittime = dev_info.wait_time;
Poll485_Info.n_retry_num = dev_info.retry_num;
Poll485_Info.Retry_Flag = 0x01;
/*2021 09 17 <20><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD>ӷ<EFBFBD><D3B7>ͺ<EFBFBD><CDBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD>жϣ<D0B6>0xF0<46><30>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>û<EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸*/
if((Poll485_Info.n_polling_cf!=0x00000000) && (Poll485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr);
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
Poll485_Info.POLL_Start = Change_Dev;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_POLL_Wait = SysTick_1ms;
Poll485_Info.POLL_Start = Wait_Reply;
}
}
break;
case Change_Dev:
Poll485_Info.Last_list_addr += SRAM_Device_List_Size; //<2F><>һ<EFBFBD><D2BB><EFBFBD>豸
if(Poll485_Info.Last_list_addr >= SRAM_Read_DW(SRAM_POLL_Device_List_Addr)) Poll485_Info.Last_list_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr);
Poll485_Info.POLL_Start = B_Polling;
break;
case B_Retry:
if((Poll485_Info.Retry_Flag == 0x01) && (Poll485_Info.n_retry_num != 0x00)) //<2F>ط<EFBFBD><D8B7><EFBFBD>־δ<D6BE><CEB4><EFBFBD>㣬<EFBFBD><E3A3AC>ʾû<CABE><C3BB><EFBFBD>ͳɹ<CDB3>
{
/*2021 09 17 <20><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD>ӷ<EFBFBD><D3B7>ͺ<EFBFBD><CDBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD>жϣ<D0B6>0xF0<46><30>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>û<EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸*/
if((Poll485_Info.n_polling_cf != 0x00000000) && (Poll485_Info.n_polling_cf != 0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr);
if(rev == RS485OCCUPYNOTIME) //<2F>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>豸
{
Poll485_Info.POLL_Start = Change_Dev;
}else { //<2F><><EFBFBD>ݷ<EFBFBD><DDB7>ͳɹ<CDB3><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4>ظ<EFBFBD>
BLV_POLL_Wait = SysTick_1ms; //<2F><><EFBFBD>¼<EFBFBD>ʱ
Poll485_Info.n_retry_num--;
Poll485_Info.POLL_Start = Wait_Reply;
}
}else if((Poll485_Info.Retry_Flag == 0x01) && (Poll485_Info.n_retry_num == 0x00))
{
Poll485_Info.POLL_Start = Change_Dev; //<2F><><EFBFBD><EFBFBD>ʧ<EFBFBD>ܣ<EFBFBD><DCA3>л<EFBFBD><D0BB>¸<EFBFBD><C2B8>豸
}else {
Poll485_Info.POLL_Start = Change_Dev;
}
break;
case Wait_Reply:
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr);
if((Poll485_Info.n_processing_cf!=0x00000000) && (Poll485_Info.n_processing_cf!=0xFFFFFFFF)) {
Poll485_Info.Retry_Flag = ((fun2_prt )Poll485_Info.n_processing_cf)(Poll485_Info.n_list_read_addr,g_uart[UART_0].RX_Buffer_ReadAddr + 2,data_len);
}
if(Poll485_Info.Retry_Flag == 0x00) {
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC\r\n");
Poll485_Info.send_wait = SysTick_1ms;
Poll485_Info.POLL_Start = B_Wait; //<2F>ظ<EFBFBD><D8B8>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF>У<EFBFBD><D0A3><EFBFBD><EFBFBD>л<EFBFBD>Ϊ<EFBFBD><CEAA>һ<EFBFBD><D2BB><EFBFBD>豸
}
if(Poll485_Info.port_mode == Port_Monitoring_mode) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>ģʽ<C4A3><CABD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>PC<50><43>
{
Udp_Internal_SeriaNet_Uploading(Polling_Port,Poll485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
}
g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) {
g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr;
}
}
/*<2A><><EFBFBD>ճ<EFBFBD>ʱ - <20><><EFBFBD><EFBFBD><EFBFBD>ط<EFBFBD>*/
if(SysTick_1ms - BLV_POLL_Wait > Poll485_Info.n_dev_waittime) Poll485_Info.POLL_Start = B_Retry;
break;
case B_Wait: //<2F><><EFBFBD>ͳɹ<CDB3><C9B9>ȴ<EFBFBD>ʱ<EFBFBD><CAB1>
if(SysTick_1ms - BLV_POLL_Wait > Poll485_Info.n_dev_waittime) Poll485_Info.POLL_Start = Change_Dev;
break;
default:
Poll485_Info.POLL_Start = Change_Dev;
break;
}
/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD>Ǵ<EFBFBD><C7B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>£<EFBFBD><C2A3><EFBFBD>ʱ<EFBFBD>ع<EFBFBD><D8B9><EFBFBD><EFBFBD><EFBFBD>ģʽ*/
if(Poll485_Info.port_mode != Port_Normal_Mode)
{
if(SysTick_1s - Poll485_Info.mode_tick > Poll485_Info.mode_outtime)
{
Poll485_Info.mode_tick = SysTick_1s;
Poll485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
}
}
}
/*******************************************************************************
* Function Name : Poll485Port_Passthrough_Task
* Description : PollPort <EFBFBD><EFBFBD>ѯ<EFBFBD>˿<EFBFBD>͸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Poll485Port_Passthrough_Task(void)
{
uint16_t data_len = 0;
switch(Poll485_Info.pass_state)
{
case B_IDLE: //<2F><><EFBFBD><EFBFBD>״̬ - <20>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD>·<EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len);
Udp_Internal_SeriaNet_Uploading(Polling_Port,Poll485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr;
}
if(g_uart[UART_0].TX_Buffer_WriteAddr != g_uart[UART_0].TX_Buffer_ReadAddr)
{
/*<2A><>ȡ<EFBFBD><C8A1><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD> - <20>·<EFBFBD>*/
data_len = SRAM_Read_Word(g_uart[UART_0].TX_Buffer_ReadAddr);
Poll485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_0].TX_Buffer_ReadAddr + 2); //<2F><>λ<EFBFBD><CEBB>S
if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
Poll485_Info.pass_tick = SysTick_1s;
MCU485_SendSRAMData(Polling_Port,g_uart[UART_0].TX_Buffer_ReadAddr + 3,data_len); //<2F>·<EFBFBD>
Poll485_Info.pass_state = Wait_Reply;
g_uart[UART_0].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].TX_Buffer_ReadAddr > SRAM_UART0_SendBuffer_End_Addr) g_uart[UART_0].TX_Buffer_ReadAddr = SRAM_UART0_SendBuffer_Start_Addr;
}
if(SysTick_1s - Poll485_Info.mode_tick > Poll485_Info.mode_outtime)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Poll485_Info Port_Normal_Mode mode_outtime");
Poll485_Info.mode_tick = SysTick_1s;
Poll485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
if(Poll485_Info.baud != Polling_Baud) //<2F><><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>
{
Poll485_Info.baud = Polling_Baud;
Poll485_Info.BaudRateCfg(Poll485_Info.baud);
}
}
break;
case Wait_Reply: //<2F>ȴ<EFBFBD><C8B4>ظ<EFBFBD> - <20>ظ<EFBFBD><D8B8><EFBFBD>ʱ<EFBFBD>Ļ<EFBFBD> - <20>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len);
Udp_Internal_SeriaNet_Uploading(Polling_Port,Act485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr);
Poll485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr;
}
if(g_uart[UART_0].TX_Buffer_WriteAddr != g_uart[UART_0].TX_Buffer_ReadAddr)
{
/*<2A><>ȡ<EFBFBD><C8A1><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD> - <20>·<EFBFBD>*/
data_len = SRAM_Read_Word(g_uart[UART_0].TX_Buffer_ReadAddr);
Poll485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_0].TX_Buffer_ReadAddr + 2); //<2F><>λ<EFBFBD><CEBB>S
if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
Poll485_Info.pass_tick = SysTick_1s;
MCU485_SendSRAMData(Polling_Port,g_uart[UART_0].TX_Buffer_ReadAddr + 3,data_len); //<2F>·<EFBFBD>
Poll485_Info.pass_state = Wait_Reply;
g_uart[UART_0].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].TX_Buffer_ReadAddr > SRAM_UART0_SendBuffer_End_Addr) g_uart[UART_0].TX_Buffer_ReadAddr = SRAM_UART0_SendBuffer_Start_Addr;
}
if(SysTick_1s - Poll485_Info.pass_tick > Poll485_Info.pass_outtime)
{
//<2F>ظ<EFBFBD><D8B8><EFBFBD>ʱ
Udp_Internal_SeriaNet_Response_Timeout();
Poll485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
}
break;
default:
Poll485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
break;
}
}
/*******************************************************************************
* Function Name : BLV_PollPort_ModeTask
* Description : PollPort Poll<EFBFBD>˿<EFBFBD>ģʽ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_PollPort_ModeTask(void)
{
uint16_t data_len = 0,rev = 0;
if((g_pc_test.test_flag == 0x03) || (g_pc_test.test_flag == 0x13))
{
if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr);
rev = BLV_PC_TEST_TOUR_DATACheck(g_uart[UART_0].RX_Buffer_ReadAddr+2,data_len);
if(rev == 0x00) {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Poll Port <20><><EFBFBD><EFBFBD>Ѳ<EFBFBD><D1B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>\r\n");
g_pc_test.tour_succ++; //<2F><>Ѳ<EFBFBD><D1B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>!\r\n");
}
g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr;
}
return; //<2F><><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
switch(Poll485_Info.port_mode)
{
case Port_Passthrough_mode:
Poll485Port_Passthrough_Task(); //͸<><CDB8>ģʽ
break;
case Port_Normal_Mode:
case Port_Monitoring_mode:
BLV_PollPort_Task(); //<2F><><EFBFBD><EFBFBD>ģʽ <20>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>¼<EFBFBD><C2BC><EFBFBD>ģʽ
break;
}
}
/*******************************************************************************
* Function Name : BLV_ActivePort_Task
* Description : ActivePort <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_ActivePort_Task(void)
{
static uint32_t BLV_Act_Wait = 0;
uint16_t data_len_1 = 0;
switch(Act485_Info.Act_Start)
{
case B_IDLE: //<2F><><EFBFBD><EFBFBD>״̬
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr)
{
data_len_1 = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr);
if((Act485_Info.n_processing_cf!=0x00000000) && (Act485_Info.n_processing_cf!=0xFFFFFFFF)) {
Act485_Info.Retry_Flag = ((fun2_prt)Act485_Info.n_processing_cf)(Act485_Info.Last_list_addr,g_uart[UART_2].RX_Buffer_ReadAddr + 2,data_len_1);
}
if(Act485_Info.Retry_Flag == 0x00) {
if(Act485_Info.Last_list_addr == Act485_Info.n_list_read_addr)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"A Reply SUCC");
Act485_Info.Send_Flag = 0x00;
Act485_Info.Act_Start = B_Send; //<2F>ظ<EFBFBD><D8B8>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>߿<EFBFBD><DFBF>У<EFBFBD><D0A3><EFBFBD><EFBFBD>л<EFBFBD>Ϊ<EFBFBD><CEAA>һ<EFBFBD><D2BB><EFBFBD>豸
}else{
//<2F><>ǰ<EFBFBD><C7B0><EFBFBD>ݲ<EFBFBD><DDB2>ǻظ<C7BB><D8B8><EFBFBD><EFBFBD><EFBFBD> <20><> <20>л<EFBFBD><D0BB>ط<EFBFBD><D8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8>Ϣ
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Not Dev Data");
Act485_Info.Act_Start = Read_Dev;
}
Act485_Info.process_num = 0;
if(Act485_Info.port_mode == Port_Monitoring_mode) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>ģʽ<C4A3><CABD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>PC<50><43>
{
Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
}
/*<2A><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD>ն<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַƫ<D6B7><C6AB>*/
g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) {
g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr;
}
}else {
Act485_Info.process_num ++;
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Data parsing failed :%d" , Act485_Info.process_num);
Act485_Info.Act_Start = Change_Dev;//<2F><><EFBFBD>ǵ<EFBFBD>ǰ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
if(Act485_Info.process_num >= Act485_Info.device_num)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"wipe cache partition:%d",Act485_Info.device_num);
Act485_Info.Act_Start = B_IDLE;
Act485_Info.process_num = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Act485_Info.Retry_Flag = 0; //<2F><><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD>־
if(Act485_Info.port_mode == Port_Monitoring_mode) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>ģʽ<C4A3><CABD>,<2C><><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD>PC<50><43>
{
Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
}
g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) {
g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr;
}
}
}else{
if(SysTick_1ms - BLV_Act_Wait > Act485_Info.send_wait)
{
if((Act485_Info.Send_Flag == RS485OCCUPYTIME) && (Act485_Info.Last_list_addr == Act485_Info.n_list_read_addr))
{
Act485_Info.Send_Flag = RS485OCCUPYNOTIME; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Act485_Info.Act_Start = B_Send; //<2F><><EFBFBD><EFBFBD><EFBFBD>ع鷢<D8B9><E9B7A2>״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>
}else {
/*
1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰû<EFBFBD><EFBFBD><EFBFBD>ݷ<EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD>л<EFBFBD><EFBFBD>豸
2<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD>Ƿ<EFBFBD>
*/
Act485_Info.Act_Start = Change_Dev;
}
}
}
break;
case B_Send: //<2F><><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD>״̬
Act485_Info.n_list_read_addr = Act485_Info.Last_list_addr;
/*<2A><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>ͺ<EFBFBD><CDBA><EFBFBD>*/
if((Act485_Info.n_polling_cf!=0x00000000) && (Act485_Info.n_polling_cf!=0xFFFFFFFF)) {
Act485_Info.Send_Flag = ((fun4_prt)Act485_Info.n_polling_cf)(Act485_Info.n_list_read_addr);
}
Act485_Info.Retry_Flag = 0x00;
BLV_Act_Wait = SysTick_1ms;
if(Act485_Info.Send_Flag == RS485OCCUPYTIME)
{
Act485_Info.send_wait = Act485_Info.n_dev_waittime;
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Send Data\r\n");
} else{
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Not Data\r\n");
Act485_Info.send_wait = 5; //<2F>л<EFBFBD><D0BB>豸ʱ<E8B1B8><CAB1>
}
Act485_Info.Act_Start = B_IDLE;
break;
case Change_Dev: //<2F>л<EFBFBD><D0BB>豸
if(Act485_Info.list_read_addr != 0x00)
{
Act485_Info.Last_list_addr = Act485_Info.list_read_addr;
Act485_Info.list_read_addr = 0x00;
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - list_read_addr:%08X\r\n",Act485_Info.Last_list_addr);
}else{
Act485_Info.Last_list_addr += SRAM_Device_List_Size;
}
if((Act485_Info.Last_list_addr >= SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr)) || (Act485_Info.Last_list_addr >= SRAM_Device_List_End_Addr)) Act485_Info.Last_list_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr);
/*У<><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ȡ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>*/
if(Device_Data_Check(Act485_Info.Last_list_addr) == 0)
{
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Read_Dev SUCC\r\n");
/*<2A><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ*/
Device_Public_Information_G dev_info;
SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Act485_Info.Last_list_addr);
Act485_Info.n_polling_cf = dev_info.polling_cf;
Act485_Info.n_processing_cf = dev_info.processing_cf;
Act485_Info.n_dev_waittime = dev_info.wait_time;
Act485_Info.n_retry_num = dev_info.retry_num;
if(Act485_Info.Retry_Flag == 0x00) Act485_Info.Act_Start = B_Send;
else Act485_Info.Act_Start = B_IDLE;
}else{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%s - Read_Dev Fail: %08X",__func__,Act485_Info.Last_list_addr);
}
break;
case Read_Dev:
if(Device_Data_Check(Act485_Info.n_list_read_addr) == 0)
{
/*<2A><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8>Ϣ*/
Device_Public_Information_G dev_info;
SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Act485_Info.n_list_read_addr);
Act485_Info.n_polling_cf = dev_info.polling_cf;
Act485_Info.n_processing_cf = dev_info.processing_cf;
Act485_Info.n_dev_waittime = dev_info.wait_time;
Act485_Info.n_retry_num = dev_info.retry_num;
Act485_Info.Last_list_addr = Act485_Info.n_list_read_addr; //<2F><>һ<EFBFBD><D2BB><EFBFBD>豸ָ<E8B1B8><D6B8><EFBFBD><EFBFBD>λ
Act485_Info.Act_Start = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>
}else {
Act485_Info.Act_Start = Change_Dev;
}
break;
default:
Act485_Info.Act_Start = B_IDLE;
break;
}
/*<2A><>ǰ<EFBFBD><C7B0><EFBFBD>Ǵ<EFBFBD><C7B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>£<EFBFBD><C2A3><EFBFBD>ʱ<EFBFBD>ع<EFBFBD><D8B9><EFBFBD><EFBFBD><EFBFBD>ģʽ*/
if(Act485_Info.port_mode != Port_Normal_Mode)
{
if(SysTick_1s - Act485_Info.mode_tick > Act485_Info.mode_outtime)
{
Act485_Info.mode_tick = SysTick_1s;
Act485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
}
}
}
/*******************************************************************************
* Function Name : Act485Port_Passthrough_Task
* Description : ActivePort <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD>͸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Act485Port_Passthrough_Task(void)
{
uint16_t data_len = 0;
switch(Act485_Info.pass_state)
{
case B_IDLE: //<2F><><EFBFBD><EFBFBD>״̬ - <20>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD>·<EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d" , data_len);
Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //<2F>ϱ<EFBFBD>
g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr;
}
if(g_uart[UART_2].TX_Buffer_WriteAddr != g_uart[UART_2].TX_Buffer_ReadAddr)
{
/*<2A><>ȡ<EFBFBD><C8A1><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD> - <20>·<EFBFBD>*/
data_len = SRAM_Read_Word(g_uart[UART_2].TX_Buffer_ReadAddr);
Act485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_2].TX_Buffer_ReadAddr + 2); //<2F><>λ<EFBFBD><CEBB>S
if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
Act485_Info.pass_tick = SysTick_1s;
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d" , data_len);
MCU485_SendSRAMData(Active_Port,g_uart[UART_2].TX_Buffer_ReadAddr + 3,data_len); //<2F>·<EFBFBD>
Act485_Info.pass_state = Wait_Reply;
g_uart[UART_2].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_2].TX_Buffer_ReadAddr > SRAM_UART2_SendBuffer_End_Addr) g_uart[UART_2].TX_Buffer_ReadAddr = SRAM_UART2_SendBuffer_Start_Addr;
}
if(SysTick_1s - Act485_Info.mode_tick > Act485_Info.mode_outtime)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Act485_Info Port_Normal_Mode mode_outtime");
Act485_Info.mode_tick = SysTick_1s;
Act485_Info.port_mode = Port_Normal_Mode; //<2F><><EFBFBD><EFBFBD>ģʽ
if(Act485_Info.baud != Active_Baud) //<2F><><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Act485_Info.baud:%d",Act485_Info.baud);
Act485_Info.baud = Active_Baud;
Act485_Info.BaudRateCfg(Act485_Info.baud);
}
}
break;
case Wait_Reply: //<2F>ȴ<EFBFBD><C8B4>ظ<EFBFBD> - <20>ظ<EFBFBD><D8B8><EFBFBD>ʱ<EFBFBD>Ļ<EFBFBD> - <20>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/*<2A><><EFBFBD>մ<EFBFBD><D5B4><EFBFBD>*/
if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr)
{
data_len = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr);
Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len);
Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr);
Act485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size;
if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr;
}
if(SysTick_1s - Act485_Info.pass_tick > Act485_Info.pass_outtime)
{
//<2F>ظ<EFBFBD><D8B8><EFBFBD>ʱ
Udp_Internal_SeriaNet_Response_Timeout();
Act485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
}
break;
default:
Act485_Info.pass_state = B_IDLE; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
break;
}
}
/*******************************************************************************
* Function Name : BLV_ActivePort_ModeTask
* Description : ActivePort Active<EFBFBD>˿<EFBFBD>ģʽ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_ActivePort_ModeTask(void)
{
switch(Act485_Info.port_mode)
{
case Port_Passthrough_mode:
Act485Port_Passthrough_Task(); //͸<><CDB8>ģʽ
break;
case Port_Normal_Mode:
case Port_Monitoring_mode:
BLV_ActivePort_Task(); //<2F><><EFBFBD><EFBFBD>ģʽ <20>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>¼<EFBFBD><C2BC><EFBFBD>ģʽ
break;
}
}
/*******************************************************************************
* Function Name : BLV_Active_Set_List_Addr
* Description : ActivePort <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_Active_Set_List_Addr(uint32_t addr)
{
Act485_Info.list_read_addr = addr;
Act485_Info.Act_Start = Change_Dev;
}
/*******************************************************************************
* Function Name : Find_Device_List_Information
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint32_t Find_Device_List_Information(uint8_t dev_type,uint8_t addr)
{
uint32_t read_addr = SRAM_Device_List_Start_Addr;
uint32_t end_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr);
//Dbg_Println(DBG_OPT_DEVICE_STATUS,"Find Device:%08x",end_addr);
if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr;
for(uint32_t i=SRAM_Device_List_Start_Addr;i<end_addr;)
{
if((SRAM_Read_Byte(read_addr + Dev_Type) == dev_type) && (SRAM_Read_Byte(read_addr + Dev_Addr) == addr))
{
if(Device_Data_Check(read_addr) == 0)
{
return read_addr;
}
}
read_addr += SRAM_Device_List_Size;
i+= SRAM_Device_List_Size;
if(read_addr >= end_addr)
{
return 0x00;
}
}
return 0x00;
}
/*******************************************************************************
* Function Name : Find_AllDevice_List_Information
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>豸
* Input :
* dev_type - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* addr - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ĵ<EFBFBD>ַ
* Return : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ַ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint32_t Find_AllDevice_List_Information(uint8_t dev_type,uint8_t addr)
{
uint32_t read_addr = SRAM_Device_List_Start_Addr;
uint32_t end_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr);
if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr;
for(uint32_t i=SRAM_Device_List_Start_Addr;i<end_addr;)
{
if((SRAM_Read_Byte(read_addr + Dev_Type) == dev_type) && (SRAM_Read_Byte(read_addr + Dev_Addr) == addr))
{
if(Device_Data_Check(read_addr) == 0)
{
return read_addr;
}
}
read_addr += SRAM_Device_List_Size;
i+= SRAM_Device_List_Size;
if(read_addr >= end_addr)
{
return 0x00;
}
}
return 0x00;
}
/*******************************************************************************
* Function Name : Find_AllDevice_List_Information2
* Description : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD>豸
* Input :
* Port - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>Ķ˿<EFBFBD>
* dev_type - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* addr - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ĵ<EFBFBD>ַ
* Return : <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ַ
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint32_t Find_AllDevice_List_Information2(uint8_t Port, uint8_t dev_type,uint8_t addr)
{
uint16_t i = 0;
uint32_t read_addr = 0x00;
switch(Port)
{
case Active_Port:
i = BUS485_Info.device_num + Poll485_Info.device_num;
break;
case Polling_Port:
i = BUS485_Info.device_num;
break;
case Bus_port:
i = 0;
break;
}
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"δ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:%d<><64><EFBFBD>±<EFBFBD>:%d", (BUS485_Info.device_num+Poll485_Info.device_num+Act485_Info.device_num), i);
for(; i < (BUS485_Info.device_num+Poll485_Info.device_num+Act485_Info.device_num); i++)
{
read_addr = SRAM_Device_List_Start_Addr + i*SRAM_Device_List_Size;
if((SRAM_Read_Byte(read_addr + Dev_Type) == dev_type) && (SRAM_Read_Byte(read_addr + Dev_Addr) == addr))
{
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"<EFBFBD>ҵ<EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD>豸");
// if(Device_Data_Check(read_addr) == 0)
{
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"<EFBFBD><EFBFBD>ǰ<EFBFBD>豸У<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>%04x", read_addr);
return read_addr;
}
}
}
return 0x00; //δ<>ҵ<EFBFBD><D2B5>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ؿ<EFBFBD>ָ<EFBFBD><D6B8>
}
/*******************************************************************************
* Function Name : Find_The_Number_Of_Device_In_The_List
* Description : <EFBFBD><EFBFBD>ѯ<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint8_t Find_The_Number_Of_Device_In_The_List(void)
{
uint32_t read_addr = SRAM_Device_List_Start_Addr;
uint32_t end_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
uint8_t temp_num = 0;
uint32_t temp_len = 0;
temp_len = end_addr - read_addr;
temp_num = (temp_len / SRAM_Device_List_Size) & 0xFF;
return temp_num;
}
/*<2A><>ȡ<EFBFBD>豸ȫ<E8B1B8><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬*/
__attribute__((section(".non_0_wait"))) uint8_t Gets_the_state_of_all_devices(uint8_t *data_buff,uint8_t num)
{
uint8_t dev_type = 0,dev_addr = 0,dev_online = 0;
uint32_t read_addr = SRAM_Device_List_Start_Addr;
uint32_t end_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr);
if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr;
for(uint8_t i=0;i<num;i++)
{
if(Device_Data_Check(read_addr) == 0)
{
dev_type = SRAM_Read_Byte(read_addr + Dev_Type);
dev_addr = SRAM_Read_Byte(read_addr + Dev_Addr);
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬*/
switch(dev_type)
{
case DEV_C5IO_Type:
dev_online = Get_BUS_C5IO_Online_Status(read_addr);
break;
case DEV_C5MUSIC_Type:
dev_online = Get_BUS_C5MUSIC_Online_Status(read_addr);
break;
case DEV_RS485_TEMP:
dev_online = Get_BLV485_TEMP_Online_Status(read_addr);
break;
case DEV_RS485_CARD:
dev_online = Get_BLV485_CARD_Online_Status(read_addr);
break;
case DEV_RS485_SWT:
dev_online = Get_Switch_Online_Status(read_addr);
break;
case Dev_Rs458_RotaryCtrl: //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ť<EFBFBD><C5A5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD>¹<EFBFBD><C2B9><EFBFBD>
//dev_online = Get_Rotary_Switch_Online_Status(read_addr);
break;
}
data_buff[i*3+0] = dev_type;
data_buff[i*3+1] = dev_addr;
data_buff[i*3+2] = dev_online;
}else {
return 0xF0; //<2F><>ȡʧ<C8A1><CAA7>
}
read_addr += SRAM_Device_List_Size;
if(read_addr >= end_addr)
{
return 0x00;
}
}
return 0x00;
}
/*******************************************************************************
* @brief д<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD><EFBFBD>SRAM
* @param
* device_type <EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* device_addr <EFBFBD>豸<EFBFBD><EFBFBD>ַ
* fault_type <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* fault_state <EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
* @retval None
* @attention һ<EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>485<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ַ 2<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽڹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽڹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Write_Device_Fault_State(
uint8_t device_type,
uint8_t device_addr,
uint8_t fault_type,
uint8_t fault_state)
{
uint8_t data[6]; //<2F><><EFBFBD>ڱ<EFBFBD><DAB1><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint32_t write_addr = 0x00,read_addr = 0x00; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬д<CCAC><D0B4><EFBFBD><EFBFBD>ַ
uint8_t len = 0;
//<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ַ
write_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR);
read_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_READ_ADDR);
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>κ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ֱַ<D6B7>Ӹ<EFBFBD>λ
if( (write_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) \
|| (read_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (read_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) )
{
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
read_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR);
SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_READ_ADDR);
SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR);
}
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s SRAM addr:%08X",__func__, write_addr);
memset(data,0x00,6); //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>0
data[0] = device_type; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
data[1] = device_addr; //<2F>豸<EFBFBD><E8B1B8>ַ
data[4] = fault_type; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
data[5] = fault_state; //<2F><><EFBFBD><EFBFBD>״̬
if( (write_addr + 0x06) > SRAM_DEVICE_ONLINE_STATE_END_ADDR )
{
Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep_1 %08X!!!",__func__,write_addr);
len = SRAM_DEVICE_ONLINE_STATE_END_ADDR - write_addr;
SRAM_DMA_Write_Buff(data,len,write_addr);
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
SRAM_DMA_Write_Buff(&data[len],(6-len),write_addr);
write_addr += (6-len);
}else {
SRAM_DMA_Write_Buff(data, 6, write_addr); //д<><D0B4><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
write_addr += 0x06; //<2F><>ַƫ<D6B7><C6AB>
}
if(write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR)
{
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s overstep:%08X",__func__,write_addr);
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
}
SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬д<CCAC><D0B4><EFBFBD><EFBFBD>ַ
//Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Write Fault Data:%02X %02X %02X %02X %02X %02X\r\n",data[0],data[1],data[2],data[3],data[4],data[5]);
}
/*******************************************************************************
* @brief д<EFBFBD>豸<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD><EFBFBD>SRAM
* @param
* device_type <EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* device_addr <EFBFBD>豸<EFBFBD><EFBFBD>ַ
* fault_type <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* fault_state <EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
* @retval None
* @attention һ<EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>485<EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ַ 2<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽڹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 1<EFBFBD><EFBFBD><EFBFBD>ֽڹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void Write_Device_Loop_Fault_State(
uint8_t device_type,
uint8_t device_addr,
uint8_t fault_type,
uint8_t fault_state,
uint16_t loop)
{
uint8_t data[6]; //<2F><><EFBFBD>ڱ<EFBFBD><DAB1><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint32_t write_addr = 0x00,read_addr = 0x00; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬д<CCAC><D0B4><EFBFBD><EFBFBD>ַ
uint8_t len = 0;
//<2F><>ȡ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ַ
write_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR);
read_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_READ_ADDR);
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1>ַ<EFBFBD>κ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ֱַ<D6B7>Ӹ<EFBFBD>λ
if( (write_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) \
|| (read_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (read_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) )
{
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
read_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR);
SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_READ_ADDR);
SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR);
}
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s SRAM addr:%08X",__func__, write_addr);
memset(data,0x00,6); //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2>0
data[0] = device_type; //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
data[1] = device_addr; //<2F>豸<EFBFBD><E8B1B8>ַ
data[2] = (loop & 0xFF);
data[3] = ((loop >> 8) & 0xFF);
data[4] = fault_type; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
data[5] = fault_state; //<2F><><EFBFBD><EFBFBD>״̬
if( (write_addr + 0x06) > SRAM_DEVICE_ONLINE_STATE_END_ADDR )
{
Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep_1 %08X!!!",__func__,write_addr);
len = SRAM_DEVICE_ONLINE_STATE_END_ADDR - write_addr;
SRAM_DMA_Write_Buff(data,len,write_addr);
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
SRAM_DMA_Write_Buff(&data[len],(6-len),write_addr);
write_addr += (6-len);
}else {
SRAM_DMA_Write_Buff(data, 6, write_addr); //д<><D0B4><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
write_addr += 0x06; //<2F><>ַƫ<D6B7><C6AB>
}
if(write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR)
{
Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s overstep:%08X",__func__,write_addr);
write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR;
}
SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); //<2F><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>״̬д<CCAC><D0B4><EFBFBD><EFBFBD>ַ
}
/*******************************************************************************
* Function Name : BLV_Communication_Record
* Description : BUSͨѶ<EFBFBD><EFBFBD>¼
* Input :
dev_record :ͨѶ<EFBFBD><EFBFBD>¼<EFBFBD>ṹ<EFBFBD><EFBFBD>
option :<EFBFBD><EFBFBD>¼ѡ<EFBFBD><EFBFBD>
0x01:<EFBFBD><EFBFBD>¼ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
0x02:<EFBFBD><EFBFBD>¼ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
state :
ѡ<EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>¼ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
ѡ<EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>¼ͨѶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><EFBFBD><EFBFBD>Ϊ0x00<EFBFBD><EFBFBD>ͨѶʧ<EFBFBD>ܣ<EFBFBD>0x01<EFBFBD><EFBFBD>ͨѶ<EFBFBD>ɹ<EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void BLV_Communication_Record(
BLV_COMM_RECORD_G *dev_record,
uint8_t option,
uint8_t state)
{
switch(option)
{
case 0x01:
if(dev_record->num >= BLV_COMM_RecordNum*8)
{
// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶ<CDA8><D1B6>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>");
dev_record->full_flag = 0x01;
dev_record->num = 0;
}
dev_record->num++;
dev_record->continue_fail_num++;
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶ<CDA8><D1B6>¼<EFBFBD><C2BC>:%d",dev_record->num);
dev_record->record[(dev_record->num-1)/8] &= ~((0x01 << ((dev_record->num-1)%8)));
//Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"ͨѶBUFF<46><46>",dev_record->record,BLV_COMM_RecordNum);
break;
case 0x02:
if(state == 0x01)
{
//Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶ<CDA8>ɹ<EFBFBD><C9B9><EFBFBD>:%d",dev_record->num);
dev_record->continue_fail_num = 0;
dev_record->record[(dev_record->num-1)/8] |= (0x01 << ((dev_record->num-1)%8));
}
break;
}
}
/*******************************************************************************
* Function Name : Get_BLV_Communication_Succ_Rate
* Description : <EFBFBD><EFBFBD>ȡͨѶʧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD>ͳ<EFBFBD>Ƶ<EFBFBD>ͨѶ<EFBFBD>е<EFBFBD>ʧ<EFBFBD><EFBFBD>)
* Return <EFBFBD><EFBFBD>ʧ<EFBFBD>ܰٷֱ<EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint16_t Get_BLV_Communication_Fail_Rate(BLV_COMM_RECORD_G *dev_record)
{
uint8_t temp = 0;
uint16_t fail_num = 0,sum = 0,precent = 0;
if(dev_record->full_flag == 0x01) sum = BLV_COMM_RecordNum*8; //<2F><>ǰ<EFBFBD><C7B0>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>
else sum = dev_record->num; //<2F><>ǰû<C7B0>м<EFBFBD>¼δ<C2BC><CEB4>
for(uint16_t i=0;i<sum;i++)
{
temp = (dev_record->record[i/8] >> (i%8)) & 0x01;
if(temp == 0x00) fail_num++; //ʧ<>ܴ<EFBFBD><DCB4><EFBFBD><EFBFBD><EFBFBD>һ
}
precent = (fail_num*100)/sum;
return precent;
}
Reference in New Issue Copy Permalink