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feat:网络升级流程完善

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1、局域网升级流程 - 初步测试OK
2、云端升级流程 - 初步测试OK
3、云端升级上报升级进度 - 初步测试OK
This commit is contained in:
caocong
2026-02-10 17:45:08 +08:00
parent f16825ea2b
commit 3041468aa7
23 changed files with 1184 additions and 336 deletions
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15
MCU_Driver/inc/blv_netcomm_function.h
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@@ -40,6 +40,8 @@
#define In_Power_Change_Cmd 0x35 //ȡ<><C8A1>״̬<D7B4>ϱ<EFBFBD> 2025-09-25 <20><><EFBFBD><EFBFBD>
#define In_DevState_Cmd 0x36 //<2F>豸״̬<D7B4>ϱ<EFBFBD> 2025-09-25 <20><><EFBFBD><EFBFBD>
#define In_Cloud_IAP_Cmd 0x68 //<2F>ƶ<EFBFBD>IAP<41><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define In_SeriaNet_Cmd 0x70 //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD>
#define In_SeriaNetReported_Cmd 0x71 //͸<><CDB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD>
@@ -75,6 +77,12 @@
#define UDP_ActSend_TimeSync_Flag 0x20 //UDP<44><50><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD> - ʱ<><CAB1>ͬ<EFBFBD><CDAC> <20><>־λ
#define UDP_ActSend_Heart_Flag 0x40 //UDP<44><50><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>־λ
#define IAPPlan_State_Starting 0x01 //<2F><><EFBFBD><EFBFBD>״̬ - <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define IAPPlan_State_Underway 0x02 //<2F><><EFBFBD><EFBFBD>״̬ - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define IAPPlan_State_Checking 0x03 //<2F><><EFBFBD><EFBFBD>״̬ - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD>
#define IAPPlan_State_CheckSucc 0x04 //<2F><><EFBFBD><EFBFBD>״̬ - У<><D0A3><EFBFBD>ɹ<EFBFBD>,RCU<43><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define IAPPlan_State_IAPTimeout 0x05 //<2F><><EFBFBD><EFBFBD>״̬ - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
#define USER_NET_Register_Timeout 30 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>ʱ,<2C><>λ<EFBFBD><CEBB>S
#define USER_NET_Send_Timeout 20 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵȴ<DDB5><C8B4>ظ<EFBFBD>ʱ<EFBFBD><CAB1>,<2C><>λ<EFBFBD><CEBB>S
#define USER_NET_Register_Times 10 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CDB4><EFBFBD>
@@ -96,8 +104,15 @@ uint8_t Udp_Internal_SeriaNet_Uploading(uint8_t port,uint32_t baud,uint32_t data
uint8_t Udp_Internal_SeriaNet_Uploading2(uint8_t port,uint32_t baud,uint8_t* data, uint16_t DataLen);
uint8_t Udp_Internal_SeriaNet_Response_Timeout(void);
uint8_t UDP_BLVIAPPlan_Cmd_SendPack(uint8_t iap_state);
uint8_t UDP_ReplyIAP_SendPack(void);
uint8_t UDP_ReplyCloudIAP_SendPack(void);
void Udp_Internal_Analysis(uint8_t *data, uint32_t len, uint8_t* ip, uint16_t port);
void BLV_UDP_Comm_Task(void);
#endif /* MCU_DRIVER_INC_BLV_NETCOMM_FUNCTION_H_ */

6
MCU_Driver/inc/flash_mem_addr.h
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@@ -20,9 +20,11 @@
#define SPIFLASH_APP_FEATURE_Addr 0x00000000 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 512Byte
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000200 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ - 512Byte
#define SPIFLASH_UPDATE_FLAG_Addr 0x00000200 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ - 512Byte
#define SPIFLASH_UPDATE_RECORD_Addr 0x00000400 //д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʊ<EFBFBD><C6B1><EFBFBD><EFBFBD><EFBFBD>ַ
#define SPIFLASH_APP_Data_Start_Addr 0x00004000
#define SPIFLASH_APP_Data_Start_Addr 0x00001000
#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF
#define SPIFLASH_APP_End_Addr 0x0006FFFF

12
MCU_Driver/inc/mcu_flash.h
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@@ -19,13 +19,13 @@
#define App_Procedure_Not_Ready 0x44 //Appδ׼<CEB4><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ
//MCU Flash Address range(0x0 -- 0x6FFFF) Size(448K)
#define MCU_APP_Flash_Start_Addr 0x00007000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_Start_Addr 0x00007000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_End_Addr 0x00027DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_Addr 0x00027E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_End_Addr 0x00027FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_Start_Addr 0x00001000 //MCU Flash<73><68>APP<50><50><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_Start_Addr 0x00001000 //MCU Flash APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
#define MCU_APP_Data_End_Addr 0x00067DFF //MCU Flash APP<50><50><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_Addr 0x00067E00 //MCU Flash <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Flash_End_Addr 0x00067FFF //MCU Flash<73><68>APP<50>Ľ<EFBFBD><C4BD><EFBFBD><EFBFBD><EFBFBD>ַ
#define MCU_APP_Feature_PageAddr 0x00027000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
#define MCU_APP_Feature_PageAddr 0x00067000 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ҳ<EFBFBD>ĵ<EFBFBD>ַ
#define MCU_APP_Feature_PageOffset 0x00000E00 //MCU APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>
#define APP_FEATURE_SIZE 0x0200 //512Byte

55
MCU_Driver/inc/sram_mem_addr.h
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@@ -116,7 +116,8 @@
/*<2A><>¼Launcher<65>汾<EFBFBD><E6B1BE>Ϣ <20><>С<EFBFBD><D0A1>0x20 2025-07-07*/
#define SRAM_Launcher_SoftwareVer_Addr 0x0000E800
/*Launcherʹ<72><CAB9> <20><><EFBFBD>ڼ<EFBFBD>¼APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> <20><>С:0x10 2026-01-14*/
#define SRAM_APP_Write_Count_Addr 0x0000E900
/**********SRAM Uart<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_Uart_Buffer_Size 0x0400 //<2F><><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>С
@@ -170,19 +171,9 @@
#define SRAM_VCard_Property_Start_Addr 0x0004D000 //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>1K
#define SRAM_VCard_Property_End_Addr 0x0004D3FF //<2F>޿<EFBFBD>ȡ<EFBFBD><C8A1> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD>
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_IAP_APP_FILE_ADDRESS 0x00050000 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50>ļ<EFBFBD><C4BC>ĵ<EFBFBD>ַ - 218K
#define SRAM_IAP_IP_ADDRESS 0x0008E600 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>IP - 4Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_PORT_ADDRESS 0x0008E604 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>port - 2Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_NET_UPGRADE_Flag_ADDRESS 0x0008E606 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ - 1Byte
#define SRAM_IAP_UPGRADE_Reply_NUM_ADDRESS 0x0008E607 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD>APP<50><50>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD> - 1Byte
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/**********<2A><>Ŀӳ<C4BF><D3B3><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_Register_Start_ADDRESS 0x0008E900
#define SRAM_Register_End_ADDRESS 0x0008EFFF
#define SRAM_Register_Start_ADDRESS 0x0004E000
#define SRAM_Register_End_ADDRESS 0x0004EFFF
#define Register_OFFSET_LEN 0x0400 //<2F><>ǰ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ռ䳤<D5BC><E4B3A4> - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˣ<EFBFBD><CBA3>ⳤ<EFBFBD><E2B3A4>ҲӦ<D2B2>ñ仯
//<2F><>Ŀ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
@@ -222,29 +213,39 @@
#define Register_TFTPDmName_OFFSET 0x0185 //TFTP<54><50>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - 64Byte
/**********<2A><>Ŀӳ<C4BF><D3B3><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_IAP_APP_FILE_ADDRESS 0x00100000 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50>ļ<EFBFBD> <20><>ʼ<EFBFBD><CABC>ַ - 412K
#define SRAM_IAP_APP_FILE_End_ADDRESS 0x00167FFF //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APP<50>ļ<EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define SRAM_IAP_IP_ADDRESS 0x00168000 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>IP - 4Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_PORT_ADDRESS 0x00168004 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>port - 2Byte <20><>ʱ<EFBFBD><CAB1>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD>ſռ䣬<D5BC><E4A3AC><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>͸<EFBFBD><CDB8>UDP<44><50>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
#define SRAM_IAP_NET_UPGRADE_Flag_ADDRESS 0x00168006 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ - 1Byte
#define SRAM_IAP_UPGRADE_Reply_NUM_ADDRESS 0x00168007 //SRAM<41>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8>ķ<EFBFBD><C4B7>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD>APP<50><50>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɵ<EFBFBD><C9B5>ϱ<EFBFBD><CFB1><EFBFBD><EFBFBD><EFBFBD> - 1Byte
#define SRAM_IAP_IAP_Reset_Flag_ADDRESS 0x00168008 //SRAM<41>д<EFBFBD><D0B4>ž<EFBFBD><C5BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ󣬸<C9BA>λ<EFBFBD><CEBB>־λ
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2>ַ <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>·<EFBFBD> <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><>ʼ**********/
#define SRAM_IAP_LOGIC_FILE_ADDRESS 0x00090000 //SRAM<41><4D><EFBFBD>߼<EFBFBD><DFBC>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ
#define SRAM_IAP_LOGIC_FILE_ADDRESS 0x00190000 //SRAM<41><4D><EFBFBD>߼<EFBFBD><DFBC>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ
#define SRAM_IAP_LOGIC_DataFlag_ADDRESS 0x00090000 //<2F>ļ<EFBFBD><C4BC><EFBFBD>־λ - 4Byte
#define SRAM_IAP_LOGIC_DataSize_ADDRESS 0x00090004 //<2F>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> - 4Byte
#define SRAM_IAP_LOGIC_DataMD5_ADDRESS 0x00090008 //<2F>ļ<EFBFBD>MD5У<35><D0A3>ֵ - 16Byte
#define SRAM_IAP_LOGIC_DataFlag_ADDRESS 0x00190000 //<2F>ļ<EFBFBD><C4BC><EFBFBD>־λ - 4Byte
#define SRAM_IAP_LOGIC_DataSize_ADDRESS 0x00190004 //<2F>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> - 4Byte
#define SRAM_IAP_LOGIC_DataMD5_ADDRESS 0x00190008 //<2F>ļ<EFBFBD>MD5У<35><D0A3>ֵ - 16Byte
#define SRAM_IAP_LOGIC_DataStart_ADDRESS 0x00090200
#define SRAM_IAP_LOGIC_DataEnd_ADDRESS 0x000FFFFF
#define SRAM_IAP_LOGIC_DataStart_ADDRESS 0x00190200
#define SRAM_IAP_LOGIC_DataEnd_ADDRESS 0x001FFFFF
/**********SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>·<EFBFBD> <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD> - <20><><EFBFBD><EFBFBD>**********/
#define SRAM_DevAction_List_Size 0x0400 //ÿ<><C3BF><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><DAB5>洢<EFBFBD>ռ<EFBFBD><D5BC><EFBFBD>С - <20><>ǰ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD>
#define SRAM_DevAction_List_Num 950
#define SRAM_DevAction_List_Start_Addr 0x00100000 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>960K
#define SRAM_DevAction_List_End_Addr 0x001EFFFF //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_BlwMap_List_Start_Addr 0x001F0000 //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>32K
#define SRAM_BlwMap_List_End_Addr 0x001F7FFF //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_DevDly_List_Start_Addr 0x001F8000 //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8>ʼ<EFBFBD><CABC>ַ һ<><D2BB>32K
#define SRAM_DevDly_List_End_Addr 0x001FFFFF //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define SRAM_DevAction_List_Start_Addr 0x00200000 //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>960K
#define SRAM_DevAction_List_End_Addr 0x002EFFFF //<2F>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_BlwMap_List_Start_Addr 0x002F0000 //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ <20><><EFBFBD><EFBFBD> һ<><D2BB>32K
#define SRAM_BlwMap_List_End_Addr 0x002F7FFF //ӳ<><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SRAM_DevDly_List_Start_Addr 0x002F8000 //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8>ʼ<EFBFBD><CABC>ַ һ<><D2BB>32K
#define SRAM_DevDly_List_End_Addr 0x002FFFFF //<2F><>ʱ<EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ

3
MCU_Driver/inc/watchdog.h
View File

@@ -8,6 +8,9 @@
#ifndef MCU_DRIVER_INC_WATCHDOG_H_
#define MCU_DRIVER_INC_WATCHDOG_H_
#include <stdint.h>
#include "ch564.h"
void WDT_Init(void);
void WDT_Feed(void);
void WDT_Reinit(void);