commit d2d8800788acf851821eff7580682625d0ec97c4 Author: caocong Date: Sat Dec 6 13:49:01 2025 +0800 feat:新建项目文件 BLV主机C1P模块 diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..80bf217 --- /dev/null +++ b/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..bbfa0fd --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +obj diff --git a/.project b/.project new file mode 100644 index 0000000..840cda7 --- /dev/null +++ b/.project @@ -0,0 +1,37 @@ + + + BLV_C1P_20251107 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1692846627047 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/.settings/com.googlecode.cppcheclipse.core.prefs b/.settings/com.googlecode.cppcheclipse.core.prefs new file mode 100644 index 0000000..5bf67ad --- /dev/null +++ b/.settings/com.googlecode.cppcheclipse.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +suppressions=rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;102\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEk1DVV9Ecml2ZXJcZGVidWcuY3cCAFx4;comparePointers;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAE05ldExpYlxldGhfZHJpdmVyLmN3AgBceA\=\=;integerOverflow;500\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAE1VzZXJcc3lzdGVtX2NoNTY0LmN3AgBceA\=\=;integerOverflow;113\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;73\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;131\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;uninitvar;2147483647\!rO0ABXNyAAxqYXZhLmlvLkZpbGUELaRFDg3k/wMAAUwABHBhdGh0ABJMamF2YS9sYW5nL1N0cmluZzt4cHQAEUNvcmVcY29yZV9yaXNjdi5jdwIAXHg\=;legacyUninitvar;2147483647\! diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..1a4b8e6 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 0000000..f34230b --- /dev/null +++ b/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/CPATH/delimiter=; +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/CPATH/operation=remove +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/append=true +environment/buildEnvironmentInclude/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/appendContributed=true +environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/append=true +environment/buildEnvironmentLibrary/ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074/appendContributed=true diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..50f01ad --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +encoding/.cproject=GBK +encoding//Peripheral/inc/ch564.h=UTF-8 diff --git a/.template b/.template new file mode 100644 index 0000000..6498948 --- /dev/null +++ b/.template @@ -0,0 +1,18 @@ +Vendor=WCH +Toolchain=RISC-V +Series=CH564 +RTOS=NoneOS +MCU=CH564F +Link=WCH-Link +PeripheralVersion=====1.2 +Description=====CH564 is an industrial-grade microcontroller based on barley RISC-V core design. CH564 built-in USBHS PHY and PD PHY, support for USB Host host and USB Device device functions, PDUSB and Type-C fast charging; built-in Ethernet controller MAC and 10 megabits/100 megabits physical layer transceiver; provides an external bus interface XBUS, 8-bit passive parallel port SLV, 12-bit analogue-to-digital converter ADC, multi-group timer, 4-group UART serial port, I2C interface, 2 SPI interface and other rich peripheral resources. +Mcu Type=CH564 +Address=0x00000000 +Target Path=obj\BLV_C1P_20250514.hex +CLKSpeed=1 +DebugInterfaceMode=1 +Erase All=true +Program=true +Verify=true +Reset=true +SDIPrintf=false diff --git a/BLV_485_Driver/blv_bus_dev_c5iofun.c b/BLV_485_Driver/blv_bus_dev_c5iofun.c new file mode 100644 index 0000000..ebfbb3c --- /dev/null +++ b/BLV_485_Driver/blv_bus_dev_c5iofun.c @@ -0,0 +1,1493 @@ +/* + * blv_bus_dev_c5iofun.c + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#include "blv_bus_dev_c5iofun.h" +#include "blv_nor_dev_lvinput.h" +#include "sram_mem_addr.h" +#include "spi_sram.h" +#include "log_api.h" +#include "logic_file_function.h" +#include "debug.h" +#include "rtc.h" +#include "check_fun.h" +#include "blv_rs485_protocol.h" +#include "blv_dev_action.h" +#include "pc_devicetest_fun.h" +#include "uart.h" +#include + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_For_Logic_Init +* Description : CSIO豸Ϣʼ - ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_BUS_CSIO_For_Logic_Init( + LOGICFILE_DEVICE_INFO *dev_info, + uint8_t *data, + uint16_t data_len) +{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&C5IO_Info,0,sizeof(BUS_C5IO_INFO)); + + BUS_Public.addr = dev_info->addr; //豸485ַ + BUS_Public.type = DEV_C5IO_Type; //豸 + BUS_Public.port = Bus_port; //豸Ͷ˿ + BUS_Public.baud = 115200; //豸Ͳ + BUS_Public.retry_num = C5IO_REPEATSENDTIMEMAX; //豸ط + BUS_Public.wait_time = C5IO_SEND_WAIT_TIME; //豸ݷ͵ȴظʱ + BUS_Public.polling_cf = (uint32_t)&BLV_BUS_C5IO_Cycle_Call; + BUS_Public.processing_cf = (uint32_t)&BLV_BUS_C5IO_Data_Processing; + + C5IO_Info.DevOffline = C5IO_Info.DevOfflineLast = DEV_IS_LINEUNINIT; //߳ʼ + C5IO_Info.C5IO_Version = 1; + + /*Ĭ϶Ϊ*/ + C5IO_Info.DI_Type[C5IO_DI_CH1] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH2] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH3] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH4] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH5] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH6] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH7] = BUS_C5IO_DI_Key_Type | BUS_C5IO_DI_Level_LOW; // + C5IO_Info.DI_Detection_Time[C5IO_DI_CH1] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH2] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH3] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH4] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH5] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH6] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH7] = 0x02; //ʱΪ20ms + + C5IO_Info.DI_Type[C5IO_DI_CH8] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH9] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH10] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH11] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH12] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + C5IO_Info.DI_Type[C5IO_DI_CH13] = BUS_C5IO_DI_Dry_Type | BUS_C5IO_DI_Level_LOW; + + C5IO_Info.DI_Detection_Time[C5IO_DI_CH8] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH9] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH10] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH11] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH12] = 0x02; //ʱΪ20ms + C5IO_Info.DI_Detection_Time[C5IO_DI_CH13] = 0x02; //ʱΪ20ms + + + Add_BUS_Device_To_List(&BUS_Public,(uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO)); + + BUS485_Info.device_num += 1; +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_For_Logic_Init +* Description : CSIO豸 - DIͳʼ - ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_BUS_CSIO_DI_For_Logic_Init( + LOGICFILE_DEVICE_INFO *dev_info, + uint8_t *data, + uint16_t data_len) +{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + + uint32_t csio_addr = Find_Device_List_Information(DEV_C5IO_Type,0x00); + + if(csio_addr == 0x00) + { + return ; + }else { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"IOַ:%08X",csio_addr); + } + + uint16_t temp_len = 0; + uint8_t input_num = 0; + uint8_t input_type = 0; + uint8_t input_level = 0; + uint8_t input_time = 0; + uint8_t input_set_flag = 0; + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&C5IO_Info,0,sizeof(BUS_C5IO_INFO)); + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),csio_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),csio_addr+Dev_Privately); + + input_num = dev_info->input_num; + + if(input_num > C5IO_DI_CH_MAX) + { + input_num = C5IO_DI_CH_MAX; + } + + temp_len = input_num*4; //DIԼô״̬ + + if((temp_len + LogicFile_DeviceInfo_InputSet) > data_len) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ʼDIݳȲ %d - %d ",data_len,(temp_len + LogicFile_DeviceInfo_InputSet)); + } + + temp_len = 0; + for(uint8_t i=0;iaddr,dev_info->input_num); +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_Cycle_Call +* Description : C5IOѯͺ +* Input : + dev_addr : 豸Ϣַ +* Return : + 0x01ȴ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_BUS_C5IO_Cycle_Call(uint32_t dev_addr) +{ +// uint16_t temp = 0; +// uint8_t crc_val = 0; +// temp = SRAM_Read_Byte(dev_addr+Dev_Type); //ж豸 +// if(temp != DEV_C5IO_Type) return 0x01; + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + if((BUS_Public.port == Bus_port) && (BUS485_Info.BUS_Start == Baud_Wait)) { + //лʹ,ֻѯ + //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"лʹ,ֻѯ"); + BUS_C5IO_Inquire_Datasend(dev_addr,&C5IO_Info); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + return RS485OCCUPYTIME; + } + + if(C5IO_Info.Relay_Control_Flag != 0x00) + { + BUS_C5IO_Relay_Control_Datasend(dev_addr,&C5IO_Info); + } + else if(C5IO_Info.Relay_Inching_Control_Flag != 0x00) + { + BUS_C5IO_Relay_Inching_Control_Datasend(dev_addr,&C5IO_Info); + } + else if(C5IO_Info.DI_Control_Flag != 0x00) + { + BUS_C5IO_DI_Control_Datasend(dev_addr,&C5IO_Info); + /*2022-12-12*/ + if(C5IO_Info.DI_Reset_Flag == 0x01) + { + C5IO_Info.DI_Reset_Tick = SysTick_1ms; + C5IO_Info.DI_Init_flag = 0x00; //2025-08-07 ϵ󣬲 + } + /*2022-12-12*/ + } + else if(C5IO_Info.DO_Control_Flag != 0x00) + { + BUS_C5IO_DO_Control_Datasend(dev_addr,&C5IO_Info); + } + else if(C5IO_Info.DO_Inching_Control_Flag != 0x00) + { + BUS_C5IO_DO_Inching_Control_Datasend(dev_addr,&C5IO_Info); + } + else if(C5IO_Info.Relay_Reset_Flag == 0x01) /*2022-12-12*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO Relay Reset!!!!!!"); + C5IO_Info.Relay_Reset_Flag = 0x00; + C5IO_Info.Relay_Control_Flag = 0xFFFFFFFF; + BUS_C5IO_Relay_Control_Datasend(dev_addr,&C5IO_Info); + } + else if((C5IO_Info.rtc_set_flag == 0x01) || ((DevActionGlobal.TimeSyncFlag & 0x02) == 0x02)) /*2024-08-02*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO Set RTC!!!!!!"); + C5IO_Info.rtc_set_flag = 0x00; + DevActionGlobal.TimeSyncFlag &= 0x01; + + BUS_CSIO_SetRTCTime_Datasend(dev_addr,&C5IO_Info); + } + else + { + BUS_C5IO_Inquire_Datasend(dev_addr,&C5IO_Info); + } + + C5IO_Info.inquire_tick = SysTick_1ms; //¼ѯʱ + + /*ͨѶ¼ + 豸ͨѶ*/ +// temp = BLV_Communication_Baud_Adjust2(&C5IO_Info.comm_record,&BUS_Public); +// if(temp != 0x00) +// { +// switch(temp) +// { +// case 0x01: +// //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰͨѶ¼δ"); +// break; +// case 0x02: +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO ʧܴѴޣлͨѶ"); +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO Adjust Baud:%ld!",BUS_Public.baud); +// //LOG_Device_COMM_Adjust_Baud_Record(DEV_C5IO_Type,BUS_Public.addr,BUS_Public.baud); +// break; +// case 0x03: +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO ͨѶʧܰٷֱѴޣлͨѶ"); +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO Adjust Baud:%ld!",BUS_Public.baud); +// //LOG_Device_COMM_Adjust_Baud_Record(DEV_C5IO_Type,BUS_Public.addr,BUS_Public.baud); +// break; +// } +// } +// +// BLV_Communication_Record(&C5IO_Info.comm_record,0x01,0x00); + + if(C5IO_Info.DevSendCnt > C5IO_REPEATSENDTIMEMAX) + { + if(C5IO_Info.DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO OFFLINE"); // ϱ + LOG_Device_Online_Record(DEV_C5IO_Type,BUS_Public.addr,LogInfo_Device_Offline); //¼豸 + } + + C5IO_Info.DevOffline = DEV_IS_OFFLINE; //Ϊ + C5IO_Info.DevSendCnt = 0; + if(C5IO_Info.DevOffline != C5IO_Info.DevOfflineLast) //ǰ״̬һ״̬ + { + C5IO_Info.DevOfflineLast = C5IO_Info.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + }else { + C5IO_Info.DevSendCnt++; //ʹۼ + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + return RS485OCCUPYTIME; +} + +/*жCSIO ʱ䴦Ч*/ +uint8_t BLV_CSIO_RTC_TimeValid(uint8_t *date) +{ + /*жޣ2024~2050*/ + if( (RTC_TimeDate_Correct_Figure(date[0]) == 0x00) && ((date[0] >= 0x24) && (date[0] <= 0x50)) ){ + /*ж·ݣ1~12*/ + if( (RTC_TimeDate_Correct_Figure(date[1]) == 0x00) && ((date[1] >= 0x01) && (date[1] <= 0x12)) ){ + /*ж1~31*/ + if( (RTC_TimeDate_Correct_Figure(date[2]) == 0x00) && ((date[2] >= 0x01) && (date[2] <= 0x31)) ){ + /*жСʱ0~23*/ + if( (RTC_TimeDate_Correct_Figure(date[3]) == 0x00) && (date[3] <= 0x23) ){ + /*жϷ֣0~59*/ + if( (RTC_TimeDate_Correct_Figure(date[4]) == 0x00) && (date[4] <= 0x59) ){ + /*ж룺0~59*/ + if( (RTC_TimeDate_Correct_Figure(date[5]) == 0x00) && (date[5] <= 0x59) ){ + /*жڣ0~6*/ + if( date[6] < 0x07 ){ + return 0x00; + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO week error:%02x",date[3]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO sec error:%02x",date[3]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO min error:%02x",date[3]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO hour error:%02x",date[3]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO day error:%02x",date[2]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO mon error:%02x",date[1]); + } + }else{ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO year error:%02x",date[0]); + } + + return 0x01; +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_Data_Processing +* Description : C5IOݴ +* Input : + dev_addr : 豸Ϣַ + data_addr : ݵַ + len ݳ +* Return : + 0x00ɹ + 0x01ʧ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_BUS_C5IO_Data_Processing(uint32_t dev_addr,uint32_t data_addr,uint16_t len) +{ + uint8_t reset_DI = 0; + static uint8_t DI_Init_flg = 0; + uint8_t temp = 0,temp1 = 0,temp2 = 0,temp3 = 0,temp4 = 0,temp5 = 0; + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + + static uint8_t rtc_err = 0; + uint16_t deal_len = len; + uint8_t deal_buff[C5IO_RecvData_Len_MAX]; + + if(deal_len > C5IO_RecvData_Len_MAX) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO Check_Len Fail!"); + return 0x01; //У + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + memset(deal_buff,0,sizeof(deal_buff)); + SRAM_DMA_Read_Buff(deal_buff,deal_len,data_addr); //ȡݳ + + if(deal_len < PKT_PARA) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_LEN Fail:",deal_buff,deal_len); + return 0x01; + } + + if(deal_buff[PKT_LEN] != deal_len) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_LEN Fail:",deal_buff,deal_len); + return 0x01; //Ȳ + } + + if(Data_CheckSum(deal_buff,deal_len) != 0x00) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO Check Fail:",deal_buff,deal_len); + return 0x01; //У + } + + BLV_Communication_Record(&C5IO_Info.comm_record,0x02,0x01); //¼ͨѶɹ + + if(deal_buff[PKT_ADD_FM] != 0x01) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_ADD_FM Fail:",deal_buff,deal_len); + return 0x01; //͵ַ + } + + if((deal_buff[PKT_TYPE] & 0x0F) != C5IO_Info.DevSendSN) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_TYPE Fail:",deal_buff,deal_len); + return 0x01; //Ų + } + + if(deal_buff[PKT_DevType] != C5IOTYPE) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_DevType Fail:",deal_buff,deal_len); + return 0x01; //豸Ͳ + } + + if(deal_buff[PKT_ADD_TO] != 0x00) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_ADD_TO Fail:",deal_buff,deal_len); + return 0x01; //յַ + } + + if(deal_buff[PKT_CMD] != BLV_C5IO_Reply_CMD) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5IO PKT_CMD Fail:",deal_buff,deal_len); + return 0x01; //ظ + } + + if(C5IO_Info.DevOffline == DEV_IS_OFFLINE) //豸״̬ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5IO LogInfo_Device_Online..........."); + LOG_Device_Online_Record(DEV_C5IO_Type,SRAM_Read_Byte(dev_addr+Dev_Addr),LogInfo_Device_Online); //¼豸 + } + + C5IO_Info.DevSendCnt = 0x00; + C5IO_Info.DevOffline = DEV_IS_ONLINE; //豸 + if(C5IO_Info.DevOffline != C5IO_Info.DevOfflineLast) //ǰ״̬һ״̬ + { + Device_Public_Information_G BUS_Public; + + C5IO_Info.DevOfflineLast = C5IO_Info.DevOffline; //һ״̬ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + if((DI_Init_flg == 0) && (deal_buff[PKT_PARA] != 0xF0)) //һѯĻظ 2024-04-01 һDzѯظDIʹDI + { + DI_Init_flg = 1; + + C5IO_Info.DI_Control_Flag = 0x1FFF; + C5IO_Info.CxIO_DI_Control_Flag = C5IO_Info.DI_Control_Flag; ////¼ҪõDI· + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"IO VERSION:%d", C5IO_Info.C5IO_Version); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"DI_Control_Flag:%X", C5IO_Info.DI_Control_Flag); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + return 0x00; + } + + //յظȷջظ־ + switch(C5IO_Info.Send_Type) + { + case BLV_C5IO_Inquire_CMD: + + break; + case BLV_C5IO_Set_Relay_CMD: + if(deal_buff[PKT_PARA] == BLV_C5IO_Relay_Result) + { + C5IO_Info.Relay_Control_Flag &= ~(C5IO_Info.Last_Relay_Control_Flag); + + LOG_Device_COMM_Control_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,deal_buff,deal_len); + } + break; + case BLV_C5IO_Set_Relay_Inching_CMD: + if(deal_buff[PKT_PARA] == BLV_C5IO_Relay_Inching_Result) + { + C5IO_Info.Relay_Inching_Control_Flag &= ~(C5IO_Info.Last_Relay_Inching_Control_Flag); + + LOG_Device_COMM_Control_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,deal_buff,deal_len); + } + break; + case BLV_C5IO_Set_Do_CMD: + if(deal_buff[PKT_PARA] == BLV_C5IO_Do_Result) + { + C5IO_Info.DO_Control_Flag &= ~(C5IO_Info.Last_DO_Control_Flag); + + LOG_Device_COMM_Control_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,deal_buff,deal_len); + } + break; + case BLV_C5IO_Set_Do_Inching_CMD: + if(deal_buff[PKT_PARA] == BLV_C5IO_Do_Inching_Result) + { + C5IO_Info.DO_Inching_Control_Flag &= ~(C5IO_Info.Last_DO_Inching_Control_Flag); + + LOG_Device_COMM_Control_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,deal_buff,deal_len); + } + break; + case BLV_C5IO_Set_Di_CMD: + if(deal_buff[PKT_PARA] == BLV_C5IO_Di_Result) + { + C5IO_Info.DI_Control_Flag &= ~(C5IO_Info.Last_DI_Control_Flag); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5IO_Set_Di_CMD Clear!!!!!!!"); + C5IO_Info.DI_Reset_Flag = 0x00; + LOG_Device_COMM_Control_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,deal_buff,deal_len); + } + break; + default: break; + } + + for(uint8_t i=0; i<4; i++) + { + temp = deal_buff[PKT_PARA + 1 + i]; + for(uint8_t j=0; j<4; j++) + { + temp1 = C5IO_Info.DI_Type[i*4+j] & 0x0F; + temp2 = (temp >> (j*2)) & 0x03; + if((temp1 == temp2) && (temp1 == BUS_C5IO_DI_Key_Type) ) //Ƿͬ + { + C5IO_Info.DI_Control_Flag &= ~(0x01<<(i*4+j)); + temp3 = deal_buff[PKT_PARA + 5 + i]; + temp3 = (temp3 >> (j*2)) & 0x03 ; + if(SysTick_1ms - C5IO_Info.DI_Reset_Tick>1000) /*2022-12-12*/ + { + if(temp3 != 0x00) + { + C5IO_Info.DI_Start[i*4+j] = temp3; + temp5++; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"CSIO DI_Start%d %d !",i*4+j,temp3); + } + } + }else if((temp1 == temp2) && ((temp1 == BUS_C5IO_DI_Pir_Type) || (temp1 == BUS_C5IO_DI_Dry_Type))){ + + C5IO_Info.DI_Control_Flag &= ~(0x01<<(i*4+j)); + temp3 = deal_buff[PKT_PARA + 5 + i]; + temp3 = (temp3 >> (j*2)) & 0x03 ; + if(SysTick_1ms - C5IO_Info.DI_Reset_Tick>1000) /*2022-12-12*/ + { + if(temp3 != C5IO_Info.DI_Start[i*4+j]) + { + C5IO_Info.DI_Start[i*4+j] = temp3; + temp5++; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"CSIO DI_PIR_Start%d %d !",i*4+j,temp3); + } + } + }else { //Ͳͬ - ־λһ + if((i*4+j >= C5IO_DI_CH_MAX)) break; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"CSIO DI_Type %d Fail! temp1:%d , temp2:%d",i*4+j,temp1,temp2); + reset_DI = 1; //DI + } + } + } + + //2025-08-07 ϵ󣬲 + if( (C5IO_Info.DI_Init_flag == 0x00) && (SysTick_1ms - C5IO_Info.DI_Reset_Tick > 1000) ){ + C5IO_Info.DI_Init_flag = 0x01; + + for(uint8_t i = 0;i= 31 ) //ȷCSIO + { + if( (deal_buff[PKT_PARA + 17] != 0) && (deal_buff[PKT_PARA + 18] != 0) && (deal_buff[PKT_PARA + 19] != 0) ) //ղΪ0 + { + /*жʱǷЧ*/ + if(BLV_CSIO_RTC_TimeValid(&deal_buff[PKT_PARA + 17]) == 0x00){ + + S_RTC sRTC; + + g_time_info.csio_rtc_cnt = 0x00; + g_time_info.time_select = 0x02; //ʹӲRTC ʱ + + RTC_ReadDate(&sRTC); + + if(sRTC.year != deal_buff[PKT_PARA + 17] + || sRTC.month != deal_buff[PKT_PARA + 18] + || sRTC.day != deal_buff[PKT_PARA + 19] + || sRTC.hour != deal_buff[PKT_PARA + 20] + || sRTC.minute != deal_buff[PKT_PARA + 21] + || sRTC.second != deal_buff[PKT_PARA + 22] + || sRTC.week != deal_buff[PKT_PARA + 23] + ) + { + sRTC.year = deal_buff[PKT_PARA + 17]; + sRTC.month = deal_buff[PKT_PARA + 18]; + sRTC.day = deal_buff[PKT_PARA + 19]; + sRTC.hour = deal_buff[PKT_PARA + 20]; + sRTC.minute = deal_buff[PKT_PARA + 21]; + sRTC.second = deal_buff[PKT_PARA + 22]; + sRTC.week = deal_buff[PKT_PARA + 23]; + + RTC_WriteDate(sRTC); + + RTC_ReadDate(&RTC_Raw_Data); //ʱͬϵͳʱ(RTC_Raw_Data) + + rtc_err = 0; + }else{ + if(rtc_err < 200) + { + rtc_err++; + }else if(rtc_err == 200) + { + g_time_info.time_select = 0x01; + } + } + }else{ + /*ʱһ*/ + C5IO_Info.rtc_set_flag = 0x01; + } + } + } + + /*жʱǷʹӲRTC ʱ ǵδʱ 2024-08-03*/ + g_time_info.csio_rtc_cnt++; + if(g_time_info.csio_rtc_cnt >= 10){ + g_time_info.csio_rtc_cnt = 0; + + g_time_info.time_select = 0x01; + } + + C5IO_Info.Relay_Level_Actual_Start = deal_buff[PKT_PARA + 15]; + C5IO_Info.Relay_Level_Actual_Start <<= 8 ; + C5IO_Info.Relay_Level_Actual_Start |= deal_buff[PKT_PARA + 14]; + C5IO_Info.Relay_Level_Actual_Start <<= 8 ; + C5IO_Info.Relay_Level_Actual_Start |= deal_buff[PKT_PARA + 13]; + + if(C5IO_Info.Relay_Level_Perfect_Start != C5IO_Info.Relay_Level_Actual_Start) /*ȽC5IO_Relay,Ƿ񱣴־*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"CSIO_Relay_Status Change"); + + C5IO_Info.Relay_Level_Perfect_Start = C5IO_Info.Relay_Level_Actual_Start; + + /*ַʱɾ*/ + SRAM_Write_Byte(deal_buff[PKT_PARA + 13],SRAM_LOG_Device_C5IO_Relay_Status); + SRAM_Write_Byte(deal_buff[PKT_PARA + 14],SRAM_LOG_Device_C5IO_Relay_Status + 1); + SRAM_Write_Byte(deal_buff[PKT_PARA + 15],SRAM_LOG_Device_C5IO_Relay_Status + 2); + + temp4++; + } + + /*PCͨѶ 2022-07-12*/ + if(temp4 != 0x00) //DORELAY״̬ıʱϱ״̬ + { + if(g_pc_test.test_flag == 0x02) + { + BLV_PC_Testing_Data_Reported(0x02,C5IOTYPE,0x00,SRAM_LOG_Device_C5IO_Relay_Status,4); + } + } + + if(temp5 != 0x00) + { + /*DI ״̬ C12IOCSIO DIĿΪ13,4Byte*/ + C5IO_Info.DI_Actual_State = deal_buff[PKT_PARA + 8]; + C5IO_Info.DI_Actual_State <<= 8 ; + C5IO_Info.DI_Actual_State |= deal_buff[PKT_PARA + 7]; + C5IO_Info.DI_Actual_State <<= 8 ; + C5IO_Info.DI_Actual_State |= deal_buff[PKT_PARA + 6]; + C5IO_Info.DI_Actual_State <<= 8 ; + C5IO_Info.DI_Actual_State |= deal_buff[PKT_PARA + 5]; + + if(C5IO_Info.DI_Perfect_State != C5IO_Info.DI_Actual_State) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"CSIO_DI_Status Change"); + + C5IO_Info.DI_Perfect_State = C5IO_Info.DI_Actual_State; + + /*ַʱɾ ʱõ2Byteֽڵַ*/ + SRAM_Write_Byte(deal_buff[PKT_PARA + 5],SRAM_LOG_Device_C5IO_DI_Status); + SRAM_Write_Byte(deal_buff[PKT_PARA + 6],SRAM_LOG_Device_C5IO_DI_Status + 1); + + temp4++; + } + } + + + + if(reset_DI) //ҪDI + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"DI_Reset_Flag"); + C5IO_Info.DI_Control_Flag = C5IO_Info.CxIO_DI_Control_Flag; + C5IO_Info.DI_Reset_Flag = 0x01; + C5IO_Info.Relay_Reset_Flag = 0x01; + DI_Init_flg = 0; //2023-12-18 ⲨƫDIͲɹ + } + + /*ѯ - ⵽״̬ıˣݺͷʱʱ*/ + if((C5IO_Info.Send_Type == BLV_C5IO_Inquire_CMD) && (temp4 != 0x00)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV Inquire_CMD Reply Change"); + LOG_Device_COMM_ASK_TO_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,(SysTick_1ms - C5IO_Info.inquire_tick),deal_buff,deal_len); + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + return 0x00; +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_DI_Control_Datasend +* Description : C5IO DIݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_DI_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[40]; + memset(send_buff,0,40); + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + + if(Dev_Info->C5IO_Version) + { + for(uint8_t i=0;iDI_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->DI_Type[i] & 0x03) << ((i%4)*2); + temp = PKT_PARA + (i/4) + 4; + send_buff[temp] |= ((Dev_Info->DI_Type[i] >> 4) & 0x03) << ((i%4)*2); + temp = PKT_PARA + 8 + i; + send_buff[temp] = Dev_Info->DI_Detection_Time[i]; + } + } + } + else + { + for(uint8_t i=0;i<8;i++) //C5IO + { + if((Dev_Info->DI_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->DI_Type[i] & 0x03) << ((i%4)*2); + temp = PKT_PARA + (i/4) + 2; + send_buff[temp] |= ((Dev_Info->DI_Type[i] >> 4) & 0x03) << ((i%4)*2); + temp = PKT_PARA + 4 + i; + send_buff[temp] = Dev_Info->DI_Detection_Time[i]; + } + } + } + + Dev_Info->Last_DI_Control_Flag = Dev_Info->DI_Control_Flag; + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + + if(Dev_Info->C5IO_Version) + { + send_buff[PKT_LEN] = 0x23; //ηݳ + } + else send_buff[PKT_LEN] = 0x17; //ηݳ + + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Set_Di_CMD; //DI + + if(Dev_Info->C5IO_Version) + { + send_buff[31] = 0x03; //ֵmin + send_buff[32] = 0xE8; + send_buff[33] = 0x0B; //ֵmax + send_buff[34] = 0xB8; + } + else + { + temp = PKT_PARA + 5 + 7; //ֵmin + send_buff[temp] = 0x03; + temp = PKT_PARA + 5 + 7 + 1; + send_buff[temp] = 0xE8; + temp = PKT_PARA + 5 + 7 + 2; //ֵmax + send_buff[temp] = 0x0B; + temp = PKT_PARA + 5 + 7 + 3; + send_buff[temp] = 0xB8; + } + + Dev_Info->Send_Type = BLV_C5IO_Set_Di_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5IO_DO_Control_Datasend +* Description : C5IO DOݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_DO_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[12]; + memset(send_buff,0,12); + + for(uint8_t i=0;iDO_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->DO_Control[i] & 0x03) << ((i%4)*2); + } + } + + Dev_Info->Last_DO_Control_Flag = Dev_Info->DO_Control_Flag; + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + + if(Dev_Info->C5IO_Version) + { + send_buff[PKT_LEN] = 0x0B; //ηݳ + } + else send_buff[PKT_LEN] = 0x09; //ηݳ + + + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Set_Do_CMD; //DI + Dev_Info->Send_Type = BLV_C5IO_Set_Do_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5IO_DO_Inching_Control_Datasend +* Description : C5IO DO Inchingݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_DO_Inching_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[45]; + memset(send_buff,0,45); + + for(uint8_t i=0;iDO_Inching_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->DO_Mode[i] & 0x03) << ((i%4)*2); //DOģʽ + if(Dev_Info->C5IO_Version) + { + temp = PKT_PARA + 4 + i*2; + } + else temp = PKT_PARA + 2 + i*2; + + send_buff[temp] = (Dev_Info->DO_Inching_Time[i] >> 8)&0xFF; //DO綯ʱ + send_buff[temp+1] = (Dev_Info->DO_Inching_Time[i] & 0xFF); + } + } + + Dev_Info->Last_DO_Inching_Control_Flag = Dev_Info->DO_Inching_Control_Flag; + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + + if(Dev_Info->C5IO_Version) + { + send_buff[PKT_LEN] = 0x2B; //ηݳ + } + else send_buff[PKT_LEN] = 0x19; //ηݳ + + + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Set_Do_Inching_CMD; //DO㶯 + Dev_Info->Send_Type = BLV_C5IO_Set_Do_Inching_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5IO_Relay_Control_Datasend +* Description : C5IO Relayݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_Relay_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[15]; + memset(send_buff,0,15); + + for(uint8_t i=0;iRelay_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->Relay_Control[i] & 0x03) << ((i%4)*2); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Relay_Control CH%d",i); + } + } + + Dev_Info->Last_Relay_Control_Flag = Dev_Info->Relay_Control_Flag; + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + send_buff[PKT_LEN] = 0x0C; //ηݳ + if(Dev_Info->C5IO_Version == 3) + { + send_buff[PKT_LEN] = 0x0D; //ηݳ + } + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Set_Relay_CMD; //DI + Dev_Info->Send_Type = BLV_C5IO_Set_Relay_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5IO_Relay_Inching_Control_Datasend +* Description : C5IO Relay Inchingݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_Relay_Inching_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[62]; + memset(send_buff,0,62); + + if(Dev_Info->C5IO_Version == 3) + { + for(uint8_t i=0;iRelay_Inching_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->Relay_Mode[i] & 0x03) << ((i%4)*2); //DOģʽ + temp = PKT_PARA + 6 + i*2; + send_buff[temp] = (Dev_Info->Relay_Inching_Time[i] >> 8)&0xFF; //DO綯ʱ + send_buff[temp+1] = (Dev_Info->Relay_Inching_Time[i] & 0xFF); + } + } + + send_buff[PKT_LEN] = 0x3D; //ηݳ + }else { + for(uint8_t i=0;iRelay_Inching_Control_Flag & ( 0x01 << i ))) + { + temp = PKT_PARA + (i/4); + send_buff[temp] |= (Dev_Info->Relay_Mode[i] & 0x03) << ((i%4)*2); //DOģʽ + temp = PKT_PARA + 5 + i*2; + send_buff[temp] = (Dev_Info->Relay_Inching_Time[i] >> 8)&0xFF; //DO綯ʱ + send_buff[temp+1] = (Dev_Info->Relay_Inching_Time[i] & 0xFF); + } + } + + send_buff[PKT_LEN] = 0x34; //ηݳ + } + + Dev_Info->Last_Relay_Inching_Control_Flag = Dev_Info->Relay_Inching_Control_Flag; + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + + + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Set_Relay_Inching_CMD; //DI + Dev_Info->Send_Type = BLV_C5IO_Set_Relay_Inching_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_CSIO_SetRTCTime_Datasend +* Description : CSIO RTCʱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_CSIO_SetRTCTime_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[62]; + memset(send_buff,0,62); + + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + + + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_SetRTC_CMD; //RTC ʱ + Dev_Info->Send_Type = BLV_C5IO_SetRTC_CMD; + + if((DevActionGlobal.TimeSyncFlag & 0x01) == 0x01) //ʱ + { + //ĵǰʱ+ؼ + uint32_t rtc_tick = 0; + + rtc_tick = RTC_Conversion_To_Unix(&Net_RTC_Data); + //rtc_tick += rtc_hour*3600+rtc_min*60+rtc_sec; + rtc_tick += SysTick_1s - g_time_info.Mcu_GetTime_tick; + Unix_Conversion_To_RTC(&Net_RTC_Data,rtc_tick); + + send_buff[PKT_PARA] = Net_RTC_Data.year; + send_buff[PKT_PARA+1] = Net_RTC_Data.month; + send_buff[PKT_PARA+2] = Net_RTC_Data.day; + send_buff[PKT_PARA+3] = Net_RTC_Data.hour; + send_buff[PKT_PARA+4] = Net_RTC_Data.minute; + send_buff[PKT_PARA+5] = Net_RTC_Data.second; + send_buff[PKT_PARA+6] = Net_RTC_Data.week; + } + else //ϵͳʱ + { + send_buff[PKT_PARA] = MCU_RTC_Data.year; + send_buff[PKT_PARA+1] = MCU_RTC_Data.month; + send_buff[PKT_PARA+2] = MCU_RTC_Data.day; + send_buff[PKT_PARA+3] = MCU_RTC_Data.hour; + send_buff[PKT_PARA+4] = MCU_RTC_Data.minute; + send_buff[PKT_PARA+5] = MCU_RTC_Data.second; + send_buff[PKT_PARA+6] = MCU_RTC_Data.week; + } + + send_buff[PKT_LEN] = PKT_PARA + 7; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5IO_Inquire_Datasend +* Description : C5IO Relay Inchingݴͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_Inquire_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[8]; + memset(send_buff,0,8); + + send_buff[PKT_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT_DevType] = C5IOTYPE; //豸 + send_buff[PKT_ADD_TO] = 0x01; //豸ַ - C5̶豸ַΪ0x01 + send_buff[PKT_LEN] = 0x07; //ηݳ + send_buff[PKT_CHKSUM] = 0x00; //У + send_buff[PKT_CMD] = BLV_C5IO_Inquire_CMD; //DI + Dev_Info->Send_Type = BLV_C5IO_Inquire_CMD; + + send_buff[PKT_CHKSUM] = Data_CheckSum(send_buff, send_buff[PKT_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit, "IO_SEND:", send_buff, send_buff[PKT_LEN]); + MCU485_SendString(temp,send_buff, send_buff[PKT_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5IO_Control_Relay +* Description : C5IO Ƽ̵״̬ +* Input : + dev_addr :豸ַ + loop :Ƽ̵· + start :Ƽ̵״̬ 0x01: 0x02: +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5IO_Control_Relay(uint32_t dev_addr,uint8_t loop,uint8_t start) +{ + uint8_t temp1 = loop; + if(dev_addr == 0x00) return; + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + if(temp1 < C5IO_Relay_CH_MAX) + { + if(start == 0x01) + { + C5IO_Info.Relay_Control[temp1] = BUS_C5IO_OUT_HIGH; + C5IO_Info.Relay_Control_Flag |= 0x0001<>= 1; + temp2 >>= 1; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); +} + +/******************************************************************************* +* Function Name : BUS_CSIO_Set_RTC_Time +* Description : CSIO RTCʱ +* Input : + dev_addr :豸ַ + loop :Relay· + start :Relay״̬ 0x01: 0x00: +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_CSIO_Set_RTC_Time(uint32_t dev_addr) +{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + if(dev_addr == 0x00) return; + + Device_Public_Information_G BUS_Public; + BUS_C5IO_INFO C5IO_Info; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); + + /*ʱһ*/ + C5IO_Info.rtc_set_flag = 0x01; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),dev_addr+Dev_Privately); +} + +/******************************************************************************* +* Function Name : Get_BUS_C5IO_Realy_Status +* Description : ȡ̵״̬ +* Input : + dev_addr :豸ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Get_BUS_C5IO_Realy_Status(uint32_t devaddr) +{ + if(devaddr == 0x00) return 0x00000000; + + BUS_C5IO_INFO C5IO_Info; + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),devaddr+Dev_Privately); + + return C5IO_Info.Relay_Level_Actual_Start; +} + +/******************************************************************************* +* Function Name : Get_BUS_C5IO_Online_Status +* Description : ȡ״̬ +* Input : + dev_addr :豸ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BUS_C5IO_Online_Status(uint32_t devaddr) +{ + BUS_C5IO_INFO C5IO_Info; + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),devaddr+Dev_Privately); + + if(C5IO_Info.DevOffline == DEV_IS_ONLINE) return 0x01; + + return 0x02; +} + +/******************************************************************************* +* Function Name : Get_Bus_C5IO_COMM_State +* Description : C5IO ȡͨѶʧܼ¼ +* Input : + devaddr :豸ַ +* Return : + 0xFF ȡʧ + ֵ ͨѶʧܰٷֱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_Bus_C5IO_COMM_State(uint32_t devaddr) +{ + if(devaddr == 0x00) return 0xFF; + uint16_t dev_rate = 0; + + BUS_C5IO_INFO C5IO_Info; + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),devaddr+Dev_Privately); + + dev_rate = Get_BLV_Communication_Fail_Rate(&C5IO_Info.comm_record); + + return dev_rate; +} + +/******************************************************************************* +* Function Name : Get_Bus_CSIO_COMM_Version +* Description : ȡCSIO 汾 +* Input : + devaddr :豸ַ +* Return : 汾 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_Bus_CSIO_COMM_Version(uint32_t devaddr) +{ + if(devaddr == 0x00) return 0xFF; + uint8_t dev_ver = 0; + + BUS_C5IO_INFO C5IO_Info; + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),devaddr+Dev_Privately); + + dev_ver = C5IO_Info.comm_version; + + return dev_ver; +} + + + + + + + + + diff --git a/BLV_485_Driver/blv_bus_dev_c5music.c b/BLV_485_Driver/blv_bus_dev_c5music.c new file mode 100644 index 0000000..31043fb --- /dev/null +++ b/BLV_485_Driver/blv_bus_dev_c5music.c @@ -0,0 +1,2451 @@ +/* + * blv_bus_dev_c5music.c + * + * Created on: Nov 13, 2025 + * Author: cc + */ +#include "blv_bus_dev_c5music.h" +#include "sram_mem_addr.h" +#include "spi_sram.h" +#include "log_api.h" + +#include "debug.h" +#include "rtc.h" +#include "check_fun.h" + +#include "blv_dev_action.h" +#include "pc_devicetest_fun.h" +#include "uart.h" +#include + +#define MUSICVOICELEVELMAX 10 //󼶱ϱ +#define MUSICVOICELEVELMIN 01 //Сϱ + +#define MUSIC_PLAY 1 //ֲ +#define MUSIC_STOP 2 //ͣ +#define MUSIC_PRE 3 //һ +#define MUSIC_NEX 4 //һ +#define MUSIC_VOICE_UP 5 // +#define MUSIC_VOICE_DOWN 6 // +#define MUSIC_VOICE_ALW_UP 7 //һֱ +#define MUSIC_VOICE_ALW_DOWN 8 //һֱ +#define MUSIC_VOICE_STOP 9 //Ӽֹͣ + +#define C5MUCSIC_RecvData_Len_Max 0x20 + +/******************************************************************************* +* Function Name : BLV_BUS_C5MUSIC_For_Logic_Init +* Description : C5 MUSIC豸Ϣʼ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_BUS_C5MUSIC_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&C5Music_Info,0,sizeof(BUS_C5MUSIC_INFO)); + + BUS_Public.addr = 0x01; //豸ַ - Ĭϵַ + BUS_Public.type = DEV_C5MUSIC_Type; //豸 + BUS_Public.port = 0x03; //豸Ͷ˿ + BUS_Public.baud = 115200; //豸Ͳ + BUS_Public.retry_num = C5MUSIC_REPEATSENDTIMEMAX; //豸ط + BUS_Public.wait_time = C5MUSIC_SEND_WAIT_TIME; //豸ݷ͵ȴظʱ + BUS_Public.polling_cf = (uint32_t)&BLV_BUS_C5MUSIC_Cycle_Call; + BUS_Public.processing_cf = (uint32_t)&BLV_BUS_C5MUSIC_Data_Processing; + BUS_Public.Protocol = dev_info->version; + + BUS_Public.DevFunInfo.Dev_Output_Ctrl = Logic_Music_Ctrl; // + + BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get = Dev_Music_Loop_State; + C5Music_Info.DevOffline = C5Music_Info.DevOfflineLast = DEV_IS_LINEUNINIT; //״̬ʼ + C5Music_Info.now_playback_type = 0x01; //ĬΪ + C5Music_Info.default_volume = BLV_C5MUSIC_Default_Volume; + C5Music_Info.fade_time = 0x01; //ʱ - 100ms + C5Music_Info.quite_flag = 0x02; +// C5Music_Info.now_playback_status = 0x01; + + C5Music_Info.playback_mode = BLV_C5MUSIC_Folder_Loop; + C5Music_Info.control_flag |= C5MUSIC_Set_Loop_Mode_Flag; + +/*ֲʼʼ*/ + C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice = 0x03; //Ϊ10 ϵΪ3 + C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice = 0x03; //Ϊ10 ϵΪ3 + C5Music_Info.BackMusicState[2].CtrlCont.CtrlVoice = 0x03; //Ϊ10 ϵΪ3 + C5Music_Info.BackMusicState[3].CtrlCont.CtrlVoice = 0x03; //Ϊ10 ϵΪ3 2025-08-22 +/*ֲʼ*/ + + C5Music_Info.adjust_volume_type |= 0x12 ; //û·ȫ + C5Music_Info.set_music_volume = C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice*3; //0x1A; + C5Music_Info.set_tone_volume = C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice*3; //0x1A; + C5Music_Info.set_door_volume = C5Music_Info.BackMusicState[2].CtrlCont.CtrlVoice*3; //0x1B +// C5Music_Info.set_helpsleep_volume = C5Music_Info.BackMusicState[3].CtrlCont.CtrlVoice*3; //0x1A; 2022-12-16 + + C5Music_Info.helpsleep_volume = C5Music_Info.BackMusicState[3].CtrlCont.CtrlVoice*3; + + C5Music_Info.set_global_volume = 60; //ϵĬȫΪ60 + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + C5Music_Info.control_flag |= C5MUSIC_Query_Versions_Flag; + //C5Music_Info.control_flag |= C5MUSIC_Query_Filenum_Flag; + C5Music_Info.control_flag |= C5MUSIC_Set_Default_Volume_Flag; + + Add_BUS_Device_To_List(&BUS_Public,(uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO)); + + BUS485_Info.device_num += 1; +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5MUSIC_Cycle_Call +* Description : C5 MUSICѯͺ +* Input : + dev_addr : 豸Ϣַ +* Return : + 0x01ȴ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_BUS_C5MUSIC_Cycle_Call(uint32_t dev_addr) +{ +// uint16_t temp = 0; + uint32_t temp1 = 0; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + +// temp = SRAM_Read_Byte(dev_addr+Dev_Type); //ж豸 +// if(temp != DEV_C5MUSIC_Type) return 0x01; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),dev_addr+Dev_Privately); + + if((BUS_Public.port == Bus_port) && (BUS485_Info.BUS_Start == Baud_Wait)) { + //лʹ,ֻѯ + //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"лʹ,ֻѯ"); + + BUS_C5MUSIC_Playback_Status_Datasend(dev_addr,&C5Music_Info); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),dev_addr+Dev_Privately); + + return RS485OCCUPYTIME; + } + + /*ѯݷ*/ + if(C5Music_Info.control_flag != 0x00) // + { + for(uint8_t i = 0;i C5MUSIC_REPEATSENDTIMEMAX) + { + if(C5Music_Info.DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC OFFLINE"); + LOG_Device_Online_Record(DEV_C5MUSIC_Type,BUS_Public.addr,LogInfo_Device_Offline); //¼豸 + } + C5Music_Info.DevOffline = DEV_IS_OFFLINE; //Ϊ + C5Music_Info.control_flag = 0x00; //ʹﵽޣƱ־λ + C5Music_Info.DevSendCnt = 0x00; //ʹ + if(C5Music_Info.DevOffline != C5Music_Info.DevOfflineLast) //ǰ״̬һ״̬ + { + C5Music_Info.DevOfflineLast = C5Music_Info.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + }else { + C5Music_Info.DevSendCnt++; //ʹۼ + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),dev_addr+Dev_Privately); + + return RS485OCCUPYTIME; +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5MUSIC_Data_Processing +* Description : C5 MUSICݴ +* Input : + dev_addr : 豸Ϣַ + data_addr : ݵַ + len ݳ +* Return : + 0x00ɹ + 0x01ʧ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_BUS_C5MUSIC_Data_Processing(uint32_t dev_addr,uint32_t data_addr,uint16_t len) +{ + uint16_t temp2 = 0,temp3 = 0; + + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),dev_addr+Dev_Privately); + + uint16_t deal_len = len; + if(deal_len > C5MUCSIC_RecvData_Len_Max) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC Check_Len Fail!"); + return 0x01; //У + } + uint8_t deal_buff[40]; + memset(deal_buff,0,sizeof(deal_buff)); + SRAM_DMA_Read_Buff(deal_buff,deal_len,data_addr); + + if(deal_len < PKT2_PARA) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC Check_Len Fail %d!",deal_len); + return 0x01; //ݳȲ + } + + if(deal_buff[PKT2_ADD_FM] != 0x01) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC PKT_ADD_FM Fail:",deal_buff,deal_len); + return 0x01; //͵ַ + } + + if(deal_buff[PKT2_DevType] != C5MUSICTYPE) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC PKT_DevType Fail:",deal_buff,deal_len); + return 0x01; //豸Ͳ + } + + if(deal_buff[PKT2_ADD_TO] != 0x00) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC PKT_ADD_TO Fail:",deal_buff,deal_len); + return 0x01; //յַ + } + + if(deal_buff[PKT2_LEN] != deal_len) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC PKT_LEN Fail:",deal_buff,deal_len); + return 0x01; //Ȳ + } + + if(Data_CheckSum(deal_buff,deal_len) != 0x00) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC Check Fail:",deal_buff,deal_len); + return 0x01; //У + } + + if((deal_buff[PKT2_TYPE] & 0x0F) != C5Music_Info.DevSendSN) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC PKT_TYPE Fail:",deal_buff,deal_len); + return 0x01; //Ų + } + + if(deal_buff[PKT2_PARA] != BLV_C5MUSIC_Relay_SUCC) + { + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC_Relay_Fail:",deal_buff,deal_len); + return 0x01; + } + + if(C5Music_Info.DevOffline == DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC LogInfo_Device_Online..........."); + LOG_Device_Online_Record(DEV_C5MUSIC_Type,BUS_Public.addr,LogInfo_Device_Online); //¼豸 + } + + switch(deal_buff[PKT2_CMD]) + { + case BLV_C5MUSIC_Playback_Status_Reply: //ѯǰ״̬ظ + + C5Music_Info.now_playback_status = deal_buff[PKT2_PARA + 1]; //ǰ״̬ + C5Music_Info.now_playback_mode = deal_buff[PKT2_PARA + 2]; //ģʽ + C5Music_Info.now_playback_dir = deal_buff[PKT2_PARA + 3]; //ǰŵļ + /*ǰļļ*/ + temp2 = deal_buff[PKT2_PARA + 5]; + temp2 <<= 8; + temp2 |= deal_buff[PKT2_PARA + 4]; + C5Music_Info.now_playback_idx = temp2; //ļ - û + + C5Music_Info.now_playback_volume = (deal_buff[PKT2_PARA + 7] & 0x7F); //ǰʵ(ȥλľ־) + C5Music_Info.now_mute_status = deal_buff[PKT2_PARA + 7] >> 7; //λľ־ + + C5Music_Info.now_global_volume = deal_buff[PKT2_PARA + 8]; //ǰȫְٷֱ + + /* */ + C5Music_Info.now_music_volume = deal_buff[PKT2_PARA + 9]; //ǰ + /*ʾ */ + C5Music_Info.now_tone_volume = deal_buff[PKT2_PARA + 10]; //ǰʾ + /* */ + C5Music_Info.now_door_volume = deal_buff[PKT2_PARA + 11]; //ǰ + + C5Music_Info.now_helpsleep_volume = deal_buff[PKT2_PARA + 12]; //ǰ 2022-12-16 + + +// Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"Music Polling Data",deal_buff,deal_len); + + + + if(C5Music_Info.last_playback_status != C5Music_Info.now_playback_status) /*ȽC5MUSIC_Playback,Ƿ񱣴־*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC_Playback_Status Change:%d",C5Music_Info.now_playback_status); + C5Music_Info.last_playback_status = C5Music_Info.now_playback_status; + SRAM_Write_Byte(C5Music_Info.last_playback_status,SRAM_LOG_Device_C5MUSIC_Playback_Status); + temp3++; + } + if(C5Music_Info.last_playback_volume != C5Music_Info.now_playback_volume) /*ȽC5MUSIC_Volume,Ƿ񱣴־*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC_Volume_Status Change"); + C5Music_Info.last_playback_volume = C5Music_Info.now_playback_volume; + SRAM_Write_Byte(C5Music_Info.last_playback_volume,SRAM_LOG_Device_C5MUSIC_Volume_Status); + temp3++; + } + if(C5Music_Info.last_playback_dir != C5Music_Info.now_playback_dir) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC_Playback_Dir Change"); + C5Music_Info.last_playback_dir = C5Music_Info.now_playback_dir; + temp3++; + } + if(C5Music_Info.last_playback_idx != C5Music_Info.now_playback_idx) /*ȽC5MUSIC_idx,Ƿ񱣴־*/ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C5MUSIC_idx_Status Change"); + C5Music_Info.last_playback_idx = C5Music_Info.now_playback_idx; + SRAM_Write_Word(C5Music_Info.last_playback_idx,SRAM_LOG_Device_C5MUSIC_idx_Status); + temp3++; + } + if(temp3 != 0x00) /*ѯ״̬,иı - ¼־*/ + { + LOG_Device_COMM_ASK_TO_Reply_Record(BUS_Public.port, BUS_Public.baud,(SysTick_1ms - C5Music_Info.inquire_tick),deal_buff,deal_len); + } + break; + case BLV_C5MUSIC_Set_Default_Volume_Reply: //趨Ĭϲظ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC_Set_Default_Volume_Reply"); + + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.control_flag &= ~(C5MUSIC_Set_Default_Volume_Flag); + break; + case BLV_C5MUSIC_Specify_Play_Reply: //ָ״̬ظ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC_Specify_Play_Reply"); + + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.control_flag &= ~(C5MUSIC_Specify_Play_Flag); + break; + case BLV_C5MUSIC_Set_Volume_Reply: //ظ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC_Set_Volume_Reply"); + + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.adjust_volume_type = 0x00; + C5Music_Info.control_flag &= ~(C5MUSIC_Set_Volume_Flag); + break; + case BLV_C5MUSIC_Query_Default_Volume_Reply: //ѯĬظ + + C5Music_Info.default_volume = deal_buff[PKT2_PARA + 1]; + C5Music_Info.playback_volume_max = deal_buff[PKT2_PARA + 2]; + C5Music_Info.playback_volume_max = deal_buff[PKT2_PARA + 3]; + + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.control_flag &= ~(C5MUSIC_Query_Default_Volume_Flag); + break; + case BLV_C5MUSIC_Query_Volume_Reply: //ѯظ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.now_playback_volume = deal_buff[PKT2_PARA + 1]; + C5Music_Info.control_flag &= ~(C5MUSIC_Query_Volume_Flag); + break; + case BLV_C5MUSIC_Set_Loop_Mode_Reply: //ѭģʽظ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.control_flag &= ~(C5MUSIC_Set_Loop_Mode_Flag); + C5Music_Info.control_flag |= C5MUSIC_Query_Loop_Mode_Flag; + break; + case BLV_C5MUSIC_Query_Loop_Mode_Reply: //ѯѭģʽظ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + + C5Music_Info.playback_mode = deal_buff[PKT2_PARA + 1]; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC playback_mode:%d",C5Music_Info.playback_mode); + C5Music_Info.control_flag &= ~(C5MUSIC_Query_Loop_Mode_Flag); + break; +// case BLV_C5MUSIC_Query_Filenum_Reply: //ѯļ()ظ +// LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); +// +// C5Music_Info.playback_num = deal_buff[PKT2_PARA + 1]; +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC playback_num:%d",C5Music_Info.playback_num); +// C5Music_Info.control_flag &= ~(C5MUSIC_Query_Filenum_Flag); +// break; + case BLV_C5MUSIC_Query_Versions_Reply: //ѯ汾Żظ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); + C5Music_Info.dev_versions = deal_buff[PKT2_PARA] << 8; + C5Music_Info.dev_versions = deal_buff[PKT2_PARA + 1]; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV_C5MUSIC dev_versions : %04X",C5Music_Info.dev_versions); + + C5Music_Info.control_flag &= ~(C5MUSIC_Query_Versions_Flag); + break; +// case BLV_C5MUSIC_Write_FILEHEAD_Reply: //дļͷظ +// LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); +// +// C5Music_Info.control_flag &= ~(C5MUSIC_Write_FILEHEAD_Flag); //дļͷ +// C5Music_Info.control_flag |= C5MUSIC_Write_FILEData_Flag; //ʼ +// break; +// case BLV_C5MUSIC_Write_FILEData_Reply: //дļݻظ +// LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,deal_buff,deal_len); +// +// if(C5Music_Info.file_block == deal_buff[PKT2_PARA + 1]) //ȶԿ +// { +// Dbg_Print(DBG_BIT_DEVICE_STATUS_bit,"BLV C5MUSIC file block:%d SUCC\r\n",C5Music_Info.file_block); +// C5Music_Info.file_block++; +// } +// if(C5Music_Info.file_block >= C5Music_Info.file_block_num) //ļս +// { +// Dbg_Print(DBG_BIT_DEVICE_STATUS_bit,"BLV C5MUSIC Wirte File END\r\n"); +// C5Music_Info.control_flag &= ~(C5MUSIC_Write_FILEData_Flag); +// } +// +// break; +// case BLV_C5MUSIC_Read_FILEHEAD_Reply: //ļͷظ +// C5Music_Info.control_flag &= ~(C5MUSIC_Read_FILEHEAD_Flag); +// break; +// case BLV_C5MUSIC_Read_FILEData_Reply: //ļ +// +// break; + } + + BLV_Communication_Record(&(C5Music_Info.comm_record),0x02,0x01); //¼ͨѶɹ + C5Music_Info.DevSendCnt = 0x00; + C5Music_Info.DevOffline = DEV_IS_ONLINE; //豸 + if(C5Music_Info.DevOffline != C5Music_Info.DevOfflineLast) //ǰ״̬һ״̬ + { + C5Music_Info.DevOfflineLast = C5Music_Info.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),dev_addr+Dev_Privately); + + return 0x00; +} + +/******************************************************************************* +* Function Name : C5MUSIC_Playback_Status_Datasend +* Description : C5 MUSIC ѯǰ״̬ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Playback_Status_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Playback_Status_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Set_Default_Volume_Datasend +* Description : C5 MUSIC 趨Ĭϲݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Default_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[15]; + memset(send_buff,0,15); + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x0C; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Set_Default_Volume_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->default_volume; //ϵĬ + send_buff[PKT2_PARA + 1] = BLV_C5MUSIC_Volume_MAX; + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Volume_MIN; + send_buff[PKT2_PARA + 3] = 0x00; + send_buff[PKT2_PARA + 4] = 0x00; + send_buff[PKT2_PARA + 5] = 0x00; //2022-12-16 + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_buff[PKT2_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x0B); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Specify_Play_Datasend +* Description : C5 MUSIC ָ״̬ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Specify_Play_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[20]; + memset(send_buff,0,20); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x13; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Specify_Play_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->now_playback_type; //ָ - Ĭ + + + switch(Dev_Info->assign_dir) + { + case BLV_C5MUSIC_Music_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Music_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = Dev_Info->set_playback_volume; + send_buff[PKT2_PARA + 5] = 0x00; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = 0x00; //½ʱ + send_buff[PKT2_PARA + 8] = 0x00; //½ʱ + send_buff[PKT2_PARA + 9] = 0x00; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Warning_Dir: + + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Warning_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = Dev_Info->set_playback_volume; + send_buff[PKT2_PARA + 5] = 0x00; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = 0x00; //½ʱ + send_buff[PKT2_PARA + 8] = 0x00; //½ʱ + send_buff[PKT2_PARA + 9] = 0x00; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Helpsleep_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Helpsleep_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = BLV_C5MUSIC_HelpSleep_Start_Volume; //ʼ + + send_buff[PKT2_PARA + 5] = 0x02; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = Dev_Info->helpsleep_time & 0xFF; //½ʱ + send_buff[PKT2_PARA + 8] = (Dev_Info->helpsleep_time >> 8) & 0xFF; //½ʱ + send_buff[PKT2_PARA + 9] = Dev_Info->helpsleep_volume; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Doorbell_Dir: + if(Dev_Info->now_playback_status == BLV_C5MUSIC_Playing) + { + send_buff[PKT2_PARA + 1] = BLV_C5MUSIC_Forestall; //ָ״̬ + }else { + send_buff[PKT2_PARA + 1] = BLV_C5MUSIC_Single_Play; //ָ״̬ + } + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Doorbell_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = Dev_Info->set_door_volume; //2022-05-08 ޸ + send_buff[PKT2_PARA + 5] = 0x00; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = 0x00; //½ʱ + send_buff[PKT2_PARA + 8] = 0x00; //½ʱ + send_buff[PKT2_PARA + 9] = 0x00; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Greet_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Greet_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = Dev_Info->set_playback_volume; + send_buff[PKT2_PARA + 5] = 0x00; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = 0x00; //½ʱ + send_buff[PKT2_PARA + 8] = 0x00; //½ʱ + send_buff[PKT2_PARA + 9] = 0x00; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Helpsleep1_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Helpsleep1_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = BLV_C5MUSIC_HelpSleep_Start_Volume; //ʼ + send_buff[PKT2_PARA + 5] = 0x02; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = Dev_Info->helpsleep_time & 0xFF; //½ʱ + send_buff[PKT2_PARA + 8] = (Dev_Info->helpsleep_time >> 8) & 0xFF; //½ʱ + send_buff[PKT2_PARA + 9] = Dev_Info->helpsleep_volume; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Helpsleep2_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Helpsleep2_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = BLV_C5MUSIC_HelpSleep_Start_Volume; //ʼ + send_buff[PKT2_PARA + 5] = 0x02; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = Dev_Info->helpsleep_time & 0xFF; //½ʱ + send_buff[PKT2_PARA + 8] = (Dev_Info->helpsleep_time >> 8) & 0xFF; //½ʱ + send_buff[PKT2_PARA + 9] = Dev_Info->helpsleep_volume; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + case BLV_C5MUSIC_Helpsleep3_Dir: + send_buff[PKT2_PARA + 1] = Dev_Info->playback_fun; //ָ״̬ + send_buff[PKT2_PARA + 2] = BLV_C5MUSIC_Helpsleep3_Dir; + send_buff[PKT2_PARA + 3] = Dev_Info->assign_playback_idx; //Ҫָ岥ļҪ0x00 + send_buff[PKT2_PARA + 4] = BLV_C5MUSIC_HelpSleep_Start_Volume; //ʼ + send_buff[PKT2_PARA + 5] = 0x02; //ʱ + send_buff[PKT2_PARA + 6] = 0x00; //ʱ + send_buff[PKT2_PARA + 7] = Dev_Info->helpsleep_time & 0xFF; //½ʱ + send_buff[PKT2_PARA + 8] = (Dev_Info->helpsleep_time >> 8) & 0xFF; //½ʱ + send_buff[PKT2_PARA + 9] = Dev_Info->helpsleep_volume; // ⲻҪ + send_buff[PKT2_PARA + 10] = 0x00; //С ⲻҪ + break; + } + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_buff[PKT2_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,send_buff[PKT2_LEN]); + + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ָļУ%d",Dev_Info->assign_dir); + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"ָݣ",send_buff,send_buff[PKT2_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Set_Volume_Datasend +* Description : C5 MUSIC ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[19]; + memset(send_buff,0,19); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x13; //ηݳ 2022-12-16 + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Set_Volume_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->now_playback_type; + send_buff[PKT2_PARA + 1] = Dev_Info->adjust_volume_type; + + + if(Dev_Info->adjust_volume_type & 0x01) // - һ㲻ʹ + { + send_buff[PKT2_PARA + 2] = Dev_Info->set_playback_volume; + } + + if(Dev_Info->adjust_volume_type & (0x01<<1)) //ȫְٷֱ + { + send_buff[PKT2_PARA + 3] = Dev_Info->set_global_volume; + } + if(Dev_Info->adjust_volume_type & (0x01<<2)) //þ + { + send_buff[PKT2_PARA + 4] = Dev_Info->set_quiet_status; + } + + if(Dev_Info->adjust_volume_type & (0x01<<3)) //Ի· + { + send_buff[PKT2_PARA + 5] = Dev_Info->adjust_volume_operate; //Եڲ + send_buff[PKT2_PARA + 6] = Dev_Info->adjust_volume_loop; //Եڻ· + } + + if(Dev_Info->adjust_volume_type & (0x01<<4)) //û· + { + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"û·::%d", Dev_Info->set_door_volume); + send_buff[PKT2_PARA + 7] = Dev_Info->set_music_volume; //·1 + send_buff[PKT2_PARA + 8] = Dev_Info->set_tone_volume; //·2 + send_buff[PKT2_PARA + 9] = Dev_Info->set_door_volume; //·3 + send_buff[PKT2_PARA + 10] = Dev_Info->set_helpsleep_volume; //·4 2022-12-16 + } + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_buff[PKT2_LEN]); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,send_buff[PKT2_LEN]); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Query_Default_Volume_Datasend +* Description : C5 MUSIC ѯĬݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Query_Default_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Query_Default_Volume_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Query_Volume_Datasend +* Description : C5 MUSIC ѯݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Query_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Query_Volume_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Set_Loop_Mode_Datasend +* Description : C5 MUSIC ѭģʽݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Loop_Mode_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[12]; + memset(send_buff,0,12); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x0A; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Set_Loop_Mode_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->now_playback_type; + send_buff[PKT2_PARA + 1] = Dev_Info->playback_mode; + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x0A); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x0A); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Query_Loop_Mode_Datasend +* Description : C5 MUSIC ѯѭģʽݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Query_Loop_Mode_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Query_Loop_Mode_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Query_Filenum_Datasend +* Description : C5 MUSIC ѯļ()ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Query_Filenum_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Query_Filenum_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Query_Versions_Datasend +* Description : C5 MUSIC ѯ汾ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Query_Versions_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t temp = 0; + uint8_t send_buff[10]; + memset(send_buff,0,10); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Query_Versions_CMD; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,0x08); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,0x08); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Write_FILEHEAD_Datasend +* Description : C5 MUSIC дļͷݷͺ - д־ļMP3ͨ͸· +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Write_FILEHEAD_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + uint8_t len = 0; + uint8_t temp = 0; + uint8_t send_buff[22]; + memset(send_buff,0,22); + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x00; + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Write_FILEHEAD_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->file_block_num & 0xFF; //ļܿͰλ + send_buff[PKT2_PARA + 1] = (Dev_Info->file_block_num >> 8) & 0xFF; //ļܿ߰λ + send_buff[PKT2_PARA + 2] = 0x01; //ļ TXT + len = 0x0B; + //len +=snprintf((char *)&send_buff[PKT2_PARA + 3],16,"%02X%02X%02X%02X",RTC_Raw_Data.year,RTC_Raw_Data.month,RTC_Raw_Data.day,RTC_Raw_Data.hour); + len +=snprintf((char *)&send_buff[PKT2_PARA + 3],16,"%02X%02X%02X%02X",RTC_Raw_Data.month,RTC_Raw_Data.day,RTC_Raw_Data.hour,RTC_Raw_Data.minute); + send_buff[PKT2_LEN] = len; //ηݳ + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,len); + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,len); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : C5MUSIC_Write_FILEData_Datasend +* Description : C5 MUSIC дļ ݷͺ +* Input : + dev_addr : 豸Ϣַ + Dev_Info 豸ṹ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Write_FILEData_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info) +{ + //ȡǰ־ļȡַ + if((Dev_Info->file_start_addr < SRAM_LOG_DATA_Address) || (Dev_Info->file_start_addr > SRAM_LOG_End_Address)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"file_start_addr :%08X",Dev_Info->file_start_addr); + return ; //־ݷΧڣֱ˳ + } + if((Dev_Info->file_end_addr < SRAM_LOG_DATA_Address) || (Dev_Info->file_end_addr > SRAM_LOG_End_Address)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"file_end_addr :%08X",Dev_Info->file_end_addr); + return ; + } + if(Dev_Info->file_block >= Dev_Info->file_block_num) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"file_block :%08X , file_block_num:%08X",Dev_Info->file_block,Dev_Info->file_block_num); + return ; // + } + + uint8_t temp = 0; + uint16_t temp1 = 0,temp2 = 0,len = 0; + uint8_t send_buff[530]; + uint32_t read_addr = 0; + memset(send_buff,0,530); + + /*ȡд볤*/ + temp1 = Dev_Info->file_size - Dev_Info->file_block*512; + if(temp1 > 512) len = 512; + else if((temp1 <= 512) && (temp1 != 0)) len = temp1; + else if(temp1 == 0) return ; + /*ȡȡݵַ*/ + read_addr = Dev_Info->file_block*512+Dev_Info->file_start_addr; + if(read_addr >= SRAM_LOG_End_Address) read_addr = read_addr - SRAM_LOG_End_Address + SRAM_LOG_DATA_Address; + /*ʼ*/ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BUS_C5MUSIC_Write_FILEData %08X,len:%d",read_addr,len); + send_buff[PKT2_ADD_FM] = 0x00; //ַ + if(Dev_Info->DevSendCnt == 0x00) + { + Dev_Info->DevSendSN++; + if(Dev_Info->DevSendSN > 0x0F) Dev_Info->DevSendSN = 0x00; + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); //÷ + }else{ + //Ϊط + send_buff[PKT2_TYPE] |= (Dev_Info->DevSendSN & 0x0F); + send_buff[PKT2_TYPE] |= BUS_Retry_Flag; + } + send_buff[PKT2_DevType] = C5MUSICTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x01; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + + temp1 = len + PKT2_PARA + 4; + send_buff[PKT2_LEN] = temp1 & 0xFF; //ηݳ + send_buff[PKT2_LEN_8] = (temp1 >> 8) & 0xFF; //ηݳ + + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_C5MUSIC_Write_FILEData_CMD; // + + send_buff[PKT2_PARA] = Dev_Info->file_block & 0xFF; //ļܿŵͰλ + send_buff[PKT2_PARA + 1] = (Dev_Info->file_block >> 8) & 0xFF; //ļܿŸ߰λ + + if(read_addr + len >= SRAM_LOG_End_Address) //һζȡ꣬Ҫȡ + { + temp2 = PKT2_PARA + 4; + temp1 = SRAM_LOG_End_Address - read_addr; + SRAM_DMA_Read_Buff(&send_buff[temp2],temp1,read_addr); + temp2 = PKT2_PARA + 4 + temp1; + temp1 = len - temp1; + SRAM_DMA_Read_Buff(&send_buff[temp2],temp1,SRAM_LOG_DATA_Address); + }else { + SRAM_DMA_Read_Buff(&send_buff[PKT2_PARA + 4],len,read_addr); + } + + temp2 = NetCRC16_2(&send_buff[PKT2_PARA + 4],len); + send_buff[PKT2_PARA + 2] = temp2 & 0xFF; //CRC Ͱλ + send_buff[PKT2_PARA + 3] = (temp2 >> 8) & 0xFF; //CRC ߰λ + temp1 = len + PKT2_PARA + 4; + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,temp1); + + /*ݷ*/ + temp = SRAM_Read_Byte(dev_addr+Dev_port); + MCU485_SendString(temp,send_buff,temp1); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,send_buff,send_buff[PKT2_LEN]); +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_Playback_Mode +* Description : C5 MUSIC òģʽ +* Input : + devaddr : 豸Ϣַ + playback_mode ģʽ + BLV_C5MUSIC_Full_Loop 0x00 //ȫѭ + BLV_C5MUSIC_Single_Cycle 0x01 //ѭ + BLV_C5MUSIC_Folder_Loop 0x02 //ļѭ + BLV_C5MUSIC_Random_Cycle 0x03 //ѭ + BLV_C5MUSIC_Order_CyCle 0x05 //˳ѭ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Playback_Mode(uint32_t devaddr,uint8_t play_mode) +{ + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + + if(devaddr == 0x00) return; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + C5Music_Info.playback_mode = play_mode; + C5Music_Info.control_flag |= C5MUSIC_Set_Loop_Mode_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Playback +* Description : C5 MUSIC ָļijһ +* Input : + devaddr : 豸Ϣַ + play_dir ļ + playback ״̬ + play_id ID +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Playback(uint32_t devaddr,uint8_t play_dir,uint8_t playback,uint8_t play_id) +{ + if(devaddr == 0x00) return; + + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + C5Music_Info.playback_fun = playback; + C5Music_Info.assign_dir = play_dir; + C5Music_Info.assign_playback_idx = play_id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Doorbell_Dir +* Description : C5 MUSIC +* Input : + devaddr : 豸Ϣַ + id ļļ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Doorbell_Dir(uint32_t devaddr,uint8_t id) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + C5Music_Info.assign_dir = BLV_C5MUSIC_Doorbell_Dir; + C5Music_Info.assign_playback_idx = id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Warning_Dir +* Description : C5 MUSIC ʾ +* Input : + devaddr : 豸Ϣַ + id ʾļļ + start ״̬ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Warning_Dir(uint32_t devaddr,uint8_t id,uint8_t start) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + C5Music_Info.playback_fun = start; + C5Music_Info.assign_dir = BLV_C5MUSIC_Warning_Dir; + C5Music_Info.assign_playback_idx = id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Greet_Dir +* Description : C5 MUSIC Żӭ +* Input : + devaddr : 豸Ϣַ + id Żӭļļ + start ״̬ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Greet_Dir(uint32_t devaddr,uint8_t id,uint8_t start) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = start; + + + C5Music_Info.assign_dir = BLV_C5MUSIC_Greet_Dir; + C5Music_Info.assign_playback_idx = id; +// C5Music_Info.set_playback_volume = 20; //ӭΪ15 + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Helpsleep_Dir +* Description : C5 MUSIC +* Input : + devaddr : 豸Ϣַ + dirļ + id ļļ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Helpsleep_Dir(uint32_t devaddr,uint8_t dir,uint8_t id) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + /*ģʽ*/ + if(C5Music_Info.quiet_mode == 0x01) + { + C5Music_Info.quiet_mode = 0x00; + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x01; //رվ + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + } + +// if((C5Music_Info.now_playback_status == BLV_C5MUSIC_Playing) && (C5Music_Info.now_playback_dir == dir)) +// { +// C5Music_Info.playback_fun = BLV_C5MUSIC_Next_Song; +// }else +// { + C5Music_Info.playback_fun = BLV_C5MUSIC_Playing; + C5Music_Info.helpsleep_tick = SysTick_1s; +// } + C5Music_Info.helpsleep_time = 600; //λS + +// C5Music_Info.helpsleep_volume = C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice*3; //23; +// C5Music_Info.helpsleep_volume =C5Music_Info.set_helpsleep_volume; //2022-12-16 + C5Music_Info.assign_dir = dir; + + C5Music_Info.assign_playback_idx = id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Play_Helpsleep_Dir +* Description : C5 MUSIC ,òʱ +* Input : + devaddr : 豸Ϣַ + dirļ + id ļļ + time: ʱ䣬λs +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Play_Helpsleep_Dir(uint32_t devaddr,uint8_t dir,uint8_t id, uint16_t time) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + /*ģʽ*/ + if(C5Music_Info.quiet_mode == 0x01) + { + C5Music_Info.quiet_mode = 0x00; + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x01; //رվ + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + } + +// if((C5Music_Info.now_playback_status == BLV_C5MUSIC_Playing) && (C5Music_Info.now_playback_dir == dir)) +// { +// C5Music_Info.playback_fun = BLV_C5MUSIC_Next_Song; +// }else +// { + C5Music_Info.playback_fun = BLV_C5MUSIC_Playing; + C5Music_Info.helpsleep_tick = SysTick_1s; +// } + C5Music_Info.helpsleep_time = time; //λS + + C5Music_Info.helpsleep_volume = 23; + C5Music_Info.assign_dir = dir; + + C5Music_Info.assign_playback_idx = id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Helpsleep_Dir +* Description : C5 MUSIC (ֻ֣ +* Input : + devaddr : 豸Ϣַ + dirļ + id ļļ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Helpsleep_Dir_Just(uint32_t devaddr,uint8_t dir,uint8_t id) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + /*ģʽ*/ +// if(C5Music_Info.quiet_mode == 0x01) +// { +// C5Music_Info.quiet_mode = 0x00; +// C5Music_Info.adjust_volume_type |= 0x04; +// //C5Music_Info.set_quiet_status = 0x01; //رվ +// C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; +// } + +// if((C5Music_Info.now_playback_status == BLV_C5MUSIC_Playing) && (C5Music_Info.now_playback_dir == dir)) +// { +// C5Music_Info.playback_fun = BLV_C5MUSIC_Next_Song; +// }else +// { + C5Music_Info.playback_fun = BLV_C5MUSIC_Playing; + C5Music_Info.helpsleep_tick = SysTick_1s; +// } + C5Music_Info.helpsleep_time = 600; //λS + + C5Music_Info.helpsleep_volume = 23; + C5Music_Info.assign_dir = dir; + + C5Music_Info.assign_playback_idx = id; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Stop_Playback +* Description : C5 MUSIC ֹͣ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Stop_Playback(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Halted; //2023-2-22 + C5Music_Info.assign_dir = 0x00; + C5Music_Info.assign_playback_idx = 0x00; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Play_Playback +* Description : C5 MUSIC +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Play_Playback(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"BUS_C5MUSIC_Play_Playback---"); + +// if(C5Music_Info.now_playback_status==0x00) +// { +// C5Music_Info.playback_fun = BLV_C5MUSIC_Halted; +//// printf("ſ:ͣ\n"); +// } +// else if(C5Music_Info.now_playback_status==0x01) +// { +// C5Music_Info.playback_fun = BLV_C5MUSIC_Playing; +//// printf("ſ:\n"); +// } + C5Music_Info.playback_fun = BLV_C5MUSIC_Playing; + C5Music_Info.assign_dir = 0x00; + C5Music_Info.assign_playback_idx = 0x00; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + +// C5Music_Info.playback_mode = BLV_C5MUSIC_Folder_Loop; +// C5Music_Info.control_flag |= C5MUSIC_Set_Loop_Mode_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Play_Playback_Next +* Description : C5 MUSIC ļ - һ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Play_Playback_Next(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Next_Song; + C5Music_Info.assign_dir = BLV_C5MUSIC_Music_Dir; + + /*Ŀǰһ ֻļе 1~40 */ + C5Music_Info.assign_playback_idx++; + if(C5Music_Info.assign_playback_idx >= 3) + { + C5Music_Info.assign_playback_idx = 1; + } + + C5Music_Info.assign_playback_idx = 0; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s %d",__func__,C5Music_Info.assign_playback_idx); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Play_Playback_Last +* Description : C5 MUSIC ļ - һ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Play_Playback_Last(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Prev_Song; + C5Music_Info.assign_dir = BLV_C5MUSIC_Music_Dir; + + /*Ŀǰһ ֻļе 1~40 */ + if(C5Music_Info.assign_playback_idx > 0x01) + { + C5Music_Info.assign_playback_idx--; + }else { + C5Music_Info.assign_playback_idx = 3; + } + + C5Music_Info.assign_playback_idx = 0; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s %d",__func__,C5Music_Info.assign_playback_idx); + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Pause_Playback +* Description : C5 MUSIC ͣ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Pause_Playback(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Halted; + C5Music_Info.assign_dir = 0x00; + C5Music_Info.assign_playback_idx = 0x00; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Playback_Next +* Description : C5 MUSIC һ +* Input : + devaddr : 豸Ϣַ] + dir : Ҫһ׵ļ +Ҳһ׵ĹܣǰǵǰŴ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Playback_Next(uint32_t devaddr, uint8_t dir) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Next_Song; + C5Music_Info.assign_dir = dir; + C5Music_Info.assign_playback_idx = 0x00; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Playback_Prev +* Description : C5 MUSIC һ +* Input : + devaddr : 豸Ϣַ] + dir : Ҫһ׵ļ +Ҳһ׵ĹܣǰǵǰŴ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Playback_Prev(uint32_t devaddr, uint8_t dir) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + C5Music_Info.playback_fun = BLV_C5MUSIC_Prev_Song; + C5Music_Info.assign_dir = dir; + C5Music_Info.assign_playback_idx = 0x00; + + C5Music_Info.control_flag |= C5MUSIC_Specify_Play_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Relative_Volume_Plus +* Description : C5 MUSIC Եڼ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Relative_Volume_Plus(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + //Ե - һ +// C5Music_Info.adjust_volume_type |= 0x08; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + C5Music_Info.set_playback_volume++; + if(C5Music_Info.set_playback_volume >= 30) C5Music_Info.set_playback_volume=30; + C5Music_Info.adjust_volume_type |= 0x08; + C5Music_Info.adjust_volume_operate = 0x02; + C5Music_Info.adjust_volume_loop = 0x03; //·1·2 + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Relative_Volume_Plus +* Description : C5 MUSIC Եڼ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Relative_Volume_Subtraction(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + //Ե - һ +// C5Music_Info.adjust_volume_type |= 0x08; + if(C5Music_Info.set_playback_volume != 0x00 ) C5Music_Info.set_playback_volume--; + + C5Music_Info.adjust_volume_type |= 0x08; + C5Music_Info.adjust_volume_operate = 0x01; + C5Music_Info.adjust_volume_loop = 0x03; //·1·2 + + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Relative_Volume_Plus +* Description : C5 MUSIC Եڼ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Relative_Volume_PlusValue(uint32_t devaddr, uint8_t value) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + //Ե - value +// C5Music_Info.adjust_volume_type |= 0x08; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d", value); + + C5Music_Info.set_music_volume = C5Music_Info.now_music_volume + value; + if(C5Music_Info.set_music_volume > 30) C5Music_Info.set_music_volume = 30; + + C5Music_Info.set_tone_volume = C5Music_Info.now_tone_volume + value; + if(C5Music_Info.set_tone_volume > 30) C5Music_Info.set_tone_volume = 30; + + C5Music_Info.set_door_volume = C5Music_Info.now_door_volume; + if(C5Music_Info.set_door_volume > 30) C5Music_Info.set_door_volume = 30; + + C5Music_Info.set_playback_volume = 0; //·ͲҪٷˣȻòЧ + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Relative_Volume_Plus +* Description : C5 MUSIC Եڼ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Relative_Volume_SubtractionValue(uint32_t devaddr, uint8_t value) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + //Ե - value +// C5Music_Info.adjust_volume_type |= 0x08; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d", value); + + if(C5Music_Info.now_music_volume > value) C5Music_Info.set_music_volume = C5Music_Info.now_music_volume - value; + else C5Music_Info.set_music_volume = 0; + + if(C5Music_Info.now_tone_volume > value) C5Music_Info.set_tone_volume = C5Music_Info.now_tone_volume - value; + else C5Music_Info.set_tone_volume = 0; + + C5Music_Info.set_door_volume = C5Music_Info.now_door_volume; + if(C5Music_Info.set_door_volume > 30) C5Music_Info.set_door_volume = 30; + + C5Music_Info.set_playback_volume = 0; //·ͲҪٷˣȻòЧ + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_Quiet_Mode +* Description : C5 MUSIC ģʽ +* Input : + devaddr : 豸Ϣַ +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Quiet_Mode(uint32_t devaddr) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + /*״̬ȡ*/ + if(C5Music_Info.quiet_mode == 0x00) // + { + C5Music_Info.quiet_mode = 0x01; + + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x00; // + + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + }else + { + C5Music_Info.quiet_mode = 0x00; + + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x01; //رվ + + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_Quiet_Mode2 +* Description : C5 MUSIC ģʽ +* Input : + devaddr : 豸Ϣַ + start ״̬ + 0x00ر + 0x01 +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Quiet_Mode2(uint32_t devaddr,uint8_t status) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + if(status == 0x00) + { + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x01; //رվ + + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + }else + { + C5Music_Info.adjust_volume_type |= 0x04; + C5Music_Info.set_quiet_status = 0x00; // + + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_Global_Volume +* Description : C5 MUSIC ȫ +* Input : + devaddr : 豸Ϣַ + vel ȫ 0~100 + +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_Global_Volume(uint32_t devaddr,uint8_t vel) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + + + C5Music_Info.adjust_volume_type |= 0x02; + C5Music_Info.set_global_volume = vel; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + if(vel == 0x00) + { + C5Music_Info.quiet_mode = 0x01; + }else { + C5Music_Info.quiet_mode = 0x00; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_LoopVolume +* Description : C5 MUSIC û· +* Input : + devaddr : 豸Ϣַ + loop + 0x01ֻ· + 0x02ʾ· + 0x03· + vel û· 0~30 + +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_LoopVolume(uint32_t devaddr,uint8_t loop,uint8_t vel) +{ + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + switch(loop) + { + case 0x01: // + C5Music_Info.set_music_volume = vel; + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + break; + case 0x02: //ʾ + C5Music_Info.set_tone_volume = vel; + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + break; + case 0x03: // + C5Music_Info.set_door_volume = vel; + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + break; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + +} + +/******************************************************************************* +* Function Name : BUS_C5MUSIC_Set_LoopVolume_2 +* Description : C5 MUSIC û· +* Input : + devaddr : 豸Ϣַ + loop + bit0:0x01ֻ· + bit1:0x01ʾ· + bit2:0x01· + vel û· 0~30 +* Return : NONE +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS_C5MUSIC_Set_LoopVolume_2(uint32_t devaddr,uint8_t loop,uint8_t vel) +{ + uint16_t temp = 0; + if(devaddr == 0x00) return; + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + if((loop & 0x01)) // + { + C5Music_Info.set_music_volume = vel; + temp++; + } + if((loop & 0x02)) //ʾ + { + C5Music_Info.set_tone_volume = vel; + temp++; + } + if((loop & 0x04)) // + { + C5Music_Info.set_door_volume = vel; + temp++; + } + + if(temp) + { + C5Music_Info.set_playback_volume = 0; //·ͲҪٷˣȻòЧ + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + } + +} + + +/******************************************************************************* +* Function Name : Get_BUS_C5MUSIC_Loop_Volume +* Description : C5 MUSIC ȡ· +* Input : + devaddr : 豸Ϣַ + loop + 0x01ֻ· + 0x02ʾ· + 0x03· + 0x04ȫְٷֱ +* Return : ·ֵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BUS_C5MUSIC_Loop_Volume(uint32_t devaddr,uint8_t loop) +{ + uint8_t volume = 0; + if(devaddr == 0x00) return 0x02; + + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + switch(loop) + { + case 0x01: + volume = C5Music_Info.now_music_volume; + break; + case 0x02: + volume = C5Music_Info.now_tone_volume; + break; + case 0x03: + volume = C5Music_Info.now_door_volume; + break; + case 0x04: + volume = C5Music_Info.now_global_volume; + break; + } + return volume; +} + +/*ȡ״̬*/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BUS_C5MUSIC_Online_Status(uint32_t devaddr) +{ + if(devaddr == 0x00) return 0x02; + + BUS_C5MUSIC_INFO C5Music_Info; + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + if(C5Music_Info.DevOffline == DEV_IS_ONLINE) + { + return 0x01; + } + return 0x02; +} + +__attribute__((section(".non_0_wait"))) void BLV_Music_CtrlState_Get(DEV_MUSIC_CTRLSTATE *music_state,uint16_t Output_state ) +{ + if(music_state == NULL) return ; + + music_state->DevMusicCtrlWay.CtrlDirect = Output_state & 0x000F; + music_state->DevMusicCtrlWay.CtrlDir = (Output_state >> 4) & 0x000F; + music_state->CtrlCont.CtrlVoice = (Output_state >> 8) & 0x00FF; +} + +/** +*@name ֿƺ +*@para +* DevAddrIn 豸 +* DevInputLoop · +* DevAddrOut 豸 +* DevOutputLoop · +* DevOutputType +*/ +__attribute__((section(".non_0_wait"))) void Logic_Music_Ctrl( + uint32_t DevAddrIn, + uint16_t DevInputLoop, + uint32_t DevAddrOut, + uint16_t DevOutputLoop, + uint16_t DevOutputType) +{ + DEV_MUSIC_CTRLSTATE DevMusicCtrlState; //ֿ״̬ + Device_Public_Information_G BUS_Public; + BUS_C5MUSIC_INFO C5Music_Info; + uint8_t KeepFlag = 0x00; + uint8_t KeepFlag1 = 0x00; + + if( (0x00000000 == DevAddrOut) || (0xFFFFFFFF == DevAddrOut) ) + { + return ; + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),DevAddrOut+Dev_Privately); + + if(DevOutputLoop >= MUSICLOOPMAX) + { + return ; + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Music Ctrl State:%04X",DevOutputType); + + BLV_Music_CtrlState_Get(&DevMusicCtrlState,DevOutputType); + + switch(DevMusicCtrlState.DevMusicCtrlWay.CtrlDirect) // + { + case 0x00: // + switch(DevMusicCtrlState.DevMusicCtrlWay.CtrlDir) + { + case 0x01: // + BUS_C5MUSIC_Play_Playback(DevAddrOut); //汣 + break; + case 0x02: //ͣ + BUS_C5MUSIC_Stop_Playback(DevAddrOut); //汣 + break; + case 0x03: //һ + BUS_C5MUSIC_Play_Playback_Last(DevAddrOut); + break; + case 0x04: //һ + BUS_C5MUSIC_Play_Playback_Next(DevAddrOut); + break; + case 0x05: // Ŀǰ10мӼÿμӼһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִбֿƣ"); + KeepFlag1 = 0x03; + if(C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice < MUSICVOICELEVELMAX) //ӵʾĻ·̶Ϊ01 2022-06-28 + { + KeepFlag = 0x01; + C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice++; + C5Music_Info.set_music_volume = C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice*3; + } + + if(C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice < MUSICVOICELEVELMAX) + { + KeepFlag = 0x01; + C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice++; + C5Music_Info.set_tone_volume = C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice*3; + } + + + break; + case 0x06: // Ŀǰ10мӼÿμӼһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִбֿƣ"); + KeepFlag1 = 0x03; + if(C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice > MUSICVOICELEVELMIN) //ʾĻ·̶Ϊ01 2022-06-28 + { + KeepFlag = 0x01; + C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice--; + C5Music_Info.set_music_volume = C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice*3; + } + if(C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice > MUSICVOICELEVELMIN) + { + KeepFlag = 0x01; + C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice--; + C5Music_Info.set_tone_volume = C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice*3; + } + +// if(C5Music_Info.now_helpsleep_volume >0) +// { +// KeepFlag = 0x01; +// if(C5Music_Info.now_helpsleep_volume-3<=0) +// { +// C5Music_Info.set_helpsleep_volume = 1; +// } +// else +// { +// C5Music_Info.set_helpsleep_volume = C5Music_Info.now_helpsleep_volume-3; +// } +// } + break; + case 0x07: //趨 + if( DevMusicCtrlState.CtrlCont.CtrlVoice <= MUSICVOICELEVELMAX ) // + { + KeepFlag = 0x01; + KeepFlag1 = 0x03; +// C5Music_Info.set_music_volume = UINT8DATACONVER(DevMusicCtrlState.CtrlCont)*3; + C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice = DevMusicCtrlState.CtrlCont.CtrlVoice; //ǰȽֵֵӦĵǰ״̬λ 2022-06-28 + C5Music_Info.set_music_volume = C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice*3; + } + break; + case 0x08: //趨ʾ + if( DevMusicCtrlState.CtrlCont.CtrlVoice <= MUSICVOICELEVELMAX) // + { + KeepFlag = 0x01; + KeepFlag1 = 0x03; +// C5Music_Info.set_tone_volume = UINT8DATACONVER(DevMusicCtrlState.CtrlCont)*3; + C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice = DevMusicCtrlState.CtrlCont.CtrlVoice; //ʾǰȽֵֵӦĵǰ״̬λ 2022-06-28 + C5Music_Info.set_tone_volume = C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice*3; + } + break; + case 0x09: //趨 + if( DevMusicCtrlState.CtrlCont.CtrlVoice <= MUSICVOICELEVELMAX ) // + { + KeepFlag = 0x01; + KeepFlag1 = 0x03; +// C5Music_Info.set_door_volume = UINT8DATACONVER(DevMusicCtrlState.CtrlCont)*3; + C5Music_Info.BackMusicState[2].CtrlCont.CtrlVoice = DevMusicCtrlState.CtrlCont.CtrlVoice; //塢ӭǰȽֵֵӦĵǰ״̬λ 2022-06-28 + C5Music_Info.set_door_volume = C5Music_Info.BackMusicState[2].CtrlCont.CtrlVoice*3; + } + break; + case 0x0A: //þ 2023-02-27 +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"趨%d",UINT8DATACONVER(DevMusicCtrlState.CtrlCont)); +// if(UINT8DATACONVER(DevMusicCtrlState.CtrlCont) <= MUSICVOICELEVELMAX) // +// { +// KeepFlag = 0x01; +// KeepFlag1 = 0x01; +// C5Music_Info.set_playback_volume = UINT8DATACONVER(DevMusicCtrlState.CtrlCont)*3; +// } +// break; +// case 0x0B: //ȫ 2023-02-27 + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"趨ȫְٷֱ%d",DevMusicCtrlState.CtrlCont.CtrlVoice); + if(DevMusicCtrlState.CtrlCont.CtrlVoice <= MUSICVOICELEVELMAX) + { + KeepFlag = 0x01; + KeepFlag1 = 0x02; + C5Music_Info.set_global_volume = DevMusicCtrlState.CtrlCont.CtrlVoice*10; + } + break; + case 0x0C: //趨 + if(DevMusicCtrlState.CtrlCont.CtrlVoice <= MUSICVOICELEVELMAX) // + { + KeepFlag = 0x01; + C5Music_Info.helpsleep_volume = DevMusicCtrlState.CtrlCont.CtrlVoice*3; + } + break; + } + break; + case 0x01: // + break; + case 0x02: //ػ + break; + case 0x03: //ʱ + case 0x04: //ʱ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִбֿƣ·:%d ״̬: %04X",DevOutputLoop, DevOutputType); + switch(DevMusicCtrlState.DevMusicCtrlWay.CtrlDir) // + { + case 0x00: //ļ +// BUS_C5MUSIC_Warning_Dir(DevAddrOut,0x0D,BLV_C5MUSIC_Single_Play); //ʾ + break; + case 0x01: //ʾļ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Tone Index:%d",DevMusicCtrlState.CtrlCont.CtrlVoice); + switch(DevMusicCtrlState.CtrlCont.CtrlVoice) + { + case 0x01: //ʾ + case 0x06: //ģʽ + case 0x09: //ģʽ + case 11: //յ + case 12: //յػ + case 18: //ԤԼ˷ + case 19: //ȡ˷ + case 20: //SOSѿ + case 21: //SOSѹر + case 22: //ȡ + case 23: //ȡ + case 24: //ǷҪ˷ + case 160: //ģʽ + case 161: //ģʽ + case 162: //ͷģʽ + case 163: //ͷ + case 164: //з + case 165: //߷ + case 167: + case 168: + case 169: + BUS_C5MUSIC_Warning_Dir(DevAddrOut,DevMusicCtrlState.CtrlCont.CtrlVoice,BLV_C5MUSIC_Forestall); //Ȳ + break; + default: + BUS_C5MUSIC_Warning_Dir(DevAddrOut,DevMusicCtrlState.CtrlCont.CtrlVoice,BLV_C5MUSIC_Single_Play); // + break; + } + break; + case 0x02: //ļ + BUS_C5MUSIC_Helpsleep_Dir(DevAddrOut, BLV_C5MUSIC_Helpsleep_Dir, 0x01); + break; + case 0x03: //ļ + BUS_C5MUSIC_Doorbell_Dir(DevAddrOut, 0x05); + break; + case 0x04: //ӭļ + BUS_C5MUSIC_Greet_Dir(DevAddrOut, DevMusicCtrlState.CtrlCont.CtrlVoice, BLV_C5MUSIC_Single_Play); //ӭ + break; + case 0x05: //ļ ڤ + BUS_C5MUSIC_Helpsleep_Dir(DevAddrOut,BLV_C5MUSIC_Helpsleep1_Dir,0x01); + break; + case 0x06: //ļ + BUS_C5MUSIC_Helpsleep_Dir(DevAddrOut,BLV_C5MUSIC_Helpsleep2_Dir,0x01); + break; + case 0x07: //ļ ɭ + BUS_C5MUSIC_Helpsleep_Dir(DevAddrOut,BLV_C5MUSIC_Helpsleep3_Dir,0x01); + break; + } + break; + } + if(KeepFlag) + { + if(KeepFlag1==0x02) + { + C5Music_Info.adjust_volume_type |= 0x02; //ȫ 2023-02-27 + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + } + else if(KeepFlag1 == 0x03) + { + C5Music_Info.set_playback_volume = 0; //·ͲҪٷˣȻòЧ + C5Music_Info.adjust_volume_type |= 0x10; + C5Music_Info.control_flag |= C5MUSIC_Set_Volume_Flag; + } + + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&C5Music_Info, sizeof(BUS_C5MUSIC_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddrOut);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),DevAddrOut+Dev_Privately); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"BLV: %d", C5Music_Info.BackMusicState[0].CtrlCont.CtrlVoice); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"BLVʾ: %d", C5Music_Info.BackMusicState[1].CtrlCont.CtrlVoice); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"BLV: %d", C5Music_Info.BackMusicState[2].CtrlCont.CtrlVoice); + + } +// BUS_C5MUSIC_Set_LoopVolume_2(DevAddrOut, DevOutputLoop, C5Music_Info.BackMusicState[DevOutputLoop].CtrlCont.CtrlVoice*3); //ֵŴ3 +} + +__attribute__((section(".non_0_wait"))) uint16_t Dev_Music_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop) +{ + BUS_C5MUSIC_INFO C5Music_Info; //ؾֲ + uint8_t status = 0x00; + + if( (devaddr == 0x00000000) || (devaddr == 0xFFFFFFFF) ) return status; + + SRAM_DMA_Read_Buff((uint8_t *)&C5Music_Info,sizeof(BUS_C5MUSIC_INFO),devaddr+Dev_Privately); + + if(C5Music_Info.now_playback_type ==0x01) // + { + if(C5Music_Info.now_playback_status == 0x00) // + { + status = 0x01; + } + else if(C5Music_Info.now_playback_status == 0x01) //ͣ + { + status = 0x02; + } + } + return status; +} + + + diff --git a/BLV_485_Driver/blv_nor_dev_hvoutfun.c b/BLV_485_Driver/blv_nor_dev_hvoutfun.c new file mode 100644 index 0000000..a7d6df1 --- /dev/null +++ b/BLV_485_Driver/blv_nor_dev_hvoutfun.c @@ -0,0 +1,392 @@ +/* + * blv_nor_dev_hvoutfun.c + * + * Created on: Nov 13, 2025 + * Author: cc + */ +#include "blv_nor_dev_hvoutfun.h" +#include "blv_dev_action.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "debug.h" + +#include "blv_bus_dev_c5iofun.h" + +#include +/*ָ궨*/ +typedef void (*DevFunP)(Device_Public_Information_G *BUS_Public, NOR_HVOUT_INFO *DevHVoutInfo); //ݹָ ˽ָ + +/*豸궨忪ʼ*/ +#define RS485_DEV_PRO_FUN_01 ((DevFunP)NULL) //DevExistJudgge(RS485_HVout_C5RELAY_Flag, BLW_RS485_C5RELAY_Data_Init) //((DevFunP)NULL) // C5C12Դ̵ +#define RS485_DEV_PRO_FUN_02 ((DevFunP)NULL) //DevExistJudgge(RS485_HVout_A9RELAY_Flag, BLW_RS485_A9RELAY_Data_Init) //((DevFunP)NULL) //A9IO̵ +#define RS485_DEV_PRO_FUN_03 ((DevFunP)NULL) //DevExistJudgge(RS485_HVout_SwiRELAY_Flag, BLW_RS485_SwiRELAY_Data_Init) //((DevFunP)NULL) //ǿ翪ؼ̵ +#define RS485_DEV_PRO_FUN_04 ((DevFunP)NULL) // +#define RS485_DEV_PRO_FUN_05 ((DevFunP)NULL) // +#define RS485_DEV_PRO_FUN_06 ((DevFunP)NULL) + +/******************************************************************************* +* Function Name : BLV_Nor_Dev_HVout_For_Logic_Init +* Description : ̵ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Nor_Dev_HVout_For_Logic_Init( + LOGICFILE_DEVICE_INFO *dev_info, + uint8_t *data, + uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&DevHVoutInfo,0,sizeof(NOR_HVOUT_INFO)); //̵ṹ + + BUS_Public.addr = dev_info->addr; //豸ַ + BUS_Public.type = dev_info->type; //豸 + BUS_Public.baud = dev_info->baud; //豸Ͳ9600 + BUS_Public.Protocol = dev_info->version; + + if(ENUM_RS485_DEV_PRO_01 == dev_info->version) + { + BUS_Public.retry_num = C5IO_REPEATSENDTIMEMAX; //豸ط + BUS_Public.wait_time = C5IO_SEND_WAIT_TIME; //豸ݷ͵ȴظʱ - 100ms + }else{ + BUS_Public.retry_num = 0x03; //豸ط + BUS_Public.wait_time = 0x0064; //豸ݷ͵ȴظʱ - 100ms + } + + BUS_Public.DevFunInfo.Dev_Output_Ctrl = BLW_HVout_Control_State; // + BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get = HVout_Loop_State; // + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl = BLW_HVout_Group_Ctrl; // + BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr = BLW_HVout_Group_Read; // + + if(dev_info->output_num > C1_HVOUTNUMMAX) + { + DevHVoutInfo.HVoutLoopValidNum = C1_HVOUTNUMMAX; + }else if(0x00 == dev_info->output_num) + { + DevHVoutInfo.HVoutLoopValidNum = 0x01; //·Ϊ0Ĭһ· + }else{ + DevHVoutInfo.HVoutLoopValidNum = dev_info->output_num; + } + + switch(BUS_Public.Protocol) + { + case ENUM_RS485_DEV_PRO_01: if(NULL!=RS485_DEV_PRO_FUN_01) RS485_DEV_PRO_FUN_01(&BUS_Public, &DevHVoutInfo);break; // + case ENUM_RS485_DEV_PRO_02: if(NULL!=RS485_DEV_PRO_FUN_02) RS485_DEV_PRO_FUN_02(&BUS_Public, &DevHVoutInfo);break; // + case ENUM_RS485_DEV_PRO_03: if(NULL!=RS485_DEV_PRO_FUN_03) RS485_DEV_PRO_FUN_03(&BUS_Public, &DevHVoutInfo);break; //3 + case ENUM_RS485_DEV_PRO_04: if(NULL!=RS485_DEV_PRO_FUN_04) RS485_DEV_PRO_FUN_04(&BUS_Public, &DevHVoutInfo);break; + case ENUM_RS485_DEV_PRO_05: if(NULL!=RS485_DEV_PRO_FUN_05) RS485_DEV_PRO_FUN_05(&BUS_Public, &DevHVoutInfo);break; + case ENUM_RS485_DEV_PRO_06: if(NULL!=RS485_DEV_PRO_FUN_06) RS485_DEV_PRO_FUN_06(&BUS_Public, &DevHVoutInfo);break; + } + + switch(dev_info->port) + { + case Active_Port: //˿ + BUS_Public.port = Active_Port; //豸Ͷ˿ + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO)); + Act485_Info.device_num += 1; + break; + case Polling_Port: //ѯ˿ + BUS_Public.port = Polling_Port; //豸Ͷ˿ + Add_POLL_Device_To_List(&BUS_Public,(uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO)); //ӵ + Poll485_Info.device_num += 1; + break; + case Bus_port: //߶˿ + BUS_Public.port = Bus_port; //豸Ͷ˿ + Add_BUS_Device_To_List(&BUS_Public,(uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO)); + BUS485_Info.device_num += 1; + break; + } +} + +/******************************************************************************* +* Function Name : HVout_Loop_State +* Description : ̵ָ·״̬õ +* Input : +* devaddr - ǰ豸ĵַ +* DevOutputLoop - Ҫҵļ̵· +* Return : +* ·״̬أ 0x01 ,0x02 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t HVout_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop) +{ + NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ + + if(devaddr == 0x00) return 0x00; + + SRAM_DMA_Read_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),devaddr+Dev_Privately); + + if(DevOutputLoop >= DevHVoutInfo.HVoutLoopValidNum) + { + return 0x00; + } + + if(DevHVoutInfo.DevHVoutState[DevOutputLoop] == 0x01) // + { + return 0x01; + }else{ + return 0x02; + } +} + +/******************************************************************************* +* Function Name : BLW_HVout_Control_State +* Description : BLW̵״̬ƺ +* Input : + devaddr : 豸Ϣַ + loop · ·Ǵ0 + start ״̬ 0x01 0x02 +* Return : +* attention : temp10Żб +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_HVout_Control_State( + uint32_t CfgDevAddIn, + uint16_t DevInputAddr, + uint32_t devaddr, + uint16_t DevOutputLoop, + uint16_t start) +{ + uint8_t temp1 = 0; + uint8_t state; //0 1 + Device_Public_Information_G BUS_Public; // + NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ + + if(devaddr == 0x00) return; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),devaddr+Dev_Privately); + + switch(start) + { + case 0x01:state = HVout_State_Open;break; + case 0x02:state = HVout_State_Close;break; + default:return; + } + + if(DevOutputLoop >= DevHVoutInfo.HVoutLoopValidNum) return ; + + if( DevHVoutInfo.DevHVoutState[DevOutputLoop] != state ) + { + switch(state) + { + case 0x00: //ָλ0 + DevHVoutInfo.DevHVoutState[DevOutputLoop] = 0x00; + break; + case 0x01: //ָλһ + DevHVoutInfo.DevHVoutState[DevOutputLoop] = 0x01; + break; + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"HVOUT loop:%d,start:%d",DevOutputLoop,start); + temp1++; + } + else if(0x01 == DevHVoutInfo.HVSwitchFlag) //ûб仯 ǿ翪 + { + temp1 = 0x01; + DevHVoutInfo.HVSwitchCtrlFlag = 0x01; //Ȼһ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"HVDevSendBuf loop:%d,start:%d",DevOutputLoop,start); + } + + if(temp1 != 0x00) + { + if(Active_Port == BUS_Public.port) + { + BLV_Active_Set_List_Addr(devaddr); //ΨŻȴ + } + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&DevHVoutInfo, sizeof(NOR_HVOUT_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),devaddr+Dev_Privately); + } +} + +/******************************************************************************* +* Function Name : BLW_HVout_Group_Ctrl +* Description : BLW̵Ⱥ +* Input : + devaddr : 豸Ϣַ + CtrlFlagƱ־ ܳ32· + CtrlNum : Ƶ豸 һΪ׼ + start ״̬ 0x01 0x02 +* Return : +* attention : temp10Żб +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_HVout_Group_Ctrl( + uint32_t CfgDevAddIn, + uint16_t DevInputAddr, + uint32_t devaddr, + uint32_t CtrlFlag, + uint8_t CtrlNum, + uint16_t *start) +{ + uint8_t temp1 = 0; + uint8_t i = 0; + Device_Public_Information_G BUS_Public; // + NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ + + if(devaddr == 0x00) return; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),devaddr+Dev_Privately); + + if(CtrlNum >= DevHVoutInfo.HVoutLoopValidNum) + { + CtrlNum = DevHVoutInfo.HVoutLoopValidNum; + } + for(i = 0; i < CtrlNum; i++) + { + if(CtrlFlag&(0x0001<= DevHVoutInfo.HVoutLoopValidNum) + { + ReadNum = DevHVoutInfo.HVoutLoopValidNum; + } + switch(SceneType) + { + case 0x01: + for(i = 0; i < ReadNum; i++) + { + if(ReadFlag&(0x0001< жĵһ-> жĵһ + 2߼ ڹ涨ʱڣ趨״̬ʱ䳬ֵж߼ִвһ + -> · == жϳʱ + -> · == ͷţжͷŵʱ + -> ֵڹ涨ʱڣʱռ涨ʱİٷֱȣ趨ΧΪ0~100ֵΪ0ʱֻҪͨ + 3ʱж ÿһ·һ(ʱ),-> жֵ,-> жֵ + -> (ʱ),ƽڷʽжϣÿһֵһڣֻҪйһ봥 + -> ǰ״̬Ϊ˵£ж·ۼƶʱ䴥жΪˣͬʱ״ˡ¼ + -> ǰ״̬Ϊ˵£ж·ۼƶʱ䴥жΪˣͬʱ״ˡ¼ + -> ÿ·ɵ趨ǷãõĻ·һжֵжΪ + -> ÿ\ˡ״̬仯ʱл·Ļȫա\ˡ״̬䣬¿ʼ + 4߼жϲ -> жĵһ-> жĵһ ʱΪǰִ߼ж; + ִ߼жڼ䣬ʱжϡͣ + 5RS485жΪˡ״̬ҽл·Ļȫաˡ״̬ + 6޿¼޸Ϊһ¼ + -> Ž룺ͨ߼жϡ->ˡʱΪжϵԱ룬Ž롱¼ + -> 룺ͨ߼жϡ->ˡҿʱ롱¼ + -> ޿룺ͨ߼жϡ->ˡ޿ʱ޿롱¼ + -> ״ˣʱжУжϡ->ˡ״ˡ¼ + -> ״ˣʱжУжϡ->ˡ״ˡ¼ + -> ڰڼ⵽RS485 ϱᴥڰ¼ + 20251008 ܴ + ޸ĵ㣺 + 1߼ ->ˡж¼룬ʱ + -> 룺ǰ״̬Ϊ˵£ţָʱ״δ""¼ + -> ʱ: ǰ״̬Ϊ˵£ţָ֮ʱ״δʱ롱¼ + -> ->ˡжϹ̣ -> -> ʱ -> жһѭ˹̣棬볤ʱѡDZ + -> ڲŶ֮""¼"ʱ"¼ҽᴥһ + + 20251013 ܴ + ޸ĵ㣺 + 1޿ȡTFTPϱ־ ˿ڴռ T6 - ·:ռ:״̬:ֵ:ͷֵ + ʽVCLog:T6:1:12.6:1:60:30 + ****************************************************************************** + */ +#include "includes.h" + + +void Dev_VirtualCard_Dis(uint32_t DevAddr); +uint8_t Dev_VirtualCard_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType); +void BLV_VirtualCard_Control_State(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t devaddr,uint16_t DevOutputLoop,uint16_t start); + +__attribute__((section(".non_0_wait"))) void BLV_Nor_Dev_VirtualCard_For_Logic_Init( + LOGICFILE_DEVICE_INFO *dev_info, + uint8_t *data, + uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + VIRTUALCARD_STRUCT VCard_Info; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&VCard_Info,0,sizeof(VIRTUALCARD_STRUCT)); + + BUS_Public.addr = dev_info->addr; //豸ַ + BUS_Public.type = DEV_Virtual_Card; //豸 + BUS_Public.port = dev_info->type; //豸Ͷ˿ + BUS_Public.baud = 0000; //豸Ͳ + + BUS_Public.DevFunInfo.Dev_Data_Process = Dev_VirtualCard_Dis; + BUS_Public.DevFunInfo.Dev_Input_Type_Get = Dev_VirtualCard_InType_Get; + BUS_Public.DevFunInfo.Dev_Output_Ctrl = BLV_VirtualCard_Control_State; + +// VCard_Info.DetWinTime = 120; //Ĭϼⴰ120 + + //2025-09-09 ⲿSRAMжȡһȡ״̬еĻͻָһε״̬ûеĻ + if( (DevActionGlobal.sram_save_flag == 0xA8) && (SRAM_Read_DW(SRAM_LOG_RCU_Reboot_Reason) == 0x05) ) + { + VCard_Info.ExistState = DevActionGlobal.Person_Detected; + VCard_Info.ExistState_Last = DevActionGlobal.Person_Detected; + }else { +// if(SRAM_Read_DW(SRAM_LOG_RCU_Reboot_Reason) == 0x05) +// { +// /*ŹλĻϵĬΪ*/ +// VCard_Info.ExistState = NOONE; +// VCard_Info.ExistState_Last = NOONE; +// }else { +// /*ǿŹλĻϵĬΪ*/ +// +// VCard_Info.ExistState = NOONE; +// VCard_Info.ExistState_Last = NOONE; +// } + + /*2147Ŀ ʹõLauncher4.4汾ֲʲôλ*/ + VCard_Info.ExistState = NOONE; + VCard_Info.ExistState_Last = NOONE; + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard_Info ExistState:%d",VCard_Info.ExistState); + //ʹ +// VCard_Info.ExistState = SOMEONE; +// VCard_Info.ExistState_Last = SOMEONE; + + SRAM_Write_Byte(0x00,SRAM_UDP_ELEReport_VirtualCard); + SRAM_Write_Byte(0x00,SRAM_UDP_ELEReport_VirtualCard_Last); + + Add_Nor_Device_To_List(&BUS_Public,(uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT)); +} + +/*޿ȡ óʱ⻺ λʹ*/ +__attribute__((section(".non_0_wait"))) void DetWin_WriteData(uint8_t port, uint8_t state, uint16_t size) +{ + uint32_t detaddr = 0; + uint8_t data[0x100]; + uint16_t writetime = 0x00; + uint16_t surplus = 0x00; + + memset(data,state,0x100); + + writetime = size / 0x100; + surplus = size % 0x100; + if(surplus > 0) + { + writetime += 1; + } + + detaddr = SRAM_VCard_DetectWin_Start_Addr + (uint32_t)(port * 0x1800); + + for(uint8_t i = 0; i < writetime; i++) + { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-----DetWin_WriteData------ addr:%08X",detaddr); + if((i == (size - 1)) && (surplus != 0x00)) + { + SRAM_DMA_Write_Buff(data,surplus,detaddr); + } + else + { + SRAM_DMA_Write_Buff(data,0x100,detaddr); + } + detaddr += 0x100; + } +} + +/*޿ȡ óʱ⻺ - Bitд*/ +__attribute__((section(".non_0_wait"))) void DetWin_WriteData_Bit(uint8_t port,uint16_t idex,uint8_t state) +{ + uint32_t detaddr = 0; + uint8_t data_val = 0; + uint8_t bit_offset = 0; + uint8_t bit_remian = 0; + + if( port >= 10) return ; + if( idex >= 0x1800) return ; + + if(idex != 0x00) + { + bit_remian = idex % 8; //ȡ + bit_offset = idex / 8; //ַƫ + } + + if( (idex > 0x08) && (bit_remian) != 0x00 ) + { + detaddr = SRAM_VCard_DetectWin_Start_Addr + (uint32_t)(port * 0x1800) + (bit_offset) + 1; + }else { + detaddr = SRAM_VCard_DetectWin_Start_Addr + (uint32_t)(port * 0x1800) + (bit_offset); + } + + data_val = SRAM_Read_Byte(detaddr); + + if(state == 0x01) + { + data_val |= 0x01 << bit_remian; + }else { + data_val &= ~(0x01 << bit_remian); + } + + SRAM_Write_Byte(data_val,detaddr); +} + +/*޿ȡ ȡʱ⻺ - Bitȡ*/ +__attribute__((section(".non_0_wait"))) uint8_t DetWin_ReadData_Bit(uint8_t port,uint16_t idex) +{ + uint32_t detaddr = 0; + uint8_t data_val = 0; + uint8_t bit_offset = 0; + uint8_t bit_remian = 0; + + if( port >= 10) return 0x00; + if( idex >= 0x1800) return 0x00; + + if(idex != 0x00) + { + bit_remian = idex % 8; //ȡ + bit_offset = idex / 8; //ַƫ + } + + if( (idex > 0x08) && (bit_remian) != 0x00 ) + { + detaddr = SRAM_VCard_DetectWin_Start_Addr + (uint32_t)(port * 0x1800) + (bit_offset) + 1; + }else { + detaddr = SRAM_VCard_DetectWin_Start_Addr + (uint32_t)(port * 0x1800) + (bit_offset); + } + + data_val = SRAM_Read_Byte(detaddr); + + if( (data_val & (0x01 << bit_remian)) != 0x00 ) + { + return 0x01; + } + + return 0x00; +} + + +__attribute__((section(".non_0_wait"))) void Dev_VirtualCard_Dis(uint32_t DevAddr) +{ + Device_Public_Information_G BUS_Public; // + VIRTUALCARD_STRUCT VCard_Info; + + uint32_t tempaddr = 0; +// NOR_LVINPUT_INFO DevLVinputInfo; //ֲ +// RS485_CARD_INFO Rs485CardInfo; +// RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + uint8_t portstate = 0; + + uint32_t temp_tickout = 0x00; + uint32_t list_addr = 0; + uint32_t temp_jumpe_time = 0x00; + + CONDITION_STRUCT condata; + memset(&condata,0,sizeof(CONDITION_STRUCT)); + + uint8_t KeepFlag = 0x00; + uint8_t condata_save_flag = 0; + + if( (0x00000000 == DevAddr) || (0xFFFFFFFF == DevAddr) ) + { + return ; + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),DevAddr+Dev_Privately); + + /*ʼӳ˿ڿʼ*/ + if(VCard_Info.PortInit_Flag == 0x00) + { + uint8_t temp[20]; + uint8_t temp_loop = 0; + memset(&temp,0,sizeof(temp)); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Crad_Info:%d - %d",sizeof(VIRTUALCARD_STRUCT),sizeof(Device_Public_Information_G)); + + for(uint8_t i = 0; i < DevActionGlobal.VC_PortNum; i++) //ʼӳ˿Ϣ + { + list_addr = SRAM_VCard_PortInf_Start_Addr + i * sizeof(VPORT_INFO_STRUCT); //õµַ + SRAM_DMA_Read_Buff(temp, sizeof(VPORT_INFO_STRUCT), list_addr); + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit,"VPORT_INFO_STRUCT ",temp,sizeof(VPORT_INFO_STRUCT)); + + if( (temp[5] != 0x00) && (temp[5] <= VIRTUAL_PORT_MAX) ) + { + temp_loop = temp[5] - 1; + VCard_Info.Port_Info[temp_loop].HPort_Type = temp[0]; + VCard_Info.Port_Info[temp_loop].HPort_Addr = temp[1]; + + VCard_Info.Port_Info[temp_loop].HPort_Loop = temp[3]; + VCard_Info.Port_Info[temp_loop].HPort_Loop <<= 8; + VCard_Info.Port_Info[temp_loop].HPort_Loop |= temp[2]; + VCard_Info.Port_Info[temp_loop].HPort_Loop -= 0x01; + + VCard_Info.Port_Info[temp_loop].PortEnFlag = temp[6]; //·óʱ - ʹܱ־λ + + /*2025-03-07 ж + 1ֵΪ0 + 2˿ڿ״̬ + */ + if( VCard_Info.Port_Info[temp_loop].PortEnFlag == 0x01 ) + { + VCard_Info.DetNum++; + } + + VCard_Info.PortState[temp_loop] = KeyRelease; + + //2025-09-19 ÿ·ijʱ + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] = temp[8]; + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] <<= 8; + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] |= temp[7]; + + switch(temp[9]) + { + case 0x01: // + if(VCard_Info.DetInfo.DetWinTotalNum[temp_loop] >= 43200) + { + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] = 43200; + } + break; + case 0x02: // + if(VCard_Info.DetInfo.DetWinTotalNum[temp_loop] >= 720) + { + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] = 720; + } + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] *= 60; + break; + case 0x03: //ʱ + if(VCard_Info.DetInfo.DetWinTotalNum[temp_loop] >= 12) + { + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] = 12; + } + VCard_Info.DetInfo.DetWinTotalNum[temp_loop] *= 3600; + break; + } + + VCard_Info.DetInfo.Trigger_Thres[temp_loop] = temp[4]; //ʱж - -> ֵ + VCard_Info.DetInfo.Release_Thres[temp_loop] = temp[10]; //ʱжͷ - -> ֵ + + VCard_Info.DetInfo.DetWinIdex[temp_loop] = 0x00; + VCard_Info.DetInfo.FullFlag[temp_loop] = 0x00; + + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʼӳ˿%d ӳ:%d ӳַ:%d ӳ·:%d ֵ:%d-%d ʹܱ־:%d - %dS",\ + temp_loop,\ + VCard_Info.Port_Info[temp_loop].HPort_Type,\ + VCard_Info.Port_Info[temp_loop].HPort_Addr,\ + VCard_Info.Port_Info[temp_loop].HPort_Loop,\ + VCard_Info.DetInfo.Trigger_Thres[temp_loop],\ + VCard_Info.DetInfo.Release_Thres[temp_loop],\ + VCard_Info.Port_Info[temp_loop].PortEnFlag,\ + VCard_Info.DetInfo.DetWinTotalNum[temp_loop]); + } + + VCard_Info.PortInit_Flag = 0x01; + VCard_Info.DetInfo.Det1sTime = 0x00; + + if(VCard_Info.ExistState == SOMEONE) + { + /*ǰʼΪ״̬*/ + VCard_Info.ConGroupIndx = DevActionGlobal.VC_ConNToSGruop + 1; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʼ޿ȡ״̬ - "); + VCard_Info.ExistState = SOMEONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + /*ջ·ijʱ״̬ - ע·1ĬDz忨ȡ磬볤ʱͳ*/ + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = VCard_Info.DetInfo.DetWinTotalNum[i]; + VCard_Info.ActThreshold[i] = 100; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0xFF, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + + }else { + /*ǰʼΪ״̬*/ + VCard_Info.ExistState = NOONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + VCard_Info.ConGroupIndx = VC_CONDGROUP_Default_StartGroup; //жϵĵһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʼ޿ȡ״̬ - ",condata.Condi_Gruop,condata.Condi_Subset); + + /*ջ·ijʱ״̬ - ע·1ĬDz忨ȡ磬볤ʱͳ*/ + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = 0x00; + VCard_Info.ActThreshold[i] = 0; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0x00, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + + } + + KeepFlag = 0x01; + } + /*ʼӳ˿ڽ*/ + + + /*˿״̬Լֵ㿪ʼ */ + if((SysTick_1ms - VCard_Info.PortTick >= 100) && (VCard_Info.PortInit_Flag == 0x01)) + { + VCard_Info.PortTick = SysTick_1ms; + + VCard_Info.DetInfo.Det1sTime++; + + if(VCard_Info.DetInfo.Det1sTime >= 10) VCard_Info.DetInfo.Det30sTime++; + + for(uint8_t i = 0; i < VIRTUAL_PORT_MAX; i++) + { + switch(VCard_Info.Port_Info[i].HPort_Type) + { + case Dev_Host_LVinput: + tempaddr = Find_AllDevice_List_Information(VCard_Info.Port_Info[i].HPort_Type,VCard_Info.Port_Info[i].HPort_Addr); + if(tempaddr != 0x00) + { +// SRAM_DMA_Read_Buff((uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO),tempaddr+Dev_Privately); +// +// if((DevLVinputInfo.DevReadBufLast[VCard_Info.Port_Info[i].HPort_Loop] == KeyPress) +// || (DevLVinputInfo.DevReadBufLast[VCard_Info.Port_Info[i].HPort_Loop] == KeyHold) ) +// { +// +// VCard_Info.PortState[i] = KeyPress; +// VCard_Info.DetInfo.TriggerNum[i]++; +// +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x03; //ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d - CH%d",VCard_Info.Port_Info[i].HPort_Loop,i); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyPress; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyPress; //ƽ״̬ǰ޵ƽ仯 +// } +// } +// else if( DevLVinputInfo.DevReadBufLast[VCard_Info.Port_Info[i].HPort_Loop] == KeyRelease ) +// { +// VCard_Info.PortState[i] = KeyRelease; +// +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x04; //½ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d ͷ - CH%d",VCard_Info.Port_Info[i].HPort_Loop,i); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyRelease; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyRelease; //ƽ״̬ǰ޵ƽ仯 +// } +// } + } + break; + case DEV_RS485_CARD: + tempaddr = Find_AllDevice_List_Information(VCard_Info.Port_Info[i].HPort_Type,VCard_Info.Port_Info[i].HPort_Addr); + if(tempaddr != 0x00) + { +// SRAM_DMA_Read_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),tempaddr+Dev_Privately); +// +// /*2025-09-03 ޸RS485ȡ - ж*/ +// if(Rs485CardInfo.Rs485CardFlag == 0x01) +// { +// VCard_Info.PortState[i] = KeyPress; +// +// VCard_Info.DetInfo.TriggerNum[i]++; +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyPress; +// } +// } +// }else { +// VCard_Info.PortState[i] = KeyRelease; +// +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyRelease; +// } +// } +// } + } + break; + case DEV_RS485_SWT: + tempaddr = Find_AllDevice_List_Information(VCard_Info.Port_Info[i].HPort_Type,VCard_Info.Port_Info[i].HPort_Addr); + if(tempaddr != 0x00) + { + Device_Public_Information_G BUS_Public; // + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),tempaddr); + if(BUS_Public.Protocol == 0x03) //A9IO + { + //SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),tempaddr+Dev_Privately); + + /*A9IO ޿ȡ߼޸ + 2025-02-28 + 1⣺ȡA9IO ״̬¼״̬ͻ¼޿ȡжһִеὫ״̬ + *ᵼ޿ȡȡA9IO״̬ + *ʽ: ȡA9IO ״̬Ϊʹ DevReadBuf_last ״̬ͬʱA9IOļжԸñʹӦ޸ + + 2⣺A9IO 㰴Ļ޿ȡ߼ûͷţһֱڴ + *ʽ: ӻƣǵ㰴Ļ޿ȡ߼жź3SЧ3S֮󽫸״̬Ϊͷ״̬ + */ +// if(Rs485SwiInfo.DevReadBuf_last[VCard_Info.Port_Info[i].HPort_Loop] == KeyPress) +// { +// if( (VCard_Info.PortState[i] == KeyPress) +// && ( SysTick_1s - VCard_Info.PortTiggleTick[i] >= 3 ) ) +// { +// VCard_Info.PortTiggleTick[i] = SysTick_1s; +// +// Rs485SwiInfo.DevReadBuf_last[VCard_Info.Port_Info[i].HPort_Loop] = KeyRelease; +// VCard_Info.PortState[i] = KeyRelease; +// +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x04; //½ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d:PressRelease",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d 㰴ͷ - CH%d",VCard_Info.Port_Info[i].HPort_Loop); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyRelease; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyRelease; //ƽ״̬ǰ޵ƽ仯 +// } +// +// BUS_Public.check = 0x00; +// BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); +// SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),tempaddr);/*ݱ*/ +// SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),tempaddr+Dev_Privately); +// +// }else if( VCard_Info.PortState[i] != KeyPress) +// { +// VCard_Info.PortTiggleTick[i] = SysTick_1s; +// VCard_Info.PortState[i] = KeyPress; +// VCard_Info.DetInfo.TriggerNum[i]++; +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x03; //ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d:Press",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d 㰴 - CH%d",VCard_Info.Port_Info[i].HPort_Loop); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyPress; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyPress; //ƽ״̬ǰ޵ƽ仯 +// } +// } +// } +// else if(Rs485SwiInfo.DevReadBuf_last[VCard_Info.Port_Info[i].HPort_Loop] == KeyHold) +// { +// VCard_Info.PortTiggleTick[i] = SysTick_1s; +// VCard_Info.PortState[i] = KeyPress; +// VCard_Info.DetInfo.TriggerNum[i]++; +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x03; //ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d - CH%d",VCard_Info.Port_Info[i].HPort_Loop); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyPress; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyPress; //ƽ״̬ǰ޵ƽ仯 +// } +// } +// else if(Rs485SwiInfo.DevReadBuf_last[VCard_Info.Port_Info[i].HPort_Loop] == KeyRelease) +// { +// VCard_Info.PortState[i] = KeyRelease; +// +// if(VCard_Info.PortState[i] != VCard_Info.PortStateLast[i]) +// { +// VCard_Info.PortStateLast[i] = VCard_Info.PortState[i]; +// +// VCard_Info.PortStateAct[i] = 0x04; //½ر仯 +// +// LOG_LogicInfo_DebugRecord("VCLog:T1:%d:%d",i,VCard_Info.PortState[i]); +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VCard ˿ڣ%d ͷ - CH%d",VCard_Info.Port_Info[i].HPort_Loop); +// if(i == 0x00) +// { +// VCard_Info.CardState = KeyRelease; +// } +// }else{ +// VCard_Info.PortStateAct[i] = KeyRelease; //ƽ״̬ǰ޵ƽ仯 +// } +// } + } + } + break; + default: + break; + } + + /*ʱ - */ + if( ( (VCard_Info.ExistState == NOONE) && (VCard_Info.ConGroupIndx == VC_CONDGROUP_Default_StartGroup) ) + || ( (VCard_Info.ExistState == SOMEONE) && (VCard_Info.ConGroupIndx == (DevActionGlobal.VC_ConNToSGruop + 1)) ) ) + { + if((i != 0x00) && (VCard_Info.Port_Info[i].PortEnFlag == 0x01)) //˿1̶Ϊпȡ豸Ļ·ͳ + { + portstate = 0x00; + if(VCard_Info.DetInfo.Det1sTime == 10) //100msһ״̬ 1sڼ10 + { + /*1S ʱ500ms㴥dzҲ */ + if(VCard_Info.DetInfo.TriggerNum[i] >= 5) + { + VCard_Info.DetInfo.TriggerNum[i] = 0x00; + portstate = 0x01; + }else { + portstate = 0x00; + } + + if(VCard_Info.DetInfo.FullFlag[i] == 0x01) + { + //ⴰ + if( DetWin_ReadData_Bit((i-1),VCard_Info.DetInfo.DetWinIdex[i]) != portstate ) + { + //֮ǰ״̬һ + if(portstate == 0x01) + { + if(VCard_Info.DetInfo.DetWinTrigger[i] < VCard_Info.DetInfo.DetWinTotalNum[i]) + { + VCard_Info.DetInfo.DetWinTrigger[i]++; + } + }else { + if(VCard_Info.DetInfo.DetWinTrigger[i] > 0) + { + VCard_Info.DetInfo.DetWinTrigger[i]--; + } + } + DetWin_WriteData_Bit((i-1),VCard_Info.DetInfo.DetWinIdex[i],portstate); + }else { + //֮ǰ״̬һı + } + }else { + //ⴰ δ + if(portstate == 0x01) + { + if(VCard_Info.DetInfo.DetWinTrigger[i] < VCard_Info.DetInfo.DetWinTotalNum[i]) + { + VCard_Info.DetInfo.DetWinTrigger[i]++; + } + } + DetWin_WriteData_Bit((i-1),VCard_Info.DetInfo.DetWinIdex[i],portstate); + } + + if(VCard_Info.DetInfo.DetWinIdex[i] < VCard_Info.DetInfo.DetWinTotalNum[i]) + { + VCard_Info.DetInfo.DetWinIdex[i]++; + }else { + VCard_Info.DetInfo.DetWinIdex[i] = 0x00; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + } + + /*ֵ*/ + VCard_Info.ActThreshold[i] = (float)VCard_Info.DetInfo.DetWinTrigger[i] * 100 / (float)VCard_Info.DetInfo.DetWinTotalNum[i]; + + /*30S - ǰдĻ¼һ´״̬*/ + if(VCard_Info.DetInfo.Det30sTime >= 30) + { + if(VCard_Info.ActThreshold[i] != 0x00) + { + /*־¼˿ڴռ - T6 + 2025-10-13 ֮ǰ¼˿ڴռT2 ·:ֵ:ռ + *ڸΪ ¼˿ڴռT6 ·:ռ:״̬:ֵ:ͷֵ + */ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˿ %d :%d %d - %d ֵ%.02f",i + 1,portstate,\ + VCard_Info.DetInfo.DetWinTrigger[i],VCard_Info.DetInfo.DetWinTotalNum[i],VCard_Info.ActThreshold[i]); + LOG_LogicInfo_DebugRecord("VCLog:T6:%d:%.02f",i,VCard_Info.ActThreshold[i],VCard_Info.ExistState,VCard_Info.DetInfo.Trigger_Thres[i],VCard_Info.DetInfo.Release_Thres[i]); + } + } + + } + } + }else { + //ͣʱͳ + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"·%d ͣʱͳ",i + 1); + } + } + + if(VCard_Info.DetInfo.Det1sTime >= 10) //100msһ״̬ 1sڼ10 + { + if(VCard_Info.DetInfo.Det30sTime >= 30) { + VCard_Info.DetInfo.Det30sTime = 0x00; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"- ״̬:%d :%d ж-%d,%d,%d,%d,%d,%d,%d,%d,%d,%d Time:%d-%d",VCard_Info.ExistState,VCard_Info.ConGroupIndx,\ + VCard_Info.PortStateAct[0],VCard_Info.PortStateAct[1],VCard_Info.PortStateAct[2],VCard_Info.PortStateAct[3],VCard_Info.PortStateAct[4],\ + VCard_Info.PortStateAct[5],VCard_Info.PortStateAct[6],VCard_Info.PortStateAct[7],VCard_Info.PortStateAct[8],VCard_Info.PortStateAct[9],\ + (SysTick_1s - VCard_Info.Condition_Trigger_Tick),(SysTick_1s - VCard_Info.Last_Trigger_Tick)); + } + + + + VCard_Info.DetInfo.Det1sTime = 0x00; + } + + KeepFlag = 0x01; + } + /*˿״̬Լֵ*/ + + /*жִпʼ*/ + if(VCard_Info.ExistState == NOONE) + { + for(uint8_t j = 0; j < DevActionGlobal.VC_ConNToSSubset; j++) + { + condata_save_flag = 0x00; + + list_addr = SRAM_VCard_ConNToS_Start_Addr + j * sizeof(CONDITION_STRUCT); + SRAM_DMA_Read_Buff((uint8_t*)&condata, sizeof(CONDITION_STRUCT), list_addr); + + /*һҪĻж*/ + if( (condata.Condi_Gruop == VC_CONDGROUP_Default_StartGroup) || (condata.Condi_Gruop == VCard_Info.ConGroupIndx) ) + { + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"- %d-%d ж-",condata.Condi_Gruop,condata.Condi_Subset); + + //ж - ʱ + temp_jumpe_time = condata.Judgment_Time; + if(condata.Judgment_Unit == 0x03) + { + temp_jumpe_time = temp_jumpe_time * 3600; //ʱ + }else if(condata.Judgment_Unit == 0x02) + { + temp_jumpe_time = temp_jumpe_time * 60; // + }else { + // + } + + //ж - ʱʱ + temp_tickout = condata.Timeout_Time; + if(condata.Timeout_Unit == 0x03) + { + temp_tickout = temp_tickout * 3600; //ʱ + }else if(condata.Timeout_Unit == 0x02) + { + temp_tickout = temp_tickout * 60; // + }else { + // + } + + //жǷ + if(((condata.Port_State[0] == 0x00) || (condata.Port_State[0] == VCard_Info.PortStateAct[0])) && + ((condata.Port_State[1] == 0x00) || (condata.Port_State[1] == VCard_Info.PortStateAct[1])) && + ((condata.Port_State[2] == 0x00) || (condata.Port_State[2] == VCard_Info.PortStateAct[2])) && + ((condata.Port_State[3] == 0x00) || (condata.Port_State[3] == VCard_Info.PortStateAct[3])) && + ((condata.Port_State[4] == 0x00) || (condata.Port_State[4] == VCard_Info.PortStateAct[4])) && + ((condata.Port_State[5] == 0x00) || (condata.Port_State[5] == VCard_Info.PortStateAct[5])) && + ((condata.Port_State[6] == 0x00) || (condata.Port_State[6] == VCard_Info.PortStateAct[6])) && + ((condata.Port_State[7] == 0x00) || (condata.Port_State[7] == VCard_Info.PortStateAct[7])) && + ((condata.Port_State[8] == 0x00) || (condata.Port_State[8] == VCard_Info.PortStateAct[8])) && + ((condata.Port_State[9] == 0x00) || (condata.Port_State[8] == VCard_Info.PortStateAct[9])) && + ((condata.Port_State[10] == 0x00) || (condata.Port_State[9] == VCard_Info.PortStateAct[10])) ) + { + //㴥 + if(condata.Trigger_Flag != 0x01) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + condata.Trigger_Flag = 0x01; + condata.Trigger_Tick = SysTick_1s; + + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + } + }else{ + //㴥 + if(condata.Trigger_Flag != 0x00) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + condata.Trigger_Flag = 0x00; + } + } + + //ʱжϣڡһʱʱ"һ" + if( (condata.Condi_Gruop != VC_CONDGROUP_Default_StartGroup) && (SysTick_1s - VCard_Info.Last_Trigger_Tick >= temp_tickout) ) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + VCard_Info.Last_Trigger_Tick = SysTick_1s; + + condata.Trigger_Flag = 0x00; + condata.Trigger_Tick = SysTick_1s; //־λ + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + + VCard_Info.ConGroupIndx = VC_CONDGROUP_Default_StartGroup; //-> ж1 + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-%d-%d жʱ %d-",condata.Condi_Gruop,condata.Condi_Subset,VCard_Info.ConGroupIndx); + }else { + //ʱж£жǷʱ + if( ( condata.Trigger_Flag == 0x01 ) && ( SysTick_1s - VCard_Info.Condition_Trigger_Tick >= temp_jumpe_time ) ) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + // - ʱ䣬ж + condata.Trigger_Flag = 0x00; + condata.Trigger_Tick = SysTick_1s; + + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + + /*ֹȴӡϢTFTP־*/ + if( condata.Condi_Gruop == VCard_Info.ConGroupIndx ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit," %d %d",condata.Condi_Gruop,VCard_Info.ConGroupIndx); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"- ״̬:%d :%d ж-%d,%d,%d,%d,%d,%d,%d,%d,%d,%d",VCard_Info.ExistState,VCard_Info.ConGroupIndx,\ + VCard_Info.PortStateAct[0],VCard_Info.PortStateAct[1],VCard_Info.PortStateAct[2],VCard_Info.PortStateAct[3],VCard_Info.PortStateAct[4],\ + VCard_Info.PortStateAct[5],VCard_Info.PortStateAct[6],VCard_Info.PortStateAct[7],VCard_Info.PortStateAct[8],VCard_Info.PortStateAct[9]); + + LOG_LogicInfo_DebugRecord("VCLog:T3:%d:%d:%d:%d%d%d%d%d%d%d%d%d%d",\ + condata.Condi_Gruop,j,condata.Exist_Flag,condata.Port_State[0],condata.Port_State[1],condata.Port_State[2],\ + condata.Port_State[3],condata.Port_State[4],condata.Port_State[5],condata.Port_State[6],condata.Port_State[7],\ + condata.Port_State[8],condata.Port_State[9]); + }else { + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit," %d %d %d",condata.Condi_Gruop,VCard_Info.ConGroupIndx,j); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"- ״̬:%d :%d ж-%d,%d,%d,%d,%d,%d,%d,%d,%d,%d",VCard_Info.ExistState,VCard_Info.ConGroupIndx,\ + VCard_Info.PortStateAct[0],VCard_Info.PortStateAct[1],VCard_Info.PortStateAct[2],VCard_Info.PortStateAct[3],VCard_Info.PortStateAct[4],\ + VCard_Info.PortStateAct[5],VCard_Info.PortStateAct[6],VCard_Info.PortStateAct[7],VCard_Info.PortStateAct[8],VCard_Info.PortStateAct[9]); + } + + //л飬ͬʱ¼ʱ䣬һʱжʹ + VCard_Info.Last_Trigger_Tick = SysTick_1s; + VCard_Info.ConGroupIndx = condata.Condi_Gruop + 1; + VCard_Info.Last_ConGroupType = 0x00; + + if( VCard_Info.ConGroupIndx > DevActionGlobal.VC_ConNToSGruop ) + { + VCard_Info.ConGroupIndx = DevActionGlobal.VC_ConNToSGruop + 1; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-%d-%d ж-",condata.Condi_Gruop,condata.Condi_Subset); + VCard_Info.ExistState = SOMEONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-¼:Ž--"); + VCard_Info.Action |= VC_Event_DoorSensor_Flag; + SRAM_Write_Byte(VC_EventID_DoorSensor,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_DoorSensor); + + /*ջ·ijʱ״̬ - ע·1ĬDz忨ȡ磬볤ʱͳ*/ + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = VCard_Info.DetInfo.DetWinTotalNum[i]; + VCard_Info.ActThreshold[i] = 100; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0xFF, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + } + } + } + + if(condata_save_flag == 0x01) + { + SRAM_DMA_Write_Buff((uint8_t*)&condata, sizeof(CONDITION_STRUCT), list_addr); + } + } + } + } + else if(VCard_Info.ExistState == SOMEONE) + { + /*ж*/ + for(uint8_t j = 0; j < DevActionGlobal.VC_ConSToNSubset; j++) + { + condata_save_flag = 0x00; + + list_addr = SRAM_VCard_ConSToN_Start_Addr + j * sizeof(CONDITION_STRUCT); + SRAM_DMA_Read_Buff((uint8_t*)&condata, sizeof(CONDITION_STRUCT), list_addr); + + /*һҪĻж*/ + if( (condata.Condi_Gruop == (DevActionGlobal.VC_ConNToSGruop + 1) ) || (condata.Condi_Gruop == VCard_Info.ConGroupIndx) ) + { + //ж - ʱ + temp_jumpe_time = condata.Judgment_Time; + if(condata.Judgment_Unit == 0x03) + { + temp_jumpe_time = temp_jumpe_time * 3600; //ʱ + }else if(condata.Judgment_Unit == 0x02) + { + temp_jumpe_time = temp_jumpe_time * 60; // + }else { + // + } + + //ж - ʱʱ + temp_tickout = condata.Timeout_Time; + if(condata.Timeout_Unit == 0x03) + { + temp_tickout = temp_tickout * 3600; //ʱ + }else if(condata.Timeout_Unit == 0x02) + { + temp_tickout = temp_tickout * 60; // + }else { + // + } + + if( (condata.Condi_Gruop != (DevActionGlobal.VC_ConNToSGruop + 1) ) && (condata.Condi_Gruop == VCard_Info.ConGroupIndx) ) + { + if( ( VCard_Info.Last_ConGroupType == VC_CONDGROUP_BrieflyLeaving_Type ) && (condata.Exist_Flag != VCard_Info.Last_ConGroupType) ) + { + /*¼ */ + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"¼ - %d",condata.Condi_Gruop); + VCard_Info.Last_ConGroupType = 0x00; + VCard_Info.Action |= VC_Event_BrieflyLeaving_Flag; + SRAM_Write_Byte(VC_EventID_BrieflyLeaving,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_BrieflyLeaving); + KeepFlag = 0x01; + }else if( ( VCard_Info.Last_ConGroupType == VC_CONDGROUP_LongTermLeaving_Type ) && (condata.Exist_Flag != VCard_Info.Last_ConGroupType) ) + { + /*ʱ¼ */ + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱ¼ - %d",condata.Condi_Gruop); + VCard_Info.Last_ConGroupType = 0x00; + VCard_Info.Action |= VC_Event_LongTermLeaving_Flag; + SRAM_Write_Byte(VC_EventID_LongTermLeaving,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_LongTermLeaving); + KeepFlag = 0x01; + } + } + + if(((condata.Port_State[0] == 0x00) || (condata.Port_State[0] == VCard_Info.PortStateAct[0])) && \ + ((condata.Port_State[1] == 0x00) || (condata.Port_State[1] == VCard_Info.PortStateAct[1])) && \ + ((condata.Port_State[2] == 0x00) || (condata.Port_State[2] == VCard_Info.PortStateAct[2])) && \ + ((condata.Port_State[3] == 0x00) || (condata.Port_State[3] == VCard_Info.PortStateAct[3])) && \ + ((condata.Port_State[4] == 0x00) || (condata.Port_State[4] == VCard_Info.PortStateAct[4])) && \ + ((condata.Port_State[5] == 0x00) || (condata.Port_State[5] == VCard_Info.PortStateAct[5])) && \ + ((condata.Port_State[6] == 0x00) || (condata.Port_State[6] == VCard_Info.PortStateAct[6])) && \ + ((condata.Port_State[7] == 0x00) || (condata.Port_State[7] == VCard_Info.PortStateAct[7])) && \ + ((condata.Port_State[8] == 0x00) || (condata.Port_State[8] == VCard_Info.PortStateAct[8])) && \ + ((condata.Port_State[9] == 0x00) || (condata.Port_State[8] == VCard_Info.PortStateAct[9])) && \ + ((condata.Port_State[10] == 0x00) || (condata.Port_State[9] == VCard_Info.PortStateAct[10])) ) + { + //㴥 + if(condata.Trigger_Flag != 0x01) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + condata.Trigger_Flag = 0x01; + condata.Trigger_Tick = SysTick_1s; + + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + } + }else{ + //㴥 + if(condata.Trigger_Flag != 0x00) + { + condata_save_flag = 0x01; + condata.Trigger_Flag = 0x00; + } + } + + //ʱжϣڡһʱʱ"һ" + if( (condata.Condi_Gruop != DevActionGlobal.VC_ConNToSGruop + 1) && (SysTick_1s - VCard_Info.Last_Trigger_Tick >= temp_tickout) ) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + VCard_Info.Last_Trigger_Tick = SysTick_1s; + + condata.Trigger_Flag = 0x01; //־λ + condata.Trigger_Tick = SysTick_1s; + + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + + VCard_Info.ConGroupIndx = DevActionGlobal.VC_ConNToSGruop + 1; //-> жĵһ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-%d-%d жʱ %d-",condata.Condi_Gruop,condata.Condi_Subset,VCard_Info.ConGroupIndx); + }else { + //ʱж£жǷʱ + if( ( condata.Trigger_Flag == 0x01 ) && ( SysTick_1s - VCard_Info.Condition_Trigger_Tick >= temp_jumpe_time ) ) + { + KeepFlag = 0x01; + condata_save_flag = 0x01; + + // - ʱ䣬ж + VCard_Info.Condition_Trigger_Tick = SysTick_1s; + condata.Trigger_Flag = 0x00; + condata.Trigger_Tick = SysTick_1s; + + if( condata.Condi_Gruop == VCard_Info.ConGroupIndx ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit," %d ",condata.Condi_Gruop); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"- ״̬:%d :%d ж-%d,%d,%d,%d,%d,%d,%d,%d,%d,%d",VCard_Info.ExistState,VCard_Info.ConGroupIndx,\ + VCard_Info.PortStateAct[0],VCard_Info.PortStateAct[1],VCard_Info.PortStateAct[2],VCard_Info.PortStateAct[3],VCard_Info.PortStateAct[4],\ + VCard_Info.PortStateAct[5],VCard_Info.PortStateAct[6],VCard_Info.PortStateAct[7],VCard_Info.PortStateAct[8],VCard_Info.PortStateAct[9]); + + LOG_LogicInfo_DebugRecord("VCLog:T3:%d:%d:%d:%d%d%d%d%d%d%d%d%d%d",\ + condata.Condi_Gruop,j,condata.Exist_Flag,condata.Port_State[0],condata.Port_State[1],condata.Port_State[2],\ + condata.Port_State[3],condata.Port_State[4],condata.Port_State[5],condata.Port_State[6],condata.Port_State[7],\ + condata.Port_State[8],condata.Port_State[9]); + }else { + // 1 + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit," %d %d %d",condata.Condi_Gruop,VCard_Info.ConGroupIndx,j); + } + + VCard_Info.Last_ConGroupType = condata.Exist_Flag; //ǰͱڴ"""ʱ" + + //л飬ͬʱ¼ʱ䣬һʱжʹ + VCard_Info.Last_Trigger_Tick = SysTick_1s; + VCard_Info.ConGroupIndx = condata.Condi_Gruop + 1; + + if( VCard_Info.ConGroupIndx > DevActionGlobal.VC_ConSToNGruop ) + { + VCard_Info.ExistState = NOONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + + VCard_Info.ConGroupIndx = VC_CONDGROUP_Default_StartGroup; //жϵĵһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-%d-%d ж-",condata.Condi_Gruop,condata.Condi_Subset); + + if(VCard_Info.CardState == 0x01) + { + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-¼:--"); + VCard_Info.Action |= VC_Event_CardedPersonLeft_Flag; + SRAM_Write_Byte(VC_EventID_CardedPersonLeft,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_CardedPersonLeft); + }else { + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-¼:޿--"); + VCard_Info.Action |= VC_Event_UncardedPersonLeft_Flag; + SRAM_Write_Byte(VC_EventID_UncardedPersonLeft,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_UncardedPersonLeft); + } + + /*ջ·ijʱ״̬ - ע·1ĬDz忨ȡ磬볤ʱͳ*/ + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = 0x00; + VCard_Info.ActThreshold[i] = 0; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0x00, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + } + } + } + + if(condata_save_flag == 0x01) + { + SRAM_DMA_Write_Buff((uint8_t*)&condata, sizeof(CONDITION_STRUCT), list_addr); + } + } + } + } + /*жִн*/ + + /*ֵж˿ʼ - ֵж߼ жϷǵһʱЧ */ + if( (VCard_Info.ExistState == NOONE) && (VCard_Info.ConGroupIndx == VC_CONDGROUP_Default_StartGroup) ) + { + /*ǰ״̬߼жϴ һʱִгʱжϣõĻ·һ·Ӧֵжϣ״̬Ϊ*/ + for(uint8_t i = 1; i < VIRTUAL_PORT_MAX; i++) + { + if( (VCard_Info.Port_Info[i].PortEnFlag == 0x01) && (VCard_Info.DetInfo.Trigger_Thres[i] != 0x00) ) + { + if(VCard_Info.ActThreshold[i] >= VCard_Info.DetInfo.Trigger_Thres[i]) + { + KeepFlag = 0x01; + + /*״̬ıΪˣл·Ļȫաˡ״̬䣬¿ʼ*/ + VCard_Info.Action |= VC_Event_RadarPersonDetected_Flag; + SRAM_Write_Byte(VC_EventID_RadarPersonDetected,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_RadarPersonDetected); + + VCard_Info.ExistState = SOMEONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + + VCard_Info.Last_ConGroupType = 0x00; + VCard_Info.ConGroupIndx = DevActionGlobal.VC_ConNToSGruop + 1; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-ʱ ·%d %d - %.02f ж-",i,VCard_Info.DetInfo.Trigger_Thres[i],VCard_Info.ActThreshold[i]); + + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = VCard_Info.DetInfo.DetWinTotalNum[i]; + VCard_Info.ActThreshold[i] = 100; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0xFF, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + + break; + } + } + } + }else if( (VCard_Info.ExistState == SOMEONE) && (VCard_Info.ConGroupIndx == (DevActionGlobal.VC_ConNToSGruop + 1) ) ) + { + /*ǰ״̬߼жϴ һʱִгʱжϣõĻ·һ·Ӧֵжϣ״̬Ϊ*/ + for(uint8_t i = 1; i < VIRTUAL_PORT_MAX; i++) + { + if( (VCard_Info.Port_Info[i].PortEnFlag == 0x01) && (VCard_Info.DetInfo.Release_Thres[i] < 100) ) + { + if(VCard_Info.ActThreshold[i] <= VCard_Info.DetInfo.Release_Thres[i]) + { + KeepFlag = 0x01; + + /*״̬ıΪˣл·Ļȫաˡ״̬䣬¿ʼ*/ + VCard_Info.Action |= VC_Event_RadarPersonLeft_Flag; + SRAM_Write_Byte(VC_EventID_RadarPersonLeft,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_RadarPersonLeft); + + VCard_Info.ExistState = NOONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + + VCard_Info.ConGroupIndx = VC_CONDGROUP_Default_StartGroup; //жϵĵһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-ʱ ·%d %d - %.02f ж-",i,VCard_Info.DetInfo.Release_Thres[i],VCard_Info.ActThreshold[i]); + + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = 0x00; + VCard_Info.ActThreshold[i] = 0; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0x00, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + + break; + } + } + } + } + /*ֵж˽*/ + + /*δȡ£ȡ*/ + + if( DevActionGlobal.People_Flag == 0x01 ) + { + DevActionGlobal.People_Flag = 0x00; + + KeepFlag = 0x01; + + /*д۵ǰ״̬жΪ˻ˣ״̬޸Ϊˣͬʱʱ߼еĻֵȫˢΪ*/ + VCard_Info.Action |= VC_Event_RS485ButtonPress_Flag; + SRAM_Write_Byte(VC_EventID_RS485ButtonPress,SRAM_UDP_ELEReport_VirtualCard); + LOG_LogicInfo_DebugRecord("VCLog:T4:%d",VC_EventID_RS485ButtonPress); + + VCard_Info.ExistState = SOMEONE; + DevActionGlobal.Person_Detected = VCard_Info.ExistState; + VCard_Info.Last_ConGroupType = 0x00; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-ڰ ǰ:%d %d %d--",VCard_Info.ConGroupIndx,(DevActionGlobal.VC_ConNToSGruop + 1),DevActionGlobal.VC_ConSToNGruop); + if( (VCard_Info.ConGroupIndx < (DevActionGlobal.VC_ConNToSGruop + 1)) || (VCard_Info.ConGroupIndx > DevActionGlobal.VC_ConSToNGruop) ) + { + VCard_Info.ConGroupIndx = DevActionGlobal.VC_ConNToSGruop + 1; //->жϵһ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-ڰ ת:%d --",VCard_Info.ConGroupIndx); + } + + for(uint8_t i= 1; i < VIRTUAL_PORT_MAX; i++) + { + if(VCard_Info.Port_Info[i].HPort_Type != 0x00) + { + VCard_Info.DetInfo.DetWinTrigger[i] = VCard_Info.DetInfo.DetWinTotalNum[i]; + VCard_Info.ActThreshold[i] = 100; + VCard_Info.DetInfo.DetWinIdex[i] = 0; + VCard_Info.DetInfo.FullFlag[i] = 0x01; + DetWin_WriteData((i - 1), 0xFF, ((VCard_Info.DetInfo.DetWinTotalNum[i] / 8) + 1 ) ); + } + } + + } + /*δȡ£ȡ*/ + + //˿ڱ仯״ֻ̬һΣ仯״̬ + if( (VCard_Info.PortStateAct[0] != VCard_Info.PortState[0]) + || (VCard_Info.PortStateAct[1] != VCard_Info.PortState[1]) + || (VCard_Info.PortStateAct[2] != VCard_Info.PortState[2]) + || (VCard_Info.PortStateAct[3] != VCard_Info.PortState[3]) + || (VCard_Info.PortStateAct[4] != VCard_Info.PortState[4]) + || (VCard_Info.PortStateAct[5] != VCard_Info.PortState[5]) + || (VCard_Info.PortStateAct[6] != VCard_Info.PortState[6]) + || (VCard_Info.PortStateAct[7] != VCard_Info.PortState[7]) + || (VCard_Info.PortStateAct[8] != VCard_Info.PortState[8]) + || (VCard_Info.PortStateAct[9] != VCard_Info.PortState[9]) + || (VCard_Info.PortStateAct[10] != VCard_Info.PortState[10]) ) + { + KeepFlag = 0x01; + + VCard_Info.PortStateAct[0] = VCard_Info.PortState[0]; + VCard_Info.PortStateAct[1] = VCard_Info.PortState[1]; + VCard_Info.PortStateAct[2] = VCard_Info.PortState[2]; + VCard_Info.PortStateAct[3] = VCard_Info.PortState[3]; + VCard_Info.PortStateAct[4] = VCard_Info.PortState[4]; + VCard_Info.PortStateAct[5] = VCard_Info.PortState[5]; + VCard_Info.PortStateAct[6] = VCard_Info.PortState[6]; + VCard_Info.PortStateAct[7] = VCard_Info.PortState[7]; + VCard_Info.PortStateAct[8] = VCard_Info.PortState[8]; + VCard_Info.PortStateAct[9] = VCard_Info.PortState[9]; + VCard_Info.PortStateAct[10] = VCard_Info.PortState[10]; + } + + if(0x01 == KeepFlag) + { + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&VCard_Info, sizeof(VIRTUALCARD_STRUCT)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),DevAddr+Dev_Privately); + } +} + +__attribute__((section(".non_0_wait"))) uint8_t Dev_VirtualCard_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType) +{ + Device_Public_Information_G BUS_Public; // + VIRTUALCARD_STRUCT VCard_Info; + uint8_t Ret = CtrlInvalid; //Ч + + + if(DevAddr == 0x00) return Ret; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),DevAddr+Dev_Privately); /*豸˽Ϣ*/ + + switch(DevInputType) + { + case 0x01: //Ž + case 0x02: // + case 0x03: //޿ + case 0x04: //״ + case 0x05: //״ + case 0x06: //ڰ + case 0x07: // + case 0x08: //ʱ + + if( ( VCard_Info.Action & (0x01 << (DevInputType - 1)) ) != 0x00 ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"-޿ȡ ¼:%02x - %02x ",VCard_Info.Action,DevInputType); + VCard_Info.Action &= ~(0x01 << (DevInputType - 1)); + Ret = CtrlValid; + } + break; + default: + break; + } + + + if(CtrlValid == Ret) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"VirtualCard Action Clear!!!!"); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&VCard_Info, sizeof(VIRTUALCARD_STRUCT)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),DevAddr+Dev_Privately); + + } + + return Ret; +} + +__attribute__((section(".non_0_wait"))) void BLV_VirtualCard_Control_State(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t devaddr,uint16_t DevOutputLoop,uint16_t start) +{ + uint8_t temp1 = 0,temp_start = 0,temp_content = 0; + Device_Public_Information_G BUS_Public; // + VIRTUALCARD_STRUCT VCard_Info; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"BLV_NoCard_Control_State"); + + if(devaddr == 0x00) return; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),devaddr+Dev_Privately); + + temp_start = start&0xFF; + temp_content = (start >> 8) & 0xFF; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"NoCard Ctrl:%d %d",temp_start,temp_content); + + switch(temp_start) + { + case 0x03: //ôڼʱ + if(temp_content <= 240) + { + //VCard_Info.DetWinTime = temp_content; + VCard_Info.PortInit_Flag = 0x00; + } + temp1++; + break; + default: // ֱӷ + break; + } + + if(temp1 != 0x00) + { + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&VCard_Info, sizeof(VIRTUALCARD_STRUCT)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&VCard_Info,sizeof(VIRTUALCARD_STRUCT),devaddr+Dev_Privately); + } +} + + + diff --git a/BLV_485_Driver/blv_not_dev_lvinput.c b/BLV_485_Driver/blv_not_dev_lvinput.c new file mode 100644 index 0000000..338fd42 --- /dev/null +++ b/BLV_485_Driver/blv_not_dev_lvinput.c @@ -0,0 +1,256 @@ +/* + * blv_not_dev_lvinput.c + * + * Created on: Nov 17, 2025 + * Author: cc + */ + +#include "blv_nor_dev_lvinput.h" +#include "blv_bus_dev_c5iofun.h" +#include "blv_rs485_dev_switchctrl.h" +#include "pc_devicetest_fun.h" + +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "ch564.h" + +#include "blv_netcomm_function.h" + +#include + + +/******************************************************************************* +* Function Name : BLV_Nor_Dev_LVinput_Init +* Description : ͨ豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Nor_Dev_LVinput_Init(uint8_t devaddr, uint16_t LoopMax) +{ + Device_Public_Information_G BUS_Public; + NOR_LVINPUT_INFO DevLVinputInfo; //ֲ + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&DevLVinputInfo,0,sizeof(NOR_LVINPUT_INFO)); + + BUS_Public.addr = devaddr; //豸ַ + BUS_Public.type = Dev_Host_LVinput; //豸 + + BUS_Public.DevFunInfo.Dev_Data_Process = Dev_LVinput_Dis; + BUS_Public.DevFunInfo.Dev_Input_Type_Get = Dev_LVinput_InType_Get; + + if(LoopMax > LVINPUTNUMMAX) + { + DevLVinputInfo.LVinputValidNum = LVINPUTNUMMAX; + }else{ + DevLVinputInfo.LVinputValidNum = LoopMax; + } + + DevLVinputInfo.DevC5IOAddr = Find_AllDevice_List_Information(DEV_C5IO_Type, 0x00); + Add_Nor_Device_To_List(&BUS_Public,(uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO)); +} + +/******************************************************************************* +* Function Name : Dev_LVinput_InType_Get +* Description : ⺯ +* Input : + DevAddr : 豸ַ + DevInputLoop : ·ַ + DevInputType +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Dev_LVinput_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType) +{ + Device_Public_Information_G BUS_Public; // + NOR_LVINPUT_INFO DevLVinputInfo; //ֲ + uint8_t Ret = CtrlInvalid; //Ч + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO),DevAddr+Dev_Privately); /*豸˽Ϣ*/ + + if(DevInputLoop >= DevLVinputInfo.LVinputValidNum) + { + return Ret; + } + + if(DevInputType == DevLVinputInfo.DevReadBuf[DevInputLoop]) //ҵ + { + DevLVinputInfo.DevReadBuf[DevInputLoop] = 0x00; // + Ret = CtrlValid; + } + + if(CtrlValid == Ret) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s %d: %d ",__func__,DevInputLoop, DevInputType); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&DevLVinputInfo, sizeof(NOR_LVINPUT_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO),DevAddr+Dev_Privately); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : Dev_LVinput_Dis +* Description : ɨ躯 +* Input : + DevAddr : 豸ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Dev_LVinput_Dis(uint32_t DevAddr) +{ + Device_Public_Information_G BUS_PublicLVinput; // + NOR_LVINPUT_INFO DevLVinputInfo; //ֲ + Device_Public_Information_G BUS_PublicC5IO; // + BUS_C5IO_INFO C5IO_Info; + uint8_t KeepFlag = 0x00; + + if( (0x00000000 == DevAddr) || (0xFFFFFFFF == DevAddr) ) + { + return ; + } + SRAM_DMA_Read_Buff((uint8_t *)&BUS_PublicLVinput,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO),DevAddr+Dev_Privately); + + if( (0x00000000 == DevLVinputInfo.DevC5IOAddr) || (0xFFFFFFFF == DevAddr) ) + { + return ; + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_PublicC5IO,sizeof(Device_Public_Information_G),DevLVinputInfo.DevC5IOAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),DevLVinputInfo.DevC5IOAddr+Dev_Privately); + + for(uint8_t i = 0;i DevLVinputInfo.HoldTick[i] + 1) && (DevLVinputInfo.DevReadBufLast[i] == KeyPress) ) ) + { + DevLVinputInfo.HoldTick[i] = SysTick_1s; + DevLVinputInfo.DevReadBuf[i] = KeyHold; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s Loop:%d Hold",__func__,i); + KeepFlag = 0x01; + } + } + + if(0x01 == KeepFlag) + { + BUS_PublicLVinput.check = 0x00; + BUS_PublicLVinput.check = DoubleData_CheckSum((uint8_t *)&BUS_PublicLVinput, sizeof(Device_Public_Information_G), (uint8_t *)&DevLVinputInfo, sizeof(NOR_LVINPUT_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_PublicLVinput, sizeof(Device_Public_Information_G),DevAddr); /*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&DevLVinputInfo,sizeof(NOR_LVINPUT_INFO),DevAddr+Dev_Privately); + + /*C5IO*/ + BUS_PublicC5IO.check = 0x00; + BUS_PublicC5IO.check = DoubleData_CheckSum((uint8_t *)&BUS_PublicC5IO, sizeof(Device_Public_Information_G), (uint8_t *)&C5IO_Info, sizeof(BUS_C5IO_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_PublicC5IO, sizeof(Device_Public_Information_G),DevLVinputInfo.DevC5IOAddr); /*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&C5IO_Info,sizeof(BUS_C5IO_INFO),DevLVinputInfo.DevC5IOAddr+Dev_Privately); + } +} + + + diff --git a/BLV_485_Driver/blv_rs485_dev_c12dimming.c b/BLV_485_Driver/blv_rs485_dev_c12dimming.c new file mode 100644 index 0000000..f8d9264 --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_c12dimming.c @@ -0,0 +1,468 @@ +/* + * blv_rs485_dev_c12dimming.c + * + * Created on: Nov 17, 2025 + * Author: cc + */ + +#include "blv_rs485_dev_c12dimming.h" + +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "ch564.h" + +#include + +#define C12Rs485AddrDefault 0x01 //ĬΪ1ַ ͨѶȻĬϵַ +#define DEVC12DimTYPE 0x03 //C12DimͨѶЭе + +/******************************************************************************* +* Function Name : BLW_RS485_C12Dim_Data_Init +* Description : 豸 - ѯ豸 +* Input : + type : ӵ豸 + addr : ӵ豸ַ + polling_cf 豸ѯݷͻص + processing_cf 豸ݴص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_RS485_C12Dim_Data_Init(Device_Public_Information_G *BUS_Public, RS485_LED_INFO *Rs485LED, uint16_t LoopNum) +{ + BUS_Public->polling_cf = (uint32_t)&BLW_C12DimCycleCtrl; + BUS_Public->processing_cf = (uint32_t)&BLW_Rs485_C12Dim_Check; + + if(LoopNum >= C12DIM_OUT_CH_MAX) //·Χ + { + Rs485LED->LEDLoopValidNum = C12DIM_OUT_CH_MAX; + } + else if(0x00 == LoopNum) + { + Rs485LED->LEDLoopValidNum = 0x01; + } + else //δΧ + { + Rs485LED->LEDLoopValidNum = LoopNum; + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"C12Dim豸·:%d", Rs485LED->LEDLoopValidNum); + + Rs485LED->LEDCtrlFlag = 0x01; + +} + +/******************************************************************************* +* Function Name : BLW_LEDCycleCtrl +* Description : BLWLEDѯƷͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLW_C12DimCycleCtrl(uint32_t dev_addr) +{ + uint8_t i; //ڱл· + uint8_t Ret = RS485OCCUPYNOTIME; + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LEDInfo; + uint8_t KeepFlag = 0x00; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); //й + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),dev_addr+Dev_Privately); + + for(i = 0; i < Rs485LEDInfo.LEDLoopValidNum; i++) + { + if(Rs485LEDInfo.DevSendBuf_last[i] != Rs485LEDInfo.DevSendBuf[i]) + { + Rs485LEDInfo.LEDCtrlFlag = 0x01; + Rs485LEDInfo.LEDCtrlCnt = BUS_Public.retry_num; + Rs485LEDInfo.DevReadBuf[i] = 0x01; //״̬仯һ + memcpy(Rs485LEDInfo.DevSendBuf_last, Rs485LEDInfo.DevSendBuf, Rs485LEDInfo.LEDLoopValidNum); //ͬ + + break; + } + } + + for(i = 0; i < Rs485LEDInfo.LEDLoopValidNum; i++) + { + if(Rs485LEDInfo.DevCtrlWayBuf_last[i] != Rs485LEDInfo.DevCtrlWayBuf[i]) // 0x00 + { + Rs485LEDInfo.LEDWayCtrlFlag |=(0x01< BUS_Public.retry_num) + { + if(Rs485LEDInfo.DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485 C12 LED DEV_IS_OFFLINE"); + LOG_Device_Online_Record(DEV_RS485_PWM,BUS_Public.addr,LogInfo_Device_Offline); //¼豸 + } + Rs485LEDInfo.DevOffline = DEV_IS_OFFLINE; // + if(Rs485LEDInfo.DevOffline != Rs485LEDInfo.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485LEDInfo.DevOfflineLast = Rs485LEDInfo.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + + if(0x00 != Rs485LEDInfo.Dim_GV_Flag) + { + Rs485LEDInfo.Dim_GV_Flag = 0x00; + } + }else{ + Rs485LEDInfo.DevSendCnt++; // + } + Rs485LEDInfo.inquire_tick = SysTick_1ms; + + /*ͨѶͳ*/ + BLV_Communication_Record(&Rs485LEDInfo.comm_record,0x01,0x00); + } + + if(0x01 == KeepFlag) + { + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485LEDInfo, sizeof(RS485_LED_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),dev_addr+Dev_Privately); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : BLW_Rs485_LED_Check +* Description : BLWLEDݴ +* Input : + dev_addr : 豸Ϣַ + data_addr : ݵַ + len ݳ +* Return : + 0x00ɹ + 0x01ʧ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLW_Rs485_C12Dim_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len) +{ + uint8_t rev = 0x01; + + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LED; + uint8_t data[0x20]; + + if(len > 0x20) + { + return rev; // + } + + SRAM_DMA_Read_Buff(data,len,data_addr); //482 + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + + if(( data[0] != C12Rs485AddrDefault ) || ( DEVC12DimTYPE != data[2] ) // + || ( len != (data[4] ) ) + ) //ַ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C12Dim ʽ"); + return rev; //Уļͷ + } + + if(data[5] == CheckSum_Overlook_Check(data, len, 5)) //Уͨ + { + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),dev_addr+Dev_Privately); + + switch(data[6]) + { + case 0x30: //ȡظ + case 0x31: //ƻظ + case 0x32: //ʽظ + case 0x33: //ȫûظ + rev = 0x00; + + if(Rs485LED.DevOffline != DEV_IS_ONLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485LED DEV_IS_ONLINE"); + LOG_Device_Online_Record(DEV_RS485_PWM,BUS_Public.addr,LogInfo_Device_Online); //¼豸 + } + Rs485LED.DevSendCnt = 0x00; + Rs485LED.DevOffline = DEV_IS_ONLINE; //豸 + if(Rs485LED.DevOffline != Rs485LED.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485LED.DevOfflineLast = Rs485LED.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + BLV_Communication_Record(&Rs485LED.comm_record,0x02,0x01); //¼ͨѶɹ + break; + } + switch(data[6]) + { + case 0x31: + Rs485LED.LEDCtrlFlag = 0x00; + /*־¼*/ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port,BUS_Public.baud,data,len); + break; + case 0x32: + Rs485LED.LEDWayCtrlFlag = 0x00; + /*־¼*/ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port,BUS_Public.baud,data,len); + break; + case 0x30: + /*⵽״̬ı䣬ű*/ + Rs485LED.LEDLightnessReadFlag = 0x00; + //Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C12Dimming Recv:",data,len); + if( Rs485LED.init_flag == 0x00) + { + /*ȡ״̬ - λ״̬*/ + for(uint8_t i = 0; i < Rs485LED.LEDLoopValidNum; i++) + { + Rs485LED.DevSendBuf[i] = data[8 + i] & 0x7F; + Rs485LED.DevSendBuf[i] = 0x00; //2025-11-05 ʱ + Rs485LED.DevSendBuf_last[i] = Rs485LED.DevSendBuf[i]; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C12Dimming CH%d Init State:%d",i,Rs485LED.DevSendBuf[i]); + } + Rs485LED.init_flag = 1; + } + break; + case 0x33: + Rs485LED.Dim_GV_Flag = 0x00; + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"C12 Global Set Ack:",data,len); + break; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485LED, sizeof(RS485_LED_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),dev_addr+Dev_Privately); + } + + return rev; +} + +#define C12DimCTRLSENDLEN 22 //C12Ʒͺ +/** + * @name BLW 12· еƺ + * @para + * dev_addr 豸ʼַ + * @return + * @attention ѭãѾж + */ +__attribute__((section(".non_0_wait"))) void BLW_Rs485_C12Dim_Ctrl(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo) +{ + uint8_t i; + //ַ 豸 շַ LEN У CMD 4ͨ 0.1s CH4 CH3 CH2 CH1 + uint8_t SendBuf[24];// = {0x00, 0x00, DEVC12DimTYPE, 0x01, C12DimCTRLSENDLEN, 0x18, 0x21, 0x0f, 0x64, 0x00, 0x50, 0x50, 0x50, 0x50}; + + SendBuf[0] = 0x00; //ַ + SendBuf[1] = 0x00; //0 + + if(Rs485LEDInfo->LEDSn > 0x0F) Rs485LEDInfo->LEDSn = 0x00; + SendBuf[1] = Rs485LEDInfo->LEDSn; + + SendBuf[2] = DEVC12DimTYPE; //豸 + SendBuf[3] = C12Rs485AddrDefault; //Ĭ1ַ + SendBuf[4] = C12DimCTRLSENDLEN; // + SendBuf[6] = 0x21; // + SendBuf[7] = 0xff; //8ͨ + SendBuf[8] = 0x0f; //4ͨ + + SendBuf[9] = Rs485LEDInfo->C12_Set_Time; //⽥ʱ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C12⽥ʱ:%d \r\n",Rs485LEDInfo->C12_Set_Time); + for(i = 0; i < Rs485LEDInfo->LEDLoopValidNum; i++) + { + SendBuf[21-i] = Rs485LEDInfo->DevSendBuf[i] & 0x7F; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"C12Dimming CH%d:%d \r\n",i,Rs485LEDInfo->DevSendBuf[i]); + } +// memcpy(&SendBuf[14], &Rs485LEDInfo->DevSendBuf[0], Rs485LEDInfo->LEDLoopValidNum); //ָʾƿ + SendBuf[5] = CheckSum_Overlook_Check(SendBuf, C12DimCTRLSENDLEN, 5); + + MCU485_SendString(BUS_Public->port,SendBuf,C12DimCTRLSENDLEN); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record(BUS_Public->port,BUS_Public->baud,SendBuf,C12DimCTRLSENDLEN); +} + +#define C12DimWAYCTRLLEN 12 +/** + * @name BLW 4· ѭ + * @para + * CfgDevAdd 豸ڵ + * PBLEDLoop ·ַ 0~3 + * @return + * @attention ѭãѾж + * ַ 豸 շַ У mask + * 00 09 03 01 0B 51 22 0F 01 00 64 + */ +__attribute__((section(".non_0_wait"))) void BLW_Rs485_C12Dim_Way_Ctrl(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo) +{ + uint8_t i; + //ַ 豸ͣ շַ LEN У CMD 4ͨ ģʽ + uint8_t SendBuf[C12DimWAYCTRLLEN];// = {0x00, 0x00, DEVC12DimTYPE, 0x01, C12DimWAYCTRLLEN, 0xBD, 0x24, 0x00, 0x01, 0x02, 0x01}; + + SendBuf[0] = 0x00; + if(Rs485LEDInfo->LEDSn > 0x0F) Rs485LEDInfo->LEDSn = 0x00; + SendBuf[1] = Rs485LEDInfo->LEDSn; //֡ + SendBuf[2] = DEVC12DimTYPE; // + SendBuf[3] = 0x01; + SendBuf[4] = C12DimWAYCTRLLEN; // + SendBuf[6] = 0x22; //ʽ + SendBuf[7] = Rs485LEDInfo->LEDWayCtrlFlag&0xFF; + SendBuf[8] = (Rs485LEDInfo->LEDWayCtrlFlag>>8)&0xFF; + + for(i = 0; i < Rs485LEDInfo->LEDLoopValidNum; i++) + { + if((Rs485LEDInfo->LEDWayCtrlFlag>>i)&0x01) + { + switch(Rs485LEDInfo->DevCtrlWayBuf_last[i]) + { + case CFG_Dev_CtrlWay_Is_Dim_CycleUp: //ѭ + SendBuf[9] = 0x01; //Ʒʽ + SendBuf[10] = 0x01; + break; + case CFG_Dev_CtrlWay_Is_Dim_CycleDown: //ѭ + SendBuf[9] = 0x01; + SendBuf[10] = 0x00; + break; + case CFG_Dev_CtrlWay_Is_Dim_Up: //ϵ + SendBuf[9] = 0x00; + SendBuf[10] = 0x01; + break; + case CFG_Dev_CtrlWay_Is_Dim_Down: //µ + SendBuf[9] = 0x00; + SendBuf[10] = 0x00; + break; + case CFG_Dev_CtrlWay_Is_Dim_Stop: //ֹͣ + SendBuf[9] = 0x02; + SendBuf[10] = 0x00; // + break; + } + break; //ֻһ + } + } + SendBuf[11] = Rs485LEDInfo->DevCtrlWayContect[i]; // + SendBuf[5] = CheckSum_Overlook_Check(SendBuf, C12DimWAYCTRLLEN, 5); + + MCU485_SendString(BUS_Public->port,SendBuf,C12DimWAYCTRLLEN); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record(BUS_Public->port,BUS_Public->baud,SendBuf,C12DimCTRLSENDLEN); +} + +#define C12DimREADLEN 7 +/** + * @name BLW 4· еȶȡ + * @para + * CfgDevAdd 豸ڵ + * @return + * @attention ѭãѾж + */ +__attribute__((section(".non_0_wait"))) void BLW_Rs485_C12Dim_Read(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo) +{ + //ַ 豸 շַ LEN У CMD + uint8_t SendBuf[C12DimREADLEN]; // = {0x00, 0x00, DEVC12DimTYPE, 0x01, C12DimREADLEN, 0xD8, 0x20}; + + SendBuf[0] = 0x00; //ѷַ + if(Rs485LEDInfo->LEDSn > 0x0F) Rs485LEDInfo->LEDSn = 0x00; + SendBuf[1] = Rs485LEDInfo->LEDSn; //֡ + SendBuf[2] = DEVC12DimTYPE; // + SendBuf[3] = C12Rs485AddrDefault; + SendBuf[4] = C12DimREADLEN; // + SendBuf[6] = 0x20; + + SendBuf[5] = CheckSum_Overlook_Check(SendBuf, C12DimREADLEN, 5); + + MCU485_SendString(BUS_Public->port,SendBuf,C12DimREADLEN); +} + +//ȫ +__attribute__((section(".non_0_wait"))) void BLW_C12_GlobalValue_Set(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo) +{ + uint8_t lens = 0x0B; + uint8_t SendBuf[15]; + memset(SendBuf,0,sizeof(SendBuf)); + + SendBuf[0] = 0x00; //ѷַ + if(Rs485LEDInfo->LEDSn > 0x0F) Rs485LEDInfo->LEDSn = 0x00; + SendBuf[1] = Rs485LEDInfo->LEDSn; //֡ + SendBuf[2] = DEVC12DimTYPE; // + SendBuf[3] = C12Rs485AddrDefault; + SendBuf[4] = lens; // + SendBuf[6] = 0x23; //Cmd + + SendBuf[7] = Rs485LEDInfo->Dim_GV_Flag; + SendBuf[8] = Rs485LEDInfo->Dim_Global_Value; //ȫ + SendBuf[9] = Rs485LEDInfo->LEDUpLightLimit; //ɵ + SendBuf[10] = Rs485LEDInfo->LEDDownLightLimit; //ɵ + + SendBuf[5] = CheckSum_Overlook_Check(SendBuf, lens, 5); + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"BLW_C12_GlobalValue_Set Buff",SendBuf,lens); + MCU485_SendString(BUS_Public->port,SendBuf,lens); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record(BUS_Public->port,BUS_Public->baud,SendBuf,lens); +} + + diff --git a/BLV_485_Driver/blv_rs485_dev_cardctrl.c b/BLV_485_Driver/blv_rs485_dev_cardctrl.c new file mode 100644 index 0000000..8f6e35f --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_cardctrl.c @@ -0,0 +1,472 @@ +/* + * blv_rs485_dev_cardctrl.c + * + * Created on: Nov 14, 2025 + * Author: cc + */ +#include "blv_rs485_dev_cardctrl.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "sram_mem_addr.h" +#include "ch564.h" + +#include + + +#define CARDACTIONCONVER(data) (*(uint16_t *)&data) //ʵu16ֵ һ ȽϺ͸ֵ + +#define REPEATSENDTIMEMAX 0x03 //ط +#define READ_LEN 0x09 + +#define Dev_Card_RecvData_Len_Max 0x20 + + +/*ָ궨*/ +typedef void (*DevFunP)(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo); + +#define RS485_DEV_PRO_FUN_01 DevExistJudgge(Dev_485_Card_Polling_Flag,BLV_RS485_Card_Polling_Init) //ѵ˿ +#define RS485_DEV_PRO_FUN_02 DevExistJudgge(Dev_485_Card_Active_Flag,BLV_RS485_Card_Active_Init) //˿ +#define RS485_DEV_PRO_FUN_03 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_04 ((DevFunP)NULL) + +/******************************************************************************* +* Function Name : BLV_RS485_Card_Active_Init +* Description : BLV忨ȡ ˿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_RS485_Card_Active_Init(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo) +{ + BUS_Public->polling_cf = (uint32_t)&BLV_RS485_Card_Cycle_Dis; + BUS_Public->processing_cf = (uint32_t)&BLV_Rs485_Card_Check; + + Rs485CardInfo->DevPort = Active_Port; //2025-08-21 Ŀ2164 ޸ + + //˿ڴ˿£Ĭ״̬Ϊ忨״̬ϢĬΪϢ + Rs485CardInfo->Rs485CardFlag = 0x01; + Rs485CardInfo->Rs485CardType = CARD_Guest_Identity; + Rs485CardInfo->Rs485CardFlagLast = Rs485CardInfo->Rs485CardFlag; + Rs485CardInfo->Rs485CardTypeLast = Rs485CardInfo->Rs485CardType; + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"˿ڲ忨ȡ:%d",Rs485CardInfo->DevPort); +} + +/******************************************************************************* +* Function Name : BLV_RS485_Card_Polling_Init +* Description : BLV忨ȡ ѯ˿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_RS485_Card_Polling_Init(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo) +{ + BUS_Public->polling_cf = (uint32_t)&BLV_RS485_Card_Cycle_Dis; + BUS_Public->processing_cf = (uint32_t)&BLV_Rs485_Card_Check; + + Rs485CardInfo->DevPort = Polling_Port; + Rs485CardInfo->DevInitFlag = 0x00; + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ѵ˿ڲ忨ȡ:%d",Rs485CardInfo->DevPort); +} + +/******************************************************************************* +* Function Name : BLV_RS485_Card_Data_For_Logic_Init +* Description : ̵ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_RS485_Card_Data_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + RS485_CARD_INFO Rs485CardInfo; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&Rs485CardInfo,0,sizeof(RS485_CARD_INFO)); + + BUS_Public.addr = dev_info->addr; //豸ַ + BUS_Public.type = dev_info->type; //豸 + BUS_Public.port = dev_info->port; //豸Ͷ˿ + BUS_Public.baud = 9600; //豸Ͳ + BUS_Public.retry_num = 0x03; //豸ط + BUS_Public.wait_time = 0x0064; //豸ݷ͵ȴظʱ - 100ms + BUS_Public.Protocol = dev_info->version; + Rs485CardInfo.DevOffline = Rs485CardInfo.DevOfflineLast = DEV_IS_LINEUNINIT; //߳ʼ + + BUS_Public.DevFunInfo.Dev_Input_Type_Get = Dev_Rs485_Card_InType_Get; + + switch(BUS_Public.Protocol) + { + case ENUM_RS485_DEV_PRO_01: if(NULL!=RS485_DEV_PRO_FUN_01) RS485_DEV_PRO_FUN_01(&BUS_Public, &Rs485CardInfo);break; // + case ENUM_RS485_DEV_PRO_02: if(NULL!=RS485_DEV_PRO_FUN_02) RS485_DEV_PRO_FUN_02(&BUS_Public, &Rs485CardInfo);break; // + case ENUM_RS485_DEV_PRO_03: if(NULL!=RS485_DEV_PRO_FUN_03) RS485_DEV_PRO_FUN_03(&BUS_Public, &Rs485CardInfo);break; //3 + case ENUM_RS485_DEV_PRO_04: if(NULL!=RS485_DEV_PRO_FUN_04) RS485_DEV_PRO_FUN_04(&BUS_Public, &Rs485CardInfo);break; + default: + break; + } + +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"˿ڲ忨ȡ_111:%d",Rs485CardInfo.DevPort); + + if((DevActionGlobal.sram_save_flag == 0xA8) && ((SRAM_Read_DW(SRAM_LOG_RCU_Reboot_Reason) == 0x05) || (SRAM_Read_DW(SRAM_LOG_RCU_Reboot_Reason) == 0x01) ) ) + { + Rs485CardInfo.Rs485CardFlag = DevActionGlobal.CardState; + Rs485CardInfo.Rs485CardFlagLast = DevActionGlobal.CardState; + Rs485CardInfo.Rs485CardType = DevActionGlobal.Rs485CardType; + Rs485CardInfo.Rs485CardTypeLast = DevActionGlobal.Rs485CardType; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"card init"); + } + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"card init end"); + + //ʼ + SRAM_Write_Byte(Rs485CardInfo.Rs485CardFlag,SRAM_UDP_ELEReport_CardState); //UDP ϱȡ״̬ʹ + SRAM_Write_Byte(Rs485CardInfo.Rs485CardType,SRAM_UDP_ELEReport_CardType); //UDP ϱȡ״̬ʹ + SRAM_Write_Byte(Rs485CardInfo.Rs485CardFlag,SRAM_UDP_ELEReport_CardState_Last); //UDP ϱȡ״̬ʹ + SRAM_Write_Byte(Rs485CardInfo.Rs485CardType,SRAM_UDP_ELEReport_CardType_Last); //UDP ϱȡ״̬ʹ + + + switch(dev_info->port) + { + case Active_Port: //˿ + BUS_Public.port = Active_Port; //豸Ͷ˿ + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO)); + Act485_Info.device_num += 1; + break; + case Polling_Port: //ѯ˿ + BUS_Public.port = Polling_Port; //豸Ͷ˿ + Add_POLL_Device_To_List(&BUS_Public,(uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO)); + Poll485_Info.device_num += 1; + break; + case Bus_port: //߶˿ + break; + default: + break; + } +} + +/******************************************************************************* +* Function Name : BLV_RS485_Card_Polling_Send +* Description : ѵ˿ѵͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_RS485_Card_Polling_Send(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo) +{ + uint8_t Cbuf[READ_LEN] = {0x55,0x55,0xee, 0x06, 0x07, 0x00, 0x01,0x00,0x00}; //0x18, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + Cbuf[5] = BUS_Public->addr; + NetCRC16(&Cbuf[3],Cbuf[3]); + + MCU485_SendString(BUS_Public->port,Cbuf,READ_LEN); + + /*ͨѶͳƼ¼*/ + Rs485CardInfo->inquire_tick = SysTick_1ms; + BLV_Communication_Record(&Rs485CardInfo->comm_record,0x01,0x00); +} + +/******************************************************************************* +* Function Name : BLV_RS485_Card_PortType_Send +* Description : ò忨ȡĶ˿ ͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_RS485_Card_PortType_Send(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo) +{ + uint8_t lens = 0x0A; + uint8_t data[10]; + + data[0] = 0x55; + data[1] = 0x55; + data[2] = 0xee; + data[3] = lens - 3; //ȥͷ3ֽ + data[4] = 0x07; //Type + data[5] = BUS_Public->addr; + data[6] = 0x07; //CMD + data[7] = Rs485CardInfo->DevPort; + + NetCRC16(&data[3],data[3]); + + MCU485_SendString(BUS_Public->port,data,lens); + + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"BLV_RS485_Card_PortType_Send:",data,lens); +} + +/******************************************************************************* +* Function Name : BLV_RS485_Card_Cycle_Dis +* Description : 忨ȡѯͺ +* Return : + 0x00û + 0x01 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_RS485_Card_Cycle_Dis(uint32_t dev_addr) +{ + uint8_t ret = RS485OCCUPYNOTIME; + Device_Public_Information_G BUS_Public; + RS485_CARD_INFO Rs485CardInfo; + + uint8_t keepflag = 0x00; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),dev_addr+Dev_Privately); + + if(Rs485CardInfo.DevPort != Rs485CardInfo.DevPort_Last) + { + Rs485CardInfo.DevPort_Last = Rs485CardInfo.DevPort; + Rs485CardInfo.DevPort_Flag = 0x01; + keepflag = 0x01; + } + + if(Rs485CardInfo.DevPort_Flag == 0x01) + { + BLV_RS485_Card_PortType_Send(&BUS_Public,&Rs485CardInfo); + ret = RS485OCCUPYTIME; + } + else + { + if(BUS_Public.port == Polling_Port) + { + BLV_RS485_Card_Polling_Send(&BUS_Public,&Rs485CardInfo); + ret = RS485OCCUPYTIME; + } + } + + if(ret == RS485OCCUPYTIME) + { + keepflag = 0x01; + if(Rs485CardInfo.DevSendCnt > REPEATSENDTIMEMAX) + { + if(Rs485CardInfo.DevOffline != DEV_IS_OFFLINE) //һ߼¼ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Dev_Card LogInfo_Device_Offline..........."); + LOG_Device_Online_Record(DEV_RS485_CARD,SRAM_Read_Byte(dev_addr+Dev_Addr),LogInfo_Device_Offline); //¼豸 + } + + Rs485CardInfo.DevOffline = DEV_IS_OFFLINE; //Ϊ + if(Rs485CardInfo.DevOffline != Rs485CardInfo.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485CardInfo.DevOfflineLast = Rs485CardInfo.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + + Rs485CardInfo.DevPort_Flag = 0x00; + }else{ + Rs485CardInfo.DevSendCnt++; //ʹۼ + } + } + + if(keepflag == 0x01) + { + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485CardInfo, sizeof(RS485_CARD_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),dev_addr+Dev_Privately); + } + + return ret; +} + +/******************************************************************************* +* Function Name : BLV_Rs485_Card_Check +* Description : BLV忨ȡݴ +* Input : + dev_addr : 豸Ϣַ + data_addr : ݵַ + len ݳ +* Return : + 0x00ɹ + 0x01ʧ + + ͷ LEN TYPE ADDR FUN L H Ԫ ¥ У + 55 55 EE 0E 07 01 01 01 00 00 00 00 00 00 00 0A 38 + +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_Rs485_Card_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len) +{ + uint8_t data[Dev_Card_RecvData_Len_Max]; + Device_Public_Information_G BUS_Public; // + RS485_CARD_INFO Rs485CardInfo; + + if(len > Dev_Card_RecvData_Len_Max) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Dev_Card Check_Len Fail!"); + return 0x01; //У + } + + if(len < 0x07) { + return 0x01; + } + + memset(data,0,sizeof(Dev_Card_RecvData_Len_Max)); + SRAM_DMA_Read_Buff(data, len, data_addr); + + if((data[0] != 0x55) || (data[1] != 0x55) || (data[2] != 0xEE) || ((data[3] + 0x03) != len) \ + || (data[4] != 0x07) || (data[5] != 0x01) \ + || ((data[len-2] + (data[len-1]<<8)) != NetCRC16_2(&data[3], len - 5)) + ) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"УļͷԻУ鲻!!"); + return 0x01; + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),dev_addr+Dev_Privately); + + if(Rs485CardInfo.DevOffline == DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Dev_Card LogInfo_Device_Online..........."); + LOG_Device_Online_Record(DEV_RS485_CARD,BUS_Public.addr, LogInfo_Device_Online); //¼豸 + } + + BLV_Communication_Record(&Rs485CardInfo.comm_record,0x02,0x01); //¼ͨѶɹ + Rs485CardInfo.DevSendCnt = 0x00; //յظ + Rs485CardInfo.DevOffline = DEV_IS_ONLINE; //豸 + if(Rs485CardInfo.DevOffline != Rs485CardInfo.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485CardInfo.DevOfflineLast = Rs485CardInfo.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + if(data[6] == 0x01) + { + if(len >= 8) + { + if(BUS_Public.port == Active_Port) + { + BLV_RS485_Card_Polling_Send(&BUS_Public,&Rs485CardInfo); + } + switch(data[7]) + { + case 0x02: // 2025-09-03 ȡM0 + Rs485CardInfo.Rs485CardFlag = 0x01; + break; + case 0x01: // 2025-09-03 ȡM1 + Rs485CardInfo.Rs485CardFlag = 0x01; + break; + case 0x00: // + Rs485CardInfo.Rs485CardFlag = 0x00; + break; + default: // 2025-09-26 ϱδ֪״̬ȡ־λ仯 + //Rs485CardInfo.Rs485CardFlag = 0x00; + break; + } + + Rs485CardInfo.Rs485CardType = data[8]; + + /*2025-08-04 ԵһͨѶȡ״̬Ϊʼ״̬Ҳִж*/ + if( (BUS_Public.port == Polling_Port) && (Rs485CardInfo.DevInitFlag == 0x00) ) + { + Rs485CardInfo.DevInitFlag = 0x01; + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"һͨѶ %d %d %d",DevActionGlobal.DevActionU64Cond.EleState,Rs485CardInfo.Rs485CardType,Rs485CardInfo.Rs485CardTypeLast); + + Rs485CardInfo.Rs485CardFlagLast = Rs485CardInfo.Rs485CardFlag; + Rs485CardInfo.Rs485CardTypeLast = Rs485CardInfo.Rs485CardType; + } + } + } + else if(data[6] == 0x07) + { + Rs485CardInfo.DevPort_Flag = 0x00; + } + + /*忨ȡ綯*/ + if( (Rs485CardInfo.DevInitFlag == 0x01) + && ( (Rs485CardInfo.Rs485CardFlag != Rs485CardInfo.Rs485CardFlagLast) + || (Rs485CardInfo.Rs485CardTypeLast != Rs485CardInfo.Rs485CardType) ) ) //״̬Ƚ + { + Rs485CardInfo.Rs485CardFlagLast = Rs485CardInfo.Rs485CardFlag; + Rs485CardInfo.Rs485CardTypeLast = Rs485CardInfo.Rs485CardType; + + + DevActionGlobal.Rs485CardType = Rs485CardInfo.Rs485CardType; + DevActionGlobal.CardState = Rs485CardInfo.Rs485CardFlag; + + SRAM_Write_Byte(Rs485CardInfo.Rs485CardFlag,SRAM_UDP_ELEReport_CardState); //UDP ϱȡ״̬ʹ + SRAM_Write_Byte(Rs485CardInfo.Rs485CardType,SRAM_UDP_ELEReport_CardType); //UDP ϱȡ״̬ʹ + + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"485忨ȡݱ仯",data,len); + + LOG_Device_COMM_ASK_TO_Reply_Record2(dev_addr+Dev_port,dev_addr+Dev_baud,(SysTick_1ms - Rs485CardInfo.inquire_tick),data,len); + + DevActionGlobal.Devi = BUS_Public.DevCoord; //ֱָ±ȥ + if(Rs485CardInfo.Rs485CardFlag == 0x01) + { + if(Rs485CardInfo.Rs485CardType != 0x00) + { + Rs485CardInfo.Rs485CardAction = 0x02 + Rs485CardInfo.Rs485CardType; // + }else { + Rs485CardInfo.Rs485CardAction = 0x01; //忨¼ + } + }else { + Rs485CardInfo.Rs485CardAction = 0x02; //ο¼ + } + } + + /*ݱSRAM*/ + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485CardInfo, sizeof(RS485_CARD_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),dev_addr+Dev_Privately); + + return 0x00; +} + +/******************************************************************************* +* Function Name : Get_BLV485_CARD_Online_Status +* Description : ȡRS485忨״̬ +* Input : +* DevAddr - 豸ַ +* Return : + 0x01 + 0x02 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BLV485_CARD_Online_Status(uint32_t devaddr) +{ + RS485_CARD_INFO Rs485CardInfo; + SRAM_DMA_Read_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),devaddr+Dev_Privately); + + if(Rs485CardInfo.DevOffline == DEV_IS_ONLINE) + { + return 0x01; + } + return 0x02; +} + +/******************************************************************************* +* Function Name : Dev_Rs485_Card_InType_Get +* Description : 忨ȡ⺯ +* Input : +* DevAddr - 豸ַ +* DevInputLoop - ·ַ +* DevInputType - +* Return : + 0x00Ч + 0x01Ч +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Dev_Rs485_Card_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType) +{ + Device_Public_Information_G BUS_Public; // + RS485_CARD_INFO Rs485CardInfo; //忨ȡֲ + uint8_t Ret = CtrlInvalid; //Ч + + /*豸˽Ϣ*/ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),DevAddr+Dev_Privately); + + if(Rs485CardInfo.Rs485CardAction == DevInputType) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"忨ȡ綯:%d ",Rs485CardInfo.Rs485CardAction); + Rs485CardInfo.Rs485CardAction = 0x00; + Ret = CtrlValid; + } + + if(CtrlValid == Ret) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"忨ȡ綯"); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485CardInfo, sizeof(RS485_CARD_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485CardInfo,sizeof(RS485_CARD_INFO),DevAddr+Dev_Privately); + } + + return Ret; +} + + + + + diff --git a/BLV_485_Driver/blv_rs485_dev_ledctrl.c b/BLV_485_Driver/blv_rs485_dev_ledctrl.c new file mode 100644 index 0000000..11b8dfe --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_ledctrl.c @@ -0,0 +1,561 @@ +/* + * blv_rs485_dev_ledctrl.c + * + * Created on: Nov 17, 2025 + * Author: cc + */ +#include "blv_rs485_dev_ledcrtl.h" +#include "ch564.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "ch564.h" + +#include "blv_netcomm_function.h" + +#include + +/*ָ궨*/ +typedef void (*DevFunP)(Device_Public_Information_G *BUS_Public, RS485_LED_INFO *Rs485LED, uint16_t LoopNum); //ݹָ ˽ָ + +/*豸궨忪ʼ*/ +#define RS485_DEV_PRO_FUN_01 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_02 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_03 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_04 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_05 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_06 ((DevFunP)NULL) + + +/******************************************************************************* +* Function Name : BLW_RS485_LED_For_Logic_Init +* Description : ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_RS485_LED_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LED; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&Rs485LED,0,sizeof(RS485_LED_INFO)); + + BUS_Public.addr = dev_info->addr; //豸485ַ + BUS_Public.type = dev_info->type; //豸 + BUS_Public.baud = dev_info->baud;; //豸Ͳ9600 + BUS_Public.retry_num = dev_info->retry; //豸ط + BUS_Public.wait_time = dev_info->writ_time; //豸ݷ͵ȴظʱ - 100ms + BUS_Public.Protocol = dev_info->version; + + Rs485LED.PWM_Set_Time=30; + Rs485LED.RGB_Set_Time=30; + Rs485LED.A8PB_Set_Time=30; + Rs485LED.A9LD_Set_Time=30; + Rs485LED.C12_Set_Time=30; + + Rs485LED.Dim_Global_Value = 100; + DevActionGlobal.DimGlobalValue = Rs485LED.Dim_Global_Value; + DevActionGlobal.Dim_Upper_limit = 100; + DevActionGlobal.Dim_Lower_limit = 0; + + BUS_Public.DevFunInfo.Dev_Output_Ctrl = BLW_LED_Control_State; + BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get = BLW_LED_Read_State; + + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl = BLW_LED_Group_Ctrl; + BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr = BLW_LED_Group_Read; + + Rs485LED.DevOffline = Rs485LED.DevOfflineLast = DEV_IS_LINEUNINIT; //״̬ʼ + switch(BUS_Public.Protocol) //Э汾 + { + case ENUM_RS485_DEV_PRO_01: if(NULL!=RS485_DEV_PRO_FUN_01) RS485_DEV_PRO_FUN_01(&BUS_Public, &Rs485LED, dev_info->output_num);break; // + case ENUM_RS485_DEV_PRO_02: if(NULL!=RS485_DEV_PRO_FUN_02) RS485_DEV_PRO_FUN_02(&BUS_Public, &Rs485LED, dev_info->output_num);break; // + case ENUM_RS485_DEV_PRO_03: if(NULL!=RS485_DEV_PRO_FUN_03) RS485_DEV_PRO_FUN_03(&BUS_Public, &Rs485LED, dev_info->output_num);break; //3 + case ENUM_RS485_DEV_PRO_04: if(NULL!=RS485_DEV_PRO_FUN_04) RS485_DEV_PRO_FUN_04(&BUS_Public, &Rs485LED, dev_info->output_num);break; + case ENUM_RS485_DEV_PRO_05: if(NULL!=RS485_DEV_PRO_FUN_05) RS485_DEV_PRO_FUN_05(&BUS_Public, &Rs485LED, dev_info->output_num);break; + case ENUM_RS485_DEV_PRO_06: if(NULL!=RS485_DEV_PRO_FUN_06) RS485_DEV_PRO_FUN_06(&BUS_Public, &Rs485LED, dev_info->output_num);break; + default: return ; //Э汾ڵ豸ֱ˳ӵ豸 + } + + switch(dev_info->port) + { + case Active_Port: //˿ + BUS_Public.port = Active_Port; //豸Ͷ˿ + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO)); + Act485_Info.device_num += 1; + break; + case Polling_Port: //ѯ˿ + BUS_Public.port = Polling_Port; //豸Ͷ˿ + Add_POLL_Device_To_List(&BUS_Public,(uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO)); //ӵ + Poll485_Info.device_num += 1; + break; + case Bus_port: //߶˿ + BUS_Public.port = Bus_port; //豸Ͷ˿ + Add_BUS_Device_To_List(&BUS_Public,(uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO)); + BUS485_Info.device_num += 1; + break; + } +} + +/******************************************************************************* +* Function Name : BLW_LED_Control_State +* Description : BLWLED״̬ƺ +* Input : + devaddr : 豸Ϣַ + loop · + start ״̬ +* Return : +* attention : temp10Żб +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_LED_Control_State(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t devaddr,uint16_t loop,uint16_t start) +{ + uint8_t temp1 = 0; + uint8_t CtrlMode; //ģʽ + uint8_t CtrlContect; + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LED; + + if(devaddr == 0x00) return; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + + if(loop >= Rs485LED.LEDLoopValidNum) //Ч· + { + return ; + } + CtrlMode = start&0x00ff; //ģʽ + CtrlContect = start>>8; // + + switch(CtrlMode) + { + case CFG_Dev_CtrlWay_Is_Dim_Stop: + case CFG_Dev_CtrlWay_Is_Dim_Up: + case CFG_Dev_CtrlWay_Is_Dim_Down: + Rs485LED.LEDLightnessReadFlag = 0x01; //Ψֹͣ£ŻᷢͶȡ + Rs485LED.LEDLightnessReadCnt = BUS_Public.retry_num; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ȡλģʽ:%d ȡ־:%d", CtrlMode, Rs485LED.LEDLightnessReadFlag); // + temp1++; + break; + } + switch(CtrlMode) + { + case CFG_Dev_CtrlWay_Is_Dim_CycleUp: //ʽ + case CFG_Dev_CtrlWay_Is_Dim_CycleDown: + case CFG_Dev_CtrlWay_Is_Dim_Stop: + Rs485LED.DevCtrlWayBuf[loop] = CtrlMode; // - CFG_Dev_CtrlWay_Is_LED_START + 1 + Rs485LED.DevCtrlWayContect[loop] = CtrlContect; // + temp1++; + break; + case CFG_Dev_CtrlWay_Is_Open: //״̬ + case CFG_Dev_CtrlWay_Is_Close: + + Rs485LED.DevSendBuf[loop] = CtrlContect; //ȸֵ + temp1++; + break; + case CFG_Dev_CtrlWay_Is_Dim_Open: //俪 + if(0x00 != Rs485LED.LEDLightRelease[loop]) //ڱֵ + { + CtrlContect = Rs485LED.LEDLightRelease[loop]; // + }else{ + CtrlContect = 0x64; //Ĭ + } + Rs485LED.DevSendBuf[loop] = CtrlContect; //ȸֵ + temp1++; + break; + case CFG_Dev_CtrlWay_Is_Dim_Up: //ϵ + if(Rs485LED.DevSendBuf[loop] + CtrlContect <= 100) + { + Rs485LED.DevSendBuf[loop] += CtrlContect; + } + else + { + Rs485LED.DevSendBuf[loop] = 100; //100 + } + temp1++; + break; + case CFG_Dev_CtrlWay_Is_Dim_Down: //µ + if(Rs485LED.DevSendBuf[loop] >= CtrlContect) + { + Rs485LED.DevSendBuf[loop] -= CtrlContect; + } + else + { + Rs485LED.DevSendBuf[loop] = 0; //0 + } + temp1++; + break; + case CFG_Dev_CtrlWay_Is_Dim_Up_Limit: //ϵ + if(0x00 != Rs485LED.DevSendBuf[loop]) + { + if(Rs485LED.DevSendBuf[loop] + CtrlContect <= 100) + { + Rs485LED.DevSendBuf[loop] += CtrlContect; + } + else + { + Rs485LED.DevSendBuf[loop] = 100; //100 + } + temp1++; + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Down_Limit: //µ + if(Rs485LED.DevSendBuf[loop] > CtrlContect) + { + Rs485LED.DevSendBuf[loop] -= CtrlContect; + temp1++; + } + + break; + } + + if(temp1 != 0x00) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"DevSendBuf loop:%d,start:%d",loop,start); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485LED, sizeof(RS485_LED_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + } +} + +/******************************************************************************* +* Function Name : BLW_LED_Read_State +* Description : BLWLED״̬ȡ +* Input : + devaddr : 豸Ϣַ + loop · +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t BLW_LED_Read_State(uint32_t devaddr,uint16_t loop) +{ + if(devaddr == 0x00) + return 0x00; + + RS485_LED_INFO Rs485LED; + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + + if(loop >= Rs485LED.LEDLoopValidNum) + { + return 0x00; //Χ ֱӷ0 + } + + return Rs485LED.DevSendBuf[loop]; +} + +/******************************************************************************* +* Function Name : BLW_LED_Read_State +* Description : BLWLED״̬ȡ +* Input : + devaddr : 豸Ϣַ +* Return : ״̬ - 0x01 0x02 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BLV485_LED_Online_Status(uint32_t devaddr) +{ + RS485_LED_INFO Rs485LED; + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LED,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + + if(Rs485LED.DevOffline == DEV_IS_ONLINE) + { + return 0x01; + } + return 0x02; +} + +/******************************************************************************* +* Function Name : BLW_LED_Group_Ctrl +* Description : BLW̵Ⱥ +* Input : + devaddr : 豸Ϣַ + CtrlFlagƱ־ ܳ32· + CtrlNum : Ƶ豸 һΪ׼ + start ״̬ 0x01 0x02 +* Return : +* attention : temp10Żб +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_LED_Group_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr,uint32_t devaddr, uint32_t CtrlFlag, uint8_t CtrlNum,uint16_t *start) +{ +// uint8_t crc_val = 0;//,temp1 = 0; +// uint1_t state; //0 1 + uint8_t i; + uint8_t CtrlMode = 0,CtrlContect = 0; + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LEDInfo; + + if(devaddr == 0x00) return; + +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"LED״̬Ⱥؿƿʼǰ·־%04X ·%d ", CtrlFlag, CtrlNum); + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + + if(CtrlNum >= Rs485LEDInfo.LEDLoopValidNum) + { + CtrlNum = Rs485LEDInfo.LEDLoopValidNum; + } + + for(i = 0; i < CtrlNum; i++) + { + if(CtrlFlag&(0x0001<>8; // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s ·%d:%04X ",__func__, i+1, start[i]); + + switch(CtrlMode) + { + case CFG_Dev_CtrlWay_Is_Dim_Stop: //ΨֹͣŻᷢͶȡ + Rs485LEDInfo.LEDLightnessReadFlag = 0x01; + Rs485LEDInfo.LEDLightnessReadCnt = BUS_Public.retry_num; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ģʽ:%dȡ־:%d", CtrlMode, Rs485LEDInfo.LEDLightnessReadFlag); // + break; + } + switch(CtrlMode) + { + case CFG_Dev_CtrlWay_Is_Dim_CycleUp: //ʽ + case CFG_Dev_CtrlWay_Is_Dim_CycleDown: + case CFG_Dev_CtrlWay_Is_Dim_Stop: + Rs485LEDInfo.DevCtrlWayBuf[i] = CtrlMode; + Rs485LEDInfo.DevCtrlWayContect[i] = CtrlContect; // + break; + case CFG_Dev_CtrlWay_Is_Open: //״̬ + case CFG_Dev_CtrlWay_Is_Close: + Rs485LEDInfo.DevSendBuf[i] = CtrlContect; //ȸֵ + break; + case CFG_Dev_CtrlWay_Is_Dim_Open: //俪 + if(0x00 != Rs485LEDInfo.LEDLightRelease[i]) //ڱֵ + { + CtrlContect = Rs485LEDInfo.LEDLightRelease[i]; // + }else{ + CtrlContect = 0x64; //Ĭ + } + Rs485LEDInfo.DevSendBuf[i] = CtrlContect; //ȸֵ + break; + case CFG_Dev_CtrlWay_Is_Dim_Up: //ϵ + if(Rs485LEDInfo.DevSendBuf[i] + CtrlContect <= 100) + { + Rs485LEDInfo.DevSendBuf[i] += CtrlContect; + }else + { + Rs485LEDInfo.DevSendBuf[i] = 100; //100 + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Down: //µ + if(Rs485LEDInfo.DevSendBuf[i] >= CtrlContect) + { + Rs485LEDInfo.DevSendBuf[i] -= CtrlContect; + }else{ + Rs485LEDInfo.DevSendBuf[i] = 0; //0 + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Up_Limit: //Ψĵ ϵ + if(0x00 != Rs485LEDInfo.DevSendBuf[i]) + { + if(Rs485LEDInfo.DevSendBuf[i] + CtrlContect <= 100) + { + Rs485LEDInfo.DevSendBuf[i] += CtrlContect; + }else{ + Rs485LEDInfo.DevSendBuf[i] = 100; //100 + } + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Down_Limit: //Ψĵ µ + if(0x00 != Rs485LEDInfo.DevSendBuf[i]) + { + if(Rs485LEDInfo.DevSendBuf[i] > CtrlContect) + { + Rs485LEDInfo.DevSendBuf[i] -= CtrlContect; + }else{ + Rs485LEDInfo.DevSendBuf[i] = 0x01; //2024-11-25 + } + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Up_Step_Cycle: //㰴ѭ + switch(Rs485LEDInfo.LedUpDown[i]) + { + case 0x00: // + if(Rs485LEDInfo.DevSendBuf[i] + CtrlContect < 100) + { + Rs485LEDInfo.DevSendBuf[i] += CtrlContect; + }else{ + Rs485LEDInfo.LedUpDown[i] = 0x01; + Rs485LEDInfo.DevSendBuf[i] = 100; //100 + } + break; + case 0x01: // + Rs485LEDInfo.LedUpDown[i] = 0x00; + Rs485LEDInfo.DevSendBuf[i] = 0; //0 + break; + default: + Rs485LEDInfo.LedUpDown[i] = 0x00; + break; + } + break; + case CFG_Dev_CtrlWay_Is_PWM_Set_Time: + Rs485LEDInfo.PWM_Set_Time=CtrlContect; + break; + case CFG_Dev_CtrlWay_Is_A9LD_Set_Time: + Rs485LEDInfo.A9LD_Set_Time=CtrlContect; + break; + case CFG_Dev_CtrlWay_Is_A8PB_Set_Time: + Rs485LEDInfo.A8PB_Set_Time=CtrlContect; + break; + case CFG_Dev_CtrlWay_Is_C12_Set_Time: + Rs485LEDInfo.C12_Set_Time=CtrlContect; + break; + case CFG_Dev_CtrlWay_Is_RGB_Set_Time: + Rs485LEDInfo.RGB_Set_Time=CtrlContect; + break; + case Dim_Global_Value_Cmd: + DevActionGlobal.DimGlobalValue = CtrlContect; //2025-08-22 + break; + case Dim_UpLimit_Value_Cmd: + DevActionGlobal.Dim_Upper_limit = CtrlContect; //2024-11-01 ÿɵԭΪťֵ + break; + case Dim_DnLimit_Value_Cmd: + DevActionGlobal.Dim_Lower_limit = CtrlContect; //2024-11-01 ÿɵԭΪťֵ + break; + } + } + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485LEDInfo, sizeof(RS485_LED_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); +} + +/******************************************************************************* +* Function Name : BLW_C12Dimming_Group_Ctrl +* Description : BLW̵Ⱥ +* Input : + devaddr : 豸Ϣַ + CtrlFlagƱ־ ܳ32· + CtrlNum : Ƶ豸 һΪ׼ + start ״̬ 0x01 0x02 +* Return : ״̬ ؿ һ ع +* attention : temp10Żб +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t BLW_LED_Group_Read(uint32_t devaddr, uint8_t SceneType, uint32_t ReadFlag, uint8_t ReadNum,uint16_t *start) +{ + uint8_t i = 0; + uint8_t Ret = 0x00; + uint8_t CtrlMode = 0,CtrlContect = 0; + uint8_t tempflag =0x00; + + if(devaddr == 0x00) return 0x00; + + Device_Public_Information_G BUS_Public; + RS485_LED_INFO Rs485LEDInfo; //̵ֲ + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),devaddr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + + if(ReadNum >= Rs485LEDInfo.LEDLoopValidNum) + { + ReadNum = Rs485LEDInfo.LEDLoopValidNum; + } + + switch(SceneType) + { + case 0x01: + for(i = 0; i < ReadNum; i++) + { + if(ReadFlag&(0x0001<>8; // + // Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"״̬Ⱥضȡʼǰ·%d:%04X ", i+1, start[i]); + + switch(CtrlMode) + { + case 0x01: //״̬ + case 0x02: //״̬ + if(Rs485LEDInfo.DevSendBuf[i] != CtrlContect) + { + Ret = DEV_STATE_CLOSE; + } + break; + case CFG_Dev_CtrlWay_Is_Dim_Open: //俪 ǰ״̬ͼȲһ + if((0x00 != Rs485LEDInfo.LEDLightRelease[i]) && (Rs485LEDInfo.LEDLightRelease[i] != Rs485LEDInfo.DevSendBuf[i])) + { + Ret = DEV_STATE_CLOSE; + } + else if((0x00 == Rs485LEDInfo.LEDLightRelease[i]) && (Rs485LEDInfo.DevSendBuf[i] != CtrlContect)) + { + Ret = DEV_STATE_CLOSE; + } + break; + } + } + } + break; + case 0x02: + for(i = 0; i < ReadNum; i++) + { + if(ReadFlag&(0x0001<>8; // + // Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"״̬Ⱥضȡʼǰ·%d:%04X ", i+1, start[i]); + + if(0x01 == CtrlMode) //״̬ + { + if(Rs485LEDInfo.DevSendBuf[i] == CtrlContect) + { + Ret = DEV_STATE_OPEN; + break; + } + } + } + } + break; + } + + if(0x00 == Ret) // + { + switch(SceneType) + { + case 0x01: + Ret = DEV_STATE_OPEN; + break; + case 0x02: + Ret = DEV_STATE_CLOSE; + break; + } + } + + for(i = 0; i < ReadNum; i++) + { + if(Rs485LEDInfo.DevSaveBuf[i]!=Rs485LEDInfo.DevSendBuf[i]) + { + Rs485LEDInfo.DevSaveBuf[i] = Rs485LEDInfo.DevSendBuf[i]; + if(Rs485LEDInfo.DevSendBuf[i]==0) + { + Udp_Addtion_Roomstate(DEV_RS485_PWM,BUS_Public.addr,i+1,((Rs485LEDInfo.DevSendBuf[i]<<8)|0x0002)); + }else{ + Udp_Addtion_Roomstate(DEV_RS485_PWM,BUS_Public.addr,i+1,((Rs485LEDInfo.DevSendBuf[i]<<8)|0x0001)); + } + tempflag++; + } + } + + if(tempflag!=0) + { + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485LEDInfo, sizeof(RS485_LED_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),devaddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485LEDInfo,sizeof(RS485_LED_INFO),devaddr+Dev_Privately); + } + + return Ret; +} + + diff --git a/BLV_485_Driver/blv_rs485_dev_switchctrl.c b/BLV_485_Driver/blv_rs485_dev_switchctrl.c new file mode 100644 index 0000000..fcf2850 --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_switchctrl.c @@ -0,0 +1,295 @@ +/* + * blv_rs485_dev_switchctrl.c + * + * Created on: Nov 13, 2025 + * Author: cc + */ +#include "blv_rs485_dev_switchctrl.h" +#include "blv_rs485_dev_touchswitch.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "ch564.h" + +#include + +typedef void (*DevFunP)(Device_Public_Information_G *BUS_Public, RS485_SWI_INFO *Rs485SwiInfo); //ݹָ ˽ָ + +#define RS485_DEV_PRO_FUN_01 DevExistJudgge(RS485_Switch_Touch_Flag, BLV_485_Dev_Touch_Switch_Init) //((DevFunP)NULL) //T1 +#define RS485_DEV_PRO_FUN_02 ((DevFunP)NULL) +#define RS485_DEV_PRO_FUN_03 ((DevFunP)NULL) //DevExistJudgge(RS485_Switch_A9IO_Flag, BLV_485_Dev_A9IO_Switch_Init) //((DevFunP)NULL) //A9IO +#define RS485_DEV_PRO_FUN_04 ((DevFunP)NULL) + + +/******************************************************************************* +* Function Name : BLW_RS485_Switch_For_Logic_Init +* Description : سʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_RS485_Switch_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&Rs485SwiInfo,0,sizeof(RS485_SWI_INFO)); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s -%d",__func__,dev_info->addr); + + BUS_Public.addr = dev_info->addr; //豸ַ + BUS_Public.type = dev_info->type; //豸 + BUS_Public.baud = dev_info->baud; //豸Ͳ + BUS_Public.retry_num = 0x00; //豸ط + BUS_Public.wait_time = 100; //豸ݷ͵ȴظʱ +// BUS_Public.polling_cf = (uint32_t)&BLW_Touch_SwitchCycleDis; +// BUS_Public.processing_cf = (uint32_t)&BLW_Rs485_Touch_Swi_Check; + + BUS_Public.Protocol = dev_info->version; + + BUS_Public.DevFunInfo.Dev_Input_Type_Get = Dev_Swi_InType_Get; + BUS_Public.DevFunInfo.Dev_Output_Ctrl = Dev_Swi_Output_Ctrl; + BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get = Dev_Swi_Loop_State; + + if(dev_info->input_num >= Key_BUFF_Size) Rs485SwiInfo.SwtInputValidNum = Key_BUFF_Size;//ʼ + else Rs485SwiInfo.SwtInputValidNum = dev_info->input_num; + + if(dev_info->output_num >= Key_BUFF_Size) Rs485SwiInfo.SwtOutputValidNum = Key_BUFF_Size;//ʼ + else Rs485SwiInfo.SwtOutputValidNum = dev_info->output_num; + Rs485SwiInfo.DevOffline = Rs485SwiInfo.DevOfflineLast = DEV_IS_LINEUNINIT; //״̬ʼ + switch(Rs485SwiInfo.SwtInputValidNum) + { + case 0x06: //Ϊ6 + Rs485SwiInfo.DevSendBuf[6] = 0x01; //򿪱 + break; + case 0x05: + Rs485SwiInfo.DevSendBuf[5] = 0x01; //򿪱 /*5أ6Ϊ*/ + break; + case 0x08: //Ϊ8 + Rs485SwiInfo.DevSendBuf[8] = 0x01; //򿪱 /*8أ9Ϊ*/ + break; + case 25: //Ϊ25 + Rs485SwiInfo.DevSendBuf[25] = 0x01; //򿪱 + break; + } + + switch(BUS_Public.Protocol) + { + case ENUM_RS485_DEV_PRO_01: if(NULL!=RS485_DEV_PRO_FUN_01) RS485_DEV_PRO_FUN_01(&BUS_Public, &Rs485SwiInfo);break; // + case ENUM_RS485_DEV_PRO_02: if(NULL!=RS485_DEV_PRO_FUN_02) RS485_DEV_PRO_FUN_02(&BUS_Public, &Rs485SwiInfo);break; // + case ENUM_RS485_DEV_PRO_03: if(NULL!=RS485_DEV_PRO_FUN_03) RS485_DEV_PRO_FUN_03(&BUS_Public, &Rs485SwiInfo);break; //3 + case ENUM_RS485_DEV_PRO_04: if(NULL!=RS485_DEV_PRO_FUN_04) RS485_DEV_PRO_FUN_04(&BUS_Public, &Rs485SwiInfo);break; + } + + switch(dev_info->port) + { + case Active_Port: //˿ + BUS_Public.port = Active_Port; //豸Ͷ˿ + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO)); + Act485_Info.device_num += 1; + break; + case Polling_Port: //ѯ˿ + BUS_Public.port = Polling_Port; //豸Ͷ˿ + Add_POLL_Device_To_List(&BUS_Public,(uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO)); //ӵ + Poll485_Info.device_num += 1; + break; + case Bus_port: //߶˿ + break; + } +} + +/******************************************************************************* +* Function Name : Get_Switch_Online_Status +* Description : ȡ״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_Switch_Online_Status(uint32_t devaddr) +{ + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + /*豸˽Ϣ*/ + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),devaddr+Dev_Privately); + + if(Rs485SwiInfo.DevOffline == DEV_IS_ONLINE) + { + return 0x01; + } + return 0x02; +} + +/******************************************************************************* +* Function Name : Dev_Swi_InType_Get +* Description : ȡ״̬ +* Input : +* DevAddr - 豸Ϣַ +* DevInputLoop - ·ַ Χ1~RS_SWITCH_CH_MAX +* DevInputType - +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Dev_Swi_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType) +{ + Device_Public_Information_G BUS_Public; // + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + uint8_t Ret = CtrlInvalid; //Ч + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAddr+Dev_Privately);/*豸˽Ϣ*/ + + if(DevInputLoop >= RS_SWITCH_CH_MAX) + { + return Ret; + } + + if((Rs485SwiInfo.MultiValidNo[DevInputLoop] > 0) && (Rs485SwiInfo.MultiValidNo[DevInputLoop] < 127)) //ǰ·Ч 2024-05-23 + { + Rs485SwiInfo.MultiNumber[DevInputLoop]++; + + if(Rs485SwiInfo.MultiNumber[DevInputLoop] > Rs485SwiInfo.MultiValidNo[DevInputLoop]) //Ч + { + Rs485SwiInfo.MultiNumber[DevInputLoop] = 0x01; + } + } + + if(DevInputType == Rs485SwiInfo.DevReadBuf[DevInputLoop]) + { + Rs485SwiInfo.DevReadBuf[DevInputLoop] = KeyNoAction; + + Ret = CtrlValid|(Rs485SwiInfo.MultiNumber[DevInputLoop]<<1); + + if(Ret > 1) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%d ·:%d ±:%d",BUS_Public.addr,DevInputLoop,Rs485SwiInfo.MultiNumber[DevInputLoop]); + } + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ضգ%d",Ret); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAddr+Dev_Privately); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : Dev_Swi_Output_Ctrl +* Description : ƺ +* Input : +* CfgDevAddIn - +* DevInputAddr - +* DevAddr - +* DevOutputLoop +* DevOutputType - +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Dev_Swi_Output_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t DevAddr, uint16_t DevOutputLoop, uint16_t DevOutputType) +{ + uint8_t start = 0x00; + uint8_t CtrlWay; +// uint8_t val_check = 0; +// uint16_t dev_datalen = 0x00; + Device_Public_Information_G BUS_Public; // + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + uint8_t KeepFlag = 0x00; //־ + + if( (0x00000000 == DevAddr) || (0xFFFFFFFF == DevAddr) ) + { + return ; + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddr); //й + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAddr+Dev_Privately);/*豸˽Ϣ*/ + + if(DevOutputLoop >= Rs485SwiInfo.SwtOutputValidNum) + { + return ; + } + + CtrlWay = DevOutputType&0x00ff; //ȡֽ + + switch(CtrlWay) //Ϊ0 + { + case 0x01: + start = 0x01; + if(DevOutputLoop == (Rs485SwiInfo.SwtOutputValidNum - 1)) + { + DevActionGlobal.SleepMode_State = 0x00; //˳˯ģʽ 2025-09-05 + DevActionGlobal.SleepLight_State = 0x01; + } + break; + case 0x02: + start = 0x00; + if(DevOutputLoop == (Rs485SwiInfo.SwtOutputValidNum - 1)) + { + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ 2025-09-05 + DevActionGlobal.SleepLight_State = 0x00; + } + break; + case 0x04: //˸ + start = Rs485SwiInfo.DevSendBuf[DevOutputLoop]; + if(0x01 == start) + { + start = 0x00; + } + else + { + start = 0x01; + } + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"485˸ֵ,start:%d\r\n",start); + break; + default: return; //ֱӷ + } + + if(Rs485SwiInfo.DevSendBuf[DevOutputLoop] != start)// + { + Rs485SwiInfo.DevSendBuf[DevOutputLoop] = start; + KeepFlag = 0x01; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"DevSendBuf loop:%d,start:%d\r\n",DevOutputLoop,start); + } + + if(0x01 == KeepFlag) + { + if(Active_Port == BUS_Public.port) + { + BLV_Active_Set_List_Addr(DevAddr); //Ψ豸ȴ + } + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAddr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAddr+Dev_Privately); + } + +// BLW_Touch_Switch_Feedback(DevAddr, DevOutputLoop, State); +} + +/******************************************************************************* +* Function Name : Dev_Swi_Loop_State +* Description : ָϢ·״̬õ +* Input : +* devaddr - ǰ豸ĵַ +* DevOutputLoop - ҪҵķϢ· +* Return : ·״̬ 1 2 0Ϊ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t Dev_Swi_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop) +{ + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + if(devaddr == 0x00) return 0x00; + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),devaddr+Dev_Privately); + + if(DevOutputLoop >= Rs485SwiInfo.SwtOutputValidNum) + { + return 0x00; + } + + if(Rs485SwiInfo.DevSendBuf[DevOutputLoop]) + { + return 0x01; + }else{ + return 0x02; + } +} + + diff --git a/BLV_485_Driver/blv_rs485_dev_tempctrl.c b/BLV_485_Driver/blv_rs485_dev_tempctrl.c new file mode 100644 index 0000000..4c62817 --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_tempctrl.c @@ -0,0 +1,1283 @@ +/* + * blv_rs485_dev_tempfun.c + * + * Created on: Nov 13, 2025 + * Author: cc + */ +#include "blv_rs485_dev_tempctrl.h" +#include "blv_rs485_dev_touchtempt1.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "sram_mem_addr.h" +#include "rtc.h" +#include "ch564.h" + +#include + +#define REPEATSENDTIMEMAX 0x03 //ط +#define Dev_Temp_RecvData_Len_Max 0x20 //¿ݳ + +/*ָ궨*/ +typedef void (*DevFunP)(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485Tem); //ݹָ ˽ָ + +/*豸궨忪ʼ*/ +#define RS485_DEV_PRO_FUN_01 DevExistJudgge(RS485_Temp_T1_Flag, BLWOut_RS485_TempT1_Data_Init) //((DevFunP)NULL) //T1¿ +#define RS485_DEV_PRO_FUN_02 ((DevFunP)NULL) //DevExistJudgge(RS485_Temp_C7T_Flag, BLV_RS485_C7T_Data_Init) //((DevFunP)NULL) //C7T¿ +#define RS485_DEV_PRO_FUN_03 DevExistJudgge(RS485_Temp_T1_Flag_Si, BLWOut_RS485_TempT1D_Data_Init) //T1¿ Ĺ 2023-03-24 +#define RS485_DEV_PRO_FUN_04 DevExistJudgge(RS485_Temp_T1_Active_Flag, BLWOut_RS485_TempT1_Activ_Init) //T1¿ Ĺ ˿ 2024-11-05 + +/*ļڵĺ - ļⲻɵ*/ +uint8_t Dev_TEMPCTRL_InType_Get(uint32_t CfgDevAddIn, uint16_t DevInputLoop, uint16_t DevInputType); +void Dev_TEMPCTRL_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t CfgDevAddOut, uint16_t DevOutputLoop, uint16_t DevOutputType); + +/******************************************************************************* +* Function Name : BLW_RS485_TempFun_For_Logic_Init +* Description : ̵ʼϢ߼ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_RS485_TempFun_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len) +{ + Device_Public_Information_G BUS_Public; + RS485_TEMP_INFO Rs485TempT1; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&Rs485TempT1,0,sizeof(RS485_TEMP_INFO)); + + BUS_Public.addr = dev_info->addr; //豸ַ + BUS_Public.type = dev_info->type; //豸 + BUS_Public.port = dev_info->port; //豸˿ + BUS_Public.baud = dev_info->baud; //豸Ͳ + BUS_Public.retry_num = dev_info->retry; //豸ط + BUS_Public.wait_time = dev_info->writ_time; //豸ݷ͵ȴظʱ - 200ms + BUS_Public.Protocol = dev_info->version; + + BUS_Public.DevFunInfo.Dev_Input_Type_Get = Dev_TEMPCTRL_InType_Get; + BUS_Public.DevFunInfo.Dev_Output_Ctrl = Dev_TEMPCTRL_Ctrl; + + Rs485TempT1.TemState.on_off = 1; + Rs485TempT1.TemState.set_t = 25; + Rs485TempT1.TemState.indoor_t = 26; + Rs485TempT1.DevOfflineLast = DEV_IS_LINEUNINIT; //״̬ʼ + Rs485TempT1.DevOffline = Rs485TempT1.DevOfflineLast; + + switch(BUS_Public.Protocol) + { + case ENUM_RS485_DEV_PRO_01: if(NULL!=RS485_DEV_PRO_FUN_01) RS485_DEV_PRO_FUN_01(&BUS_Public, &Rs485TempT1);break; // + case ENUM_RS485_DEV_PRO_02: if(NULL!=RS485_DEV_PRO_FUN_02) RS485_DEV_PRO_FUN_02(&BUS_Public, &Rs485TempT1);break; // + case ENUM_RS485_DEV_PRO_03: if(NULL!=RS485_DEV_PRO_FUN_03) RS485_DEV_PRO_FUN_03(&BUS_Public, &Rs485TempT1);break; //3 + case ENUM_RS485_DEV_PRO_04: if(NULL!=RS485_DEV_PRO_FUN_04) RS485_DEV_PRO_FUN_04(&BUS_Public, &Rs485TempT1);break; + } + + Rs485TempT1.ValveNoExist = dev_info->priproperty[0]; //޷ + + switch(dev_info->port) + { + case Active_Port: //˿ + BUS_Public.port = Active_Port; //豸Ͷ˿ + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO)); + Act485_Info.device_num += 1; + break; + case Polling_Port: //ѯ˿ + BUS_Public.port = Polling_Port; //豸Ͷ˿ + Add_POLL_Device_To_List(&BUS_Public,(uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO)); + Poll485_Info.device_num += 1; + break; + case Bus_port: //߶˿ + break; + } +} + +/******************************************************************************* +* Function Name : Dev_Temp_State_Sync +* Description : յ״̬ͬ sync_temp ״̬ͬ temp +* Input : +* temp - յ״̬ +* sync_temp - յ״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Dev_Temp_State_Sync(TemState_Struct *temp,TemState_Struct *sync_temp) +{ + temp->on_off = sync_temp->on_off; + temp->mode = sync_temp->mode; + temp->fan = sync_temp->fan; + temp->valve = sync_temp->valve; + temp->set_t = sync_temp->set_t; + temp->indoor_t = sync_temp->indoor_t; +} + +/******************************************************************************* +* Function Name : Dev_Temp_State_Data +* Description : յ״̬תΪuint16_t +* Input : +* temp - յ״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t Dev_Temp_State_Data(TemState_Struct temp) +{ + uint16_t temp_data = 0; + + temp_data = temp.on_off & 0x01; + temp_data <<= 2; + temp_data |= temp.mode & 0x03; + temp_data <<= 2; + temp_data |= temp.fan & 0x03; + temp_data <<= 1; + temp_data |= temp.valve & 0x01; + temp_data <<= 5; + temp_data |= temp.set_t & 0x1F; + temp_data <<= 5; + temp_data |= temp.indoor_t & 0x1F; + + return temp_data; +} + +/******************************************************************************* +* Function Name : Dev_TEMPCTRL_InType_Get +* Description : յ״̬õԼ豸״̬õ +* Input : +* CfgDevAddIn - 봥ڵ +* DevInputLoop - 豸· Ҳǿյ± Χ1~3 +* DevInputType - +* Return : · +* 0x01:̵״̬ı +* 0x00:̵״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Dev_TEMPCTRL_InType_Get(uint32_t CfgDevAddIn, uint16_t DevInputLoop, uint16_t DevInputType) +{ + Device_Public_Information_G BUS_Public; // + RS485_TEMP_INFO Rs485Tem; //¿ֲ + uint8_t Ret = CtrlInvalid; + + uint8_t SingFlag; //һж 1Ϊһ 2Ϊǵһ + uint8_t SingCnt = 0; + uint8_t i; + + if( (DevInputLoop > 0x00) || (0x00000000 == CfgDevAddIn)) //ֻҪ· + { + return 0; //ͷ + } + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),CfgDevAddIn); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485Tem,sizeof(RS485_TEMP_INFO),CfgDevAddIn+Dev_Privately); + + Rs485Tem.TemCondCfg.IndoorFlag = DevInputType & 0x0001; + Rs485Tem.TemCondCfg.SetTFlag = (DevInputType >> 1) & 0x0001; + Rs485Tem.TemCondCfg.ValveFlag = (DevInputType >> 2) & 0x0001; + Rs485Tem.TemCondCfg.FanFlag = (DevInputType >> 3) & 0x0001; + Rs485Tem.TemCondCfg.ModeFlag = (DevInputType >> 4) & 0x0001; + Rs485Tem.TemCondCfg.OnOffFlag = (DevInputType >> 5) & 0x0001; + Rs485Tem.TemCondCfg.IndoorState = (DevInputType >> 6) & 0x0001; + Rs485Tem.TemCondCfg.SetTState = (DevInputType >> 7) & 0x0001; + Rs485Tem.TemCondCfg.HValveFlag = (DevInputType >> 8) & 0x0001; + Rs485Tem.TemCondCfg.HValveState = (DevInputType >> 9) & 0x0001; + Rs485Tem.TemCondCfg.ValveState = (DevInputType >> 10) & 0x0001; + Rs485Tem.TemCondCfg.FanState = (DevInputType >> 11) & 0x0003; + Rs485Tem.TemCondCfg.ModeState = (DevInputType >> 13) & 0x0003; + Rs485Tem.TemCondCfg.OnOffState = (DevInputType >> 15) & 0x0001; + + for(i = 0; i < 9; i++) + { + if( (i!=6) && (i!=7) ) + { + if(DevInputType&(0x01<>14)&0x0003; //ȡλ + TempMode = (DevOutputType>>12)&0x0003; //ȡλ + TempFan = (DevOutputType>>10)&0x0003; //ȡλ +// TempValve = (DevOutputType>>8)&0x0003; //ȡλ + TempSet = (DevOutputType)&0x00ff; //¶(0x00 == TempOnOff) || + + if(((DevOutputType&0xC000)&&(0x00 == (DevOutputType&0x3CFF))) || + ((DevOutputType&0x3000)&&(0x00 == (DevOutputType&0xCCFF))) || + ((DevOutputType&0x0C00)&&(0x00 == (DevOutputType&0xF0FF))) || +// ((DevOutputType&0x0300)&&(0x00 == (DevOutputType&0xFCFF))) || + ((DevOutputType&0x00FF)&&(0x00 == (DevOutputType&0xFC00)))) //ػΪ0Ϊ0ģʽΪ0Ϊ0ٲΪ0Ϊ0¶ȲΪ0Ϊ0 Ų + { + SingleCtrlFlag = 0x01; //Ϊ1ΪأΪ0ͲҪֵ + } + + if(0x00 == SingleCtrlFlag) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ȫ %d %d %d %d",TempOnOff,TempMode,TempFan,TempSet); + } + else + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ %d %d %d %d",TempOnOff,TempMode,TempFan,TempSet); + } + + if((0x00 == TempOnOff) && (0x00 == TempMode) && (0x00 == TempFan) && (0x00 == TempSet)) //ԭ + { + if(0x00 != Dev_Temp_State_Data(Rs485Tem.TemKeepState)) //б״̬ + { + //״̬Կ״̬иֵ + Dev_Temp_State_Sync(&Rs485TemLoc,&Rs485Tem.TemKeepState); + } + } + else if(0x03 == TempOnOff) // + { + Rs485Tem.TemKeepState = Rs485Tem.TemState; + } + else if((0x00 == TempOnOff) && (0x00 != TempMode) && (0x00 != TempFan) && (0x00 == TempSet)) //¿߼ 2024-03-12 + { + switch(TempMode) + { + case 0x01: //忨״̬ͬ + switch(TempFan) + { + case 0x01: + Rs485Tem.CardEn = 0x01; + break; + case 0x02: + Rs485Tem.CardEn = 0x00; + break; + default: + break; + } + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿忨ͬ%d",Rs485Tem.CardEn); + Rs485Tem.CardFlag = 0x01; + Rs485Tem.CardCnt = 0x03; + break; + case 0x02: //ģʽʾ +// switch(TempFan) +// { +// case 0x01: +// PlayList.EnFlag = 0x01; +// break; +// case 0x02: +// PlayList.EnFlag = 0x00; +// break; +// default: +// break; +// } +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ģʽʾ%d",PlayList.EnFlag); + break; + default: + break; + } + KeepFlag = 0x01; + } + else //ȫת Rs485Tem->TemStateCtrl ֵ + { + switch(TempOnOff) + { + case 0x01:Rs485TemLoc.on_off = TEMP_STATE_ON;Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿");break;// + case 0x02: Rs485TemLoc.on_off = TEMP_STATE_OFF;Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ػ");break; //ػ + } + + switch(TempMode) //ģʽ + { + case 1: // + case 2: // + case 3: //ͷ + Rs485TemLoc.mode = TempMode; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ģʽ:%d", TempMode); + break; + case 0: // + if((0x00 == SingleCtrlFlag) && ((0x01 == TempOnOff)||(0x02 == TempOnOff))) //ȫ ҿػЧ + { + uint32_t Season; + + SRAM_DMA_Read_Buff((uint8_t *)&Season,4,SRAM_Register_Start_ADDRESS + Register_SeasonStatus_OFFSET); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ڴӡ:%08X ǰ·:%x", Season, RTC_Raw_Data.month); + + switch((Season>>(HEX_Conversion_To_DEC(RTC_Raw_Data.month)-1)*2)&0x03) //ǰ·ݵļ + { + case Season_Summer: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰļ"); + Rs485TemLoc.mode = TEMP_COLD; + Rs485TemLoc.fan = TEMP_MID; + Rs485TemLoc.set_t = 24; + break; // + case Season_Winter: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰڶ"); + Rs485TemLoc.mode = TEMP_HOT; + Rs485TemLoc.fan = TEMP_MID; + Rs485TemLoc.set_t = 26; + break; // + case Season_Spring: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰڴ"); + Rs485TemLoc.mode = TEMP_WIND; + Rs485TemLoc.fan = TEMP_MID; + Rs485TemLoc.set_t = 25; + break; // + case Season_Autumn: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰ＾"); + Rs485TemLoc.mode = TEMP_WIND; + Rs485TemLoc.fan = TEMP_LOW; + Rs485TemLoc.set_t = 25; + break; + } + } + break; + } + + switch(TempFan) + { + case TEMP_FANAUTO: //Զ + if(0x00 == SingleCtrlFlag) //ȫ + { + Rs485TemLoc.fan = TEMP_FANAUTO; + } + break; + default: + Rs485TemLoc.fan = TempFan; //ȫֵ + break; + } + + switch(TempSet) //¶ȵ ߷Ӽ ¶Ӽ + { + case TEM_DecTem: //¶ + if(Rs485TemLoc.set_t == 0) //32 + { + Rs485TemLoc.set_t = 31; + }else if(Rs485TemLoc.set_t > 16) + { + Rs485TemLoc.set_t = Rs485Tem.TemState.set_t - 1; + }else{ + //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰ¶ѴСֵ"); + } + + break; + case TEM_AddTem: //¶ + if(Rs485TemLoc.set_t == 0) //32 + { + //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǰ¶Ѵֵ"); + }else if(Rs485TemLoc.set_t < 32) + { + Rs485TemLoc.set_t = Rs485Tem.TemState.set_t + 1; + if(Rs485TemLoc.set_t >= 32) + { + Rs485TemLoc.set_t = 0x00; + } + } + + break; + case TEM_DecFan: // + switch(Rs485Tem.TemState.fan) + { + case TEMP_HIGH:Rs485TemLoc.fan = TEMP_MID;break; + case TEMP_MID:Rs485TemLoc.fan = TEMP_LOW;break; + } + break; + case TEM_AddFan: //ӷ + switch(Rs485Tem.TemState.fan) + { + case TEMP_MID:Rs485TemLoc.fan = TEMP_HIGH;break; + case TEMP_LOW:Rs485TemLoc.fan = TEMP_MID;break; + } + break; + case 0x20: //Ψ32 ŸֵΪ0 + Rs485TemLoc.set_t = 0x00; + break; + case 0x00: //ֵ ԭ¶ + break; + default: + Rs485TemLoc.set_t = TempSet; //¶ȫֵ ֵ0, 16~31 + break; + } + } + } +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ƺ״̬:%4x", TEMSTATECONVER(Rs485TemLoc)); + + if(0x01 == TemCtrlFlag) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿״̬:%4x - %4x", Dev_Temp_State_Data(Rs485Tem.TemStateCtrl),Dev_Temp_State_Data(Rs485TemLoc)); + + if(Rs485Tem.Carbon_Set_Temp != Rs485TemLoc.set_t){ + Rs485Tem.Carbon_Set_Temp = Rs485TemLoc.set_t; + KeepFlag = 0x01; + } + + if(Dev_Temp_State_Data(Rs485Tem.TemStateCtrl) != Dev_Temp_State_Data(Rs485TemLoc) ) + { + KeepFlag = 0x01; + + Dev_Temp_State_Sync(&Rs485Tem.TemStateCtrl,&Rs485TemLoc); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"TemStateCtrl: %04X", Dev_Temp_State_Data(Rs485Tem.TemStateCtrl)); + } + } + + if(0x01 == KeepFlag) + { + BUS_PublicOut.check = 0x00; + BUS_PublicOut.check = DoubleData_CheckSum((uint8_t *)&BUS_PublicOut, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485Tem, sizeof(RS485_TEMP_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_PublicOut, sizeof(Device_Public_Information_G),CfgDevAddOut);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485Tem,sizeof(RS485_TEMP_INFO),CfgDevAddOut+Dev_Privately); + } +} + +/******************************************************************************* +* Function Name : Get_BLV485_TEMP_Online_Status +* Description : ȡ豸״̬ +* Input : +* devaddr - 豸ַ +* Return : 豸״̬ +* 0x01:豸 +* 0x00:豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_BLV485_TEMP_Online_Status(uint32_t devaddr) +{ + RS485_TEMP_INFO Rs485TempT1; + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),devaddr+Dev_Privately); + + if(Rs485TempT1.DevOffline == DEV_IS_ONLINE) + { + return 0x01; + } + return 0x02; +} + +/******************************************************************************* +* Function Name : Get_BLV485_TEMP_Status +* Description : ȡ¿豸״̬ +* Input : +* devaddr - 豸ַ +* loop - 豸· +* Return : 豸״̬ - +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t Get_BLV485_TEMP_Status(uint32_t devaddr,uint16_t loop) +{ + RS485_TEMP_INFO Rs485TempT1; + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),devaddr+Dev_Privately); + + return Dev_Temp_State_Data(Rs485TempT1.TemState); +} + +/******************************************************************************* +* Function Name : TemSingleJudge +* Description : յ豸ر־ж +* Input : +* CfgDevAdd - յ豸ڵ +* Rs485TemCtrl - յƺ +* Rs485TemCycle - յѯ +* Return : +* 0x01 - Ҫȴظ +* 0x00 - Ҫȴظ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t TemSingleJudge(uint32_t CfgDevAdd, RS485_Tem_Ctrl_ptr Rs485TemCtrl, RS485_Tem_CycleCtrl_ptr Rs485TemCycle) +{ + uint8_t Ret = RS485OCCUPYNOTIME; + + uint8_t keepflag = 0x00; + + Device_Public_Information_G BUS_Public; + RS485_TEMP_INFO Rs485TempT1; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),CfgDevAdd); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),CfgDevAdd+Dev_Privately);/*豸˽Ϣ*/ + + if(Rs485TempT1.TemStateCtrlLast.on_off != Rs485TempT1.TemStateCtrl.on_off) //ػ + { + Rs485TempT1.TemStateCtrlLast.on_off = Rs485TempT1.TemStateCtrl.on_off; + Rs485TempT1.TemStateCtrlFlag.TemOnOffCtrlVar = 0x01; + Rs485TempT1.TemStateCtrlCnt.TemOnOffCtrlVar = REPEATSENDTIMEMAX; + } + if(Rs485TempT1.TemStateCtrlLast.mode != Rs485TempT1.TemStateCtrl.mode) //ģʽ + { + Rs485TempT1.TemStateCtrlLast.mode = Rs485TempT1.TemStateCtrl.mode; + Rs485TempT1.TemStateCtrlFlag.TemModeCtrlVar = 0x01; + Rs485TempT1.TemStateCtrlCnt.TemModeCtrlVar = REPEATSENDTIMEMAX; + } + if(Rs485TempT1.TemStateCtrlLast.set_t != Rs485TempT1.TemStateCtrl.set_t) //¶ + { + Rs485TempT1.TemStateCtrlLast.set_t = Rs485TempT1.TemStateCtrl.set_t; + Rs485TempT1.TemStateCtrlFlag.TemSetTCtrlVar = 0x01; + Rs485TempT1.TemStateCtrlCnt.TemSetTCtrlVar = REPEATSENDTIMEMAX; + } + if(Rs485TempT1.TemStateCtrlLast.fan != Rs485TempT1.TemStateCtrl.fan) // + { + Rs485TempT1.TemStateCtrlLast.fan = Rs485TempT1.TemStateCtrl.fan; + Rs485TempT1.TemStateCtrlFlag.TemFanCtrlVar = 0x01; + Rs485TempT1.TemStateCtrlCnt.TemFanCtrlVar = REPEATSENDTIMEMAX; + } + + if(Rs485TempT1.DevPort != Rs485TempT1.DevPort_Last) + { + Rs485TempT1.DevPort_Last = Rs485TempT1.DevPort; + Rs485TempT1.DevPort_Flag = 0x01; + } + + if(0x01 == Rs485TempT1.TemStateCtrlFlag.TemOnOffCtrlVar) //ػ + { + if(0x00 != Rs485TempT1.TemStateCtrlCnt.TemOnOffCtrlVar) + { + Rs485TempT1.TemStateCtrlCnt.TemOnOffCtrlVar--; + }else{ + Rs485TempT1.TemStateCtrlFlag.TemOnOffCtrlVar = 0x00; + } + Rs485TemCtrl(&BUS_Public,&Rs485TempT1, 0x00); //ػ + Ret = RS485OCCUPYTIME; //Ϳ + } + else if(0x01 == Rs485TempT1.TemStateCtrlFlag.TemModeCtrlVar) //ģʽ + { + if(0x00 != Rs485TempT1.TemStateCtrlCnt.TemModeCtrlVar) + { + Rs485TempT1.TemStateCtrlCnt.TemModeCtrlVar--; + }else{ + Rs485TempT1.TemStateCtrlFlag.TemModeCtrlVar = 0x00; + } + Rs485TemCtrl(&BUS_Public, &Rs485TempT1, 0x01); //ģʽ + Ret = RS485OCCUPYTIME; //Ϳ + } + else if(0x01 == Rs485TempT1.TemStateCtrlFlag.TemSetTCtrlVar) //¶ + { + if(0x00 != Rs485TempT1.TemStateCtrlCnt.TemSetTCtrlVar) + { + Rs485TempT1.TemStateCtrlCnt.TemSetTCtrlVar--; + }else{ + Rs485TempT1.TemStateCtrlFlag.TemSetTCtrlVar = 0x00; + } + Rs485TemCtrl(&BUS_Public, &Rs485TempT1, 0x02); //¶ + Ret = RS485OCCUPYTIME; //Ϳ + } + else if(0x01 == Rs485TempT1.TemStateCtrlFlag.TemFanCtrlVar) // + { + if(0x00 != Rs485TempT1.TemStateCtrlCnt.TemFanCtrlVar) + { + Rs485TempT1.TemStateCtrlCnt.TemFanCtrlVar--; + }else{ + Rs485TempT1.TemStateCtrlFlag.TemFanCtrlVar = 0x00; + } + Rs485TemCtrl(&BUS_Public, &Rs485TempT1, 0x03); // + Ret = RS485OCCUPYTIME; //Ϳ + } + else if(Rs485TempT1.CardFlag == 0x01) + { + if(0x00 != Rs485TempT1.CardCnt) + { + BLWOut_tempT1CardCtrl(&BUS_Public, &Rs485TempT1); + Rs485TempT1.CardCnt--; + Ret = RS485OCCUPYTIME; //Ϳ + }else{ + Rs485TempT1.CardFlag = 0x00; + Rs485TempT1.CardCnt = 0x03; + keepflag = 0x01; + } + } + else if(Rs485TempT1.DevPort_Flag == 0x01) + { + BLV_T1Temp_PortSet_Send(&BUS_Public,&Rs485TempT1); + Ret = RS485OCCUPYTIME; + }else{ + if(BUS_Public.port == Polling_Port) //2024-11-05 + { + if(NULL != Rs485TemCycle) + { + Rs485TemCycle(&BUS_Public); + Ret = RS485OCCUPYTIME;// ѯ + } + } + } + + if((RS485OCCUPYTIME == Ret) || (keepflag == 0x01)) + { + /*ͨѶͳ*/ + BLV_Communication_Record(&Rs485TempT1.comm_record,0x01,0x00); + Rs485TempT1.inquire_tick = SysTick_1ms; + + if(Rs485TempT1.DevSendCnt > REPEATSENDTIMEMAX) + { + if(Rs485TempT1.DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485TempT1%d DEV_IS_OFFLINE",BUS_Public.addr); + LOG_Device_Online_Record(DEV_RS485_TEMP,BUS_Public.addr,LogInfo_Device_Offline); //¼豸SRAM_Read_Byte(CfgDevAdd+Dev_Addr) + } + Rs485TempT1.DevOffline = DEV_IS_OFFLINE; //Ϊ + if(Rs485TempT1.DevOffline != Rs485TempT1.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485TempT1.DevOfflineLast = Rs485TempT1.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + Rs485TempT1.DevPort_Flag = 0x00; + } + else + { + Rs485TempT1.DevSendCnt++; //ʹۼ + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485TempT1, sizeof(RS485_TEMP_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),CfgDevAdd);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),CfgDevAdd+Dev_Privately); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : TemGlobalJudge +* Description : յ豸ȫر־ж +* Input : +* CfgDevAdd - յ豸ڵ +* Rs485TemCtrl - յƺ +* Rs485TemCycle - յѯ +* Return : +* 0x01 - Ҫȴظ +* 0x00 - Ҫȴظ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t TemGlobalJudge(uint32_t CfgDevAdd, RS485_Tem_Ctrl_ptr Rs485TemCtrl, RS485_Tem_CycleCtrl_ptr Rs485TemCycle) +{ + uint8_t Ret = RS485OCCUPYNOTIME,Keep_flag = 0; + + Device_Public_Information_G BUS_Public; + RS485_TEMP_INFO Rs485Tem; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),CfgDevAdd); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485Tem,sizeof(RS485_TEMP_INFO),CfgDevAdd+Dev_Privately);/*豸˽Ϣ*/ + + if(Dev_Temp_State_Data(Rs485Tem.TemStateCtrlLast) != Dev_Temp_State_Data(Rs485Tem.TemStateCtrl)) //״̬ı + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s",__func__); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485Temp %d CtrlFlag Set %04x - ", BUS_Public.addr, Dev_Temp_State_Data(Rs485Tem.TemStateCtrl),Dev_Temp_State_Data(Rs485Tem.TemStateCtrlLast)); + + //C7T ֻһͱ־λ + + Rs485Tem.TemStateCtrlFlag.TemOnOffCtrlVar = 0x01; + Rs485Tem.TemStateCtrlCnt.TemOnOffCtrlVar = REPEATSENDTIMEMAX; + + Dev_Temp_State_Sync(&Rs485Tem.TemStateCtrlLast,&Rs485Tem.TemStateCtrl); + + Keep_flag = 0x01; + } + + + if(0x01 == Rs485Tem.TemStateCtrlFlag.TemOnOffCtrlVar) + { + if(0x00 != Rs485Tem.TemStateCtrlCnt.TemOnOffCtrlVar) + { + Rs485Tem.TemStateCtrlCnt.TemOnOffCtrlVar--; + }else{ + Rs485Tem.TemStateCtrlCnt.TemOnOffCtrlVar = 0x00; + } + if(NULL != Rs485TemCtrl) + { + Rs485TemCtrl(&BUS_Public, &Rs485Tem, 0x00); //Ϳ + Ret = RS485OCCUPYTIME; + } + + Keep_flag = 0x01; + } + else + { + if(NULL != Rs485TemCycle) + { + Rs485TemCycle(&BUS_Public); + Ret = RS485OCCUPYTIME;// ѯ + + Keep_flag = 0x01; + } + } + + if( Keep_flag == 0x01 ) + { + /*ͨѶͳ*/ + BLV_Communication_Record(&Rs485Tem.comm_record,0x01,0x00); + Rs485Tem.inquire_tick = SysTick_1ms; + + if(Rs485Tem.DevSendCnt > REPEATSENDTIMEMAX) + { + if(Rs485Tem.DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485TempT1 %d DEV_IS_OFFLINE", BUS_Public.addr); + LOG_Device_Online_Record(DEV_RS485_TEMP,BUS_Public.addr,LogInfo_Device_Offline); //¼豸SRAM_Read_Byte(CfgDevAdd+Dev_Addr) + } + Rs485Tem.DevOffline = DEV_IS_OFFLINE; //Ϊ + if(Rs485Tem.DevOffline != Rs485Tem.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485Tem.DevOfflineLast = Rs485Tem.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + }else{ + Rs485Tem.DevSendCnt++; //ʹۼ + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485Tem, sizeof(RS485_TEMP_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),CfgDevAdd);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485Tem,sizeof(RS485_TEMP_INFO),CfgDevAdd+Dev_Privately); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : Temp_FanAuto_Set +* Description : յԶٶֵ ԶٵתɵиߵĶ +* Input : +* Rs485TemRecBuf - յ״̬ +* Rs485Tem - յ豸Ϣ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Temp_FanAuto_Set(RS485_TEMP_BASIC *Rs485TemRecBuf, RS485_TEMP_INFO *Rs485Tem) +{ + static uint8_t last_auto_fan = TEMP_LOW; //Ĭϵǵ + uint8_t indoor_temp = 0, set_temp = 0; //¶ȣ¶ת + + if((Rs485TemRecBuf->TemState.indoor_t > 0 && Rs485TemRecBuf->TemState.indoor_t < 16) || + (Rs485TemRecBuf->TemState.set_t > 0 && Rs485TemRecBuf->TemState.set_t < 16)) + { + return; + } + + if(Rs485TemRecBuf->TemState.indoor_t == 0) { + indoor_temp = 32; + }else { + indoor_temp = Rs485TemRecBuf->TemState.indoor_t; + } + + if(Rs485TemRecBuf->TemState.set_t == 0) { + set_temp = 32; + }else { + set_temp = Rs485TemRecBuf->TemState.set_t; + } + + if(0x00 == Rs485TemRecBuf->FanAutoRelay) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," Զ٣Ϊ0"); + + if(TEMP_COLD == Rs485TemRecBuf->TemState.mode) // + { + if(indoor_temp <= (set_temp - 3)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ֹͣٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = 0x00; //ֹͣ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(indoor_temp == (set_temp - 1)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ͷٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_LOW; //ͷ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(indoor_temp == (set_temp + 1)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," зٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_MID; //з + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(indoor_temp >= (set_temp + 3)) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ߷ٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_HIGH; //߷ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(indoor_temp == set_temp) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = last_auto_fan; //߷ + } + } + else if(TEMP_HOT == Rs485TemRecBuf->TemState.mode) // + { + if(set_temp <= (indoor_temp - 3)) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = 0x00; //ֹͣ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(set_temp == (indoor_temp - 1)) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_LOW; //ͷ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(set_temp == (indoor_temp + 1)) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_MID; //з + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(set_temp >= (indoor_temp + 3)) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_HIGH; //߷ + last_auto_fan = Rs485Tem->TemCondRec.FanState; + } + else if(set_temp == indoor_temp) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = last_auto_fan; //߷ + } + } + }else if(0x00 != Rs485TemRecBuf->FanAutoRelay) //0 ͰԶ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," Զ٣ٷ0"); + + switch(Rs485TemRecBuf->FanAutoRelay) + { + case 0x00: //ֹͣ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ֹͣٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = 0x00; //ֹͣ + break; + case 0x01: //ͷ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ͷٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_LOW; //ͷ + break; + case 0x02: //з + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," зٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_MID; //з + break; + case 0x04: //߷ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit," ߷ٶλ"); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = TEMP_HIGH; //߷ + break; + } + } +} + +/******************************************************************************* +* Function Name : Temp_Action_Set +* Description : յõ ¿Բ6 ÿԶ Ҳһ +* Input : +* Rs485TemRecBuf - 485յ¿ +* Rs485Tem - 485¿豸Ϣ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Temp_Action_Set(RS485_TEMP_BASIC *Rs485TemRecBuf, RS485_TEMP_INFO *Rs485Tem) +{ + if(Rs485Tem->TemState.on_off != Rs485TemRecBuf->TemState.on_off) + { + Rs485Tem->TemState.on_off = Rs485TemRecBuf->TemState.on_off; //ػͬ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ػǰ״̬: %d",Rs485TemRecBuf->TemState.on_off); + Rs485Tem->TemCondRec.OnOffFlag = 0x01; // + Rs485Tem->TemCondRec.OnOffState = Rs485TemRecBuf->TemState.on_off; + if(TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = Rs485TemRecBuf->TemState.fan; + + if(Rs485Tem->ValveSameFlag == 0x01) //˫ + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; //Ŷ + } + else if(Rs485Tem->ValveSameFlag == 0x02) //Ĺ + { + if(Rs485TemRecBuf->TemState.mode==0x01) + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; //䷧Ŷ + Rs485Tem->TemCondRec.HValveFlag = 0x00; + } + else if(Rs485TemRecBuf->TemState.mode==0x02) + { + Rs485Tem->TemCondRec.ValveFlag = 0x00; //ȷŶ + Rs485Tem->TemCondRec.HValveFlag = 0x01; + } + else if(Rs485TemRecBuf->TemState.mode==0x03) + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; + Rs485Tem->TemCondRec.HValveFlag = 0x01; + } + } + Rs485Tem->TemCondRec.ValveState = Rs485TemRecBuf->TemState.valve; + if(TEMP_FANAUTO == Rs485TemRecBuf->TemState.fan) //Զ + { + Temp_FanAuto_Set(Rs485TemRecBuf, Rs485Tem); //תɵиͣĶ + } + Rs485Tem->TemCondRec.ModeFlag = 0x01; //ģʽ + Rs485Tem->TemCondRec.ModeState = Rs485TemRecBuf->TemState.mode; + } + } + if(Rs485Tem->TemState.mode != Rs485TemRecBuf->TemState.mode) + { + Rs485Tem->TemState.mode = Rs485TemRecBuf->TemState.mode; //ģʽͬ + if(TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ģʽǰ״̬: %d",Rs485TemRecBuf->TemState.mode); + Rs485Tem->TemCondRec.ModeFlag = 0x01; //ģʽ + Rs485Tem->TemCondRec.ModeState = Rs485TemRecBuf->TemState.mode; + + if(TEMP_FANAUTO == Rs485TemRecBuf->TemState.fan) //Զ + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = Rs485TemRecBuf->TemState.fan; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ģʽлԶתΪиٶ"); + Temp_FanAuto_Set(Rs485TemRecBuf, Rs485Tem);//תɵиͣĶ + } +// if(Rs485Tem->inif_flag != 0x00) +// { +// if(Rs485TemRecBuf->TemState.mode == 0x01) // +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʾ"); +// AddPrompt_ToList(0x00); +// } +// else if(Rs485TemRecBuf->TemState.mode == 0x02) // +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʾ"); +// AddPrompt_ToList(0x01); +// } +// else if(Rs485TemRecBuf->TemState.mode == 0x03) //ͷ +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ͷʾ"); +// AddPrompt_ToList(0x02); +// } +// }else { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"һ յʾ Ӧ"); +// } + } + } + if(Rs485Tem->TemState.fan != Rs485TemRecBuf->TemState.fan) + { + Rs485Tem->TemState.fan = Rs485TemRecBuf->TemState.fan; //ͬ + if((TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off)&&(TEMP_FANAUTO != Rs485TemRecBuf->TemState.fan)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ٶǰ״̬: %d",Rs485TemRecBuf->TemState.fan); + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = Rs485TemRecBuf->TemState.fan; + +// if(Rs485Tem->inif_flag != 0x00) +// { +// if(Rs485TemRecBuf->TemState.fan == 0x01) // +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ӵʾ"); +// AddPrompt_ToList(0x03); +// } +// else if(Rs485TemRecBuf->TemState.fan == 0x02) // +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʾ"); +// AddPrompt_ToList(0x04); +// } +// else if(Rs485TemRecBuf->TemState.fan == 0x03) // +// { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ӹʾ"); +// AddPrompt_ToList(0x05); +// } +// }else { +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"һ յʾ Ӧ"); +// } + } + } + if((Rs485Tem->FanAutoRelay != Rs485TemRecBuf->FanAutoRelay)||(Rs485Tem->TemState.set_t != Rs485TemRecBuf->TemState.set_t) + ||(Rs485Tem->TemState.indoor_t != Rs485TemRecBuf->TemState.indoor_t)) //Զٱ ¶ȣ¶ȱ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Զٱ仯¶ȱ仯 : %d",Rs485TemRecBuf->FanAutoRelay); + Rs485Tem->FanAutoRelay = Rs485TemRecBuf->FanAutoRelay; + if((TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) && (TEMP_FANAUTO == Rs485TemRecBuf->TemState.fan)) //Զ ¸ֵ + { + Temp_FanAuto_Set(Rs485TemRecBuf, Rs485Tem);//תɵиͣĶ + } + } + + if(Rs485Tem->TemState.valve != Rs485TemRecBuf->TemState.valve) + { + Rs485Tem->TemState.valve = Rs485TemRecBuf->TemState.valve; //ͬ + if(TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ŷǰ״̬: %d",Rs485TemRecBuf->TemState.valve); + if(Rs485Tem->ValveSameFlag == 0x01) //˫ + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; //Ŷ + Rs485Tem->TemCondRec.ValveState = Rs485TemRecBuf->TemState.valve; + } + else if(Rs485Tem->ValveSameFlag == 0x02) //Ĺ + { + if(Rs485TemRecBuf->TemState.mode==0x01) + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; //Ŷ + Rs485Tem->TemCondRec.HValveFlag = 0x00; //Ŷ + Rs485Tem->TemCondRec.ValveState = Rs485TemRecBuf->TemState.valve; + } + else if(Rs485TemRecBuf->TemState.mode==0x02) + { + Rs485Tem->TemCondRec.ValveFlag = 0x00; //Ŷ + Rs485Tem->TemCondRec.HValveFlag = 0x01; //Ŷ + Rs485Tem->TemCondRec.HValveState = Rs485TemRecBuf->TemState.valve; + } + else if(Rs485TemRecBuf->TemState.mode==0x03) + { + Rs485Tem->TemCondRec.ValveFlag = 0x01; //Ŷ + Rs485Tem->TemCondRec.HValveFlag = 0x01; //Ŷ + Rs485Tem->TemCondRec.ValveState = Rs485TemRecBuf->TemState.valve; + Rs485Tem->TemCondRec.HValveState = Rs485TemRecBuf->TemState.valve; + } + } + } + } + + //޷ʱ󶨷ٶ + if(Rs485Tem->ValveNoExist == 0x01) + { + if((Rs485Tem->TemCondRec.ValveFlag == 0x01) || (Rs485Tem->TemCondRec.HValveFlag == 0x01)) + { + if(Rs485Tem->TemState.on_off == TEMP_STATE_ON) + { + if(Rs485Tem->TemState.valve == 0x01) + { + if(TEMP_FANAUTO != Rs485TemRecBuf->TemState.fan) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = Rs485TemRecBuf->TemState.fan; + }else{ + Temp_FanAuto_Set(Rs485TemRecBuf, Rs485Tem); //תɵиͣĶ + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޷: %d",Rs485Tem->TemCondRec.FanState); + }else{ + if(TEMP_FANAUTO != Rs485TemRecBuf->TemState.fan) + { + Rs485Tem->TemCondRec.FanFlag = 0x01; //ٶ + Rs485Tem->TemCondRec.FanState = 0x00; //ֹͣ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޷ͣ"); + }else{ + Temp_FanAuto_Set(Rs485TemRecBuf, Rs485Tem); //תɵиͣĶ + } + } + } + } + } + + if(Rs485Tem->TemState.set_t != Rs485TemRecBuf->TemState.set_t) + { + Rs485Tem->TemState.set_t = Rs485TemRecBuf->TemState.set_t; //¶ͬ + if(TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) + { + Rs485Tem->TemCondRec.SetTFlag = 0x01; //¶ȶ + + if(Rs485Tem->TemState.set_t < Rs485TemRecBuf->TemState.set_t) + { + Rs485Tem->TemCondRec.SetTState = 0x00; //¶ + }else{ + Rs485Tem->TemCondRec.SetTState = 0x01; //¶Ƚ + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"¶ȶǰ״̬: %d",Rs485Tem->TemCondRec.SetTState); + + } + } + if(Rs485Tem->TemState.indoor_t != Rs485TemRecBuf->TemState.indoor_t) + { + Rs485Tem->TemState.indoor_t = Rs485TemRecBuf->TemState.indoor_t; //¶ͬ + Rs485Tem->TemCondRec.IndoorFlag = 0x01; //¶ȶ + if(TEMP_STATE_ON == Rs485TemRecBuf->TemState.on_off) + { + if(Rs485Tem->TemState.indoor_t < Rs485TemRecBuf->TemState.indoor_t) + { + Rs485Tem->TemCondRec.IndoorState = 0x00; //¶ + }else{ + Rs485Tem->TemCondRec.IndoorState = 0x01; //¶Ƚ + } + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"¶ȶǰ״̬: %d",Rs485Tem->TemCondRec.IndoorState); + } + + if(Rs485Tem->inif_flag == 0x00) + { + Rs485Tem->inif_flag = 0x01; + } + + Rs485Tem->Carbon_Set_Temp = Rs485Tem->TemState.set_t; +} + + + + + + diff --git a/BLV_485_Driver/blv_rs485_dev_touchswitch.c b/BLV_485_Driver/blv_rs485_dev_touchswitch.c new file mode 100644 index 0000000..c2ebcc6 --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_touchswitch.c @@ -0,0 +1,401 @@ +/* + * blv_rs485_dev_touchswitch.c + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#include "blv_rs485_dev_switchctrl.h" // +#include "blv_rs485_dev_touchswitch.h" +#include "blv_nor_dev_hvoutfun.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" + +#include + +#include "blv_netcomm_function.h" + +#define RS485_TOUCH_INPUT_QUERY(data,x) (((data&(0x03<<((x%4)*2)))>>(x%4)*2)) //ÿжλ + +#define REPEATSENDTIMEMAX 0x03 //豸ط +#define BLWTOUCHCTRLTIMEOUT 100 //豸Ƴʱʱ +#define BLWTOUCHASKTIMEOUT 10 //豸ƻظʱʱ +#define BLW_TOUCH_LOOPIN_NUM 26 //豸RS485· 6 +#define BLW_TOUCH_LOOPOUT_NUM 26 //豸· 7 +#define BLW_SWT_ASK_LEN_M 12 //(((BLW_TOUCH_LOOPOUT_NUM+7)/4)+3) +#define BLW_SWT_BUF_LEN 0x05 //鳤Ϊ5 16 +#define BLW_SWT_BUF_LEN_M 8 //(((BLW_TOUCH_LOOPOUT_NUM+7)/8)+3) + +#define Dev_TouchSwitch_RecvData_Len_Max 0x18 + +/******************************************************************************* +* Function Name : BlwTouchSwtRecAsk +* Description : 485豸 - T1ļ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_485_Dev_Touch_Switch_Init(Device_Public_Information_G *BUS_Public, RS485_SWI_INFO *Rs485SwiInfo) +{ + BUS_Public->polling_cf = (uint32_t)&BLW_Touch_SwitchCycleDis; + BUS_Public->processing_cf = (uint32_t)&BLW_Rs485_Touch_Swi_Check; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"485T1 ַ: %d",BUS_Public->addr); +} + +/******************************************************************************* +* Function Name : BlwTouchSwtRecAsk +* Description : ȷյظ +* Input : + DevAdd : ӵ豸 + data : ӵ豸ַ + DataLen 豸ѯݷͻص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BlwRelaySwtRecAsk(uint8_t *data) +{ + uint8_t SendBuf[5]; + uint32_t device_addr = 0x00; + + device_addr = Find_AllDevice_List_Information2(Active_Port, 0x01, data[0]); + + Device_Public_Information_G BUS_Public; // + NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),device_addr); //й + SRAM_DMA_Read_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),device_addr+Dev_Privately); + + if(DevHVoutInfo.HVSwitchFlag==0x01) + { + SendBuf[0] = data[0]; + SendBuf[1] = 0x04; + SendBuf[2] = data[2]; + SendBuf[3] = data[3]; + SendBuf[4] = SOR_CRC(SendBuf,4); + /*ͺ*/ + MCU485_SendString(0x02,SendBuf,5); +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǿ翪ػظ\r\n"); + } +} + +/******************************************************************************* +* Function Name : BlwTouchSwtRecAsk +* Description : ȷյظ +* Input : + DevAdd : ӵ豸 + data : ӵ豸ַ + DataLen 豸ѯݷͻص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BlwTouchSwtRecAsk(uint32_t DevAdd, uint8_t *data, uint16_t DataLen) +{ + uint8_t SendBuf[BLW_SWT_ASK_LEN_M]; + uint8_t port_id = SRAM_Read_Byte(DevAdd+Dev_port); + + if(DataLen > BLW_SWT_ASK_LEN_M) + { + return ; + } + memcpy(SendBuf, data, DataLen); + + /*ͺ*/ + MCU485_SendString(port_id,SendBuf,DataLen); +} + +/******************************************************************************* +* Function Name : BLW_Touch_Rs485_Swi_Pro +* Description : BLW_Touchж +* Input : + data_addr : ӵ豸 + Switch_Info : ӵ豸ַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLW_Touch_Rs485_Swi_Pro(Device_Public_Information_G* BUS_Public, uint8_t *data, RS485_SWI_INFO *Switch_Info, uint8_t lens) +{ + uint8_t KeyValue = 0x00; + uint8_t i; + uint8_t temp = 0,temp2 = 0; + uint8_t loopnum = 0x00; + + if(Switch_Info->DevOffline == DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Dev_TouchSwitch LogInfo_Device_Online..........."); + LOG_Device_Online_Record(DEV_RS485_SWT,BUS_Public->addr,LogInfo_Device_Online); //¼豸 + DevActionGlobal.OffLineDevType = 0xff; + } + + BLV_Communication_Record(&Switch_Info->comm_record,0x02,0x01); //¼ͨѶɹ + Switch_Info->DevSendCnt = 0x00; //յظ + Switch_Info->DevOffline = DEV_IS_ONLINE; //豸 + if(Switch_Info->DevOffline != Switch_Info->DevOfflineLast) //ǰ״̬һ״̬ + { + Switch_Info->DevOfflineLast = Switch_Info->DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public->type,BUS_Public->addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + + loopnum = (lens - 3) * 4; //ȥַ֡У һֽڱʾ4״̬ + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"T1 switch Input Num:%d",loopnum); + + switch(data[1]) // + { + case 0x03: + for(i = 0; i < loopnum; i++) //6·״ֵ̬ + { + temp = data[i/4+2]; //SRAM_Read_Byte(data_addr + (i/4+2)); + KeyValue = RS485_TOUCH_INPUT_QUERY(temp, i); //±2ʼ + switch(KeyValue&0x03) + { + case 1: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"switch%d Dev%02X KeyPress Coord:%d",BUS_Public->addr, (i + 1), BUS_Public->DevCoord); + Switch_Info->DevReadBuf[i] = KeyPress; //ַ1ʼ + DevActionGlobal.Devi = BUS_Public->DevCoord; //ֱָ±ȥ + temp2++; + + Udp_Addtion_Roomstate(DEV_RS485_SWT,BUS_Public->addr,i,KeyPress); + break; + case 2: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"switch%d Dev%02X KeyRelease Coord:%d",BUS_Public->addr, (i + 1), BUS_Public->DevCoord); + Switch_Info->DevReadBuf[i] = KeyRelease; + DevActionGlobal.Devi = BUS_Public->DevCoord; //ֱָ±ȥ + temp2++; + + Udp_Addtion_Roomstate(DEV_RS485_SWT,BUS_Public->addr,i,KeyRelease); + break; + case 3: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"switch%d Dev%02X KeyHold Coord:%d",BUS_Public->addr, (i + 1), BUS_Public->DevCoord); + Switch_Info->DevReadBuf[i] = KeyHold; + DevActionGlobal.Devi = BUS_Public->DevCoord; //ֱָ±ȥ + temp2++; + + Udp_Addtion_Roomstate(DEV_RS485_SWT,BUS_Public->addr,i,KeyHold); + break; + default: + break; + } + KeyValue = 0; + } + DevActionGlobal.People_Flag = 0x01; + break; + case 0x06: + Switch_Info->SwtRelayLedCtrlFlag = 0x00; + Switch_Info->SwtRelayLedCtrlCnt = REPEATSENDTIMEMAX; + break; + default: + break; + } +} + +#define RECDATALENMAX 10 //󳤶 + +/******************************************************************************* +* Function Name : BLW_Rs485_Touch_Swi_Check +* Description : BLW485մ + +* Return : + 0x01ݴʧ + 0x00ݴɹ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLW_Rs485_Touch_Swi_Check(uint32_t DevAdd ,uint32_t Data_addr, uint16_t DataLen) +{ + uint8_t ret = 0x01; + uint8_t data[RECDATALENMAX]; + Device_Public_Information_G BUS_Public; // + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + if(DataLen > RECDATALENMAX) + { + //Dbg_Print(DBG_BIT_DEVICE_STATUS_bit,"Rs485_TouchݳȳΧ!!\r\n"); + return ret; // + } + + SRAM_DMA_Read_Buff(data,DataLen,Data_addr); //482 + + if((DataLen < 0x05)||((data[1] != 0x03)&&(data[1] != 0x06))||(data[DataLen - 1] != SOR_CRC(data, DataLen-1))) //ƥ俪صַ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ǴصݣDevAdd:%d,len:%d",BUS_Public.addr,DataLen); + return ret; //Ǿֱӷ + } + + if(data[0] == SRAM_Read_Byte(DevAdd+Dev_Addr)) //ַպƥBUS_Public.addr + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"صַƥ DevAdd:%d,len:%d",data[0],DataLen); + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAdd); + } + else //ַûƥ + { + DevAdd = Find_AllDevice_List_Information2(Active_Port, 0x06, data[0]); //ַ¸ֵ + if( (0x00000000 != DevAdd) || (0xFFFFFFFF != DevAdd) ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAdd); + }else{ + return ret; + } + } + + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately); + + if(data[1] == 0x03) + { + BlwRelaySwtRecAsk(data); + } + + if( (data[1] == 0x03) || (data[1] == 0x06) ) + { + ret = 0x00; + BLW_Touch_Rs485_Swi_Pro(&BUS_Public, data, &Rs485SwiInfo,DataLen); + } + + /*־¼*/ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port,BUS_Public.baud,data,DataLen); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAdd);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately); + + return ret; +} + +__attribute__((section(".non_0_wait"))) void BLW_Touch_Switch_ctrl(Device_Public_Information_G *BUS_Public, RS485_SWI_INFO *Rs485SwiInfo) +{ + uint8_t i; + uint8_t SendLen; + //ַ Ĵ + uint8_t BLW_swt_buf[BLW_SWT_BUF_LEN_M]; // = {0x01, 0x06, 0x00, 0x00, 0x00}; //7ֽ + + BLW_swt_buf[0] = BUS_Public->addr;//SRAM_Read_Byte(DevAdd + Dev_Addr); //õصת + BLW_swt_buf[1] = 0x06; //д + BLW_swt_buf[2] = 0x00; //ָʾ + BLW_swt_buf[3] = 0x00; //ָʾ + + for(i = 0; i < Rs485SwiInfo->SwtOutputValidNum; i++) + { + if(0x00 != Rs485SwiInfo->DevSendBuf[i]) //Ϊ0 + { + BLW_swt_buf[2+i/8] |= 0x01<<(i%8); + }else{ + BLW_swt_buf[2+i/8] &= ~(0x01<<(i%8)); + } + } + if(Rs485SwiInfo->SwtOutputValidNum <= 16) + { + SendLen = BLW_SWT_BUF_LEN; + }else{ + SendLen = ((Rs485SwiInfo->SwtOutputValidNum+7)/8)+3; //16·ʵʻ·Ϊ׼ + } + + BLW_swt_buf[SendLen-1] = SOR_CRC(BLW_swt_buf,SendLen-1); + /*ͺ*/ + //Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"switch send data---\r\n"); + MCU485_SendString(BUS_Public->port,BLW_swt_buf,SendLen); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record(BUS_Public->port,BUS_Public->baud,BLW_swt_buf,SendLen); + + if(Rs485SwiInfo->DevSendCnt > REPEATSENDTIMEMAX) + { + if(Rs485SwiInfo->DevOffline != DEV_IS_OFFLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Dev_TouchSwitch LogInfo_Device_Offline....."); + LOG_Device_Online_Record(DEV_RS485_SWT, BUS_Public->addr,LogInfo_Device_Offline); //¼豸 + } + + Rs485SwiInfo->DevOffline = DEV_IS_OFFLINE; //Ϊ + DevActionGlobal.OffLineDevType = BUS_Public->type; //2023-10-08 + DevActionGlobal.OffLineDevAddr = BUS_Public->addr; //2023-10-08 + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"TouchSwitch Offline,type:%d addr:%d",BUS_Public->type,BUS_Public->addr); + if(Rs485SwiInfo->DevOffline != Rs485SwiInfo->DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485SwiInfo->DevOfflineLast = Rs485SwiInfo->DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public->type,BUS_Public->addr,In_ErrFun_LineState,DEV_IS_OFFLINE); //豸״̬SRAM + } + }else{ + Rs485SwiInfo->DevSendCnt++; //ʹۼ + } + +} + +/******************************************************************************* +* Function Name : BLW_Touch_SwitchCycleDis +* Description : BLW485ݷʹط + +* Return : + 0x01Ҫ + 0x00ûҪ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLW_Touch_SwitchCycleDis(uint32_t DevAdd) +{ + Device_Public_Information_G BUS_Public; + RS485_SWI_INFO Rs485SwiInfo; //ؾֲ + + uint8_t i; + uint8_t Ret = RS485OCCUPYNOTIME; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAdd); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately);/*豸˽Ϣ*/ + + if(DevActionGlobal.DevActionU64Cond.EleState==0x01) + { + if( DevActionGlobal.SleepMode_State == 0x01 ) + { + Rs485SwiInfo.DevSendBuf[Rs485SwiInfo.SwtOutputValidNum-1] = 0x00; //˯ģʽر + }else{ + Rs485SwiInfo.DevSendBuf[Rs485SwiInfo.SwtOutputValidNum-1] = 0x01; //忨 + } + } + else if(DevActionGlobal.DevActionU64Cond.EleState==0x02) + { + Rs485SwiInfo.DevSendBuf[Rs485SwiInfo.SwtOutputValidNum-1] = 0x00; //οر + } + else + { + if( DevActionGlobal.SleepMode_State == 0x01 ) + { + Rs485SwiInfo.DevSendBuf[Rs485SwiInfo.SwtOutputValidNum-1] = 0x00; //˯ģʽر + }else{ + Rs485SwiInfo.DevSendBuf[Rs485SwiInfo.SwtOutputValidNum-1] = 0x01; + } + } + + /*ж豸ǷҪ*/ + for(i = 0; i < Rs485SwiInfo.SwtOutputValidNum; i++) + { + if(Rs485SwiInfo.DevSendBuf_last[i] != Rs485SwiInfo.DevSendBuf[i]) + { + Rs485SwiInfo.SwtRelayLedCtrlFlag = 0x01; + memcpy(Rs485SwiInfo.DevSendBuf_last, Rs485SwiInfo.DevSendBuf, Rs485SwiInfo.SwtOutputValidNum); + break; + } + } + + if(0x01 == Rs485SwiInfo.SwtRelayLedCtrlFlag) + { + if(0x00 != Rs485SwiInfo.SwtRelayLedCtrlCnt) + { + Rs485SwiInfo.SwtRelayLedCtrlCnt--; + }else{ + Rs485SwiInfo.SwtRelayLedCtrlCnt = REPEATSENDTIMEMAX; + Rs485SwiInfo.SwtRelayLedCtrlFlag = 0x00; + } + BLW_Touch_Switch_ctrl(&BUS_Public, &Rs485SwiInfo); + Ret = RS485OCCUPYTIME; + + /*ͨѶͳƼ¼*/ + BLV_Communication_Record(&Rs485SwiInfo.comm_record,0x01,0x00); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAdd);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately); + } + + return Ret; +} + + + + + + diff --git a/BLV_485_Driver/blv_rs485_dev_touchtempt1.c b/BLV_485_Driver/blv_rs485_dev_touchtempt1.c new file mode 100644 index 0000000..5759c66 --- /dev/null +++ b/BLV_485_Driver/blv_rs485_dev_touchtempt1.c @@ -0,0 +1,514 @@ +/* + * blv_rs485_dev_touchtempt1.c + * ļ T1 ¿ + * Created on: Nov 14, 2025 + * Author: cc + */ +#include "blv_rs485_dev_touchtempt1.h" +#include "blv_dev_action.h" +#include "blv_device_type.h" +#include "blv_device_option.h" +#include "debug.h" +#include "uart.h" +#include "spi_sram.h" +#include "check_fun.h" +#include "log_api.h" +#include "sram_mem_addr.h" +#include "rtc.h" +#include "ch564.h" + +#include "blv_netcomm_function.h" + +#include + + +uint8_t BLWOut_TempT1CycleCtrl(uint32_t dev_addr); +uint8_t BLWOut_Rs485_TempT1_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len); + +/******************************************************************************* +* Function Name : BLWOut_RS485_TempT1_Data_Init +* Description : 豸 - ѯ豸 +* Input : + type : ӵ豸 + addr : ӵ豸ַ + polling_cf 豸ѯݷͻص + processing_cf 豸ݴص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_RS485_TempT1_Data_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1) +{ + BUS_Public->polling_cf = (uint32_t)&BLWOut_TempT1CycleCtrl; + BUS_Public->processing_cf = (uint32_t)&BLWOut_Rs485_TempT1_Check; + Rs485TempT1->ValveSameFlag = 0x01; //ȷһ 2023-04-17 + Rs485TempT1->DevPort = Polling_Port; //2024-11-05 ѵ˿豸 +} + +/******************************************************************************* +* Function Name : BLWOut_RS485_TempT1D_Data_Init +* Description : 豸 - ѯ豸 +* Input : + type : ӵ豸 + addr : ӵ豸ַ + polling_cf 豸ѯݷͻص + processing_cf 豸ݴص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_RS485_TempT1D_Data_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1) +{ + BUS_Public->polling_cf = (uint32_t)&BLWOut_TempT1CycleCtrl; + BUS_Public->processing_cf = (uint32_t)&BLWOut_Rs485_TempT1_Check; + Rs485TempT1->ValveSameFlag = 0x02; //ȷһ 2023-04-17 + Rs485TempT1->DevPort = Polling_Port; //2024-11-05 ѵ˿豸 +} + + +/******************************************************************************* +* Function Name : BLWOut_RS485_TempT1_Activ_Init +* Description : 豸 - 豸 +* Input : + type : ӵ豸 + addr : ӵ豸ַ + polling_cf 豸ѯݷͻص + processing_cf 豸ݴص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_RS485_TempT1_Activ_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1) +{ + BUS_Public->polling_cf = (uint32_t)&BLWOut_TempT1CycleCtrl; + BUS_Public->processing_cf = (uint32_t)&BLWOut_Rs485_TempT1_Check; + Rs485TempT1->ValveSameFlag = 0x02; //ȷһ 2023-04-17 + Rs485TempT1->DevPort = Active_Port; //2024-11-05 ˿豸 +} + +/******************************************************************************* +* Function Name : BLWOut_TempT1CycleCtrl +* Description : BLWOut¿Ʒͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_TempT1Ctrl(Device_Public_Information_G *BUS_Public,RS485_TEMP_INFO *Rs485Tem,uint8_t CtrlWay) +{ + // ͷ LEN Type Addr + uint8_t CtrlSend[10] = {0x55, 0x55, 0xee, 0x07, 0x03, 0x01, 0x00, 0x00}; + + CtrlSend[5] = BUS_Public->addr; + + switch(CtrlWay) + { + case 0: //ػ + CtrlSend[6] = 0x01; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s:ػ״̬:%d", __func__,Rs485Tem->TemStateCtrl.on_off); + + switch(Rs485Tem->TemStateCtrl.on_off) //ػ + { + case TEMP_STATE_ON: // + CtrlSend[7] = 0x01; + break; + case TEMP_STATE_OFF: //ػ + CtrlSend[7] = 0x00; + break; + } + break; + case 1: //ģʽ + CtrlSend[6] = 0x02; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s:ģʽ״̬:%d",__func__, Rs485Tem->TemStateCtrl.mode); + switch(Rs485Tem->TemStateCtrl.mode) + { + case TEMP_COLD: CtrlSend[7] = 0x01; break; // + case TEMP_HOT: CtrlSend[7] = 0x02; break; // + case TEMP_WIND: CtrlSend[7] = 0x03; break; //ͨ + + } + break; + case 3: // + CtrlSend[6] = 0x04; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s:״̬:%d", __func__,Rs485Tem->TemStateCtrl.fan); + switch(Rs485Tem->TemStateCtrl.fan) + { +// case 0: CtrlSend[5] = 0x03; break; //ֹͣ + case TEMP_LOW: CtrlSend[7] = 0x03; break; // + case TEMP_MID: CtrlSend[7] = 0x02; break; // + case TEMP_HIGH: CtrlSend[7] = 0x01; break; // + case TEMP_FANAUTO: CtrlSend[7] = 0x00; break; //Զ + } + break; + case 2: //¶ + CtrlSend[6] = 0x03; + CtrlSend[7] = TEMTEMPCONVER(Rs485Tem->TemStateCtrl.set_t); // + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s:¶:%d", __func__,CtrlSend[7]); + break; + } + + NetCRC16(&CtrlSend[3],7); + Rs485Tem->DevOffline = DEV_IS_LINEUNINIT; //豸״̬δȷ + + /**/ + MCU485_SendString(BUS_Public->port,CtrlSend,10); + + /*־¼*/ + LOG_Device_COMM_Send_Control_Record(BUS_Public->port,BUS_Public->baud,CtrlSend,10); +} + +/******************************************************************************* +* Function Name : BLWOut_tempCycle +* Description : BLWOut¿ѯͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_tempT1Cycle(Device_Public_Information_G *BUS_Public) +{ + // ͷ LEN Type Addr CMD + uint8_t t_send[9] = {0x55, 0x55, 0xEE, 0x06, 0x03, 0x01, 0x0A}; //ѯ + + t_send[5] = BUS_Public->addr; // SRAM_Read_Byte(dev_addr+Dev_Addr); + + NetCRC16(&t_send[3],6); + + /**/ + MCU485_SendString(BUS_Public->port,t_send,9); +} + +/******************************************************************************* +* Function Name : BLWOut_tempT1CardCtrl +* Description : BLWOut¿忨״̬ܷͬͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLWOut_tempT1CardCtrl(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485Tem) +{ + // ͷ LEN Type Addr CMD + uint8_t t_send[10] = {0x55, 0x55, 0xEE, 0x07, 0x03, 0x01, 0x11 , 0x00 ,0x00, 0x00}; //ѯ + + t_send[5] = BUS_Public->addr; + t_send[7] = Rs485Tem->CardEn; + + NetCRC16(&t_send[3],7); + + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"BLWOut_tempT1CardCtrl",t_send,10); + /**/ + MCU485_SendString(BUS_Public->port,t_send,10); +} + +/******************************************************************************* +* Function Name : BLV_T1Temp_PortSet_Send +* Description : BLV T1¿ض˿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_T1Temp_PortSet_Send(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485Tem) +{ + // ͷ LEN Type Addr CMD + uint8_t t_send[10] = {0x55, 0x55, 0xEE, 0x07, 0x03, 0x01, 0x12 , 0x00 ,0x00, 0x00}; //ѯ + + t_send[5] = BUS_Public->addr; + t_send[7] = Rs485Tem->DevPort; + + NetCRC16(&t_send[3],7); + + Dbg_Print_Buff(DBG_BIT_DEVICE_STATUS_bit,"BLV_T1Temp_PortSet_Send",t_send,10); + /**/ + MCU485_SendString(BUS_Public->port,t_send,10); +} + +/******************************************************************************* +* Function Name : BLWOut_TempT1CycleCtrl +* Description : BLWOut¿ѯƷͺ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLWOut_TempT1CycleCtrl(uint32_t dev_addr) +{ + return TemSingleJudge(dev_addr, BLWOut_TempT1Ctrl, BLWOut_tempT1Cycle); +} + +/******************************************************************************* +* Function Name : BLWOut_TempT1CtrDataProc +* Description : BLWOut¿ݴ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLWOut_TempT1CtrDataProc(Device_Public_Information_G* BUS_Public, uint8_t *data, RS485_TEMP_INFO *Rs485Tem) +{ + RS485_TEMP_BASIC Rs485TemRecBuf; //¿ֲڴ洢¿ + uint8_t temp = 0; + + switch(data[4]) + { + case 0x01: // + Rs485TemRecBuf.TemState.on_off = TEMP_STATE_ON; + break; + case 0x00: //ػ + Rs485TemRecBuf.TemState.on_off = TEMP_STATE_OFF; + break; + } + + switch(data[6]) + { + case 1: // + Rs485TemRecBuf.TemState.mode = TEMP_COLD; + break; + case 2: // + Rs485TemRecBuf.TemState.mode = TEMP_HOT; + break; + case 3: //ͷ + Rs485TemRecBuf.TemState.mode = TEMP_WIND; + break; + } + Rs485TemRecBuf.TemState.set_t = data[7]; + switch(data[10]) + { + case 1: + Rs485TemRecBuf.TemState.fan = TEMP_HIGH; + break; // + case 2: + Rs485TemRecBuf.TemState.fan = TEMP_MID; + break; // + case 3: + Rs485TemRecBuf.TemState.fan = TEMP_LOW; + break; // + case 0: + Rs485TemRecBuf.TemState.fan = TEMP_FANAUTO; + break; //Զ + } + + + if((data[13] & 0x08)) //||(temp & 0x10) + { + Rs485TemRecBuf.TemState.valve = TEMP_VALVE_OPEN; + }else{ + Rs485TemRecBuf.TemState.valve = TEMP_VALVE_CLOSE; // + } + + if(0x00 != (data[13]&0x07)) //0 Ͱնȥ + { + Rs485TemRecBuf.FanAutoRelay = (data[13]&0x07); //Զٻõ ֵֻλ + }else{ + Rs485TemRecBuf.FanAutoRelay = 0x00; //֧Զ + } + Rs485TemRecBuf.TemState.indoor_t = data[17];//SRAM_Read_Byte(data_addr + 17); // + + if((Rs485TemRecBuf.TemState.on_off != Rs485Tem->TemState.on_off) || (Rs485TemRecBuf.TemState.mode != Rs485Tem->TemState.mode) || + (Rs485TemRecBuf.TemState.fan != Rs485Tem->TemState.fan) || (Rs485TemRecBuf.TemState.valve != Rs485Tem->TemState.valve)|| + (Rs485TemRecBuf.FanAutoRelay != Rs485Tem->FanAutoRelay) || + (Rs485TemRecBuf.TemState.set_t != Rs485Tem->TemState.set_t)||(Rs485TemRecBuf.TemState.indoor_t != Rs485Tem->TemState.indoor_t))//ػ ģʽ ¶ ¶봢IJһ + { + + Temp_Action_Set(&Rs485TemRecBuf, Rs485Tem); //ͬ״̬ + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿ַ:%d ״̬", BUS_Public->addr); // + switch(Rs485Tem->TemState.on_off) + { + case TEMP_STATE_OFF: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ػ"); + break; + case TEMP_STATE_ON: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + } + switch(Rs485Tem->TemState.mode) + { + case 0x01: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + case 0x02: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + case 0x03: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ͷ"); + break; + } + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,":%d", Rs485Tem->FanAutoRelay); + + switch(Rs485Tem->TemState.fan) + { + case 0x00: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Զ"); + break; + case 0x01: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + case 0x02: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + case 0x03: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + } + switch(Rs485Tem->TemState.valve) + { + case TEMP_VALVE_OPEN: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + case TEMP_VALVE_CLOSE: + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,""); + break; + } + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¶:%d ¶:%d\r\n",Rs485Tem->TemState.set_t,Rs485TemRecBuf.TemState.indoor_t); + + temp++; + } + + if(Rs485Tem->TemState.on_off == Rs485Tem->control_start) //ؿ״̬Ƴɹ־λ + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"״̬־"); + Rs485Tem->control_start = 0xFF; + + temp++; + } + + /*ȶԷϱ״̬ - Ƿд־ + 2025-10-13 ޸ + 1ֻû״̬仯ϱ¶ȱ仯ϱ + 2¿ֹͣ30Sٽϱ + */ + if( (Rs485Tem->TemStateLast.on_off != Rs485Tem->TemState.on_off) \ + || (Rs485Tem->TemStateLast.mode != Rs485Tem->TemState.mode) \ + || (Rs485Tem->TemStateLast.fan != Rs485Tem->TemState.fan) \ + || (Rs485Tem->TemStateLast.valve != Rs485Tem->TemState.valve) \ + || (Rs485Tem->TemStateLast.set_t != Rs485Tem->TemState.set_t) ) + { + Dev_Temp_State_Sync(&Rs485Tem->TemStateLast,&Rs485Tem->TemState); + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"ϱ:%04x",Dev_Temp_State_Data(Rs485Tem->TemState)); + + Rs485Tem->udp_flag = 0x01; + Rs485Tem->udp_tick = SysTick_1ms; + temp++; + } + + if(Rs485Tem->udp_flag == 0x01) + { + if( SysTick_1ms - Rs485Tem->udp_tick >= 30000) + { + Rs485Tem->udp_tick = SysTick_1ms; + Rs485Tem->udp_flag = 0x00; + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"д־:%04x",Dev_Temp_State_Data(Rs485Tem->TemStateLast)); + + temp++; + //д־ + Udp_Addtion_Roomstate(DEV_RS485_TEMP,BUS_Public->addr,0x0000,Dev_Temp_State_Data(Rs485Tem->TemStateLast)); + } + } + + return temp; +} + +#define RECDATALENMAX 24 //󳤶 + +/******************************************************************************* +* Function Name : BLWOut_Rs485_Tem_Check +* Description : BLWOut¿ݴ +* Input : + dev_addr : 豸Ϣַ + data_addr : ݵַ + len ݳ +* Return : + 0x00ɹ + 0x01ʧ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLWOut_Rs485_TempT1_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len) +{ + uint8_t temp_1 = 0; + uint8_t rev = 0x01; + + uint8_t data[RECDATALENMAX]; + uint16_t crc_val = 0; + RS485_TEMP_INFO Rs485TempT1; + Device_Public_Information_G BUS_Public; + + memset(data,0x00,RECDATALENMAX); + + if(len > RECDATALENMAX) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"T1 Temp ݳȳΧ!!\r\n"); + return rev; // + } + SRAM_DMA_Read_Buff(data,len,data_addr); //482 + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),dev_addr+Dev_Privately); + + if(len < 6) return rev; + + if((data[0] != 0x55) || (data[1] != 0x55) || (data[2] != 0xee) || (len != data[3] + 0x03) || (0x03 != data[4]) ||BUS_Public.addr!=data[5] ) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"%s Addr:%d Check Error",__func__,BUS_Public.addr); + return rev; + } + crc_val = data[len-2] + (data[len-1]<<8); + + if(crc_val == NetCRC16_2(&data[3],len - 5)) + { + rev = 0x00; + + if(Rs485TempT1.DevOffline != DEV_IS_ONLINE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"Rs485TempT1 LogInfo_Device_Online..........."); + LOG_Device_Online_Record(DEV_RS485_TEMP,BUS_Public.addr,LogInfo_Device_Online); //¼豸 + } + BLV_Communication_Record(&Rs485TempT1.comm_record,0x02,0x01); //¼ͨѶɹ + Rs485TempT1.DevSendCnt = 0x00; //0 + + switch(data[3]) //ݳ + { + case 0x15://ѯظ + Rs485TempT1.DevOffline = DEV_IS_ONLINE; //Ψѯ豸 + if(Rs485TempT1.DevOffline != Rs485TempT1.DevOfflineLast) //ǰ״̬һ״̬ + { + Rs485TempT1.DevOfflineLast = Rs485TempT1.DevOffline; //һ״̬ + Write_Device_Fault_State(BUS_Public.type,BUS_Public.addr,In_ErrFun_LineState,DEV_IS_ONLINE); //豸״̬SRAM + } + temp_1 = BLWOut_TempT1CtrDataProc(&BUS_Public, &data[3], &Rs485TempT1); + if(temp_1 != 0x00) //ѯظб仯 + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"BLV Rs485 TempT1 Reply Change"); + LOG_Device_COMM_ASK_TO_Reply_Record(BUS_Public.port, BUS_Public.baud,(SysTick_1ms - Rs485TempT1.inquire_tick),data,len); + } + if(BUS_Public.port == Active_Port) //2024-11-26 + { + BLWOut_tempT1Cycle(&BUS_Public); + } + break; + case 0x07: //ƿػ + switch(data[6]) //SRAM_Read_Byte(data_addr + 6) + { + case 0x01: //ػظ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յػظ忪ػƱ־", BUS_Public.addr); + Rs485TempT1.TemStateCtrlFlag.TemOnOffCtrlVar = 0x00; //տػƱ־ + break; + case 0x02: //ģʽ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յģʽظģʽƱ־", BUS_Public.addr); + Rs485TempT1.TemStateCtrlFlag.TemModeCtrlVar = 0x00; //ģʽƱ־ + break; + case 0x04: // + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յٻظٿƱ־", BUS_Public.addr); + Rs485TempT1.TemStateCtrlFlag.TemFanCtrlVar = 0x00; //շٿƱ־ + break; + case 0x03: //¶ + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յ¶Ȼظ¶ñ־", BUS_Public.addr); + Rs485TempT1.TemStateCtrlFlag.TemSetTCtrlVar = 0x00; //¶ȿƱ־ + break; + case 0x11: + Rs485TempT1.CardFlag = 0x00; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յ忨״̬ûظñ־", BUS_Public.addr); + break; + case 0x12: + Rs485TempT1.DevPort_Flag = 0x00; + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"¿:%d յö˿ûظñ־", BUS_Public.addr); + break; + } + + /*־¼*/ + LOG_Device_COMM_Control_Reply_Record(BUS_Public.port, BUS_Public.baud,data,len); + break; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485TempT1, sizeof(RS485_TEMP_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&Rs485TempT1,sizeof(RS485_TEMP_INFO),dev_addr+Dev_Privately); + } + + return rev; +} + + + + + + + + + + + + + + diff --git a/BLV_485_Driver/inc/blv_bus_dev_c5iofun.h b/BLV_485_Driver/inc/blv_bus_dev_c5iofun.h new file mode 100644 index 0000000..893a5ec --- /dev/null +++ b/BLV_485_Driver/inc/blv_bus_dev_c5iofun.h @@ -0,0 +1,192 @@ +/* + * blv_bus_dev_c5iofun.h + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_BUS_DEV_C5IOFUN_H_ +#define BLV_485_DRIVER_INC_BLV_BUS_DEV_C5IOFUN_H_ + +#include +#include "ch564.h" +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define C5IOTYPE 0xF1 //C5IO豸 - 豸ֻBLV_BUSЭͨѶʹ +#define DEV_C5IO_Type 0xF1 //豸бе豸 + +#define C5IO_REPEATSENDTIMEMAX 0x02 //ط +#define C5IO_SEND_WAIT_TIME 0x28 //ȴʱ 2024-02-23 + +#define C5IO_RecvData_Len_MAX 0x28 //ݳĿǰ30Byte + +#define BLV_C5IO_Inquire_CMD 0x20 +#define BLV_C5IO_Set_Relay_CMD 0x21 +#define BLV_C5IO_Set_Relay_Inching_CMD 0x22 +#define BLV_C5IO_Set_Do_CMD 0x23 +#define BLV_C5IO_Set_Do_Inching_CMD 0x24 +#define BLV_C5IO_Set_Di_CMD 0x25 +#define BLV_C5IO_SetRTC_CMD 0x27 +#define BLV_C5IO_Reply_CMD 0xA0 + +#define BLV_C5IO_Reply_Result 0x00 +#define BLV_C5IO_Relay_Result 0x01 +#define BLV_C5IO_Relay_Inching_Result 0x02 +#define BLV_C5IO_Do_Result 0x03 +#define BLV_C5IO_Do_Inching_Result 0x04 +#define BLV_C5IO_Di_Result 0x05 +#define BLV_C5IO_Error_Result 0xF0 + +#define BUS_C5IO_DI_Key_Type 0x01 //DI - +#define BUS_C5IO_DI_Pir_Type 0x02 //DI - PIR +#define BUS_C5IO_DI_Dry_Type 0x03 //DI - ɽӵ +#define BUS_C5IO_DI_Level_HIGH 0x20 //DIΪߵƽ +#define BUS_C5IO_DI_Level_LOW 0x10 //DIΪ͵ƽ + +#define BUS_C5IO_DO_Common_Mode 0x00 //DOģʽ - ģʽ +#define BUS_C5IO_DO_Inching_Mode 0x01 //DOģʽ - 㶯ģʽ +#define BUS_C5IO_OUT_LOW 0x01 +#define BUS_C5IO_OUT_HIGH 0x02 +#define BUS_C5IO_OUT_TOGGLE 0x03 +#define BUS_C5IO_Right_Inching 0x01 +#define BUS_C5IO_Reverse_Inching 0x02 +#define BUS_C5IO_Toggle_Inching 0x03 + +typedef enum{ + C5IO_Relay_CH1, + C5IO_Relay_CH2, + C5IO_Relay_CH3, + C5IO_Relay_CH4, + C5IO_Relay_CH5, + C5IO_Relay_CH6, + C5IO_Relay_CH7, + C5IO_Relay_CH8, + C5IO_Relay_CH9, + C5IO_Relay_CH10, + C5IO_Relay_CH11, + C5IO_Relay_CH12, + C5IO_Relay_CH13, + C5IO_Relay_CH14, + C5IO_Relay_CH15, + C5IO_Relay_CH16, + C5IO_Relay_CH17, + C5IO_Relay_CH18, + C5IO_Relay_CH19, + C5IO_Relay_CH20, + C5IO_Relay_CH21, + C5IO_Relay_CH22, + C5IO_Relay_CH23, + C5IO_Relay_CH24, + C5IO_Relay_CH_MAX, +}BUS_C5IO_RELAY_NUM_E; + +typedef enum{ + C5IO_DO_CH1, + C5IO_DO_CH2, + C5IO_DO_CH3, + C5IO_DO_CH4, + C5IO_DO_CH5, + C5IO_DO_CH_MAX, +}BUS_C5IO_DO_NUM_E; + +typedef enum{ + C5IO_DI_CH1, + C5IO_DI_CH2, + C5IO_DI_CH3, + C5IO_DI_CH4, + C5IO_DI_CH5, + C5IO_DI_CH6, + C5IO_DI_CH7, + C5IO_DI_CH8, + C5IO_DI_CH9, + C5IO_DI_CH10, + C5IO_DI_CH11, + C5IO_DI_CH12, + C5IO_DI_CH13, + C5IO_DI_CH_MAX, +}BUS_C5IO_DI_NUM_E; + +typedef struct{ + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + + uint8_t DO_Mode[C5IO_DO_CH_MAX]; //DOģʽ + uint8_t DO_Control[C5IO_DO_CH_MAX]; //Do + uint16_t Last_DO_Level_Start; //֮ǰDOʵʵƽ״̬ + uint16_t DO_Level_Actual_Start; //DOʵʵƽ״̬ + uint16_t DO_Level_Perfect_Start; //DOƽ״̬ + uint16_t DO_Inching_Tick[C5IO_DO_CH_MAX]; //DO㶯ʱ + uint16_t DO_Inching_Time[C5IO_DO_CH_MAX]; //DO㶯ʱ + + uint8_t Relay_Mode[C5IO_Relay_CH_MAX]; //̵ģʽ + uint8_t Relay_Control[C5IO_Relay_CH_MAX]; //̵ + uint32_t Last_Relay_Level_Start; //֮ǰ̵ʵʵƽ״̬ + uint32_t Relay_Level_Actual_Start; //̵ʵ״̬ + uint32_t Relay_Level_Perfect_Start; //̵״̬ + uint16_t Relay_Inching_Tick[C5IO_Relay_CH_MAX]; //̵㶯ʱ + uint16_t Relay_Inching_Time[C5IO_Relay_CH_MAX]; //̵㶯ʱ + uint8_t Relay_feedback; //̵־λ + + uint8_t DI_Type[C5IO_DI_CH_MAX]; //DI 0~3: 4~7:ƽ + uint16_t DI_Level_Actual_Start; + uint32_t DI_Actual_State; + uint32_t DI_Perfect_State; + uint8_t DI_Start[C5IO_DI_CH_MAX]; //DI״̬ + uint8_t DI_LastStart[C5IO_DI_CH_MAX]; + uint8_t DI_Detection_Time[C5IO_DI_CH_MAX]; //DIʱ + + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ + uint8_t DevOffline; //豸߱־ 1豸 0豸 + uint8_t DevOfflineLast; //豸һ߱־ 1豸 0豸 + uint8_t DevSendSN; //SN + + uint8_t Send_Type; // + uint16_t DI_Control_Flag; //DIƱ־λ + uint16_t Last_DI_Control_Flag; //DIϴοƱ־λ + uint8_t DO_Control_Flag; //DOƱ־λ + uint8_t Last_DO_Control_Flag; //DOϴοƱ־λ + uint8_t DO_Inching_Control_Flag; //DO㶯Ʊ־ + uint8_t Last_DO_Inching_Control_Flag; //DO㶯ϴοƱ־ + uint32_t Relay_Control_Flag; //̵Ʊ־λ + uint32_t Last_Relay_Control_Flag; //̵ϴοƱ־ + uint32_t Relay_Inching_Control_Flag; //̵㶯Ʊ־λ + uint32_t Last_Relay_Inching_Control_Flag; //̵㶯ϴοƱ־λ + + uint8_t C5IO_Version; //IO汾 - C5 C12 CSIO + uint8_t comm_version; //CSIOͨѶЭ - Դİ汾 + uint32_t inquire_tick; //ѯʱ + uint16_t CxIO_DI_Control_Flag; //¼ҪõDI· + uint8_t DI_Reset_Flag; //DI + uint32_t DI_Reset_Tick; //DIʱ + uint8_t Relay_Reset_Flag; //̵״ָ̬ + uint8_t rtc_set_flag; + uint8_t DI_Init_flag; //DIʼ־λ 2025-08-07 ϵ󣬲 +}BUS_C5IO_INFO; + +void BLV_BUS_CSIO_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +void BLV_BUS_CSIO_DI_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +uint8_t BLV_BUS_C5IO_Cycle_Call(uint32_t dev_addr); +uint8_t BLV_CSIO_RTC_TimeValid(uint8_t *date); +uint8_t BLV_BUS_C5IO_Data_Processing(uint32_t dev_addr,uint32_t data_addr,uint16_t len); +void BUS_C5IO_DI_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_DO_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_DO_Inching_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_Relay_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_Relay_Inching_Control_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_CSIO_SetRTCTime_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_Inquire_Datasend(uint32_t dev_addr,BUS_C5IO_INFO *Dev_Info); +void BUS_C5IO_Control_Relay(uint32_t dev_addr,uint8_t loop,uint8_t start); +void BUS_C5IO_Control_Do(uint32_t dev_addr,uint8_t loop,uint8_t start); +void BUS_C5IO_Control_Relay_Inching(uint32_t dev_addr,uint8_t loop,uint8_t start,uint16_t d_time); +void BUS_C5IO_Group_Control_Relay(uint32_t dev_addr,uint32_t loop,uint32_t start); +void BUS_CSIO_Set_RTC_Time(uint32_t dev_addr); +uint32_t Get_BUS_C5IO_Realy_Status(uint32_t devaddr); +uint8_t Get_BUS_C5IO_Online_Status(uint32_t devaddr); +uint8_t Get_Bus_C5IO_COMM_State(uint32_t devaddr); +uint8_t Get_Bus_CSIO_COMM_Version(uint32_t devaddr); + + + + + +#endif /* BLV_485_DRIVER_INC_BLV_BUS_DEV_C5IOFUN_H_ */ diff --git a/BLV_485_Driver/inc/blv_bus_dev_c5music.h b/BLV_485_Driver/inc/blv_bus_dev_c5music.h new file mode 100644 index 0000000..7446a78 --- /dev/null +++ b/BLV_485_Driver/inc/blv_bus_dev_c5music.h @@ -0,0 +1,250 @@ +/* + * blv_bus_dev_c5music.h + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_BUS_DEV_C5MUSIC_H_ +#define BLV_485_DRIVER_INC_BLV_BUS_DEV_C5MUSIC_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define C5MUSICTYPE 0x01 //C5IO豸 - 豸ֻBLV_BUSЭͨѶʹ +#define DEV_C5MUSIC_Type 0x15 //豸бе豸 + +#define C5MUSIC_REPEATSENDTIMEMAX 0x04 //豸ط +#define C5MUSIC_SEND_WAIT_TIME 0x0020 //C5MUSIC͵ȴʱ - 32ms + +#define BLV_C5MUSIC_Playback_Status_CMD 0x20 //ѯǰ״̬ +#define BLV_C5MUSIC_Set_Default_Volume_CMD 0x21 //趨Ĭϲ +#define BLV_C5MUSIC_Specify_Play_CMD 0x22 //ָ״̬ +#define BLV_C5MUSIC_Set_Volume_CMD 0x23 // +#define BLV_C5MUSIC_Query_Default_Volume_CMD 0x24 //ѯĬ +#define BLV_C5MUSIC_Query_Volume_CMD 0x26 //ѯ +#define BLV_C5MUSIC_Set_Loop_Mode_CMD 0x29 //ѭģʽ +#define BLV_C5MUSIC_Query_Loop_Mode_CMD 0x2A //ѯѭģʽ +#define BLV_C5MUSIC_Query_Filenum_CMD 0x2B //ѯļ() +#define BLV_C5MUSIC_Query_Versions_CMD 0x2C //ѯ汾 +#define BLV_C5MUSIC_Write_FILEHEAD_CMD 0x2D //дļͷ +#define BLV_C5MUSIC_Write_FILEData_CMD 0x2E //дļ +#define BLV_C5MUSIC_Read_FILEHEAD_CMD 0x2F //ļͷ +#define BLV_C5MUSIC_Read_FILEData_CMD 0x40 //ļ + +#define BLV_C5MUSIC_Playback_Status_Reply 0x30 //ѯǰ״̬ظ +#define BLV_C5MUSIC_Set_Default_Volume_Reply 0x31 //趨Ĭϲظ +#define BLV_C5MUSIC_Specify_Play_Reply 0x32 //ָ״̬ظ +#define BLV_C5MUSIC_Set_Volume_Reply 0x33 //ظ +#define BLV_C5MUSIC_Query_Default_Volume_Reply 0x34 //ѯĬظ +#define BLV_C5MUSIC_Query_Volume_Reply 0x36 //ѯظ +#define BLV_C5MUSIC_Set_Loop_Mode_Reply 0x39 //ѭģʽظ +#define BLV_C5MUSIC_Query_Loop_Mode_Reply 0x3A //ѯѭģʽظ +#define BLV_C5MUSIC_Query_Filenum_Reply 0x3B //ѯļ()ظ +#define BLV_C5MUSIC_Query_Versions_Reply 0x3C //ѯ汾Żظ +#define BLV_C5MUSIC_Write_FILEHEAD_Reply 0x3D //дļͷظ +#define BLV_C5MUSIC_Write_FILEData_Reply 0x3E //дļݻظ +#define BLV_C5MUSIC_Read_FILEHEAD_Reply 0x3F //ļͷظ +#define BLV_C5MUSIC_Read_FILEData_Reply 0x50 //ļݻظ + +#define C5MUSIC_Control_Num 13 //13ֿ +#define C5MUSIC_Set_Default_Volume_Flag 0x0001 //趨ĬϲƱ־λ +#define C5MUSIC_Set_Volume_Flag 0x0002 //Ʊ־λ +#define C5MUSIC_Set_Loop_Mode_Flag 0x0004 //ѭģʽƱ־λ +#define C5MUSIC_Specify_Play_Flag 0x0008 //ָ״̬Ʊ־λ +#define C5MUSIC_Query_Default_Volume_Flag 0x0010 //ѯĬƱ־λ +#define C5MUSIC_Query_Volume_Flag 0x0020 //ѯƱ־λ +#define C5MUSIC_Query_Loop_Mode_Flag 0x0040 //ѯѭģʽƱ־λ +#define C5MUSIC_Query_Filenum_Flag 0x0080 //ѯļ()Ʊ־λ +#define C5MUSIC_Query_Versions_Flag 0x0100 //ѯ汾ſƱ־λ +#define C5MUSIC_Write_FILEHEAD_Flag 0x0200 //дļͷƱ־λ +#define C5MUSIC_Write_FILEData_Flag 0x0400 //дļݿƱ־λ +#define C5MUSIC_Read_FILEHEAD_Flag 0x0800 //ļͷƱ־λ +#define C5MUSIC_Read_FILEData_Flag 0x1000 //ļݻظ־λ + +#define BLV_C5MUSIC_Relay_SUCC 0xE0 //޴ +#define BLV_C5MUSIC_Relay_Check_Error 0xE1 //CRCУ +#define BLV_C5MUSIC_Relay_CMD_Error 0xE2 // +#define BLV_C5MUSIC_Relay_Para_Error 0xE3 // +#define BLV_C5MUSIC_Relay_Other_Error 0xE4 // + +#define BLV_C5MUSIC_Music_Dir 0x00 //ļ +#define BLV_C5MUSIC_Warning_Dir 0x01 //ʾļ +#define BLV_C5MUSIC_Helpsleep_Dir 0x02 //ļ +#define BLV_C5MUSIC_Doorbell_Dir 0x03 //ļ +#define BLV_C5MUSIC_Greet_Dir 0x04 //ӭļ +#define BLV_C5MUSIC_Helpsleep1_Dir 0x05 //ļ_1_ڤ +#define BLV_C5MUSIC_Helpsleep2_Dir 0x06 //ļ_2_ +#define BLV_C5MUSIC_Helpsleep3_Dir 0x07 //ļ_3_ɭ + + +#define BLV_C5MUSIC_Full_Loop 0x00 //ȫѭ +#define BLV_C5MUSIC_Single_Cycle 0x01 //ѭ +#define BLV_C5MUSIC_Folder_Loop 0x02 //ļѭ +#define BLV_C5MUSIC_Random_Cycle 0x03 //ѭ +#define BLV_C5MUSIC_Order_CyCle 0x05 //˳ѭ + +#define BLV_C5MUSIC_Playing 0x00 //״̬ +#define BLV_C5MUSIC_Halted 0x01 //ͣ״̬ +#define BLV_C5MUSIC_Stopped 0x02 //ֹͣ״̬ +#define BLV_C5MUSIC_Next_Song 0x03 //һ +#define BLV_C5MUSIC_Prev_Song 0x04 //һ +#define BLV_C5MUSIC_Fast_Forward 0x05 // +#define BLV_C5MUSIC_Rewind 0x06 // +#define BLV_C5MUSIC_Single_Play 0x07 // +#define BLV_C5MUSIC_Forestall 0x08 //Ȳ + +#define BLV_C5MUSIC_Volume_MAX 30 // +#define BLV_C5MUSIC_Volume_MIN 0 //С +#define BLV_C5MUSIC_Default_Volume 25 //Ĭ +#define BLV_C5MUSIC_HelpSleep_Start_Volume 10 //ʼ + +/*ֺ궨忪ʼ*/ +#define MUSICLOOPMAX 0x05 //ÿ· +#define CtrlDirectOpen 0x01 // +#define CtrlDirectClose 0x02 // + +typedef struct{ + + uint8_t CtrlDirect; //Ʒ ù:0x00 0x01 0x02ػ 0x03 0x04ز + uint8_t CtrlDir; //Ŀ¼ CtrlDirectΪ0x03ʱ CtrlDirʾļ CtrlContʾ CtrlDirectΪ0x00ʱ CtrlDirΪ1ʾ CtrlDirΪ2ʾͣ + +}DEV_MUSIC_CTRLWAY; //Ʒʽ 1ֽڴǿػ + +typedef struct{ + uint8_t CtrlMode; //ģʽ + uint8_t CtrlVoice; // +}DEV_MUSIC_CTRLCONT; // + +typedef struct{ + DEV_MUSIC_CTRLWAY DevMusicCtrlWay; //Ʒʽ + DEV_MUSIC_CTRLCONT CtrlCont; // +}DEV_MUSIC_CTRLSTATE; // +/*ֺ궨*/ + +typedef struct{ + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ + uint8_t DevOffline; //豸߱־ 1豸 0豸 + uint8_t DevOfflineLast; //һ߱־ 1豸 0豸 + uint8_t DevSendSN; //SN + + uint8_t now_playback_status_num; //״̬ı - ȡ״̬һŸֵ״̬ + uint8_t now_playback_type; //ǰ - 0x01:֡0x02:ϴּ֡0x03:ϴ֡0x04:塢0x05Żӭ + uint8_t now_playback_status; //ǰ״̬ - ţδ + uint8_t last_playback_status; + uint8_t now_playback_volume; //ǰ + uint8_t last_playback_volume; + uint8_t now_mute_status; //ǰ״̬ + uint8_t now_global_volume; //ǰȫְٷֱ + uint8_t now_music_volume; //ǰ + uint8_t now_tone_volume; //ǰʾ + uint8_t now_door_volume; //ǰ + uint8_t now_helpsleep_volume; //ǰ 2022-12-16 + uint8_t now_playback_mode; //ǰģʽ - 0x00:ȫѭš0x01:ѭ0x02:ļѭ0x03:š0x05:˳򲥷 + uint8_t now_playback_dir; //ǰļ + uint8_t last_playback_dir; + uint16_t now_playback_idx; //ǰ + uint16_t last_playback_idx; + + uint8_t assign_dir; //0x00:ļ 0x01:ʾļ 0x02:ļ 0x03:ļ 0x04:ӭļ + uint16_t assign_playback_path; //ָ· + uint16_t assign_playback_idx; //ָļ + + uint8_t adjust_volume_type; // 0x01:Ե 0x02:Ե + uint8_t adjust_volume_operate; //0x01 - һ0x02 - һ + uint8_t adjust_volume_loop; //· + uint8_t set_playback_volume; // + uint8_t set_music_volume; // + uint8_t set_tone_volume; //ʾ + uint8_t set_door_volume; // + uint8_t set_helpsleep_volume; + uint8_t set_global_volume; //ȫְٷֱ + uint16_t fade_time; //ʱ - λ100ms + uint16_t helpsleep_time; //ʱ - λ1S + uint32_t helpsleep_tick; //ʱ + + uint8_t playback_type; // - 0x01:֡0x02:ϴּ֡0x03:ϴ֡0x04:塢0x05Żӭ + uint8_t playback_fun; //Ź - 0x00:š0x01:ͣ0x02:ֹͣ0x03:һס0x04:һס0x05:0x06:ˡ0x07: + uint8_t playback_mode; //ģʽ - 0x00:ȫѭš0x01:ѭ0x02:ļѭ0x03:š0x05:˳򲥷 + uint8_t quiet_mode; //ģʽ - 0x00:0x01: + uint8_t set_quiet_status; //þ״̬ - 0x00:0x01:رվ + uint8_t quite_flag; //ƷƱ־λ + uint8_t global_volume; //ȫְٷֱ + uint8_t default_volume; //Ĭ + uint8_t helpsleep_volume; // + uint8_t playback_volume_max; // + uint8_t playback_volume_min; //С + +/*״̬忪ʼ*/ + DEV_MUSIC_CTRLSTATE BackMusicState[MUSICLOOPMAX]; //ֵǰ״̬ + DEV_MUSIC_CTRLSTATE BackMusicStateLast[MUSICLOOPMAX]; //һ״̬ + +/*״̬*/ + + uint16_t file_block; //ļǰ + uint16_t file_block_num; //ļܿ + uint16_t file_size; //ļС + uint32_t file_start_addr; //ļʼַ + uint32_t file_end_addr; //ļַ + + uint16_t playback_num; // + uint16_t dev_versions; //豸汾 + uint32_t control_flag; //Ʊ־λ + + uint32_t inquire_tick; //ѯʱ +}BUS_C5MUSIC_INFO; + +void BLV_BUS_C5MUSIC_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +uint8_t BLV_BUS_C5MUSIC_Cycle_Call(uint32_t dev_addr); +uint8_t BLV_BUS_C5MUSIC_Data_Processing(uint32_t dev_addr,uint32_t data_addr,uint16_t len); +void BUS_C5MUSIC_Playback_Status_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Set_Default_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Specify_Play_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Set_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Query_Default_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Query_Volume_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Set_Loop_Mode_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Query_Loop_Mode_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Query_Filenum_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Query_Versions_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Write_FILEHEAD_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Write_FILEData_Datasend(uint32_t dev_addr,BUS_C5MUSIC_INFO *Dev_Info); +void BUS_C5MUSIC_Set_Playback_Mode(uint32_t devaddr,uint8_t play_mode); +void BUS_C5MUSIC_Playback(uint32_t devaddr,uint8_t play_dir,uint8_t playback,uint8_t play_id); +void BUS_C5MUSIC_Doorbell_Dir(uint32_t devaddr,uint8_t id); +void BUS_C5MUSIC_Warning_Dir(uint32_t devaddr,uint8_t id,uint8_t start); +void BUS_C5MUSIC_Greet_Dir(uint32_t devaddr,uint8_t id,uint8_t start); +void BUS_C5MUSIC_Helpsleep_Dir(uint32_t devaddr,uint8_t dir,uint8_t id); +void BUS_C5MUSIC_Play_Helpsleep_Dir(uint32_t devaddr,uint8_t dir,uint8_t id, uint16_t time); +void BUS_C5MUSIC_Helpsleep_Dir_Just(uint32_t devaddr,uint8_t dir,uint8_t id); +void BUS_C5MUSIC_Stop_Playback(uint32_t devaddr); +void BUS_C5MUSIC_Play_Playback(uint32_t devaddr); +void BUS_C5MUSIC_Play_Playback_Next(uint32_t devaddr); +void BUS_C5MUSIC_Play_Playback_Last(uint32_t devaddr); +void BUS_C5MUSIC_Pause_Playback(uint32_t devaddr); +void BUS_C5MUSIC_Playback_Next(uint32_t devaddr, uint8_t dir); +void BUS_C5MUSIC_Playback_Prev(uint32_t devaddr, uint8_t dir); +void BUS_C5MUSIC_Relative_Volume_Plus(uint32_t devaddr); +void BUS_C5MUSIC_Relative_Volume_Subtraction(uint32_t devaddr); +void BUS_C5MUSIC_Relative_Volume_PlusValue(uint32_t devaddr, uint8_t value); +void BUS_C5MUSIC_Relative_Volume_SubtractionValue(uint32_t devaddr, uint8_t value); +void BUS_C5MUSIC_Set_Quiet_Mode(uint32_t devaddr); +void BUS_C5MUSIC_Set_Quiet_Mode2(uint32_t devaddr,uint8_t status); +void BUS_C5MUSIC_Set_Global_Volume(uint32_t devaddr,uint8_t vel); +void BUS_C5MUSIC_Set_LoopVolume(uint32_t devaddr,uint8_t loop,uint8_t vel); +void BUS_C5MUSIC_Set_LoopVolume_2(uint32_t devaddr,uint8_t loop,uint8_t vel); +uint8_t Get_BUS_C5MUSIC_Loop_Volume(uint32_t devaddr,uint8_t loop); +uint8_t Get_BUS_C5MUSIC_Online_Status(uint32_t devaddr); +void BLV_Music_CtrlState_Get(DEV_MUSIC_CTRLSTATE *music_state,uint16_t Output_state ); +void Logic_Music_Ctrl(uint32_t DevAddrIn, uint16_t DevInputLoop, uint32_t DevAddrOut, uint16_t DevOutputLoop, uint16_t DevOutputType); +uint16_t Dev_Music_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop); + + + + + + +#endif /* BLV_485_DRIVER_INC_BLV_BUS_DEV_C5MUSIC_H_ */ diff --git a/BLV_485_Driver/inc/blv_device_option.h b/BLV_485_Driver/inc/blv_device_option.h new file mode 100644 index 0000000..a16c602 --- /dev/null +++ b/BLV_485_Driver/inc/blv_device_option.h @@ -0,0 +1,133 @@ +/* + * blv_device_option.h + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_DEVICE_OPTION_H_ +#define BLV_485_DRIVER_INC_BLV_DEVICE_OPTION_H_ + +#define ProCode NULL //Ŀ - uint32_t +#define HouseType NULL // +#define ProName "ͨAPP̼MQTT,֧LuancherV04" //Ŀ˵ -64Bytes + +#define C8_TYPE 0x00 //C8 + +#define FLash_Fix_Data 0x00 //Flashijڴ̶FF + +#define UDPServer_Internal_Flag 0x00 //UDPͨѶʹܱ־λ + +//#define LOGIC_FILE_EN 0x01 //ʹ߼ļ +#define Restart_Address_EN 0x01 //APPַ - 0x00:ĬַΪ0x8000,0x01:ַΪ0x5000 + +#define NET_DHCP_Optimized_INIT_EN 0x00 //DHCPŻDHCPʱIPΪ0.0.0.0 2022-07-19 + + +#define DevExistJudgge(Flag, FunName) ((0x01 == Flag)?FunName:NULL) //־λΪ1ͷغ 򷵻ؿ + + +/*̵궨忪ʼ*/ +#define RS485_HVout_C5RELAY_Flag 0x01 //C5̵ 1Ϊ 0Ϊر +#define RS485_HVout_A9RELAY_Flag 0x00 //A9̵ 1Ϊ 0Ϊر +#define RS485_HVout_SwiRELAY_Flag 0x01 //ǿ翪ؼ̵ 1Ϊ 0Ϊر +/*̵궨*/ + +/*485궨忪ʼ*/ +#define RS485_Switch_Touch_Flag 0x01 // 1Ϊ 0Ϊر +#define RS485_Switch_A9IO_Flag 0x00 //A9IO 1Ϊ 0Ϊر +#define RS485_Switch_Rotary_Flag 0x00 //ť +#define RS485_Switch_Rotary_P1_Flag 0x00 //ť Э1 +#define RS485_Switch_Rotary_P2_Flag 0x00 //ť Э2 +/*485궨*/ + +/*485¿궨忪ʼ*/ +#define RS485_Temp_T1_Flag 0x01 //T1¿ 1Ϊ 0Ϊر +#define RS485_Temp_T1_Flag_Si 0x01 //T1¿Ĺܣ +#define RS485_Temp_T1_Active_Flag 0x01 //T1¿ Ĺ +#define RS485_Temp_C7T_Flag 0x00 //C7T¿ 1Ϊ 0Ϊر +/*485¿궨*/ + +/*485¿궨忪ʼ*/ +#define RS485_LED_Flag 0x01 //485PWMܱ +#define RS485_LED_PWM_Flag 0x00 //PWM0~10V 1Ϊ 0Ϊر +#define RS485_LED_A9LD_Flag 0x00 //A9LD 1Ϊ 0Ϊر +#define RS485_LED_Slider_Flag 0x00 //Slider 1Ϊ 0Ϊر +#define RS485_LED_A8PB_Flag 0x00 //A8PB 1Ϊ 0Ϊر +#define RS485_LED_C12Dim_Flag 0x01 //C12Dim 1Ϊ 0Ϊر +#define RS485_LED_RGB_Flag 0x00 //RGB 1Ϊ 0Ϊر +/*485¿궨*/ + +/*485궨忪ʼ*/ +#define RS485_MUSIC_BLW_Flag 0x00 //С֣ 1Ϊ 0Ϊر +#define RS485_MUSIC_HES_Flag 0x00 //485˼ 1Ϊ 0Ϊر +/*485궨*/ + +#define RS485_RFGatewayHost_Flag 0x00 // BLW΢ +/*485΢궨忪ʼ*/ +#define RS485_WxLock_Flag 0x00 //΢ +#define RS485_WxLock_BLW_Flag 0x00 //BLW΢ 1Ϊ 0Ϊر +#define RS485_WxLock_FreeGo_Flag 0x00 //΢ 1Ϊ 0Ϊر +#define RS485_WxLock_CJia_Flag 0x00 //΢ 1Ϊ 0Ϊر +/*485΢궨*/ + +#define RS485_AirDetect_Flag 0x00 //־ +#define RS485_AirReveal_Flag 0x00 //ʾ־ + +#define RS485_TimeCtrl_Flag 0x00 //ʱ豸 + +#define RS485_Curtain_Flag 0x01 //485 +#define RS485_DOOYA_Curtain_Flag 0x00 //Ǵ +#define RS485_BinShen_Curtain_Flag 0x01 //괰 + +#define RS485_CardState_Flag 0x01 //忨״̬ͬ + +#define RS485_FreshAir_Flag 0x00 //· +#define RS485_FloorHeat_Flag 0x00 //ů +#define RS485_BLW_FreshAir_Flag 0x00 //· 1Ϊ 0Ϊر +#define RS485_BLW_FloorHeat_Flag 0x00 //ů 1Ϊ 0Ϊر +#define RS485_CLED_FreshAir_Flag 0x00 //CLED· 1Ϊ 0Ϊر +#define RS485_CLED_FloorHeat_Flag 0x00 //CLEDů 1Ϊ 0Ϊر + + +#if C8_TYPE + +#define RS485_PB20Fun_Flag 0x01 //PB20 +#define RS485_PB20_LD_Flag 0x00 //PB20-LD +#define RS485_PB20_LS_Flag 0x01 //PB20-LS +#define RS485_PB20_Relay_Flag 0x01 //PB20-Relay +#define RS485_LCD_1602_Flag 0x01 //LCD + +#else + +#define RS485_PB20Fun_Flag 0x00 //PB20 +#define RS485_PB20_LD_Flag 0x00 //PB20-LD +#define RS485_PB20_LS_Flag 0x00 //PB20-LS +#define RS485_PB20_Relay_Flag 0x00 //PB20-Relay +#define RS485_LCD_1602_Flag 0x00 //LCD + +#endif + +#define Dev_Nor_NoCard_Flag 0x00 //޿ϵ豸 +#define Dev_Nor_VirtualCard_Flag 0x01 //޿ȡ豸 +#define RS485_Dev_IN_CH6 0x00 //6· + +#define Dev_485_Pir_Flag 0x00 //485Ӧ + +#define Dev_Nor_ColorTemp 0x01 //ɫģ + +#define Dev_485_Card_Polling_Flag 0x01 //ѵ˿485忨ȡ +#define Dev_485_Card_Active_Flag 0x01 //˿485忨ȡ + +#define Dev_485_IrSend_Polling_Flag 0x01 //ѵ˿ںת +#define Dev_485_IrSend_Active_Flag 0x01 //˿ںת + +#define Dev_485_BLE_Music_Flag 0x00 //Ƶ + +#define Dev_Nor_Carbon_Flag 0x01 //̼ + +#define Dev_Nor_Scene_Restore_Flag 0x01 //滹ԭ + +#define Dev_Nor_GlobalSet_Flag 0x01 //ȫ,2025-07-14,YYW + +#endif /* BLV_485_DRIVER_INC_BLV_DEVICE_OPTION_H_ */ diff --git a/BLV_485_Driver/inc/blv_device_type.h b/BLV_485_Driver/inc/blv_device_type.h new file mode 100644 index 0000000..cf1376a --- /dev/null +++ b/BLV_485_Driver/inc/blv_device_type.h @@ -0,0 +1,92 @@ +/* + * blv_device_type.h + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_DEVICE_TYPE_H_ +#define BLV_485_DRIVER_INC_BLV_DEVICE_TYPE_H_ + +typedef enum +{ + Dev_Host_Invalid = 0, //0 - Ч豸 ҲԱΪdz + Dev_Host_HVout, //1 - ǿ̵ ״̬ + Dev_Host_LVinput, //2 - ״̬ + Dev_Host_LVoutput, //3 - ״̬ + Dev_Host_Service, //4 - Ϣ ״̬ + Dev_NodeCurtain, //5 - ɽڵ㴰 ״̬ + +/*485豸Ϳʼ*/ + DEV_RS485_SWT, //6 - ָʾ ״̬ ״̬ 485豸׵ַ + DEV_RS485_TEMP, //7 - յ1 յ״̬ + DEV_RS485_INFRARED, //8 - Ӧ + DEV_RS485_AirDetect, //9 - 豸 + DEV_RS485_CARD, //10 - 忨ȡ ȡ״̬ + DEV_RS485_HEATER, //11 - ů ů״̬ + Dev_RCU_NET, //12 - RCU豸 + DEV_RS485_CURTAIN, //13 - ״̬ + DEV_RS485_RELAY, //14 - ̵ ̵״̬ + DEV_RS485_IR_SEND, //15 - ⷢ ת״̬ + DEV_RS485_DIMMING, //16 - ֱ ״̬ + DEV_RS485_TRAIC, //17 - ɿع ɿع״̬ + DEV_RS485_STRIP, //18 - ƴ ƴ״̬ --2025-11-24 ȡ + DEV_RS485_CoreCtrl, //19 - п + DEV_RS485_WxLock, //20 - ΢ ΢״̬ 𹷵Ĭ0ַ + DEV_RS485_MUSIC, //21 - ״̬ +/*485豸ͽ*/ + DEV_NET_ROOMSTATE, //22 - ̬· + + Dev_Host_PWMLight, //23 - ص + DEV_RS485_PWM, //24 - 485PWM PWM״̬ + DEV_PB_LED, //25 - ߵ PBLED״̬ + DEV_RCU_POWER, //26 - RCUԴ + + DEV_RS485_A9_IO_SWT, //27 - A9IO أûЭ + DEV_RS485_A9_IO_EXP, //28 - A9IOչ չûЭ + DEV_RS485_A9_IO_POWER, //29 - A9IOԴ ԴûЭ + + DEV_RS485_RFGatewayCycle, //30 - ѯ ѯѯ豸 ·úѯ״̬ + DEV_RS485_RFGatewayHost, //31 - 豸 + + DEV_RS485_RFGatewayDoor, //32 - Ŵ + DEV_RS485_AirReveal, //33 - ʾ豸 + DEV_RS485_RFGatewayRelayPir, //34 - ߼̵ ڼ̵չ + + Dev_Host_TimeCtrl, //35 - ʱͬ + + Dev_Rs458_MonitorCtrl, //36 - ؿ + + Dev_Rs458_RotaryCtrl, //37 - ťؿ + + Dev_BUS_C5IO, //38 - C5IO - + + Dev_RS485_CardState, //39 - 忨״̬豸 + DEV_RS485_FreshAir, //40 - 485·豸 + DEV_RS485_FaceMach, //41 - 485 + DEV_Center_Control, //42 - п + DEV_Domain_Control, //43 - + DEV_RS485_LCD, //44 - LCD + DEV_Virtual_NoCard, //45 - ޿ϵ --2025-11-24 ȡ + DEV_Virtual_Card, //46 - ޿ȡ2 + + DEV_Virtual_Time, //47 - ʱ豸 + + Dev_Rs485_PB20 = 0x30, + Dev_Rs485_PB20_LD = 0x31, + Dev_Rs485_PB20_LS = 0x32, + Dev_Rs485_PB20_Relay = 0x33, + + DEV_Virtual_ColorTemp, //52 - ɫµڹ + + Dev_485_BLE_Music, //53 - Ƶ + DEV_Carbon_Saved, //54 - ̼ + Dev_Scene_Restore, //55 - ԭ + Dev_Virtual_GlobalSet, //56 - ȫ + + Dev_Energy_Monitor, //57 - ܺļ + + Dev_Num_MAX, //豸 +}Enum_Dev_Type; //豸ͼ + +#endif /* BLV_485_DRIVER_INC_BLV_DEVICE_TYPE_H_ */ diff --git a/BLV_485_Driver/inc/blv_nor_dec_virtualcard.h b/BLV_485_Driver/inc/blv_nor_dec_virtualcard.h new file mode 100644 index 0000000..ca4c8b9 --- /dev/null +++ b/BLV_485_Driver/inc/blv_nor_dec_virtualcard.h @@ -0,0 +1,144 @@ +/* + * blv_nor_dec_virtualcard.h + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_NOR_DEC_VIRTUALCARD_H_ +#define BLV_485_DRIVER_INC_BLV_NOR_DEC_VIRTUALCARD_H_ + +#define VC_CONDGROUP_MAX 10 //֧ +#define VC_CONDSUB_MAX 10 //ÿ֧ + +#define VIRTUAL_PORT_MAX 11 //˿ + +#define SOMEONE 1 // +#define NOONE 2 // + + + +#define VC_CONDGROUP_Default_StartGroup 0x01 // ĬʼΪ0x01 + +#define VC_CONDGROUP_SomeOne_Type 0x01 // +#define VC_CONDGROUP_NoOne_Type 0x02 +#define VC_CONDGROUP_BrieflyLeaving_Type 0x03 +#define VC_CONDGROUP_LongTermLeaving_Type 0x04 + +#define DETECTION_Window_Time_Max 43200 //ʱ䴰ڼʱ䣬λS + +//¼ID +#define VC_EventID_DoorSensor 0x01 //Ž¼߼ж-> +#define VC_EventID_CardedPersonLeft 0x02 //¼߼ж->ˣͬʱ +#define VC_EventID_UncardedPersonLeft 0x03 //޿¼߼ж->ˣ޿ +#define VC_EventID_RadarPersonDetected 0x04 //״¼ʱ߼жԱ +#define VC_EventID_RadarPersonLeft 0x05 //״¼ʱ߼ж +#define VC_EventID_RS485ButtonPress 0x06 //¼ڼ⵽RS485 д +#define VC_EventID_BrieflyLeaving 0x07 //¼߼ж->Уж +#define VC_EventID_LongTermLeaving 0x08 //¼߼ж->Уʱж + +//־λ +#define VC_Event_DoorSensor_Flag 0x01 //Ž¼߼ж-> +#define VC_Event_CardedPersonLeft_Flag 0x02 //¼߼ж->ˣͬʱ +#define VC_Event_UncardedPersonLeft_Flag 0x04 //޿¼߼ж->ˣ޿ +#define VC_Event_RadarPersonDetected_Flag 0x08 //״¼ʱ߼жԱ +#define VC_Event_RadarPersonLeft_Flag 0x10 //״¼ʱ߼ж +#define VC_Event_RS485ButtonPress_Flag 0x20 //¼ڼ⵽RS485 д +#define VC_Event_BrieflyLeaving_Flag 0x40 //¼߼ж->Уж +#define VC_Event_LongTermLeaving_Flag 0x80 //¼߼ж->Уʱж + + + +typedef struct +{ + uint8_t HPort_Type; //ӳ˿ + uint8_t HPort_Addr; //ӳ˿485ַ + uint16_t HPort_Loop; //ӳ˿ڻ· + + uint8_t PortIndex; //˿ں + uint8_t PortEnFlag; //·ͳñ +}VPORT_STRUCT; //˿Խṹ + +typedef struct +{ + uint8_t HPort_Type; //ӳ˿ + uint8_t HPort_Addr; //ӳ˿485ַ + uint16_t HPort_Loop; //ӳ˿ڻ· + + uint8_t Release_Thres; //ͷֵ -> + uint8_t PortIndex; //˿ں + uint8_t PortEnFlag; //·ʱ ñ + uint16_t Judgment_Time; //·ͳʱ + uint8_t Judgment_Unit; //·ͳʱ䵥λ + uint8_t Trigger_Thres; //ֵ -> +}VPORT_INFO_STRUCT; //˿Ϣṹ - ļд洢ݽṹ + +typedef struct +{ + uint8_t Exist_Flag; //˱ 1: 2: 3: 4:ʱ + uint8_t Condi_Gruop; // + uint8_t Condi_Subset; // + + uint16_t Judgment_Time; // - жʱ + uint8_t Judgment_Unit; // - жʱ䵥λ + + uint8_t Port_State[VIRTUAL_PORT_MAX]; //0:ж 1: 2:ͷ + + uint16_t Timeout_Time; // - жʱʱ + uint8_t Timeout_Unit; // - жʱʱ䵥λ + + uint8_t Trigger_Flag; // + + uint32_t Trigger_Tick; //ʱ + +}CONDITION_STRUCT; //ṹ + +typedef struct +{ + uint8_t Det1sTime; //1s⵱ǰ + uint8_t Det30sTime; //30s дһ־ + uint8_t TriggerNum[VIRTUAL_PORT_MAX]; //1sڴ + uint8_t FullFlag[VIRTUAL_PORT_MAX]; //ⴰ - ־λ + + uint8_t Trigger_Thres[VIRTUAL_PORT_MAX]; //ֵ -> + uint8_t Release_Thres[VIRTUAL_PORT_MAX]; //ͷֵ -> + uint16_t DetWinTotalNum[VIRTUAL_PORT_MAX]; //ʱ Ĭ12Сʱ(43200) λS + uint16_t DetWinTrigger[VIRTUAL_PORT_MAX]; //ʱ() + uint16_t DetWinIdex[VIRTUAL_PORT_MAX]; //± + +}DETECT_STRUCT; //89B + +typedef struct +{ + uint32_t PortTick; //˿ڼʱ 4 + uint8_t PortInit_Flag; //˿ӳ 1 + + VPORT_STRUCT Port_Info[VIRTUAL_PORT_MAX]; //ӳ˿ 77 + uint8_t PortState[VIRTUAL_PORT_MAX]; //˿״̬ 11 + uint8_t PortStateLast[VIRTUAL_PORT_MAX]; //һζ˿״̬ 11 + uint8_t PortStateAct[VIRTUAL_PORT_MAX]; //˿ڶ״̬ 11 ȶʹ + + uint32_t PortTiggleTick[VIRTUAL_PORT_MAX]; //˿ڼ¼㰴ʱ - A9IOط״̬ 44 + + DETECT_STRUCT DetInfo; //ʱϢ 102 + + float ActThreshold[VIRTUAL_PORT_MAX]; //ʵʴֵ 44 + + uint8_t ExistState; //˻״̬ + uint8_t ExistState_Last; + uint8_t ConGroupIndx; //ǰж± + uint8_t Action; // + uint8_t CardState; //п״̬ + uint8_t CardStateLast; // + uint8_t DetNum; //봰ڼ˿ + uint8_t Last_ConGroupType; //һ - ڲ롢ʱ ¼ + uint32_t Condition_Trigger_Tick; + + uint32_t Last_Trigger_Tick; //һʱ +}VIRTUALCARD_STRUCT; + + + +void BLV_Nor_Dev_VirtualCard_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); + +#endif /* BLV_485_DRIVER_INC_BLV_NOR_DEC_VIRTUALCARD_H_ */ diff --git a/BLV_485_Driver/inc/blv_nor_dev_hvoutfun.h b/BLV_485_Driver/inc/blv_nor_dev_hvoutfun.h new file mode 100644 index 0000000..5d5bba2 --- /dev/null +++ b/BLV_485_Driver/inc/blv_nor_dev_hvoutfun.h @@ -0,0 +1,55 @@ +/* + * blv_rs485_dev_hvoutfun.h + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_NOR_DEV_HVOUTFUN_H_ +#define BLV_485_DRIVER_INC_BLV_NOR_DEV_HVOUTFUN_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define HVoutNumMAX 32 //ǿ̵ +#define C1_HVOUTNUMMAX 0x18 //C1Ϊ20· + +#define HVout_State_Open 0x01 //ǿ̵״̬ - +#define HVout_State_Close 0x00 //ǿ̵״̬ - + +typedef struct +{ + uint8_t DevHVoutState[HVoutNumMAX]; //ǰǿ̵״̬ 豸״̬仯־жϵǰǿ̵Ǵ򿪻ǹر + uint8_t DevHVoutStateLast[HVoutNumMAX]; //ǰǿ̵һ״̬ + uint8_t DevHVoutSaveState[HVoutNumMAX]; //״̬ + + uint8_t A9Relay_ReadFlag; + + uint8_t HVoutLoopValidNum; //ǿ̵Ч· + uint8_t HVoutCtrlCnt; //Ƽ + + uint8_t HVSwitchFlag; //ǿ翪ر־ 1ǿ翪 0ͨ ü̵ӦĿأǿ翪 + uint8_t HVSwitchCtrlFlag; //ǿ翪ؿƱ־ ǿ翪طƱʱû״̬仯ô˱־ + + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ ռ4λ + uint8_t DevOffline; //豸߱־ 1豸 0豸 ռ2λ + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 ռ2λ + uint8_t RELAYSn; //չSn + + uint8_t init_flag; //ʼ־λ + uint32_t DevC5IOAddr; //C5IO豸ַ + uint32_t DevChangeFlag; //豸仯־ Ϊ1ʾ ־Ҫ + + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + +}NOR_HVOUT_INFO; //ǿ̵Ľṹ + +void BLV_Nor_Dev_HVout_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +uint16_t HVout_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop); +void BLW_HVout_Control_State(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t devaddr,uint16_t DevOutputLoop,uint16_t start); +void BLW_HVout_Group_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr,uint32_t devaddr, uint32_t CtrlFlag, uint8_t CtrlNum,uint16_t *start); +uint16_t BLW_HVout_Group_Read(uint32_t devaddr, uint8_t SceneType, uint32_t ReadFlag, uint8_t ReadNum,uint16_t *start); +uint8_t Get_BLV485_Expand_Online_Status(uint32_t devaddr); + +#endif /* BLV_485_DRIVER_INC_BLV_NOR_DEV_HVOUTFUN_H_ */ diff --git a/BLV_485_Driver/inc/blv_nor_dev_lvinput.h b/BLV_485_Driver/inc/blv_nor_dev_lvinput.h new file mode 100644 index 0000000..813f3a3 --- /dev/null +++ b/BLV_485_Driver/inc/blv_nor_dev_lvinput.h @@ -0,0 +1,102 @@ +/* + * blv_nor_dev_lvinput.h + * + * Created on: Nov 17, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_NOR_DEV_LVINPUT_H_ +#define BLV_485_DRIVER_INC_BLV_NOR_DEV_LVINPUT_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define LVINPUTNUMMAX 20 // +#define C1_LVINPUTNUMMAX 0x07 //C1Ϊ7· + +typedef struct{ + uint64_t LVinputCH01:2; //1 + uint64_t LVinputCH02:2; //2 + uint64_t LVinputCH03:2; //3 + uint64_t LVinputCH04:2; //4 + uint64_t LVinputCH05:2; //5 + uint64_t LVinputCH06:2; //6 + uint64_t LVinputCH07:2; //7 + uint64_t LVinputCH08:2; //8 + uint64_t LVinputCH09:2; //9 + uint64_t LVinputCH10:2; //10 + uint64_t LVinputCH11:2; //11 + uint64_t LVinputCH12:2; //12 + uint64_t LVinputCH13:2; //13 + uint64_t LVinputCH14:2; //14 + uint64_t LVinputCH15:2; //15 + + uint64_t LVinputCH16:2; //16 //·ڿ + uint64_t LVinputCH17:2; //17 + uint64_t LVinputCH18:2; //18 + uint64_t LVinputCH19:2; //19 + uint64_t LVinputCH20:2; //20 + uint64_t LVinputCH21:2; //21 + uint64_t LVinputCH22:2; //22 + uint64_t LVinputCH23:2; //23 + uint64_t LVinputCH24:2; //24 + uint64_t LVinputCH25:2; //25 + uint64_t LVinputCH26:2; //26 + uint64_t LVinputCH27:2; //27 + uint64_t LVinputCH28:2; //28 + uint64_t LVinputCH29:2; //29 + uint64_t LVinputCH30:2; //30 + uint64_t LVinputCH31:2; //31 + uint64_t LVinputCH32:2; //32 + +}DEV_LVINPUTDATA_TYPE; //Ϣ + +#define INCH6_DI_CH_MAX 0x06 + +typedef struct +{ + uint8_t DevReadBuf[LVINPUTNUMMAX]; //ÿλ水״̬ ⣬ + uint8_t DevReadBufLast[LVINPUTNUMMAX]; //ÿλ水״̬ ڽȽ + + uint8_t LVinputValidNum; //Ч· + uint8_t DevSendCnt; //ͼ + uint8_t DevOffline; // 1豸 0豸 + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 ռ2λ + uint8_t DevSn; //豸Sn + uint8_t Dev_Init_Flag; //豸ʼ־λ 2025-09-26 + + uint8_t Send_Type; + + uint8_t DI_Type[INCH6_DI_CH_MAX]; //DI 0~3: 4~7:ƽ + uint8_t DI_Start[INCH6_DI_CH_MAX]; //DI״̬ + uint8_t DI_Report_En[INCH6_DI_CH_MAX]; //DIϱʹ + uint8_t DI_LastStart[INCH6_DI_CH_MAX]; + uint8_t DI_Detection_Time[INCH6_DI_CH_MAX]; //DIʱ + + uint16_t Version; //IO汾 + uint16_t control_flag; //Ʊ־λ + uint16_t DI_set_flag; //DIñ־λ + uint16_t Last_DI_set_flag; + uint16_t DI_Level_Actual_Start; + + uint32_t DevC5IOAddr; //C5IO豸ַ + uint32_t DI_Actual_State; + uint32_t DI_Perfect_State; + + // ֧30· + uint32_t inquire_tick; //ѯʱ + uint32_t HoldTick[LVINPUTNUMMAX]; + + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + +}NOR_LVINPUT_INFO; //ϢĽṹ + +void BLV_Nor_Dev_LVinput_Init(uint8_t devaddr, uint16_t LoopMax); +uint8_t Dev_LVinput_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType); +void Dev_LVinput_Dis(uint32_t DevAddr); + + + + +#endif /* BLV_485_DRIVER_INC_BLV_NOR_DEV_LVINPUT_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_c12dimming.h b/BLV_485_Driver/inc/blv_rs485_dev_c12dimming.h new file mode 100644 index 0000000..ed2677b --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_c12dimming.h @@ -0,0 +1,29 @@ +/* + * blv_rs485_dev_c12dimming.h + * + * Created on: Nov 17, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_C12DIMMING_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_C12DIMMING_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" +#include "blv_rs485_dev_ledcrtl.h" + +#define C12DIM_OUT_CH_MAX 0x0C //C12Dim12· + +#define C12_SET_LIGHT_CMD 0x21 //ٷֱ趨 + +void BLW_RS485_C12Dim_Data_Init(Device_Public_Information_G *BUS_Public, RS485_LED_INFO *Rs485LED, uint16_t LoopNum); +uint8_t BLW_C12DimCycleCtrl(uint32_t dev_addr); +uint8_t BLW_Rs485_C12Dim_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len); +void BLW_Rs485_C12Dim_Ctrl(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo); +void BLW_Rs485_C12Dim_Way_Ctrl(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo); +void BLW_Rs485_C12Dim_Read(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo); +void BLW_C12_GlobalValue_Set(Device_Public_Information_G *BUS_Public, RS485_LED_INFO* Rs485LEDInfo); + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_C12DIMMING_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_cardctrl.h b/BLV_485_Driver/inc/blv_rs485_dev_cardctrl.h new file mode 100644 index 0000000..70ca4b9 --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_cardctrl.h @@ -0,0 +1,56 @@ +/* + * blv_rs485_dev_cardctrl.h + * + * Created on: Nov 14, 2025 + * Author: cc + */ +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_CARDCTRL_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_CARDCTRL_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define CARD_Anonymous_Identity 0x00 //Ϣ +#define CARD_Guest_Identity 0x01 // +#define CARD_Staff_Identity 0x02 //Ա +#define CARD_Identity_3 0x03 //3 +#define CARD_Identity_4 0x04 //4 +#define CARD_Identity_5 0x05 //5 + +typedef struct +{ + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ + uint8_t DevOffline; //豸߱־ 1豸 0豸 + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 + + uint8_t Rs485CardAction; // + uint8_t Rs485CardFlag; //忨ȡ־ + uint8_t Rs485CardFlagLast; //һβ忨ȡ־λ + uint8_t Rs485CardTypeLast; //һ״̬ + uint8_t Rs485CardType; //״̬ + + uint8_t DevPort; //2024-11-05 + uint8_t DevPort_Last; //2024-11-05 + uint8_t DevPort_Flag; //2024-11-05 + + uint8_t DevInitFlag; //2025-08-04 ԵһͨѶĶȡ״̬Ϊʼ״̬Ҳִж + + uint32_t inquire_tick; //ѯʱ + + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + +}RS485_CARD_INFO; + + +void BLV_RS485_Card_Active_Init(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo); +void BLV_RS485_Card_Polling_Init(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo); +void BLV_RS485_Card_Data_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +void BLV_RS485_Card_Polling_Send(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo); +void BLV_RS485_Card_PortType_Send(Device_Public_Information_G *BUS_Public, RS485_CARD_INFO *Rs485CardInfo); +uint8_t BLV_RS485_Card_Cycle_Dis(uint32_t dev_addr); +uint8_t BLV_Rs485_Card_Check(uint32_t dev_addr,uint32_t data_addr,uint16_t len); +uint8_t Get_BLV485_CARD_Online_Status(uint32_t devaddr); +uint8_t Dev_Rs485_Card_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType); + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_CARDCTRL_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_ledcrtl.h b/BLV_485_Driver/inc/blv_rs485_dev_ledcrtl.h new file mode 100644 index 0000000..cee8419 --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_ledcrtl.h @@ -0,0 +1,158 @@ +/* + * blv_rs485_dev_ledcrtl.h + * + * Created on: Nov 17, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_LEDCRTL_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_LEDCRTL_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define CFG_Dev_CtrlWay_Is_Open 0x01 //豸ִзʽΪ +#define CFG_Dev_CtrlWay_Is_Close 0x02 //豸ִзʽΪ +#define CFG_Dev_CtrlWay_Is_TOGGLE 0x04 //豸ִзʽΪȡ + +#define CFG_Dev_CtrlWay_Is_Dim_CycleUp 0x07 //ѭ +#define CFG_Dev_CtrlWay_Is_Dim_CycleDown 0x08 //ѭ +#define CFG_Dev_CtrlWay_Is_Dim_Stop 0x09 //ֹͣ +#define CFG_Dev_CtrlWay_Is_Dim_Up 0x0A //ϵ +#define CFG_Dev_CtrlWay_Is_Dim_Down 0x0B //µ +#define CFG_Dev_CtrlWay_Is_Dim_Open 0x0C //㰴 +#define CFG_Dev_CtrlWay_Is_Dim_Close 0x0D //㰴ر +#define CFG_Dev_CtrlWay_Is_RelateBlink 0x0E //豸ִзʽΪӦ˸ רɽڵ485 +#define CFG_Dev_CtrlWay_Is_Dim_Up_Step_Cycle 0x0F //ϵ㰴ѭ + +#define CFG_Dev_CtrlWay_Is_OnlySwitch 0x11 //ֻؿ +#define CFG_Dev_CtrlWay_Is_OnlyBright 0x12 //ֻ + +#define CFG_Dev_CtrlWay_Is_Dim_Up_Limit 0x1A //Ψĵ ϵ +#define CFG_Dev_CtrlWay_Is_Dim_Down_Limit 0x1B //Ψĵ µ +#define CFG_Dev_CtrlWay_Is_Dim_Up_Step_Cycle_Limit 0x1F //Ψĵ ϵ㰴ѭ + +#define CFG_Dev_CtrlWay_Is_PWM_Set_Time 0x20 //PWM⽥ʱ +#define CFG_Dev_CtrlWay_Is_A9LD_Set_Time 0x21 //A9LD⽥ʱ +#define CFG_Dev_CtrlWay_Is_A8PB_Set_Time 0x22 //A8PB⽥ʱ +#define CFG_Dev_CtrlWay_Is_C12_Set_Time 0x23 //C12⽥ʱ +#define CFG_Dev_CtrlWay_Is_RGB_Set_Time 0x24 //RGB⽥ʱ + +#define Dim_Global_Value_Cmd 0x30 //ȫ +#define Dim_UpLimit_Value_Cmd 0x31 //ȫֿɵ +#define Dim_DnLimit_Value_Cmd 0x32 //ȫֿɵ + +typedef enum{ + LED_OUT_CH01, + LED_OUT_CH02, + LED_OUT_CH03, + LED_OUT_CH04, + LED_OUT_CH05, + LED_OUT_CH06, + LED_OUT_CH07, + LED_OUT_CH08, + LED_OUT_CH09, + LED_OUT_CH10, + LED_OUT_CH11, + LED_OUT_CH12, + LED_OUT_CH13, + LED_OUT_CH14, + LED_OUT_CH15, + LED_OUT_CH16, + LED_OUT_CH17, + LED_OUT_CH18, + LED_OUT_CH19, + LED_OUT_CH20, + LED_OUT_CH21, + LED_OUT_CH22, + LED_OUT_CH23, + LED_OUT_CH24, + LED_OUT_CH25, + LED_OUT_CH26, + LED_OUT_CH27, + LED_OUT_CH28, + LED_OUT_CH29, + LED_OUT_CH30, + LED_OUT_CH31, + LED_OUT_CH32, + LED_OUT_CH_MAX, +}RS485_LED_OUT_NUM_E; + +#define LED_BUFF_Size LED_OUT_CH_MAX //· + + +typedef struct +{ + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + + uint8_t DevSendBuf[LED_BUFF_Size]; //飬洢л·״̬ + uint8_t DevSendBuf_last[LED_BUFF_Size]; //飬洢л·һ״̬ + uint8_t DevSendBufNext[LED_BUFF_Size]; //޸Ϊȫʹ + + uint8_t DevSaveBuf[LED_BUFF_Size]; + + uint8_t DevReadBuf[LED_BUFF_Size]; //·״̬仯Ʊ־ + uint8_t DevRecBuf[LED_BUFF_Size]; //յ· + uint8_t DevRecBufLast[LED_BUFF_Size]; //յ·һ + + uint8_t LEDSn; //λʾSn + + uint8_t WayCtrli; //ʽƵ± + + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ ռ4λ + uint8_t DevOffline; //豸߱־ 1豸 0豸 ռ2λ + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 ռ2λ + + uint8_t LEDUpLightLimit; // + uint8_t LEDUpLightLimitLast; // + uint8_t LEDDownLightLimit; // + uint8_t LEDDownLightLimitLast; // + uint8_t Dim_Global_Value; //ȫ + uint8_t Dim_Global_Value_Last; //ϴȫ + uint8_t Dim_GV_Flag; //ȫñ + + uint8_t PWM_Set_Time; + uint8_t A9LD_Set_Time; + uint8_t A8PB_Set_Time; + uint8_t C12_Set_Time; + uint8_t RGB_Set_Time; + + uint8_t LEDCtrlCnt; //ȿƼ + uint8_t LEDLoopValidNum; //Ч· + + uint8_t LEDLightRelease[LED_BUFF_Size]; //ɿȱ + uint8_t LedUpDown[LED_BUFF_Size]; //ѭⷽ + + uint8_t LEDLightnessReadFlag; //ȶȡ־ + uint8_t LEDLightnessReadCnt; //ȶȡ־ + + uint8_t LEDCycleStep; //״̬ + + uint8_t DevCtrlWayBuf[LED_BUFF_Size]; //Ʒʽ + uint8_t DevCtrlWayBuf_last[LED_BUFF_Size]; //ⷽʽһ״̬ + uint8_t DevCtrlWayContect[LED_BUFF_Size]; //ⷽʽ + + uint8_t LEDWayCtrlCnt; //ⷽʽƼ + + uint8_t init_flag; //ʼ־λ + + uint16_t LEDCtrlFlag; //ȿƱ־ + uint16_t LEDWayCtrlFlag; //ⷽʽƱ־ + uint32_t inquire_tick; //ѯʱ + +}RS485_LED_INFO; //485¿뺯 + +void BLW_RS485_LED_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +void BLW_LED_Control_State(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t devaddr,uint16_t loop,uint16_t start); +uint16_t BLW_LED_Read_State(uint32_t devaddr,uint16_t loop); +uint8_t Get_BLV485_LED_Online_Status(uint32_t devaddr); +void BLW_LED_Group_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr,uint32_t devaddr, uint32_t CtrlFlag, uint8_t CtrlNum,uint16_t *start); +uint16_t BLW_LED_Group_Read(uint32_t devaddr, uint8_t SceneType, uint32_t ReadFlag, uint8_t ReadNum,uint16_t *start); + + + + + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_LEDCRTL_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_switchctrl.h b/BLV_485_Driver/inc/blv_rs485_dev_switchctrl.h new file mode 100644 index 0000000..85a27bd --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_switchctrl.h @@ -0,0 +1,127 @@ +/* + * blv_rs485_dev_switchctrl.h + * + * Created on: Nov 12, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_SWITCHCTRL_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_SWITCHCTRL_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define Key_BUFF_Size 32 +#define KeyHoldJudgeTime 400 +#define SWI_KEY_LONG_PERIOD 200 +#define SWIOUTUPEXIST 0x00 //طϱ־ + +typedef enum{ + RS_SWITCH_CH1 = 0x00, + RS_SWITCH_CH2, + RS_SWITCH_CH3, + RS_SWITCH_CH4, + RS_SWITCH_CH5, + RS_SWITCH_CH6, + RS_SWITCH_CH7, + RS_SWITCH_CH8, + RS_SWITCH_CH9, + RS_SWITCH_CH10, + RS_SWITCH_CH11, + RS_SWITCH_CH12, + RS_SWITCH_CH13, + RS_SWITCH_CH14, + RS_SWITCH_CH15, + RS_SWITCH_CH16, + RS_SWITCH_CH17, + RS_SWITCH_CH18, + RS_SWITCH_CH19, + RS_SWITCH_CH20, + RS_SWITCH_CH21, + RS_SWITCH_CH22, + RS_SWITCH_CH23, + RS_SWITCH_CH24, + RS_SWITCH_CH25, + RS_SWITCH_CH26, + RS_SWITCH_CH27, + RS_SWITCH_CH28, + RS_SWITCH_CH29, + RS_SWITCH_CH30, + RS_SWITCH_CH_MAX, +}RS485_SWITCH_NUM_E; + +typedef enum +{ + KeyNoAction = 0x00, //޶ + KeyPress = 0x01, // ̰ + KeyRelease = 0x02, //ɿ ͷ + KeyHold = 0x03, // + RotaryLight = 0x04, //ת + RotaryVol = 0x05, //ת + RotaryTemp = 0x06, //ת¶ + RotaryCCT = 0x07, //תɫ + RotaryOther = 0x08, //ת +}keyState_Typedef; //밴״̬ö + +typedef struct +{ + uint8_t DevReadBuf[Key_BUFF_Size]; //飬ÿֽڴ水״̬ + uint8_t DevReadBuf_last[Key_BUFF_Size]; //飬ÿֽڴ水״̬ + + uint8_t DevSendBuf[Key_BUFF_Size]; //飬ÿֽڴָʾƵ״̬ + uint8_t DevSendBuf_last[Key_BUFF_Size]; //飬ÿֽڴָʾƵһ״̬ + + uint8_t A9IORepeatFlag; //A9IOط־ûнյֵʱط־һSnŲӡյֵʱط־0Sn + + uint8_t SwtInputValidNum; //Ч + uint8_t SwtOutputValidNum; //Ч + + uint8_t SwtRelayLedCtrlFlag; //ָʾƿƱ־ + uint8_t SwtRelayLedCtrlCnt; //ָʾƿƼ + + uint8_t KeyCntChangFlag; //仯 + uint8_t SwtCycleStep; //ؿ״̬ÿؿƿ + + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ + uint8_t DevOffline; //豸߱־ 1豸 0豸 + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 + + uint8_t SwitchSn; //Sn + + uint8_t MultiValidNo[Key_BUFF_Size]; //Ч 2024-05-23 + uint8_t MultiNumber[Key_BUFF_Size]; //صǰִ± 2024-05-23 + + uint8_t RotaryValue_Flag; //ťֵ仯 + uint8_t RotaryBL; //ť״̬ + uint8_t RotaryBL_Last; //ťϴ״̬ + uint8_t RotaryBL_Flag; //ť仯 + uint8_t RotaryCCTValue_Flag; //ťɫֵ仯,2025-07-10,YYW + + uint8_t RL_Upper_limit; //ȵ + uint8_t RL_Upper_limit_Last; //ȵ + uint8_t RL_Lower_limit; //ȵ + uint8_t RL_Lower_limit_Last; //ȵ + + uint8_t RL_Limit_Flag; + uint8_t Rotary_PageFlag; //ťҳ÷ͱ + + uint16_t RotaryValue[5]; //ťϱֵ + + uint32_t Rotary_PageEn; //ťҳñ + uint32_t Rotary_PageEnLast; + uint32_t KeyBitValue; //λֵ 32λԱʾ32ӵλʼ洢 OCYأ1ʾг 0ʾ޳ + + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + +}RS485_SWI_INFO; //485ص뺯 + +void BLW_RS485_Switch_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +uint8_t Get_Switch_Online_Status(uint32_t devaddr); +uint8_t Dev_Swi_InType_Get(uint32_t DevAddr, uint16_t DevInputLoop, uint16_t DevInputType); +void Dev_Swi_Output_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t DevAddr, uint16_t DevOutputLoop, uint16_t DevOutputType); +uint16_t Dev_Swi_Loop_State(uint32_t devaddr, uint16_t DevOutputLoop); + + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_SWITCHCTRL_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_tempctrl.h b/BLV_485_Driver/inc/blv_rs485_dev_tempctrl.h new file mode 100644 index 0000000..8019646 --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_tempctrl.h @@ -0,0 +1,175 @@ +/* + * blv_rs485_dev_tempfun.h + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_TEMPCTRL_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_TEMPCTRL_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" + +#define TMEP_TYPE_IR 0 //¿ԶٲƼ̵ +#define TEMP_TYPE_VALVE 1 //ŷ¿ԶٻƼ̵ + +#define TEM_DecTem 15 //¶ +#define TEM_AddTem 33 //¶ +#define TEM_DecFan 14 //ٷ +#define TEM_AddFan 34 //ӷ + +#define TEM_MIN_SET 0x10 //¶ +#define TEM_MAX_SET 0x20 //¶ + +#define TEMP_ONOFF_CTRL_MAX 0x03 //¿ط + +#define TEMP_VALVE_OPEN 0x01 // +#define TEMP_VALVE_CLOSE 0x00 // + +#define TEMP_ON 0x01 //յ +#define TEMP_OFF 0x02 //յػ + +#define TEMP_STATE_ON 0x01 //յ״̬ +#define TEMP_STATE_OFF 0x00 //յ״̬ػ + +#define TEMP_HIGH 0x03 // +#define TEMP_MID 0x02 // +#define TEMP_LOW 0x01 // +#define TEMP_FANAUTO 0x00 //Զ + +#define TEMP_COLD 0x01 //յ +#define TEMP_HOT 0x02 //յ +#define TEMP_WIND 0x03 //յͷ +#define TEMP_MODEAUTO 0x00 //յģʽԶ ԶΨȥƿյʱ Ŵ ϱյ״̬ûԶ + +#define TEMTEMPCONVER(data) ((0x00 == data)?TEM_MAX_SET:data) //¿¶תΪ032 + +typedef struct +{ + uint8_t indoor_t ; //¶ + uint8_t set_t ; //¶ + uint8_t valve ; // 1 0 + uint8_t fan ; // 1,2,3,0ֹͣ,4Զ + uint8_t mode ; // 1,2,3ͷ,0Զ + uint8_t on_off ; // 1,2 +}TemState_Struct; + +typedef struct +{ + uint8_t IndoorFlag:1; //¶жϱ־ + uint8_t SetTFlag:1; //¶жϱ־ + uint8_t ValveFlag:1; //жϱ־ + uint8_t FanFlag:1; //жϱ־ + uint8_t ModeFlag:1; //ģʽжϱ־ + uint8_t OnOffFlag:1; //ػжϱ־ + + uint8_t IndoorState:1; //¶״̬ + uint8_t SetTState:1; //¶״̬ + uint8_t HValveFlag:1; //ȷжϱ־ + uint8_t HValveState:1; //ȷ״̬ + uint8_t ValveState:1; //״̬ + uint8_t FanState:2; //״̬ + uint8_t ModeState:2; //ģʽ״̬ + uint8_t OnOffState:1; //ػ״̬ + +}TemCond_Struct; //һжʱҪ״̬һж ǵһжʱֻжϱ־λ + +typedef struct +{ + uint8_t TemIndoorCtrlVar ; //¶ȿƱ־ + uint8_t TemSetTCtrlVar ; //¶ȿƱ־ + uint8_t TemValveCtrlVar ; //ſƱ־ + uint8_t TemFanCtrlVar ; //ٿƱ־ + uint8_t TemModeCtrlVar ; //ģʽƱ־ + uint8_t TemOnOffCtrlVar ; //ػƱ־ +}TemStateCtrlVar_Struct; + +typedef struct +{ + BLV_COMM_RECORD_G comm_record; //ͨѶ¼ + + TemState_Struct TemState; + + TemState_Struct TemStateCtrl; //ҪƵ״̬ + TemState_Struct TemStateCtrlLast; //ҪƵһ״̬ + + TemStateCtrlVar_Struct TemStateCtrlFlag; //¿Ʊ־ + TemStateCtrlVar_Struct TemStateCtrlCnt; //¿Ƽ + + TemCond_Struct TemCondCfg; //ò 6λһΪ1ʱʾһ 6λ2Ϊ1ʱΪǵһ + TemCond_Struct TemCondRec; //¿ղ 6λΪĶ 10λΪ + + uint8_t FanAutoRelay; //Զʱ̵״̬ + uint8_t FanAutoFlag; //Ϊ0Զ٣Ϊ1ЭԶ + uint8_t relay_out; //0λ 1λ 2λ 3λȷ 4λ䷧ + uint8_t ValveSameFlag; //ȷһΪ1 һΪ2 //2023-04-17 + + uint8_t control_start; //ؿػ״̬ + + TemState_Struct TemStateVir; //¿״̬仯Ƚ δ + TemState_Struct TemStateLast; //¿һ״̬ ״̬仯ϱ + + TemState_Struct TemKeepState; + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ ռ4λ + uint8_t DevOffline; //豸߱־ 1豸 0豸 ռ2λ + uint8_t DevOfflineLast; //豸߱־ 1豸 0豸 ռ2λ + + uint8_t TemCycleCnt; //¿ѯLF¿ѯר + + uint8_t TemDataChangeFlag; //¿ݸı־ + uint8_t TempType; //¿ͣĬΪ¿м̵ڣǵŷ¿0Ϊ¿1Ϊŷ¿ + + uint8_t TempComSetFlag; //¿²ñ־ʼΪ1C43ʱһ² + uint8_t TempComSetCnt; //¿²ü + + uint8_t CardEn; //2023-12-26 忨״̬ͬ/ + + uint8_t CardFlag; //2023-12-26 忨״̬ͬñ + uint8_t CardCnt; //2023-12-26 忨״̬ͬ + uint8_t ValveNoExist; //2024-06-27 ˮ޷ + + uint8_t DevPort; //2024-11-05 + uint8_t DevPort_Last; //2024-11-05 + uint8_t DevPort_Flag; //2024-11-05 + + uint8_t inif_flag; //2025-08-21 ʼ־λ + + uint8_t Carbon_Set_Temp; //2025-10-13 ̼ʹ + uint8_t udp_flag; //2025-10-13 ϱ־λ + uint32_t udp_tick; //2025-10-13 + uint32_t inquire_tick; //ѯʱ + +}RS485_TEMP_INFO; //485¿뺯 + +typedef struct +{ + TemState_Struct TemState; // + uint8_t FanAutoRelay; //Զʱ̵״̬ +}RS485_TEMP_BASIC; //485¿ + + +typedef void (*RS485_Tem_CycleCtrl_ptr)(Device_Public_Information_G *BUS_Public); //ѯָ +typedef void (*RS485_Tem_Ctrl_ptr)(Device_Public_Information_G *BUS_Public,RS485_TEMP_INFO *Rs485Tem, uint8_t CtrlWay); //ƺָ + +void BLW_RS485_TempFun_For_Logic_Init(LOGICFILE_DEVICE_INFO *dev_info,uint8_t *data,uint16_t data_len); +void Dev_Temp_State_Sync(TemState_Struct *temp,TemState_Struct *sync_temp); +uint16_t Dev_Temp_State_Data(TemState_Struct temp); +uint8_t Dev_TEMPCTRL_InType_Get(uint32_t CfgDevAddIn, uint16_t DevInputLoop, uint16_t DevInputType); +void Dev_TEMPCTRL_Ctrl(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t CfgDevAddOut, uint16_t DevOutputLoop, uint16_t DevOutputType); +uint8_t Get_BLV485_TEMP_Online_Status(uint32_t devaddr); +uint16_t Get_BLV485_TEMP_Status(uint32_t devaddr,uint16_t loop); + +uint8_t TemSingleJudge(uint32_t CfgDevAdd, RS485_Tem_Ctrl_ptr Rs485TemCtrl, RS485_Tem_CycleCtrl_ptr Rs485TemCycle); +uint8_t TemGlobalJudge(uint32_t CfgDevAdd, RS485_Tem_Ctrl_ptr Rs485TemCtrl, RS485_Tem_CycleCtrl_ptr Rs485TemCycle); +void Temp_Action_Set(RS485_TEMP_BASIC *Rs485TemRecBuf, RS485_TEMP_INFO *Rs485Tem); +void Temp_Action_Set(RS485_TEMP_BASIC *Rs485TemRecBuf, RS485_TEMP_INFO *Rs485Tem); + + + + + + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_TEMPCTRL_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_touchswitch.h b/BLV_485_Driver/inc/blv_rs485_dev_touchswitch.h new file mode 100644 index 0000000..945ec9a --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_touchswitch.h @@ -0,0 +1,27 @@ +/* + * blv_rs485_dev_touchswitch.h + * + * Created on: Nov 13, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHSWITCH_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHSWITCH_H_ + +#include +#include "blv_rs485_protocol.h" +#include "logic_file_function.h" +#include "blv_rs485_dev_switchctrl.h" + +void BLV_485_Dev_Touch_Switch_Init(Device_Public_Information_G *BUS_Public, RS485_SWI_INFO *Rs485SwiInfo); +void BlwRelaySwtRecAsk(uint8_t *data); +void BlwTouchSwtRecAsk(uint32_t DevAdd, uint8_t *data, uint16_t DataLen); +void BLW_Touch_Rs485_Swi_Pro(Device_Public_Information_G* BUS_Public, uint8_t *data, RS485_SWI_INFO *Switch_Info, uint8_t lens); +uint8_t BLW_Rs485_Touch_Swi_Check(uint32_t DevAdd ,uint32_t Data_addr, uint16_t DataLen); +void BLW_Touch_Switch_ctrl(Device_Public_Information_G *BUS_Public, RS485_SWI_INFO *Rs485SwiInfo); +uint8_t BLW_Touch_SwitchCycleDis(uint32_t DevAdd); + + + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHSWITCH_H_ */ diff --git a/BLV_485_Driver/inc/blv_rs485_dev_touchtempt1.h b/BLV_485_Driver/inc/blv_rs485_dev_touchtempt1.h new file mode 100644 index 0000000..998f1e6 --- /dev/null +++ b/BLV_485_Driver/inc/blv_rs485_dev_touchtempt1.h @@ -0,0 +1,24 @@ +/* + * blv_rs485_dev_touchtempt1.h + * + * Created on: Nov 14, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHTEMPT1_H_ +#define BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHTEMPT1_H_ + +#include +#include "blv_rs485_protocol.h" +#include "blv_rs485_dev_tempctrl.h" + +void BLWOut_RS485_TempT1_Data_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1); +void BLWOut_RS485_TempT1D_Data_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1); +void BLWOut_RS485_TempT1_Activ_Init(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485TempT1); + +void BLWOut_tempT1CardCtrl(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485Tem); +void BLV_T1Temp_PortSet_Send(Device_Public_Information_G *BUS_Public, RS485_TEMP_INFO *Rs485Tem); + + + +#endif /* BLV_485_DRIVER_INC_BLV_RS485_DEV_TOUCHTEMPT1_H_ */ diff --git a/BLV_485_Driver/inc/pc_devicetest_fun.h b/BLV_485_Driver/inc/pc_devicetest_fun.h new file mode 100644 index 0000000..1e76e4b --- /dev/null +++ b/BLV_485_Driver/inc/pc_devicetest_fun.h @@ -0,0 +1,114 @@ +/* + * pc_devicetest_fun.h + * + * Created on: Nov 10, 2025 + * Author: cc + */ + +#ifndef BLV_485_DRIVER_INC_PC_DEVICETEST_FUN_H_ +#define BLV_485_DRIVER_INC_PC_DEVICETEST_FUN_H_ + +#include + +#define PCTESTTYPE 0xF2 //豸Э - 豸ֻͨѶЭʹ +#define DEV_PCTEST_TYPE 0xF2 //豸бе豸 +#define DEV_PCTEST_Addr 0xFC //豸бе豸ַ + +#define BLV_PC_TEST_SearchMCU_CMD 0x01 // +#define BLV_PC_TEST_SyncTime_CMD 0x02 //ͬʱ +#define BLV_PC_TEST_QueryTime_CMD 0x03 //ѯʱ +#define BLV_PC_TEST_ConfigInfo_CMD 0x04 //Ϣ· - ·豸Ϣ +#define BLV_PC_TEST_ReadRegister_CMD 0x05 //ȡӳĴ +#define BLV_PC_TEST_WriteRegister_CMD 0x06 //дӳĴ +#define BLV_PC_TEST_StartTesting_CMD 0x07 //豸 +#define BLV_PC_TEST_SetBaud_CMD 0x08 //PC˿ڽ +#define BLV_PC_SET_DEBUG_CMD 0x09 //ô0 - DebugϢ +#define BLV_PC_TEST_GPIO_CMD 0x0A //GPIO +#define BLV_PC_SET_MCU_Revision_CMD 0x0B //MCU汾űFlash +#define BLV_PC_READ_MCU_Revision_CMD 0x0C //ȡMCU汾 +#define BLV_PC_SET_MQTT_CMD 0x0D //MQTT +#define BLV_PC_READ_MQTT_CMD 0x0E //ȡMQTT +#define BLV_PC_CORE_TEST_CMD 0x0F //ģ +#define BLV_PC_READ_RCU_Data_CMD 0x10 //ȡRCU - 2022-06-06 +#define BLV_PC_READ_Device_Data_CMD 0x21 //ȡ豸Ϣ +#define BLV_PC_READ_RCU_VERSION_CMD 0x22 //ȡ汾Ϣ̼laucherã + +#define BLV_PC_TEST_SearchMCU_Relay 0x11 //ظ +#define BLV_PC_TEST_SyncTime_Relay 0x12 //ظͬʱ +#define BLV_PC_TEST_QueryTime_Relay 0x13 //ظѯʱ +#define BLV_PC_TEST_ConfigInfo_Relay 0x14 //ظϢ· - ·豸Ϣ +#define BLV_PC_TEST_ReadRegister_Relay 0x15 //ظȡӳĴ +#define BLV_PC_TEST_WriteRegister_Relay 0x16 //ظдӳĴ +#define BLV_PC_TEST_StartTesting_Relay 0x17 //ظ豸 +#define BLV_PC_TEST_SetBaud_Relay 0x18 //ظPC˿ڲʣģʽ+ +#define BLV_PC_SET_DEBUG_Relay 0x19 //ô0 - DebugϢ +#define BLV_PC_TEST_GPIO_Relay 0x1A //GPIO +#define BLV_PC_SET_MCU_Revision_Relay 0x1B //MCU汾űFlash +#define BLV_PC_READ_MCU_Revision_Relay 0x1C //ȡMCU汾 +#define BLV_PC_SET_MQTT_Relay 0x1D //MQTTظ +#define BLV_PC_READ_MQTT_Relay 0x1E //ȡMQTTظ +#define BLV_PC_CORE_TEST_Relay 0x1F //ģԻظ +#define BLV_PC_READ_RCU_Data_Relay 0x20 //ȡRCUݻظ - 2022-06-06 +#define BLV_PC_READ_Device_Data_Relay 0x31 //ȡ豸Ϣظ - 2024-05-22 +#define BLV_PC_READ_RCU_VERSION_Relay 0x32 //ȡ汾Ϣ̼laucherã - 2025-07-05 + +typedef struct{ + + uint8_t DevSendSN; //SN + uint8_t link_port; //PC Ӷ˿ + uint8_t link_flag; //PC ӱ־λ + uint8_t test_flag; //PC Ա־λ - 0x01ԣ0x02,0x03Ѳز + uint8_t test_dev; //PC 豸 + uint8_t test_addr; //PC 豸ַ + + uint8_t tour_num; //Ѳش + uint8_t tour_succ; //Ѳسɹ + + uint8_t pc_ip[4]; //PCIPַ + uint16_t pc_port; //PCĶ˿ + + uint32_t tour_tick; //Ѳزʱ + uint32_t core_tick; //ģʱ + uint32_t link_baud; //PC ͨѶ + +}PC_TEST_FLAG_G; + + +typedef struct +{ + uint8_t DevSendCnt; //豸ͼ ﵽطûлظΪ + uint8_t DevOffline; //豸߱־ 1豸 0豸 + uint8_t DevSendSN; //SN + + uint8_t send_flag; + uint8_t test_flag; //PC Ա־λ - 0x01ԣ0x02 + uint32_t test_time; //PC ʱ + uint32_t test_tick; //PC ʱ + +}PC_TEST_DEVICE_INFO; + +extern PC_TEST_FLAG_G g_pc_test; + +void BLV_PC_DEVICE_TEST_Init(void); +uint8_t BLV_PC_DEVICE_TEST_Cycle_Call(uint32_t dev_addr); +uint8_t BLV_PC_DEVICE_TEST_Data_Processing(uint32_t dev_addr,uint32_t data_addr,uint16_t len); +uint8_t BLV_PC_ReadRegister_DataDeal(uint32_t data_addr,uint16_t len); +uint8_t BLV_PC_WriteRegister_DataDeal(uint32_t data_addr,uint16_t len); +uint8_t BLV_PC_Testing_DataDeal(uint32_t data_addr,uint16_t len); +uint8_t BLV_PC_Testing_Data_Reported(uint8_t type,uint8_t dev_type,uint8_t dev_addr,uint32_t data_addr,uint8_t data_len); +uint8_t BLV_PC_Testing_Data_Reported2(uint8_t type,uint8_t dev_type,uint8_t dev_addr,uint8_t *data_buff,uint8_t data_len); +uint8_t BLV_PC_TEST_TOUR_DATASEND(void); +uint8_t BLV_PC_TEST_TOUR_DATASEND2(void); +uint8_t BLV_PC_TEST_TOUR_DATACheck(uint32_t data_addr,uint16_t len); +uint8_t BLV_PC_TEST_TOUR_ACKSend(uint8_t ack_data); +uint8_t BLV_PC_SET_MCU_Revision_Data_Reported(uint32_t data_addr,uint8_t data_len); +uint8_t BLV_PC_READ_MCU_Revision_Data_Reported(uint32_t data_addr,uint8_t data_len); +uint8_t BLV_PC_READ_RCU_Data_Reported(uint32_t data_addr,uint8_t data_len); +uint8_t BLV_PC_READ_RCU_VERSION_Reported(uint32_t data_addr,uint8_t data_len); +uint8_t BLV_PC_READ_Device_Data_Reported(uint32_t data_addr,uint8_t data_len); +uint8_t SyncTime_DATA_Processing(uint32_t data_addr,uint16_t data_len); +uint16_t QueryTime_Relay_DATA_Packaging(uint32_t data_addr,uint16_t data_len); +uint8_t TEST_GPIO_Relay_Fail(void); + + +#endif /* BLV_485_DRIVER_INC_PC_DEVICETEST_FUN_H_ */ diff --git a/BLV_485_Driver/pc_devicetest_fun.c b/BLV_485_Driver/pc_devicetest_fun.c new file mode 100644 index 0000000..8d47c07 --- /dev/null +++ b/BLV_485_Driver/pc_devicetest_fun.c @@ -0,0 +1,1782 @@ +/* + * pc_devicetest_fun.c + * + * Created on: Nov 10, 2025 + * Author: cc + * + * + */ +#include "includes.h" +#include + + +#define PC_REPEATSENDTIMEMAX 0x04 //豸ط + +PC_TEST_FLAG_G g_pc_test; //pcԱ־λ + +/******************************************************************************* +* Function Name : BLV_PC_DEVICE_TEST_Init +* Description : PCʼ - 豸豸бһ˿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_PC_DEVICE_TEST_Init(void) +{ + Device_Public_Information_G BUS_Public; + PC_TEST_DEVICE_INFO PC_Test_Info; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&PC_Test_Info,0,sizeof(PC_TEST_DEVICE_INFO)); + + BUS_Public.addr = DEV_PCTEST_Addr; //豸ַ - Ĭϵַ + BUS_Public.type = DEV_PCTEST_TYPE; //豸 + BUS_Public.port = 0x02; //豸Ͷ˿ + BUS_Public.baud = 115200; //豸Ͳ + BUS_Public.retry_num = PC_REPEATSENDTIMEMAX; //豸ط + BUS_Public.wait_time = 0x01F4; //豸ݷ͵ȴظʱ - 100ms + BUS_Public.polling_cf = (uint32_t)&BLV_PC_DEVICE_TEST_Cycle_Call; + BUS_Public.processing_cf = (uint32_t)&BLV_PC_DEVICE_TEST_Data_Processing; + + g_pc_test.link_port = 0xFF; //Ĭϲ 2022-05-29 + + Add_ACT_Device_To_List(&BUS_Public,(uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO)); +} + +/******************************************************************************* +* Function Name : BLV_BUS_C5MUSIC_Cycle_Call +* Description : PCظͺ +* Input : + dev_addr : 豸Ϣַ +* Return : + 0x00û + 0x01 - 豸Ͳ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_DEVICE_TEST_Cycle_Call(uint32_t dev_addr) +{ + Device_Public_Information_G BUS_Public; + PC_TEST_DEVICE_INFO PC_Test_Info; + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + if((PC_Test_Info.test_flag == 0x01) || (PC_Test_Info.test_flag == 0x02) || (PC_Test_Info.test_flag == 0x11) || (PC_Test_Info.test_flag == 0x12)) //Խж + { + if(SysTick_1ms - PC_Test_Info.test_tick > PC_Test_Info.test_time) + { + PC_Test_Info.test_flag = 0x00; + g_pc_test.test_flag = PC_Test_Info.test_flag; //ȫֲΪ0x00 + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test - The Input Test END"); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&PC_Test_Info, sizeof(PC_TEST_DEVICE_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + } + }else if((PC_Test_Info.test_flag == 0x03) || (PC_Test_Info.test_flag == 0x13)) //Ѳزԣرն˿1񣬿ʼʱ + { + if(SysTick_1ms - g_pc_test.tour_tick > 60) + { + + g_pc_test.tour_tick = SysTick_1ms; + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test BLV_PC_TEST_TOUR_DATASEND%d num:%d------",PC_Test_Info.test_flag,g_pc_test.tour_num); + + if(g_pc_test.tour_num >= 100) + { + /*Ӧ*/ + if(PC_Test_Info.test_flag == 0x13) //ظ + { + uint8_t ack_buff[3] = {0}; + ack_buff[0] = 0x13; + ack_buff[1] = g_pc_test.tour_succ; + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"ظѲؽ!IP:%d.%d.%d.%d Port:%ld\n",g_pc_test.pc_ip[0],g_pc_test.pc_ip[1],g_pc_test.pc_ip[2],g_pc_test.pc_ip[3],g_pc_test.pc_port); + Udp_Internal_PC_Testing_Reported(ack_buff,0x02,g_pc_test.pc_ip,g_pc_test.pc_port); + + }else if(PC_Test_Info.test_flag == 0x03) //ڻظ + { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"ڻظѲؽ!\r\n"); + BLV_PC_TEST_TOUR_ACKSend(g_pc_test.tour_succ); + } + + + PC_Test_Info.test_flag = 0; + g_pc_test.test_flag = PC_Test_Info.test_flag; + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test TOUR DATAS END%d num:%d SUCC:%d",PC_Test_Info.test_flag,g_pc_test.tour_num,g_pc_test.tour_succ); + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&PC_Test_Info, sizeof(PC_TEST_DEVICE_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + }else { + g_pc_test.tour_num++; + BLV_PC_TEST_TOUR_DATASEND(); //Ѳ + return RS485OCCUPYTIME; + } + } + } + + return RS485OCCUPYNOTIME; +} + +/******************************************************************************* +* Function Name : Uart_Search_Cmd +* Description : ڽ +* Input : buff - + len - ݳ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Uart_Search_Cmd(uint8_t *buff,uint8_t len) +{ + char Boot_cmd[10] = "Search:1"; + uint8_t rev = 0; + + if(len != 10) return 0xFF; + + if((buff[len - 1] == 0x0A) && (buff[len - 2] == 0x0D)) + { + for(int i =0;i SRAM_UART1_RecvBuffer_Start_Addr) && (data_addr < SRAM_UART1_RecvBuffer_End_Addr)) + { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test UART1------"); + g_pc_test.link_port = 0x01; + }else if((data_addr > SRAM_UART2_RecvBuffer_Start_Addr) && (data_addr < SRAM_UART2_RecvBuffer_End_Addr)) + { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test UART2------"); + g_pc_test.link_port = 0x02; + } + + /*ظ*/ + if(Uart_Search_Cmd_from_SRAM(data_addr, len) == 0x00) + { + Dbg_Switch = 0x00; //յرյϢ + char* cmd = "Search:1\r\n"; + char ack[35] = {0}; + sprintf(ack, "%s%s\r\n", cmd, APP_NAME); + + if(g_pc_test.link_port == 0x01) + { + UART1_SendString((uint8_t *)ack, strlen(ack)); + } + else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2((uint8_t *)ack, strlen(ack)); + } + } + else if(Uart_Jump_Cmd_from_SRAM(data_addr, len) == 0x00) + { + char* cmd = "Jump:1\r\n"; + char ack[30] = {0}; + sprintf(ack, "%s%s\r\n", cmd, APP_NAME); + WDT_Feed(); //ֹŹλ + if(g_pc_test.link_port == 0x01) + { + UART1_SendString((uint8_t *)ack, strlen(ack)); + Uart1_Flush(100); + } + else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2((uint8_t *)ack, strlen(ack)); + } + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"SYS_ResetExecute!"); + + SRAM_Write_Word(APPFlag_UartUpgrade_Reset,SRAM_APPFlag_Reset_Source); + + WDT_Reinit(); + Delay_Ms(100); + + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"λ!"); + LOG_LogicInfo_DebugRecord("λ"); + + //SYS_ResetExecute(); //λ + } + + temp = SRAM_Read_Byte(data_addr + PKT2_ADD_FM); + if(temp != 0x00) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"PC PKT_ADD_FM Fail!"); + return 0x01; //͵ַ + } + temp = SRAM_Read_Byte(data_addr + PKT2_DevType); + if(temp != PCTESTTYPE) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"PC PKT_DevType Fail!"); + return 0x01; //豸Ͳ + } + temp = SRAM_Read_Byte(data_addr + PKT2_ADD_TO); + if(temp != 0x00) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"PC PKT_ADD_TO Fail!"); + return 0x01; //յַ + } + temp = SRAM_Read_Byte(data_addr + PKT2_LEN); + if(temp != len||(len>256)) //2022-12-13 ӳǷ512Byteж + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"PC PKT_LEN Fail!"); + return 0x01; //Ȳ + } + + /*У*/ //2022-12-13 УڳУ֮ + if(Log_CheckSum(data_addr,len) != 0x00) + { + Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"PC Check Fail!"); + return 0x01; //У + } + + + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test Data Addr:%08X Len:%d",data_addr,len); + + temp = SRAM_Read_Byte(data_addr + PKT2_TYPE); + PC_Test_Info.DevSendSN = temp & 0x0F; + g_pc_test.DevSendSN = PC_Test_Info.DevSendSN; + /**/ + temp = SRAM_Read_Byte(data_addr + PKT2_CMD); + switch(temp) + { + case BLV_PC_TEST_SearchMCU_CMD: // + + break; + case BLV_PC_TEST_SyncTime_CMD: //ͬʱ + SyncTime_DATA_Processing(data_addr,len); + break; + case BLV_PC_TEST_QueryTime_CMD: //ѯʱ + QueryTime_Relay_DATA_Packaging(data_addr,len); + break; + case BLV_PC_TEST_ConfigInfo_CMD: //Ϣ· - ·豸Ϣ + + break; + case BLV_PC_TEST_ReadRegister_CMD: //ȡӳĴ + BLV_PC_ReadRegister_DataDeal(data_addr,len); + break; + case BLV_PC_TEST_WriteRegister_CMD: //дӳĴ - MACַĿš + BLV_PC_WriteRegister_DataDeal(data_addr,len); + break; + case BLV_PC_TEST_StartTesting_CMD: //豸,Ͳ + /*Ͳ */ + temp1 = SRAM_Read_Byte(data_addr + PKT2_PARA); + if(temp1 == 0x01) // - ͬʱʱ + { + g_pc_test.test_flag = 0x01; + + g_pc_test.test_dev = SRAM_Read_Byte(data_addr + PKT2_PARA + 1); + g_pc_test.test_addr = SRAM_Read_Byte(data_addr + PKT2_PARA + 2); + PC_Test_Info.test_time = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); //ʱ䣬λ + + PC_Test_Info.test_flag = g_pc_test.test_flag; + PC_Test_Info.test_tick = SysTick_1ms; + PC_Test_Info.test_time *= 60000; + } + else if(temp1 == 0x02) // + { + g_pc_test.test_flag = 0x02; + PC_Test_Info.test_flag = g_pc_test.test_flag; + PC_Test_Info.test_tick = SysTick_1ms; + PC_Test_Info.test_time = 120000; + + BLV_PC_Testing_DataDeal(data_addr,len); + }else if(temp1 == 0x03) //Ѳز - 485˿ + { + g_pc_test.test_flag = 0x03; + PC_Test_Info.test_flag = g_pc_test.test_flag; + g_pc_test.tour_num = 0; + g_pc_test.tour_succ = 0; + } + break; + case BLV_PC_TEST_SetBaud_CMD: //PC˿ڲʣģʽ + + break; + case BLV_PC_SET_DEBUG_CMD: //DebugϢ + /* + 1Ʋ 0 1 + bit0: ϵͳϢӡ + bit1: Ϣӡ + bit2: 豸ӡϢӡ + bit3: ߼Ϣӡ + */ + { + uint32_t temp_switch = 0x00FFFFFF; + switch(len) + { + case 0x0C: + { + temp_switch = 0x00FFFFFF; + Dbg_Switch &= temp_switch; + temp_switch = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); + temp_switch <<= 24; + Dbg_Switch |= temp_switch; + } + case 0x0B: + { + temp_switch = 0xFF00FFFF; + Dbg_Switch &= temp_switch; + temp_switch = SRAM_Read_Byte(data_addr + PKT2_PARA + 2); + temp_switch <<= 16; + Dbg_Switch |= temp_switch; + } + case 0x0A: + { + temp_switch = 0xFFFF00FF; + Dbg_Switch &= temp_switch; + temp_switch = SRAM_Read_Byte(data_addr + PKT2_PARA + 1); + temp_switch <<= 8; + Dbg_Switch |= temp_switch; + } + case 0x09: + { + temp_switch = 0xFFFFFF00; + Dbg_Switch &= temp_switch; + temp_switch = SRAM_Read_Byte(data_addr + PKT2_PARA ); + Dbg_Switch |= temp_switch; + } + break; + + } + + Dbg_Switch &= 0x00; + Dbg_Switch |= SRAM_Read_Byte(data_addr + PKT2_PARA); + + printf("Dbg_Switch:%08X",Dbg_Switch); + } + break; + case BLV_PC_TEST_GPIO_CMD: + Dbg_Println(DBG_OPT_DEVICE_STATUS,"BLV_PC_TEST_GPIO_CMD"); + TEST_GPIO_Relay_Fail(); + break; + case BLV_PC_SET_MCU_Revision_CMD: //MCUͺԼпͺ + BLV_PC_SET_MCU_Revision_Data_Reported(data_addr,len); + break; + case BLV_PC_READ_MCU_Revision_CMD: //ȡMCUͺԼпͺ + BLV_PC_READ_MCU_Revision_Data_Reported(data_addr,len); + break; +// case BLV_PC_SET_MQTT_CMD: //MQTT +// BLV_PC_SET_MQTT_Reported(data_addr,len); +// break; +// case BLV_PC_READ_MQTT_CMD: //ȡMQTT +// Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC_READ_MQTT:%d", BLV_PC_READ_MQTT_Reported(data_addr,len)); +// break; +// case BLV_PC_CORE_TEST_CMD: //PC +// BLV_PC_CORE_TEST_Data_Reported(); +// break; + case BLV_PC_READ_RCU_Data_CMD: + BLV_PC_READ_RCU_Data_Reported(data_addr,len); + break; + case BLV_PC_READ_Device_Data_CMD: + //ȡ豸Ϣ + BLV_PC_READ_Device_Data_Reported(data_addr,len); + break; + case BLV_PC_READ_RCU_VERSION_CMD: + //ȡ豸Ϣ + BLV_PC_READ_RCU_VERSION_Reported(data_addr,len); + break; + default: break; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&PC_Test_Info, sizeof(PC_TEST_DEVICE_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + return 0; +} + +/******************************************************************************* +* Function Name : BLV_PC_ReadRegister_DataDeal +* Description : ȡӳĴ +* Input : + data_addr : ݵַ + len ݳ +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_ReadRegister_DataDeal(uint32_t data_addr,uint16_t len) +{ + uint8_t i = 0,temp = 0; + uint32_t read_register = 0,temp_offset = 0,temp_data = 0; + uint16_t temp_len = 0; + uint8_t back_data[100]; + + memset(back_data,0,100); + + temp = SRAM_Read_Byte(data_addr + PKT2_PARA); //üĴ,10 + if(temp > 10) back_data[PKT2_PARA] = 10; //ȡĴ,10 + else back_data[PKT2_PARA] = temp; + /*ȡĴ*/ + for(i = 0;i SRAM_Register_End_ADDRESS) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Not In The Right Range"); + continue; + } + temp_data = SRAM_Read_DW(read_register); //ȡĴ + + back_data[PKT2_PARA+i*8+8] = ((temp_data >> 24) & 0xFF); + back_data[PKT2_PARA+i*8+7] = ((temp_data >> 16) & 0xFF); + back_data[PKT2_PARA+i*8+6] = ((temp_data >> 8) & 0xFF); + back_data[PKT2_PARA+i*8+5] = (temp_data & 0xFF); + } + + temp_len = 0x09 + back_data[PKT2_PARA]*8; + + /*ظݴ*/ + back_data[PKT2_ADD_FM] = 0x00; //ַ + back_data[PKT2_TYPE] = g_pc_test.DevSendSN; + back_data[PKT2_DevType] = PCTESTTYPE; //豸 + back_data[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + back_data[PKT2_LEN] = temp_len & 0xFF; //ηݳ + back_data[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + back_data[PKT2_CHKSUM] = 0x00; //У + back_data[PKT2_CMD] = BLV_PC_TEST_ReadRegister_Relay; // + + back_data[PKT2_CHKSUM] = Data_CheckSum(back_data,temp_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + UART0_SendString(back_data,temp_len); //0 + }else if(g_pc_test.link_port == 0x01) + { + UART1_SendString(back_data,temp_len); //1 + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(back_data,temp_len); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +/******************************************************************************* +* Function Name : BLV_PC_WriteRegister_DataDeal +* Description : дӳĴ +* Input : + data_addr : ݵַ + len ݳ +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_WriteRegister_DataDeal(uint32_t data_addr,uint16_t len) +{ + uint8_t i = 0,temp = 0,temp_num = 0,temp1 = 0x01; + uint32_t read_register = 0,temp_offset = 0,temp_data = 0; + uint16_t temp_len = 0x09; + uint8_t back_data[10]; + + memset(back_data,0,10); + + /*üĴ*/ + temp = SRAM_Read_Byte(data_addr + PKT2_PARA); //üĴ,10 + + if(temp > 10) temp_num = 10; //üĴ,10 + else temp_num = temp; + + for(i = 0;i SRAM_Register_End_ADDRESS) + { + temp1 = 0x00; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Not In The Right Range"); + continue; + } + + SRAM_Write_DW(temp_data,read_register); + if(temp_data != SRAM_Read_DW(read_register)) temp = 0x02; //дʧ + } + + Retain_Flash_Register_Data(); //ݱ浽Flash + + SRAM_DMA_Read_Buff(back_data, 4, SRAM_Register_Start_ADDRESS + Register_NETMACKADDR_OFFSET); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"MACAddr:%02X.%02X.%02X.%02X.%02X.%02X",back_data[0],back_data[1],back_data[2],back_data[3],back_data[4],back_data[5]); + + /*ظݴ*/ + back_data[PKT2_ADD_FM] = 0x00; //ַ + back_data[PKT2_TYPE] = g_pc_test.DevSendSN; + back_data[PKT2_DevType] = PCTESTTYPE; //豸 + back_data[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + back_data[PKT2_LEN] = temp_len & 0xFF; //ηݳ + back_data[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + back_data[PKT2_CHKSUM] = 0x00; //У + back_data[PKT2_CMD] = BLV_PC_TEST_WriteRegister_Relay; // + + back_data[PKT2_PARA] = temp1; //óɹ + back_data[PKT2_CHKSUM] = Data_CheckSum(back_data,temp_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(back_data,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(back_data,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(back_data,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(back_data,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(back_data,temp_len); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +/******************************************************************************* +* Function Name : BLV_PC_Testing_DataDeal +* Description : ݴ +* Input : + data_addr : ݵַ + len ݳ +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_Testing_DataDeal(uint32_t data_addr,uint16_t len) +{ + uint8_t control_dev = 0,control_addr = 0,control_cmd = 0,temp = 0,temp1 = 0,temp2 = 0; + uint8_t control_num = 0; + + uint32_t device_listaddr = 0; + uint16_t temp_len = 0x09; + uint8_t back_data[15]; + + memset(back_data,0,15); + + control_dev = SRAM_Read_Byte(data_addr + PKT2_PARA + 1); //豸 + control_addr = SRAM_Read_Byte(data_addr + PKT2_PARA + 2); //豸ַ + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test DevType:%08x",control_dev); + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test DevAddr:%08x",control_addr); + /*¼һµǰԵ豸ͼ豸ַ*/ + g_pc_test.test_dev = control_dev; + g_pc_test.test_addr = control_addr; + + device_listaddr = Find_Device_List_Information(control_dev,control_addr); + if((device_listaddr < SRAM_Device_List_Start_Addr) || (device_listaddr > SRAM_Device_List_End_Addr)) { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test Find Dev Error:%08x",control_dev); + return 0xF0; + } + + switch(control_dev) + { + case DEV_C5IO_Type: //C5IO ݴ + control_cmd = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); + + if(control_cmd == BLV_C5IO_Set_Relay_CMD) //̵ + { + control_num = len - 12; + if(control_num >= 6) control_num = 6; //Ŀǰ6ByteĿ + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test C5IO_Control Len %d,Control_NUM:%d",len,control_num); + + for(uint8_t i = 0;i> j*2) & 0x03; //״̬ + if(temp1 != 0x00) + { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test C5IO_Control_RelayCH%d status:%d - %08X",temp2,temp1,device_listaddr); + { + UINT8 control[6]; + control[0] = Dev_Host_HVout; + control[1] = 0x00; + control[2] = temp2; //· + control[3] = 0x00; + control[4] = temp1; //״̬ + control[5] = 0x00; + DevActionCtrl(control, 6); //̵ + } + BUS_C5IO_Control_Relay(device_listaddr,temp2,temp1); + } + } + } + }else if(control_cmd == BLV_C5IO_Set_Do_CMD) //DO + { + for(uint8_t i = 0;i<2;i++) + { + temp = SRAM_Read_Byte(data_addr + PKT2_PARA + 4 + i); + for(uint8_t j = 0;j<4;j++) + { + temp2 = i*4+j; //ƻ· + temp1 = (temp >> j*2) & 0x03; //״̬ + if(temp1 != 0x00) + { + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test C5IO_Control_DoCH%d status:%d",temp2,temp1); + BUS_C5IO_Control_Do(device_listaddr,temp2,temp1); + } + } + } + } + return 0x00; + case DEV_C5MUSIC_Type: + control_cmd = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); + if(control_cmd == BLV_C5MUSIC_Specify_Play_CMD) + { + temp = SRAM_Read_Byte(data_addr + PKT2_PARA + 4); //״̬ + temp1 = SRAM_Read_Byte(data_addr + PKT2_PARA + 5); //ļ + temp2 = SRAM_Read_Byte(data_addr + PKT2_PARA + 6); //ID + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"PC Test C5Music_Control dir:%d id:%d status:%d",temp1,temp2,temp); + BUS_C5MUSIC_Playback(device_listaddr,temp1,temp,temp2); + } + + /*ظݴ*/ + back_data[PKT2_ADD_FM] = 0x00; //ַ + back_data[PKT2_TYPE] = g_pc_test.DevSendSN; + back_data[PKT2_DevType] = PCTESTTYPE; //豸 + back_data[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + back_data[PKT2_LEN] = temp_len & 0xFF; //ηݳ + back_data[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + back_data[PKT2_CHKSUM] = 0x00; //У + back_data[PKT2_CMD] = BLV_PC_TEST_StartTesting_Relay; // + + back_data[PKT2_PARA] = 0x01; //óɹ + back_data[PKT2_CHKSUM] = Data_CheckSum(back_data,temp_len); + +// /**/ +// if(g_pc_test.link_port == 0x00) +// { +// UART0_SendString(back_data,temp_len); //0 +// }else if(g_pc_test.link_port == 0x01) +// { +// MCU485_SendString_1(back_data,temp_len); //1 +// }else if(g_pc_test.link_port == 0x02) +// { +// MCU485_SendString_2(back_data,temp_len); //2 +// }else { +// return 0xF0; +// } + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(back_data,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(back_data,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(back_data,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(back_data,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(back_data,temp_len); //2 + }else { + return 0xF0; + } + + break; + + case DEV_RS485_PWM: + control_cmd = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); + if(control_cmd == C12_SET_LIGHT_CMD) + { + temp = SRAM_Read_Byte(data_addr + PKT2_PARA + 4); //û· + temp1 = SRAM_Read_Byte(data_addr + PKT2_PARA + 5); //ֵ + temp2 = SRAM_Read_Byte(data_addr + PKT2_PARA + 6); //ʱ + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"PC Test C12Dimming:%d light:%d fade:%d",temp1,temp2,temp); + + if(temp) + { + UINT8 control[6]; + control[0] = DEV_RS485_PWM; + control[1] = 0x00; + control[2] = temp-1; //· + control[3] = 0x00; + control[4] = 0x01; //״̬ + control[5] = temp1; //ֵ + DevActionCtrl(control, 6); //̵ + } + } + break; + default: + // + { + uint8_t control[8]; + + SRAM_DMA_Read_Buff(control,6,data_addr + PKT2_PARA + 1); + DevActionCtrl(control, 6); + Dbg_Print_Buff(DBG_BIT_NET_STATUS_bit,"PC Test Control Data:",control,6); + + /*ظݴ*/ + back_data[PKT2_ADD_FM] = 0x00; //ַ + back_data[PKT2_TYPE] = g_pc_test.DevSendSN; + back_data[PKT2_DevType] = PCTESTTYPE; //豸 + back_data[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + back_data[PKT2_LEN] = temp_len & 0xFF; //ηݳ + back_data[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + back_data[PKT2_CHKSUM] = 0x00; //У + back_data[PKT2_CMD] = BLV_PC_TEST_StartTesting_Relay; // + + back_data[PKT2_PARA] = 0x01; //óɹ + back_data[PKT2_CHKSUM] = Data_CheckSum(back_data,temp_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(back_data,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(back_data,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(back_data,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(back_data,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(back_data,temp_len); //2 + }else { + return 0xF0; + } + } + break; + } + + return 0x00; +} + +/*ϱ*/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_Testing_Data_Reported(uint8_t type,uint8_t dev_type,uint8_t dev_addr,uint32_t data_addr,uint8_t data_len) +{ + uint8_t send_buff[50]; + memset(send_buff,0,50); + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"%s",__func__); + g_pc_test.DevSendSN++; + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + send_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + send_buff[PKT2_DevType] = PCTESTTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = 0x08+data_len+3; //ηݳ + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_PC_TEST_StartTesting_Relay; // + + send_buff[PKT2_PARA] = type; //ϱ + send_buff[PKT2_PARA + 1] = dev_type; //ϱ + send_buff[PKT2_PARA + 2] = dev_addr; //ϱ + + for(uint8_t i=0;i (PKT2_PARA + 9)) { + return 0x01; + } + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"%s",__func__); + + read_flag = SRAM_Read_Byte(data_addr+PKT2_PARA); + read_addr = SRAM_Read_DW(data_addr+PKT2_PARA+1); + read_len = SRAM_Read_DW(data_addr+PKT2_PARA+5); + + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡRCU:%08X,Len:%08X",read_addr,read_len); + if(read_len >= 512) read_len = 512; //ȡݳΪ512Byte + + switch(read_flag) + { + case 0x01: //SRAM + if(read_addr >= SRAM_ADDRESS_MAX) { + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"Addr Error"); + break; + } + SRAM_DMA_Read_Buff(&send_buff[PKT2_PARA+10],read_len,read_addr); + send_len += read_len; + result = 0x01; + break; + case 0x02: //Flash + if(read_addr >= Flash_ADDRESS_MAX) { + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"Addr Error"); + break; + } + Flash_Read(&send_buff[PKT2_PARA+10],read_len,read_addr); + send_len += read_len; + result = 0x01; + break; + default: + + break; + } + + send_buff[PKT2_PARA] = result; + SRAM_DMA_Read_Buff(&send_buff[PKT2_PARA+1],9,data_addr+PKT2_PARA); + + /*ݴظ*/ + g_pc_test.DevSendSN++; + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + send_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + send_buff[PKT2_DevType] = PCTESTTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = (send_len & 0xFF); //ηݳ + send_buff[PKT2_LEN_8] = ((send_len >> 8) & 0xFF); + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_PC_READ_MCU_Revision_Relay; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(send_buff,send_buff[PKT2_LEN]); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(send_buff,send_buff[PKT2_LEN]); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(send_buff,send_buff[PKT2_LEN]); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(send_buff,send_buff[PKT2_LEN]); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(send_buff,send_buff[PKT2_LEN]); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_READ_RCU_VERSION_Reported(uint32_t data_addr,uint8_t data_len) +{ + uint8_t send_buff[100]; + uint16_t send_len = 0x00; + uint8_t read_flag; + memset(send_buff,0,sizeof(send_buff)); + + /*ݴ*/ + Dbg_Println(DBG_OPT_DEVICE_STATUS,"%s",__func__); + + read_flag = SRAM_Read_Byte(data_addr+PKT2_PARA); //1:̼汾 2:launcher汾 3:ð汾 + + switch(read_flag){ + case 1: + memcpy(&send_buff[PKT2_PARA+2],SoftwareVer,sizeof(SoftwareVer)); + break; + case 2: + SRAM_DMA_Read_Buff((uint8_t *)&send_buff[PKT2_PARA+2],20,SRAM_Launcher_SoftwareVer_Addr); + break; + case 3: + if (Read_LogicFile_Information(0x08,(uint8_t *)&send_buff[PKT2_PARA+2]) != 0x00) return 0xF1; + + send_buff[PKT2_PARA+9] = send_buff[PKT2_PARA+4]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+8] = send_buff[PKT2_PARA+4]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+6] = send_buff[PKT2_PARA+3]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+5] = send_buff[PKT2_PARA+3]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+3] = send_buff[PKT2_PARA+2]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+2] = send_buff[PKT2_PARA+2]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+4] = (uint8_t)'.'; + send_buff[PKT2_PARA+7] = (uint8_t)'.'; + + break; + case 4: + if (Read_LogicFile_Information(0x02,(uint8_t *)&send_buff[PKT2_PARA+2]) != 0x00) return 0xF2; + send_buff[PKT2_PARA+12] = send_buff[PKT2_PARA+5]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+11] = send_buff[PKT2_PARA+5]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+9] = send_buff[PKT2_PARA+4]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+8] = send_buff[PKT2_PARA+4]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+6] = send_buff[PKT2_PARA+3]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+5] = send_buff[PKT2_PARA+3]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+3] = send_buff[PKT2_PARA+2]%10+(uint8_t)'0'; + send_buff[PKT2_PARA+2] = send_buff[PKT2_PARA+2]/10%10+(uint8_t)'0'; + send_buff[PKT2_PARA+4] = (uint8_t)'.'; + send_buff[PKT2_PARA+7] = (uint8_t)'.'; + send_buff[PKT2_PARA+10] = (uint8_t)'.'; + + break; + default: + break; + } + + send_buff[PKT2_PARA] = 0x01; + send_buff[PKT2_PARA+1] = strlen((char *)&send_buff[PKT2_PARA+2]); + + send_len = PKT2_PARA + 0x02 + strlen((char *)&send_buff[PKT2_PARA+2]); + + /*ݴظ*/ + + g_pc_test.DevSendSN++; + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + send_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + send_buff[PKT2_DevType] = PCTESTTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = (send_len & 0xFF); //ηݳ + send_buff[PKT2_LEN_8] = ((send_len >> 8) & 0xFF); + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_PC_READ_RCU_VERSION_Relay; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(send_buff,send_buff[PKT2_LEN]); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(send_buff,send_buff[PKT2_LEN]); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(send_buff,send_buff[PKT2_LEN]); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(send_buff,send_buff[PKT2_LEN]); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(send_buff,send_buff[PKT2_LEN]); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +__attribute__((section(".non_0_wait"))) uint8_t BLV_PC_READ_Device_Data_Reported(uint32_t data_addr,uint8_t data_len) +{ + uint8_t send_buff[100]; + uint16_t send_len = 0x00; + uint8_t read_devaddr = 0,read_devtype = 0,read_devinfo = 0; + uint32_t read_addr = 0; + memset(send_buff,0,sizeof(send_buff)); + + /*ݴ*/ + if(data_len < (PKT2_PARA + 3)) { + return 0x01; + } + + Dbg_Println(DBG_OPT_DEVICE_STATUS,"%s",__func__); + + read_devtype = SRAM_Read_Byte(data_addr+PKT2_PARA); //豸 + read_devaddr = SRAM_Read_Byte(data_addr+PKT2_PARA+1); //豸ַ + read_devinfo = SRAM_Read_Byte(data_addr+PKT2_PARA+2); //ȡϢ + + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡ豸:%08X, ַ:%d Ϣ:%d",read_devtype,read_devaddr,read_devinfo); + + //豸 + read_addr = Find_Device_List_Information(read_devtype,read_devaddr); + if(read_addr != 0x00){ + //ĿǰBLV-C8 ʹõ + send_buff[PKT2_PARA] = 0x01; + + switch(read_devtype){ + case Dev_Rs485_PB20: + #if RS485_PB20Fun_Flag + if(read_devinfo == 0x01){ + //ѯ汾 + send_buff[PKT2_PARA + 1] = Get_BLV_PB20_COMM_Version(read_addr); + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡ汾:%d",send_buff[PKT2_PARA + 1] ); + send_len = PKT2_PARA + 0x02; + }else if(read_devinfo == 0x02){ + //ѯPS ѹ + uint16_t temp_val = 0x00; + temp_val = Get_BLV_PB20_PS_Voltage(read_addr); + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡPSѹ:%dmV",temp_val ); + send_buff[PKT2_PARA + 1] = (temp_val >> 8) & 0xFF; + send_buff[PKT2_PARA + 2] = temp_val & 0xFF; + send_len = PKT2_PARA + 0x03; + }else if(read_devinfo == 0x03){ + //ѯBUS ѹ + uint16_t temp_val = 0x00; + temp_val = Get_BLV_PB20_BUS_Voltage(read_addr); + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡBUSѹ:%dmV",temp_val ); + send_buff[PKT2_PARA + 1] = (temp_val >> 8) & 0xFF; + send_buff[PKT2_PARA + 2] = temp_val & 0xFF; + send_len = PKT2_PARA + 0x03; + }else if(read_devinfo == 0x04){ + //ѯBUS + uint16_t temp_val = 0x00; + temp_val = Get_BLV_PB20_BUS_Current(read_addr); + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡBUS:%dmV",temp_val ); + send_buff[PKT2_PARA + 1] = (temp_val >> 8) & 0xFF; + send_buff[PKT2_PARA + 2] = temp_val & 0xFF; + send_len = PKT2_PARA + 0x03; + } + #endif + break; + case DEV_C5IO_Type: + if(read_devinfo == 0x01){ + //ѯ汾 + send_buff[PKT2_PARA + 1] = Get_Bus_CSIO_COMM_Version(read_addr); + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡ汾:%d",send_buff[PKT2_PARA + 1] ); + send_len = PKT2_PARA + 0x02; + } + break; + default: + send_len = PKT2_PARA + 0x01; + break; + } + }else{ + //豸 + Dbg_Println(DBG_BIT_Debug_STATUS_bit,"ȡ豸ʧ"); + send_buff[PKT2_PARA] = 0x00; + send_len = PKT2_PARA + 0x01; + } + + + /*ݴظ*/ + + g_pc_test.DevSendSN++; + + send_buff[PKT2_ADD_FM] = 0x00; //ַ + send_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + send_buff[PKT2_DevType] = PCTESTTYPE; //豸 + send_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + send_buff[PKT2_LEN] = (send_len & 0xFF); //ηݳ + send_buff[PKT2_LEN_8] = ((send_len >> 8) & 0xFF); + send_buff[PKT2_CHKSUM] = 0x00; //У + send_buff[PKT2_CMD] = BLV_PC_READ_Device_Data_Relay; // + + send_buff[PKT2_CHKSUM] = Data_CheckSum(send_buff,send_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(send_buff,send_buff[PKT2_LEN]); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(send_buff,send_buff[PKT2_LEN]); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(send_buff,send_buff[PKT2_LEN]); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(send_buff,send_buff[PKT2_LEN]); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(send_buff,send_buff[PKT2_LEN]); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +__attribute__((section(".non_0_wait"))) uint8_t SyncTime_DATA_Processing(uint32_t data_addr,uint16_t data_len) +{ +// uint32_t utc_tick = 0; + uint16_t temp_len = 0x09; + uint8_t temp = 0; + uint32_t device_listaddr = 0; + S_RTC set_time; + uint8_t ack_buff[temp_len]; + memset(ack_buff,0,temp_len); + + set_time.year = SRAM_Read_Byte(data_addr + PKT2_PARA); + + set_time.month = SRAM_Read_Byte(data_addr + PKT2_PARA + 1); + + set_time.day = SRAM_Read_Byte(data_addr + PKT2_PARA + 2); + + set_time.hour = SRAM_Read_Byte(data_addr + PKT2_PARA + 3); + + set_time.minute = SRAM_Read_Byte(data_addr + PKT2_PARA + 4); + + set_time.second = SRAM_Read_Byte(data_addr + PKT2_PARA + 5); + + set_time.week = SRAM_Read_Byte(data_addr + PKT2_PARA + 6); + + + temp = RTC_WriteDate(set_time); + + //ҵCSIO + if(g_time_info.time_select == 0x02){ + device_listaddr = Find_Device_List_Information(DEV_C5IO_Type,0x00); + if((device_listaddr >= SRAM_Device_List_Start_Addr) && (device_listaddr <= SRAM_Device_List_End_Addr)) { + + BUS_CSIO_Set_RTC_Time(device_listaddr); + } + } + + +// /*UTCʱ*/ +// utc_tick = RTC_Conversion_To_Unix(&set_time); +// Unix_Conversion_To_RTC(&set_time,utc_tick); + + /*ظݴ*/ + ack_buff[PKT2_ADD_FM] = 0x00; //ַ + ack_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + ack_buff[PKT2_DevType] = PCTESTTYPE; //豸 + ack_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + ack_buff[PKT2_LEN] = temp_len & 0xFF; //ηݳ + ack_buff[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + ack_buff[PKT2_CHKSUM] = 0x00; //У + ack_buff[PKT2_CMD] = BLV_PC_TEST_QueryTime_Relay; // + + ack_buff[PKT2_PARA] = temp; //ظ״̬ 0x01ִгɹ 0x00ִʧ + + ack_buff[PKT2_CHKSUM] = Data_CheckSum(ack_buff,temp_len); + + /**/ + + if(g_pc_test.link_port == 0x00) + { + UART0_SendString(ack_buff,temp_len); //0 + }else if(g_pc_test.link_port == 0x01) + { + MCU485_SendString_1(ack_buff,temp_len); //1 + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(ack_buff,temp_len); //2 + }else { + return 0xF0; + } + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(ack_buff,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(ack_buff,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(ack_buff,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(ack_buff,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(ack_buff,temp_len); //2 + }else { + return 0xF0; + } + + return 0x00; +} + +/*ͬʱظݴ*/ +__attribute__((section(".non_0_wait"))) uint16_t QueryTime_Relay_DATA_Packaging(uint32_t data_addr,uint16_t data_len) +{ + uint16_t temp_len = 0x0F; + uint8_t ack_buff[temp_len]; + memset(ack_buff,0,temp_len); + + ack_buff[PKT2_ADD_FM] = 0x00; //ַ + ack_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + ack_buff[PKT2_DevType] = PCTESTTYPE; //豸 + ack_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + ack_buff[PKT2_LEN] = temp_len & 0xFF; //ηݳ + ack_buff[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + ack_buff[PKT2_CHKSUM] = 0x00; //У + ack_buff[PKT2_CMD] = BLV_PC_TEST_QueryTime_Relay; // + + ack_buff[PKT2_PARA] = HEX_Conversion_To_DEC(RTC_Raw_Data.year); + ack_buff[PKT2_PARA+1] = HEX_Conversion_To_DEC(RTC_Raw_Data.month); + ack_buff[PKT2_PARA+2] = HEX_Conversion_To_DEC(RTC_Raw_Data.day); + ack_buff[PKT2_PARA+3] = HEX_Conversion_To_DEC(RTC_Raw_Data.hour); + ack_buff[PKT2_PARA+4] = HEX_Conversion_To_DEC(RTC_Raw_Data.minute); + ack_buff[PKT2_PARA+5] = HEX_Conversion_To_DEC(RTC_Raw_Data.second); + ack_buff[PKT2_PARA+6] = HEX_Conversion_To_DEC(RTC_Raw_Data.week); + + ack_buff[PKT2_CHKSUM] = Data_CheckSum(ack_buff,temp_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(ack_buff,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(ack_buff,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(ack_buff,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(ack_buff,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(ack_buff,temp_len); //2 + }else { + return 0xF0; + } + return 0x00; +} + +__attribute__((section(".non_0_wait"))) uint8_t TEST_GPIO_Relay_Fail(void) +{ + uint16_t temp_len = 0x09; + uint8_t ack_buff[10]; + memset(ack_buff,0,10); + + /*ظݴ*/ + ack_buff[PKT2_ADD_FM] = 0x00; //ַ + ack_buff[PKT2_TYPE] = g_pc_test.DevSendSN; + ack_buff[PKT2_DevType] = PCTESTTYPE; //豸 + ack_buff[PKT2_ADD_TO] = 0x00; //豸ַ - C5 MUSIC̶豸ַΪ0x01 + ack_buff[PKT2_LEN] = temp_len & 0xFF; //ηݳ + ack_buff[PKT2_LEN_8] = (temp_len >> 8) & 0xFF; + ack_buff[PKT2_CHKSUM] = 0x00; //У + ack_buff[PKT2_CMD] = BLV_PC_TEST_GPIO_Relay; // + + ack_buff[PKT2_PARA] = 0x00; //ظ״̬ 0x01ִгɹ 0x00ִʧ + + ack_buff[PKT2_CHKSUM] = Data_CheckSum(ack_buff,temp_len); + + /**/ + if(g_pc_test.link_port == 0x00) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ + MCU485_SendString_0(ack_buff,temp_len); //0 + #elif (USE_CORE_TYPE == 2) //ʹC1İ -- DEBUG + UART0_SendString(ack_buff,temp_len); //0 + #endif + }else if(g_pc_test.link_port == 0x01) + { + #if (USE_CORE_TYPE == 1) //ʹC1Fİ -- DEBUG + UART1_SendString(ack_buff,temp_len); //1 + #elif (USE_CORE_TYPE == 2) //ʹC1İ + MCU485_SendString_1(ack_buff,temp_len); //1 + #endif + }else if(g_pc_test.link_port == 0x02) + { + MCU485_SendString_2(ack_buff,temp_len); //2 + }else { + return 0xF0; + } + + return 0x00; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Core/core_riscv.c b/Core/core_riscv.c new file mode 100644 index 0000000..c5a6018 --- /dev/null +++ b/Core/core_riscv.c @@ -0,0 +1,317 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : RISC-V V4J Core Peripheral Access Layer Source File for CH564 + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "stdint.h" + +/* define compiler specific symbols */ +#if defined(__CC_ARM) +#define __ASM __asm /* asm keyword for ARM Compiler */ +#define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) +#define __ASM __asm /* asm keyword for IAR Compiler */ +#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) +#define __ASM __asm /* asm keyword for GNU Compiler */ +#define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) +#define __ASM __asm /* asm keyword for TASKING Compiler */ +#define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mtvec" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mcause" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mtval" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile("csrw mtval, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp" : "=r"(result):); + return (result); +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__((noinline)) void NVIC_SystemReset(void) +{ + asm("li t0, 0xa8"); + asm("jr t0"); +} + diff --git a/Core/core_riscv.h b/Core/core_riscv.h new file mode 100644 index 0000000..9283528 --- /dev/null +++ b/Core/core_riscv.h @@ -0,0 +1,686 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : RISC-V V4J Core Peripheral Access Layer Header File for CH564 + ********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* IO definitions */ +#ifdef __cplusplus +#define __I volatile /* defines 'read only' permissions */ +#else +#define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vuint32_t; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vuint8_t; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum +{ + NoREADY = 0, + READY = !NoREADY +} ErrorStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct +{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +} PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +} SysTick_Type; + +#define PFIC ((PFIC_Type *)0xE000E000) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) +#define SysTick ((SysTick_Type *)0xE000F000) + +/* CSR_Operation_Function */ +#define READ_CSR(reg) \ +({ \ + unsigned long __tmp; \ + __asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; \ +}) + +#define WRITE_CSR(reg, val) \ +({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + __asm volatile("csrw " #reg ", %0" ::"i"(val)); \ + else \ + __asm volatile("csrw " #reg ", %0" ::"r"(val)); \ +}) + +#define SWAP_CSR(reg, val) \ +({ \ + unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + __asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + __asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; \ +}) + +#define SET_CSR(reg, bit) \ +({ \ + unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + __asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + __asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; \ +}) + +#define CLEAR_CSR(reg, bit) \ +({ \ + unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + __asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + __asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; \ +}) + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile("csrs 0x800, %0" : : "r"(0x88)); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile("csrc 0x800, %0" : : "r"(0x88)); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __NOP() +{ + __asm volatile("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(CSR-0x804 bit1 = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1 << 3); // wfi + __asm volatile("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1 << 3) | (1 << 5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1 << 5)) | (t & (1 << 5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1 << 3); + __asm volatile("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param addr - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, + FunctionalState NewState) +{ + if (num > 3) + return; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) | 0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) & (~0x1)); + } +} + +/********************************************************************* + * @fn ICacheEnable + * + * @brief Enable ICache + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void ICacheEnable(void) +{ + WRITE_CSR(0xBD0, 0x4); + __asm volatile("fence.i"); + CLEAR_CSR(0xBC2, 0x2); +} + +/********************************************************************* + * @fn ICacheDisable + * + * @brief Disable ICache + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void ICacheDisable(void) +{ + SET_CSR(0xBC2, 0x2); + WRITE_CSR(0xBD0, 0x4); + __asm volatile("fence.i"); +} + +/********************************************************************* + * @fn ICacheInvalidate + * + * @brief Invalidate ICache + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate(void) +{ + WRITE_CSR(0xBD0, 0x4); + __asm volatile("fence.i"); +} + +/********************************************************************* + * @fn ICacheInvalidate_By_Address + * + * @brief Invalidate ICache By Address + * + * @param addr - operation address(addr%4 = 0) + * size - operation size(unit 4Byte) + * + * @return none + */ +__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate_By_Address(uint32_t *addr, uint32_t size) +{ + uint32_t t; + uint32_t temp; + + for (t = 0; t < size; t++) + { + temp = (uint32_t)(addr + t); + WRITE_CSR(0xBD0, (temp & 0xFFFFFFF8)); + __asm volatile("fence.i"); + } +} + + + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the bigger value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return the smaller value + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); +extern void NVIC_SystemReset(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Flashlib/ISP564.h b/Flashlib/ISP564.h new file mode 100644 index 0000000..9e4296c --- /dev/null +++ b/Flashlib/ISP564.h @@ -0,0 +1,263 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ISP564.h + * Author : WCH + * Version : V1.1.0 + * Date : 2024/07/17 + * Description : This file contains all the functions prototypes for the + * FLASH firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __ISP564_H +#define __ISP564_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_VERIFY_ERROR, + FLASH_ADR_RANGE_ERROR, + FLASH_UNLOCK_ERROR, +}FLASH_Status; + +/********************************************************************* + * @fn FLASH_Unlock + * + * @brief Unlocks the FLASH Program and Erase Controller. + * + * @return none + */ +extern void FLASH_Unlock(void); + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program and Erase Controller. + * + * @return none + */ +extern void FLASH_Lock(void); + +/********************************************************************* + * @fn GetMACAddress + * + * @brief Get MAC address(6Bytes) + * + * @param Buffer - Pointer to the buffer where data should be stored, + * Must be aligned to 4 bytes. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT. + */ +extern FLASH_Status GetMACAddress( void *Buffer ); + +/********************************************************************* + * @fn GET_UNIQUE_ID + * + * @brief Get unique ID(8Bytes) + * + * @param Buffer - Pointer to the buffer where data should be stored, + * Must be aligned to 4 bytes. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT. + */ +extern FLASH_Status GET_UNIQUE_ID( void *Buffer ); + +/********************************************************************* + * @fn GetCHIPID + * + * @brief Get chip ID(4Bytes) + * + * @param Buffer - Pointer to the buffer where data should be stored, + * Must be aligned to 4 bytes. + * ChipID List- + * CH564L-0x564005x8 + * CH564Q-0x564105x8 + * CH564F-0x564305x8 + * CH564C-0x564205x8 + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT. + */ +extern FLASH_Status GetCHIPID( void *Buffer ); + +/********************************************************************* + * @fn Get_Flash_Size + * + * @brief Get FLASH Size(1Bytes) + * + * @param Buffer - Pointer to the buffer where data should be stored. + * 0 - FLASH-256K + * ROMA(UserFLASH) + * - Size(192K) + * - Address range(0x0 -- 0x2FFFF) + * EEPROM(DataFLASH) + * - Size(32K) + * - Address range(0x30000 -- 0x37FFF) + * 1 - FLASH-512K + * ROMA(UserFLASH) + * - Size(448K) + * - Address range(0x0 -- 0x6FFFF) + * EEPROM(DataFLASH) + * - Size(32K) + * - Address range(0x70000 -- 0x77FFF) + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT. + */ +extern FLASH_Status Get_Flash_Size( void *Buffer ); + +/********************************************************************* + * @fn FLASH_EnableCodeProtection + * + * @brief Enables the code protection. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +extern FLASH_Status FLASH_EnableCodeProtection( void ); + +/********************************************************************* + * @fn FLASH_ROM_PWR_UP + * + * @brief The function `FLASH_ROM_PWR_DOWN` sends a command to put + * the SPI flash memory into power down mode. + * + * @return none + */ +extern void FLASH_ROM_PWR_DOWN( void ); + +/********************************************************************* + * @fn FLASH_ROM_PWR_UP + * + * @brief The function `FLASH_ROM_PWR_UP` sets up the SPI flash + * control register to power up the flash memory + * + * @return none + */ +extern void FLASH_ROM_PWR_UP( void ); + +/********************************************************************* + * @fn EEPROM_READ + * + * @brief (DataFLASH) - The EEPROM_READ function reads data from a specified address + * in flash memory with error handling for address range checks. + * + * @param StartAddr - Read the starting address of the DataFLASH. + * Buffer - Read the value of the DataFLASH. + * Length - Read the length of the DataFLASH. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR. + */ +extern FLASH_Status EEPROM_READ( uint32_t StartAddr, void *Buffer, uint32_t Length ); + +/********************************************************************* + * @fn EEPROM_ERASE + * + * @brief (DataFLASH) - The function EEPROM_ERASE checks the flash size and address + * range before erasing a specified portion of flash memory. + * + * @param StartAddr - Erases the starting address of the DataFLASH(StartAddr%4096 == 0). + * Length - Erases the length of the DataFLASH(Length%4096 == 0). + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR. + */ +extern FLASH_Status EEPROM_ERASE( uint32_t StartAddr, uint32_t Length ); + +/********************************************************************* + * @fn EEPROM_WRITE + * + * @brief (DataFLASH) - The function EEPROM_WRITE writes data to EEPROM memory + * based on specified address and length, performing address + * range and unlock checks. + * + * @param StartAddr - Writes the starting address of the DataFLASH. + * Buffer - Writes the value of the DataFLASH. + * Length - Writes the length of the DataFLASH. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR. + */ +extern FLASH_Status EEPROM_WRITE( uint32_t StartAddr, void *Buffer, uint32_t Length ); + +/********************************************************************* + * @fn FLASH_ROMA_ERASE + * + * @brief (UserFLASH) - The function `FLASH_ROMA_ERASE` checks the flash size and + * address range before erasing a specified portion of flash + * memory. + * + * @param StartAddr - Erases the starting address of the UserFLASH(StartAddr%4096 == 0). + * Length - Erases the length of the UserFLASH(Length%4096 == 0). + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR. + */ +extern FLASH_Status FLASH_ROMA_ERASE( uint32_t StartAddr, uint32_t Length ); + +/********************************************************************* + * @fn FLASH_ROMA_WRITE + * + * @brief (UserFLASH) - The function FLASH_ROMA_WRITE writes data to a specific + * flash memory address after performing size and unlock checks. + * + * @param StartAddr - Writes the starting address of the UserFLASH. + * Buffer - Writes the value of the UserFLASH. + * Length - Writes the length of the UserFLASH. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_UNLOCK_ERROR. + */ +extern FLASH_Status FLASH_ROMA_WRITE( uint32_t StartAddr, void *Buffer, uint32_t Length ); + +/********************************************************************* + * @fn FLASH_ROMA_VERIFY + * + * @brief (UserFLASH) - The function `FLASH_ROMA_VERIFY` verifies the contents of + * a specified flash memory region against a provided buffer. + * + * @param StartAddr - Verify the starting address of the UserFLASH. + * Buffer - Verify the value of the UserFLASH. + * Length - Verify the length of the UserFLASH. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR,FLASH_VERIFY_ERROR. + */ +extern FLASH_Status FLASH_ROMA_VERIFY( uint32_t StartAddr, void *Buffer, uint32_t Length ); + +/********************************************************************* + * @fn FLASH_ROMA_READ + * + * @brief (UserFLASH) - The function `FLASH_ROMA_READ` reads data from a specific + * flash memory address with error handling for different flash + * size + * + * @param StartAddr - Read the starting address of the UserFLASH. + * Buffer - Read the value of the UserFLASH. + * Length - Read the length of the UserFLASH. + * + * @return FLASH_Status -The returned value can be: FLASH_COMPLETE, + * FLASH_TIMEOUT,FLASH_ADR_RANGE_ERROR. + */ +extern FLASH_Status FLASH_ROMA_READ( uint32_t StartAddr, void *Buffer, uint32_t Length ); + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Flashlib/libISP564.a b/Flashlib/libISP564.a new file mode 100644 index 0000000..698c08e Binary files /dev/null and b/Flashlib/libISP564.a differ diff --git a/Ld/Link.ld b/Ld/Link.ld new file mode 100644 index 0000000..c2c835c --- /dev/null +++ b/Ld/Link.ld @@ -0,0 +1,220 @@ +ENTRY( _start ) + +__stack_size = 2048; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ +/* FLASH + RAM supports the following configuration + FLASH-80K + RAM-64K + FLASH-48K + RAM-96K + FLASH-16K + RAM-128K +*/ + +/* FLASH-16K + RAM-128K */ +/* + FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 16K + FLASH1 (rx) : ORIGIN = 0x00004000 , LENGTH = 448K - 16K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 128K +*/ + + +/* FLASH-48K + RAM-96K */ +/* + FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 48K + FLASH1 (rx) : ORIGIN = 0x0000C000 , LENGTH = 448K - 48K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 96K +*/ + +/* FLASH-80K + RAM-64K */ +/* + FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 80K + FLASH1 (rx) : ORIGIN = 0x00014000 , LENGTH = 448K - 80K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K +*/ + + FLASH (rx) : ORIGIN = 0x00000000 , LENGTH = 80K + FLASH1 (rx) : ORIGIN = 0x00014000 , LENGTH = 368K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K + +} + + +SECTIONS +{ + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + _endof_Vector = .; + ASSERT(_endof_Vector < ORIGIN(FLASH1), "The vector must maintain in 0-wait zone"); + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _cache_beg = __cache_beg ); + PROVIDE( _cache_end = __cache_end ); + + .text : + { + . = ALIGN(4); + KEEP(*libISP564.a:(.text)) + KEEP(*libISP564.a:(.text.*)) + KEEP(*libISP564.a:(.rodata)) + KEEP(*libISP564.a:(.rodata.*)) + _endof_Flashlib = .; + ASSERT(_endof_Flashlib < ORIGIN(FLASH1), "The Flash lib must maintain in 0-wait zone"); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .text1 : + { + . = ALIGN(4); + PROVIDE( __cache_beg = .); + *(.cache); + *(.cache.*); + PROVIDE( __cache_end = .); + *(.non_0_wait); + *(.non_0_wait.*); + . = ALIGN(4); + } >FLASH1 AT>FLASH1 + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + } >RAM + +} + + + + diff --git a/MCU_Driver/blv_authorize.c b/MCU_Driver/blv_authorize.c new file mode 100644 index 0000000..4676229 --- /dev/null +++ b/MCU_Driver/blv_authorize.c @@ -0,0 +1,92 @@ +/* + * blv_authorize.c + * + * Created on: Nov 8, 2025 + * Author: cc + */ +#include "blv_authorize.h" + +#include "SPI_SRAM.h" +#include "rw_logging.h" +#include "sram_mem_addr.h" +#include + +BLV_AUTHORIZE sys_authorize; + +/******************************************************************************* +* Function Name : BLV_Set_Authorize_Status +* Description : BLVϵͳȨ״̬ +* Input : + expires_time :Ȩʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Set_Authorize_Status(uint32_t Expires_time,uint8_t lock) +{ + memset(&sys_authorize,0,sizeof(BLV_AUTHORIZE)); + + sys_authorize.lock_status = lock; + sys_authorize.expires_time = Expires_time; +} + +/******************************************************************************* +* Function Name : BLV_Authorize_Processing +* Description : BLVϵͳȨ +* Input : + utc_time :utcʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Authorize_Processing(uint32_t utc_time) +{ + uint32_t temp_tick = utc_time; + uint32_t temp_lock = 0; + if((sys_authorize.expires_time != 0x00) && (temp_tick >= sys_authorize.expires_time ) ) + { + sys_authorize.lock_status = 1; + /*⵽ʱ䵽ں󣬽״̬λͬʱ浽Flash*/ + temp_lock = SRAM_Read_DW(SRAM_Register_Start_ADDRESS + Register_MandateLock_OFFSET); + if(temp_lock != 0x00000001) + { + SRAM_Write_DW(0x01,SRAM_Register_Start_ADDRESS + Register_MandateLock_OFFSET); + //Retain_Flash_Register_Data(); + } + } +} + +/******************************************************************************* +* Function Name : Get_Authorize_Lock_Status +* Description : ȡȨ״̬ +* Input : + 0x00ǰȨδ + 0x01ǰȨ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Set_Authorize_Lock_Status(uint8_t state) +{ + sys_authorize.lock_status = state; +} + +/******************************************************************************* +* Function Name : Get_Authorize_Lock_Status +* Description : ȡȨ״̬ +* Input : None +* Return : + 0x00ǰȨδ + 0x01ǰȨ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Get_Authorize_Lock_Status(void) +{ + if(sys_authorize.expires_time != 0x00) return sys_authorize.lock_status; + return 0x00; +} + +/******************************************************************************* +* Function Name : Get_Authorize_UnixTime +* Description : ȡȨʱ +* Input : None +* Return : Ȩʱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Get_Authorize_UnixTime(void) +{ + return sys_authorize.expires_time; +} + + diff --git a/MCU_Driver/blv_dev_action.c b/MCU_Driver/blv_dev_action.c new file mode 100644 index 0000000..6a2e8a0 --- /dev/null +++ b/MCU_Driver/blv_dev_action.c @@ -0,0 +1,3037 @@ +/* + * blv_dev_action.c + * + * Created on: Nov 11, 2025 + * Author: cc + */ +#include "includes.h" + +BLV_DevAction_Manage_G DevActionGlobal; //豸Ϣȫֱ + +#define Action_Group_Ctrl_Num 30 //е Ⱥظ + +/******************************************************************************* +* Function Name : Expand_And_Dimm_Action_Get +* Description : ɨ趯еļ̵͵ĶӵȺ +* ʵ 1DzǿŻĿǰֻȺؼ̵͵Ķ +* ʵ 2ȺDzǿʹͬһ̵ΪɶҪֿΪɶҪŪ ʽDzǿŻ +* ̵ͷֿĻֻһ顣Ǻ滹һα +* Input : +* DevActionInfo - Ϣ +* expand_type - ̵Ⱥ +* dimm_type - Ⱥ +* on_off - Ⱥ״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Expand_And_Dimm_Action_Get(DEV_ACTION_INFO *DevActionInfo,EXPAND_TYPE_G *expand_type,DIMM_TYPE_G *dimm_type,uint8_t on_off) +{ + uint8_t TNum = 0x00; //ַͬ + uint8_t i = 0x00,j = 0x00; + + uint8_t expandexnum=0; //̵ڼ + #if RS485_LED_Flag + uint8_t dimmexnum=0; //ڼ + #endif + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + //̵ ״̬ + if( (expandexnum == 0) && (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == Dev_Host_HVout) ) + { + expand_type[expandexnum].Addr = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr; + expandexnum++; + }else if( (expandexnum > 0) && (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == Dev_Host_HVout) ) + { + for(j = 0; j <= expandexnum; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + TNum++; + break; + } + } + + if(TNum == 0x00) + { + expand_type[expandexnum].Addr = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr; + expandexnum++; + } + else if(TNum > 0) + { + TNum = 0x00; + } + } + +#if RS485_LED_Flag + //豸 ״̬ + if( (dimmexnum == 0x00) && (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == DEV_RS485_PWM) ) + { + dimm_type[dimmexnum].Addr = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr; + dimmexnum++; + } + else if( (dimmexnum > 0) && (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == DEV_RS485_PWM) ) + { + for(j = 0; j <= dimmexnum; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr) + { + TNum++; + break; + } + } + + if(TNum == 0x00) + { + dimm_type[dimmexnum].Addr = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr; + dimmexnum++; + } + else if(TNum > 0) + { + TNum = 0x00; + } + } +#endif + } + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) //һαͬ豸ŵһ + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) //ִвŲж + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == Dev_Host_HVout) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop < HVoutNumMAX) + { + for(j = 0 ; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + expand_type[j].ExpandReadFlag|= 0x01<DevActionOutput[i].DevActionOutCfg.DevOutputLoop; //Ʊ־λ - λ + if(on_off == 0x01) + { + expand_type[j].ExpandReadState[DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop]= DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState; + }else if(on_off == 0x00) + { + expand_type[j].ExpandReadState[DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop]= DEV_CTRLWAY_CLOSE; + } + } + } + } + } +#if RS485_LED_Flag + else if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType == DEV_RS485_PWM) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop < LED_OUT_CH_MAX) + { + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr) + { + dimm_type[j].DimmReadFlag |= 0x01<DevActionOutput[i].DevActionOutCfg.DevOutputLoop; + if(on_off == 0x01) + { + dimm_type[j].DimmReadState[DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop] = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState; + }else if(on_off == 0x02) + { + dimm_type[j].DimmReadState[DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop] = DEV_CTRLWAY_CLOSE; + } + } + } + } + } +#endif + } + } +} + +/******************************************************************************* +* Function Name : RcuLockState_Scan +* Description : RCU״̬ɨ - Ȩȡر +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void RcuLockState_Scan(void) +{ + uint8_t LockState; + + LockState = Get_Authorize_Lock_Status(); //õRCU״̬ 1 0 + if(DevActionGlobal.DevActionU64Cond.RcuLockState != LockState) + { + DevActionGlobal.DevActionU64Cond.RcuLockState = LockState; //ͬ + switch(DevActionGlobal.DevActionU64Cond.RcuLockState) + { + case 0x01: // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"RCUȡر"); + //Ele_Ctrl_OpenClose(0x02); //ϵ + break; + case 0x00: // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"RCUѽӭʹ"); + break; + } + } +} + +/******************************************************************************* +* @Function Name : CondJudge +* @Description : ж +* @Input : +* State1 е0x00 жϣֵ:жֵ +* State2 ʵ״ֵ̬ +* @Return 1 0 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t CondJudge(uint8_t State1, uint8_t State2) +{ + if( (0x00 == State1) || ( (0x00 != State1) && (State1 == State2) )) + { + return CondIsPass; + }else{ + return CondIsNotPass; + } +} + +/******************************************************************************* +* @Function Name : BLV_DevAction_Cond_Judge +* @Description : 豸жϺ +* @Input : +* DevActionAddr : 豸ַ +* @Return 1 0 Ҫ ȫ8λ ͨ56λ +* @Attention : ж8ֽڵͷ1ͷ0 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_DevAction_Cond_Judge(DEV_ACTION_INFO *DevActionInfo) +{ + + if(0x01 == DevActionInfo->DevActionCond.DevActionU64Cond.DevActionOutFlag) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,""); + return CondIsNotPass; //ֱӷ + } + + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.RoomState, DevActionGlobal.DevActionU64Cond.RoomState)){Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"̬δжͨ"); return CondIsNotPass; } //̬ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.EleState, DevActionGlobal.DevActionU64Cond.EleState)){Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"ȡδжͨ"); return CondIsNotPass; } //ȡ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.DndState, DevActionGlobal.DevActionU64Cond.DndState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.CleanState, DevActionGlobal.DevActionU64Cond.CleanState)){Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.CallState, DevActionGlobal.DevActionU64Cond.CallState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.WashState, DevActionGlobal.DevActionU64Cond.WashState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"ϴδжͨ"); return CondIsNotPass; } //ϴ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.CheckOutState, DevActionGlobal.DevActionU64Cond.CheckOutState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"˷δжͨ"); return CondIsNotPass; } //˷ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.WaitState, DevActionGlobal.DevActionU64Cond.WaitState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"Ժδжͨ"); return CondIsNotPass; } //Ժ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.SosState, DevActionGlobal.DevActionU64Cond.SosState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"SOSδжͨ"); return CondIsNotPass; } //SOS + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.RentState, DevActionGlobal.DevActionU64Cond.RentState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"ԤԼδжͨ"); return CondIsNotPass; } //ԤԼ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.LockState, DevActionGlobal.DevActionU64Cond.LockState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.LuggageState, DevActionGlobal.DevActionU64Cond.LuggageState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.StrongState, DevActionGlobal.DevActionU64Cond.StrongState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.DoorState, DevActionGlobal.DevActionU64Cond.DoorState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"Ŵδжͨ"); return CondIsNotPass; } //Ŵ + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.SeasonState, DevActionGlobal.DevActionU64Cond.SeasonState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"δжͨ"); return CondIsNotPass; } // + if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.TimeState, DevActionGlobal.DevActionU64Cond.TimeState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"ʱδжͨ"); return CondIsNotPass; } //ʱ +// if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag, DevActionInfo->DevActionCond.DevActionU64Cond.NeightState, DevActionGlobal.DevActionU64Cond.NeightState)){Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"ҹδжͨ"); return CondIsNotPass; } //ҹ +// if(CondIsNotPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.RcuLockState, DevActionGlobal.DevActionU64Cond.RcuLockState)) {Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"Ȩδжͨ,:%s",DevActionInfo->DevActionCore.DevActionName); return CondIsNotPass; } // DevActionGlobal.DevActionU64Cond.RcuLockState + + if( (0x00 != DevActionInfo->DevActionCond.DevActionU64Cond.RcuLockState) + && ( ((0x01 == DevActionInfo->DevActionCond.DevActionU64Cond.RcuLockState)&&(0x00 == DevActionGlobal.DevActionU64Cond.RcuLockState)) + ||((0x02 == DevActionInfo->DevActionCond.DevActionU64Cond.RcuLockState)&&(0x01 == DevActionGlobal.DevActionU64Cond.RcuLockState) ) ) ) + { + // + Dbg_Println(DBG_BIT_ActCond_STATUS_bit,"Ȩδжͨ,:%s",DevActionInfo->DevActionCore.DevActionName); + return CondIsNotPass; + } + + return CondIsPass; +} + +/******************************************************************************* +* Function Name : Expand_State_Get +* Description : չ״̬õ иóµл·״̬ +* Ż Ż˼· +* 1ȺصĿΪ˼ٴⲿSRAMȡ豸ݣȻ˶ȡ豸ݣˣʱ +* 2ĿDZǰж·״̬Ӷжϵǰ״̬ǿǹأÿ豸״̬һв߼ת +* 細״̬жϣɫ״̬жϡ +* ЩжӦ豸ɣӦ豸ִת +* ʵ㣺 +* if(DevActionInfo->DevActionCond.SceneExcute != ACTION_SCENE_SLEEP) жʲôΪʲô˯ģʽ²ж +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Expand_State_Get(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0x00,j = 0x00; + uint32_t DevAddrOut = 0x00; //豸ֲַ + uint8_t DevCtrlWay = 0x00; //ִзʽ + uint8_t DevCtrlCont = 0x00; //ִ + uint8_t SceneState = DEV_STATE_OPEN; + uint8_t SceneType = 0x01; + + Device_Public_Information_G BUS_Public; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x01); //̵͵Ķ + + /* + * 1Ȼѭеļ̵ͣжٸѭٴ + * 2жϵ̵ͻʱҪѭ30ȺҵǰӦȺ + * */ + for(i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: //̵豸 + for(j = 0;j < Action_Group_Ctrl_Num;j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if(expand_type[j].ExpandReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevActionInfo->DevActionOutput[i].DevActionOutAddr); //й + if(NULL != BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr) + { + if(DEV_STATE_CLOSE == BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr(DevActionInfo->DevActionOutput[i].DevActionOutAddr, SceneType, expand_type[j].ExpandReadFlag, HVoutNumMAX, expand_type[j].ExpandReadState)) + { + SceneState = DEV_STATE_CLOSE; + } + } + expand_type[j].ExpandReadFlag=0x00; //ȡ־λ㣬ͬĵַ㲻ڽж + } + break; //ҵ豸ӦȺַ ,ֱ˳ + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: //豸 + for(j = 0;j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if(0x00!=dimm_type[j].DimmReadFlag) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevActionInfo->DevActionOutput[i].DevActionOutAddr); //й + if(NULL != BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr) + { + if(DEV_STATE_CLOSE == BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr(DevActionInfo->DevActionOutput[i].DevActionOutAddr, SceneType, dimm_type[j].DimmReadFlag, LED_OUT_CH_MAX, dimm_type[j].DimmReadState)) + { + SceneState = DEV_STATE_CLOSE; + } + } + dimm_type[j].DimmReadFlag = 0x00; //ȡ־λ㣬ͬĵַ㲻ڽж + } + break; //ҵ豸ӦȺַ ,ֱ˳ + } + } + break; +#endif + } + } + } + + for(i = 0;i < DevActionInfo->DevCtrlNum; i++) + { + //ж϶ʱҶӦ豸ַǿ + if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00) + && (DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00 ) ) + { + switch( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType ) + { + case Dev_Host_LVoutput: + case DEV_RS485_SWT: + case Dev_Host_Service: + case Dev_Scene_Restore: + if(DevActionInfo->DevActionCond.SceneExcute != ACTION_SCENE_SLEEP) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); //ȡ豸Ϣ + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) || (DevCtrlWay == DEV_CTRLWAY_CLOSE) || (DevCtrlWay == DEV_CTRLWAY_STOP) ) + { + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlWay) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + } + break; +#if RS485_PB20_Relay_Flag + case Dev_Rs485_PB20_Relay: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) || (DevCtrlWay == DEV_CTRLWAY_CLOSE) || (DevCtrlWay == DEV_CTRLWAY_STOP) ) + { + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlWay) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + break; +#endif + case Dev_NodeCurtain: //豸 - + case DEV_RS485_CURTAIN: //RS485豸 - + if(DevActionInfo->DevActionCond.SceneExcute != ACTION_SCENE_SLEEP) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) \ + || (DevCtrlWay == DEV_CTRLWAY_CLOSE) \ + || (DevCtrlWay == DEV_CTRLWAY_STOP) \ + || (DevCtrlWay == 0x15) \ + || (DevCtrlWay == 0x16) ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlWay) + { + SceneState = DEV_STATE_CLOSE; + break; + } + }else if( (DevCtrlWay == CFG_Dev_CtrlWay_Is_TOGGLE) || (DevCtrlWay == 0x05) ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DEV_CTRLWAY_STOP) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + } + break; +#if Dev_Nor_ColorTemp + case Dev_Nor_ColorTemp: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + DevCtrlCont = ((DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)>>8)&0x00ff; + + if(DevCtrlWay == DEV_CTRLWAY_OPEN) + { + DevCtrlCont |= 0x80; + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlCont ) + { + SceneState = DEV_STATE_CLOSE; + break; + } + }else if(DevCtrlWay == DEV_CTRLWAY_CLOSE) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != (DevCtrlCont & 0x80) ) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + break; +#endif + case DEV_C5MUSIC_Type: + if(DevActionInfo->DevActionCond.SceneExcute != ACTION_SCENE_SLEEP) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DEV_MUSIC_CTRLSTATE DevMusicCtrlState; + BLV_Music_CtrlState_Get(&DevMusicCtrlState,DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + if(DevMusicCtrlState.DevMusicCtrlWay.CtrlDirect == 0x00) //ʵ - ̫ + { + DevCtrlWay = DevMusicCtrlState.DevMusicCtrlWay.CtrlDir; + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) \ + || (DevCtrlWay == DEV_CTRLWAY_CLOSE) ) + { + if(DevCtrlWay != BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop)) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + } + } + break; +#if Dev_Nor_Carbon_Flag + case DEV_Carbon_Saved: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); //й + if(NULL != BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get) //ǿ + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; //ֽ + DevCtrlCont = ((DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)>>8)&0x00ff; //ֽ + if(0x01 == DevCtrlWay) //ҿƽ״̬ ͹ + { + if(DevCtrlCont != BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop)) + { + SceneState = DEV_STATE_CLOSE; //ֻҪһ״̬ ʱ״̬Ϊ + break; //switchѭ + } + } + } + break; +#endif + } + } + if(SceneState == DEV_STATE_CLOSE) break; + } + + if(DevActionInfo->DevActionState.SceneState != SceneState) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit," ǰ:%d ״̬:%d", DevActionInfo->DevActionCore.ActionNo, SceneState); + DevActionInfo->DevActionState.SceneState = SceneState; //1 2 0δʼ + } +} + +/******************************************************************************* +* Function Name : Sleep_State_Get +* Description : ˯ģʽ״̬ȡ +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Sleep_State_Get(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i;//,j; + + uint32_t DevAddrOut = 0x00; //豸ֲַ + Device_Public_Information_G BUS_Public; // + uint8_t DevCtrlWay = 0x00; //ִзʽ + uint8_t DevCtrlCont = 0x00; //ִ + uint8_t SceneState = DEV_STATE_OPEN; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x01); + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + DevAddrOut = DevActionInfo->DevActionOutput[i].DevActionOutAddr; + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: //̵ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) == DEV_STATE_OPEN) + { + SceneState = DEV_STATE_CLOSE; //ֵֻ + break; + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != 0x00) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + break; +#endif + } + } + } + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00) + && (DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) ) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Rs485_PB20_Relay: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) || (DevCtrlWay == DEV_CTRLWAY_CLOSE) || (DevCtrlWay == DEV_CTRLWAY_STOP) ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlWay ) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + break; + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00 ) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00ff); + DevCtrlCont = ((DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState) >> 8) & 0x00ff; + + // - + + } + break; + case DEV_Virtual_ColorTemp: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + DevCtrlCont = ((DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)>>8)&0x00ff; + + if( (DevCtrlWay == DEV_CTRLWAY_OPEN) || (DevCtrlWay == DEV_CTRLWAY_CLOSE) ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) != DevCtrlCont ) + { + SceneState = DEV_STATE_CLOSE; + break; + } + } + } + break; + } + } + if(DEV_STATE_CLOSE == SceneState) break; + } + + if(DevActionInfo->DevActionState.SceneState != SceneState) + { + DevActionInfo->DevActionState.SceneState = SceneState; + } +} + +/******************************************************************************* +* Function Name : MainSwitch_Expand_State_Get +* Description : ܿչ״̬õ +* ע:ܿسжϿĵƣһƿ״̬Ϊȫز +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void MainSwitch_Expand_State_Get(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0,j = 0; + uint32_t DevAddrOut = 0x00; + Device_Public_Information_G BUS_Public; // + uint8_t DevCtrlWay = 0x00; //ִзʽ + uint8_t DevCtrlCont = 0x00; //ִ + uint8_t SceneState = DEV_STATE_CLOSE; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x01); + + for(i = 0;i < DevActionInfo->DevCtrlNum; i++) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutAddr != DevAddrOut ) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: //̵ + for(j = 0;j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if(expand_type[j].ExpandReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr != 0x00) + { + if(BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr(DevAddrOut, DEV_STATE_CLOSE, expand_type[j].ExpandReadFlag, HVoutNumMAX, expand_type[j].ExpandReadState) == DEV_STATE_OPEN) + { + SceneState = DEV_STATE_OPEN; + } + } + expand_type[j].ExpandReadFlag=0x00; //Ʊ־λ + } + break; + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + for(j = 0;j < Action_Group_Ctrl_Num; j++) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr ) + { + if( dimm_type[j].DimmReadFlag != 0x00 ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr != 0x00 ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_Group_State_Get_ptr(DevAddrOut, DEV_STATE_CLOSE, dimm_type[j].DimmReadFlag, LED_OUT_CH_MAX, dimm_type[j].DimmReadState) == DEV_STATE_OPEN ) + { + SceneState = DEV_STATE_OPEN; + } + } + dimm_type[j].DimmReadFlag=0x00; //Ʊ־λ + } + break; + } + } + break; +#endif + } + } + } + + for( i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00 ) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case DEV_RS485_STRIP: + case Dev_Rs485_PB20: + case DEV_Virtual_ColorTemp: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00 ) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + DevCtrlCont = ((DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)>>8)&0x00ff; + + if(DevCtrlWay == DEV_STATE_OPEN) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) == DevCtrlCont ) + { + SceneState = DEV_STATE_OPEN; + break; + } + } + } + break; + case Dev_Scene_Restore: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get != 0x00 ) + { + DevCtrlWay = (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState)&0x00ff; + if( (DevCtrlWay == DEV_STATE_OPEN) || (DevCtrlWay == DEV_STATE_CLOSE) ) + { + if( BUS_Public.DevFunInfo.Dev_Output_Loop_State_Get(DevAddrOut, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop) == DevCtrlWay ) + { + SceneState = DEV_STATE_OPEN; + break; + } + } + } + break; + } + } + if(SceneState == DEV_STATE_OPEN) break; //forѭ + } + } + + DevActionInfo->DevActionState.SceneState = SceneState; +} + +/******************************************************************************* +* Function Name : DevAction_State_Get +* Description : 豸״̬õ +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_State_Get(DEV_ACTION_INFO *DevActionInfo) +{ + switch(DevActionInfo->DevActionCond.SceneExcute) //ݶǰִзʽ + { + case ACTION_SCENE_SLEEP: //豸ִзʽ - ˯ģʽ + if(DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01) //ҹƴ + { + if(DevActionGlobal.DevActionU64Cond.NeightState == NightModeStart) //ҹ ֵȫֶ + { + DevActionInfo->DevActionState.SceneState = DEV_STATE_OPEN; //ҹ - + if( DevActionGlobal.SleepLight_State != 0x01 ) + { + DevActionGlobal.SleepMode_State = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳ 5"); + } + } + + if(DevActionGlobal.CardInFlag == 0x01) //ס־λ - ˯߱־λ + { + Sleep_State_Get(DevActionInfo); + if(DevActionInfo->DevActionState.SceneState == DEV_STATE_CLOSE) //ǰ ҹƴڵĻ,Ϊʱر˯ģʽ - ʵ + { + DevActionGlobal.CardInFlag = 0x00; + DevActionGlobal.SleepMode_State = 0x00; + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -5"); + } + } + break; //ҹ ֱ + }else { + Expand_State_Get(DevActionInfo); + if(DevActionInfo->DevActionState.SceneState == DEV_STATE_CLOSE) + { + if(DevActionGlobal.CardInFlag == 0x01) + { + DevActionGlobal.CardInFlag = 0x00; + DevActionGlobal.SleepMode_State = 0x00; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -6"); + } + } + } + break; + case ACTION_SCENE_ONE: //豸ִзʽ - ɹر + case ACTION_SCENE_TWO: //豸ִзʽ - ɹر + case ACTION_SCENE_HELPSLEEP: //豸ִзʽ - ߳ + Expand_State_Get(DevActionInfo); + break; + case ACTION_SCENE_MAINSWITCH: //豸ִзʽ - ܿ + MainSwitch_Expand_State_Get(DevActionInfo); //״̬õ + break; + } + + if( DevActionGlobal.DevActionU64Cond.NeightState != DevActionGlobal.Last_NeightState ) + { + DevActionGlobal.Last_NeightState = DevActionGlobal.DevActionU64Cond.NeightState; + } +} + +/******************************************************************************* +* Function Name : DevDly_InfoSet +* Description : ʱִУϢֱӸֵ +* Input : + DevDlyAddr : ʱĽڵַ + DlyExcuteFlag ʱִб־ + DevOutputType ִзʽ + DevDelayTime ִʱ + DlyBlinkFlag ˸־λ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevDly_InfoSet( + uint32_t DevDlyAddr, + uint8_t DlyExcuteFlag, + uint16_t DevOutputType, + Dev_Dly_Value DevDelayTime, + uint8_t DlyBlinkFlag) +{ + Struct_Dev_Dly DevDlyInfo; + Dev_Dly_Value DevDlyValue; + uint32_t DlyExcuteTime = 0x00; + + if( DevDlyAddr == 0x00 ) return ; + + DevDlyValue.DelayCont = DevDelayTime.DelayCont; + DevDlyValue.DelayWeight = DevDelayTime.DelayWeight; + + switch(DevDlyValue.DelayWeight) + { + case 0x00: //λΪ0׼ʱ + DlyExcuteTime = 0x00; + break; + case DELAY_TIME_MS: //0x01 // + DlyExcuteTime = SysTick_1ms + DevDlyValue.DelayCont; + break; + case DELAY_TIME_S: //0x02 // + DlyExcuteTime = SysTick_1ms + DevDlyValue.DelayCont*1000; + break; + case DELAY_TIME_MIN: //0x03 // + DlyExcuteTime = SysTick_1ms + DevDlyValue.DelayCont*1000*60; + break; + case DELAY_TIME_HOUR: //0x04 //Сʱ + DlyExcuteTime = SysTick_1ms + DevDlyValue.DelayCont*1000*60*60; + break; + default: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱλΪЧ:", DevDlyValue.DelayWeight); + return; //ֱӷ + } + + SRAM_DMA_Read_Buff((uint8_t *)&DevDlyInfo, sizeof(Struct_Dev_Dly), DevDlyAddr); //״̬ȡ + + if( ( DevDlyInfo.DlyExcuteTime != DlyExcuteTime ) + || ( DevDlyInfo.DlyExcuteFlag != DlyExcuteFlag ) + || ( DevDlyInfo.DevOutputType != DevOutputType ) + || ( DevDlyInfo.DlyBlinkFlag != DlyBlinkFlag ) + || ( DevDlyInfo.DlyBlinkTime.DelayCont != DevDelayTime.DelayCont ) + || ( DevDlyInfo.DlyBlinkTime.DelayWeight != DevDelayTime.DelayWeight ) ) + { + DevDlyInfo.DlyExcuteFlag = DlyExcuteFlag; + DevDlyInfo.DevOutputType = DevOutputType; + switch(DlyBlinkFlag) + { + case 0x01: //˸ + DevDlyInfo.DlyBlinkFlag = DlyBlinkFlag; + DevDlyInfo.DlyExcuteTime = DlyExcuteTime; + + break; + case 0x02: //ر˸ ¸ֵʱʱ + if(0x01 == DevDlyInfo.DlyBlinkFlag) //֮ǰǿ˸״̬ + { + DevDlyInfo.DlyBlinkFlag = DlyBlinkFlag; + } + break; + default: + DevDlyInfo.DlyBlinkFlag = DlyBlinkFlag; + DevDlyInfo.DlyExcuteTime = DlyExcuteTime; + break; + } + + DevDlyInfo.DlyBlinkTime.DelayCont = DevDelayTime.DelayCont; + DevDlyInfo.DlyBlinkTime.DelayWeight = DevDelayTime.DelayWeight; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱڵ㸳ֵڵַ:%08X ִб־:%d ʱ:%02x%02x, ִзʽ:%04X ˸־:%d", \ + DevDlyAddr, DlyExcuteFlag, \ + DevDlyValue.DelayCont, \ + DevDlyValue.DelayWeight, \ + DevOutputType, \ + DevDlyInfo.DlyBlinkFlag); + + SRAM_DMA_Write_Buff((uint8_t *)&DevDlyInfo, sizeof(Struct_Dev_Dly), DevDlyAddr); //״̬ȡ + } +} + +/******************************************************************************* +* Function Name : DevDlyAddr_Get +* Description : 豸Ϣͻ·õʱڵ +* Input : + DevDlyAddr : ʱĽڵַ + DevOutputLoop ʱ· +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t DevDlyAddr_Get(uint32_t DevDlyAddr, uint16_t DevOutputLoop) +{ + uint16_t i = 0x00; + uint32_t list_addr = 0x00; + Struct_Dev_Dly_Core DevDlyCore; + + for(i = 0; i < DevActionGlobal.DevDlyNum; i++) + { + list_addr = SRAM_DevDly_List_Start_Addr + i * DevDlyStructLen; + SRAM_DMA_Read_Buff((uint8_t *)&DevDlyCore, sizeof(Struct_Dev_Dly_Core), list_addr); + + if( (DevDlyCore.DevDlyAddr == DevDlyAddr) && (DevDlyCore.DevOutputLoop == DevOutputLoop) ) + { + return list_addr; + } + } + return 0x00; +} + +/******************************************************************************* +* Function Name : Add_DevDly_To_List +* Description : ʱ豸Ϣӵ +* ҪʱĽڵӵ½ڵ㣬ͷµĵַǾɽڵ㣬ͷؾɵַ +* Input : + DevType : 豸 + DevDlyAddr 豸ڵַ + DevOutputLoop ·ַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Add_DevDly_To_List(uint8_t DevType, uint32_t DevDlyAddr, uint16_t DevOutputLoop) +{ + uint32_t list_addr = 0x00; + Struct_Dev_Dly_Core DevDlyCore; + + if(DevActionGlobal.DevActionNum >= DevDlyNumMax) //ʱ豸Χͷ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱ豸ӳΧ ʱ豸: %d", DevDlyNumMax); + return 0x00; + } + list_addr = DevDlyAddr_Get(DevDlyAddr, DevOutputLoop); //ǰʱڵ + if(list_addr != 0x00) return list_addr; //ֱӽַ + + DevDlyCore.DevType = DevType; + DevDlyCore.DevDlyAddr = DevDlyAddr; + DevDlyCore.DevOutputLoop = DevOutputLoop; // + list_addr = SRAM_DevDly_List_Start_Addr + DevActionGlobal.DevDlyNum*DevDlyStructLen; + + SRAM_DMA_Write_Buff((uint8_t *)&DevDlyCore, sizeof(Struct_Dev_Dly_Core), list_addr); + DevActionGlobal.DevDlyNum++; //ʱڵ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱ豸ӳɹǰʱڵַ:%08X ǰʱ豸:%d ʱ豸ַ: %08X ʱ豸·%d", + list_addr , + DevActionGlobal.DevDlyNum, + DevDlyCore.DevDlyAddr, + DevDlyCore.DevOutputLoop); + + /*ǰеʱ豸ڹģͲӣڵľ*/ + return list_addr; //Чĵַ +} + +/******************************************************************************* +* Function Name : DevAddrCtr +* Description : 豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t DevAddrCtr(DEV_ACTION_INFO *DevActionInfo, uint8_t *p, uint8_t DataLen) +{ + uint8_t Ret = 0x02; //Ĭϲ + uint32_t DevAddrOut = 0x00; //豸ֲַ + Dev_Action_Output DevActionOutput; + + memset((uint8_t *)&DevActionOutput, 0x00, sizeof(Dev_Action_Output)); + + switch(DataLen) + { + case DevCtrlLen: + case DevCtrlDlyLenAddr: + memcpy((uint8_t *)&DevActionOutput, p, DataLen); + break; + default: + return Ret; + } + switch(DataLen) + { + case DevCtrlLen: //6ֽ ҪԼ豸 + DevAddrOut = Find_AllDevice_List_Information(DevActionOutput.DevActionOutCfg.DevType, DevActionOutput.DevActionOutCfg.DevAddr); + break; + case DevCtrlDlyLenAddr: //ʱַƣʱ豸ַ + DevAddrOut = DevActionOutput.DevActionOutAddr; + break; + } + + if(DevAddrOut == 0x00) return Ret; + Ret = 0x01; + + if( DevActionOutput.DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) + { + Device_Public_Information_G BUS_Public; + + DevDly_InfoSet( + DevActionOutput.DevDlyAddr, + 0x00, + DevActionOutput.DevActionOutCfg.DevCtrlState, + DevActionOutput.DevActionOutCfg.DevDlyValue, + 0x00); + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + switch(DevActionOutput.DevActionOutCfg.DevType) + { + case DEV_RS485_SWT: + case DEV_RS485_WxLock: + case Dev_Host_Service: + case Dev_Host_HVout: + case Dev_Host_LVoutput: + case Dev_NodeCurtain: + case DEV_RS485_CURTAIN: + case DEV_RS485_IR_SEND: + case DEV_RS485_TEMP: + case DEV_RS485_FreshAir: + case DEV_RS485_HEATER: + case Dev_Energy_Monitor: + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionOutput.DevActionOutCfg.DevType, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + } + } + break; + case DEV_RS485_PWM: + case DEV_RS485_STRIP: + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + case Dev_Rs485_PB20_Relay: + case DEV_Virtual_ColorTemp: + case Dev_Virtual_GlobalSet: + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL ) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionOutput.DevActionOutCfg.DevType, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState); + } + } + break; + } + }else if( (DevActionOutput.DevActionOutCfg.DevDlyValue.DelayCont != 0x00) && (DevActionOutput.DevDlyAddr != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionOutput.DevActionOutCfg.DevType, + DevActionOutput.DevActionOutCfg.DevOutputLoop, + DevActionOutput.DevActionOutCfg.DevCtrlState, + DevActionOutput.DevActionOutCfg.DevDlyValue.DelayCont, + DevActionOutput.DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet( + DevActionOutput.DevDlyAddr, + 0x01, + DevActionOutput.DevActionOutCfg.DevCtrlState, + DevActionOutput.DevActionOutCfg.DevDlyValue, + 0x00); + } + + return Ret; +} + +/******************************************************************************* +* Function Name : DevActionCtrl +* Description : 豸ר +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t DevActionCtrl(uint8_t *p, uint8_t DataLen) +{ + uint8_t Ret = 0x02; //Ĭʧ + uint16_t SceneCtrlNo = 0x00; //Ƶij + uint16_t SceneCtrlState = 0x00; + + if(DevCtrlLen != DataLen) return Ret; + + switch(p[0]) + { + case Dev_Host_Invalid: + DevActionGlobal.ServerCtrl = 0x01; + SceneCtrlNo = p[3]; + SceneCtrlNo <<= 0x08; + SceneCtrlNo |= p[2]; + + SceneCtrlState = p[5]; + SceneCtrlState <<= 0x08; + SceneCtrlState |= p[4]; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ƴ :%d", SceneCtrlNo); + if(SceneCtrlNo == DevActionGlobal.SleepActionNo) p[4] = 0x02; + DevAction_No_Ctrl(SceneCtrlNo, 0x01, SceneCtrlState); + break; + default: + Ret = DevAddrCtr(NULL, p, DataLen); + break; + } + return Ret; +} + +/******************************************************************************* +* Function Name : Ele_Ctrl_OpenClose +* Description : ȡȡ״̬ +* Input : + Ctrl : 0x01-0x00- +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Ele_Ctrl_OpenClose(uint8_t Ctrl) +{ + uint8_t DataBuf[6]; + + DataBuf[0] = Dev_Host_Service; + DataBuf[1] = 0x00; + DataBuf[2] = 0x00; + DataBuf[3] = 0x00; + DataBuf[4] = Ctrl; + DataBuf[5] = 0x00; + + DevAddrCtr(NULL, DataBuf, 0x06); //忨ȡ +} + +/******************************************************************************* +* Function Name : DevAction_ExpandCtrl +* Description : չ״̬ƺ +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ExpandCtrl(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0,j = 0; + uint32_t DevAddrOut = 0x00; //豸ֲַ + Device_Public_Information_G BUS_Public; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x01); + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != DevAddrOut) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if( expand_type[j].ExpandReadFlag != 0x00 ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != 0x00 ) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + expand_type[j].ExpandReadFlag, + HVoutNumMAX, + expand_type[j].ExpandReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"̵״̬Ⱥؿƿʼ·־:%08X :%s ", + expand_type[j].ExpandReadFlag, + DevActionInfo->DevActionCore.DevActionName); + + } + expand_type[j].ExpandReadFlag=0x00; + } + break; //ɣֱ˳ǰѭ + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + for(j = 0; j < Action_Group_Ctrl_Num; j++ ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr ) + { + if( dimm_type[j].DimmReadFlag != 0x00 ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != 0x00 ) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + dimm_type[j].DimmReadFlag, + LED_OUT_CH_MAX, + dimm_type[j].DimmReadState); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"PWM״̬Ⱥؿƿʼַ:%d·־:%08X :%s ", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + dimm_type[j].DimmReadFlag, + DevActionInfo->DevActionCore.DevActionName); + + } + dimm_type[j].DimmReadFlag = 0x00; + } + break; //ɣֱ˳ǰѭ + } + } + break; +#endif + } + } + } + + for(i = 0; i < DevActionInfo->DevCtrlNum ; i++ ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) + { + //ʱִб־λ + DevDly_InfoSet( + DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case DEV_RS485_SWT: + case DEV_RS485_WxLock: + case Dev_Host_Service: + case Dev_Host_LVoutput: + case Dev_NodeCurtain: + case DEV_RS485_IR_SEND: + case DEV_RS485_TEMP: + case DEV_RS485_CURTAIN: + case DEV_RS485_FreshAir: + case DEV_RS485_HEATER: + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + case Dev_Rs485_PB20_Relay: + case DEV_Virtual_NoCard: + case DEV_Virtual_Card: + case Dev_485_BLE_Music: + case DEV_Carbon_Saved: + case Dev_Scene_Restore: + case Dev_Energy_Monitor: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( (DevActionInfo != NULL) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); //Ϣ״ֵ̬ + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + } + } + break; + case DEV_RS485_STRIP: + case DEV_Virtual_ColorTemp: + case Dev_Virtual_GlobalSet: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( (DevActionInfo != NULL) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); //Ϣ״ֵ̬ + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + } + } + break; + case DEV_RS485_MUSIC: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( ( DevActionInfo != NULL ) + && ( CondIsPass == CondJudge(DevActionInfo->DevActionCond.DevActionU64Cond.WarningState, DevActionGlobal.DevActionU64Cond.WarningState) ) ) + { + DEV_MUSIC_CTRLSTATE DevMusicCtrlState; //ֿ״̬ + BLV_Music_CtrlState_Get(&DevMusicCtrlState,DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + + switch(DevMusicCtrlState.DevMusicCtrlWay.CtrlDirect) + { + case 0x03: // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ִбָļпţ·:%d ״̬: %04X",DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); //ִпָ + break; + case 0x04: //ز + break; + default: // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ִбֿػģʽƣַ:%d ·:%d״̬: %04X",BUS_Public.addr, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); //ִпָ + break; + } + } + } + break; + } + } + else if( ( 0x00 != DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont ) + && ( 0x00 != DevActionInfo->DevActionOutput[i].DevDlyAddr ) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet( + DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x01, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + } + } + } +} + +/******************************************************************************* +* Function Name : DevAction_ExpandLightOpen +* Description : չƹ豸ƺ ߳ +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ExpandLightOpen(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0,j = 0; + uint32_t DevAddrOut = 0; + Device_Public_Information_G BUS_Public; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x01); + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if( expand_type[j].ExpandReadFlag != 0x00 ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL ) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + expand_type[j].ExpandReadFlag, + HVoutNumMAX, + expand_type[j].ExpandReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"̵Ⱥؿƣ·־:%08X :%s ", + expand_type[j].ExpandReadFlag, + DevActionInfo->DevActionCore.DevActionName); + + } + expand_type[j].ExpandReadFlag=0x00; + } + break; + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr ) + { + if( dimm_type[j].DimmReadFlag != 0x00 ) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + dimm_type[j].DimmReadFlag, + LED_OUT_CH_MAX, + dimm_type[j].DimmReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"PWMȺؿƿʼַ:%d·־:%08X :%s ", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + dimm_type[j].DimmReadFlag, + DevActionInfo->DevActionCore.DevActionName); + } + dimm_type[j].DimmReadFlag = 0x00; + } + } + } + break; +#endif + } + } + } + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutAddr == 0x00 ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) + { + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, 0x00, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, 0x00); + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_LVoutput: + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + case Dev_Rs485_PB20_Relay: + case Dev_Scene_Restore: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + }else{ + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + } + } + break; + case DEV_RS485_STRIP: + case DEV_Virtual_ColorTemp: + case Dev_Virtual_GlobalSet: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL ) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + } + } + break; + } + }else if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont != 0x00) && (DevActionInfo->DevActionOutput[i].DevDlyAddr != 0x00) ) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: + case Dev_Host_LVoutput: + case DEV_RS485_PWM: + case DEV_RS485_STRIP: + case DEV_Virtual_ColorTemp: + case Dev_Scene_Restore: + case Dev_Virtual_GlobalSet: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x01, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + break; + } + } + } + } +} + +/******************************************************************************* +* Function Name : DevAction_ExpandLightClose +* Description : չ״̬ƺ ִе豸ִ 豸ر +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ExpandLightClose(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0x00,j = 0x00; + uint32_t DevAddrOut = 0x00; + Device_Public_Information_G BUS_Public; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + Expand_And_Dimm_Action_Get(DevActionInfo,expand_type,dimm_type,0x00); + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++ ) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType ) + { + case Dev_Host_HVout: + for(j = 0; j < Action_Group_Ctrl_Num ; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if(expand_type[j].ExpandReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + expand_type[j].ExpandReadFlag, + HVoutNumMAX, + expand_type[j].ExpandReadState); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"̵״̬Ⱥؿƿʼ·־:%08X :%s ", + expand_type[j].ExpandReadFlag, + DevActionInfo->DevActionCore.DevActionName); + } + expand_type[j].ExpandReadFlag=0x00; + } + break; //ִɣֱ˳ + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + for(j = 0;j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr) + { + if(dimm_type[j].DimmReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + dimm_type[j].DimmReadFlag, + LED_OUT_CH_MAX, + dimm_type[j].DimmReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"PWM״̬Ⱥؿƿʼַ:%d·־:%08X :%s ", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + dimm_type[j].DimmReadFlag, + DevActionInfo->DevActionCore.DevActionName); + } + dimm_type[j].DimmReadFlag = 0x00; + } + break; + } + } + break; +#endif + } + } + } + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00 ) + { + if( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00 ) + { + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_LVoutput: + case DEV_RS485_STRIP: + case Dev_Rs485_PB20_Relay: + case DEV_Virtual_ColorTemp: + case Dev_Scene_Restore: + case Dev_Virtual_GlobalSet: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL ) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + } + } + break; + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL ) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + } + } + break; + } + }else if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont != 0x00) && (DevActionInfo->DevActionOutput[i].DevDlyAddr != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x01, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + } + } + } +} + +/******************************************************************************* +* Function Name : DevAction_ExpandClose +* Description : չ״̬ƺ ִе豸ִ 豸ر +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ExpandClose(DEV_ACTION_INFO *DevActionInfo, uint8_t ModeCtrl) +{ + uint8_t i = 0x00,j = 0x00; + uint32_t DevAddrOut = 0x00; + Device_Public_Information_G BUS_Public; + + EXPAND_TYPE_G expand_type[Action_Group_Ctrl_Num]={0}; + DIMM_TYPE_G dimm_type[Action_Group_Ctrl_Num]={0}; + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case Dev_Host_HVout: + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == expand_type[j].Addr) + { + if(expand_type[j].ExpandReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + expand_type[j].ExpandReadFlag, + HVoutNumMAX, + expand_type[j].ExpandReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"̵״̬Ⱥؿƿʼ·־:%08X :%s ", + expand_type[j].ExpandReadFlag, + DevActionInfo->DevActionCore.DevActionName); + } + expand_type[j].ExpandReadFlag=0x00; + } + break; //ִɣֱ˳ + } + } + break; +#if RS485_LED_Flag + case DEV_RS485_PWM: + for(j = 0; j < Action_Group_Ctrl_Num; j++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr == dimm_type[j].Addr) + { + if(dimm_type[j].DimmReadFlag != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Group_Ctrl( + 0x00, + 0x00, + DevAddrOut, + dimm_type[j].DimmReadFlag, + LED_OUT_CH_MAX, + dimm_type[j].DimmReadState); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"PWM״̬Ⱥؿƿʼַ:%d·־:%08X :%s ", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + dimm_type[j].DimmReadFlag, + DevActionInfo->DevActionCore.DevActionName); + } + dimm_type[j].DimmReadFlag = 0x00; + } + break; + } + } + break; +#endif + } + } + } + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont == 0x00) + { + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case DEV_RS485_SWT: + case Dev_Host_LVoutput: + case DEV_RS485_STRIP: + case Dev_Rs485_PB20_Relay: + case DEV_Virtual_ColorTemp: + case Dev_Scene_Restore: + case Dev_Virtual_GlobalSet: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + if( (DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + }else { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + } + } + break; + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) //ǿ + { + if((DevActionInfo != 0x00) && (DevActionInfo->DevActionState.DevAddrIn != 0x00)) // + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%04X 豸:%d ַ:%04X %d· ״̬: %04X", + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + }else{ + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x0012); + } + } + break; + case Dev_NodeCurtain: //ȡΪͣ ȡΪͣ ͣȡΪ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); //й + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + switch(ModeCtrl) + { + case NOR_MODE_CTRL: + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00FF) + { + case DEV_CTRLWAY_OPEN: // + case DEV_CTRLWAY_CLOSE: // + case CFG_Dev_CtrlWay_Is_TOGGLE: // + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_STOP); + break; + case 0x15: //ʱƿ + case 0x16: //ʱƹ - ɹرʱʱƹر״̬Ϊ0x17 + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + 0x17); + break; + case DEV_CTRLWAY_STOP: + break; + } + break; + case SLEEP_MODE_CTRL: + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + break; + } + } + break; + case DEV_RS485_CURTAIN: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if( BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL ) + { + switch(ModeCtrl) + { + case NOR_MODE_CTRL: //ͨģʽ + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00FF) + { + case DEV_CTRLWAY_OPEN: + case DEV_CTRLWAY_CLOSE: + case CFG_Dev_CtrlWay_Is_TOGGLE: + case 0x05: + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + DevActionInfo->DevActionState.DevAddrIn, + DevActionInfo->DevActionInput.inAddr, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_STOP); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"485رտ state:%4X",DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + break; + case DEV_CTRLWAY_STOP: + break; + } + break; + case SLEEP_MODE_CTRL: //˯ģʽ + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + break; + } + } + break; + case Dev_Host_Service: //˯߿ƷϢ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + switch(ModeCtrl) + { + case NOR_MODE_CTRL: //ͨģʽ Ϣ + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState) + { + case DEV_CTRLWAY_OPEN: + case DEV_CTRLWAY_CLOSE: + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_CLOSE); + break; + } + break; + case SLEEP_MODE_CTRL: //˯ģʽ Ϣ + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevAddrOut, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState); + break; + } + } + break; + } + }else if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont != 0x00) && (DevActionInfo->DevActionOutput[i].DevDlyAddr != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + } + } + } +} + +/******************************************************************************* +* Function Name : DevAction_Mode_Ctrl +* Description : ģʽ +* Input : + DevActionInfo : Ϣ + Mode 0x01-ƣ0x02-ƹ + SceneMode NOR_MODE_CTRL 0x01 ͨģʽƣSLEEP_MODE_CTRL 0x02 ˯߳ + CtrlState ״̬ 1-2- +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ExpandDlyClear(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0; + uint32_t DevAddrOut = 0x00; + Device_Public_Information_G BUS_Public; + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType != Dev_Host_Invalid) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAddrOut); + } + + if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont != 0x00) && (DevActionInfo->DevActionOutput[i].DevDlyAddr != 0x00) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"׼ʱ豸ִλ豸:%d %d· : %d,ʱ䣺%dλ%d", + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayWeight); + + DevDly_InfoSet(DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); + } + } + } +} + +/******************************************************************************* +* Function Name : DevAction_No_Get +* Description : ݳŵõĵַ +* Input : + DevActionInfo : Ϣ + Mode 0x01-ƣ0x02-ƹ + SceneMode NOR_MODE_CTRL 0x01 ͨģʽƣSLEEP_MODE_CTRL 0x02 ˯߳ + CtrlState ״̬ 1-2- +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t DevAction_No_Get(uint16_t DevActionNo) +{ + uint16_t i = 0; + uint32_t list_addr = 0; + DEV_ACTION_INFO DevActionInfo; + + for(i = 0; i < DevActionGlobal.DevActionNum; i++ ) + { + list_addr = SRAM_DevAction_List_Start_Addr + i*SRAM_DevAction_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), list_addr); + if(DevActionInfo.DevActionCore.ActionNo == DevActionNo) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"жҵӦij:%d %s", DevActionNo, DevActionInfo.DevActionCore.DevActionName); + return list_addr; //صǰĵַ + } + } + + return 0x00; +} + +/******************************************************************************* +* Function Name : DevAction_Mode_Ctrl +* Description : ģʽ +* Input : + DevActionInfo : Ϣ + Mode 0x01-ƣ0x02-ƹ + SceneMode NOR_MODE_CTRL 0x01 ͨģʽƣSLEEP_MODE_CTRL 0x02 ˯߳ + CtrlState ״̬ 1-2- +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_Mode_Ctrl( + DEV_ACTION_INFO *DevActionInfo, + uint8_t Mode, + uint8_t SceneMode, + uint16_t CtrlState) +{ + switch(CtrlState) + { + case DEV_CTRLWAY_OPEN: + switch(Mode) + { + case SCENE_MODE_CTRL: + DevAction_ExpandCtrl(DevActionInfo); + break; + case LIGHT_MODE_CTRL: + DevAction_ExpandLightOpen(DevActionInfo); + break; + } + break; + case DEV_CTRLWAY_CLOSE: + switch(Mode) + { + case SCENE_MODE_CTRL: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ͨƹرգ:%d", DevActionInfo->DevActionCore.ActionNo); + DevAction_ExpandClose(DevActionInfo, SceneMode); + break; + case LIGHT_MODE_CTRL: + DevAction_ExpandLightClose(DevActionInfo); + break; + } + break; + case DEV_CTRLWAY_INVALID: //ƷʽЧȡеʱִ + DevAction_ExpandDlyClear(DevActionInfo); + break; + } +} + +/******************************************************************************* +* Function Name : DevAction_Output +* Description : 豸ִ +* Input : + DevActionNo : + Mode 0x01-ƣ0x02-ƹ + CtrlState ״̬ 1-2- +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_No_Ctrl(uint16_t DevActionNo, uint8_t Mode, uint16_t CtrlState) +{ + uint16_t i = 0x00; //ڱж + uint32_t list_addr = 0x00; //ĵַ + DEV_ACTION_INFO DevActionInfo; + Dev_Dly_Value Temp_Dly; + + if(DevActionNo == 0x00) return ; //ֱ˳ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ж׼ִг:%d", DevActionNo); + + for(i = 0; i < DevActionGlobal.DevActionNum; i++) + { + list_addr = SRAM_DevAction_List_Start_Addr + i*SRAM_DevAction_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), list_addr); + + if(DevActionInfo.DevActionCore.ActionNo == DevActionNo) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҵӦij:%d %s洢ַ:%08X,ִУʱִб־", \ + DevActionNo, \ + DevActionInfo.DevActionCore.DevActionName, \ + list_addr); + + Temp_Dly.DelayCont = 0x00; + Temp_Dly.DelayWeight = 0x00; + DevDly_InfoSet(DevDlyAddr_Get(list_addr, DevActionNo), 0x00, 0x00, Temp_Dly, 0x00);//ʱִб־λ õʱڵĵַ + + if( (DevActionNo == ACTION_SCENE_SLEEP) || (DevActionInfo.DevActionCond.SceneExcute == ACTION_SCENE_SLEEP) ) + { + DevAction_Mode_Ctrl(&DevActionInfo, Mode, SLEEP_MODE_CTRL, CtrlState); + }else { + DevAction_Mode_Ctrl(&DevActionInfo, Mode, NOR_MODE_CTRL, CtrlState); + } + + if( DevActionGlobal.ServerCtrl == 0x01 ) + { + DevActionGlobal.ServerCtrl = 0x00; + if( DevActionInfo.DevActionCond.SceneExcute == ACTION_SCENE_SLEEP ) + { + if( DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01 ) //ҹйأҹƴ + { + if( DevActionGlobal.DevActionU64Cond.NeightState != NightModeStart) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeStart; + } + } + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ + DevActionGlobal.SleepLight_State = 0x00; //Ϩ𱳹⣬ر + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳"); + }else { + if( DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01 ) //ҹйأҹƴ + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + } + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳"); + } + } + break; + } + } +} + +/******************************************************************************* +* Function Name : DevAction_Output +* Description : 豸ִ +* Input : + DevActionInfo : 豸Ϣṹ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_Output(DEV_ACTION_INFO *DevActionInfo) +{ + switch( DevActionInfo->DevActionCond.SceneExcute ) + { + case ACTION_SCENE_ONE: + case ACTION_SCENE_MULTI: + if( ( DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01 ) + && ( 0x01 == DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag ) ) + { + switch( DevActionGlobal.DevActionU64Cond.NeightState ) + { + case NightModeStart: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹر ׼ִдҹ:"); + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_OPEN); //ҹ + if( DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT ) + { + DevActionGlobal.SleepMode_State = 0x00; + Logic_Music_Ctrl(0x00, 0x00, Find_Device_List_Information(0x15,0x01), 0x00, 0x0020); //ҹ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -1"); + } + break; + case NightModeOpen: + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_CLOSE);//رҹ + case NightModeClose: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹرտʼ豸״̬иֵ:"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + break; + } + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ɹرտʼ豸״̬иֵ:"); + DevAction_ExpandCtrl(DevActionInfo); + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -2"); + } + } + break; + case ACTION_SCENE_TWO: //ɹرգִӦ + if( (DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01) && (DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag == 0x01) ) + { + switch(DevActionGlobal.DevActionU64Cond.NeightState) + { + case NightModeStart: + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_OPEN); //ҹ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ 2025-09-05 + Logic_Music_Ctrl(0x00, 0x00, Find_Device_List_Information(0x15,0x01), 0x00, 0x0020); //ҹ + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -3"); + break; + case NightModeClose: + case NightModeOpen: + if(NightModeOpen == DevActionGlobal.DevActionU64Cond.NeightState) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_CLOSE); //رҹ + } + if(DEV_STATE_CLOSE == DevActionInfo->DevActionState.SceneState) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + } + else if(DEV_STATE_OPEN == DevActionInfo->DevActionState.SceneState) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandClose(DevActionInfo, NOR_MODE_CTRL); //ִеǰ + } + break; + } + }else { + if(DEV_STATE_CLOSE == DevActionInfo->DevActionState.SceneState) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + } + else if(DEV_STATE_OPEN == DevActionInfo->DevActionState.SceneState) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandClose(DevActionInfo, NOR_MODE_CTRL); //ִеǰ + } + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ -4"); + } + } + break; + case ACTION_SCENE_MAINSWITCH: //ܿ + + if( (DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01) && (DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag == 0x01) ) + { + switch(DevActionGlobal.DevActionU64Cond.NeightState) + { + case NightModeStart: + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_OPEN); //ҹ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + Logic_Music_Ctrl(0x00, 0x00, Find_Device_List_Information(0x15,0x01), 0x00, 0x0020); //ҹ + } + break; + case NightModeClose: + case NightModeOpen: + if(DevActionGlobal.DevActionU64Cond.NeightState == NightModeOpen) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_CLOSE); //رҹ + } + if(DevActionInfo->DevActionState.SceneState == DEV_STATE_CLOSE) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandLightOpen(DevActionInfo); //򿪵ǰĵƹ + } + else if(DevActionInfo->DevActionState.SceneState == DEV_STATE_OPEN) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandClose(DevActionInfo, SLEEP_MODE_CTRL); //ִеǰƹ豸ر + } + break; + } + }else { + if(DevActionInfo->DevActionState.SceneState == DEV_STATE_CLOSE) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandLightOpen(DevActionInfo); //򿪵ǰĵƹ + } + else if(DevActionInfo->DevActionState.SceneState == DEV_STATE_OPEN) //ǰΪ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ɹرտʼ豸״̬иֵ:׼ִг"); + DevAction_ExpandClose(DevActionInfo, SLEEP_MODE_CTRL); //ִеǰ + } + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + } + } + break; + case ACTION_SCENE_SLEEP: //˯ģʽ ȫز㿪һء + if(DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01) //ҹй ҹƴ + { + if(DevActionGlobal.DevActionU64Cond.NeightState != NightModeStart) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeStart; //ҹ + DevAction_ExpandClose(DevActionInfo, SLEEP_MODE_CTRL); //˯߳Ϊ ǵùرе Ӧ + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ + DevActionGlobal.SleepLight_State = 0x00; //Ϩ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳ 1"); + }else{ + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_ExpandLightOpen(DevActionInfo); //ҹ + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + Logic_Music_Ctrl(0x00, 0x00, Find_Device_List_Information(0x15,0x01), 0x00, 0x0020); //ҹ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˳˯߳ 1"); + } + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ˯߳ʼ豸״̬иֵ:"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ + DevActionGlobal.SleepLight_State = 0x00; //Ϩ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳ 2"); + } + break; + case ACTION_SCENE_HELPSLEEP: //ģʽ ´ҹƿ־ʱܹͨرҹƣȡ˯ߵʱ + if((DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01 )&& (DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag == 0x01)) //ҹй ҹƴ + { + switch(DevActionGlobal.DevActionU64Cond.NeightState) + { + case NightModeStart: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ׼ִдҹ:"); + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_OPEN);//ҹ ȡ˯ߵʱ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ + } + Logic_Music_Ctrl(0x00, 0x00, Find_Device_List_Information(0x15,0x01), 0x00, 0x0020); //ҹ + break; + case NightModeClose: + case NightModeOpen: + if(DevActionGlobal.DevActionU64Cond.NeightState == NightModeOpen) //ҹƱ־ + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ߽ҹƱ־ر"); + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_CLOSE);//رҹ + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ߿ʼ豸״̬иֵ:"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeStart; //ҹ + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ + DevActionGlobal.SleepLight_State = 0x00; //Ϩ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳ 3"); + } + break; + } + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ߳ʼ豸״̬иֵ:"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x01; //˯ģʽ + DevActionGlobal.SleepLight_State = 0x00; //Ϩ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˯߳ 4"); + } + } + break; +#if RS485_Switch_Rotary_Flag + case ACTION_SCENE_Rotary: //ת + if((DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01) && (DevActionInfo->DevActionCond.DevActionU64Cond.NeightFlag == 0x01)) //ҹй + { + switch(DevActionGlobal.DevActionU64Cond.NeightState) + { + case NightModeStart: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ť ׼ִдҹ:"); + DevActionGlobal.DevActionU64Cond.NeightState = NightModeOpen; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_OPEN);//ҹ + if(DevActionInfo->DevActionInput.DevType == DEV_RS485_SWT) + { + DevActionGlobal.SleepMode_State = 0x00; //˯ģʽ 2025-09-05 + } + break; + case NightModeClose: + case NightModeOpen: + if(NightModeOpen == DevActionGlobal.DevActionU64Cond.NeightState) + { + DevActionGlobal.DevActionU64Cond.NeightState = NightModeClose; + DevAction_No_Ctrl(DevActionGlobal.SleepActionNo, 0x02, DEV_CTRLWAY_CLOSE);//رҹ + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹй ť ʼ豸״̬иֵ:"); + DevAction_RotaryCtrl(DevActionInfo); + break; + } + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ťʼ豸״̬иֵ:"); + DevAction_RotaryCtrl(DevActionInfo); + } + break; +#endif + case ACTION_SCENE_SLEEP_UNRELATED: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҹ޹ ޿ȡ-ⰴ ׼ִдҹ:"); + DevAction_ExpandCtrl(DevActionInfo); //ִеǰ + break; + } + + if(DevActionGlobal.DevActionU64Cond.NeightState != DevActionGlobal.Last_NeightState) { + DevActionGlobal.Last_NeightState = DevActionGlobal.DevActionU64Cond.NeightState; + } + +} + +/******************************************************************************* +* @Function Name : DevAction_IndicateCtrl +* @Description : 豸ִ +* @Input : +* DevActionInfo : 豸Ϣ +* @Return +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_IndicateCtrl(DEV_ACTION_INFO *DevActionInfo) +{ + uint8_t i = 0x00; + uint8_t CtrlWay = 0x00; + Device_Public_Information_G BUS_Public; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"״̬ı׼ִзƿƣ:%s״̬%d,豸:%d", + DevActionInfo->DevActionCore.DevActionName, + DevActionInfo->DevActionState.SceneState, + DevActionInfo->DevCtrlNum); + + for(i = 0; i < DevActionInfo->DevCtrlNum; i++) + { + if(DevActionInfo->DevActionOutput[i].DevActionOutAddr != 0x00) + { + switch(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevType) + { + case DEV_RS485_SWT: + case Dev_Host_LVoutput: + CtrlWay = DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState&0x00ff; + switch(CtrlWay) + { + case DEV_CTRLWAY_RELATESCENE: + switch(DevActionInfo->DevActionState.SceneState) + { + case DEV_STATE_OPEN: + case DEV_STATE_CLOSE: + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevActionInfo->DevActionOutput[i].DevActionOutAddr); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ƿ˳ʱִ,豸: %d ַ:%d·:%d״̬:%d", + BUS_Public.type, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionState.SceneState); + + DevDly_InfoSet( + DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x00); //˸ ʱ + + if(NULL != BUS_Public.DevFunInfo.Dev_Output_Ctrl) + { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutAddr, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionState.SceneState); //ݳ״̬ȥƷ + } + break; + } + break; + case CFG_Dev_CtrlWay_Is_RelateBlink: + if(0x00 != DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue.DelayCont) //ִ + { + switch(DevActionInfo->DevActionState.SceneState) + { + case DEV_STATE_OPEN: //˸ Ӧȿָʾ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevActionInfo->DevActionOutput[i].DevActionOutAddr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"˸,״̬:%04X",CFG_Dev_CtrlWay_Is_TOGGLE |(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState&0xff00)); + DevDly_InfoSet( + DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x01, + CFG_Dev_CtrlWay_Is_TOGGLE |(DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState&0xff00), + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x01); + + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutAddr, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DEV_CTRLWAY_OPEN | ( DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0xff00 ) ); + } + break; + case DEV_STATE_CLOSE: //ر˸ Ӧָʾ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ر˸"); + DevDly_InfoSet( + DevActionInfo->DevActionOutput[i].DevDlyAddr, + 0x01, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevDlyValue, + 0x02); + break; + } + } + break; + } + break; + case Dev_NodeCurtain: + if( (DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00ff) == DEV_CTRLWAY_RELATESCENE ) + { + if( DevActionInfo->DevActionState.SceneState == DEV_STATE_OPEN ) + { + switch(DevActionInfo->DevActionInput.inType) + { + case DEV_CTRLWAY_OPEN: // + case DEV_CTRLWAY_CLOSE: // + case DEV_CTRLWAY_STOP: //ͣ + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevActionInfo->DevActionOutput[i].DevActionOutAddr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ƿ˳ʱִ,豸: %d ַ:%d·:%d״̬:%d", + BUS_Public.type, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevAddr, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionState.SceneState); + + if(BUS_Public.DevFunInfo.Dev_Output_Ctrl != NULL) + { + BUS_Public.DevFunInfo.Dev_Output_Ctrl( + 0x00, + 0x00, + DevActionInfo->DevActionOutput[i].DevActionOutAddr, + DevActionInfo->DevActionOutput[i].DevActionOutCfg.DevOutputLoop, + DevActionInfo->DevActionInput.inType); + } + break; + } + } + } + break; + } + } + } +} + +/******************************************************************************* +* @Function Name : BLV_DevAction_Cycle +* @Description : еĶͬ봥ڵĶһɨ +* @Input : +* Dev_processing_addr : 豸ַ +* BUS_Public +* @Return +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_DevAction_Cycle(uint32_t Dev_processing_addr,Device_Public_Information_G *BUS_Public) +{ + DEV_ACTION_INFO DevActionInfo; //豸ȫϢ - ռ512Byte + uint32_t DevActionAddr = 0x00,temp_offset = 0x00; //ڱж + uint16_t j = 0x00; //ڱ + uint8_t BreakFlag = 0x00; //ѭ־ 豸ִ + + for(j = BUS_Public->ActionCoord; j < DevActionGlobal.DevActionNum; j++) //ΪɶҪѭ - ʵ + { + DevActionAddr = SRAM_DevAction_List_Start_Addr + j*SRAM_DevAction_List_Size; + temp_offset = DevActionAddr + sizeof(Dev_Action_Core) + sizeof(Dev_Action_Input) + sizeof(Dev_Action_Cond) + sizeof(Dev_Action_State) - 4; + + if(SRAM_Read_DW(temp_offset) == Dev_processing_addr) //ӵͬ봥ڵ DevActionInfo.DevActionState.DevAddrIn + { + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), DevActionAddr); //豸Ϣ 豸ȥִп + + if( Data_CheckSum((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO)) != 0x00 ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Уδͨ:%d"); + continue; + } + + RcuLockState_Scan(); + + DevAction_State_Get(&DevActionInfo); //ǰ״̬ 豸ȥж + + if( DevActionInfo.DevActionCond.DevActionU64Cond.DevActionOutFlag == 0x00 ) //豸 - жñ־λ + { + if( DevActionInfo.DevActionState.SceneReuseFlag == 0x00 ) //״̬ - ñ־λ ʵ㣺ñ־λʲô + { + if( (BUS_Public->DevFunInfo.Dev_Input_Type_Get != NULL) + && (BUS_Public->DevFunInfo.Dev_Input_Type_Get(DevActionInfo.DevActionState.DevAddrIn, DevActionInfo.DevActionInput.inAddr, DevActionInfo.DevActionInput.inType) == CtrlValid) ) + { + if(BLV_DevAction_Cond_Judge(&DevActionInfo) == CondIsPass) + { + BreakFlag = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d 豸ַ%d ַ:%d ַ:%d ַ:%08Xͨ", \ + DevActionInfo.DevActionInput.DevType, \ + DevActionInfo.DevActionInput.DevAddr, \ + DevActionInfo.DevActionInput.inAddr, \ + DevActionInfo.DevActionCore.ActionNo, \ + DevActionAddr); + DevAction_Output(&DevActionInfo); //ִ + }else if(DevActionInfo.DevActionCond.DevActionU64Cond.EleCtrlFlag == 0x01) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d 豸ַ%d ַ:%d ַ:%d ַ:%08Xδͨпȡ翪־", + DevActionInfo.DevActionInput.DevType, + DevActionInfo.DevActionInput.DevAddr, + DevActionInfo.DevActionInput.inAddr, + DevActionInfo.DevActionCore.ActionNo, + DevActionAddr); + + if(0x00 == Get_Authorize_Lock_Status()) //Ȩж + { + BreakFlag = 0x01; + Ele_Ctrl_OpenClose(0x01); //ȡ + } + } + } + }else if(DevActionInfo.DevActionState.SceneReuseFlag == 0x01) //ڸñ־ + { + if( (DevActionInfo.DevActionCond.SceneExcute == ACTION_SCENE_MULTI) && (DevActionInfo.DevActionInput.DevType == DEV_RS485_SWT) ) + { + if( (CondIsPass == BLV_DevAction_Cond_Judge(&DevActionInfo)) && (BUS_Public->DevFunInfo.Dev_Input_Type_Get != NULL) ) + { + uint8_t ret = BUS_Public->DevFunInfo.Dev_Input_Type_Get(DevActionInfo.DevActionState.DevAddrIn, DevActionInfo.DevActionInput.inAddr, DevActionInfo.DevActionInput.inType); + + if( (ret & 0x01) == CtrlValid ) + { + if( DevActionInfo.DevActionState.MultiNumber == (ret >> 0x01) ) + { + BreakFlag = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%s,豸͸:%d 豸ַ%d ַ:%d :%d ַ:%08Xͨ", + DevActionInfo.DevActionCore.DevActionName, + DevActionInfo.DevActionInput.DevType, + DevActionInfo.DevActionInput.DevAddr, + DevActionInfo.DevActionInput.inAddr, + DevActionInfo.DevActionCore.ActionNo, + DevActionAddr); + + DevAction_Output(&DevActionInfo); //ִ + }else { + //ǰ±Ϳش±겻ȣѰҶַ + uint32_t TempAddr = 0x00,deal_addr = 0; + deal_addr = TempAddr+sizeof(Dev_Action_Core)+sizeof(Dev_Action_Input)+sizeof(Dev_Action_Cond)+sizeof(Dev_Action_State) - 4 ; + for(uint8_t i = 0; i < DevActionGlobal.DevActionNum; i++ ) + { + TempAddr = SRAM_DevAction_List_Start_Addr + i * SRAM_DevAction_List_Size; + if( SRAM_Read_DW(deal_addr) == Dev_processing_addr ) + { + deal_addr = deal_addr - 3; + if( SRAM_Read_Byte(deal_addr) == (ret >> 0x01) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҵ:%d ַ:%08X",SRAM_Read_Byte(deal_addr),TempAddr); + break; + } + } + } + + deal_addr = TempAddr+sizeof(Dev_Action_Core)+sizeof(Dev_Action_Input)+sizeof(Dev_Action_Cond)+sizeof(Dev_Action_State) - 4 ; + if( (TempAddr != 0x00) && (SRAM_Read_DW(deal_addr) == Dev_processing_addr) ) + { + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), TempAddr); + if( Data_CheckSum( (uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO) ) != 0x00 ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Уδͨ:%d"); + continue ; + } + + BreakFlag = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%s,豸͸:%d 豸ַ%d ַ:%d :%d ַ:%08Xͨ", + DevActionInfo.DevActionCore.DevActionName, + DevActionInfo.DevActionInput.DevType, + DevActionInfo.DevActionInput.DevAddr, + DevActionInfo.DevActionInput.inAddr, + DevActionInfo.DevActionCore.ActionNo, + DevActionAddr); + DevAction_Output(&DevActionInfo); //ִ + } + } + } + } + }else { + if( (BLV_DevAction_Cond_Judge(&DevActionInfo) == CondIsPass) + && (BUS_Public->DevFunInfo.Dev_Input_Type_Get != NULL) + && ( BUS_Public->DevFunInfo.Dev_Input_Type_Get( + DevActionInfo.DevActionState.DevAddrIn, + DevActionInfo.DevActionInput.inAddr, + DevActionInfo.DevActionInput.inType ) == CtrlValid ) ) + { + BreakFlag = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%s,豸͸:%d 豸ַ%d ַ:%d :%d ַ:%08Xͨ", + DevActionInfo.DevActionCore.DevActionName, + DevActionInfo.DevActionInput.DevType, + DevActionInfo.DevActionInput.DevAddr, + DevActionInfo.DevActionInput.inAddr, + DevActionInfo.DevActionCore.ActionNo, + DevActionAddr); + + DevAction_Output(&DevActionInfo); //ִ + } + } + } + } + + if(BreakFlag == 0x01) //ز¼ˢ³״̬ + { + DevAction_State_Get(&DevActionInfo); //ǰ״̬ 豸ȥж + } + + //״̬ı,Ʒ + if( DevActionInfo.DevActionState.SceneState != DevActionInfo.DevActionState.SceneStateLast ) + { + DevActionInfo.DevActionState.SceneStateLast = DevActionInfo.DevActionState.SceneState; + DevAction_IndicateCtrl(&DevActionInfo); + + DevActionInfo.CheckVal = 0x00; + DevActionInfo.CheckVal = Data_CheckSum((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), DevActionAddr); + } + + if(BreakFlag == 0x01) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ±:%d", j); + break; + } + } + } +} + +/******************************************************************************* +* @Function Name : BLV_DevAction_Task +* @Description : BLV豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_DevAction_Task(void) +{ + static uint32_t dev_action_processing_tick = 0; + uint32_t Dev_processing_addr; + Device_Public_Information_G BUS_Public; //ȫ + uint8_t BreakFlag = 0x00; + + if( SysTick_1ms - dev_action_processing_tick >= 50) + { + if(DevActionGlobal.Devi >= DevActionGlobal.DevNum) + { + DevActionGlobal.Devi = 0x00; + } + + for( ; DevActionGlobal.Devi < DevActionGlobal.DevNum ;) + { + Dev_processing_addr = SRAM_Device_List_Start_Addr + DevActionGlobal.Devi*SRAM_Device_List_Size; + + switch(SRAM_Read_Byte(Dev_processing_addr+Dev_Type)) + { + case Dev_Host_LVinput: //豸 - + case Dev_NodeCurtain: //ɽӵ豸 - + case DEV_RS485_CARD: //RS485豸 - 忨ȡ + case DEV_RS485_TEMP: //RS485豸 - ¿ + case Dev_Host_Service: //豸 - Ϣ + case DEV_RS485_SWT: //RS485豸 - + case DEV_RS485_PWM: //RS485豸 - + case DEV_RS485_FreshAir: //RS485豸 - · + case DEV_RS485_HEATER: //RS485豸 - ů + case Dev_Rs458_RotaryCtrl: //RS485豸 - ť + case DEV_Virtual_Card: //豸 - ޿ȡ + case DEV_Carbon_Saved: //豸 - ̼ + case Dev_Scene_Restore: //豸 - ԭ + BreakFlag = 0x01; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), Dev_processing_addr); //й + BLV_DevAction_Cycle(Dev_processing_addr, &BUS_Public); //ҵڵ㣬ѵַȫԴȥ + break; + } + + DevActionGlobal.Devi++; + if(BreakFlag == 0x01) break; + } + + dev_action_processing_tick = SysTick_1ms; + } +} + +/******************************************************************************* +* @Function Name : BLV_DevAction_Cycle +* @Description : еĶͬ봥ڵĶһɨ +* @Input : +* Dev_processing_addr : 豸ַ +* BUS_Public +* @Return +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_DevAddr_Ctrl( + uint32_t DevActionAddr, + uint8_t Mode, + uint8_t SceneMode, + uint16_t CtrlState) +{ + DEV_ACTION_INFO DevActionInfo; + + if( (DevActionAddr < SRAM_DevAction_List_Start_Addr) || (DevActionAddr >= SRAM_DevAction_List_End_Addr) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ַЧ:%08X",DevActionAddr); + return ; + } + + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), DevActionAddr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ƣַЧ:%08X:%d",DevActionAddr, DevActionInfo.DevActionCore.ActionNo); + + if( DevActionInfo.DevActionCore.ActionNo == ACTION_SCENE_SLEEP ) + { + if( DevActionGlobal.DevActionU64Cond.NeightFlag == 0x01 ) + { + if( DevActionGlobal.DevActionU64Cond.NeightState != NightModeStart ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ƣг˯ߣҹ"); + DevActionGlobal.DevActionU64Cond.NeightState = NightModeStart; + } + } + DevAction_Mode_Ctrl(&DevActionInfo, LIGHT_MODE_CTRL, SLEEP_MODE_CTRL, DEV_CTRLWAY_CLOSE); + }else { + DevAction_Mode_Ctrl(&DevActionInfo, Mode, SceneMode, CtrlState); + } +} + +/******************************************************************************* +* @Function Name : BLV_DevDly_Process +* @Description : ʱ豸 +* ʱ豸ִ: +* 豸 +* ִ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_DevDly_Process(uint32_t dly_processing_addr) +{ + Struct_Dev_Dly DevDlyInfo; + uint8_t KeepFlag = 0x00; + Dev_Output_Ctrl_ptr Dev_Output_Ctrl; + + SRAM_DMA_Read_Buff((uint8_t *)&DevDlyInfo, sizeof(Struct_Dev_Dly), dly_processing_addr); + + if( (DevDlyInfo.DlyExcuteFlag == 0x01) && (SysTick_1ms >= DevDlyInfo.DlyExcuteTime) ) + { + DevDlyInfo.DlyExcuteFlag = 0x00; //־0 + KeepFlag = 0x01; + + if(DevDlyInfo.DevDlyCore.DevDlyAddr != 0x00) + { + switch(DevDlyInfo.DevDlyCore.DevType) + { + case Dev_Host_HVout: + case Dev_Host_LVoutput: + case Dev_Host_Service: + case Dev_NodeCurtain: + case DEV_RS485_TEMP: + case DEV_RS485_SWT: + case DEV_RS485_STRIP: + case DEV_RS485_PWM: + case DEV_RS485_MUSIC: + case DEV_RS485_CURTAIN: + case DEV_RS485_FreshAir: + case DEV_RS485_HEATER: + case Dev_Rs485_PB20: + case Dev_Rs485_PB20_LD: + case Dev_Rs485_PB20_LS: + case Dev_Rs485_PB20_Relay: + case DEV_Virtual_NoCard: + case DEV_Virtual_Card: + case DEV_Virtual_ColorTemp: + case Dev_485_BLE_Music: + case DEV_Carbon_Saved: + case Dev_Energy_Monitor: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱ豸ִ:%d %d· : %04X",DevDlyInfo.DevDlyCore.DevType, DevDlyInfo.DevDlyCore.DevOutputLoop ,DevDlyInfo.DevOutputType); + Dev_Output_Ctrl = (Dev_Output_Ctrl_ptr)SRAM_Read_DW(DevDlyInfo.DevDlyCore.DevDlyAddr + Dev_Output_Ctrl_0); + if(Dev_Output_Ctrl != NULL) + { + Dev_Output_Ctrl(0x00, 0x00, DevDlyInfo.DevDlyCore.DevDlyAddr, DevDlyInfo.DevDlyCore.DevOutputLoop, DevDlyInfo.DevOutputType); + } + break; + case Dev_Host_Invalid: + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʱִеʱ䣬ַ:%08X ״̬: %04X",DevDlyInfo.DevDlyCore.DevDlyAddr, DevDlyInfo.DevOutputType); + DevAction_DevAddr_Ctrl(DevDlyInfo.DevDlyCore.DevDlyAddr, 0x01, NOR_MODE_CTRL, DevDlyInfo.DevOutputType); + break; + } + } + if( KeepFlag == 0x01 ) + { + SRAM_DMA_Write_Buff((uint8_t *)&DevDlyInfo,sizeof(Struct_Dev_Dly),dly_processing_addr); + } + + if( DevDlyInfo.DlyBlinkFlag == 0x01 ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰʱʱ˸ִ:%d %d· : %04X",DevDlyInfo.DevDlyCore.DevType, DevDlyInfo.DevDlyCore.DevOutputLoop ,DevDlyInfo.DevOutputType); //̵״ֵ̬ + DevDly_InfoSet(dly_processing_addr, 0x01, DevDlyInfo.DevOutputType, DevDlyInfo.DlyBlinkTime, 0x01); + }else if( DevDlyInfo.DlyBlinkFlag == 0x02 ) + { + DevDly_InfoSet(dly_processing_addr, 0x01, DEV_CTRLWAY_CLOSE, DevDlyInfo.DlyBlinkTime, 0x00); + } + } +} + +/******************************************************************************* +* @Function Name : BLV_DevDly_Task +* @Description : BLV豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_DevDly_Task(void) +{ + static uint32_t dev_devdly_processing_tick = 0; + uint32_t dly_processing_addr = 0; + + if( SysTick_1ms - dev_devdly_processing_tick >= 10 ) + { + dev_devdly_processing_tick = SysTick_1ms; + + if( DevActionGlobal.DevDlyi > DevActionGlobal.DevDlyNum ) DevActionGlobal.DevDlyi = 0x00; + + dly_processing_addr = SRAM_DevDly_List_Start_Addr + DevActionGlobal.DevDlyi*DevDlyStructLen; + BLV_DevDly_Process(dly_processing_addr); + DevActionGlobal.DevDlyi++; + } +} + diff --git a/MCU_Driver/blv_netcomm_function.c b/MCU_Driver/blv_netcomm_function.c new file mode 100644 index 0000000..5530695 --- /dev/null +++ b/MCU_Driver/blv_netcomm_function.c @@ -0,0 +1,1517 @@ +/* + * BLV_NETCOMM_Function.c + * + * Created on: Nov 3, 2025 + * Author: cc + */ +#include "includes.h" +#include + +uint8_t Global_Large_Buff[1100] = {0}; //׽ͨѶдⲿSRAMӳĴ +uint32_t ProjectCode = 1001; //ģĿ +uint8_t Versions[4] = {0,0,0,0}; //ģð汾 + +/******************************************************************************* +* Function Name : UDP_Add_Header +* Description : ӱ - ͨѶЭͷ +* Input : +* data - Ҫӵ +* cmd - ͨѶ +* length - ͨѶ +* frame_no - ͨѶ֡ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_Header(uint8_t *data,uint8_t cmd,uint16_t length, uint16_t frame_no) +{ + uint8_t len = 0x00; + + data[len++] = 0xAA; + data[len++] = 0x55; + data[len++] = length%256; + data[len++] = length/256; + data[len++] = 'T'; + data[len++] = '3'; + data[len++] = 'S'; + data[len++] = 'A'; + data[len++] = cmd; + data[len++] = frame_no%256; + data[len++] = frame_no/256; + data[len++] = ProjectCode%256; + data[len++] = ProjectCode/256; + + data[len++] = g_netinfo.device_ip[2]; //ip + data[len++] = g_netinfo.device_ip[3]; + + return len; +} + +/******************************************************************************* +* Function Name : UDP_ADD_SoftwareVer +* Description : 汾 +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_ADD_SoftwareVer(uint8_t *data) +{ + uint8_t len = strlen(SoftwareVer); + if(len > RCU_SoftwareVer) len = RCU_SoftwareVer; //ֹ汾 + + memcpy(data,SoftwareVer,len); //RCU_SoftwareVer + return len; +} + +/******************************************************************************* +* Function Name : UDP_ADD_ConfigVer +* Description : ߼ð汾 +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_ADD_ConfigVer(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = Versions[0]; + data[1] = Versions[1]; + data[2] = Versions[2]; + + return 0x03; +} + +/******************************************************************************* +* Function Name : UDP_Add_ServerIp +* Description : ӷIPַ +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_ServerIp(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = server_info.dis_ip[0]; + data[1] = server_info.dis_ip[1]; + data[2] = server_info.dis_ip[2]; + data[3] = server_info.dis_ip[3]; + + return 0x04; +} + +/******************************************************************************* +* Function Name : UDP_Add_ServerPort +* Description : ӷͨѶ˿ +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_ServerPort(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = server_info.dis_port & 0xFF; + data[1] = (server_info.dis_port >> 8) & 0xFF; + + return 0x02; +} + +/******************************************************************************* +* Function Name : UDP_Add_Subnet +* Description : +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_Subnet(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = g_netinfo.subnet[0]; + data[1] = g_netinfo.subnet[1]; + data[2] = g_netinfo.subnet[2]; + data[3] = g_netinfo.subnet[3]; + + return 0x04; +} + +/******************************************************************************* +* Function Name : UDP_Add_Gateway +* Description : +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_Gateway(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = g_netinfo.gateway[0]; + data[1] = g_netinfo.gateway[1]; + data[2] = g_netinfo.gateway[2]; + data[3] = g_netinfo.gateway[3]; + + return 0x04; +} + +/******************************************************************************* +* Function Name : UDP_Add_Mac +* Description : MACַ +* Input : +* data - Ҫӵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Add_Mac(uint8_t *data) +{ + //ϵʱиֵVersions ð汾 + data[0] = g_netinfo.mac_addr[0]; + data[1] = g_netinfo.mac_addr[1]; + data[2] = g_netinfo.mac_addr[2]; + data[3] = g_netinfo.mac_addr[3]; + data[4] = g_netinfo.mac_addr[4]; + data[5] = g_netinfo.mac_addr[5]; + + return 0x06; +} + +/******************************************************************************* +* Function Name : UDP_Search_Ack +* Description : עắ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Search_Ack(void) +{ + uint32_t sendlen = BLV_UDP_HEAD_LEN; + uint8_t rev = 0; + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + //Ҫص֡ + sendlen += UDP_Add_ServerIp(&Global_Large_Buff[BLV_UDP_HEAD_LEN]); //ӷIPַ + sendlen += UDP_Add_Subnet(&Global_Large_Buff[sendlen]); // + sendlen += UDP_Add_Gateway(&Global_Large_Buff[sendlen]); // + sendlen += UDP_Add_ServerPort(&Global_Large_Buff[sendlen]); //RCU˿ + sendlen += UDP_Add_Mac(&Global_Large_Buff[sendlen]); //Mac + sendlen += UDP_ADD_SoftwareVer(&Global_Large_Buff[sendlen]); //ӹ̼汾 + sendlen += UDP_ADD_ConfigVer(&Global_Large_Buff[sendlen]); //ð汾 + + Global_Large_Buff[sendlen++] = g_netinfo.dns_server_ip[0]; + Global_Large_Buff[sendlen++] = g_netinfo.dns_server_ip[1]; + Global_Large_Buff[sendlen++] = g_netinfo.dns_server_ip[2]; + Global_Large_Buff[sendlen++] = g_netinfo.dns_server_ip[3]; + SRAM_DMA_Read_Buff(&Global_Large_Buff[sendlen],16,SRAM_Register_Start_ADDRESS + Register_RoomTypeNote_OFFSET); + sendlen += 16; + SRAM_DMA_Read_Buff(&Global_Large_Buff[sendlen],16,SRAM_Register_Start_ADDRESS + Register_RoomNumNote_OFFSET); + sendlen += 16; + SRAM_DMA_Read_Buff(&Global_Large_Buff[sendlen],4,SRAM_Register_Start_ADDRESS + Register_HouseType_OFFSET); + sendlen += 4; + SRAM_DMA_Read_Buff(&Global_Large_Buff[sendlen],4,SRAM_Register_Start_ADDRESS + Register_RoomNumber_OFFSET); + sendlen += 4; + + sendlen += 2; //CRC16 ݳ2Byte + UDP_Add_Header(Global_Large_Buff,Search_Cmd,sendlen,0xffff); //ͷ + NetCRC16(&Global_Large_Buff[0],sendlen); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"SocketId:%d , IP:%d.%d.%d.%d , port:%d",g_netinfo.SocketId[SocketIdnex_BLVSeriver],server_info.dis_ip[0],server_info.dis_ip[1],server_info.dis_ip[2],server_info.dis_ip[3],server_info.dis_port); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s rev:%d",__func__,rev); + + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + + return rev; +} + +/******************************************************************************* +* Function Name : UDP_Heart_Send +* Description : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Heart_Send(void) +{ + uint32_t sendlen = 0x00; + uint8_t rev = 0; + + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + }else{ + server_info.frame_no = 0x8000; + } + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + sendlen = SocketIdnex_BLVSeriver; + //2025-9-25 ޸ + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[0]; + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[1]; + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[2]; + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[3]; + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[4]; + Global_Large_Buff[sendlen++] = g_netinfo.mac_addr[5]; + + sendlen += 0x06; + + sendlen += 0x02; //CRCУ鳤 + UDP_Add_Header(Global_Large_Buff,Heart_Cmd,sendlen,server_info.frame_no); //ͷ + + NetCRC16(&Global_Large_Buff[0],sendlen); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s..",__func__); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + + return rev; +} + +/******************************************************************************* +* Function Name : Udp_Internal_GetTime_Data +* Description : ȡʱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_GetTime_CMD(void) +{ + uint32_t sendlen = BLV_UDP_PACK_LEN; + uint8_t rev = 0; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s",__func__); + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if(server_info.udp_retry_cnt == 0x00) + { + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + }else{ + server_info.frame_no = 0x8000; + } + } + + UDP_Add_Header(Global_Large_Buff,In_QueryTime_Cmd,sendlen,server_info.frame_no); + NetCRC16(&Global_Large_Buff[0],sendlen); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + return rev; +} + +/******************************************************************************* +* Function Name : Udp_Internal_GetRoomRent_CMD +* Description : ȡ̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_GetRoomRent_CMD(void) +{ + uint32_t sendlen = BLV_UDP_PACK_LEN; + uint8_t rev = 0; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s",__func__); + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if(server_info.udp_retry_cnt == 0x00) + { + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + }else{ + server_info.frame_no = 0x8000; + } + } + + UDP_Add_Header(Global_Large_Buff,In_Get_RoomRent_Cmd,sendlen,server_info.frame_no); + NetCRC16(&Global_Large_Buff[0],sendlen); + + //Dbg_Print_Buff(DBG_BIT_NET_STATUS_bit," ȡ̬",back_data,sendlen); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + return rev; +} + +/******************************************************************************* +* Function Name : Udp_Internal_Reboot_Reason_Report_CMD +* Description : RCUԭ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_Reboot_Reason_Report_CMD(void) +{ + uint8_t temp_data[24] = {0}; + uint32_t sendlen = 0x00; + uint8_t rev = 0; + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if( server_info.udp_retry_cnt == 0x00 ) + { + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + }else { + server_info.frame_no = 0x8000; + } + }else { + //ݰطУ֡Ųı + } + + sendlen = BLV_UDP_HEAD_LEN; + + /*Launcher汾 ֻLauncher_C1F_V04 ϰ汾ſԶȡLauncher汾°汾Ƕȡ 2022-08-04*/ + //MCU_Flash_Read((uint8_t *)&temp_data,20,Launcher_SoftwareVer_Addr); + if(strncmp((char *)temp_data,"Launcher_",strlen("Launcher_")) == 0x00) + { + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN],temp_data,20); + }else { + /*ȡLauncher_ ǰ׺ַĬΪLauncher_C1F_V02*/ + memset(temp_data,0,sizeof(temp_data)); + snprintf((char *)temp_data,sizeof(temp_data),"Launcher_C1F_V02 "); + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN],temp_data,20); + } + sendlen += 20; + + Global_Large_Buff[sendlen++] = SRAM_Read_DW(SRAM_LOG_RCU_Reboot_Reason) & 0xFF; //ԭ + + sendlen += 0x02; //CRCУ鳤 + UDP_Add_Header(Global_Large_Buff,In_Reboot_Reason_Cmd,sendlen,server_info.frame_no); + + NetCRC16(&Global_Large_Buff[0],sendlen); + + //Dbg_Print_Buff(DBG_BIT_NET_STATUS_bit,"RCUԭ: ",Global_Large_Buff,sendlen); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + + return rev; +} + +/******************************************************************************* +* Function Name : Udp_Internal_Power_Change_Report_CMD +* Description : ȡ仯ϱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_Power_Change_Report_CMD(void) +{ + uint32_t sendlen = 0x00; + uint8_t temp_flag = 0,rev = 0; + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if( server_info.udp_retry_cnt == 0x00 ) + { + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + }else { + server_info.frame_no = 0x8000; + } + } + + temp_flag = SRAM_Read_Byte(SRAM_UDP_ELEReport_Action); + + sendlen = BLV_UDP_HEAD_LEN; + if( (temp_flag & 0x01) != 0x00 ) + { + Global_Large_Buff[sendlen++] = SRAM_Read_Byte(SRAM_UDP_ELEReport_EleState_Last); //ȡ綯 + }else { + Global_Large_Buff[sendlen++] = 0x00; + } + + if( (temp_flag & 0x02) != 0x00 ) + { + Global_Large_Buff[sendlen++] = SRAM_Read_Byte(SRAM_UDP_ELEReport_CardState_Last); //忨 + }else { + Global_Large_Buff[sendlen++] = 0x00; + } + + if( (temp_flag & 0x04) != 0x00 ) + { + Global_Large_Buff[sendlen++] = SRAM_Read_Byte(SRAM_UDP_ELEReport_CardType_Last); //ݱ仯 + }else { + Global_Large_Buff[sendlen++] = 0x00; + } + + if( (temp_flag & 0x08) != 0x00 ) + { + Global_Large_Buff[sendlen++] = SRAM_Read_Byte(SRAM_UDP_ELEReport_VirtualCard_Last); //޿¼ + }else { + Global_Large_Buff[sendlen++] = 0x00; + } + + sendlen += 0x02; //CRCУ鳤 + UDP_Add_Header(Global_Large_Buff,In_Power_Change_Cmd,sendlen,server_info.frame_no); + + NetCRC16(&Global_Large_Buff[0],sendlen); + + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &sendlen, server_info.dis_ip, server_info.dis_port); + + LOG_NET_COMM_Send_Record(0x01,server_info.dis_ip,server_info.dis_port,&Global_Large_Buff[0],sendlen); + + return rev; +} + +/******************************************************************************* +* Function Name : Find_TempDevice_List_Information +* Description : ҵ豸бе¿ +* Input : +* buff - ݵַ +* dev_num_max - ¿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Find_TempDevice_List_Information(uint8_t *buff,uint8_t dev_num_max) +{ + uint32_t read_addr = SRAM_Device_List_Start_Addr; + uint32_t end_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr); + Device_Public_Information_G BUS_Public; + RS485_TEMP_INFO Rs485Temp; + uint8_t dev_num = 0; + uint8_t data_offset = 0; + uint16_t temp_val = 0; + + memset(&BUS_Public,0,sizeof(Device_Public_Information_G)); + memset(&Rs485Temp,0,sizeof(RS485_TEMP_INFO)); + + if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr; + + for(uint32_t i=SRAM_Device_List_Start_Addr;i> 8) & 0xFF; + + dev_num++; + if(dev_num >= dev_num_max) return dev_num; //ޣֱ˳ + } + } + read_addr += SRAM_Device_List_Size; + i+= SRAM_Device_List_Size; + if(read_addr >= end_addr) + { + return dev_num; + } + } + + return dev_num; +} + +/******************************************************************************* +* Function Name : Udp_Scan_Roomstate +* Description : ӷ豸״̬仯 - ϱд +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Udp_Addtion_Roomstate(uint8_t type,uint8_t addr,uint16_t loop,uint16_t start) +{ + uint8_t len = 0x00; + uint8_t back_data[8]; + uint32_t write_addr = SRAM_Read_DW(SRAM_UDP_SendData_Writeaddr),read_addr = SRAM_Read_DW(SRAM_UDP_SendData_Readaddr); + + memset(back_data,0,8); + + /*жϵַǷڷΧ*/ + if( (write_addr < SRAM_UDP_SendData_Startaddr) || (write_addr > SRAM_UDP_SendData_Endaddr) \ + || (read_addr < SRAM_UDP_SendData_Startaddr) || (read_addr > SRAM_UDP_SendData_Endaddr) ) + { + write_addr = SRAM_UDP_SendData_Startaddr; + read_addr = SRAM_UDP_SendData_Startaddr; + SRAM_Write_DW(write_addr,SRAM_UDP_SendData_Writeaddr); + SRAM_Write_DW(read_addr,SRAM_UDP_SendData_Readaddr); + SRAM_Write_DW(read_addr,SRAM_UDP_SendData_Tempaddr); + } + + back_data[0] = type; + back_data[1] = addr; + back_data[2] = (loop & 0xFF); + back_data[3] = ((loop >> 8) & 0xFF); + back_data[4] = (start & 0xFF); + back_data[5] = ((start >> 8) & 0xFF); + + if( (write_addr + 6) > SRAM_UDP_SendData_Endaddr) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep_1 %08X!!!",__func__,write_addr); + len = SRAM_UDP_SendData_Endaddr - write_addr; + SRAM_DMA_Write_Buff(back_data,len,write_addr); + write_addr = SRAM_UDP_SendData_Startaddr; + SRAM_DMA_Write_Buff(&back_data[len],(6-len),write_addr); + write_addr += (6-len); + } + else{ + SRAM_DMA_Write_Buff(back_data,0x06,write_addr); + write_addr += 0x06; //ַƫ + } + + if(write_addr > SRAM_UDP_SendData_Endaddr) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep %08X!!!",__func__,write_addr); + write_addr = SRAM_UDP_SendData_Startaddr; + } + SRAM_Write_DW(write_addr,SRAM_UDP_SendData_Writeaddr); +} + + +/******************************************************************************* +* Function Name : Udp_Internal_Read_MCU_System_SendAck +* Description : - ظACK +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_Read_MCU_System_SendAck(uint8_t *ip,uint16_t port,uint16_t frame_id) +{ + UINT32 back_len = BLV_UDP_HEAD_LEN + 449 + 2; //ݳ + + uint8_t temp_data[34] = {0}; + uint8_t temp_rev = 0,rev = 0; + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + /*ݴ*/ + UDP_Add_Header(Global_Large_Buff,In_Read_MCUSystem_Cmd,back_len,frame_id); //ͷ + Global_Large_Buff[BLV_UDP_HEAD_LEN] = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_NetInfo_EN_OFFSET); //IP 2022-12-02 + + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 1],MCU_TYPE,sizeof(MCU_TYPE)); //ͱ + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 17],g_netinfo.device_ip,4); //IPַ + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 21],server_info.dis_ip,4); //IPַ + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 25],g_netinfo.subnet,4); // + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 29],g_netinfo.gateway,4); // + UDP_Add_ServerPort(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 33]); //MCUĬ϶˿Ϊ3341 + Global_Large_Buff[BLV_UDP_HEAD_LEN + 35] = 0; //ֽû + Global_Large_Buff[BLV_UDP_HEAD_LEN + 36] = 0; + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 37],g_netinfo.dns_server_ip,4); // + UDP_ADD_SoftwareVer(&Global_Large_Buff[BLV_UDP_HEAD_LEN+41]); //ͱ - 汾 + + /*RTCʱ*/ + Global_Large_Buff[BLV_UDP_HEAD_LEN+61] = HEX_Conversion_To_DEC(RTC_Raw_Data.year); + Global_Large_Buff[BLV_UDP_HEAD_LEN+62] = HEX_Conversion_To_DEC(RTC_Raw_Data.month); + Global_Large_Buff[BLV_UDP_HEAD_LEN+63] = HEX_Conversion_To_DEC(RTC_Raw_Data.day); + Global_Large_Buff[BLV_UDP_HEAD_LEN+64] = HEX_Conversion_To_DEC(RTC_Raw_Data.hour); + Global_Large_Buff[BLV_UDP_HEAD_LEN+65] = HEX_Conversion_To_DEC(RTC_Raw_Data.minute); + Global_Large_Buff[BLV_UDP_HEAD_LEN+66] = HEX_Conversion_To_DEC(RTC_Raw_Data.second); + + /*Launcher汾 ֻLauncher_C1F_V04 ϰ汾ſԶȡLauncher汾°汾Ƕȡ 2022-08-04*/ + //MCU_Flash_Read((uint8_t *)&temp_data,20,Launcher_SoftwareVer_Addr); + if(strncmp((char *)temp_data,"Launcher_",strlen("Launcher_")) == 0x00) + { + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+67],temp_data,20); + }else { + /*ȡLauncher_ ǰ׺ַĬΪLauncher_C1F_V02*/ + memset(temp_data,0,sizeof(temp_data)); + snprintf((char *)temp_data,sizeof(temp_data),"Launcher_C1F_V02 "); + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+67],temp_data,20); + } + + UDP_Add_Mac(&Global_Large_Buff[BLV_UDP_HEAD_LEN+87]); //MACַ + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+93],4,SRAM_Register_Start_ADDRESS + Register_ProjectCode_OFFSET); //Ŀ + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+97],4,SRAM_Register_Start_ADDRESS + Register_RoomNumber_OFFSET); + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+101],4,SRAM_Register_Start_ADDRESS + Register_HouseType_OFFSET); + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+105],4,SRAM_Register_Start_ADDRESS + Register_ConfigVersion_OFFSET); //汾 + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+109],4,SRAM_Register_Start_ADDRESS + Register_RoomRent_OFFSET); + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+113],4,SRAM_Register_Start_ADDRESS + Register_SeasonStatus_OFFSET); + + Global_Large_Buff[BLV_UDP_HEAD_LEN+117] = Get_Authorize_Lock_Status(); //ȡȨ״̬ + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+121],4,SRAM_Register_Start_ADDRESS + Register_MandateUTC_OFFSET); + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+125],4,SRAM_Register_Start_ADDRESS + Register_MandateExpiresTime_OFFSET); + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN+129],128,SRAM_Register_Start_ADDRESS + Register_RoomNumNote_OFFSET); + Flash_Read(&Global_Large_Buff[BLV_UDP_HEAD_LEN+257],64,FLASH_MCU_Model_Revision_ADDRESS); + Flash_Read(&Global_Large_Buff[BLV_UDP_HEAD_LEN+321],64,FLASH_MCU_Control_Revision_ADDRESS); + + //temp_rev = Read_LogicFile_Information(0x04,(uint8_t *)&temp_data); //ѯLOGICļеľƵ - 32Byte + if(temp_rev == 0x00) + { + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+385],temp_data,32); + }else { + memset(temp_data,0,32); + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+385],temp_data,32); + } + //temp_rev = Read_LogicFile_Information(0x07,(uint8_t *)&temp_data); //ѯLOGICļеķ - 32Byte + if(temp_rev == 0x00) + { + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+417],temp_data,32); + }else { + memset(temp_data,0,32); + memcpy(&Global_Large_Buff[BLV_UDP_HEAD_LEN+417],temp_data,32); + } + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s ip:%d:%d:%d:%d Port:%d",__func__,ip[0],ip[1],ip[2],ip[3],port); + + //ݴ + NetCRC16(&Global_Large_Buff[0],back_len); + rev = WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], Global_Large_Buff, &back_len, ip, port); //SOCK_UDPS, + LOG_NET_COMM_Send_Record(0x01,ip,port,&Global_Large_Buff[0],back_len); + + return rev; +} + +/************************* +**Udp_Internal_PC_Testing_Reply +** dataܵ len ipַ port˿ +** ãUDPPC豸ظ +**ֵ + 0x00ݴɹ + 0xF0ݵCRCУʧ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_PC_Testing_Reply(uint8_t *reply_data,uint16_t reply_len,uint16_t pack_frame,uint8_t *ip,uint16_t port) +{ + UINT32 back_len = BLV_UDP_HEAD_LEN + reply_len + 3; + + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + + UDP_Add_Header(Global_Large_Buff,In_BLVPCTestDevice_Cmd,back_len,pack_frame); //ͷ + + for(uint16_t i=0;i= 0x8000)) + { + server_info.frame_no++; + } + else + { + server_info.frame_no = 0x8000; + } + + UDP_Add_Header(Global_Large_Buff,In_BLVPCTestDevice_Cmd,back_len,server_info.frame_no); //ͷ + + for(uint16_t i=0;i SRAM_Device_List_End_Addr)) return 0xF0; + + switch(control_dev) + { + case DEV_C5IO_Type: //C5IO ݴ + control_cmd = data[BLV_UDP_HEAD_LEN+3]; + if(control_cmd == BLV_C5IO_Set_Relay_CMD) //̵ + { + control_num = DataLen - BLV_UDP_HEAD_LEN - 2 - 4; + + if(control_num >= 6) control_num = 6; //Ŀǰ6ByteĿ + //Dbg_Println(DBG_OPT_DEVICE_STATUS,"NET PC Test C5IO_Control Len %d,Control_NUM:%d",DataLen,control_num); + + for(uint8_t i = 0;i> j*2) & 0x03; //״̬ + if(temp1 != 0x00) + { + //Dbg_Println(DBG_BIT_NET_STATUS_bit,"PC Test C5IO_Control_RelayCH%d status:%d",temp2,temp1); + uint8_t control[6]; + control[0] = Dev_Host_HVout; + control[1] = 0x00; + control[2] = temp2; //· + control[3] = 0x00; + control[4] = temp1; //״̬ + control[5] = 0x00; + + DevActionCtrl(control, 6); //̵ + } + } + } + }else if(control_cmd == BLV_C5IO_Set_Do_CMD) //DO + { + for(uint8_t i = 0;i<2;i++) + { + temp = data[BLV_UDP_HEAD_LEN + 4 + i]; + for(uint8_t j = 0;j<4;j++) + { + temp2 = i*4+j; //ƻ· + temp1 = (temp >> j*2) & 0x03; //״̬ + if(temp1 != 0x00) + { + //Dbg_Println(DBG_BIT_Debug_STATUS_bit,"PC Test C5IO_Control_DoCH%d status:%d",temp2,temp1); + BUS_C5IO_Control_Do(device_listaddr,temp2,temp1); + } + } + } + } + return 0x00; + case DEV_C5MUSIC_Type: + control_cmd = data[BLV_UDP_HEAD_LEN + 3]; + if(control_cmd == BLV_C5MUSIC_Specify_Play_CMD) + { + temp = data[BLV_UDP_HEAD_LEN + 4]; //״̬ + temp1 = data[BLV_UDP_HEAD_LEN + 5]; //ļ + temp2 = data[BLV_UDP_HEAD_LEN + 6]; //ID + + //Dbg_Println(DBG_BIT_NET_STATUS_bit,"PC Test C5Music_Control dir:%d id:%d status:%d",temp1,temp2,temp); + BUS_C5MUSIC_Playback(device_listaddr,temp1,temp,temp2); + } + + { + /*ظݴ*/ + uint8_t ack_buff[4] = {0}; + + ack_buff[0] = g_pc_test.test_flag; + ack_buff[1] = g_pc_test.test_dev; + ack_buff[2] = g_pc_test.test_addr; + ack_buff[3] = 0x01; //ִн + + Udp_Internal_PC_Testing_Reply(ack_buff,0x04,ack_frame,g_pc_test.pc_ip,g_pc_test.pc_port); + } + break; + case DEV_RS485_PWM: + + control_cmd = data[BLV_UDP_HEAD_LEN + 3]; + if(control_cmd == C12_SET_LIGHT_CMD) + { + temp = data[BLV_UDP_HEAD_LEN + 4]; //û· + temp1 = data[BLV_UDP_HEAD_LEN + 5]; //ֵ + temp2 = data[BLV_UDP_HEAD_LEN + 6]; //ʱ + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"PC Test C12Dimming:%d light:%d fade:%d",temp1,temp2,temp); + + if(temp) + { + UINT8 control[6]; + control[0] = DEV_RS485_PWM; + control[1] = 0x00; + control[2] = temp-1; //· + control[3] = 0x00; + control[4] = 0x01; //״̬ + control[5] = temp1; //ֵ + DevActionCtrl(control, 6); //̵ + } + + } + break; + default: break; + } + + + return 0x00; +} + +/************************* +**Udp_Internal_BLVPCTestDevice_Process +** dataܵ len ipַ port˿ +** ãBLV-C1PC·豸ݴ +**ֵ + 0x00ݴɹ + 0xF0ݵCRCУʧ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_BLVPCTestDevice_Process(uint8_t* data, uint16_t DataLen, uint8_t *ip,uint16_t port) +{ + /*CRCУ*/ + uint16_t data_crc = data[DataLen-2] + (data[DataLen-1] << 8); + if(NetCRC16_2(data,DataLen-2) != data_crc) return 0xF0; + + uint8_t temp1 = 0; + uint32_t dev_addr = 0; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s",__func__); + + dev_addr = Find_Device_List_Information(DEV_PCTEST_TYPE,DEV_PCTEST_Addr); + + Device_Public_Information_G BUS_Public; + PC_TEST_DEVICE_INFO PC_Test_Info; + + + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),dev_addr); + SRAM_DMA_Read_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + /**/ + temp1 = data[BLV_UDP_HEAD_LEN]; + if(temp1 == 0x01) // - ͬʱʱ + { + g_pc_test.test_flag = 0x11; + + g_pc_test.test_dev = data[BLV_UDP_HEAD_LEN + 1]; //豸 + g_pc_test.test_addr = data[BLV_UDP_HEAD_LEN + 2]; //豸ַ + PC_Test_Info.test_time = data[BLV_UDP_HEAD_LEN + 3]; //ʱ䣬λ + + PC_Test_Info.test_flag = g_pc_test.test_flag; + PC_Test_Info.test_tick = SysTick_1ms; + PC_Test_Info.test_time *= 60000; + + g_pc_test.pc_ip[0] = ip[0]; //2022-07-12 + g_pc_test.pc_ip[1] = ip[1]; + g_pc_test.pc_ip[2] = ip[2]; + g_pc_test.pc_ip[3] = ip[3]; + g_pc_test.pc_port = port; + } + else if(temp1 == 0x02) // + { + g_pc_test.test_flag = 0x12; + PC_Test_Info.test_flag = g_pc_test.test_flag; + PC_Test_Info.test_tick = SysTick_1ms; + PC_Test_Info.test_time = 120000; + + Udp_Internal_PC_Testing_DataDeal(data,DataLen,ip,port); + }else if(temp1 == 0x03) //Ѳز - 485˿ + { + g_pc_test.test_flag = 0x13; + PC_Test_Info.test_flag = g_pc_test.test_flag; + g_pc_test.tour_num = 0; + g_pc_test.tour_succ = 0; + + + g_pc_test.pc_ip[0] = ip[0]; + g_pc_test.pc_ip[1] = ip[1]; + g_pc_test.pc_ip[2] = ip[2]; + g_pc_test.pc_ip[3] = ip[3]; + g_pc_test.pc_port = port; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&PC_Test_Info, sizeof(PC_TEST_DEVICE_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),dev_addr);/*ݱ*/ + SRAM_DMA_Write_Buff((uint8_t *)&PC_Test_Info,sizeof(PC_TEST_DEVICE_INFO),dev_addr+Dev_Privately); + + return 0x00; +} + +/************************* +**UDP_Conversion_Baud +** dataܵ +** ãתΪӦIJ +**ֵӦIJ +************************/ +__attribute__((section(".non_0_wait"))) uint32_t UDP_Conversion_Baud(uint8_t data) +{ + uint32_t baud = 0; + switch(data) + { + case 0x01: + baud = 9600; + break; + case 0x02: + baud = 14400; + break; + case 0x03: + baud = 19200; + break; + case 0x04: + baud = 38400; + break; + case 0x05: + baud = 56000; + break; + case 0x06: + baud = 57600; + break; + case 0x07: + baud = 115200; + break; + } + return baud; +} + +/************************* +**UDP_Conversion_Baud +** dataܵ +** ãתΪӦIJ +**ֵӦIJ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t UDP_Baud_Conversion_Data(uint32_t data) +{ + uint8_t re_data = 0; + switch(data) + { + case 9600: + re_data = 0x01; + break; + case 14400: + re_data = 0x02; + break; + case 19200: + re_data = 0x03; + break; + case 38400: + re_data = 0x04; + break; + case 56000: + re_data = 0x05; + break; + case 57600: + re_data = 0x06; + break; + case 115200: + re_data = 0x07; + break; + } + return re_data; +} + +/************************* +**Udp_Internal_SeriaNet_Process +** dataܵ len ipַ port˿ +** ãBLV-C1͸ݴ +**ֵ + 0x00ݴɹ + 0xF0ݵCRCУʧ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_SeriaNet_Process(uint8_t* data, uint16_t DataLen, uint8_t *ip,uint16_t port) +{ + /*CRCУ*/ + uint16_t data_crc = data[DataLen-2] + (data[DataLen-1] << 8); + if(NetCRC16_2(data,DataLen-2) != data_crc) return 0xF0; + + uint8_t back_data[SeriaNet_Cmd_Send_Len]={0}; + UINT32 sendlen = SeriaNet_Cmd_Send_Len; + uint8_t temp = 0; + uint16_t pack_frame = 0,temp_len = 0; + + pack_frame = data[FRAME_NO_OFFSET] + (data[FRAME_NO_OFFSET+1]<<8); //֡ + + SRAM_DMA_Write_Buff(ip,4,SRAM_IAP_IP_ADDRESS); //PC IPַ + SRAM_Write_Word(port,SRAM_IAP_PORT_ADDRESS); //PC ˿ں + /*յ͸*/ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s IP:%02X.%02X.%02X.%02X Port:%d\r\n",__func__,ip[0],ip[1],ip[2],ip[3],port); + + /*͸ô*/ + temp = data[BLV_UDP_HEAD_LEN]; + switch(temp) + { + case 0x01: //͸״̬ѯ - ظ + UDP_Add_Header(back_data,In_SeriaNet_Cmd,SeriaNet_Cmd_Send_Len,pack_frame); //ͷ + back_data[BLV_UDP_HEAD_LEN] = 0x01; + + if(data[BLV_UDP_HEAD_LEN+1] == 0x01) //˿1 + { + back_data[BLV_UDP_HEAD_LEN+1] = Poll485_Info.port_mode; + Poll485_Info.mode_tick = SysTick_1s; + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x02) //˿2 + { + back_data[BLV_UDP_HEAD_LEN+1] = Act485_Info.port_mode; + Act485_Info.mode_tick = SysTick_1s; + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x03) //˿3 + { + back_data[BLV_UDP_HEAD_LEN+1] = BUS485_Info.port_mode; + BUS485_Info.mode_tick = SysTick_1s; + } + + NetCRC16(&back_data[0],SeriaNet_Cmd_Send_Len); + WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &back_data[0], &sendlen, ip, port); + break; + case 0x02: //͸ - ظ + UDP_Add_Header(back_data,In_SeriaNet_Cmd,SeriaNet_Cmd_Send_Len,pack_frame); //ͷ + back_data[BLV_UDP_HEAD_LEN] = 0x02; + back_data[BLV_UDP_HEAD_LEN+1] = 0x01; + + if(data[BLV_UDP_HEAD_LEN+1] == 0x01) //˿1 + { + Poll485_Info.baud = UDP_Conversion_Baud(data[BLV_UDP_HEAD_LEN+2]); //õIJ + if(Poll485_Info.baud != Polling_Baud) //ò + { + Poll485_Info.BaudRateCfg(Poll485_Info.baud); + } + Poll485_Info.mode_outtime = data[BLV_UDP_HEAD_LEN+3]*2; //ģʽʱʱ + Poll485_Info.port_mode = data[BLV_UDP_HEAD_LEN+4]; //ö˿ģʽ + Poll485_Info.mode_tick = SysTick_1s; + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x02) //˿2 + { + Act485_Info.baud = UDP_Conversion_Baud(data[BLV_UDP_HEAD_LEN+2]); //õIJ + if(Act485_Info.baud != Active_Baud) //ò + { + Act485_Info.BaudRateCfg(Act485_Info.baud); + } + Act485_Info.mode_outtime = data[BLV_UDP_HEAD_LEN+3]*2; //ģʽʱʱ + Act485_Info.port_mode = data[BLV_UDP_HEAD_LEN+4]; //ö˿ģʽ + Act485_Info.mode_tick = SysTick_1s; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Act485_Info.baud:%d",Act485_Info.baud ); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Act485_Info.pass_outtime:%d",Act485_Info.mode_outtime ); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Act485_Info.port_mode:%d",Act485_Info.port_mode ); + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x03) //˿3 + { + BUS485_Info.baud = UDP_Conversion_Baud(data[BLV_UDP_HEAD_LEN+2]); //õIJ + if(BUS485_Info.baud != Bus_Baud) //ò + { + + } + BUS485_Info.mode_outtime = data[BLV_UDP_HEAD_LEN+3]*2; //ģʽʱʱ + BUS485_Info.port_mode = data[BLV_UDP_HEAD_LEN+4]; //ö˿ģʽ + BUS485_Info.mode_tick = SysTick_1s; + }else { + back_data[BLV_UDP_HEAD_LEN+1] = 0x02; + } + + NetCRC16(&back_data[0],SeriaNet_Cmd_Send_Len); + WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &back_data[0], &sendlen, ip, port); + break; + case 0x03: //͸ݴ - 豸ظ豸ûظظ + if(data[BLV_UDP_HEAD_LEN+1] == 0x01) + { + Poll485_Info.mode_tick = SysTick_1s; + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x02) + { + Act485_Info.mode_tick = SysTick_1s; + }else if(data[BLV_UDP_HEAD_LEN+1] == 0x03) + { + BUS485_Info.mode_tick = SysTick_1s; + } + + /*͸ݷŵͻ*/ + temp_len = DataLen - 15 - 2 - 3; + //Dbg_Println(DBG_BIT_NET_STATUS_bit,"NET temp_len:%d ",temp_len ); + Write_Uart_SendBuff(data[BLV_UDP_HEAD_LEN+1],data[BLV_UDP_HEAD_LEN+2],&data[BLV_UDP_HEAD_LEN+3],temp_len); + break; + } + + return 0x00; +} + +/************************* +**Udp_Internal_SeriaNet_Uploading +** data_addrҪϱ - ݻ ǰ2byteֽΪݳ - ͸Ϊ480Byte +** ãBLV-C1͸Ϸ +**ֵ + 0x00ݴɹ + 0xF0ݵCRCУʧ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_SeriaNet_Uploading(uint8_t port,uint32_t baud,uint32_t data_addr) +{ + uint8_t pc_ip[4]; + uint16_t pc_port = 0; + uint32_t write_addr = data_addr; + UINT32 data_len = SRAM_Read_Word(data_addr); + + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; + + memset(pc_ip,0,sizeof(pc_ip)); + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + } + else + { + server_info.frame_no = 0x8000; + } + /*ȡPC IPַ*/ + SRAM_DMA_Read_Buff(pc_ip,4,SRAM_IAP_IP_ADDRESS); + pc_port = SRAM_Read_Word(SRAM_IAP_PORT_ADDRESS); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Udp_Internal_SeriaNet_Uploading IP:%02X.%02X.%02X.%02X Port:%d",pc_ip[0],pc_ip[1],pc_ip[2],pc_ip[3],pc_port); + + write_addr = data_addr+2; + SRAM_DMA_Read_Buff(&Global_Large_Buff[BLV_UDP_HEAD_LEN + 2],data_len,write_addr); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Udp_Internal_SeriaNet_Uploading Len:%d",data_len); + + data_len += 19; //ϰͷ15ByteβCRC2Byte + /**/ + UDP_Add_Header(Global_Large_Buff,In_SeriaNetReported_Cmd,data_len,server_info.frame_no); //ͷ + + Global_Large_Buff[BLV_UDP_HEAD_LEN] = port; //ǰݶ˿ں + Global_Large_Buff[BLV_UDP_HEAD_LEN + 1] = UDP_Baud_Conversion_Data(baud); //ǰݲ + + NetCRC16(&Global_Large_Buff[0],data_len); + WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &Global_Large_Buff[0], &data_len, pc_ip, pc_port); + + + return 0x00; + +} + +/************************* +**Udp_Internal_SeriaNet_Uploading +** data_addrҪϱ - ݻ ǰ2byteֽΪݳ - ͸Ϊ480Byte +** ãBLV-C1͸Ϸ +**ֵ + 0x00ݴɹ + 0xF0ݵCRCУʧ +************************/ +__attribute__((section(".non_0_wait"))) uint8_t Udp_Internal_SeriaNet_Uploading2(uint8_t port,uint32_t baud,uint8_t* data, uint16_t DataLen) +{ + uint8_t pc_ip[4]; + uint16_t pc_port = 0; + UINT32 data_len = DataLen + 19; + + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; + + memset(pc_ip,0,sizeof(pc_ip)); + memset(Global_Large_Buff,0,sizeof(Global_Large_Buff)); + + if((server_info.frame_no < 0xfffe) && (server_info.frame_no >= 0x8000)) + { + server_info.frame_no++; + } + else + { + server_info.frame_no = 0x8000; + } + /*ȡPC IPַ*/ + SRAM_DMA_Read_Buff(pc_ip,4,SRAM_IAP_IP_ADDRESS); + pc_port = SRAM_Read_Word(SRAM_IAP_PORT_ADDRESS); + + + UDP_Add_Header(Global_Large_Buff,In_SeriaNetReported_Cmd,data_len,server_info.frame_no); //ͷ + + Global_Large_Buff[BLV_UDP_HEAD_LEN] = port; //ǰݶ˿ں + Global_Large_Buff[BLV_UDP_HEAD_LEN + 1] = UDP_Baud_Conversion_Data(baud); //ǰݲ + + for(uint16_t i = 0;i= 0x8000)) + { + server_info.frame_no++; + } + else + { + server_info.frame_no = 0x8000; + } + /*ȡPC IPַ*/ + SRAM_DMA_Read_Buff(pc_ip,4,SRAM_IAP_IP_ADDRESS); + pc_port = SRAM_Read_Word(SRAM_IAP_PORT_ADDRESS); + + + UDP_Add_Header(back_data,In_SeriaNet_Cmd,data_len,server_info.frame_no); //ͷ + back_data[BLV_UDP_HEAD_LEN] = 0x03; //͸ظ + back_data[BLV_UDP_HEAD_LEN + 1] = 0x03; //ʱ״̬ + + NetCRC16(&back_data[0],data_len); + WCHNET_SocketUdpSendTo(g_netinfo.SocketId[SocketIdnex_BLVSeriver], &back_data[0], &data_len, pc_ip, pc_port); + + + return 0x00; +} + + +/******************************************* +* BLV_UDP_Comm_Task +* +* ãص +* ֵ +* ÷ʽѭе +********************************************/ +__attribute__((section(".non_0_wait"))) void BLV_UDP_Comm_Task(void) +{ + static uint32_t udp_state_tick = 0; + uint32_t temp_val = 0; + + /*Ҫ - */ + if( SysTick_1ms - udp_state_tick >= 100 ) + { + udp_state_tick = SysTick_1ms; + + if(server_info.init_flag == 0x00) return ; //DNSʧֱ˳ + + /*ҲTFTP*/ +// if(IAPVarTypeStruct_Ptr != NULL) +// { +// if(IAPSTART == IAPVarTypeStruct_Ptr->IapState) +// { +// Dbg_Println(DBG_BIT_NET_STATUS_bit,"RoomState_Cmdͣ,IAP.."); +// return; +// } +// } + + server_info.udp_scan_cnt++; + if(server_info.udp_scan_cnt >= 9) + { + server_info.udp_scan_cnt = 0x00; + + server_info.udp_timesync_cnt++; + server_info.udp_periodic_cnt++; + + //жʱͬ - ûеʱ + if(server_info.udp_timesync_cnt >= 7200){ + server_info.udp_timesync_cnt = 0x00; + server_info.active_cmd_flag |= UDP_ActSend_TimeSync_Flag; + } + //ж϶ϱ - ûеʱ + if(server_info.udp_periodic_cnt >= server_info.udp_periodic_time){ + server_info.udp_periodic_cnt = 0x00; + server_info.active_cmd_flag |= UDP_ActSend_Periodic_Flag; + } + + //жRCUԭ־λɲ + if(server_info.rcu_reboot_flag == 0x01){ + server_info.rcu_reboot_flag = 0x00; + + server_info.active_cmd_flag |= UDP_ActSend_Reboot_Flag; //ϱRCUԭ + } + + //UDP_ActSend_PowerChange_Scan_State(); //ɨȡϱ + + //Udp_Scan_Roomstate(); //ɨ跿豸״̬ + } + + switch(server_info.udp_sta) + { + case 0x01: //ע + if(server_info.register_flag == 0x01) + { + if(SysTick_1s - server_info.register_tick > USER_NET_Register_Timeout) //ÿ30S һע + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"UDPעݷͳʱ %d",server_info.register_num); + server_info.register_tick = SysTick_1s; + server_info.register_num++; + server_info.register_flag = 0x00; + + if(server_info.register_num >= USER_NET_Register_Times) server_info.init_flag = 0x00; + } + + return ; + } + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"UDPעݷ"); + UDP_Search_Ack(); //ڷһֱע + server_info.udp_idle_tick = SysTick_1ms; + server_info.register_flag = 0x01; + server_info.register_tick = SysTick_1s; + break; + case 0x02: //жݰǷҪ + + /*UDP жǷﵽ״̬*/ + if(SysTick_1ms - server_info.udp_idle_tick >= 30000) + { + server_info.udp_idle_tick = SysTick_1ms; + + // + server_info.active_cmd_flag |= UDP_ActSend_Heart_Flag; + } + + /*UDP ж*/ + if(SysTick_1ms - server_info.udp_online_tick >= server_info.udp_online_time) + { + server_info.udp_online_tick = SysTick_1ms; + + server_info.init_flag = 0x00; //UDP + //LOG_SYS_Server_Comm_State_Record(RCU_NO_SERVER); + return ; + } + + for(uint8_t i=0;i<7;i++) + { + if( ( server_info.active_cmd_flag & (0x01 << i) ) != 0x00 ) + { + server_info.udp_send_flag = 0x01 << i; + server_info.udp_sta = 0x03; + + server_info.udp_retry_cnt = 0x00; + server_info.udp_retry_time = 2000; + break; + } + } + + break; + case 0x03: //ݰ + switch(server_info.udp_send_flag) + { + case 0x01: //ȡϵϱ - ȼ + Udp_Internal_Power_Change_Report_CMD(); + + server_info.udp_retry_num = 0x02; //һ3 + server_info.udp_retry_tick = SysTick_1ms; + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_sta = 0x04; //뷢͵ȴ + break; + case 0x02: //豸״̬ϱ - + //Udp_Internal_RoomState(); + + server_info.udp_retry_num = 0x02; //һ3 + server_info.udp_retry_tick = SysTick_1ms; + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_sta = 0x04; //뷢͵ȴ + break; + case 0x04: //ϱ - ֻһ + //Udp_Internal_Periodic_Report_PackSend(); + + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_send_flag = 0x00; + server_info.active_cmd_flag &= ~UDP_ActSend_Periodic_Flag; + server_info.udp_sta = 0x02; + break; + case 0x08: //ϱRCUԭ - + //Udp_Internal_Reboot_Reason_Report_CMD(); + + server_info.udp_retry_num = 0x02; //һ3 + server_info.udp_retry_tick = SysTick_1ms; + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_sta = 0x04; //뷢͵ȴ + break; + case 0x10: //ȡ̬ - + Udp_Internal_GetRoomRent_CMD(); + + server_info.udp_retry_num = 0x02; //һ3 + server_info.udp_retry_tick = SysTick_1ms; + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_sta = 0x04; //뷢͵ȴ + break; + case 0x20: //ʱͬ - + Udp_Internal_GetTime_CMD(); + + server_info.udp_retry_num = 0x02; //һ3 + server_info.udp_retry_tick = SysTick_1ms; + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_sta = 0x04; //뷢͵ȴ + break; + case 0x40: // - 30S һ + UDP_Heart_Send(); + + server_info.udp_idle_tick = SysTick_1ms; + server_info.udp_send_flag = 0x00; + server_info.active_cmd_flag &= ~UDP_ActSend_Heart_Flag; + server_info.udp_sta = 0x02; + break; + default: + server_info.udp_sta = 0x02; + break; + } + return ; //ֱ˳ + + case 0x04: //ȴACK + + if(server_info.udp_send_flag == 0x00) { + server_info.udp_sta = 0x02; //յظˣ + break; + } + + if( server_info.udp_retry_cnt <= server_info.udp_retry_num ) + { + if( SysTick_1ms - server_info.udp_retry_tick >= server_info.udp_retry_time) + { + server_info.udp_retry_tick = SysTick_1ms; + //ͳʱ + + server_info.udp_retry_cnt++; + if(server_info.udp_retry_cnt > server_info.udp_retry_num) + { + //طѴޣͱ־λ + + if(server_info.udp_send_flag == 0x02) //豸״̬ʧܣͻ + { + temp_val = SRAM_Read_DW(SRAM_UDP_SendData_Tempaddr); + SRAM_Write_DW(temp_val, SRAM_UDP_SendData_Readaddr); //ַλ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ϱ豸״̬ʧ :%8X",temp_val); + + temp_val = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR); //ʱĹ϶ȡַ + SRAM_Write_DW(temp_val, SRAM_DEVICE_ONLINE_STATE_READ_ADDR); //϶ַ¸ֵ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ϱ豸ʧ :%8X",temp_val); + } + + server_info.active_cmd_flag &= ~server_info.udp_send_flag; + server_info.udp_sta = 0x02; // + }else { + server_info.udp_sta = 0x03; //ݷ + server_info.udp_retry_time += 2000; + } + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"udp_retry:%02x - %d - %d",server_info.udp_send_flag,server_info.udp_retry_cnt,server_info.udp_retry_time); + } + }else { + //طѴޣͱ־λ + + server_info.active_cmd_flag &= ~server_info.udp_send_flag; + server_info.udp_sta = 0x02; // + } + break; + default: + server_info.udp_sta = 0x02; + break; + } + + } + + /* - ıظ ʱ ʱMACַһλ * 2ms */ + if(server_info.search_ack_flag == 0x01) + { + uint32_t temp_tick = 0; + + temp_tick = g_netinfo.mac_addr[5]; + temp_tick = temp_tick * 2; + + if( SysTick_1ms - server_info.search_ack_tick >= temp_tick ) + { + server_info.search_ack_tick = SysTick_1ms; + server_info.search_ack_flag = 0x00; + + //Udp_Internal_Read_MCU_System_SendAck(server_info.udp_ip,server_info.local_port,server_info.ack_frame); + } + } + + +} diff --git a/MCU_Driver/blv_rs485_protocol.c b/MCU_Driver/blv_rs485_protocol.c new file mode 100644 index 0000000..bd67df5 --- /dev/null +++ b/MCU_Driver/blv_rs485_protocol.c @@ -0,0 +1,1661 @@ +/* + * blv_rs485_protocol.c + * + * Created on: Nov 10, 2025 + * Author: cc + */ +#include "includes.h" +#include + +BLV_BUS_Manage_G BUS485_Info; +BLV_ACTIVE_Manage_G Act485_Info; +BLV_POLL_Manage_G Poll485_Info; +BLV_NORDEV_Manage_G NorDevInfoGlobal; /*ͨ豸ȫֱ*/ + +uint8_t rs485_temp_buff[612]; + +/******************************************************************************* +* Function Name : Add_BUS_Device_To_List +* Description : BUS豸 +* Input : + dev_info : ӵ豸 + dev_data : 豸˽ + data_len 豸˽ݳ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Add_BUS_Device_To_List( + Device_Public_Information_G *dev_info, + uint8_t *dev_data, + uint16_t data_len) +{ + /*豸BUS485豸*/ + dev_info->data_len = data_len + Dev_Privately; //豸˽ݳȼϹ + uint32_t list_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr); //ȡ豸Ϣַ + if((list_addr < SRAM_Device_List_Start_Addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = SRAM_Device_List_Start_Addr; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately); + memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len); + + dev_info->check = 0x00; + dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len); + SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr); + +// /*ӹ*/ +// SRAM_DMA_Write_Buff(rs485_temp_buff,Dev_Privately,list_addr); +// +// /*豸˽б*/ +// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately); +// +// /*Уֵ*/ +// check_val = Dev_CheckSum(list_addr,dev_info->data_len); +// SRAM_Write_Byte(check_val,list_addr+Dev_Check); //Уֵд + +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len); +// for(uint16_t i = 0;i < write_len;i++) +// { +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i)); +// } +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n"); + + /*豸,豸ַƫ*/ + list_addr += SRAM_Device_List_Size; + SRAM_Write_DW(list_addr,SRAM_BUS_Device_List_Addr); +} + +/******************************************************************************* +* Function Name : Add_POLL_Device_To_List +* Description : ѯ豸 +* Input : + dev_info : ӵ豸 + dev_data 豸˽ + addr : 豸˽ݳ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Add_POLL_Device_To_List( + Device_Public_Information_G *dev_info, + uint8_t *dev_data, + uint16_t data_len) +{ + /*豸POLL485豸*/ + + dev_info->data_len = data_len + Dev_Privately; //豸˽ݳȼϹ + + uint32_t list_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr); //ȡ豸Ϣַ + uint32_t Start_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr); //ȡѯ豸Ϣʼַ + if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr)) + { + Start_addr = SRAM_Device_List_Start_Addr; + SRAM_Write_DW(Start_addr,SRAM_BUS_Device_List_Addr); + } + if( (list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately); + memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len); + + dev_info->check = 0x00; + dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len); + SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr); + +// /**/ +// for(uint16_t i = 0;ipolling_cf,list_addr+Dev_Polling_CF); +// +// SRAM_Write_DW(dev_info->processing_cf,list_addr+Dev_Processing_CF); +// +// /*豸˽б*/ +// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately); +// +// /*Уֵ*/ +// dev_info->check = Dev_CheckSum(list_addr,dev_info->data_len); +// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //Уֵд + +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len); +// for(uint16_t i = 0;i < write_len;i++) +// { +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i)); +// } +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n"); + + /*豸,豸ַƫ*/ + list_addr += SRAM_Device_List_Size; + SRAM_Write_DW(list_addr,SRAM_POLL_Device_List_Addr); +} + +/******************************************************************************* +* Function Name : Add_ACT_Device_To_List2 +* Description : 豸 +* Input : + dev_info : ӵ豸 + dev_data 豸˽ + addr : 豸˽ݳ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Add_ACT_Device_To_List( + Device_Public_Information_G *dev_info, + uint8_t *dev_data, + uint16_t data_len) +{ + /*豸POLL485豸*/ + dev_info->check = 0x00; + dev_info->data_len = data_len + Dev_Privately; //豸˽ݳȼϹ + + uint32_t list_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //ȡ豸Ϣַ + uint32_t Start_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr); //ȡѯ豸Ϣʼַ + + if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr)) + { + Start_addr = SRAM_Device_List_Start_Addr; + SRAM_Write_DW(Start_addr,SRAM_POLL_Device_List_Addr); + } + if((list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately); + memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len); + + dev_info->check = 0x00; + dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len); + SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr); + +// /**/ +// for(uint16_t i = 0;ipolling_cf,list_addr+Dev_Polling_CF); +// +// SRAM_Write_DW(dev_info->processing_cf,list_addr+Dev_Processing_CF); +// +// /*豸˽б*/ +// SRAM_DMA_Write_Buff(dev_data,data_len,list_addr+Dev_Privately); +// +// /*Уֵ*/ +// dev_info->check = Dev_CheckSum(list_addr,dev_info->data_len); +// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //Уֵд + +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len); +// for(uint16_t i = 0;i < write_len;i++) +// { +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i)); +// } +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n"); + + /*豸,豸ַƫ*/ + list_addr += SRAM_Device_List_Size; + SRAM_Write_DW(list_addr,SRAM_ACTIVE_Device_List_Addr); +} + +/******************************************************************************* +* Function Name : Add_Nor_Device_To_List2 +* Description : ͨ豸 +* Input : + Device_Public_Information_G *dev_info : ӵ豸 + dev_data 豸˽ + data_len : 豸˽ݳ + +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Add_Nor_Device_To_List( + Device_Public_Information_G *dev_info, + uint8_t *dev_data, + uint16_t data_len) +{ + /*豸ͨ豸*/ + + dev_info->data_len = data_len + Dev_Privately; //豸˽ݳȼϹݵij + + uint32_t list_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr); //ȡ豸Ϣַ + uint32_t Start_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //ȡ豸Ϣʼַ + + if((Start_addr < SRAM_Device_List_Start_Addr) || (Start_addr > SRAM_Device_List_End_Addr)) + { + Start_addr = SRAM_Device_List_Start_Addr; + SRAM_Write_DW(Start_addr,SRAM_ACTIVE_Device_List_Addr); + } + if((list_addr < Start_addr) || (list_addr > SRAM_Device_List_End_Addr)) list_addr = Start_addr; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately); + memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len); + + dev_info->check = 0x00; + dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len); + SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,list_addr); + +// /**/ +// for(uint16_t i = 0;icheck = Dev_CheckSum(list_addr,dev_info->data_len); +// SRAM_Write_Byte(dev_info->check,list_addr+Dev_Check); //Уֵд + +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"data_len :%d ,dev Buffer:" , write_len); +// for(uint16_t i = 0;i < write_len;i++) +// { +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%02X " , SRAM_Read_Byte(list_addr + i)); +// } +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"\r\n"); + + /*豸,豸ַƫ*/ + list_addr += SRAM_Device_List_Size; + SRAM_Write_DW(list_addr,SRAM_NORMAL_Device_List_Addr); +} + +/******************************************************************************* +* Function Name : BLV_Device_Info_Write_To_SRAM +* Description : 豸д뵽SRAM +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t BLV_Device_Info_Write_To_SRAM( + uint32_t dev_addr, + Device_Public_Information_G *dev_info, + uint8_t *dev_data, + uint16_t data_len) +{ + if(dev_info == NULL) return 1; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + memcpy(rs485_temp_buff,(uint8_t *)dev_info,Dev_Privately); + memcpy(&rs485_temp_buff[Dev_Privately],(uint8_t *)dev_data,data_len); + + dev_info->check = 0x00; + dev_info->check = Data_CheckSum(rs485_temp_buff,dev_info->data_len); + SRAM_DMA_Write_Buff(rs485_temp_buff,dev_info->data_len,dev_addr); + return 0x00; +} + +/******************************************************************************* +* Function Name : Device_Data_Check +* Description : 豸У +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Device_Data_Check(uint32_t sram_addr) +{ + uint16_t data_len = SRAM_Read_Word(sram_addr + Dev_DataLen); + uint8_t data_sum = 0; + if(data_len > SRAM_Device_List_Size) return 1; + + memset(rs485_temp_buff,0,sizeof(rs485_temp_buff)); + + SRAM_DMA_Read_Buff(rs485_temp_buff,data_len,sram_addr); + + for(uint16_t i = 0;i= SRAM_Read_DW(SRAM_BUS_Device_List_Addr)) BUS485_Info.Last_list_addr = SRAM_Device_List_Start_Addr; + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS Change_Dev"); + BUS485_Info.BUS_Start = B_Polling; + break; + case B_Retry: + if((BUS485_Info.Retry_Flag == 0x01) && (BUS485_Info.n_retry_num != 0x00)) //ط־δ㣬ʾûͳɹ + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS Retransmitting Data:%d-%d-%08X...",BUS485_Info.n_dev_type,BUS485_Info.n_dev_addr,BUS485_Info.n_list_read_addr); + + //޸ʱ:2022-07-12 + if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //豸ͺ + + if(rev == RS485OCCUPYNOTIME) //лһ豸 + { + BUS485_Info.BUS_Start = Change_Dev; + /*BUS485вҪѯݵ豸Ҫȴظ׶ֱл豸ط־λҪλ - 2022-05-04*/ + BUS485_Info.Retry_Flag = 0x00; + BUS485_Info.n_retry_num = 0x00; + }else { //ݷͳɹȴظ + BLV_BUS_Wait = SysTick_1ms; //¼ʱ + BUS485_Info.n_retry_num--; + BUS485_Info.BUS_Start = Wait_Reply; + } + + }else if((BUS485_Info.Retry_Flag == 0x01) && (BUS485_Info.n_retry_num == 0x00)) + { + BUS485_Info.BUS_Start = Change_Dev; //ʧܣл¸豸 + }else { //2021-06-29 + BUS485_Info.BUS_Start = Change_Dev; //ʧܣл¸豸 + } + break; + case Wait_Reply: + /*մ*/ + if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr); + + if((BUS485_Info.n_processing_cf!=0x00000000) && (BUS485_Info.n_processing_cf!=0xFFFFFFFF)) { + BUS485_Info.Retry_Flag = ((fun2_prt)BUS485_Info.n_processing_cf)(BUS485_Info.n_list_read_addr,g_uart[UART_3].RX_Buffer_ReadAddr + 2,data_len); + } + + if(BUS485_Info.Retry_Flag == 0x00) { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC\r\n"); + BUS485_Info.send_wait = SysTick_1ms; + BUS485_Info.BUS_Start = B_Wait; //ظɹȴ߿УлΪһ豸 + } + + if(BUS485_Info.port_mode == Port_Monitoring_mode) //ǰڼģʽ,ݷPC + { + Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //ϱ + } + + g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) { + g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr; + } + } + /*ճʱ - ط*/ + if(SysTick_1ms - BLV_BUS_Wait > BUS485_Info.n_dev_waittime) BUS485_Info.BUS_Start = B_Retry; + break; + case B_Wait: + if(SysTick_1ms - BUS485_Info.send_wait > BLV_BUS485_WaitLdle_Time) { + + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS B_Wait"); + BUS485_Info.BUS_Start = Change_Dev; + } + //BUS485_Info.BUS_Start = Change_Dev; + break; + /*2021-11-24 : C5IOʲ׼ǰݵǰ豸ͨѶʣлͲʣл겨ʺ󣬵ȴ10msڽз + 2022-07-19 : лʱͨѶһΣջݲֱӶ + */ + + case Baud_Wait: //лʵȴʱ + if(SysTick_1ms - BUS485_Info.change_tick > BLV_BUS485_ChangeBaudWaitTime) + { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Wait"); + + if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //豸ͺ + + BUS485_Info.change_tick = SysTick_1ms; + BUS485_Info.BUS_Start = Baud_Comm; + } + + break; + case Baud_Comm: + /*մ*/ + if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr); + + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm1"); + + if((BUS485_Info.n_processing_cf!=0x00000000) && (BUS485_Info.n_processing_cf!=0xFFFFFFFF)) { + BUS485_Info.Retry_Flag = ((fun2_prt)BUS485_Info.n_processing_cf)(BUS485_Info.n_list_read_addr,g_uart[UART_3].RX_Buffer_ReadAddr + 2,data_len); + } + if(BUS485_Info.Retry_Flag == 0x00) //ظɹʼһͨѶ + { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm3"); + BUS485_Info.BUS_Start = Baud_SendWait; + BUS485_Info.change_tick = SysTick_1ms; + } + + + if(BUS485_Info.port_mode == Port_Monitoring_mode) //ǰڼģʽ,ݷPC + { + Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //ϱ + } + + g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) { + g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr; + } + } + /*յȴʱ*/ + if(SysTick_1ms - BUS485_Info.change_tick > BUS485_Info.n_dev_waittime) { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm2"); + BUS485_Info.change_tick = SysTick_1ms; + BUS485_Info.BUS_Start = Baud_SendWait; + } + break; + case Baud_SendWait: + if(SysTick_1ms - BUS485_Info.change_tick > BLV_BUS485_ChangeBaudSendWaitTime) { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- Baud_Comm2"); + BUS485_Info.change_tick = SysTick_1ms; + BUS485_Info.BUS_Start = B_Send; + } + break; + case B_Send: //ͺ + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_BUS State -- send"); + + //if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) Convert_To_Fun_Prt(BUS485_Info.n_polling_cf,BUS485_Info.n_list_read_addr); + + //޸ʱ:2022-07-12 + if((BUS485_Info.n_polling_cf!=0x00000000) && (BUS485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)BUS485_Info.n_polling_cf)(BUS485_Info.n_list_read_addr); //豸ͺ + + if(rev == RS485OCCUPYNOTIME) //лһ豸 + { + BUS485_Info.BUS_Start = Change_Dev; + /*BUS485вҪѯݵ豸Ҫȴظ׶ֱл豸ط־λҪλ - 2022-05-04*/ + BUS485_Info.Retry_Flag = 0x00; + BUS485_Info.n_retry_num = 0x00; + }else { //ݷͳɹȴظ + BLV_BUS_Wait = SysTick_1ms; //¼ʱ + BUS485_Info.BUS_Start = Wait_Reply; + } + + break; + default: + BUS485_Info.BUS_Start = Change_Dev; + break; + + } + + /*ǰǴģʽ£ʱعģʽ*/ + if(BUS485_Info.port_mode != Port_Normal_Mode) + { + if(SysTick_1s - BUS485_Info.mode_tick > BUS485_Info.mode_outtime) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC"); + BUS485_Info.mode_tick = SysTick_1s; + BUS485_Info.port_mode = Port_Normal_Mode; //ģʽ + } + } +} + +/******************************************************************************* +* Function Name : BUS485Port_Passthrough_Task +* Description : BUSPort BUS˿͸ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BUS485Port_Passthrough_Task(void) +{ + uint16_t data_len = 0; + switch(BUS485_Info.pass_state) + { + case B_IDLE: //״̬ - жǷϱ· + /*մ*/ + if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr); + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len); + Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); //ϱ + + g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr; + + } + + if(g_uart[UART_3].TX_Buffer_WriteAddr != g_uart[UART_3].TX_Buffer_ReadAddr) + { + /*ȡͻ - ·*/ + data_len = SRAM_Read_Word(g_uart[UART_3].TX_Buffer_ReadAddr); + BUS485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_3].TX_Buffer_ReadAddr + 2); //λS + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸ݳ + BUS485_Info.pass_tick = SysTick_1s; + + MCU485_SendSRAMData(Bus_port,g_uart[UART_3].TX_Buffer_ReadAddr + 3,data_len); //· + + BUS485_Info.pass_state = Wait_Reply; + + g_uart[UART_3].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].TX_Buffer_ReadAddr > SRAM_UART3_SendBuffer_End_Addr) g_uart[UART_3].TX_Buffer_ReadAddr = SRAM_UART3_SendBuffer_Start_Addr; + } + + if(SysTick_1s - BUS485_Info.mode_tick > BUS485_Info.mode_outtime) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BUS485_Info Port_Normal_Mode mode_outtime"); + BUS485_Info.mode_tick = SysTick_1s; + BUS485_Info.port_mode = Port_Normal_Mode; //ģʽ + BUS485_Info.baud = Bus_Baud; + } + break; + case Wait_Reply: //ȴظ - ظʱĻ - ϱ + /*մ*/ + if(g_uart[UART_3].RX_Buffer_WriteAddr != g_uart[UART_3].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_3].RX_Buffer_ReadAddr); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len); + + Udp_Internal_SeriaNet_Uploading(Bus_port,BUS485_Info.baud,g_uart[UART_3].RX_Buffer_ReadAddr); + + BUS485_Info.pass_state = B_IDLE; //״̬ + + g_uart[UART_3].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].RX_Buffer_ReadAddr > SRAM_UART3_RecvBuffer_End_Addr) g_uart[UART_3].RX_Buffer_ReadAddr = SRAM_UART3_RecvBuffer_Start_Addr; + } + + if(SysTick_1s - BUS485_Info.pass_tick > BUS485_Info.pass_outtime) + { + //ظʱ + Udp_Internal_SeriaNet_Response_Timeout(); + BUS485_Info.pass_state = B_IDLE; //״̬ + } + + break; + default: + BUS485_Info.pass_state = B_IDLE; //״̬ + break; + + } +} + +/******************************************************************************* +* Function Name : BLV_BUS485Port_ModeTask +* Description : BUS˿ģʽ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_BUS485Port_ModeTask(void) +{ + switch(BUS485_Info.port_mode) + { + case Port_Passthrough_mode: + BUS485Port_Passthrough_Task(); //͸ģʽ + break; + case Port_Normal_Mode: + case Port_Monitoring_mode: + + BLV_BUS_Polling_Task(); //ģʽ Լģʽ¼ģʽ + + break; + } +} + +/******************************************************************************* +* Function Name : BLV_PollPort_Task +* Description : PollPortѯ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_PollPort_Task(void) +{ + static uint32_t BLV_POLL_Wait = 0; + uint16_t data_len = 0; + uint8_t rev = 0; + + if(Poll485_Info.device_num == 0x00) return ; + + switch(Poll485_Info.POLL_Start) + { + case B_IDLE: + Poll485_Info.POLL_Start = B_Polling; + break; + case B_Polling: + if(SRAM_Read_Byte(Poll485_Info.Last_list_addr + Dev_port) == Polling_Port) + { + /*У*/ + if(Device_Data_Check(Poll485_Info.Last_list_addr) == 0) + { + Poll485_Info.n_list_read_addr = Poll485_Info.Last_list_addr; + /*л*/ + if(Poll485_Info.baud != SRAM_Read_DW(Poll485_Info.n_list_read_addr + Dev_baud)) + { + Poll485_Info.baud = SRAM_Read_DW(Poll485_Info.n_list_read_addr + Dev_baud); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev change baud:%08X",Poll485_Info.baud); + Poll485_Info.BaudRateCfg( Poll485_Info.baud ); + Poll485_Info.POLL_Start = Baud_Wait; + Poll485_Info.change_tick = SysTick_1ms; + }else { + /*ȡ豸Ϣ*/ + Device_Public_Information_G dev_info; + SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Poll485_Info.n_list_read_addr); + + Poll485_Info.n_dev_type = dev_info.type; + Poll485_Info.n_dev_addr = dev_info.addr; + Poll485_Info.n_dev_datalen = dev_info.data_len; + Poll485_Info.n_polling_cf = dev_info.polling_cf; + Poll485_Info.n_processing_cf = dev_info.processing_cf; + Poll485_Info.n_dev_waittime = dev_info.wait_time; + + Poll485_Info.n_retry_num = dev_info.retry_num; + Poll485_Info.Retry_Flag = 0x01; + + /*2021 09 17 ޸ӷͺֵжϣRS485OCCUPYNOTIMEʾûзݣ豸*/ + + if((Poll485_Info.n_polling_cf!=0x00000000) && (Poll485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr); + + if(rev == RS485OCCUPYNOTIME) //лһ豸 + { + Poll485_Info.POLL_Start = Change_Dev; + }else { //ݷͳɹȴظ + BLV_POLL_Wait = SysTick_1ms; + Poll485_Info.POLL_Start = Wait_Reply; + } + } + }else { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev Check Fail:%08X",Poll485_Info.Last_list_addr); + Poll485_Info.POLL_Start = Change_Dev; + } + }else { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_POLL_dev Type Fail:%08X , %d",Poll485_Info.Last_list_addr,SRAM_Read_Byte(Poll485_Info.Last_list_addr + Dev_Type)); + Poll485_Info.POLL_Start = Change_Dev; + } + + break; + case Baud_Wait: + if(SysTick_1ms - Poll485_Info.change_tick > BLV_POLL485_ChangeBaudWaitTime) + { + /*ȡ豸Ϣ*/ + + Device_Public_Information_G dev_info; + SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Poll485_Info.n_list_read_addr); + + Poll485_Info.n_dev_type = dev_info.type; + Poll485_Info.n_dev_addr = dev_info.addr; + Poll485_Info.n_dev_datalen = dev_info.data_len; + Poll485_Info.n_polling_cf = dev_info.polling_cf; + Poll485_Info.n_processing_cf = dev_info.processing_cf; + Poll485_Info.n_dev_waittime = dev_info.wait_time; + + Poll485_Info.n_retry_num = dev_info.retry_num; + + Poll485_Info.Retry_Flag = 0x01; + + /*2021 09 17 ޸ӷͺֵжϣ0xF0ʾûзݣ豸*/ + + if((Poll485_Info.n_polling_cf!=0x00000000) && (Poll485_Info.n_polling_cf!=0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr); + + if(rev == RS485OCCUPYNOTIME) //лһ豸 + { + Poll485_Info.POLL_Start = Change_Dev; + }else { //ݷͳɹȴظ + BLV_POLL_Wait = SysTick_1ms; + Poll485_Info.POLL_Start = Wait_Reply; + } + } + break; + case Change_Dev: + Poll485_Info.Last_list_addr += SRAM_Device_List_Size; //һ豸 + if(Poll485_Info.Last_list_addr >= SRAM_Read_DW(SRAM_POLL_Device_List_Addr)) Poll485_Info.Last_list_addr = SRAM_Read_DW(SRAM_BUS_Device_List_Addr); + + Poll485_Info.POLL_Start = B_Polling; + break; + case B_Retry: + if((Poll485_Info.Retry_Flag == 0x01) && (Poll485_Info.n_retry_num != 0x00)) //ط־δ㣬ʾûͳɹ + { + /*2021 09 17 ޸ӷͺֵжϣ0xF0ʾûзݣ豸*/ + if((Poll485_Info.n_polling_cf != 0x00000000) && (Poll485_Info.n_polling_cf != 0xFFFFFFFF)) rev = ((fun4_prt)Poll485_Info.n_polling_cf)(Poll485_Info.n_list_read_addr); + + if(rev == RS485OCCUPYNOTIME) //лһ豸 + { + Poll485_Info.POLL_Start = Change_Dev; + }else { //ݷͳɹȴظ + BLV_POLL_Wait = SysTick_1ms; //¼ʱ + Poll485_Info.n_retry_num--; + Poll485_Info.POLL_Start = Wait_Reply; + } + }else if((Poll485_Info.Retry_Flag == 0x01) && (Poll485_Info.n_retry_num == 0x00)) + { + Poll485_Info.POLL_Start = Change_Dev; //ʧܣл¸豸 + }else { + Poll485_Info.POLL_Start = Change_Dev; + } + break; + case Wait_Reply: + /*մ*/ + if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr); + + if((Poll485_Info.n_processing_cf!=0x00000000) && (Poll485_Info.n_processing_cf!=0xFFFFFFFF)) { + Poll485_Info.Retry_Flag = ((fun2_prt )Poll485_Info.n_processing_cf)(Poll485_Info.n_list_read_addr,g_uart[UART_0].RX_Buffer_ReadAddr + 2,data_len); + } + + if(Poll485_Info.Retry_Flag == 0x00) { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Reply SUCC\r\n"); + Poll485_Info.send_wait = SysTick_1ms; + Poll485_Info.POLL_Start = B_Wait; //ظɹȴ߿УлΪһ豸 + } + + if(Poll485_Info.port_mode == Port_Monitoring_mode) //ǰڼģʽ,ݷPC + { + Udp_Internal_SeriaNet_Uploading(Polling_Port,Poll485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr); //ϱ + } + + g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) { + g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr; + } + } + /*ճʱ - ط*/ + if(SysTick_1ms - BLV_POLL_Wait > Poll485_Info.n_dev_waittime) Poll485_Info.POLL_Start = B_Retry; + break; + case B_Wait: //ͳɹȴʱ + if(SysTick_1ms - BLV_POLL_Wait > Poll485_Info.n_dev_waittime) Poll485_Info.POLL_Start = Change_Dev; + break; + default: + Poll485_Info.POLL_Start = Change_Dev; + break; + } + + /*ǰǴģʽ£ʱعģʽ*/ + if(Poll485_Info.port_mode != Port_Normal_Mode) + { + if(SysTick_1s - Poll485_Info.mode_tick > Poll485_Info.mode_outtime) + { + Poll485_Info.mode_tick = SysTick_1s; + Poll485_Info.port_mode = Port_Normal_Mode; //ģʽ + } + } +} + +/******************************************************************************* +* Function Name : Poll485Port_Passthrough_Task +* Description : PollPort ѯ˿͸ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Poll485Port_Passthrough_Task(void) +{ + uint16_t data_len = 0; + + switch(Poll485_Info.pass_state) + { + case B_IDLE: //״̬ - жǷϱ· + /*մ*/ + if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr); + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len); + Udp_Internal_SeriaNet_Uploading(Polling_Port,Poll485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr); //ϱ + + g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr; + + } + + if(g_uart[UART_0].TX_Buffer_WriteAddr != g_uart[UART_0].TX_Buffer_ReadAddr) + { + /*ȡͻ - ·*/ + data_len = SRAM_Read_Word(g_uart[UART_0].TX_Buffer_ReadAddr); + Poll485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_0].TX_Buffer_ReadAddr + 2); //λS + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸ݳ + Poll485_Info.pass_tick = SysTick_1s; + + MCU485_SendSRAMData(Polling_Port,g_uart[UART_0].TX_Buffer_ReadAddr + 3,data_len); //· + + Poll485_Info.pass_state = Wait_Reply; + + g_uart[UART_0].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].TX_Buffer_ReadAddr > SRAM_UART0_SendBuffer_End_Addr) g_uart[UART_0].TX_Buffer_ReadAddr = SRAM_UART0_SendBuffer_Start_Addr; + } + + if(SysTick_1s - Poll485_Info.mode_tick > Poll485_Info.mode_outtime) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Poll485_Info Port_Normal_Mode mode_outtime"); + Poll485_Info.mode_tick = SysTick_1s; + Poll485_Info.port_mode = Port_Normal_Mode; //ģʽ + + if(Poll485_Info.baud != Polling_Baud) //ò + { + Poll485_Info.baud = Polling_Baud; + Poll485_Info.BaudRateCfg(Poll485_Info.baud); + } + } + break; + case Wait_Reply: //ȴظ - ظʱĻ - ϱ + /*մ*/ + if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len); + + Udp_Internal_SeriaNet_Uploading(Polling_Port,Act485_Info.baud,g_uart[UART_0].RX_Buffer_ReadAddr); + + Poll485_Info.pass_state = B_IDLE; //״̬ + + g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr; + } + + if(g_uart[UART_0].TX_Buffer_WriteAddr != g_uart[UART_0].TX_Buffer_ReadAddr) + { + /*ȡͻ - ·*/ + data_len = SRAM_Read_Word(g_uart[UART_0].TX_Buffer_ReadAddr); + Poll485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_0].TX_Buffer_ReadAddr + 2); //λS + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸ݳ + Poll485_Info.pass_tick = SysTick_1s; + + MCU485_SendSRAMData(Polling_Port,g_uart[UART_0].TX_Buffer_ReadAddr + 3,data_len); //· + + Poll485_Info.pass_state = Wait_Reply; + + g_uart[UART_0].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].TX_Buffer_ReadAddr > SRAM_UART0_SendBuffer_End_Addr) g_uart[UART_0].TX_Buffer_ReadAddr = SRAM_UART0_SendBuffer_Start_Addr; + } + + if(SysTick_1s - Poll485_Info.pass_tick > Poll485_Info.pass_outtime) + { + //ظʱ + Udp_Internal_SeriaNet_Response_Timeout(); + + Poll485_Info.pass_state = B_IDLE; //״̬ + } + break; + default: + Poll485_Info.pass_state = B_IDLE; //״̬ + break; + } +} + +/******************************************************************************* +* Function Name : BLV_PollPort_ModeTask +* Description : PollPort Poll˿ģʽ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_PollPort_ModeTask(void) +{ + uint16_t data_len = 0,rev = 0; + + if((g_pc_test.test_flag == 0x03) || (g_pc_test.test_flag == 0x13)) + { + if(g_uart[UART_0].RX_Buffer_WriteAddr != g_uart[UART_0].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_0].RX_Buffer_ReadAddr); + + rev = BLV_PC_TEST_TOUR_DATACheck(g_uart[UART_0].RX_Buffer_ReadAddr+2,data_len); + if(rev == 0x00) { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Poll Port Ѳ\r\n"); + g_pc_test.tour_succ++; //Ѳ + }else { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Ѳ!\r\n"); + } + g_uart[UART_0].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].RX_Buffer_ReadAddr > SRAM_UART0_RecvBuffer_End_Addr) g_uart[UART_0].RX_Buffer_ReadAddr = SRAM_UART0_RecvBuffer_Start_Addr; + + } + return; //Уͣ + } + + switch(Poll485_Info.port_mode) + { + case Port_Passthrough_mode: + Poll485Port_Passthrough_Task(); //͸ģʽ + break; + case Port_Normal_Mode: + case Port_Monitoring_mode: + BLV_PollPort_Task(); //ģʽ Լģʽ¼ģʽ + break; + } +} + +/******************************************************************************* +* Function Name : BLV_ActivePort_Task +* Description : ActivePort ˿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_ActivePort_Task(void) +{ + static uint32_t BLV_Act_Wait = 0; + uint16_t data_len_1 = 0; + + switch(Act485_Info.Act_Start) + { + case B_IDLE: //״̬ + /*մ*/ + if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr) + { + data_len_1 = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr); + + if((Act485_Info.n_processing_cf!=0x00000000) && (Act485_Info.n_processing_cf!=0xFFFFFFFF)) { + Act485_Info.Retry_Flag = ((fun2_prt)Act485_Info.n_processing_cf)(Act485_Info.Last_list_addr,g_uart[UART_2].RX_Buffer_ReadAddr + 2,data_len_1); + } + + if(Act485_Info.Retry_Flag == 0x00) { + + if(Act485_Info.Last_list_addr == Act485_Info.n_list_read_addr) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"A Reply SUCC"); + Act485_Info.Send_Flag = 0x00; + Act485_Info.Act_Start = B_Send; //ظɹȴ߿УлΪһ豸 + }else{ + //ǰݲǻظ лط豸Ϣ + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Not Dev Data"); + Act485_Info.Act_Start = Read_Dev; + } + + Act485_Info.process_num = 0; + + if(Act485_Info.port_mode == Port_Monitoring_mode) //ǰڼģʽ,ݷPC + { + Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //ϱ + } + + /*豸ϣնȡַƫ*/ + g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) { + g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr; + } + }else { + Act485_Info.process_num ++; + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Data parsing failed :%d" , Act485_Info.process_num); + Act485_Info.Act_Start = Change_Dev;//ǵǰ豸ݣһ + } + + if(Act485_Info.process_num >= Act485_Info.device_num) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"wipe cache partition:%d",Act485_Info.device_num); + Act485_Info.Act_Start = B_IDLE; + Act485_Info.process_num = 0; // + Act485_Info.Retry_Flag = 0; //ظ־ + + + if(Act485_Info.port_mode == Port_Monitoring_mode) //ǰڼģʽ,ݷPC + { + Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //ϱ + } + g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) { + g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr; + } + } + }else{ + if(SysTick_1ms - BLV_Act_Wait > Act485_Info.send_wait) + { + if((Act485_Info.Send_Flag == RS485OCCUPYTIME) && (Act485_Info.Last_list_addr == Act485_Info.n_list_read_addr)) + { + Act485_Info.Send_Flag = RS485OCCUPYNOTIME; //ݷ + Act485_Info.Act_Start = B_Send; //ع鷢״̬ͺڲжǷҪ + }else { + /* + 1ǰûݷ л豸 + 2ǰǷ + */ + Act485_Info.Act_Start = Change_Dev; + } + } + } + + break; + case B_Send: //ݷ״̬ + + Act485_Info.n_list_read_addr = Act485_Info.Last_list_addr; + + /*豸ͺ*/ + if((Act485_Info.n_polling_cf!=0x00000000) && (Act485_Info.n_polling_cf!=0xFFFFFFFF)) { + Act485_Info.Send_Flag = ((fun4_prt)Act485_Info.n_polling_cf)(Act485_Info.n_list_read_addr); + } + + Act485_Info.Retry_Flag = 0x00; + BLV_Act_Wait = SysTick_1ms; + + if(Act485_Info.Send_Flag == RS485OCCUPYTIME) + { + Act485_Info.send_wait = Act485_Info.n_dev_waittime; +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Send Data\r\n"); + } else{ +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Not Data\r\n"); + Act485_Info.send_wait = 5; //л豸ʱ + } + + Act485_Info.Act_Start = B_IDLE; + + break; + case Change_Dev: //л豸 + if(Act485_Info.list_read_addr != 0x00) + { + Act485_Info.Last_list_addr = Act485_Info.list_read_addr; + Act485_Info.list_read_addr = 0x00; +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - list_read_addr:%08X\r\n",Act485_Info.Last_list_addr); + }else{ + Act485_Info.Last_list_addr += SRAM_Device_List_Size; + } + + if((Act485_Info.Last_list_addr >= SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr)) || (Act485_Info.Last_list_addr >= SRAM_Device_List_End_Addr)) Act485_Info.Last_list_addr = SRAM_Read_DW(SRAM_POLL_Device_List_Addr); + + /*У ȡ豸*/ + if(Device_Data_Check(Act485_Info.Last_list_addr) == 0) + { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"BLV_ActivePort_Task - Read_Dev SUCC\r\n"); + + /*ȡ豸Ϣ*/ + Device_Public_Information_G dev_info; + SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Act485_Info.Last_list_addr); + + Act485_Info.n_polling_cf = dev_info.polling_cf; + Act485_Info.n_processing_cf = dev_info.processing_cf; + Act485_Info.n_dev_waittime = dev_info.wait_time; + Act485_Info.n_retry_num = dev_info.retry_num; + + if(Act485_Info.Retry_Flag == 0x00) Act485_Info.Act_Start = B_Send; + else Act485_Info.Act_Start = B_IDLE; + }else{ + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%s - Read_Dev Fail: %08X",__func__,Act485_Info.Last_list_addr); + } + break; + case Read_Dev: + + if(Device_Data_Check(Act485_Info.n_list_read_addr) == 0) + { + /*ȡ豸Ϣ*/ + Device_Public_Information_G dev_info; + SRAM_DMA_Read_Buff((uint8_t *)&dev_info,sizeof(Device_Public_Information_G),Act485_Info.n_list_read_addr); + + Act485_Info.n_polling_cf = dev_info.polling_cf; + Act485_Info.n_processing_cf = dev_info.processing_cf; + Act485_Info.n_dev_waittime = dev_info.wait_time; + Act485_Info.n_retry_num = dev_info.retry_num; + + Act485_Info.Last_list_addr = Act485_Info.n_list_read_addr; //һ豸ָλ + Act485_Info.Act_Start = B_IDLE; //ȴ + }else { + Act485_Info.Act_Start = Change_Dev; + } + break; + default: + Act485_Info.Act_Start = B_IDLE; + break; + + } + + /*ǰǴģʽ£ʱعģʽ*/ + if(Act485_Info.port_mode != Port_Normal_Mode) + { + if(SysTick_1s - Act485_Info.mode_tick > Act485_Info.mode_outtime) + { + Act485_Info.mode_tick = SysTick_1s; + Act485_Info.port_mode = Port_Normal_Mode; //ģʽ + } + } +} + +/******************************************************************************* +* Function Name : Act485Port_Passthrough_Task +* Description : ActivePort ˿͸ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Act485Port_Passthrough_Task(void) +{ + uint16_t data_len = 0; + switch(Act485_Info.pass_state) + { + case B_IDLE: //״̬ - жǷϱ· + /*մ*/ + if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr); + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d" , data_len); + Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); //ϱ + + g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr; + + } + + if(g_uart[UART_2].TX_Buffer_WriteAddr != g_uart[UART_2].TX_Buffer_ReadAddr) + { + /*ȡͻ - ·*/ + data_len = SRAM_Read_Word(g_uart[UART_2].TX_Buffer_ReadAddr); + Act485_Info.pass_outtime = SRAM_Read_Byte(g_uart[UART_2].TX_Buffer_ReadAddr + 2); //λS + if(data_len > Passthrough_DataLen_Max) data_len = Passthrough_DataLen_Max; //͸ݳ + Act485_Info.pass_tick = SysTick_1s; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d" , data_len); + MCU485_SendSRAMData(Active_Port,g_uart[UART_2].TX_Buffer_ReadAddr + 3,data_len); //· + + Act485_Info.pass_state = Wait_Reply; + + g_uart[UART_2].TX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].TX_Buffer_ReadAddr > SRAM_UART2_SendBuffer_End_Addr) g_uart[UART_2].TX_Buffer_ReadAddr = SRAM_UART2_SendBuffer_Start_Addr; + } + + if(SysTick_1s - Act485_Info.mode_tick > Act485_Info.mode_outtime) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Act485_Info Port_Normal_Mode mode_outtime"); + Act485_Info.mode_tick = SysTick_1s; + Act485_Info.port_mode = Port_Normal_Mode; //ģʽ + + if(Act485_Info.baud != Active_Baud) //ò + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Act485_Info.baud:%d",Act485_Info.baud); + Act485_Info.baud = Active_Baud; + Act485_Info.BaudRateCfg(Act485_Info.baud); + } + } + break; + case Wait_Reply: //ȴظ - ظʱĻ - ϱ + /*մ*/ + if(g_uart[UART_2].RX_Buffer_WriteAddr != g_uart[UART_2].RX_Buffer_ReadAddr) + { + data_len = SRAM_Read_Word(g_uart[UART_2].RX_Buffer_ReadAddr); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART2 data_len :%d ,RX_Buffer:" , data_len); + + + Udp_Internal_SeriaNet_Uploading(Active_Port,Act485_Info.baud,g_uart[UART_2].RX_Buffer_ReadAddr); + + Act485_Info.pass_state = B_IDLE; //״̬ + + g_uart[UART_2].RX_Buffer_ReadAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].RX_Buffer_ReadAddr > SRAM_UART2_RecvBuffer_End_Addr) g_uart[UART_2].RX_Buffer_ReadAddr = SRAM_UART2_RecvBuffer_Start_Addr; + + } + + if(SysTick_1s - Act485_Info.pass_tick > Act485_Info.pass_outtime) + { + //ظʱ + Udp_Internal_SeriaNet_Response_Timeout(); + + Act485_Info.pass_state = B_IDLE; //״̬ + } + break; + default: + Act485_Info.pass_state = B_IDLE; //״̬ + break; + } +} + +/******************************************************************************* +* Function Name : BLV_ActivePort_ModeTask +* Description : ActivePort Active˿ģʽ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_ActivePort_ModeTask(void) +{ + switch(Act485_Info.port_mode) + { + case Port_Passthrough_mode: + Act485Port_Passthrough_Task(); //͸ģʽ + break; + case Port_Normal_Mode: + case Port_Monitoring_mode: + + BLV_ActivePort_Task(); //ģʽ Լģʽ¼ģʽ + + break; + } +} + +/******************************************************************************* +* Function Name : BLV_Active_Set_List_Addr +* Description : ActivePort ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Active_Set_List_Addr(uint32_t addr) +{ + Act485_Info.list_read_addr = addr; + Act485_Info.Act_Start = Change_Dev; +} + +/******************************************************************************* +* Function Name : Find_Device_List_Information +* Description : 豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Find_Device_List_Information(uint8_t dev_type,uint8_t addr) +{ + uint32_t read_addr = SRAM_Device_List_Start_Addr; + uint32_t end_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr); + //Dbg_Println(DBG_OPT_DEVICE_STATUS,"Find Device:%08x",end_addr); + if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr; + + for(uint32_t i=SRAM_Device_List_Start_Addr;i= end_addr) + { + return 0x00; + } + } + + return 0x00; +} + +/******************************************************************************* +* Function Name : Find_AllDevice_List_Information +* Description : 豸ͨ豸 +* Input : +* dev_type - 豸 +* addr - 豸ĵַ +* Return : 豸ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Find_AllDevice_List_Information(uint8_t dev_type,uint8_t addr) +{ + uint32_t read_addr = SRAM_Device_List_Start_Addr; + uint32_t end_addr = SRAM_Read_DW(SRAM_NORMAL_Device_List_Addr); + if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr; + + for(uint32_t i=SRAM_Device_List_Start_Addr;i= end_addr) + { + return 0x00; + } + } + + return 0x00; +} + +/******************************************************************************* +* Function Name : Find_AllDevice_List_Information2 +* Description : 豸ͨ豸 +* Input : +* Port - 豸Ķ˿ +* dev_type - 豸 +* addr - 豸ĵַ +* Return : 豸ַ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t Find_AllDevice_List_Information2(uint8_t Port, uint8_t dev_type,uint8_t addr) +{ + uint16_t i = 0; + uint32_t read_addr = 0x00; + + switch(Port) + { + case Active_Port: + i = BUS485_Info.device_num + Poll485_Info.device_num; + break; + case Polling_Port: + i = BUS485_Info.device_num; + break; + case Bus_port: + i = 0; + break; + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"δ豸ʱҪ豸:%d±:%d", (BUS485_Info.device_num+Poll485_Info.device_num+Act485_Info.device_num), i); + + for(; i < (BUS485_Info.device_num+Poll485_Info.device_num+Act485_Info.device_num); i++) + { + read_addr = SRAM_Device_List_Start_Addr + i*SRAM_Device_List_Size; + if((SRAM_Read_Byte(read_addr + Dev_Type) == dev_type) && (SRAM_Read_Byte(read_addr + Dev_Addr) == addr)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҵǰ豸"); + +// if(Device_Data_Check(read_addr) == 0) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ豸Уͨ%04x", read_addr); + + return read_addr; + } + } + } + + return 0x00; //δҵ豸ؿָ +} + +/******************************************************************************* +* Function Name : Find_The_Number_Of_Device_In_The_List +* Description : ѯ豸 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Find_The_Number_Of_Device_In_The_List(void) +{ + uint32_t read_addr = SRAM_Device_List_Start_Addr; + uint32_t end_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); //豸ַ + uint8_t temp_num = 0; + uint32_t temp_len = 0; + + temp_len = end_addr - read_addr; + temp_num = (temp_len / SRAM_Device_List_Size) & 0xFF; + + return temp_num; +} + +/*ȡ豸ȫ״̬*/ +__attribute__((section(".non_0_wait"))) uint8_t Gets_the_state_of_all_devices(uint8_t *data_buff,uint8_t num) +{ + uint8_t dev_type = 0,dev_addr = 0,dev_online = 0; + uint32_t read_addr = SRAM_Device_List_Start_Addr; + uint32_t end_addr = SRAM_Read_DW(SRAM_ACTIVE_Device_List_Addr); + if((end_addr < SRAM_Device_List_Start_Addr) || (end_addr > SRAM_Device_List_End_Addr)) end_addr = SRAM_Device_List_End_Addr; + + for(uint8_t i=0;i= end_addr) + { + return 0x00; + } + } + + return 0x00; +} + +/******************************************************************************* + * @brief д豸״̬SRAM + * @param + * device_type 豸 + * device_addr 豸ַ + * fault_type + * fault_state ״̬ + * @retval None + * @attention һֹ 1ֽ485豸 1ֽ豸ַ 2ֽ豸·ֽǰ 1ֽڹ 1ֽڹ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Write_Device_Fault_State( + uint8_t device_type, + uint8_t device_addr, + uint8_t fault_type, + uint8_t fault_state) +{ + uint8_t data[6]; //ڱ豸 + uint32_t write_addr = 0x00,read_addr = 0x00; //豸״̬дַ + uint8_t len = 0; + + //ȡ豸 дַ + write_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); + read_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_READ_ADDR); + + //ȡַκһдֱַӸλ + if( (write_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) \ + || (read_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (read_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) ) + { + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + read_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); + SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_READ_ADDR); + SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR); + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s SRAM addr:%08X",__func__, write_addr); + + memset(data,0x00,6); //豸Ϣ0 + + data[0] = device_type; //豸 + data[1] = device_addr; //豸ַ + data[4] = fault_type; // + data[5] = fault_state; //״̬ + + if( (write_addr + 0x06) > SRAM_DEVICE_ONLINE_STATE_END_ADDR ) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep_1 %08X!!!",__func__,write_addr); + len = SRAM_DEVICE_ONLINE_STATE_END_ADDR - write_addr; + SRAM_DMA_Write_Buff(data,len,write_addr); + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + SRAM_DMA_Write_Buff(&data[len],(6-len),write_addr); + write_addr += (6-len); + }else { + SRAM_DMA_Write_Buff(data, 6, write_addr); //д豸Ϣ + write_addr += 0x06; //ַƫ + } + + if(write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s overstep:%08X",__func__,write_addr); + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + } + + SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); //豸״̬дַ + //Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Write Fault Data:%02X %02X %02X %02X %02X %02X\r\n",data[0],data[1],data[2],data[3],data[4],data[5]); +} + +/******************************************************************************* + * @brief д豸·״̬SRAM + * @param + * device_type 豸 + * device_addr 豸ַ + * fault_type + * fault_state ״̬ + * @retval None + * @attention һֹ 1ֽ485豸 1ֽ豸ַ 2ֽ豸·ֽǰ 1ֽڹ 1ֽڹ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Write_Device_Loop_Fault_State( + uint8_t device_type, + uint8_t device_addr, + uint8_t fault_type, + uint8_t fault_state, + uint16_t loop) +{ + uint8_t data[6]; //ڱ豸 + uint32_t write_addr = 0x00,read_addr = 0x00; //豸״̬дַ + uint8_t len = 0; + + //ȡ豸 дַ + write_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); + read_addr = SRAM_Read_DW(SRAM_DEVICE_ONLINE_STATE_READ_ADDR); + + //ȡַκһдֱַӸλ + if( (write_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) \ + || (read_addr < SRAM_DEVICE_ONLINE_STATE_START_ADDR) || (read_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) ) + { + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + read_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); + SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_READ_ADDR); + SRAM_Write_DW(read_addr,SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR); + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s SRAM addr:%08X",__func__, write_addr); + + memset(data,0x00,6); //豸Ϣ0 + + data[0] = device_type; //豸 + data[1] = device_addr; //豸ַ + data[2] = (loop & 0xFF); + data[3] = ((loop >> 8) & 0xFF); + data[4] = fault_type; // + data[5] = fault_state; //״̬ + + if( (write_addr + 0x06) > SRAM_DEVICE_ONLINE_STATE_END_ADDR ) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s overstep_1 %08X!!!",__func__,write_addr); + len = SRAM_DEVICE_ONLINE_STATE_END_ADDR - write_addr; + SRAM_DMA_Write_Buff(data,len,write_addr); + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + SRAM_DMA_Write_Buff(&data[len],(6-len),write_addr); + write_addr += (6-len); + }else { + SRAM_DMA_Write_Buff(data, 6, write_addr); //д豸Ϣ + write_addr += 0x06; //ַƫ + } + + if(write_addr > SRAM_DEVICE_ONLINE_STATE_END_ADDR) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s overstep:%08X",__func__,write_addr); + write_addr = SRAM_DEVICE_ONLINE_STATE_START_ADDR; + } + + SRAM_Write_DW(write_addr,SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR); //豸״̬дַ +} + +/******************************************************************************* +* Function Name : BLV_Communication_Record +* Description : BUSͨѶ¼ +* Input : + dev_record :ͨѶ¼ṹ + option :¼ѡ + 0x01:¼ͨѶ + 0x02:¼ͨѶ + state : + ѡΪ¼ͨѶʱòЧ + ѡΪ¼ͨѶʱòΪ0x00ͨѶʧܣ0x01ͨѶɹ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void BLV_Communication_Record( + BLV_COMM_RECORD_G *dev_record, + uint8_t option, + uint8_t state) +{ + switch(option) + { + case 0x01: + if(dev_record->num >= BLV_COMM_RecordNum*8) + { +// Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶ¼"); + dev_record->full_flag = 0x01; + dev_record->num = 0; + } + + dev_record->num++; + dev_record->continue_fail_num++; + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶ¼:%d",dev_record->num); + + dev_record->record[(dev_record->num-1)/8] &= ~((0x01 << ((dev_record->num-1)%8))); + //Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"ͨѶBUFF",dev_record->record,BLV_COMM_RecordNum); + break; + case 0x02: + if(state == 0x01) + { + //Dbg_Println(DBG_BIT_SYS_STATUS_bit,"ͨѶɹ:%d",dev_record->num); + dev_record->continue_fail_num = 0; + dev_record->record[(dev_record->num-1)/8] |= (0x01 << ((dev_record->num-1)%8)); + } + break; + } +} + + +/******************************************************************************* +* Function Name : Get_BLV_Communication_Succ_Rate +* Description : ȡͨѶʧ(ǰͳƵͨѶеʧ) +* Return ʧܰٷֱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t Get_BLV_Communication_Fail_Rate(BLV_COMM_RECORD_G *dev_record) +{ + uint8_t temp = 0; + uint16_t fail_num = 0,sum = 0,precent = 0; + + if(dev_record->full_flag == 0x01) sum = BLV_COMM_RecordNum*8; //ǰ¼ + else sum = dev_record->num; //ǰûм¼δ + + for(uint16_t i=0;irecord[i/8] >> (i%8)) & 0x01; + if(temp == 0x00) fail_num++; //ʧܴһ + } + + precent = (fail_num*100)/sum; + + return precent; +} + + + + + + + diff --git a/MCU_Driver/check_fun.c b/MCU_Driver/check_fun.c new file mode 100644 index 0000000..5f5153d --- /dev/null +++ b/MCU_Driver/check_fun.c @@ -0,0 +1,235 @@ +/* + * check_fun.c + * + * Created on: Nov 8, 2025 + * Author: cc + */ + +#include "includes.h" + +/******************************************************************************* +* Function Name : Log_CheckSum +* Description : УȡݴSRAMжȡ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Log_CheckSum(uint32_t addr,uint8_t len) +{ + uint8_t data_sum = 0; + for(uint8_t i = 0;i>= 1 ; + if( xdabit ) xda ^= xdapoly ; + } + } + aStr[alen] = (uint8_t)(xda & 0xFF) ; + aStr[alen+1] = (uint8_t)(xda>>8) ; +} + +/******************************************************************************* +* Function Name : NetCRC16_2 +* Description : CRCУ - ȡSRAM +* Input : + aStr : ҪУ׵ַ + len : ݵij -- FlashеУһ512Byte +* Return : ݵУֵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t NetCRC16_2(uint8_t *aStr ,uint16_t len) +{ + uint16_t xda , xdapoly ; + uint16_t i,j, xdabit ; + xda = 0xFFFF ; + xdapoly = 0xA001 ; // (X**16 + X**15 + X**2 + 1) + for(i=0;i>= 1 ; + if( xdabit ) xda ^= xdapoly ; + } + } + return xda; +} + +/******************************************************************************* +* Function Name : NetCRC16_Data +* Description : CRCУ - CRCڼ +* Input : + aStr : ҪУ׵ַ + len : ݵij -- FlashеУһ512Byte + crc_id CRCе±λã͵ַǰ +* Return : ݵУֵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t NetCRC16_Data(uint8_t *aStr ,uint16_t len,uint16_t crc_id) +{ + uint16_t xda , xdapoly ; + uint16_t i,j, xdabit ; + xda = 0xFFFF ; + xdapoly = 0xA001 ; // (X**16 + X**15 + X**2 + 1) + for(i=0;i>= 1 ; + if( xdabit ) xda ^= xdapoly ; + } + } + + return xda; +} + +/******************************************************************************* +* Function Name : DoubleData_CheckSum +* Description : Уȡ +* Data1 ݰ1 +* Data1Len ݰ1ij +* Data2 ݰ2 +* Data2Len ݰ2ij +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t DoubleData_CheckSum(uint8_t *Data1, uint16_t Data1Len, uint8_t *Data2, uint16_t Data2Len) +{ + uint8_t data_sum = 0; + uint16_t i; + + for(i = 0; i < Data1Len;i++) + { + data_sum += Data1[i]; + } + + for(i = 0; i < Data2Len; i++) + { + data_sum += Data2[i]; + } + + return ~data_sum; +} + +/******************************************************************************* +* Function Name : SOR_CRC +* Description : У +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t SOR_CRC(uint8_t *Data, uint8_t DataLen) +{ + uint8_t i; + uint8_t sor_data = 0; + + for(i = 0; i < DataLen; i++)//iΪ0 Ҳ1 + { + sor_data = sor_data+Data[i]; + } + return sor_data; +} + +/******************************************************************************* +* Function Name : DevAction_Data_Check +* Description : 豸У +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t DeAction_Data_Check(uint32_t sram_addr) +{ + uint16_t data_len = SRAM_Read_Word(sram_addr + sizeof(Dev_Action_Core) + sizeof(Dev_Action_Input) + sizeof(Dev_Action_Cond) + sizeof(Dev_Action_State) + 1); + uint8_t data_sum = 0; + uint8_t check_temp_buff[SRAM_DevAction_List_Size] = {0}; + + if(data_len > SRAM_DevAction_List_Size) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰУ1ǰַ:%08X 洢ijȣ%04X",sram_addr, data_len); + return 1; + } + memset(check_temp_buff,0,SRAM_DevAction_List_Size); + + SRAM_DMA_Read_Buff(check_temp_buff,data_len,sram_addr); + + for(uint16_t i = 0;i SRAM_DevAction_List_Size) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰУ2ǰַ:%08X 洢ijȣ%04X",addr, len); + return 1; + } + + memset(check_temp_buff,0,SRAM_DevAction_List_Size); + SRAM_DMA_Read_Buff(check_temp_buff,len,addr); + + for(uint16_t i = 0;i +#include +#include + +volatile uint32_t SysTick_100us = 0; +volatile uint32_t SysTick_1ms = 0; +volatile uint32_t SysTick_1s = 0; + +__attribute__((section(".non_0_wait"))) void Systick_Init(void) +{ + /*жȼ*/ + NVIC_SetPriority(SysTick_IRQn, 0x00); + NVIC_EnableIRQ(SysTick_IRQn); + + /*öʱ*/ + SysTick->CTLR= 0; + SysTick->SR = 0; + SysTick->CNT = 0; + SysTick->CMP = SystemCoreClock/10000;//10001000HZ(Ǿ1msһж) + SysTick->CTLR= 0xf; +} + +void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void SysTick_Handler(void) +{ + static uint8_t NUM = 0; + static uint16_t NUM_s = 0; + + SysTick->SR = 0; //жϱ־ + + SysTick_100us++; + NUM++; + + if(NUM >= 10){ + NUM = 0; + + SysTick_1ms++; + NUM_s++; + + if(NUM_s >= 1000){ + NUM_s = 0x00; + SysTick_1s++; + } + } +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +__attribute__((section(".non_0_wait"))) void Delay_Us(uint32_t n) +{ + for(uint32_t i=0;i _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + + +uint32_t SysTick_Now = 0, SysTick_Last = 0, SysTick_Diff = 0; +char Dbg_Buffer[100]; + +uint32_t Dbg_Switch = (DBG_OPT_ActCond_STATUS << DBG_BIT_ActCond_STATUS_bit) + \ + (DBG_OPT_MQTT_STATUS << DBG_BIT_MQTT_STATUS_bit) + \ + (DBG_OPT_Debug_STATUS << DBG_BIT_Debug_STATUS_bit) + \ + (DBG_OPT_LOGIC_STATUS << DBG_BIT_LOGIC_STATUS_bit) + \ + (DBG_OPT_DEVICE_STATUS << DBG_BIT_DEVICE_STATUS_bit) + \ + (DBG_OPT_NET_STATUS << DBG_BIT_NET_STATUS_bit) + \ + (DBG_OPT_SYS_STATUS << DBG_BIT_SYS_STATUS_bit); + +//÷ʽٴռ䣬 +void __putchar__ (char ch) +{ + +#if (DEBUG) == DEBUG_UART0 + while ((R8_UART0_LSR & RB_LSR_TX_FIFO_EMP) == 0); + R8_UART0_THR = ch; +#elif (DEBUG) == DEBUG_UART1 + while ((R8_UART1_LSR & RB_LSR_TX_FIFO_EMP) == 0); + R8_UART1_THR = ch; +#elif (DEBUG) == DEBUG_UART2 + while ((R8_UART2_LSR & RB_LSR_TX_FIFO_EMP) == 0); + R8_UART2_THR = ch; +#elif (DEBUG) == DEBUG_UART3 + while ((R8_UART3_LSR & RB_LSR_TX_FIFO_EMP) == 0); + R8_UART3_THR = ch; +#endif + +} +/******************************************************************************* +* Function Name : Dbg_NoTick_Print +* Description : DEBUGϢ - ʱӡ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Dbg_NoTick_Print(int DbgOptBit ,const char *fmt, ...) +{ + char ch; + va_list ap; + + if (DBG_LOG_EN && (Dbg_Switch & (1 << DbgOptBit ))) + { + va_start(ap, fmt); + while (*fmt) { + if (*fmt != '%') { + __putchar__(*fmt++); + continue; + } + switch (*++fmt) { + case 's': + { + char *str = va_arg(ap, char *); + printf("%s",str); + } + break; + case 'd': + { + int num = va_arg(ap, int); + printf("%d", num); + } + break; + + case 'x': + case 'X': + { + int num = va_arg(ap, unsigned int); + printf("%x", num); + } + break; + // Add other specifiers here... + case 'c': + case 'C': + ch = (unsigned char)va_arg(ap, int); + printf("%c", ch); + break; + default: + __putchar__(*fmt); + break; + } + fmt++; + } + va_end(ap); + printf("\r\n"); + } +} + +__attribute__((section(".non_0_wait"))) void Dbg_Print(int DbgOptBit ,const char *fmt, ...) +{ + char ch; + va_list ap; + if (DBG_LOG_EN && (Dbg_Switch & (1 << DbgOptBit ))) + { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //һδӡʱ + SysTick_Last = SysTick_Now; + + printf("%8d [%6d]: ",SysTick_Now,SysTick_Diff); + + va_start(ap, fmt); + while (*fmt) { + if (*fmt != '%') { + __putchar__(*fmt++); + continue; + } + switch (*++fmt) { + case 's': + { + char *str = va_arg(ap, char *); + printf("%s",str); + } + break; + case 'd': + { + int num = va_arg(ap, int); + printf("%d", num); + } + break; + + case 'x': + case 'X': + { + int num = va_arg(ap, unsigned int); + printf("%x", num); + } + break; + // Add other specifiers here... + case 'c': + case 'C': + ch = (unsigned char)va_arg(ap, int); + printf("%c", ch); + break; + default: + __putchar__(*fmt); + break; + } + fmt++; + } + va_end(ap); + } +} + +__attribute__((section(".non_0_wait"))) void Dbg_Println(int DbgOptBit ,const char *fmt, ...) +{ + char ch; + va_list ap; + if (DBG_LOG_EN && (Dbg_Switch & (1 << DbgOptBit ))) + { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //һδӡʱ + SysTick_Last = SysTick_Now; + + printf("%8d [%6d]: ",SysTick_Now,SysTick_Diff); + + va_start(ap, fmt); + while (*fmt) { + if (*fmt != '%') { + __putchar__(*fmt++); + continue; + } + switch (*++fmt) { + case 's': + { + char *str = va_arg(ap, char *); + printf("%s",str); + } + break; + case 'd': + { + int num = va_arg(ap, int); + printf("%d", num); + } + break; + + case 'x': + case 'X': + { + int num = va_arg(ap, unsigned int); + printf("%x", num); + } + break; + // Add other specifiers here... + case 'c': + case 'C': + ch = (unsigned char)va_arg(ap, int); + printf("%c", ch); + break; + default: + __putchar__(*fmt); + break; + } + fmt++; + } + va_end(ap); + printf("\r\n"); + } +} + +__attribute__((section(".non_0_wait"))) void Dbg_Print_Buff(int DbgOptBit ,const char *cmd ,uint8_t *buff,uint32_t len) +{ + if (DBG_LOG_EN && (Dbg_Switch & (1 << DbgOptBit ))) + { + SysTick_Now = SysTick_1ms; + SysTick_Diff = SysTick_Now - SysTick_Last; //һδӡʱ + SysTick_Last = SysTick_Now; + + DBG_Printf("%8d [%6d]: %s",SysTick_Now,SysTick_Diff,cmd); + for(uint32_t i=0;i + + +typedef struct +{ + uint8_t lock_status; //Ȩ״̬ + uint8_t last_status; + uint32_t expires_time; //Ȩʱ +}BLV_AUTHORIZE; + +void BLV_Set_Authorize_Status(uint32_t Expires_time,uint8_t lock); +void BLV_Authorize_Processing(uint32_t utc_time); +void Set_Authorize_Lock_Status(uint8_t state); +uint8_t Get_Authorize_Lock_Status(void); +uint32_t Get_Authorize_UnixTime(void); + +#endif /* MCU_DRIVER_INC_BLV_AUTHORIZE_H_ */ diff --git a/MCU_Driver/inc/blv_dev_action.h b/MCU_Driver/inc/blv_dev_action.h new file mode 100644 index 0000000..de7393b --- /dev/null +++ b/MCU_Driver/inc/blv_dev_action.h @@ -0,0 +1,304 @@ +/* + * blv_dev_action.h + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_BLV_DEV_ACTION_H_ +#define MCU_DRIVER_INC_BLV_DEV_ACTION_H_ + +#include +#include "ch564.h" + +#define DevActionNameLenMax 0x20 //豸 +#define DevCtrlNumMax 50 //չ豸 - ӵ50 + +#define CtrlValid 0x01 //Ч +#define CtrlInvalid 0x00 //Ч + +#define CondIsPass 0x01 //жϳ +#define CondIsNotPass 0x00 //жϲ + +#define DEV_STATE_OPEN 0x01 //豸״̬Ϊ +#define DEV_STATE_CLOSE 0x02 //豸״̬Ϊ + +#define SCENE_MODE_CTRL 0x01 //ģʽ +#define LIGHT_MODE_CTRL 0x02 //ƹģʽ + +#define NOR_MODE_CTRL 0x01 //ͨģʽ +#define SLEEP_MODE_CTRL 0x02 //˯ģʽ + +#define DEV_CTRLWAY_INVALID 0x00 //ƷʽЧ +#define DEV_CTRLWAY_OPEN 0x01 //ƷʽΪ +#define DEV_CTRLWAY_CLOSE 0x02 //ƷʽΪ +#define DEV_CTRLWAY_RELATESCENE 0x03 //ƷʽΪӦ +#define DEV_CTRLWAY_STOP 0x06 //ƷʽΪͣ + +#define Season_Spring 0x01 // +#define Season_Summer 0x02 //ļ +#define Season_Winter 0x03 // +#define Season_Autumn 0x00 //＾ + +#define ACTION_SCENE_ONE 0x01 //ɹرգִӦ +#define ACTION_SCENE_TWO 0x02 //ɹرգִӦ +#define ACTION_SCENE_SLEEP 0x04 //˯ģʽ ȫز㿪һء +#define ACTION_SCENE_MAINSWITCH 0x05 //ܿأһָʾƾͿеƹأָʾƲŹ +#define ACTION_SCENE_HELPSLEEP 0x06 //ģʽ ȫز㿪һء +#define ACTION_SCENE_MULTI 0x0B // +#define ACTION_SCENE_Rotary 0x0C //ť +#define ACTION_SCENE_SLEEP_UNRELATED 0x0E //˯޹صijᴥҹ + +#define NightModeStart 0x01 //ҹģʽ +#define NightModeOpen 0x02 //ҹ +#define NightModeClose 0x00 //رҹ + +#define DevCtrlLen 0x06 //豸Ƴȹ̶6ֽ +#define DevCtrlDlyLen 0x08 //豸Ƴȴʱ̶8ֽ ҪԼ豸ʱڵ +#define DevCtrlDlyLenAddr 0x10 //豸Ƴȴ豸̶ַ16ֽ Ҫڲʹ + +typedef struct +{ + uint16_t ActionNo; // + char DevActionName[DevActionNameLenMax]; //ǰƣ32ֽ жƣ÷ָ +}Dev_Action_Core; //Ϣ һ34ֽ + +typedef struct +{ + uint8_t DevType; //豸 + uint8_t DevAddr; //豸ַ + uint16_t inAddr; //ַ + uint16_t inType; // 豸ͣʶ +}Dev_Action_Input; // һ6ֽ + +typedef struct +{ + uint64_t DevActionOutFlag:1; //ʹ + uint64_t RoomState:3; //̬ 0ж 1 2˷ 3 4շ + uint64_t EleCtrlFlag:1; //ȡ 0ж 1Ҫȡ + uint64_t EleState:3; //ȡ״̬ 0ж 1 2 + uint64_t DndState:3; //״̬ 0ж 1 2 + uint64_t CleanState:3; //״̬ 0ж 1 2 + uint64_t CallState:3; //״̬ 0ж 1 2 + uint64_t WashState:3; //ϴ״̬ 0ж 1 2 + uint64_t CheckOutState:3; //˷״̬ 0ж 1 2 + uint64_t WaitState:3; //Ժ״̬ 0ж 1 2 + uint64_t SosState:3; //SOS״̬ 0ж 1 2 + uint64_t RentState:3; //ԤԼ״̬ 0ж 1 2 + uint64_t LockState:3; //״̬ 0ж 1 2 + uint64_t LuggageState:3; //״̬ 0ж 1 2 + uint64_t StrongState:3; //״̬ 0ж 1 2 + uint64_t DoorState:3; //Ŵ״̬ 0ж 1 2 + uint64_t WarningState:3; //ʾ״̬ 0ж 1 2 + uint64_t BacklightState:3; //״̬ 0ж 1 2 + uint64_t SeasonState:3; // 0ж 1 2 3 4 ȫ1 2 3 0 + uint64_t TimeState:3; //ʱ 1ȫ 2 3ҹ + uint64_t NeightFlag:1; //ҹй Ϊ1ҹй Ϊ0ҹ޹ ڱȫΪ1ҹܴ Ϊ0ҹܲ + uint64_t NeightState:2; //ҹ״̬ ڱȫ 1ҹ 2ҹ 0˳ҹ + uint64_t RcuLockState:3; //RCU 0ж 1 2 ڱȫ 1 0 + uint64_t Reserve1:2; //2λ + +}Dev_Action_U64Cond; //ijִ һ9ֽ + +typedef struct{ + Dev_Action_U64Cond DevActionU64Cond; //64λ + uint8_t SceneExcute; //ִзʽ ɹر ɹر +}Dev_Action_Cond; //ijִ һ9ֽ + +typedef struct +{ + uint8_t DelayCont; //ʱʱ Ķ̬豸ʱִ + uint8_t DelayWeight; //ʱλ +}Dev_Dly_Value; //豸ʱϢ + +typedef struct +{ + /*豸Ϣʼ*/ + uint8_t DevType; //豸 + uint8_t DevAddr; //豸ַ + uint16_t DevOutputLoop; //豸ַ + uint16_t DevCtrlState; //豸״̬ + Dev_Dly_Value DevDlyValue; //豸ʱϢ + /*豸Ϣ*/ +}Dev_Action_OutCfg; //豸 8ֽ + +#define DEVACTIONOUTCFGLEN sizeof(Dev_Action_OutCfg) //̶8ֽ + +typedef struct +{ + Dev_Action_OutCfg DevActionOutCfg; // 8ֽ + uint32_t DevActionOutAddr; //ÿ豸ĵַ + uint32_t DevDlyAddr; //ʱ豸ĵַ +}Dev_Action_Output; //豸 16ֽ + +typedef struct +{ + uint8_t SceneState; //ͨ״̬ Ŀǰ״̬߹ ΪƵı־ ˯߽ڵжݱȽ⣬ȫΪһΪΪ + uint8_t SceneStateLast; //ͨ״̬һ״̬ ָʾƿ + uint8_t SceneReuseFlag; //ڵ·ȫһҶãñ־һ Ϊ1ɨ趯ʱж + uint8_t MultiSetFlag; //±ñ 2024-05-23 + uint8_t MultiNumber; //ǰ± 2024-05-23 + uint8_t MultiValidNo; //ЧĶ 2024-05-23 + uint8_t SceneTypeFlag; //жϱ־ 1Ҫжϳ״̬ 0жϳ״̬ ɹرգ˯ߣܿأߣӦҪж 1ʾس 2ʾس 0ʾδ峡 Ƶƹһ࣬һ·Ƽǵأ·ƼǶءΪأƷϢյֶ + uint32_t DevAddrIn; //豸 豸ַ +}Dev_Action_State; //豸״̬ һ11ֽ + +typedef struct CFG_Action_Add +{ + Dev_Action_Core DevActionCore; //豸Ϣ һ34ֽ + Dev_Action_Input DevActionInput; //豸 һ6ֽ + Dev_Action_Cond DevActionCond; //豸 һ9ֽ + +/* ṹ峤Ƚ ݿܳ49ֽ */ + + Dev_Action_State DevActionState; //״̬ һ11ֽ + uint8_t CheckVal; //ǰ豸У 1ֽ + uint16_t data_len; //豸 2ֽ + uint8_t DevCtrlNum; //豸 1ֽ + Dev_Action_Output DevActionOutput[DevCtrlNumMax]; //豸 16N ʵ28 +}DEV_ACTION_INFO; //豸ýṹ 豸 ܳ49+11+4+448 = 512ֽ + +typedef struct{ + uint16_t DevActionNum; //豸 Χ0~(DevActionNumMax-1) + uint16_t DevActioni; //ڱжȫֲ Χ0~(DevActionNumMax-1) + uint16_t DevDlyNum; //ʱ豸 + uint16_t DevDlyi; //ڱеʱ豸 + + uint16_t BlwMapDevNum; //ӳ豸 2024-08-28 uint8_t uint16_t + uint8_t BlwMapDevi; //ڱӳ豸 + + uint8_t DevNum; //豸 + uint8_t DevBusNum; //Bus豸 + uint8_t DevPollNum; //ѯ豸 + uint8_t DevActiveNum; //豸 + uint8_t DevNorNum; //ͨ豸 + + uint8_t Devi; //ڱ豸 + +/*ʱʼ*/ + uint8_t TimeGetFlag; //ʱȡ־ ÿõʱ䣬ͼ ӷȡʱ +/*ʱ*/ + + Dev_Action_U64Cond DevActionU64Cond; //64λο + uint16_t SleepActionNo; //˯߳ Ϊ0Ч + uint32_t DevLockAddr; //΢豸ַ + uint8_t Lock485Addr; //΢485ַ + uint32_t pc_addr; //豸ַ + + uint16_t CheckMapDevNum; //2023-11-27 Ѳ + uint8_t CheckTypeNum; //Ѳ豸 + uint8_t CheckMapList[4]; //Ѳ豸б + + uint8_t OffLineDevType; //豸 2023-10-08 + uint8_t OffLineDevAddr; //豸ַ 2023-10-08 + uint8_t InputType; //豸 2023-10-08 + uint8_t InputAddr; //豸ַ 2023-10-08 + uint8_t InputLoop; //豸· 2023-10-08 + + uint8_t People_Flag; //˱ 2024-03-01 + uint8_t ServerCtrl; // + uint8_t CardInFlag; //סʱ˯߱ 2024-04-29 + + uint16_t DimGlobalValue; //ȫ + + uint8_t TimeSyncFlag; //ʱͬ + uint8_t DayStart; //쿪ʼʱ + uint8_t DayEnd; //ʱ + + uint8_t VC_ConNToSGruop; //޿ȡ + uint8_t VC_ConNToSSubset; //޿ȡ + + uint8_t VC_ConSToNGruop; //޿ȡ + uint8_t VC_ConSToNSubset; //޿ȡ + + uint8_t VC_PortNum; //޿ȡ˿ + + uint16_t CCTValue; //ɫֵ + uint8_t Dim_Lower_limit; // + uint8_t Dim_Upper_limit; // + + uint8_t Service_16; //16״̬ + + uint8_t sram_save_flag; //ⲿSRAM־λ + + uint8_t Last_EleState; //һȡ״̬ + uint8_t SleepMode_State; + uint8_t Last_SleepMode_State; + uint8_t SleepLight_State; + uint8_t Last_SleepLight_State; + uint8_t Person_Detected; //ȡе ˻״̬ 忨ȡ硢״ӦҲ㣩 + uint8_t Last_Person_Detected; + + uint16_t Last_DimGlobalValue; //ϴαĵֵ + uint16_t Last_CCTValue; //ϴαĵɫֵ + + uint8_t CardState; //忨״̬ + uint8_t Last_CardState; + + uint8_t Rs485CardType; //忨ݣͣ û -> "޿++"¼ + uint8_t Last_Rs485CardType; + uint8_t Last_NeightState; + +}BLV_DevAction_Manage_G; + +#define DevDlyStructLen sizeof(Struct_Dev_Dly) //ʱṹ峤 +#define DevDlyNumMax ((SRAM_DevDly_List_End_Addr - SRAM_DevDly_List_Start_Addr) / DevDlyStructLen) //ʱ + +#define DELAY_TIME_MS 0x01 // +#define DELAY_TIME_S 0x02 // +#define DELAY_TIME_MIN 0x03 // +#define DELAY_TIME_HOUR 0x04 //Сʱ + +typedef struct +{ + uint8_t DevType; //豸 0Ϊ + uint16_t DevOutputLoop; //豸· Ϊڵʱ˱û + uint32_t DevDlyAddr; //豸ʱڵ ڵܴ豸Χ߶Χ +}Struct_Dev_Dly_Core; //ʱ豸ؼϢ 7ֽ + +typedef struct +{ + uint8_t DlyExcuteFlag; //ʱִб־ʱ־һ + uint8_t DlyBlinkFlag; //ʱ˸־ʱ˸־һʱʱִб־һ ҲǶ־ 0Ϊ 1Ϊ ʱ ֱִ豸 + uint16_t DevOutputType; //豸ͣ豸ִзʽִ + uint32_t DlyExcuteTime; //ʱִʱ䣬ʱʱ䱻ֵ + Struct_Dev_Dly_Core DevDlyCore; //ʱ ؼϢ + + Dev_Dly_Value DlyBlinkTime; //˸Ƶ 0201 Ϊ1Sл 0202 Ϊ2Sл Ϊ ΪǰҪִеչ豸± +}Struct_Dev_Dly; //豸ʱṹ壬дʱչ豸 ̶16ֽ + + + + + +typedef struct{ + uint8_t Addr; + uint32_t ExpandReadFlag; + uint16_t ExpandReadState[32]; +}EXPAND_TYPE_G; //̵Ⱥ״̬ṹ + +typedef struct{ + uint8_t Addr; + uint32_t DimmReadFlag; + uint16_t DimmReadState[32]; +}DIMM_TYPE_G; //Ⱥ״̬ṹ + + + + + + + + + + +extern BLV_DevAction_Manage_G DevActionGlobal; + +uint32_t DevAction_No_Get(uint16_t DevActionNo); +uint32_t Add_DevDly_To_List(uint8_t DevType, uint32_t DevDlyAddr, uint16_t DevOutputLoop); +uint32_t DevDlyAddr_Get(uint32_t DevDlyAddr, uint16_t DevOutputLoop); +void DevAction_No_Ctrl(uint16_t DevActionNo, uint8_t Mode, uint16_t CtrlState); +uint8_t DevActionCtrl(uint8_t *p, uint8_t DataLen); + + +#endif /* MCU_DRIVER_INC_BLV_DEV_ACTION_H_ */ diff --git a/MCU_Driver/inc/blv_netcomm_function.h b/MCU_Driver/inc/blv_netcomm_function.h new file mode 100644 index 0000000..2355938 --- /dev/null +++ b/MCU_Driver/inc/blv_netcomm_function.h @@ -0,0 +1,93 @@ +/* + * BLV_NETCOMM_Function.h + * + * Created on: Nov 3, 2025 + * Author: cc + */ + +#ifndef _BLV_NETCOMM_FUNCTION_H_ +#define _BLV_NETCOMM_FUNCTION_H_ + +#define FRAME_HEAD_OFFSET 0 //ͷλ 0 +#define FRAME_LEN_OFFSET 2 //֡λ 2 +#define SYSTEM_ID_OFFSET 4 //ϵͳIDλ 4 +#define CMD_OFFSET 8 //λ 8 +#define FRAME_NO_OFFSET 9 //֡λ 9 +#define FLOOR_NUM_OFFSET 11 //¥λ 11 +#define BLV_UDP_HEAD_LEN 15 //Эͷ +#define BLV_UDP_PACK_LEN 17 // + +#define SeriaNet_Cmd_Send_Len 19 //ͷ15Byte+ݣ2Byte+CRC2Byte + +#define Search_Cmd 0x01 // +#define Heart_Cmd 0x02 // +#define In_QueryTime_Cmd 0x08 //ʱ +#define In_RoomState_Cmd 0x0E //״̬ϱ 2025-09-25 ȡ +#define In_DevCtr_Cmd 0x0F //豸̵ƺ͵ +#define In_SingleAirCtrl_Cmd 0x13 //¿ +#define In_Sys_Key_Cmd 0x24 //һϵ + +#define In_SetSecretKey_Cmd 0x28 //MQTTԿ +#define In_ReadSecretKey_Cmd 0x29 //ȡMQTTԿ +#define In_ReadRegister_Cmd 0x30 //ȡӳĴ 2021-07-13 +#define In_WriteRegister_Cmd 0x31 //ӳĴ 2021-07-13 +#define In_Get_RoomRent_Cmd 0x32 //ȡ̬Ϣ 2025-09-09 +#define In_Reboot_Reason_Cmd 0x33 //ϱԭ 2025-09-25 +#define In_PeriodicReport_Cmd 0x34 //ϱ 2025-09-25 +#define In_Power_Change_Cmd 0x35 //ȡ״̬ϱ 2025-09-25 +#define In_DevState_Cmd 0x36 //豸״̬ϱ 2025-09-25 + +#define In_SeriaNet_Cmd 0x70 //͸· +#define In_SeriaNetReported_Cmd 0x71 //͸ϱ + +#define In_Read_MCUSystem_Cmd 0xB1 //ȡϵͳϢ +#define In_BLVIAP_Cmd 0xB2 //BLV_CxAϵ̣ͨļִеBLV_Cxϵе +#define In_BLVIAPCheck_Cmd 0xB3 //BLV_CxУ +#define In_BLVIAPJump_Cmd 0xB4 //BLV_Cxת +#define In_BLVIAPLogic_Cmd 0xB5 //BLV_Cx߼Aϵ̣߼ͨ·BLV_Cxϵе߼ļ +#define In_BLVIAPPlan_Cmd 0xB6 //BLV_Cxƶ״̬ϱ +#define In_BLVPCTest_Cmd 0xD1 //BLV-C1 PC豸״̬ 2021-07-13 +#define In_BLVConfig_Cmd 0xD2 //BLV-C1Ϣ· 2025-10-09 ȡʹ +#define In_BLVPCTestDevice_Cmd 0xD3 //BLV-C1 PC豸 2021-10-26 +#define In_BLVFlashInfoWrite_CMD 0xD4 //BLV-C1 Flashд 2021-12-01 +#define In_BLVFlashInfoRead_CMD 0xD5 //BLV-C1 Flashд 2021-12-01 +#define In_BLVQueryTFTPIP_CMD 0xD6 //ӷTFTPIP +#define In_BLVRpDomainCtrl_Cmd 0xD7 //ϱ״̬ +#define In_BLVQueryCommonState_Cmd 0xD8 //ѯʹ״̬ + +#define In_BLVTFTPDomainName_Cmd 0xD9 //·RCU-TFTP +#define In_BLVTFTPDataRead_Cmd 0xDA //TFTPϢȡ +#define In_BLVDayNightTimeSet_Cmd 0xDB //ʱ䷶Χ + + + +#define UDP_ActSend_PowerChange_Flag 0x01 //UDPϱ - ȡ״̬仯 ־λ +#define UDP_ActSend_DevState_Flag 0x02 //UDPϱ - 豸״̬仯 ־λ +#define UDP_ActSend_Periodic_Flag 0x04 //UDPϱ - ϱ ־λ +#define UDP_ActSend_Reboot_Flag 0x08 //UDPϱ - RCUԭ ־λ +#define UDP_ActSend_RoomState_Flag 0x10 //UDPϱ - ȡ̬Ϣ ־λ +#define UDP_ActSend_TimeSync_Flag 0x20 //UDPϱ - ʱͬ ־λ +#define UDP_ActSend_Heart_Flag 0x40 //UDPϱ - ־λ + +#define USER_NET_Register_Timeout 30 //עͳʱ,λS +#define USER_NET_Send_Timeout 20 //ݵȴظʱ,λS +#define USER_NET_Register_Times 10 //עʹ +#define USER_NET_Send_Times 10 //ط +#define RCU_SoftwareVer 20 //RCU̼汾 +#define RCU_ConfigVer 3 //RCUð汾 + + + +extern uint8_t Global_Large_Buff[1100]; + +void Udp_Addtion_Roomstate(uint8_t type,uint8_t addr,uint16_t loop,uint16_t start); + +uint8_t Udp_Internal_PC_Testing_Reported(uint8_t *reply_data,uint16_t reply_len,uint8_t *ip,uint16_t port); +uint8_t Udp_Internal_BLVPCTestDevice_Process(uint8_t* data, uint16_t DataLen, uint8_t *ip,uint16_t port); + +uint8_t Udp_Internal_SeriaNet_Process(uint8_t* data, uint16_t DataLen, uint8_t *ip,uint16_t port); +uint8_t Udp_Internal_SeriaNet_Uploading(uint8_t port,uint32_t baud,uint32_t data_addr); +uint8_t Udp_Internal_SeriaNet_Uploading2(uint8_t port,uint32_t baud,uint8_t* data, uint16_t DataLen); +uint8_t Udp_Internal_SeriaNet_Response_Timeout(void); + +#endif /* MCU_DRIVER_INC_BLV_NETCOMM_FUNCTION_H_ */ diff --git a/MCU_Driver/inc/blv_rs485_protocol.h b/MCU_Driver/inc/blv_rs485_protocol.h new file mode 100644 index 0000000..985ffb8 --- /dev/null +++ b/MCU_Driver/inc/blv_rs485_protocol.h @@ -0,0 +1,355 @@ +/* + * blv_rs485_protocol.h + * + * Created on: Nov 10, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_BLV_RS485_PROTOCOL_H_ +#define MCU_DRIVER_INC_BLV_RS485_PROTOCOL_H_ + +#include + +#define Polling_Port 0x01 //ѯ˿ +#define Active_Port 0x02 //˿ +#define Bus_port 0x03 //BUS˿ + +#define Active_Baud 9600 //˿Ĭϲ +#define Polling_Baud 9600 //ѯ˿Ĭϲ +#define Bus_Baud 115200 //BUS˿Ĭϲ + +#define RS485OCCUPYTIME 0x01 //485ͺռʱ +#define RS485OCCUPYNOTIME 0x00 //485ͺռʱ + +/*豸Ϣ洢ṹ*/ +typedef enum{ + Dev_Type = 0x00, //豸 - 1Byte + Dev_Addr, //豸ַ - 1Byte + Dev_port, //豸˿ - 1Byte + Dev_baud, //豸 - 4Byte + Dev_baud_8, + Dev_baud_16, + Dev_baud_24, + Dev_Check, //豸У - 1Byte + Dev_DataLen, //豸ݳ - 2Byte + Dev_DataLen_H, //豸ݳ + Dev_Retrynum, //豸ط - 1Byte + Dev_WaitTime, //豸͵ȴʱ - 2Byte + Dev_WaitTime_8, + Dev_Protocol, //豸Э + Dev_Coord, //豸± + Dev_Coord_8, + Dev_ActionCoord, //± + Dev_ActionCoord_8, + Dev_Polling_CF, //豸ѯݷͻص - 4Byte + Dev_Polling_CF_8, + Dev_Polling_CF_16, + Dev_Polling_CF_24, + Dev_Processing_CF, //豸ݴص - 4Byte + Dev_Processing_CF_8, + Dev_Processing_CF_16, + Dev_Processing_CF_24, + Dev_Data_Process_0, //豸ݴص - 4Byte ҲǺָʼַ + Dev_Data_Process_8, + Dev_Data_Process_16, + Dev_Data_Process_24, + Dev_Input_Type_Get_0, //豸õص - 4Byte + Dev_Input_Type_Get_8, + Dev_Input_Type_Get_16, + Dev_Input_Type_Get_24, + Dev_Output_Ctrl_0, //豸ƻص - 4Byte + Dev_Output_Ctrl_8, + Dev_Output_Ctrl_16, + Dev_Output_Ctrl_24, + Dev_Output_Loop_State_Get_0, //豸״̬õص - 4Byte + Dev_Output_Loop_State_Get_8, + Dev_Output_Loop_State_Get_16, + Dev_Output_Loop_State_Get_24, + Dev_Output_Group_Ctrl_0, //豸ȺƵõص - 4Byte + Dev_Output_Group_Ctrl_8, + Dev_Output_Group_Ctrl_16, + Dev_Output_Group_Ctrl_24, + Dev_Output_Loop_Group_State_Get_0, //豸Ⱥ״̬õص - 4Byte + Dev_Output_Loop_Group_State_Get_8, + Dev_Output_Loop_Group_State_Get_16, + Dev_Output_Loop_Group_State_Get_24, + Dev_Privately, //豸˽б -- 豸Ͷ豸ݳ +}Device_Attribute_E; + +/*485豸״̬忪ʼ*/ +#define DEV_IS_ONLINE 0x00 //豸 +#define DEV_IS_OFFLINE 0x01 //豸 +#define DEV_IS_LINEUNINIT 0x02 //豸δʼδȷ + +#define Port_Normal_Mode 0x01 //ģʽ +#define Port_Passthrough_mode 0x02 //͸ģʽ +#define Port_Monitoring_mode 0x03 //ģʽ + +#define In_ErrFun_LineState 0x01 // - ״̬ +#define In_ErrFun_ELEPercent 0x02 // - ص +#define In_ErrFun_CurValue 0x03 // - ֵ +#define In_ErrFun_ResetTime 0x04 // - 1901 +#define In_ErrFun_LoopState 0x05 // - 豸·״̬ + +#define Passthrough_DataLen_Max 0x01E0 //͸Ϊ480Byte + +#define BLV_BUS485_WaitLdle_Time 20 //λ:ms +#define BUS_Retry_Flag 0x40 //ط־ +#define BLV_BUS485_ChangeBaudWaitTime 10 //λms +#define BLV_BUS485_ChangeBaudSendWaitTime 20 //λms +#define BLV_POLL485_ChangeBaudWaitTime 10 //λms + +/* BLV_BUS 485߿Эʽ + PKT_ADD_FMߣַ + PKT_TYPEͣʹַҲȺ + bit 7 ʾָĵַǵַȺš + bit 7 = 0 ַ + bit 7 = 1 Ⱥַ + bit 6 ʾ׷ݻطݡ + bit 6 = 0 ׷ݰ + bit 6 = 1 طݰ + bit 30 кš + кŷΧ0~15ѭۼӣÿɹһμ1 + PKT_DevType豸 + PKT_ADD_TOԷַȺţ + ΪȺʱȺ0Ӧ豸ʱϢΪȫԱ㲥Ϣ + PKT_LENȣ50 + PKT_CHKSUMУͣ1ByteݳPKT_CHKSUMֽȡࡣ + PKT_CMD̶ͣ 1Byte + PKT_PARAPKT_CMDȲ̶ +*/ +typedef enum{ + PKT_ADD_FM, + PKT_TYPE, + PKT_DevType, + PKT_ADD_TO, + PKT_LEN, + PKT_CHKSUM, + PKT_CMD, + PKT_PARA, +}BLV_BUS_PKT_E; + +/*BUS߿Э2 - ȸΪuint16_t*/ +typedef enum{ + PKT2_ADD_FM, + PKT2_TYPE, + PKT2_DevType, + PKT2_ADD_TO, + PKT2_LEN, + PKT2_LEN_8, + PKT2_CHKSUM, + PKT2_CMD, + PKT2_PARA, +}BLV_BUS_PKT2_E; + +typedef enum{ + B_IDLE, // + B_Polling, //豸ѯݷ + B_Send, //豸ݷ + Change_Dev, //л豸 + Read_Dev, //ǰ豸Ϣ + B_Retry, //ط + Wait_Reply, //ȴظ + B_Wait, //BUSߵȴ + Baud_Wait, //лʵȴ + Baud_Comm, //лʺȷһѯݣڽͨѶ + Baud_SendWait, //лʺ͵ȴ +}G_BLV_BUS; + +/*ָͶ忪ʼ*/ +typedef void (*fun_prt)(uint32_t ); +typedef uint8_t (*fun2_prt)(uint32_t ,uint32_t ,uint16_t ); +typedef void (*fun3_prt)(unsigned long); +typedef uint8_t (*fun4_prt)(uint32_t ); + + +typedef void (*Dev_Dev_Data_Process_ptr)(uint32_t CfgDevAdd); //豸ݴ ƺ⺯ +typedef uint8_t (*Dev_Dev_Input_Type_Get_ptr)(uint32_t CfgDevAddIn, uint16_t DevInputLoop, uint16_t DevInputType); //豸⺯豸·ַ +typedef void (*Dev_Output_Ctrl_ptr)(uint32_t CfgDevAddIn, uint16_t DevInputAddr, uint32_t CfgDevAddOut, uint16_t DevOutputLoop, uint16_t DevOutputType); //豸ƺ豸ͣ·ַͣɿ豸 +typedef uint16_t (*Dev_Output_Loop_State_Get_ptr)(uint32_t CfgDevAddOut, uint16_t DevOutputLoop); //豸·״̬õʱLEDָ·Ϊ50 ôӦ÷50 + +typedef void (*Dev_Output_Group_Ctrl_ptr)(uint32_t CfgDevAddIn, uint16_t DevInputAddr,uint32_t devaddr, uint32_t CtrlFlag, uint8_t CtrlNum,uint16_t *start); +typedef uint16_t (*Dev_Output_Loop_Group_State_Get_ptr)(uint32_t devaddr, uint8_t SceneType, uint32_t ReadFlag, uint8_t ReadNum,uint16_t *start); + +/*ָͶ*/ +#define Dev_Fun_Ptr_Len sizeof(Struct_Dev_Fun_Info) //Ŀǰÿ豸ĸָ һ16ֽ + +typedef struct +{ + Dev_Dev_Data_Process_ptr Dev_Data_Process; //ݴ + Dev_Dev_Input_Type_Get_ptr Dev_Input_Type_Get; // + Dev_Output_Ctrl_ptr Dev_Output_Ctrl; // + Dev_Output_Loop_State_Get_ptr Dev_Output_Loop_State_Get; //״̬õ + Dev_Output_Group_Ctrl_ptr Dev_Output_Group_Ctrl; //Ⱥ + Dev_Output_Loop_Group_State_Get_ptr Dev_Output_Loop_Group_State_Get_ptr; //Ⱥ״̬õ + +}Struct_Dev_Fun_Info; //豸Ϣṹ壬ͬ豸ӵͬĺֻǴIJһ + +/*ͨѶ¼ض*/ +#define BLV_COMM_RecordNum 30 +#define BLV_CONTINUE_FAIL_MAX 20 //ʧ +#define BLV_COMM_Fail_Precent_Max 30 //ʧٷֱ +#define BLV_COMM_Precent_Num 100 //ͨѶٷֱȿʼ¼ +#define BLV_BUS_BAUD_ADJUST_SIZE 1000 //ÿ115200*1% +#define BLV_BUS_BAUD_ADJUST_MIN 103200 +#define BLV_BUS_BAUD_ADJUST_MAX 126200 + +typedef struct{ + uint8_t record[BLV_COMM_RecordNum]; //ͨѶ¼BUFF + uint8_t num; //ǰд± + uint8_t continue_fail_num; //ʧܼ + uint8_t comm_percent; //ͨѶٷֱ + uint8_t full_flag; //¼־λ + uint8_t remian1; + uint8_t remian2; +}BLV_COMM_RECORD_G; + +typedef struct{ + uint8_t type; + uint8_t addr; + uint8_t port; + uint32_t baud; + uint8_t check; + uint16_t data_len; + uint8_t retry_num; + uint16_t wait_time; + uint8_t Protocol; //Э + uint16_t DevCoord; //豸± + uint16_t ActionCoord; //Ӧ± +/*ָʼ*/ + uint32_t polling_cf; //ͺ + uint32_t processing_cf; //մ + Struct_Dev_Fun_Info DevFunInfo; //ָṹ +/*ָ*/ +}Device_Public_Information_G; + +typedef struct{ + uint8_t port_mode; //˿ģʽ - 0x01:ģʽ 0x02:͸ģʽ 0x03:ģʽ + uint8_t pass_state; //͸״̬ + uint32_t mode_tick; //ģʽǰʱ + uint32_t mode_outtime; //ģʽʱʱ + uint32_t pass_tick; //͸ǰʱ + uint32_t pass_outtime; //͸ʱʱ + uint32_t baud; //ǰ + fun4_prt BaudRateCfg; //л + + uint8_t BUS_Start; //BUS״̬ + uint8_t device_num; //豸 + uint32_t n_list_read_addr; //ǰȡ豸ַ + uint32_t Last_list_addr; //һ豸ַ + uint32_t send_wait; //͵ȴʱ + uint8_t Process_Flag; //־ + uint8_t Retry_Flag; //طǣ֮ǰ,յظǺ㣬 + uint32_t change_tick; //лʱ + + uint8_t n_dev_type; //ǰ豸 + uint8_t n_dev_addr; //ǰ豸ַ + uint16_t n_dev_datalen; //ǰ豸ݳ + uint32_t n_dev_waittime; //ǰ豸͵ȴʱ + uint8_t n_retry_num; //ǰ豸ط + uint32_t n_polling_cf; //ǰ豸ѯͻصָ + uint32_t n_processing_cf; //ǰ豸ݻصָ + +}BLV_BUS_Manage_G; + +typedef struct{ + uint8_t port_mode; //˿ģʽ - 0x01:ģʽ 0x02:͸ģʽ 0x03:ģʽ + uint8_t pass_state; //͸״̬ + uint32_t mode_tick; //ģʽǰʱ + uint32_t mode_outtime; //ģʽʱʱ + uint32_t pass_tick; //͸ǰʱ + uint32_t pass_outtime; //͸ʱʱ + uint32_t baud; //ǰ + fun4_prt BaudRateCfg; //л + + uint8_t POLL_Start; //POLL״̬ + uint8_t device_num; //豸 + uint32_t n_list_read_addr; //ǰȡ豸ַ + uint32_t Last_list_addr; //һ豸ַ + uint32_t send_wait; //͵ȴʱ + uint8_t Process_Flag; //־ + uint8_t Retry_Flag; //طǣ֮ǰ,յظǺ㣬 + uint32_t change_tick; //лʱ + + uint8_t n_dev_type; //ǰ豸 + uint8_t n_dev_addr; //ǰ豸ַ + uint16_t n_dev_datalen; //ǰ豸ݳ + uint32_t n_dev_waittime; //ǰ豸͵ȴʱ + uint8_t n_retry_num; //ǰ豸ط + uint32_t n_polling_cf; //ǰ豸ѯͻصָ + uint32_t n_processing_cf; //ǰ豸ݻصָ + +}BLV_POLL_Manage_G; + +typedef struct{ + uint8_t port_mode; //˿ģʽ - 0x01:ģʽ 0x02:͸ģʽ 0x03:ģʽ + uint8_t pass_state; //͸״̬ + uint32_t mode_tick; //ģʽǰʱ + uint32_t mode_outtime; //ģʽʱʱ + uint32_t pass_tick; //͸ǰʱ + uint32_t pass_outtime; //͸ʱʱ + uint32_t baud; //ǰ + fun4_prt BaudRateCfg; //л + + uint8_t Act_Start; //Active״̬ + uint8_t device_num; //豸 + uint8_t process_num; //ݴ + + uint32_t list_read_addr; //ַ + uint32_t n_list_read_addr; //ǰȡ豸ַ + uint32_t Last_list_addr; //һ豸ַ + uint32_t send_wait; //͵ȴʱ + uint8_t Process_Flag; //־ + uint8_t Send_Flag; //ͱ + uint8_t Retry_Flag; //طǣ֮ǰ,յظǺ㣬 + + uint32_t n_dev_waittime; //ǰ豸͵ȴʱ + uint8_t n_retry_num; //ǰ豸ط + uint32_t n_polling_cf; //ǰ豸ѯͻصָ + uint32_t n_processing_cf; //ǰ豸ݻصָ + +}BLV_ACTIVE_Manage_G; + +typedef struct{ + uint8_t NorDeviceNum; //ͨ豸 Χ0~(DevActionNumMax-1) + uint8_t NorDevicei; //ڱͨ豸IJ +}BLV_NORDEV_Manage_G; + +extern BLV_BUS_Manage_G BUS485_Info; +extern BLV_POLL_Manage_G Poll485_Info; +extern BLV_ACTIVE_Manage_G Act485_Info; +extern BLV_NORDEV_Manage_G NorDevInfoGlobal; + +void Add_BUS_Device_To_List(Device_Public_Information_G *dev_info,uint8_t *dev_data,uint16_t data_len); +void Add_POLL_Device_To_List(Device_Public_Information_G *dev_info,uint8_t *dev_data,uint16_t data_len); +void Add_ACT_Device_To_List(Device_Public_Information_G *dev_info,uint8_t *dev_data,uint16_t data_len); +void Add_Nor_Device_To_List(Device_Public_Information_G *dev_info,uint8_t *dev_data,uint16_t data_len); +uint8_t Device_Data_Check(uint32_t sram_addr); +void BLV_BUS_Polling_Task(void); +void BUS485Port_Passthrough_Task(void); +void BLV_BUS485Port_ModeTask(void); +void BLV_PollPort_Task(void); +void Poll485Port_Passthrough_Task(void); +void BLV_PollPort_ModeTask(void); +void BLV_ActivePort_Task(void); +void Act485Port_Passthrough_Task(void); +void BLV_ActivePort_ModeTask(void); +void BLV_Active_Set_List_Addr(uint32_t addr); +uint32_t Find_Device_List_Information(uint8_t dev_type,uint8_t addr); +uint32_t Find_AllDevice_List_Information(uint8_t dev_type,uint8_t addr); +uint32_t Find_AllDevice_List_Information2(uint8_t Port, uint8_t dev_type,uint8_t addr); +uint8_t Find_The_Number_Of_Device_In_The_List(void); +uint8_t Gets_the_state_of_all_devices(uint8_t *data_buff,uint8_t num); +void Write_Device_Fault_State(uint8_t device_type,uint8_t device_addr,uint8_t fault_type,uint8_t fault_state); +void Write_Device_Loop_Fault_State(uint8_t device_type,uint8_t device_addr,uint8_t fault_type,uint8_t fault_state,uint16_t loop); +void BLV_Communication_Record(BLV_COMM_RECORD_G *dev_record,uint8_t option,uint8_t state); +uint16_t Get_BLV_Communication_Fail_Rate(BLV_COMM_RECORD_G *dev_record); + + + + + + + + +#endif /* MCU_DRIVER_INC_BLV_RS485_PROTOCOL_H_ */ diff --git a/MCU_Driver/inc/check_fun.h b/MCU_Driver/inc/check_fun.h new file mode 100644 index 0000000..429be4d --- /dev/null +++ b/MCU_Driver/inc/check_fun.h @@ -0,0 +1,25 @@ +/* + * check_fun.h + * + * Created on: Nov 8, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_CHECK_FUN_H_ +#define MCU_DRIVER_INC_CHECK_FUN_H_ + +#include + +uint8_t Log_CheckSum(uint32_t addr,uint8_t len); +uint8_t Data_CheckSum(uint8_t* data,uint16_t len); +uint8_t CheckSum_Overlook_Check(uint8_t *data, uint16_t len, uint16_t check_id); +void NetCRC16(uint8_t *aStr ,uint16_t len); +uint16_t NetCRC16_2(uint8_t *aStr ,uint16_t len); +uint16_t NetCRC16_Data(uint8_t *aStr ,uint16_t len,uint16_t crc_id); +uint8_t DoubleData_CheckSum(uint8_t *Data1, uint16_t Data1Len, uint8_t *Data2, uint16_t Data2Len); +uint8_t SOR_CRC(uint8_t *Data, uint8_t DataLen); +uint8_t DeAction_Data_Check(uint32_t sram_addr); +uint8_t DevAction_CheckSum(uint32_t addr,uint16_t len); + + +#endif /* MCU_DRIVER_INC_CHECK_FUN_H_ */ diff --git a/MCU_Driver/inc/debug.h b/MCU_Driver/inc/debug.h new file mode 100644 index 0000000..36aa448 --- /dev/null +++ b/MCU_Driver/inc/debug.h @@ -0,0 +1,83 @@ +/* + * debug.h + * + * Created on: May 14, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_DEBUG_H_ +#define MCU_DRIVER_DEBUG_H_ + +#include "ch564.h" +#include + +/* UART Printf Definition */ +#define DEBUG_UART0 1 +#define DEBUG_UART1 2 +#define DEBUG_UART2 3 +#define DEBUG_UART3 4 + +/* DEBUG log function. DEBUG printf() ض*/ +#ifndef DBG_LOG_EN +#define DBG_LOG_EN 1 //DEBUG LOG ܿ +#endif + +#define DBG_Particular_EN 1 //ϸϢ -- 嵽ļúк +#define DBG_NET_LOG_EN 1 //ģϢ + +/*Ϣʼ״̬*/ +#define DBG_OPT_ActCond_STATUS 1 //ִϢӡ +#define DBG_OPT_MQTT_STATUS 1 //MQTTϢӡ +#define DBG_OPT_Debug_STATUS 1 //ʱϢӡ +#define DBG_OPT_LOGIC_STATUS 1 //߼Ϣӡ +#define DBG_OPT_DEVICE_STATUS 1 //豸ӡϢӡ +#define DBG_OPT_NET_STATUS 1 //Ϣӡ +#define DBG_OPT_SYS_STATUS 1 //ϵͳϢӡ + +/*Ϣλ*/ +#define DBG_BIT_ActCond_STATUS_bit 6 +#define DBG_BIT_MQTT_STATUS_bit 5 +#define DBG_BIT_Debug_STATUS_bit 4 +#define DBG_BIT_LOGIC_STATUS_bit 3 +#define DBG_BIT_DEVICE_STATUS_bit 2 +#define DBG_BIT_NET_STATUS_bit 1 +#define DBG_BIT_SYS_STATUS_bit 0 + + +#ifdef DBG_LOG_EN +#define DBG_Printf(...) printf(__VA_ARGS__) +#else +#define DBG_Printf(...) +#endif + +#ifdef DBG_Particular_EN +#define DBG_log(...) {DBG_Printf("%s %s-%d :",__FILE__,__func__,__LINE__);DBG_Printf(__VA_ARGS__);} +#else +#define DBG_log(...) DBG_Printf(__VA_ARGS__) +#endif + +#define DBG_INFO(msg) DBG_Printf("%s %s-%d :%s",__FILE__,__func__,__LINE__,msg) + +#ifdef DBG_NET_LOG_EN +#define DBG_NET_log(...) DBG_Printf(__VA_ARGS__) +#else +#define DBG_NET_log(...) +#endif + +extern uint32_t Dbg_Switch; + + +extern volatile uint32_t SysTick_100us; +extern volatile uint32_t SysTick_1ms; +extern volatile uint32_t SysTick_1s; + +void Systick_Init(void); +void Delay_Us(uint32_t n); +void Delay_Ms(uint32_t n); + +void Dbg_NoTick_Print(int DbgOptBit ,const char *cmd, ...); +void Dbg_Print(int DbgOptBit ,const char *cmd, ...); +void Dbg_Println(int DbgOptBit ,const char *cmd, ...); +void Dbg_Print_Buff(int DbgOptBit ,const char *cmd ,uint8_t *buff,uint32_t len); + +#endif /* MCU_DRIVER_DEBUG_H_ */ diff --git a/MCU_Driver/inc/flash_mem_addr.h b/MCU_Driver/inc/flash_mem_addr.h new file mode 100644 index 0000000..78ffae6 --- /dev/null +++ b/MCU_Driver/inc/flash_mem_addr.h @@ -0,0 +1,43 @@ +/* + * flash_mem_addr.h + * + * Created on: Oct 30, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_FLASH_MEM_ADDR_H_ +#define MCU_DRIVER_INC_FLASH_MEM_ADDR_H_ + +/*APPݼ - ʼ*/ +#define APPFlag_UartUpgrade_Reset 0xBBC1 //APP־λ + +#define SPIFLASH_APP_Start_Addr 0x00000000 + +#define SPIFLASH_APP_FEATURE_Addr 0x00000000 // - 512Byte + + +#define SPIFLASH_UPDATE_RECORD_Addr 0x00000200 //дͳƱַ - 512Byte + +#define SPIFLASH_APP_Data_Start_Addr 0x00004000 +#define SPIFLASH_APP_Data_End_Addr 0x0006FFFF + +#define SPIFLASH_APP_End_Addr 0x0006FFFF +/*APPݼ - */ + + +#define FLASH_Register_Start_ADDRESS 0x00088000 //ĿĴֵ - ʼַ +#define FLASH_Register_End_ADDRESS 0x000887FF //ĿĴֵ - ַ + +#define FLASH_MCU_Model_Revision_ADDRESS 0x0008A000 //MCU汾ͺ 64Byte +#define FLASH_MCU_Control_Revision_ADDRESS 0x0008A040 //MCUпذ汾ͺ 64Byte + +/*ļ*/ + +#define SPIFLASH_LOGIC_FILE_Start_Addr 0x00090000 +#define SPIFLASH_LOGIC_DataFlag_ADDRESS 0x00090000 //ļ־λ - 4Byte +#define SPIFLASH_LOGIC_DataSize_ADDRESS 0x00090004 //ļ - 4Byte +#define SPIFLASH_LOGIC_DataMD5_ADDRESS 0x00090008 //ļMD5Уֵ - 16Byte +#define SPIFLASH_LOGIC_DataStart_ADDRESS 0x00090200 //ļʼַ +#define SPIFLASH_LOGIC_FILE_End_Addr 0x000FFFFF + +#endif /* MCU_DRIVER_INC_FLASH_MEM_ADDR_H_ */ diff --git a/MCU_Driver/inc/led.h b/MCU_Driver/inc/led.h new file mode 100644 index 0000000..e960935 --- /dev/null +++ b/MCU_Driver/inc/led.h @@ -0,0 +1,20 @@ +/* + * led.h + * + * Created on: May 15, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_LED_H_ +#define MCU_DRIVER_INC_LED_H_ + +#include "ch564.h" + +#define SYS_LED_ON GPIOB_ResetBits(GPIO_Pin_12) +#define SYS_LED_OFF GPIOA_SetBits(GPIO_Pin_12) +#define SYS_LED_FLIP GPIOA_InverseBits(GPIO_Pin_12) + +void SYS_LED_Init(void); +void SYS_LED_Task(void); + +#endif /* MCU_DRIVER_INC_LED_H_ */ diff --git a/MCU_Driver/inc/log_api.h b/MCU_Driver/inc/log_api.h new file mode 100644 index 0000000..c0fba84 --- /dev/null +++ b/MCU_Driver/inc/log_api.h @@ -0,0 +1,126 @@ +/* + * log_api.h + * + * Created on: Jul 29, 2025 + * Author: cc + */ + +#ifndef _LOG_API_H_ +#define _LOG_API_H_ + +#include "ch564.h" +#include + +#define LogType_Enable 1 //LOGʹ + +/*־洢Ͷ*/ +#define LogType_Launcher 0x01 //LauncherϢ¼ +#define LogType_SYS_Record 0x02 //ϵͳϢ¼ +#define LogType_Device_COMM 0x03 //豸ͨѶ¼ +#define LogType_Device_Online 0x04 //豸ͨѶ״̬¼ +#define LogType_Global_Parameters 0x05 //豸״̬ڼ¼ +#define LogType_Net_COMM 0x06 //ͨѶ¼ +#define LogType_Logic_Record 0x07 //߼¼ + +/*־洢 - ʼ״̬*/ +#define LogType_Launcher_SWITCH 1 +#define LogType_SYS_Record_SWITCH 1 +#define LogType_Device_COMM_SWITCH 1 +#define LogType_Device_Online_SWITCH 1 +#define LogType_Global_Parameters_SWITCH 1 +#define LogType_Net_COMM_SWITCH 1 +#define LogType_Logic_Record_SWITCH 1 + +/*־洢λ*/ +#define LogType_Launcher_bit 0 +#define LogType_SYS_Record_bit 1 +#define LogType_Device_COMM_bit 2 +#define LogType_Device_Online_bit 3 +#define LogType_Global_Parameters_bit 4 +#define LogType_Net_COMM_bit 5 +#define LogType_Logic_Record_bit 6 + +extern uint32_t SYS_Log_Switch; + +/*־ز*/ +#define LogInfo_Device_Online 0x01 //豸 +#define LogInfo_Device_Offline 0x02 //豸 + +typedef enum{ + LLauncher_App_Check = 0x01, //УAPP + LLauncher_Read_App, //ȡAPPAPPд뵽MCU FLash + LLauncher_Write_Flash, //дFlash + LLauncher_Factory_Reset, //ָ + LLauncher_Reset_Source, //λԴ + LLauncher_RCUKey_State, //RCU¼¼ +}LOGTYPE_Launcher_E; + +typedef enum { + LSYS_PHY_Change = 0x01, //PHY״̬仯¼ + LSYS_DevInfo_Error, //豸Ϣ + LSYS_API_State, //״̬ + LSYS_NET_ARGC, //ʼ + LSYS_MQTT_ARGC, //MQTT + LSYS_Server_Comm_State, //ƶͨѶ״̬¼ + LSYS_NET_DefaultARGC, //Ĭϲ + LSYS_RCUKey_State, //RCU¼¼ +}LOGTYPR_SYSRecord; + +typedef enum { + LCOMM_ASK_TO_Reply = 0x01, //ѯظ + LCOMM_Send_Control, //RCU· + LCOMM_Control_Reply, //RCUƻظ + LCOMM_Adjust_Baud, //豸 +}LOGTYPE_DEV_COMM; + +typedef enum { + LGlobal_Para = 0x01, // + LGlobal_Dev, //豸 +}LOGTYPE_Global_E; + +typedef enum { + LNetComm_Send = 0x01, //緢 + LNetComm_Recv, // +}LOGTYPE_NET_COMM_E; + +typedef enum { + LLogic_DebugString = 0x01, //߼ - ַϢ + +}LOGTYPE_LOGICRecord_E; + +/*LauncherϢ¼API*/ +void LOG_Launcher_APP_Check_Record(uint8_t state); +void LOG_Launcher_Read_App_Record(uint8_t state); +void LOG_Launcher_Write_Flash_Record(uint32_t addr,uint16_t len); +void LOG_Launcher_Factory_Reset_Record(void); +/*ϵͳϢ¼API*/ +void LOG_SYS_PHY_Change_Record(uint8_t state); +void LOG_SYS_DevInfo_Error_Record(uint8_t dev,uint8_t addr,uint32_t info_addr); +void LOG_SYS_API_State_Record(uint8_t API_way,uint8_t state); +void LOG_SYS_NET_Argc_Record(uint8_t *IP,uint8_t *MAC,uint8_t *DNS_IP1,uint8_t *DNS_IP2,uint8_t *DNS_IP3); +void LOG_SYS_MQTT_Argc_Record(uint8_t *productkey,uint8_t *devname,uint8_t *devsecret,uint8_t *publish,uint8_t *sublish); +void LOG_SYS_Server_Comm_State_Record(uint8_t state); +void LOG_SYS_NET_Argc_Init_Record(uint8_t *IP,uint8_t *Gateway,uint8_t *IP_Mask,uint8_t *DNS_Add,uint8_t ArgcFlag,uint8_t DHCPFlag,uint8_t ServerFlag); +void LOG_SYS_RCUKey_State_Record(uint8_t state); +/*豸ͨѶ¼API*/ +void LOG_Device_COMM_ASK_TO_Reply_Record(uint8_t port,uint32_t baud,uint32_t data_tick,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_ASK_TO_Reply_Record2(uint32_t port_addr,uint32_t baud_addr,uint32_t data_tick,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_Send_Control_Record(uint8_t port,uint32_t baud,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_Send_Control_Record2(uint32_t port_addr,uint32_t baud_addr,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_Control_Reply_Record(uint8_t port,uint32_t baud,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_Control_Reply_Record2(uint32_t port_addr,uint32_t baud_addr,uint8_t *buff,uint16_t len); +void LOG_Device_COMM_Control_Reply_Record3(uint32_t port_addr,uint32_t baud_addr,uint32_t buff_addr,uint16_t len); +void LOG_Device_COMM_Adjust_Baud_Record(uint8_t dev_type,uint8_t dev_addr,uint32_t baud,uint8_t way,uint8_t fail_num,uint8_t sum,uint8_t num); +void LOG_Device_COMM_Adjust_Baud_Record2(uint32_t dev_type,uint32_t dev_addr,uint32_t baud_addr); +/*豸ͨѶ״̬¼API*/ +void LOG_Device_Online_Record(uint8_t dev,uint8_t addr,uint8_t state); +/*豸״̬ڼ¼API*/ +void LOG_Global_ParaInfo_Record(uint8_t *buff,uint16_t len); +void LOG_Global_DevInfo_Record(uint8_t *buff,uint16_t len); +/*ͨѶ¼API*/ +void LOG_NET_COMM_Send_Record(uint8_t SocketId,uint8_t *ip,uint16_t port,uint8_t *buff,uint16_t len); +void LOG_NET_COMM_Recv_Record(uint8_t SocketId,uint8_t *ip,uint16_t port,uint8_t *buff,uint16_t len); +/*߼¼API*/ +void LOG_LogicInfo_DebugRecord(char *fmt,...); + +#endif /* MCU_DRIVER_INC_LOG_API_H_ */ diff --git a/MCU_Driver/inc/logic_file_function.h b/MCU_Driver/inc/logic_file_function.h new file mode 100644 index 0000000..2800ee2 --- /dev/null +++ b/MCU_Driver/inc/logic_file_function.h @@ -0,0 +1,171 @@ +/* + * logic_file_function.h + * + * Created on: Nov 11, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_LOGIC_FILE_FUNCTION_H_ +#define MCU_DRIVER_INC_LOGIC_FILE_FUNCTION_H_ + +#include + + +typedef enum +{ + ENUM_RS485_DEV_PRO_00, //0Э //0 + ENUM_RS485_DEV_PRO_01, //1Э //1 + ENUM_RS485_DEV_PRO_02, //2Э //2 + ENUM_RS485_DEV_PRO_03, //3Э //3 + ENUM_RS485_DEV_PRO_04, //4Э //4 + ENUM_RS485_DEV_PRO_05, //5Э //5 + ENUM_RS485_DEV_PRO_06, //6Э //6 + ENUM_RS485_DEV_PRO_07, //7Э //7 + ENUM_RS485_DEV_PRO_08, //8Э //8 + ENUM_RS485_DEV_PRO_09, //9Э //9 + ENUM_RS485_DEV_PRO_10, //10Э //10 + ENUM_RS485_DEV_PRO_11, //11Э //11 + ENUM_RS485_DEV_PRO_12, //12Э //12 + ENUM_RS485_DEV_PRO_13, //13Э //13 + ENUM_RS485_DEV_PRO_14, //14Э //14 + ENUM_RS485_DEV_PRO_15, //15Э //15 + ENUM_RS485_DEV_PRO_16, //16Э //16 + ENUM_RS485_DEV_PRO_17, //17Э //17 + ENUM_RS485_DEV_PRO_18, //18Э //18 + ENUM_RS485_DEV_PRO_19, //19Э //19 +// ENUM_RS485_DEV_PRO_20, //ǰЭֵ //20 + +}enum_RS485Protocol; //ͬ豸԰Эз + +#define LOGIC_DataFlag 0xCC060001 //߼־ +#define Logic_FrameType_LogicInfo 0x01 //Ϣ +#define Logic_FrameType_Global 0x02 //ȫϢ +#define Logic_FrameType_DeviceExist 0x03 //豸 +#define Logic_FrameType_DeviceAction 0x04 //豸 +#define Logic_FrameType_VoiceMap 0x05 //ӳϢ + +#define Logic_FrameType_DevCheckMap 0x07 //豸Ѳ·Ϣ + +#define Logic_FrameType_VCCondition 0x08 //޿ȡϢ +#define Logic_FrameType_VCPortInfor 0x09 //޿ȡӳ˿Ϣ +#define Logic_FrameType_VCProperty 0x0B //޿ȡ豸 + +#define Logic_FrameType_ColorTempMap 0x0A //ɫµڶ˿ӳ + +#define LogicFile_DeviceInfo_InputSet 79 //߼ļ豸Ϣ± 2022-05-30 ֽڴ32->64 + +typedef enum{ + Logic_D_Hear_L, + Logic_D_Hear_H, + Logic_D_Len_L, + Logic_D_Len_H, + Logic_D_CRC_L, + Logic_D_CRC_H, + Logic_D_Frame_L, + Logic_D_Frame_H, + Logic_D_FrameNum_L, + Logic_D_FrameNum_H, + Logic_D_FrameType, + Logic_D_Para, +}LOGIC_INFO_E; + +typedef struct { + uint8_t type; //豸 + uint8_t addr; //豸ַ + uint8_t port; //豸˿ + uint32_t baud; //豸 + uint8_t version; //豸Э汾 + uint8_t retry; //ͨѶط + uint16_t writ_time; //ͨѶȴʱ + uint8_t ipaddr[4]; //п豸 + uint8_t parent_type; //豸 + uint8_t parent_addr; //豸ַ + uint8_t parent_port; //豸˿ + uint8_t lin[5]; //޿ϵ· + uint8_t priproperty[10]; //˽ + uint8_t remain[42]; //ֽ + uint16_t input_num; //· + uint16_t output_num; //· +}LOGICFILE_DEVICE_INFO; //߼ļ - 豸Ϣṹ + +typedef struct{ + uint64_t DevActionOutFlag:1; //ʹ + uint64_t RoomState:3; //̬ + uint64_t EleCtrlFlag:1; //ȡ + uint64_t EleState:3; //ȡ״̬ + uint64_t DndState:3; //״̬ + uint64_t CleanState:3; //״̬ + uint64_t CallState:3; //״̬ + uint64_t WashState:3; //ϴ״̬ + uint64_t CheckOutState:3; //˷״̬ + uint64_t WaitState:3; //Ժ״̬ + uint64_t SosState:3; //SOS״̬ + uint64_t RentState:3; //ԤԼ״̬ + uint64_t LockState:3; //״̬ + uint64_t LuggageState:3; //״̬ + uint64_t StrongState:3; //״̬ + uint64_t DoorState:3; //Ŵ״̬ + uint64_t WarningState:3; //ʾ״̬ + uint64_t BacklightState:3; //״̬ + uint64_t SeasonState:3; // + uint64_t TimeState:3; //ʱ + uint64_t NeightState:3; //ҹ״̬ + uint64_t RcuLockState:3; //1 0 + uint64_t Reserve1:2; //2λ +}LOGIC_ACTIVE_CONDITION_G; //߼ļ - 豸ṹ + +typedef struct { + uint8_t type; //豸 + uint8_t addr; //豸ַ + uint16_t loop; //豸· + uint8_t execute; //豸ִзʽ + uint8_t content; //豸ִ + uint8_t delay_time; //ִʱʱ + uint8_t delay_unit; //ִʱʱ䵥λ +}LOGIC_DEVICE_ACTIVE_G; //߼ݽṹ + +#if C8_TYPE + +#define BusDevice_NumMax 10 //BUS豸 +#define PollingDevice_NumMax 15 //ѯ豸 +#define ActiveDevice_NumMax 20 //豸 +#define NorDevice_NumMax 34 //ͨ豸 + +#else + +#define BusDevice_NumMax 10 //BUS豸 +#define PollingDevice_NumMax 20 //ѯ豸 +#define ActiveDevice_NumMax 34 //豸 +#define NorDevice_NumMax 15 //ͨ豸 + +#endif + +typedef struct { + uint8_t Bus_device_num; + uint8_t Active_device_num; + uint8_t Polling_device_num; + uint8_t Nor_device_num; + + uint16_t device_num; + uint16_t active_num; + uint16_t voicemap_num; + uint16_t devcheckmap_num; //2023-11-27 + + uint32_t Bus_device_addr[BusDevice_NumMax]; + uint32_t Polling_device_addr[PollingDevice_NumMax]; + uint32_t Active_device_addr[ActiveDevice_NumMax]; + uint32_t Nor_device_addr[NorDevice_NumMax]; + + uint32_t ColorTemp_Map_Addr; //ɫӳַ +}LOGICFILE_Content_Of_Statistical; //߼ļͳʹ + + + +void BLV_DevAction_AllData_Init(void); +uint8_t Read_LogicFile_Information(uint8_t select,uint8_t *buff); +uint8_t LOGIC_FILE_Check(void); + + + + +#endif /* MCU_DRIVER_INC_LOGIC_FILE_FUNCTION_H_ */ diff --git a/MCU_Driver/inc/md5.h b/MCU_Driver/inc/md5.h new file mode 100644 index 0000000..f55dde7 --- /dev/null +++ b/MCU_Driver/inc/md5.h @@ -0,0 +1,20 @@ +/* + * md5.h + * + * Created on: Nov 12, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_MD5_H_ +#define MCU_DRIVER_INC_MD5_H_ + +#include +#include +#include +#include + +void MD5Digest(char *pszInput, unsigned int nInputSize, char *pszOutPut); +void MD5Digest_SRAM(uint32_t add, unsigned int nInputSize, char *pszOutPut); +void MD5Digest_FLASH(uint32_t add, unsigned int nInputSize, char *pszOutPut); + +#endif /* MCU_DRIVER_INC_MD5_H_ */ diff --git a/MCU_Driver/inc/rtc.h b/MCU_Driver/inc/rtc.h new file mode 100644 index 0000000..14244a6 --- /dev/null +++ b/MCU_Driver/inc/rtc.h @@ -0,0 +1,55 @@ +/* + * rtc.h + * + * Created on: Jul 29, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_RTC_H_ +#define MCU_DRIVER_INC_RTC_H_ + +#include +#include "ch564.h" + +typedef struct{ + uint8_t second; + uint8_t minute; + uint8_t hour; + uint8_t week; + uint8_t day; + uint8_t month; + uint8_t year; +}S_RTC; + +typedef struct{ + uint32_t hour; + uint16_t minute; + uint16_t second; +}G_CORE_RTC; + +typedef struct{ + uint8_t time_select; //ǰʱѡ 0x00:ǰδѡ0x01: ѡ񱾵ضʱ0x02:ӲCSIO RTCʱ + uint8_t csio_rtc_cnt; //CSIO RTCʱӼ + + int16_t timezone; //ʱƫ + uint32_t Mcu_GetTime_tick; +}TIME_INFO_T; + +extern S_RTC RTC_Raw_Data; +extern S_RTC MCU_RTC_Data; +extern S_RTC Net_RTC_Data; +extern TIME_INFO_T g_time_info; +extern uint32_t Log_Time_ms; + +void RTC_Init(void); +uint8_t HEX_Conversion_To_DEC(uint8_t c_num); +uint8_t DEV_Conversion_To_HEX(uint8_t c_num); +uint32_t RTC_Conversion_To_Unix(S_RTC *rtc_time); +void Unix_Conversion_To_RTC(S_RTC *rtc_time,uint32_t utc_tick); +uint8_t RTC_ReadDate(S_RTC *psRTC); +uint8_t RTC_WriteDate(S_RTC SetRTC); +void RTC_TASK(void); +uint8_t RTC_TimeDate_Correct_Figure(uint8_t data); + + +#endif /* MCU_DRIVER_INC_RTC_H_ */ diff --git a/MCU_Driver/inc/rw_logging.h b/MCU_Driver/inc/rw_logging.h new file mode 100644 index 0000000..790eb46 --- /dev/null +++ b/MCU_Driver/inc/rw_logging.h @@ -0,0 +1,49 @@ +/* + * rw_logging.h + * + * Created on: Jul 29, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_RW_LOGGING_H_ +#define MCU_DRIVER_INC_RW_LOGGING_H_ + +#include "ch564.h" +#include + +#define APPFlag_UartUpgrade_Reset 0xBBC1 //APP־λ + +//־ض +#define LOG_Data_Hand 0xA5 //LOGͷ +#define Log_Data_End 0x5A //LOGβ +#define Log_Data_Len_MAX 512 //־512Byte + +/*־ݸʽ*/ +typedef enum{ + S_Log_Hand, + S_Log_SN, //־ÿк + S_Log_Len, + S_Log_Len_8, + S_Log_Check, + S_Log_Date_H, //꣺5bit £5bit գ5bit + S_Log_Date_L, + S_Log_Type, + S_Log_Time8B, //Сʱʱ + S_Log_Time16B, + S_Log_Time24B, + S_Log_Time32B, + S_Log_Data, +}Sram_Log_Data_Format; + + +uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len); +void Retain_Flash_Register_Data(void); +void Read_Flash_Register_Data(void); +void LOG_Save_Global_Parameters(void); +uint8_t SRAM_PowerOn_Restore_ParaInfo(void); + + + + + +#endif /* MCU_DRIVER_INC_RW_LOGGING_H_ */ diff --git a/MCU_Driver/inc/spi_flash.h b/MCU_Driver/inc/spi_flash.h new file mode 100644 index 0000000..1c59336 --- /dev/null +++ b/MCU_Driver/inc/spi_flash.h @@ -0,0 +1,65 @@ +/* + * spi_flash.h + * + * Created on: May 20, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_SPI_FLASH_H_ +#define MCU_DRIVER_INC_SPI_FLASH_H_ + +#include "ch564.h" + +#define Flash_CS_H GPIOA_SetBits(GPIO_Pin_11) +#define Flash_CS_L GPIOA_ResetBits(GPIO_Pin_11) + +#define Flash_ADDRESS_MAX 0x00200000 + +/***********ָ**********/ +//Read +#define P24Q40H_ReadData 0x03 +#define P24Q40H_FastReadData 0x0B +#define P24Q40H_FastReadDual 0x3B +//Program and Erase +#define P24Q40H_PageErase 0x81 +#define P24Q40H_SectorErase 0x20 +#define P24Q40H_BlockErase 0xD8 +#define P24Q40H_ChipErase 0xC7 +#define P24Q40H_PageProgram 0x02 +//Protection +#define P24Q40H_WriteEnable 0x06 +#define P24Q40H_WriteDisable 0x04 +//Status Register +#define P24Q40H_ReadStatusReg 0x05 +#define P24Q40H_WriteStatusReg 0x01 +//Other Commands +#define P24Q40H_PowerDown 0xB9 +#define P24Q40H_ReleasePowerDown 0xAB +#define P24Q40H_ReadManufactureID 0x90 +#define P24Q40H_ReadDeviceID 0x9F +#define P24Q40H_ResetEnable 0x66 +#define P24Q40H_Reset 0x99 + +extern uint8_t Temp_Flash_Buff[4100]; + +void SPI_FLASH_Init(void); +uint8_t Flash_ReadSR(void); +void Flash_WriteSR(uint8_t sr_val); +void Flash_Write_Enable(void); +void Flash_Write_Disable(void); +uint16_t Flash_ReadID(void); +uint8_t Flash_Wait_Busy(void); +void Flash_PowerDown(void); +void Flash_Wakeup(void); +void Flash_Erase_Chip(void); +void Flash_Erase_Block(uint32_t BLK_ID); +void Flash_Erase_Sector(uint32_t DST_ID); +void Flash_Erase_Page(uint32_t Page_ID); +void Flash_Erase_Pageaddr(uint32_t Page_addr); +void Flash_Read(uint8_t* pBuffer,uint16_t NumByteToRead,uint32_t ReadAddr); +void Flash_Write_Page(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr); +void Flash_Write_NoCheck(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr); +void Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t WriteAddr); + + +#endif /* MCU_DRIVER_INC_SPI_FLASH_H_ */ diff --git a/MCU_Driver/inc/spi_sram.h b/MCU_Driver/inc/spi_sram.h new file mode 100644 index 0000000..498b45d --- /dev/null +++ b/MCU_Driver/inc/spi_sram.h @@ -0,0 +1,46 @@ +/* + * spi_sram.h + * + * Created on: May 16, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_SPI_SRAM_H_ +#define MCU_DRIVER_INC_SPI_SRAM_H_ + +#include "ch564.h" + +#define SRAM_CE_H GPIOA_ResetBits(GPIO_Pin_11) +#define SRAM_CE_L GPIOA_SetBits(GPIO_Pin_11) + +#define SRAM_CMD_Read 0x03 +#define SRAM_CMD_Fast_Read 0x0B +#define SRAM_CMD_Fast_Read_Quad 0xEB +#define SRAM_CMD_Write 0x02 +#define SRAM_CMD_Quad_Write 0x38 +#define SRAM_CMD_Enter_Quad_Mode 0x35 +#define SRAM_CMD_Exit_Quad_Mode 0xF5 +#define SRAM_CMD_Reset_Enable 0x66 +#define SRAM_CMD_Reset 0x99 +#define SRAM_CMD_Wrap_Boundary_Toggle 0xC0 +#define SRAM_CMD_Read_ID 0x9F + +#define SRAM_ADDRESS_MAX 0x00800000 + + +void SPI_SRAM_Init(void); +void SRAM_Write_Byte(uint8_t wdate,uint32_t add); +uint8_t SRAM_Read_Byte(uint32_t add); +void SRAM_Write_Word(uint16_t wdate,uint32_t add); +uint16_t SRAM_Read_Word(uint32_t add); +void SRAM_Write_DW(uint32_t wdate,uint32_t add); +uint32_t SRAM_Read_DW(uint32_t add); +uint8_t SRAM_Read_ID_Opeartion(void); +void SRAM_Reset_Operation(void); + +void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add); +void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add); + + + +#endif /* MCU_DRIVER_INC_SPI_SRAM_H_ */ diff --git a/MCU_Driver/inc/sram_mem_addr.h b/MCU_Driver/inc/sram_mem_addr.h new file mode 100644 index 0000000..1acc5aa --- /dev/null +++ b/MCU_Driver/inc/sram_mem_addr.h @@ -0,0 +1,272 @@ +/* + * sram_mem_addr.h + * ⲿSRAMַΧ0x00000000 ~ 0x007FFFF + * + * Created on: Oct 30, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_SRAM_MEM_ADDR_H_ +#define MCU_DRIVER_INC_SRAM_MEM_ADDR_H_ + +/*豸ض - ʼ + *********************************************************** +//SRAM豸Ϣ洢ַ - + 豸ṹ - + ʼַΪ0x000100 + ȴ洢BUS豸ϢN ַƫ0x000200*N -> SRAM_BUS_Device_List_Addr + ڴ֮Ǵ洢ѯ豸ϢN ַƫ0x000200*N -> SRAM_POLL_Device_List_Addr + Ȼ豸ϢN ַƫ0x000200*N -> SRAM_ACTIVE_Device_List_Addr + ͨ豸ϢN + + 豸ʱҪ豸˳ӣ + +***************************************************************************************** +| | ʼַ | ַ | +| BUS豸Ϣ | SRAM_Device_List_Start_Addr | SRAM_BUS_Device_List_Addr | +| ѯ豸Ϣ | SRAM_BUS_Device_List_Addr | SRAM_POLL_Device_List_Addr | +| 豸Ϣ | SRAM_POLL_Device_List_Addr | SRAM_ACTIVE_Device_List_Addr | +| ͨ豸Ϣ | SRAM_ACTIVE_Device_List_Addr| SRAM_Device_List_End_Addr | +***************************************************************************************** + * */ +#define SRAM_Device_List_Size 0x00000200 //豸洢ռС - 豸ϢܴС +#define SRAM_BUS_Device_List_Addr 0x00000000 //BUS豸ƫƵַ - 4Byte +#define SRAM_POLL_Device_List_Addr 0x00000004 //ѯ豸ƫƵַ +#define SRAM_ACTIVE_Device_List_Addr 0x00000008 //豸ƫƵַ +#define SRAM_NORMAL_Device_List_Addr 0x0000000C //ͨ豸ƫƵַ + +#define SRAM_Device_List_Start_Addr 0x00000100 //豸ʼַ +#define SRAM_Device_List_End_Addr 0x00009FFF //豸ַ +/*豸ض - */ + +/*豸Ϣ - LOGȫ +ַΧ0x00B000 - 0x00BFFF*/ +#define SRAM_LOG_Device_C5IO_Relay_Status 0x0000B000 //̵״̬ - 3Byte +#define SRAM_LOG_Device_C5IO_DO_Status 0x0000B003 //DO״̬ - 1byte +#define SRAM_LOG_Device_C5IO_DI_Status 0x0000B004 //DI״̬ - 2Byte +#define SRAM_LOG_Device_C5MUSIC_Playback_Status 0x0000B006 //Ƶ - ǰ״̬ - 1Byte +#define SRAM_LOG_Device_C5MUSIC_Volume_Status 0x0000B007 //Ƶ - ǰ - 1Bye +#define SRAM_LOG_Device_C5MUSIC_idx_Status 0x0000B008 //Ƶ - ǰ - 2Byte +#define SRAM_LOG_Device_Card_Status 0x0000B00A //忨ȡ - 1Byte 2025-09-03 ûʹ +#define SRAM_LOG_Device_Temp_Status 0x0000B00B //¿ - 2Byte + +/**/ +#define SRAM_LOG_Device_Switch_Type 0x0000B00D // - 1Byte +#define SRAM_LOG_Device_Switch_Num 0x0000B00E //ظ - 1Byte +#define SRAM_LOG_Device_Switch1_Status 0x0000B00F //1 2Byte һռ2Byte +#define SRAM_LOG_Device_Switch2_Status 0x0000B011 //2 2Byte һռ2Byte +#define SRAM_LOG_Device_Switch3_Status 0x0000B013 //3 2Byte һռ2Byte +#define SRAM_LOG_RCU_Reboot_Reason 0x0000B015 //RCUԭ¼ϱʹ 2025-09-27 + +/*豸Ϣ - UDPȫ +ַΧ0x00C000 - 0x00CFFF*/ +#define SRAM_UDP_Device_C5IO_Relay_Status 0x0000C000 //̵״̬ - 3Byte +#define SRAM_UDP_Device_C5IO_DO_Status 0x0000C003 //DO״̬ - 1byte +#define SRAM_UDP_Device_C5IO_DI_Status 0x0000C004 //DI״̬ - 2Byte +#define SRAM_UDP_Device_C5MUSIC_Playback_Status 0x0000C006 //Ƶ - ǰ״̬ - 1Byte +#define SRAM_UDP_Device_C5MUSIC_Volume_Status 0x0000C007 //Ƶ - ǰ - 1Bye +#define SRAM_UDP_Device_C5MUSIC_idx_Status 0x0000C008 //Ƶ - ǰ - 2Byte +#define SRAM_UDP_Device_Card_Status 0x0000C00A //忨ȡ - 1Byte +#define SRAM_UDP_Device_Temp_Status 0x0000C00B //¿ - 2Byte +/**/ +#define SRAM_UDP_Device_Switch_Type 0x0000C00D // - 1Byte +#define SRAM_UDP_Device_Switch_Num 0x0000C00E //ظ - 1Byte +#define SRAM_UDP_Device_Switch1_Status 0x0000C00F //1 2Byte һռ2Byte + +#define SRAM_UDP_ELEReport_Action 0x0000C011 //UDP ȡϱУȡ״̬ж +#define SRAM_UDP_ELEReport_EleState 0x0000C012 //UDP ȡϱУȡ״̬ж費Ҫϱ +#define SRAM_UDP_ELEReport_EleState_Last 0x0000C013 +#define SRAM_UDP_ELEReport_CardState 0x0000C014 //UDP ȡϱУ忨ȡ״̬ж費Ҫϱ +#define SRAM_UDP_ELEReport_CardState_Last 0x0000C015 +#define SRAM_UDP_ELEReport_CardType 0x0000C016 //UDP ȡϱУ忨ȡж費Ҫϱ +#define SRAM_UDP_ELEReport_CardType_Last 0x0000C017 +#define SRAM_UDP_ELEReport_VirtualCard 0x0000C018 //UDP ȡϱУ޿ȡ¼ж費Ҫϱ +#define SRAM_UDP_ELEReport_VirtualCard_Last 0x0000C019 +#define SRAM_UDP_Report_CarbonSatet 0x0000C01A //UDP ϱУ̼˵״̬ + +/*SRAMϱ豸仯·ƻ +ַΧ0x00D000 - 0x00DFFF*/ +#define SRAM_UDP_SendData_Writeaddr 0x0000D000 //豸дַ +#define SRAM_UDP_SendData_Readaddr 0x0000D004 //豸ݶȡַ +#define SRAM_UDP_SendData_Tempaddr 0x0000D008 // + +#define SRAM_UDP_SendData_Startaddr 0x0000D010 //豸ݱʼַ +#define SRAM_UDP_SendData_Endaddr 0x0000D7EA //豸ݱַ +#define SRAM_UDP_SendData_Size 0x9C //һη + +#define SRAM_UDP_RecvData_Writeaddr 0x0000D800 //շ·дַ +#define SRAM_UDP_RecvData_Readaddr 0x0000D804 //շ·ݶȡַ +#define SRAM_UDP_RecvData_Tempaddr 0x0000D808 //շ·ʱַ +#define SRAM_UDP_RecvData_ControlNum 0x0000D80C //շ·豸 +#define SRAM_UDP_RecvData_Startaddr 0x0000D810 //ջʼַ +#define SRAM_UDP_RecvData_Endaddr 0x0000DFEA //ջݽַ + +/*ϵָ + * ַΧ:0x0x00E100 ~ 0x00E1FF */ +#define SRAM_PowerOn_Restore_StartAddr 0x0000E100 +#define SRAM_PowerOn_Restore_Flag 0x0000E100 +#define SRAM_PowerOn_Restore_Len 0x0000E101 +#define SRAM_PowerOn_Restore_Check 0x0000E102 +#define SRAM_PowerOn_Restore_Param 0x0000E103 +#define SRAM_PowerOn_Restore_EndAddr 0x0000E1FF + +/*Launcherʹ ڼ¼Boot дMCU Flash С0x200 2025-04-28*/ +#define SRAM_APP_FEATURE_2_CHECK_Addr 0x0000E600 + +/*¼Launcher汾Ϣ С0x20 2025-07-07*/ +#define SRAM_Launcher_SoftwareVer_Addr 0x0000E800 + + + +/**********SRAM Uartض - ʼ**********/ +#define SRAM_Uart_Buffer_Size 0x0400 //ڻһݴС + +#define SRAM_UART0_RecvBuffer_Start_Addr 0x00010000 +#define SRAM_UART0_RecvBuffer_End_Addr 0x00010FFF +#define SRAM_UART0_SendBuffer_Start_Addr 0x00011000 +#define SRAM_UART0_SendBuffer_End_Addr 0x00011FFF + +#define SRAM_UART1_RecvBuffer_Start_Addr 0x00012000 +#define SRAM_UART1_RecvBuffer_End_Addr 0x00012FFF +#define SRAM_UART1_SendBuffer_Start_Addr 0x00013000 +#define SRAM_UART1_SendBuffer_End_Addr 0x00013FFF + +#define SRAM_UART2_RecvBuffer_Start_Addr 0x00014000 +#define SRAM_UART2_RecvBuffer_End_Addr 0x00014FFF +#define SRAM_UART2_SendBuffer_Start_Addr 0x00015000 +#define SRAM_UART2_SendBuffer_End_Addr 0x00015FFF + +#define SRAM_UART3_RecvBuffer_Start_Addr 0x00016000 +#define SRAM_UART3_RecvBuffer_End_Addr 0x00016FFF +#define SRAM_UART3_SendBuffer_Start_Addr 0x00017000 +#define SRAM_UART3_SendBuffer_End_Addr 0x00017FFF +/**********SRAM Uartض - **********/ + +/*2022.12.26 ֿ޸Ŀʼ -- Ҫ޸ */ +/*豸״̬¼ 0x031400~0x031FFF 3Kÿ豸6ֽڣһܹܴ509豸*/ +#define SRAM_DEVICE_ONLINE_STATE_WRITE_ADDR 0x00031400 //豸״̬дַ +#define SRAM_DEVICE_ONLINE_STATE_READ_ADDR 0x00031404 //豸״̬ȡַ +#define SRAM_DEVICE_ONLINE_STATE_TEMP_ADDR 0x00031408 //豸״̬мַȡĵַ +#define SRAM_DEVICE_ONLINE_STATE_START_ADDR 0x00031410 //豸״̬ʼַʵʿʼдݵַ +//#define SRAM_DEVICE_ONLINE_STATE_END_ADDR 0x00031500 //豸״ַ̬ʵʽдݵַ - ʹ +#define SRAM_DEVICE_ONLINE_STATE_END_ADDR 0x00031FFE //豸״ַ̬ʵʽдݵַ +/*2022.12.26 ֿ޸Ľ*/ + +#define SRAM_CheckMap_List_Start_Addr 0x0003A800 //Ѳʼַ һ10K +#define SRAM_CheckMap_List_End_Addr 0x0003CFFF //Ѳַ + +#define SRAM_VCard_PortInf_Start_Addr 0x0003D000 //޿ȡ ӳ˿Ϣ ʼַ һ2K +#define SRAM_VCard_PortInf_End_Addr 0x0003D7FF //޿ȡ ӳ˿Ϣ ַ + +#define SRAM_VCard_ConNToS_Start_Addr 0x0003D800 //޿ȡ Ϣ ʼַ һ1K +#define SRAM_VCard_ConNToS_End_Addr 0x0003DBFF //޿ȡ Ϣ ַ + +#define SRAM_VCard_ConSToN_Start_Addr 0x0003DC00 //޿ȡ Ϣ ʼַ һ1K +#define SRAM_VCard_Con_End_Addr 0x0003DFFF //޿ȡ Ϣ ַ + +#define SRAM_VCard_DetectWin_Start_Addr 0x0003E000 //޿ȡ ⴰ״̬ ʼַ һ60K +#define SRAM_VCard_DetectWin_End_Addr 0x0004CFFF //޿ȡ ⴰ״̬ ַ + +#define SRAM_VCard_Property_Start_Addr 0x0004D000 //޿ȡ ʼַ һ1K +#define SRAM_VCard_Property_End_Addr 0x0004D3FF //޿ȡ ַ + +/**********SRAM洢ַ ض - ʼ**********/ +#define SRAM_IAP_APP_FILE_ADDRESS 0x00050000 //SRAMдAPPļĵַ - 218K + +#define SRAM_IAP_IP_ADDRESS 0x0008E600 //SRAMдʱõIP - 4Byte ʱUDPַſռ䣬ͬʱ͸UDPַ +#define SRAM_IAP_PORT_ADDRESS 0x0008E604 //SRAMдʱõport - 2Byte ʱUDPַſռ䣬ͬʱ͸UDPַ +#define SRAM_IAP_NET_UPGRADE_Flag_ADDRESS 0x0008E606 //SRAMд־λ - 1Byte +#define SRAM_IAP_UPGRADE_Reply_NUM_ADDRESS 0x0008E607 //SRAMдظɺAPPʼϱɼ - 1Byte + +/**********SRAM洢ַ ض - **********/ + +/**********ĿӳĴض - ʼ**********/ +#define SRAM_Register_Start_ADDRESS 0x0008E900 +#define SRAM_Register_End_ADDRESS 0x0008EFFF + +#define Register_OFFSET_LEN 0x0400 //ǰĴռ䳤 - ĿĴˣⳤҲӦñ仯 +//ĿĴƫƵַ +#define Register_NetIP_OFFSET 0x0000 //IPַ - DHCPɹ֮󣬻DHCPʧ֮ ʹõIPַ - PCMCUĬIP +#define Register_NetPort_OFFSET 0x0004 //ͨѶ˿ - PCñ +#define Register_NetMask_OFFSET 0x0008 // - PCñ +#define Register_NetGateway_OFFSET 0x000C // - PCñ +#define Register_DNSServerIP_OFFSET 0x0010 //DNSַ - PCñ +#define Register_NETMACKADDR_OFFSET 0x0014 //MACKַ +#define Register_WebServerIP_OFFSET 0x0018 //ƶ˷IPַ - PCõƶIPַ +#define Register_WebServerPort_OFFSET 0x001C //ƶ˷ͨѶ˿ - 2025-10-11 +#define Register_MandateExpiresTime_OFFSET 0x0020 //MCUȨʱ - Ȩ +#define Register_CurrentUsageTime_OFFSET 0x0024 //MCUǰʱ +#define Register_MandateUTC_OFFSET 0x0028 //Ȩʱ - ȨʱĵǰUTCʱ +#define Register_MandateLock_OFFSET 0x002C //Ȩ +#define Register_NetInfo_EN_OFFSET 0x0030 //ʹܣDHCPʹ - 1ByteʾDHCPʹ 1ByteǷIPΪĬIPַ - PCñ +#define Register_NetOfflineTime_OFFSET 0x0034 //жʱ - 4Byte λms +#define Register_ProjectCode_OFFSET 0x0038 //Ŀ +#define Register_SoftwareVersion_OFFSET 0x003C //汾 - ̼汾 +#define Register_ConfigVersion_OFFSET 0x0040 //ð汾 +#define Register_RoomNumber_OFFSET 0x0044 // +#define Register_HouseType_OFFSET 0x0048 // +#define Register_RoomRent_OFFSET 0x004C //̬Ϣ - ״̬ +#define Register_SeasonStatus_OFFSET 0x0050 //״̬ +#define Register_TFTPStatus_OFFSET 0x0054 //TFTP־ 4Byte +#define Register_TFTPUploadTime_OFFSET 0x0058 //TFTP־ϱʱ 4Byte +#define Register_BLVServerDmLen_OFFSET 0x005C //BLV 4Byte +#define Register_BLVServerDmName_OFFSET 0x0060 //BLV 64Byte +#define Register_UDPPeriodicTime_OFFSET 0x00A0 //UDPͨѶ ϱʱ 4Byte λ:ms + +#define Register_RoomNumNote_OFFSET 0x0100 //űעϢŵַռ - 16Byte +#define Register_RoomTypeNote_OFFSET 0x0110 //ͱעϢŵַռ - 16Byte +#define Register_RoomNote_OFFSET 0x0120 //䱸עϢŵַռ - 96Byte +#define Register_TFTPLOGPort_OFFSET 0x0180 //TFTP־˿ - 2Byte +#define Register_TFTPLOGTime_OFFSET 0x0182 //TFTP־ϴʱ - 2Byte +#define Register_TFTPDmLens_OFFSET 0x0184 //TFTP־ - 1Byte +#define Register_TFTPDmName_OFFSET 0x0185 //TFTP־ - 64Byte +/**********ĿӳĴض - **********/ + +/**********SRAMļ· ض - ʼ**********/ +#define SRAM_IAP_LOGIC_FILE_ADDRESS 0x00090000 //SRAM߼·ļ׵ַ + +#define SRAM_IAP_LOGIC_DataFlag_ADDRESS 0x00090000 //ļ־λ - 4Byte +#define SRAM_IAP_LOGIC_DataSize_ADDRESS 0x00090004 //ļ - 4Byte +#define SRAM_IAP_LOGIC_DataMD5_ADDRESS 0x00090008 //ļMD5Уֵ - 16Byte + +#define SRAM_IAP_LOGIC_DataStart_ADDRESS 0x00090200 +#define SRAM_IAP_LOGIC_DataEnd_ADDRESS 0x000FFFFF +/**********SRAMļ· ض - **********/ + +#define SRAM_DevAction_List_Size 0x0400 //ÿ豸ڵ洢ռС - ǰ豸ڵ +#define SRAM_DevAction_List_Start_Addr 0x00100000 //豸ʼַ һ960K +#define SRAM_DevAction_List_End_Addr 0x001EFFFF //豸ַ + +#define SRAM_BlwMap_List_Start_Addr 0x001F0000 //ӳʼַ һ32K +#define SRAM_BlwMap_List_End_Addr 0x001F7FFF //ӳַ + +#define SRAM_DevDly_List_Start_Addr 0x001F8000 //ʱ豸ʼַ һ32K +#define SRAM_DevDly_List_End_Addr 0x001FFFFF //ʱ豸ַ + + + + + +/**********־ռض - ʼ********* + * + * 2025-07-29 ޸SRAM洢ַ 0x00400000 ~ 0x007FFFFF SIZE:4MByte + * 1޸ĶԿռַУ飬ֹ쳣 + * 2־ȥûʹõı + * */ +#define SRAM_LOG_Start_Address 0x00400000 //־ռʼַ - ǰSRAM־ݵдַ - 4Byte +#define SRAM_TFTP_LOG_READ_Address 0x00400004 //TFTP־ϱȡַ - 4Byte +#define SRAM_FLASH_LOG_READ_Address 0x00400008 //Flash־дȡַ - 4Byte +#define SRAM_SD_LOG_READ_Start_Address 0x0040000C //SDȡʼַ - TFTPʼļʱͬʱǰʼֵַַñSDдLOGʹ - 4Byte +#define SRAM_SD_LOG_READ_End_Address 0x00400010 //SDȡַ - 4Byte +#define SRAM_Flash_Serial_Number 0x00400014 //־űַ - 1Byte +#define SRAM_LOGFlag_Reset_Source 0x00400018 //LauncherԴ - APPʹ +#define SRAM_LOGFlag_Addr_INIT 0x00400019 //Launcher¼ַSRAMʼ״̬־λ - APPʹ +#define SRAM_LOGFlag_Debug_Switch 0x0040001A //LauncherϢ 4Byte - APPʹ +#define SRAM_APPFlag_Reset_Source 0x0040001E //App־λ 2Byte - LauncherϢʹ 0xBBC1 +#define SRAM_LOG_DATA_Address 0x00400100 //־ݵַ +#define SRAM_LOG_End_Address 0x007FFFFF //־ռַ - 0x007FFFFF + +/**********־ռض - **********/ + + +#endif /* MCU_DRIVER_INC_SRAM_MEM_ADDR_H_ */ diff --git a/MCU_Driver/inc/timer.h b/MCU_Driver/inc/timer.h new file mode 100644 index 0000000..164b6a0 --- /dev/null +++ b/MCU_Driver/inc/timer.h @@ -0,0 +1,20 @@ +/* + * timer.h + * + * Created on: May 16, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_TIMER_H_ +#define MCU_DRIVER_INC_TIMER_H_ + +#include "ch564.h" + + +extern volatile uint32_t Time0_100us; +extern volatile uint32_t Time0_1ms; + +void TIMER0_Init(void); +void Timer0_Task(void); + +#endif /* MCU_DRIVER_INC_TIMER_H_ */ diff --git a/MCU_Driver/inc/uart.h b/MCU_Driver/inc/uart.h new file mode 100644 index 0000000..e9d5641 --- /dev/null +++ b/MCU_Driver/inc/uart.h @@ -0,0 +1,82 @@ +/* + * uart.h + * + * Created on: May 14, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_UART_H_ +#define MCU_DRIVER_INC_UART_H_ + +#include "ch564.h" + +#define Recv_2400_TimeOut 10 //ms +#define Recv_9600_TimeOut 5 //ms +#define Recv_115200_TimeOut 3 //ms + +#define USART_BUFFER_NUM 3 +#define USART_BUFFER_SIZE 100 + +#define MCU485_EN1_H +#define MCU485_EN1_L +#define MCU485_EN2_H +#define MCU485_EN2_L +#define MCU485_EN3_H +#define MCU485_EN3_L + +typedef uint8_t (*Uart_prt)(uint8_t *,uint16_t); + +typedef enum +{ + UART_0, + UART_1, + UART_2, + UART_3, + UART_MAX, +}UART_IDX; + +typedef struct{ + uint8_t RecvBuffer[USART_BUFFER_SIZE]; + uint8_t Receiving; + uint16_t RecvLen; + + uint32_t RecvTimeout; + uint32_t RecvIdleTiming; + + uint32_t TX_Buffer_WriteAddr; + uint32_t TX_Buffer_ReadAddr; + uint32_t RX_Buffer_WriteAddr; + uint32_t RX_Buffer_ReadAddr; +}__attribute__((packed)) UART_t; + +extern UART_t g_uart[UART_MAX]; + +void UARTx_Init(UART_IDX uart_id, uint32_t buad); +void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud); + +void UART0_RECEIVE(void); +void UART1_RECEIVE(void); +void UART2_RECEIVE(void); +void UART3_RECEIVE(void); + +uint8_t UART0_ChangeBaud(uint32_t baudrate); +uint8_t UART1_ChangeBaud(uint32_t baudrate); +uint8_t UART2_ChangeBaud(uint32_t baudrate); +uint8_t UART3_ChangeBaud(uint32_t baudrate); + +void Uart0_Flush(uint16_t over_time); +void Uart1_Flush(uint16_t over_time); +void Uart2_Flush(uint16_t over_time); +void Uart3_Flush(uint16_t over_time); + +void Uart_SendString(uint8_t uart_id,uint8_t* buff,uint16_t len); +void MCU485_SendString_1(uint8_t *buf, uint16_t len); +void MCU485_SendString_2(uint8_t *buf, uint16_t len); +void MCU485_SendString_3(uint8_t *buf, uint16_t len); +void MCU485_SendString(uint8_t uart_id,uint8_t* buff,uint16_t len); +void MCU485_SendSRAMData(uint8_t uart_id,uint32_t data_addr,uint16_t len); +void Write_Uart_SendBuff(uint8_t uart_id,uint8_t uart_outime,uint8_t* buff,uint16_t len); + + + +#endif /* MCU_DRIVER_INC_UART_H_ */ diff --git a/MCU_Driver/inc/watchdog.h b/MCU_Driver/inc/watchdog.h new file mode 100644 index 0000000..03553f7 --- /dev/null +++ b/MCU_Driver/inc/watchdog.h @@ -0,0 +1,15 @@ +/* + * watchdog.h + * + * Created on: Nov 12, 2025 + * Author: cc + */ + +#ifndef MCU_DRIVER_INC_WATCHDOG_H_ +#define MCU_DRIVER_INC_WATCHDOG_H_ + +void WDT_Init(void); +void WDT_Feed(void); +void WDT_Reinit(void); + +#endif /* MCU_DRIVER_INC_WATCHDOG_H_ */ diff --git a/MCU_Driver/led.c b/MCU_Driver/led.c new file mode 100644 index 0000000..7926513 --- /dev/null +++ b/MCU_Driver/led.c @@ -0,0 +1,33 @@ +/* + * led.c + * + * Created on: 2025515 + * Author: cc + */ + +#include "led.h" +#include "debug.h" +#include +#include + +__attribute__((section(".non_0_wait"))) void SYS_LED_Init(void) +{ + GPIOA_ModeCfg(GPIO_Pin_12,GPIO_ModeOut_PP); //LED + + SYS_LED_ON; +} + +__attribute__((section(".non_0_wait"))) void SYS_LED_Task(void) +{ + static uint32_t led_tick = 0; + + if(SysTick_1ms - led_tick >= 1000 ){ + led_tick = SysTick_1ms; + + SYS_LED_FLIP; + } +} + + + + diff --git a/MCU_Driver/log_api.c b/MCU_Driver/log_api.c new file mode 100644 index 0000000..64ce080 --- /dev/null +++ b/MCU_Driver/log_api.c @@ -0,0 +1,866 @@ +/***********************************־ݴ洢 - ṩͱú***************************************/ +#include "rw_logging.h" +#include "SPI_SRAM.h" +#include "Log_api.h" +#include "string.h" +#include "spi_flash.h" + +#include +#include +#include +#include + +uint32_t SYS_Log_Switch = (LogType_Launcher_SWITCH << LogType_Launcher_bit) + \ + (LogType_SYS_Record_SWITCH << LogType_SYS_Record_bit) + \ + (LogType_Device_COMM_SWITCH << LogType_Device_COMM_bit) + \ + (LogType_Device_Online_SWITCH << LogType_Device_Online_bit) + \ + (LogType_Global_Parameters_SWITCH << LogType_Global_Parameters_bit) + \ + (LogType_Net_COMM_SWITCH << LogType_Net_COMM_bit) + \ + (LogType_Logic_Record_SWITCH << LogType_Logic_Record_bit); + + +/******************************************************************************* +* Function Name : LOG_Launcher_APP_Check_Record +* Description : Launcher - УAPP +* Input : + state :״̬ + 0x00:ͬ + 0x01:ͬ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Launcher_APP_Check_Record(uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) ) + { + uint8_t temp_buff[3] = {0}; + + temp_buff[0] = LLauncher_App_Check; + temp_buff[1] = state; + + Log_write_sram(LogType_Launcher,temp_buff,2); + } +} + +/******************************************************************************* +* Function Name : LOG_Launcher_APP_Check_Record +* Description : Launcher - УAPP +* Input : + state :״̬ + 0x00:ɹ + 0x01:ʧ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Launcher_Read_App_Record(uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) ) + { + uint8_t temp_buff[3] = {0}; + + temp_buff[0] = LLauncher_Read_App; + temp_buff[1] = state; + + Log_write_sram(LogType_Launcher,temp_buff,2); + } +} + +/******************************************************************************* +* Function Name : LOG_Launcher_Write_Flash_Record +* Description : Launcher - Flashд +* Input : + addr :дַ + len :д볤 +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Launcher_Write_Flash_Record(uint32_t addr,uint16_t len) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) ) + { + uint8_t temp_buff[7] = {0}; + + temp_buff[0] = LLauncher_Write_Flash; + temp_buff[1] = addr & 0xFF; + temp_buff[2] = (addr >> 8) & 0xFF; + temp_buff[3] = (addr >> 16) & 0xFF; + temp_buff[4] = (addr >> 24) & 0xFF; + temp_buff[5] = len & 0xFF; + temp_buff[6] = (len >> 8) & 0xFF; + + Log_write_sram(LogType_Launcher,temp_buff,7); + } +} + +/******************************************************************************* +* Function Name : LOG_Launcher_Factory_Reset_Record +* Description : Launcher - ָ +* Input : +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Launcher_Factory_Reset_Record(void) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Launcher_bit )) ) + { + uint8_t temp_buff[3] = {0}; + + temp_buff[0] = LLauncher_Factory_Reset; + temp_buff[1] = 0x00; + + Log_write_sram(LogType_Launcher,temp_buff,2); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_PHY_Change_Record +* Description : SYS_Record - PHY״̬¼ +* Input : + state :״̬ + 0x00:γ + 0x01: + 0x02:TCPʱ + 0x03:TCPϿ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_PHY_Change_Record(uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[3] = {0}; + + temp_buff[0] = LSYS_PHY_Change; + temp_buff[1] = state; + + Log_write_sram(LogType_SYS_Record,temp_buff,2); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_DevInfo_Error_Record +* Description : SYS_Record - 豸ȡϢ¼ +* Input : + dev :豸 + addr :豸ַ + info_addr :豸Ϣ洢ַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_DevInfo_Error_Record(uint8_t dev,uint8_t addr,uint32_t info_addr) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[8] = {0}; + + temp_buff[0] = LSYS_DevInfo_Error; + temp_buff[1] = dev; + temp_buff[2] = addr; + temp_buff[3] = info_addr & 0xFF; + temp_buff[4] = (info_addr >> 8) & 0xFF; + temp_buff[5] = (info_addr >> 16) & 0xFF; + temp_buff[6] = (info_addr >> 24) & 0xFF; + + Log_write_sram(LogType_SYS_Record,temp_buff,7); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_API_State_Record +* Description : SYS_Record - API״̬¼ +* Input : + API_way :ʽ + 0x01: + 0x02: + state :״̬ + 0x01:дɹ + 0x02:дʧ + 0x03:ļ + 0x04:MD5У + 0x05:CRCУ + 0x06:תLauncher +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_API_State_Record(uint8_t API_way,uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[8] = {0}; + uint8_t temp_len = 0; + + temp_buff[temp_len++] = LSYS_API_State; + temp_buff[temp_len++] = API_way; + temp_buff[temp_len++] = state; + + Log_write_sram(LogType_SYS_Record,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_NET_Argc_Record +* Description : SYS_Record - ¼ +* Input : + IP :ǰIPַ - 4Byte + MAC :ǰMACַ - 4Byte + DNS_IP1 :DNSIP1 - ƶ˷ - 4Byte + DNS_IP2 :DNSIP2 - TFTP - 4Byte + DNS_IP3 :DNSIP3 - MQTT - 4Byte +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_NET_Argc_Record(uint8_t *IP,uint8_t *MAC,uint8_t *DNS_IP1,uint8_t *DNS_IP2,uint8_t *DNS_IP3) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[40] = {0}; + uint8_t temp_len = 0; + + temp_buff[temp_len++] = LSYS_NET_ARGC; + temp_buff[temp_len++] = IP[0]; + temp_buff[temp_len++] = IP[1]; + temp_buff[temp_len++] = IP[2]; + temp_buff[temp_len++] = IP[3]; + + temp_buff[temp_len++] = MAC[0]; + temp_buff[temp_len++] = MAC[1]; + temp_buff[temp_len++] = MAC[2]; + temp_buff[temp_len++] = MAC[3]; + temp_buff[temp_len++] = MAC[4]; + temp_buff[temp_len++] = MAC[5]; + + temp_buff[temp_len++] = DNS_IP1[0]; + temp_buff[temp_len++] = DNS_IP1[1]; + temp_buff[temp_len++] = DNS_IP1[2]; + temp_buff[temp_len++] = DNS_IP1[3]; + + temp_buff[temp_len++] = DNS_IP2[0]; + temp_buff[temp_len++] = DNS_IP2[1]; + temp_buff[temp_len++] = DNS_IP2[2]; + temp_buff[temp_len++] = DNS_IP2[3]; + + temp_buff[temp_len++] = DNS_IP3[0]; + temp_buff[temp_len++] = DNS_IP3[1]; + temp_buff[temp_len++] = DNS_IP3[2]; + temp_buff[temp_len++] = DNS_IP3[3]; + + Log_write_sram(LogType_SYS_Record,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_MQTT_Argc_Record +* Description : SYS_Record - MQTT¼ +* Input : + productkey :ƷԿ - 12Byte + devname :豸 - 65Byte + devsecret :豸Կ - 33Byte + publish :ַ - 65Byte + sublish :ĵַ - 65Byte +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_MQTT_Argc_Record(uint8_t *productkey,uint8_t *devname,uint8_t *devsecret,uint8_t *publish,uint8_t *sublish) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LSYS_MQTT_ARGC; + + for(uint8_t i=0;i<12;i++) + { + Temp_Flash_Buff[temp_len++] = productkey[i]; + } + + for(uint8_t i=0;i<65;i++) + { + Temp_Flash_Buff[temp_len++] = devname[i]; + } + + for(uint8_t i=0;i<33;i++) + { + Temp_Flash_Buff[temp_len++] = devsecret[i]; + } + + for(uint8_t i=0;i<65;i++) + { + Temp_Flash_Buff[temp_len++] = publish[i]; + } + + for(uint8_t i=0;i<65;i++) + { + Temp_Flash_Buff[temp_len++] = sublish[i]; + } + + Log_write_sram(LogType_SYS_Record,Temp_Flash_Buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_Server_Comm_State_Record +* Description : SYS_Record - ƶͨѶ״̬¼ +* Input : + state :״̬ + 0x00: + 0x01: +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_Server_Comm_State_Record(uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[8] = {0}; + uint8_t temp_len = 0; + + temp_buff[temp_len++] = LSYS_Server_Comm_State; + temp_buff[temp_len++] = state; + + Log_write_sram(LogType_SYS_Record,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_NET_Argc_Record +* Description : SYS_Record - ʼǰ¼ +* Input : + IP :ĬIPַ - 4Byte + Gateway :Ĭصַ - 4Byte + IP_Mask :Ĭ - 4Byte + DNS_Add :DNSַ - 4Byte + ArgcFlag :־ - 1Byte + DHCPFlag :DHCPʹܱ־ - 1Byte + ServerFlag :־ - 1Byte +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_NET_Argc_Init_Record(uint8_t *IP,uint8_t *Gateway,uint8_t *IP_Mask,uint8_t *DNS_Add,uint8_t ArgcFlag,uint8_t DHCPFlag,uint8_t ServerFlag) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[40] = {0}; + uint8_t temp_len = 0; + + temp_buff[temp_len++] = LSYS_NET_DefaultARGC; + temp_buff[temp_len++] = IP[0]; + temp_buff[temp_len++] = IP[1]; + temp_buff[temp_len++] = IP[2]; + temp_buff[temp_len++] = IP[3]; + + temp_buff[temp_len++] = Gateway[0]; + temp_buff[temp_len++] = Gateway[1]; + temp_buff[temp_len++] = Gateway[2]; + temp_buff[temp_len++] = Gateway[3]; + + temp_buff[temp_len++] = IP_Mask[0]; + temp_buff[temp_len++] = IP_Mask[1]; + temp_buff[temp_len++] = IP_Mask[2]; + temp_buff[temp_len++] = IP_Mask[3]; + + temp_buff[temp_len++] = DNS_Add[0]; + temp_buff[temp_len++] = DNS_Add[1]; + temp_buff[temp_len++] = DNS_Add[2]; + temp_buff[temp_len++] = DNS_Add[3]; + + temp_buff[temp_len++] = ArgcFlag; + temp_buff[temp_len++] = DHCPFlag; + temp_buff[temp_len++] = ServerFlag; + + Log_write_sram(LogType_SYS_Record,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_SYS_NET_Argc_Record +* Description : SYS_Record - ʼǰ¼ +* Input : + state״̬ + 0x01㰴 + 0x02 + 0x03ɿ + 0x04ﵽָ״̬ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_SYS_RCUKey_State_Record(uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_SYS_Record_bit )) ) + { + uint8_t temp_buff[5] = {0}; + uint8_t temp_len = 0; + + temp_buff[temp_len++] = LSYS_RCUKey_State; + temp_buff[temp_len++] = state; + + Log_write_sram(LogType_SYS_Record,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_Device_COMM_ASK_TO_Reply_Record +* Description : Device_COMM - RCUѯظ仯ݼ¼ +* Input : + port :˿ں + baud :ͨѶ + data_tick :ѯʱ + buff : + len :ݳ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Device_COMM_ASK_TO_Reply_Record(uint8_t port,uint32_t baud,uint32_t data_tick,uint8_t *buff,uint16_t len) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Device_COMM_bit )) ) + { + uint16_t buff_len = len ; + if(buff_len >= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_ASK_TO_Reply; + Temp_Flash_Buff[temp_len++] = port; + Temp_Flash_Buff[temp_len++] = baud & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 8) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 16) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 24) & 0xFF; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_ASK_TO_Reply; + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(port_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 1); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 2); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 3); + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_Send_Control; + Temp_Flash_Buff[temp_len++] = port; + Temp_Flash_Buff[temp_len++] = baud & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 8) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 16) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 24) & 0xFF; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_Send_Control; + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(port_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 1); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 2); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 3); + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_Control_Reply; + Temp_Flash_Buff[temp_len++] = port; + Temp_Flash_Buff[temp_len++] = baud & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 8) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 16) & 0xFF; + Temp_Flash_Buff[temp_len++] = (baud >> 24) & 0xFF; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_Control_Reply; + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(port_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 1); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 2); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 3); + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LCOMM_Control_Reply; + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(port_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 1); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 2); + Temp_Flash_Buff[temp_len++] = SRAM_Read_Byte(baud_addr + 3); + + for(uint16_t i=0;i> 8) & 0xFF; + temp_buff[temp_len++] = (baud >> 16) & 0xFF; + temp_buff[temp_len++] = (baud >> 24) & 0xFF; + temp_buff[temp_len++] = way; + temp_buff[temp_len++] = fail_num; + temp_buff[temp_len++] = sum; + temp_buff[temp_len++] = num; + + + Log_write_sram(LogType_Device_COMM,temp_buff,temp_len); + } +} + +__attribute__((section(".non_0_wait"))) void LOG_Device_COMM_Adjust_Baud_Record2(uint32_t dev_type,uint32_t dev_addr,uint32_t baud_addr) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Device_COMM_bit )) ) + { + uint8_t temp_buff[8]; + uint16_t temp_len = 0; + + memset(temp_buff,0,sizeof(temp_buff)); + + temp_buff[temp_len++] = LCOMM_Adjust_Baud; + temp_buff[temp_len++] = SRAM_Read_Byte(dev_type); + temp_buff[temp_len++] = SRAM_Read_Byte(dev_addr); + temp_buff[temp_len++] = SRAM_Read_Byte(baud_addr); + temp_buff[temp_len++] = SRAM_Read_Byte(baud_addr + 1); + temp_buff[temp_len++] = SRAM_Read_Byte(baud_addr + 2); + temp_buff[temp_len++] = SRAM_Read_Byte(baud_addr + 3); + + Log_write_sram(LogType_Device_COMM,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_Device_Online_Record +* Description : Device_Online - 豸߼¼ +* Input : + dev :豸 + addr :豸ַ + state :豸״̬ - 0x00ߣ0x01豸 +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Device_Online_Record(uint8_t dev,uint8_t addr,uint8_t state) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Device_Online_bit )) ) + { + uint8_t temp_buff[6]; + uint16_t temp_len = 0; + + memset(temp_buff,0,sizeof(temp_buff)); + + temp_buff[temp_len++] = dev; + temp_buff[temp_len++] = addr; + temp_buff[temp_len++] = state; + + Log_write_sram(LogType_Device_Online,temp_buff,temp_len); + } +} + +/******************************************************************************* +* Function Name : LOG_Global_ParaInfo_Record +* Description : Global_Parameters - ȫֲ¼ 10Ӽ¼ +* Input : + buff :豸 + len :豸ַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOG_Global_ParaInfo_Record(uint8_t *buff,uint16_t len) +{ + if(LogType_Enable && (SYS_Log_Switch & (1 << LogType_Global_Parameters_bit )) ) + { + uint16_t buff_len = len ; + if(buff_len >= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LGlobal_Para; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LGlobal_Dev; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LNetComm_Send; + Temp_Flash_Buff[temp_len++] = SocketId; + Temp_Flash_Buff[temp_len++] = ip[0]; + Temp_Flash_Buff[temp_len++] = ip[1]; + Temp_Flash_Buff[temp_len++] = ip[2]; + Temp_Flash_Buff[temp_len++] = ip[3]; + Temp_Flash_Buff[temp_len++] = (port) & 0xFF; + Temp_Flash_Buff[temp_len++] = (port >> 8) & 0xFF; + + for(uint16_t i=0;i= 512) buff_len = 512; //¼512Byte + + uint16_t temp_len = 0; + + memset(Temp_Flash_Buff,0,sizeof(Temp_Flash_Buff)); + + Temp_Flash_Buff[temp_len++] = LNetComm_Recv; + Temp_Flash_Buff[temp_len++] = SocketId; + Temp_Flash_Buff[temp_len++] = ip[0]; + Temp_Flash_Buff[temp_len++] = ip[1]; + Temp_Flash_Buff[temp_len++] = ip[2]; + Temp_Flash_Buff[temp_len++] = ip[3]; + Temp_Flash_Buff[temp_len++] = (port) & 0xFF; + Temp_Flash_Buff[temp_len++] = (port >> 8) & 0xFF; + + for(uint16_t i=0;i +#include + +/******************************************************************************* +* Function Name : DevAction_CondData_Init +* Description : ݳʼ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_CondData_Init(void) +{ + DevActionGlobal.DevActionU64Cond.RcuLockState = Get_Authorize_Lock_Status(); +} + +/******************************************************************************* +* Function Name : Action_Coord_Get +* Description : ±õ +* Input : + Dev_processing_addr :豸ڵַ + BUS_Public : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Action_Coord_Get(uint32_t Dev_processing_addr, Device_Public_Information_G *BUS_Public) +{ + uint16_t i; + uint32_t DevActionAddr; + + for(i = 0; i < DevActionGlobal.DevActionNum; i++) // + { + DevActionAddr = SRAM_DevAction_List_Start_Addr + i*SRAM_DevAction_List_Size; + + if(SRAM_Read_DW(DevActionAddr+sizeof(Dev_Action_Core)+sizeof(Dev_Action_Input)+sizeof(Dev_Action_Cond)+sizeof(Dev_Action_State)-4) == Dev_processing_addr) + { + BUS_Public->ActionCoord = i; //ǰһڵ豸ڵһµĶ + break; + } + } +} + +/******************************************************************************* +* Function Name : Action_Coord_Get +* Description : 豸±õ +* Input : + Dev_processing_addr :豸ڵַ + BUS_Public : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Dev_Coord_Get(void) +{ + uint16_t i; //豸 + uint32_t Dev_processing_addr; + Device_Public_Information_G BUS_Public; //ȫ + + for(i = 0; i < DevActionGlobal.DevNum; i++) + { + Dev_processing_addr = SRAM_Device_List_Start_Addr + i*SRAM_Device_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), Dev_processing_addr); //й + BUS_Public.DevCoord = i; //õ豸± + Action_Coord_Get(Dev_processing_addr, &BUS_Public); //õ± + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ豸׼±,ַ:%08X豸:%d豸ַ:%d豸±:%d±:%d", Dev_processing_addr, BUS_Public.type, BUS_Public.addr, BUS_Public.DevCoord, BUS_Public.ActionCoord); + switch(BUS_Public.type) + { + case Dev_Host_HVout: //Ϊ̵ + if((ENUM_RS485_DEV_PRO_01 == BUS_Public.Protocol)&&(0x00 == BUS_Public.addr)) //1Э ַΪ0 + { +// NOR_HVOUT_INFO DevHVoutInfo; //̵ֲ +// SRAM_DMA_Read_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),Dev_processing_addr+Dev_Privately); +// +// DevHVoutInfo.DevC5IOAddr = Find_AllDevice_List_Information(DEV_C5IO_Type, 0x00); //õC5IO洢ַ +// Dbg_Println(DBG_BIT_DEVICE_STATUS_bit,"DevHVoutInfo.DevC5IOAddr:%08X", DevHVoutInfo.DevC5IOAddr); +// SRAM_DMA_Write_Buff((uint8_t *)&DevHVoutInfo,sizeof(NOR_HVOUT_INFO),Dev_processing_addr+Dev_Privately); //̵˽д + } + break; + } + /*±浱ǰ豸*/ + BUS_Public.check = 0x00; + SRAM_Write_Byte(BUS_Public.check, Dev_processing_addr+Dev_Check); //У + SRAM_Write_Word(BUS_Public.DevCoord, Dev_processing_addr+Dev_Coord); //д豸± + SRAM_Write_Word(BUS_Public.ActionCoord, Dev_processing_addr+Dev_ActionCoord); //д붯± + + BUS_Public.check = Log_CheckSum(Dev_processing_addr,BUS_Public.data_len); //¼У DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_Write_Byte(BUS_Public.check, Dev_processing_addr+Dev_Check); //дУ + } +} + +/******************************************************************************* +* Function Name : DevAction_ReuseFlag_Get +* Description : Ϊöñ־õ +* ÿеĶ ͬڵͻ·öĸñ־һһɨ趯ʱж +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void DevAction_ReuseFlag_Get(void) +{ + uint16_t i = 0x00,j = 0x00,k = 0x00; //ڱж + uint32_t list_addri = 0x00,list_addrj = 0x00; + DEV_ACTION_INFO DevActionInfoi; //ǰ豸ȫϢ + DEV_ACTION_INFO DevActionInfoj; //ǰ豸ȫϢ + + for(i = 0; i < DevActionGlobal.DevActionNum; i++) + { + list_addri = SRAM_DevAction_List_Start_Addr + i * SRAM_DevAction_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfoi, sizeof(DEV_ACTION_INFO), list_addri); + DevActionInfoi.DevActionState.DevAddrIn = Find_AllDevice_List_Information(DevActionInfoi.DevActionInput.DevType, DevActionInfoi.DevActionInput.DevAddr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ豸:%d豸:%d豸ַ:%d,豸ַ:%04x", + DevActionInfoi.DevCtrlNum, + DevActionInfoi.DevActionInput.DevType, + DevActionInfoi.DevActionInput.DevAddr, + DevActionInfoi.DevActionState.DevAddrIn); + + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit,"ǰݴӡ:",(uint8_t *)&DevActionInfoi,sizeof(Dev_Action_Core) + sizeof(Dev_Action_Input)+sizeof(Dev_Action_Cond)+sizeof(Dev_Action_State)); + + for(j = 0; j < DevActionGlobal.DevActionNum ; j++) + { + if( j != i ) + { + list_addrj = SRAM_DevAction_List_Start_Addr + j * SRAM_DevAction_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfoj, sizeof(DEV_ACTION_INFO), list_addrj); + if( ( DevActionInfoi.DevActionCond.DevActionU64Cond.DevActionOutFlag == 0x00 ) + && ( DevActionInfoj.DevActionCond.DevActionU64Cond.DevActionOutFlag == 0x00 ) + && ( DevActionInfoi.DevActionInput.DevType == DevActionInfoj.DevActionInput.DevType ) + && ( DevActionInfoi.DevActionInput.DevAddr == DevActionInfoj.DevActionInput.DevAddr ) + && ( DevActionInfoi.DevActionInput.inAddr == DevActionInfoj.DevActionInput.inAddr ) + && ( DevActionInfoi.DevActionInput.inType == DevActionInfoj.DevActionInput.inType ) ) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰַ:%08X֮ǰַ:%08X", list_addri, list_addrj); + DevActionInfoi.DevActionState.SceneReuseFlag = 0x01; + if( (DevActionInfoi.DevActionInput.DevType == DEV_RS485_SWT) + && (DevActionInfoi.DevActionCond.SceneExcute == ACTION_SCENE_MULTI) + && (DevActionInfoj.DevActionInput.DevType == DEV_RS485_SWT) + && (DevActionInfoj.DevActionCond.SceneExcute == ACTION_SCENE_MULTI) ) + { + if( j > i ) + { + if( (DevActionInfoi.DevActionState.MultiValidNo == 0x00) + && (DevActionInfoi.DevActionState.MultiSetFlag == 0x00) ) + { + DevActionInfoi.DevActionState.MultiSetFlag = 0x01; + DevActionInfoi.DevActionState.MultiNumber = 0x01; + DevActionInfoi.DevActionState.MultiValidNo++; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d ·:%d ʼַ:%08X ±:%d", + DevActionInfoi.DevActionInput.DevAddr, + DevActionInfoi.DevActionInput.inAddr, + list_addri, + DevActionInfoi.DevActionState.MultiNumber); + } + + if(DevActionInfoj.DevActionState.MultiSetFlag == 0x00) + { + Device_Public_Information_G BUS_Public; + RS485_SWI_INFO Rs485SwiInfo; + uint32_t DevAdd = 0x00; + + DevActionInfoi.DevActionState.MultiValidNo++; + DevActionInfoj.DevActionState.MultiNumber = DevActionInfoi.DevActionState.MultiValidNo; + DevActionInfoj.DevActionState.MultiSetFlag = 0x01; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d ·:%d ǰַ:%08X ±:%d", + DevActionInfoj.DevActionInput.DevAddr, + DevActionInfoj.DevActionInput.inAddr, + list_addrj, + DevActionInfoj.DevActionState.MultiNumber); + + //Ż + for(k = 0; k < SRAM_DevAction_List_Size; k++) + { + SRAM_Write_Byte(0x00,list_addrj+k); + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ϊ±λ׼±,ַ:%08X", list_addrj); + DevActionInfoj.CheckVal = 0x00; + SRAM_DMA_Write_Buff((uint8_t *)&DevActionInfoj, DevActionInfoj.data_len, list_addrj); + DevActionInfoj.CheckVal = DevAction_CheckSum(list_addrj,DevActionInfoj.data_len); + SRAM_Write_Byte(DevActionInfoj.CheckVal, ( list_addrj + sizeof(Dev_Action_Core) + sizeof(Dev_Action_Input) + sizeof(Dev_Action_Cond) + sizeof(Dev_Action_State) ) ); + + DevAdd = Find_AllDevice_List_Information2(Active_Port, DevActionInfoi.DevActionInput.DevType, DevActionInfoi.DevActionInput.DevAddr); + if(DevAdd != 0x00) + { + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public,sizeof(Device_Public_Information_G),DevAdd); + SRAM_DMA_Read_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately); + if(DevActionInfoi.DevActionState.MultiValidNo <= 127) + { + Rs485SwiInfo.MultiValidNo[DevActionInfoi.DevActionInput.inAddr] = DevActionInfoi.DevActionState.MultiValidNo; + } + + BUS_Public.check = 0x00; + BUS_Public.check = DoubleData_CheckSum((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), (uint8_t *)&Rs485SwiInfo, sizeof(RS485_SWI_INFO)); + SRAM_DMA_Write_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G),DevAdd); + SRAM_DMA_Write_Buff((uint8_t *)&Rs485SwiInfo,sizeof(RS485_SWI_INFO),DevAdd+Dev_Privately); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%d ,·:%d Ч:%d", + DevActionInfoi.DevActionInput.DevAddr, + DevActionInfoi.DevActionInput.inAddr, + Rs485SwiInfo.MultiValidNo[DevActionInfoi.DevActionInput.inAddr]); + } + } + } + }else { + break; + } + } + } + } + + for( k = 0; k < DevActionInfoi.DevCtrlNum; k++ ) + { + if(DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevType == Dev_Host_Invalid) //Ψг + { + DevActionInfoi.DevActionOutput[k].DevActionOutAddr = DevAction_No_Get(DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ,ַ:%08X ַ:%08X ±:%d ·:%d", + list_addri, + DevActionInfoi.DevActionOutput[k].DevActionOutAddr, + i, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop); + }else { + + DevActionInfoi.DevActionOutput[k].DevActionOutAddr = Find_AllDevice_List_Information( + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevType, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevAddr); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"չ豸:%dչ豸ַ:%d,չ豸·ַ:%d,չ豸洢ַ:%04x", + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevType, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop, + DevActionInfoi.DevActionOutput[k].DevActionOutAddr); + + } + + if(DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevDlyValue.DelayCont != 0x00) + { + DevActionInfoi.DevActionOutput[k].DevDlyAddr = Add_DevDly_To_List( + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevType, + DevActionInfoi.DevActionOutput[k].DevActionOutAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop); + + if(Dev_Host_Invalid != DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevType) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰʱ豸׼±,ַ:%08X ±:%d,ʱڵ:%08X 漰ʱ豸ַ:%08X, ·:%d", + list_addri, + i, + DevActionInfoi.DevActionOutput[k].DevDlyAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop); + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰʱ׼±,ַ:%08X ±:%d,ʱڵ:%08X 漰ʱ豸ַ:%08X, ·:%d", + list_addri, + i, + DevActionInfoi.DevActionOutput[k].DevDlyAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutAddr, + DevActionInfoi.DevActionOutput[k].DevActionOutCfg.DevOutputLoop); + } + }else { + DevActionInfoi.DevActionOutput[k].DevDlyAddr = 0x00; //չ豸δʱģʱڵ㡣±ٸֵʱ豸Ϣ + } + } + + for(k = 0; k < SRAM_DevAction_List_Size; k++) + { + SRAM_Write_Byte(0x00,list_addri+k); + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰΪñ־λ׼±,ַ:%08X", list_addri); + DevActionInfoi.CheckVal = 0x00; + SRAM_DMA_Write_Buff((uint8_t *)&DevActionInfoi, DevActionInfoi.data_len, list_addri); //д + + DevActionInfoi.CheckVal = DevAction_CheckSum(list_addri,DevActionInfoi.data_len); //У + + SRAM_Write_Byte(DevActionInfoi.CheckVal,(list_addri + sizeof(Dev_Action_Core) + sizeof(Dev_Action_Input) + sizeof(Dev_Action_Cond) + sizeof(Dev_Action_State)) ); //Уֵд + } +} + +/******************************************************************************* +* Function Name : Expand_Scene_Get +* Description : ΪƳ豸еַõ +* ʼԼʱ֮±ÿеÿչ豸иֵ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Expand_Scene_Get(void) +{ + uint8_t KeepFlag = 0,CtrlWay = 0; + uint16_t i = 0,j = 0; + uint32_t list_addr = 0; + DEV_ACTION_INFO DevActionInfo; + + for(i = 0; i < DevActionGlobal.DevActionNum; i++ ) + { + KeepFlag = 0x00; + list_addr = SRAM_DevAction_List_Start_Addr + i*SRAM_DevAction_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&DevActionInfo, sizeof(DEV_ACTION_INFO), list_addr); + + for(j = 0; j < DevActionInfo.DevCtrlNum; j++) + { + if( DevActionInfo.DevActionOutput[j].DevActionOutCfg.DevType == Dev_Host_Invalid ) + { + DevActionInfo.DevActionOutput[j].DevActionOutAddr = DevAction_No_Get(DevActionInfo.DevActionOutput[j].DevActionOutCfg.DevOutputLoop); + if( DevActionInfo.DevActionOutput[j].DevActionOutAddr != 0x00 ) + { + KeepFlag = 0x01; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ׼±,ַ:%08X ַ:%08X ±:%d ·:%d", + list_addr,DevActionInfo.DevActionOutput[j].DevActionOutAddr, + i, + DevActionInfo.DevActionOutput[j].DevActionOutCfg.DevOutputLoop); + } + } + + switch(DevActionInfo.DevActionOutput[i].DevActionOutCfg.DevType) + { + case DEV_RS485_SWT: + case Dev_Host_LVoutput: + CtrlWay = DevActionInfo.DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00ff; //ִзʽ + switch(CtrlWay) + { + case DEV_CTRLWAY_RELATESCENE: //Ӧ + case CFG_Dev_CtrlWay_Is_RelateBlink: //Ӧ˸ + DevActionInfo.DevActionState.SceneTypeFlag = 0x01; + KeepFlag = 0x01; //ǰҪ± + break; + } + break; + case Dev_NodeCurtain: + if(DEV_CTRLWAY_RELATESCENE == (DevActionInfo.DevActionOutput[i].DevActionOutCfg.DevCtrlState & 0x00ff)) + { + KeepFlag = 0x01; //ǰҪ± + DevActionInfo.DevActionState.SceneTypeFlag = 0x01; + } + break; + } + + switch(DevActionInfo.DevActionCond.SceneExcute) + { + case ACTION_SCENE_TWO: + case ACTION_SCENE_SLEEP: + case ACTION_SCENE_MAINSWITCH: + case ACTION_SCENE_HELPSLEEP: + KeepFlag = 0x01; //ǰҪ± + DevActionInfo.DevActionState.SceneTypeFlag = 0x01; + break; + } + } + + if( KeepFlag == 0x01 ) + { + for(uint16_t k = 0;k 0x70000)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"߼ļȲ:%08X",file_len); + return 0x01; + } + + MD5Digest_FLASH(SPIFLASH_LOGIC_DataStart_ADDRESS, file_len,(char *)&md5[0]); + + if(0==strncmp((const char *)md5,(const char *)&file_info[8],16)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"MD5Уɹ!"); + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"MD5У󣬲 Len:%08X",file_len); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʧܣMd5:%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X%02X,%02X,%02X,%02X,%02X,%02X",md5[0],md5[1],md5[2],md5[3],md5[4],md5[5],md5[6],md5[7],md5[8],md5[9],md5[10],md5[11],md5[12],md5[13],md5[14],md5[15]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"File Md5:%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X",\ + file_info[8],file_info[9],\ + file_info[10],file_info[11],\ + file_info[12],file_info[13],\ + file_info[14],file_info[15],\ + file_info[16],file_info[17],\ + file_info[18],file_info[19],\ + file_info[21],file_info[21],\ + file_info[22],file_info[23]); + + /*Flashеļ־λMD5ֵ*/ + memset(file_info,0,sizeof(file_info)); + Flash_Write(file_info,24,SPIFLASH_LOGIC_DataFlag_ADDRESS); + + return 0x01; + } + + if((Flash_read_Byte(SPIFLASH_LOGIC_DataStart_ADDRESS+Logic_D_Hear_L) == 0xCC) && (Flash_read_Byte(SPIFLASH_LOGIC_DataStart_ADDRESS+Logic_D_Hear_H) == 0xC0)) + { + uint8_t temp_data[4]; + uint16_t temp_len = 0; + Flash_Read(temp_data,4,SPIFLASH_LOGIC_DataStart_ADDRESS+Logic_D_Len_L); + temp_len = temp_data[1]; + temp_len <<= 8; + temp_len |= temp_data[0]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ҵļȡݳ:%d",temp_len); + if((temp_len <= file_len) && (temp_len <= 1024)) //Ŀǰ1024 + { + uint16_t temp_crc = 0,data_crc = 0; + uint16_t data_frame = 0,data_sn = 0; + uint8_t temp_buff[temp_len]; + memset(temp_buff,0,sizeof(temp_buff)); + + Flash_Read(temp_buff,temp_len,SPIFLASH_LOGIC_DataStart_ADDRESS); + temp_crc = NetCRC16_Data(temp_buff ,temp_len,Logic_D_CRC_L); + + data_crc = temp_buff[Logic_D_CRC_H]; + data_crc <<= 8; + data_crc |= temp_buff[Logic_D_CRC_L]; + + if(data_crc == temp_crc) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"CRCУɹ"); + + data_frame = temp_buff[Logic_D_FrameNum_H]; + data_frame <<= 8; + data_frame |= temp_buff[Logic_D_FrameNum_L]; + + data_sn = temp_buff[Logic_D_Frame_H]; + data_sn <<= 8; + data_sn |= temp_buff[Logic_D_Frame_L]; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Logic Data SN:%d,NUM:%d",data_sn,data_frame); + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit,"߼֡" ,temp_buff,temp_len); + + if(temp_buff[Logic_D_FrameType] == Logic_FrameType_LogicInfo) + { + switch(select) + { + case 0x00: //ѯȫϢ + memcpy(buff,&temp_buff[Logic_D_Para],LogicFile_InfoDetails_Len); + rev = 0x00; + break; + case 0x01: //ѯ - 32Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_InfoDetails_Author_Offset],32); + rev = 0x00; + break; + case 0x02: //ѯ汾 - 4Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_SWVersion_Offset],4); + rev = 0x00; + break; + case 0x03: //ѯʱ - 7Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_ReleaseDate_Offset],7); + rev = 0x00; + break; + case 0x04: //ѯƵ - 32Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_HotelName_Offset],32); + rev = 0x00; + break; + case 0x05: //ѯƵ - 4Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_HotelCode_Offset],4); + rev = 0x00; + break; + case 0x06: //ѯĿ - 32Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_HotelGroupName_Offset],32); + rev = 0x00; + break; + case 0x07: //ѯͱ - 32Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_HomeName_Offset],32); + rev = 0x00; + break; + case 0x08: //ѯ汾 - 3Byte + memcpy(buff,&temp_buff[Logic_D_Para + LogicFile_Infodetails_Version_Offset],3); + rev = 0x00; + break; + } + } + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"CRCУʧ!"); + } + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ȡݳȲڷΧ:%08X - %d",temp_len); + } + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"߼ļݰͷ!%02X %02X",Flash_read_Byte(SPIFLASH_LOGIC_DataStart_ADDRESS+Logic_D_Hear_L) , Flash_read_Byte(SPIFLASH_LOGIC_DataStart_ADDRESS+Logic_D_Hear_H)); + } + + return rev; +} + +/******************************************************************************* +* Function Name : Logic_FrameType_Global_TempProcessing +* Description : ߼ļ - ȫϢ ʱ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_Global_TempProcessing(uint8_t *data,uint16_t len) +{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); +} + +/******************************************************************************* +* Function Name : Logic_FrameType_DeviceAction_TempProcessing +* Description : ߼ļ - 豸Э֧ж +* Input : +* Return : + 0x00 :жӦЭ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Logic_DeviceType_Legal_Judgment(LOGICFILE_DEVICE_INFO *dev_info) +{ + uint8_t rev = 0x01; + + switch(dev_info->type) + { + case Dev_Host_Invalid: // + if((dev_info->version == 0x00) && (dev_info->port == 0x00)) rev = 0x00; + break; + case Dev_Host_HVout: //ǿ̵ + if((dev_info->version == 0x01) && (dev_info->port == Bus_port)) rev = 0x00; //BLV_Cx̵ + else if((dev_info->version == 0x02) && (dev_info->port == Polling_Port)) rev = 0x00; //A9IO̵ + else if((dev_info->version == 0x03) && (dev_info->port == Active_Port)) rev = 0x00; //ǿ翪 + break; + case Dev_Host_LVinput: // + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //BLV_Cx - ͨ豸 + else if((dev_info->version == 0x02) && (dev_info->port == Polling_Port)) rev = 0x00; //485Ӧ + else if((dev_info->version == 0x03) && (dev_info->port == Active_Port)) rev = 0x00; //6· + break; + case Dev_Host_LVoutput: // + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //BLV_Cx - ͨ豸 + break; + case Dev_Host_Service: //Ϣ + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //Ϣ豸 + break; + case Dev_NodeCurtain: //ɽӵ㴰 + if((dev_info->version == 0x00) && (dev_info->port == 0x00)) rev = 0x00; //ɽӵ㴰豸 + break; + case DEV_RS485_SWT: // + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //T1 + else if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //C7T/C43 + else if((dev_info->version == 0x03) && (dev_info->port == Polling_Port)) rev = 0x00; //A9IO + break; + case DEV_RS485_TEMP: //յ + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //T1¿ + else if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //C7T/C43¿ + else if((dev_info->version == 0x03) && (dev_info->port == Polling_Port)) rev = 0x00; //T1Ĺ¿ + else if((dev_info->version == 0x04) && (dev_info->port == Active_Port)) rev = 0x00; //T1¿ + break; + case DEV_RS485_INFRARED: // + //豸ʱûжԽ + break; + case DEV_RS485_AirDetect: // + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //M702 + break; + case DEV_RS485_CARD: //忨ȡ + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //BLW忨ȡ磨ѵ + else if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //BLW忨ȡ() + break; + case DEV_RS485_HEATER: //ů + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //ů + if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //CLEDů + break; + case Dev_RCU_NET: //RCU豸 + //豸ʱûжԽ + break; + case DEV_RS485_CURTAIN: //485 + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //Ǵ + if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //괰 + break; + case DEV_RS485_RELAY: //̵ + //豸Ԥȡ + break; + case DEV_RS485_IR_SEND: //ⷢ + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //ѵת豸 + if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //ת豸 + break; + case DEV_RS485_DIMMING: //ֱ + //豸Ԥȡ - ϲ485PWM + break; + case DEV_RS485_TRAIC: //ɿع + //豸Ԥȡ - ϲ485PWM + break; + case DEV_RS485_STRIP: //ƴ +// if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //ϲPWM + break; + case DEV_RS485_CoreCtrl: //п + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //С + break; + case DEV_RS485_WxLock: //΢ + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //BLW΢ + else if((dev_info->version == 0x02) && (dev_info->port == Polling_Port)) rev = 0x00; //΢ + else if((dev_info->version == 0x03) && (dev_info->port == Polling_Port)) rev = 0x00; //΢ + break; + case DEV_RS485_MUSIC: // + if((dev_info->version == 0x01) && (dev_info->port == Bus_port)) rev = 0x00; //BLV_Cx + else if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //BLWֺС + else if((dev_info->version == 0x06) && (dev_info->port == Polling_Port)) rev = 0x00; //˼ + break; + case DEV_NET_ROOMSTATE: //̬· + //豸ʱûжԽ + break; + case Dev_Host_PWMLight: //ص + //豸Ԥȡ + break; + case DEV_RS485_PWM: //485PWM + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //PWM + else if((dev_info->version == 0x02) && (dev_info->port == Polling_Port)) rev = 0x00; //A9LD + else if((dev_info->version == 0x03) && (dev_info->port == Active_Port)) rev = 0x00; //C7T + else if((dev_info->version == 0x04) && (dev_info->port == Polling_Port)) rev = 0x00; //A8PB + else if((dev_info->version == 0x05) && (dev_info->port == Bus_port)) rev = 0x00; //C12 + else if((dev_info->version == 0x06) && (dev_info->port == Polling_Port)) rev = 0x00; //ƴ + break; + case DEV_PB_LED: //ߵ + //豸Ԥȡ + break; + case DEV_RCU_POWER: //RCUԴ + //豸Ԥȡ + break; + case DEV_RS485_A9_IO_SWT: //A9IO + //豸Ԥȡ + break; + case DEV_RS485_A9_IO_EXP: //A9IOչ + //豸Ԥȡ + break; + case DEV_RS485_A9_IO_POWER: //A9IOԴ + //豸Ԥȡ + break; + case DEV_RS485_RFGatewayCycle: //ѯ + //豸Ԥȡ + break; + case DEV_RS485_RFGatewayHost: // + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //RF + break; + case DEV_RS485_RFGatewayDoor: //Ŵ + //豸Ԥȡ + break; + case DEV_RS485_AirReveal: //ʾ + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //C7Tʾ + break; + case DEV_RS485_RFGatewayRelayPir: //߼̵ + //豸Ԥȡ + break; + case Dev_Host_TimeCtrl: //ʱͬ + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //C7Tʱͬ + break; + case Dev_Rs458_MonitorCtrl: //ؿ + //豸Ԥȡ + break; + case Dev_Rs458_RotaryCtrl: //ťؿ + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //ť Э1 + if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //ť Э2 + break; + case Dev_BUS_C5IO: //BLV_CSIO + if((dev_info->version == 0x01) && (dev_info->port == Bus_port)) rev = 0x00; //BLV_CxIO豸 + break; + case Dev_RS485_CardState: + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //˿ڲ忨ͬ + if((dev_info->version == 0x02) && (dev_info->port == Polling_Port)) rev = 0x00; //ѯ˿ڲ忨ͬ + break; + case DEV_RS485_FreshAir: //485· + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //· + if((dev_info->version == 0x02) && (dev_info->port == Active_Port)) rev = 0x00; //CLED· + break; + case DEV_RS485_LCD: //LCD1602 + if((dev_info->version == 0x01) && (dev_info->port == Bus_port)) rev = 0x00; //LCD1602 + break; + case Dev_Rs485_PB20: + if((dev_info->version == 0x01) && (dev_info->port == Bus_port)) rev = 0x00; //PB20 + break; + case Dev_Rs485_PB20_LD: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //PB20_LED + break; + case Dev_Rs485_PB20_LS: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //PB20_LightStrip + break; + case Dev_Rs485_PB20_Relay: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //PB20_Relay + break; + case DEV_Virtual_NoCard: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //ϵ豸 + break; + case DEV_Virtual_Card: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //޿ȡ豸 + break; + case DEV_Virtual_ColorTemp: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //ɫµ + break; + #if Dev_485_BLE_Music_Flag + case Dev_485_BLE_Music: + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //Ƶ + break; + #endif + #if Dev_Nor_Carbon_Flag + case DEV_Carbon_Saved: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //̼ + break; + #endif + #if Dev_Nor_Scene_Restore_Flag + case Dev_Scene_Restore: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //ԭ + break; + #endif + #if Dev_Nor_GlobalSet_Flag //2025-07-15,YYW,ȫ + case Dev_Virtual_GlobalSet: + if((dev_info->version == 0x01) && (dev_info->port == 0x00)) rev = 0x00; //ȫ + break; + #endif + case Dev_Energy_Monitor: + if((dev_info->version == 0x01) && (dev_info->port == Polling_Port)) rev = 0x00; //ܺļ + if((dev_info->version == 0x01) && (dev_info->port == Active_Port)) rev = 0x00; //ܺļ + break; + } + + return rev; +} + +/******************************************************************************* +* Function Name : Logic_FrameType_DeviceExist_TempProcessing +* Description : ߼ļ - 豸 ʱ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_DeviceExist_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + char temp_str[38] = {0}; + LOGICFILE_DEVICE_INFO temp_dev_info; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + memcpy(&temp_dev_info,data,sizeof(LOGICFILE_DEVICE_INFO)); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d - %s",temp_dev_info.type,Logic_Info_DeviceType_To_String(temp_dev_info.type)); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%d",temp_dev_info.addr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸˿:%d - %s",temp_dev_info.port,Logic_Info_DevicePort_To_String(temp_dev_info.port)); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d",temp_dev_info.baud); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸Э汾:%d",temp_dev_info.version); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ͨѶط:%d",temp_dev_info.retry); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ͨѶȴʱ:%dms",temp_dev_info.writ_time); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸·:%d",temp_dev_info.input_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸·:%d",temp_dev_info.output_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d",temp_dev_info.parent_type); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%d",temp_dev_info.parent_addr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸˿:%d",temp_dev_info.parent_port); + + temp_len += sizeof(LOGICFILE_DEVICE_INFO); + + if((temp_len + temp_dev_info.input_num*4 + temp_dev_info.output_num*32) > len) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸·Ȳ:%d - %d",temp_len + temp_dev_info.input_num*4 + temp_dev_info.output_num*16,len); + } + + /*·Ϣ - ·*4Byte*/ + temp_len += temp_dev_info.input_num*4; + + /*· - ·*32Byte 2022-06-07 ȸΪ32Byte*/ + for(uint16_t i=0;idevice_num += 1; + + switch(temp_dev_info.port) + { + case Bus_port: + if(Logic_DeviceType_Legal_Judgment(&temp_dev_info) == 0x00) { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸жӦЭ--"); + + if(Lfile_info->Bus_device_num < BusDevice_NumMax) + { + Lfile_info->Bus_device_addr[Lfile_info->Bus_device_num] = data_addr; + Lfile_info->Bus_device_num += 1; + } + } + break; + case Polling_Port: + if(Logic_DeviceType_Legal_Judgment(&temp_dev_info) == 0x00){ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸жӦЭ--"); + + if(Lfile_info->Polling_device_num < PollingDevice_NumMax) + { + Lfile_info->Polling_device_addr[Lfile_info->Polling_device_num] = data_addr; + Lfile_info->Polling_device_num += 1; + } + + } + break; + case Active_Port: + if(Logic_DeviceType_Legal_Judgment(&temp_dev_info) == 0x00){ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸жӦЭ--"); + + if(Lfile_info->Active_device_num < ActiveDevice_NumMax) + { + Lfile_info->Active_device_addr[Lfile_info->Active_device_num] = data_addr; + Lfile_info->Active_device_num += 1; + } + } + break; + case 0x00: //豸 - ͨ豸 + if(Logic_DeviceType_Legal_Judgment(&temp_dev_info) == 0x00){ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸жӦЭ--"); + + if(Lfile_info->Nor_device_num < NorDevice_NumMax) + { + Lfile_info->Nor_device_addr[Lfile_info->Nor_device_num] = data_addr; + Lfile_info->Nor_device_num += 1; + } + } + break; + default: + break; + } +} + +__attribute__((section(".non_0_wait"))) char *Logic_Device_DelayUnit_To_String(uint8_t type) +{ + memset(device_temp_string,0,sizeof(device_temp_string)); + + #if LOGIC_DEBUG_INFO_EN + switch(type) + { + case 0x01: + strncpy(device_temp_string,(const char *)"ms",sizeof("ms")); + break; + case 0x02: + strncpy(device_temp_string,(const char *)"s",sizeof("s")); + break; + case 0x03: + strncpy(device_temp_string,(const char *)"min",sizeof("min")); + break; + + } + #endif + + return device_temp_string; +} + +__attribute__((section(".non_0_wait"))) char *Logic_Data_Service_Info_To_String(uint8_t id) +{ + memset(device_temp_string,0,sizeof(device_temp_string)); + + #if LOGIC_DEBUG_INFO_EN + + switch(id) + { + case 0x01: + strncpy(device_temp_string,(const char *)"ס",sizeof("ס")); + break; + case 0x02: + strncpy(device_temp_string,(const char *)"ŷ",sizeof("ŷ")); + break; + case 0x03: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case 0x04: + strncpy(device_temp_string,(const char *)"з",sizeof("з")); + break; + case 0x05: + strncpy(device_temp_string,(const char *)"ϴ·",sizeof("ϴ·")); + break; + case 0x06: + strncpy(device_temp_string,(const char *)"˷",sizeof("˷")); + break; + case 0x07: + strncpy(device_temp_string,(const char *)"Ժ",sizeof("Ժ")); + break; + case 0x08: + strncpy(device_temp_string,(const char *)"SOS",sizeof("SOS")); + break; + case 0x09: + strncpy(device_temp_string,(const char *)"Ͳͷ",sizeof("Ͳͷ")); + break; + case 0x0A: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case 0x0B: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case 0x0C: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case 0x0D: + strncpy(device_temp_string,(const char *)"Ŵŷ",sizeof("Ŵŷ")); + break; + default: + strncpy(device_temp_string,(const char *)"Զ",sizeof("Զ")); + break; + } + + #endif + + return device_temp_string; +} + + +__attribute__((section(".non_0_wait"))) char *Logic_Data_Music_folder_To_String(uint8_t id) +{ + memset(device_temp_string,0,sizeof(device_temp_string)); + + #if LOGIC_DEBUG_INFO_EN + + switch(id) + { + case BLV_C5MUSIC_Music_Dir: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case BLV_C5MUSIC_Warning_Dir: + strncpy(device_temp_string,(const char *)"ʾ",sizeof("ʾ")); + break; + case BLV_C5MUSIC_Helpsleep_Dir: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case BLV_C5MUSIC_Doorbell_Dir: + strncpy(device_temp_string,(const char *)"",sizeof("")); + break; + case BLV_C5MUSIC_Greet_Dir: + strncpy(device_temp_string,(const char *)"ӭ",sizeof("ӭ")); + break; + case BLV_C5MUSIC_Helpsleep1_Dir: + strncpy(device_temp_string,(const char *)"ڤ",sizeof("ڤ")); + break; + case BLV_C5MUSIC_Helpsleep2_Dir: + strncpy(device_temp_string,(const char *)"ߺ",sizeof("ߺ")); + break; + case BLV_C5MUSIC_Helpsleep3_Dir: + strncpy(device_temp_string,(const char *)"ɭ",sizeof("ɭ")); + break; + default: + strncpy(device_temp_string,(const char *)"δ֪ļ",sizeof("δ֪ļ")); + break; + } + + #endif + + return device_temp_string; +} + +/******************************************************************************* +* Function Name : Logic_FrameType_DeviceAction_TempProcessing +* Description : ߼ļ - 豸ݽ - 8Byte +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_Device_Action_Data_Analysis(uint8_t *data) +{ + #if LOGIC_DEBUG_INFO_EN + + LOGIC_DEVICE_ACTIVE_G temp_active; + memcpy(&temp_active,data,sizeof(LOGIC_DEVICE_ACTIVE_G)); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"****************************"); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d - %s",temp_active.type,Logic_Info_DeviceType_To_String(temp_active.type)); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%d",temp_active.addr); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ƻ·:%d",temp_active.loop); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ִзʽ:%d",temp_active.execute); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ִ:%d",temp_active.content); + + Dbg_Print(DBG_BIT_LOGIC_STATUS_bit,"ƶϸ:",temp_active.addr); + + + switch(temp_active.type) + { + case Dev_Host_Invalid: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case Dev_Host_HVout: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case Dev_Host_LVinput: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ûп\r\n"); + break; + case Dev_Host_LVoutput: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," ֵ:%d\r\n",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," ֵ:%d\r\n",temp_active.content); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ӧ ֵ:%d\r\n",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case Dev_Host_Service: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"%s ",Logic_Data_Service_Info_To_String(temp_active.loop)); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case Dev_NodeCurtain: + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case DEV_RS485_SWT: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ر·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," ֵ:%d\r\n",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," ֵ:%d\r\n",temp_active.content); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"볡й ֵ:%d\r\n",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case DEV_RS485_TEMP: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"յ״̬:"); + { + uint8_t temp_1 = 0; + uint8_t tempstate = temp_active.execute; + + temp_1 = (tempstate >> 6) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ػ"); + break; + } + + temp_1 = (tempstate >> 4) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ͷ "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + + temp_1 = (tempstate >> 2) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + + temp_1 = (tempstate >> 0) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"¶:%d\r\n",temp_active.content); + } + break; + case DEV_RS485_INFRARED: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ӧûп\r\n"); + break; + case DEV_RS485_AirDetect: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ûп\r\n"); + break; + case DEV_RS485_CARD: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"忨ȡûп\r\n"); + + break; + case DEV_RS485_HEATER: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ů״̬:"); + { + uint8_t temp_1 = 0; + uint8_t tempstate = temp_active.execute; + + temp_1 = (tempstate >> 6) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ػ"); + break; + } + + temp_1 = (tempstate >> 4) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ͷ "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + + temp_1 = (tempstate >> 2) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + + temp_1 = (tempstate >> 0) & 0x03; + switch(temp_1) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + break; + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Զ "); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"¶:%d\r\n",temp_active.content); + } + break; + case Dev_RCU_NET: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"RCU豸ûп\r\n"); + break; + case DEV_RS485_CURTAIN: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ûп\r\n"); + break; + case DEV_RS485_RELAY: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"̵·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + break; + case DEV_RS485_IR_SEND: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ⷢ-%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + switch(temp_active.content) + { + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ת"); + break; + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x04: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x05: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ƶ"); + break; + case 0x06: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ƶ"); + break; + case 0x07: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x08: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x09: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x0A: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x0B: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"OK"); + break; + case 0x0C: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ҳ"); + break; + case 0x0D: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"˵"); + break; + case 0x0E: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Դ"); + break; + case 0x0F: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ؿ"); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + } + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + switch(temp_active.content) + { + case 0x00: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ת"); + break; + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x04: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x05: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ƶ"); + break; + case 0x06: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ƶ"); + break; + case 0x07: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x08: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x09: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x0A: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x0B: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"OK"); + break; + case 0x0C: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ҳ"); + break; + case 0x0D: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"˵"); + break; + case 0x0E: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Դ"); + break; + case 0x0F: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ؿ"); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ݲ"); + break; + } + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ƥ "); + switch(temp_active.content) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"յ"); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ݲ"); + break; + } + break; + case 0x04: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," "); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ƶ:%d ",temp_active.content); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_DIMMING: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ֱ·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x07: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ѭ"); + break; + case 0x08: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ѭ"); + break; + case 0x09: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ֹͣ"); + break; + case 0x0A: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ϵ :%d",temp_active.content); + break; + case 0x0B: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"µ :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_TRAIC: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ɿع·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_STRIP: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ƴ·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_CoreCtrl: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"пûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_WxLock: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"΢ûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_MUSIC: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,":%d ",temp_active.loop); + + { + uint8_t function = temp_active.execute & 0x0F; + uint8_t function_para = (temp_active.execute >> 4) & 0x0F; + + switch(function) + { + case 0x00: + switch(function_para) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ʼ"); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ֹͣ"); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"һ"); + break; + case 0x04: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"һ"); + break; + case 0x05: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x06: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x07: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,":%d",temp_active.content); + break; + case 0x08: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ʾ:%d",temp_active.content); + break; + case 0x09: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,":%d",temp_active.content); + break; + } + break; + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,""); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ػ"); + break; + case 0x03: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ʱ %s-%d",Logic_Data_Music_folder_To_String(function_para),temp_active.content); + break; + case 0x04: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ʱ %s-%d",Logic_Data_Music_folder_To_String(function_para),temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_NET_ROOMSTATE: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"̬·ûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case Dev_Host_PWMLight: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ص·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_PWM: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"485PWM·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x07: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ѭ"); + break; + case 0x08: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"µ"); + break; + case 0x09: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ֹͣ"); + break; + case 0x0A: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ϵ :%d",temp_active.content); + break; + case 0x0B: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"µ :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_PB_LED: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"PBߵ·:%d ",temp_active.loop); + switch(temp_active.execute) + { + case 0x01: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + case 0x02: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit," :%d",temp_active.content); + break; + default: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ִзʽݲ"); + break; + } + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RCU_POWER: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"RCUԴûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_A9_IO_SWT: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"A9IOûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_A9_IO_EXP: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"A9IOչûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_A9_IO_POWER: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"A9IOԴûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_RFGatewayCycle: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ѯûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_RFGatewayHost: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_RFGatewayDoor: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"Ŵûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_AirReveal: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case DEV_RS485_RFGatewayRelayPir: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"߼̵ûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case Dev_Host_TimeCtrl: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ʱͬûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case Dev_Rs458_MonitorCtrl: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ؿûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case Dev_Rs458_RotaryCtrl: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"ťؿûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + case Dev_BUS_C5IO: + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"BLV_CSIOûп"); + Dbg_NoTick_Print(DBG_BIT_LOGIC_STATUS_bit,"\r\n"); + break; + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִʱʱ:%d%s",temp_active.delay_time,Logic_Device_DelayUnit_To_String(temp_active.delay_unit)); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"****************************"); + + #endif +} + +/******************************************************************************* +* Function Name : Logic_FrameType_DeviceAction_TempProcessing +* Description : ߼ļ - 豸 ʱ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_DeviceAction_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + char temp_str[38] = {0}; + uint32_t temp_len = 0; + uint32_t temp_data = 0; + uint8_t temp_num = 0; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + Lfile_info->active_num += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d - %s",temp_data,Logic_Info_DeviceType_To_String(temp_data)); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸ַ:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"¼:%d",temp_data); + temp_len += 2; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"·:%d",temp_data); + temp_len += 2; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"¼:0x%04x",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Logic_Info_DeviceAction_Condition_To_String(&data[temp_len]); // + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ1:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ2:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ3:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ4:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ5:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ6:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ7:%02X",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִ8:%02X",temp_data); + temp_len += 1; + + temp_len += 32; //2022-05-29 32Byte + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ִзʽ:%02X",temp_data); + temp_len += 1; + + strncpy(temp_str,(const char *)&data[temp_len],32); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%s",temp_str); + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit,"" ,&data[temp_len],32); + temp_len += 32; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d",temp_data); + temp_len += 2; // + + temp_len += 32; //2022-05-29 + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%02X",temp_data); + temp_len += 1; + + if((temp_len + temp_data*8) > len) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ȳ:%d - %d",temp_len + temp_data*8,len); + return ; + } + temp_num = temp_data; + // + for(uint16_t i=0;ivoicemap_num += 1; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + +// temp_data = data[temp_len]; +// Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d ",temp_data); +// temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ַ:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,":%d - %s",temp_data,Logic_Info_DeviceType_To_String(temp_data)); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ƶַ:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ƻ·:%d",temp_data); + temp_len += 2; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ±:%d",Lfile_info->voicemap_num); + + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit, "ǰӦϵ:", data, 6); + if(Dev_Host_Invalid != data[0]) //dz + { + if( (0x00 != data[4]) && (data[2]!=Dev_Host_Invalid) ) + { + data[4]--; + } + } + //Voice_Map_Dev_Add(&data[0]); +} + +#if RS485_PB20Fun_Flag +/******************************************************************************* +* Function Name : Logic_FrameType_DevCheckMap_TempProcessing +* Description : ߼ļ - Ѳ豸· +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_DevCheckMap_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + uint32_t temp_data = 0; + + Lfile_info->devcheckmap_num += 1; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ѳ豸:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ѳ豸ַ:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ѳ豸·:%d",temp_data); + temp_len += 2; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d W",temp_data); + temp_len += 2; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸:%d W",temp_data); + temp_len += 2; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰѲ±:%d",Lfile_info->devcheckmap_num); + + Dbg_Print_Buff(DBG_BIT_LOGIC_STATUS_bit, "ǰѲ豸:", data, 8); + + Dev_Check_Map_Add(&data[0]); +} +#endif + +/******************************************************************************* +* Function Name : Logic_FrameType_VCCondition_TempProcessing +* Description : ߼ļ - ޿ȡϢ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_VCCondition_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + uint32_t temp_data = 0; + + uint32_t list_addr = 0; + + uint8_t condata[len + 4]; //Ϣ + 4ֽʱ + memset(condata, 0 , sizeof(condata)); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ˱:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ :%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ :%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ʱʱ:%d",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ʱλ:%d",temp_data); + temp_len += 1; + + for(uint8_t i = 0; i < 11; i++) + { + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ˿%02d״̬:%d",i,temp_data); + temp_len += 1; + } + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ʱʱ:%d",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ʱλ:%d",temp_data); + temp_len += 1; + + if(data[0] == 0x01) //߼ + { + if(DevActionGlobal.VC_ConNToSSubset < (VC_CONDSUB_MAX * VC_CONDGROUP_MAX / 2)) + { + list_addr = SRAM_VCard_ConNToS_Start_Addr + DevActionGlobal.VC_ConNToSSubset * sizeof(CONDITION_STRUCT); //õµַ + memcpy(condata,data,len); + SRAM_DMA_Write_Buff(condata, sizeof(CONDITION_STRUCT), list_addr); //д + DevActionGlobal.VC_ConNToSSubset++; + if((data[1] > DevActionGlobal.VC_ConNToSGruop) && (data[1] <= VC_CONDGROUP_MAX)) + { + DevActionGlobal.VC_ConNToSGruop = data[1]; + + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳɹ,ǰַ:%08X ǰ:%d ",list_addr ,DevActionGlobal.VC_ConNToSSubset); + } + else + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ "); + } + } + else if( (data[0] == 0x02) || (data[0] == 0x03) || (data[0] == 0x04) ) //߼ + { + if(DevActionGlobal.VC_ConSToNSubset < (VC_CONDSUB_MAX * VC_CONDGROUP_MAX / 2)) + { + list_addr = SRAM_VCard_ConSToN_Start_Addr + DevActionGlobal.VC_ConSToNSubset * sizeof(CONDITION_STRUCT); //õµַ + memcpy(condata,data,len); + SRAM_DMA_Write_Buff(condata, sizeof(CONDITION_STRUCT), list_addr); //д + DevActionGlobal.VC_ConSToNSubset++; + if((data[1] > DevActionGlobal.VC_ConSToNGruop) && (data[1] <= VC_CONDGROUP_MAX)) + { + DevActionGlobal.VC_ConSToNGruop = data[1]; + } + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳɹ,ǰַ:%08X ǰ:%d ",list_addr ,DevActionGlobal.VC_ConSToNSubset); + } + else + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ "); + } + } +} + +/******************************************************************************* +* Function Name : Logic_FrameType_VCPortInfor_TempProcessing +* Description : ߼ļ - ޿ȡӳ˿Ϣ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_VCPortInfor_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + uint32_t temp_data = 0; + + uint32_t list_addr = 0; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳ˿:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳ˿ڵַ:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳ˿ڻ·:%d",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ˿ڴֵ:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ˿ں:%d",temp_data); + temp_len += 1; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ͳƱ:%d",temp_data); + temp_len += 1; + + + if(DevActionGlobal.VC_PortNum < VIRTUAL_PORT_MAX) + { + list_addr = SRAM_VCard_PortInf_Start_Addr + DevActionGlobal.VC_PortNum * sizeof(VPORT_INFO_STRUCT); //õµַ + + SRAM_DMA_Write_Buff(data,sizeof(VPORT_INFO_STRUCT), list_addr); //д + DevActionGlobal.VC_PortNum++; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ӳӳɹ,ǰ˿ڵַ:%08X ǰ˿ڼ:%d ",list_addr ,DevActionGlobal.VC_PortNum); // + } + else + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡӳ˿ڳ: %d", VIRTUAL_PORT_MAX); + } + +} + + +/******************************************************************************* +* Function Name : Logic_FrameType_VCProperty_TempProcessing +* Description : ߼ļ - ޿ȡ繫 +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_VCProperty_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + uint32_t temp_data = 0; + + uint32_t list_addr = 0; + + uint8_t tempflag = 0x00; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ڼñ:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ڼʱ:%d",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ʱ䵥λ:%d",temp_data); + temp_len += 1; + + /*ڼʱ 10Сʱ*/ + switch(data[3]) + { + case 0x01: // + if(Data_Uint8_Convert_To_Uint16(&data[1]) <= (60 * 60 * 10)) + { + tempflag = 0x01; + } + break; + case 0x02: // + if(Data_Uint8_Convert_To_Uint16(&data[1]) <= (60 * 10)) + { + tempflag = 0x01; + } + break; + case 0x03: //ʱ + if(Data_Uint8_Convert_To_Uint16(&data[1]) <= 10) + { + tempflag = 0x01; + } + break; + } + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ ñ־:%d",temp_data); + temp_len += 1; + + temp_data = Data_Uint8_Convert_To_Uint16(&data[temp_len]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ һʱʱ:%d",temp_data); + temp_len += 2; + + temp_data = data[temp_len]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡ һʱʱ䵥λ:%d",temp_data); + temp_len += 1; + + if(tempflag == 0x01) + { + list_addr = SRAM_VCard_Property_Start_Addr; + if(len < 1024) + { + SRAM_DMA_Write_Buff(data, len, list_addr); //д + } + } + else + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"޿ȡʱ䳬"); + } + +} + + +/******************************************************************************* +* Description : ߼ļ - ɫµڶ˿ӳϢ +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Logic_FrameType_ColorTempMap_TempProcessing( + uint32_t data_addr, + LOGICFILE_Content_Of_Statistical *Lfile_info, + uint8_t *data, + uint16_t len) +{ + uint32_t temp_len = 0; + uint32_t temp_data = 0; + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"%s",__func__); + + Lfile_info->ColorTemp_Map_Addr = data_addr; //ðȼ¼豸ʼɺڽ + + temp_data = data[temp_len++]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ɫ豸ַ:%d",temp_data); + + temp_data = data[temp_len++]; + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ɫ»·ӳ:%d",temp_data); + + +} + +/******************************************************************************* +* Function Name : LOGIC_FILE_Analysis +* Description : ߼ļȡSRAM +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void LOGIC_FILE_Analysis(LOGICFILE_Content_Of_Statistical *Lfile_info,uint32_t data_len) +{ + uint32_t read_addr = 0; + uint8_t temp_data[4] = {0}; + uint16_t temp_frame_num = 0; //߼ܰ + uint16_t temp_frame_id = 0; //߼ǰ + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"LOGIC_FILE_Analysis Len:%d",data_len); + + read_addr = SPIFLASH_LOGIC_DataStart_ADDRESS; + for(uint32_t i=0;idevice_num <= device_Init_num) { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Logic File 豸ʼ"); + break; + } + } + + read_addr+=temp_len-1; + i+=temp_len - 1; + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"CRCУʧ!"); + } + + }else{ + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ȡݳȲڷΧ:%08X - %d",read_addr,temp_len); + } + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"߼ļݰͷ! %d - %08x",i,read_addr); + } + + read_addr++; + } +} + +/******************************************************************************* +* Function Name : SRAM_Dev_Data_Check +* Description : SRAM 豸У +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_Dev_Data_Check(void) +{ + uint16_t i; //豸 + uint32_t Dev_processing_addr; + Device_Public_Information_G BUS_Public; //ȫ + + for(i = 0; i < DevActionGlobal.DevNum; i++) + { + Dev_processing_addr = SRAM_Device_List_Start_Addr + i*SRAM_Device_List_Size; + SRAM_DMA_Read_Buff((uint8_t *)&BUS_Public, sizeof(Device_Public_Information_G), Dev_processing_addr); //й + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ǰ豸±:%d,ַ:%08X豸:%d豸ַ:%d", i, Dev_processing_addr, BUS_Public.type, BUS_Public.addr); + Dbg_Print_Buff(DBG_BIT_NET_STATUS_bit,"BUS_Public Data:",(uint8_t *)&BUS_Public, sizeof(BUS_Public)); + } +} + +/******************************************************************************* +* Function Name : LOGIC_FILE_Check +* Description : ߼ļȡSRAM +* Input : +* Return : +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t LOGIC_FILE_Check(void) +{ + uint32_t temp = 0; + uint32_t file_len = 0; + uint8_t file_info[24]; + uint8_t md5[16]; + LOGICFILE_Content_Of_Statistical Lfile_stat; + + memset(md5,0,sizeof(md5)); + memset(file_info,0,sizeof(file_info)); + memset(&Lfile_stat,0,sizeof(LOGICFILE_Content_Of_Statistical)); //ļͳ + + //ȡMD5ֵУ + Flash_Read(file_info,24,SPIFLASH_LOGIC_DataFlag_ADDRESS); + + temp = file_info[3]; + temp <<= 8; + temp |= file_info[2]; + temp <<= 8; + temp |= file_info[1]; + temp <<= 8; + temp |= file_info[0]; + + if(temp == LOGIC_DataFlag) + { + file_len = file_info[7]; + file_len <<= 8; + file_len |= file_info[6]; + file_len <<= 8; + file_len |= file_info[5]; + file_len <<= 8; + file_len |= file_info[4]; + + if((file_len != 0x00) &&(file_len >= 0x70000)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"߼ļȲ:%08X",file_len); + return 0x01; + } + + MD5Digest_FLASH(SPIFLASH_LOGIC_DataStart_ADDRESS, file_len,(char *)&md5[0]); + + if(0==strncmp((const char *)md5,(const char *)&file_info[8],16)) + { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"MD5Уɹ!"); + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"MD5У󣬲 Len:%08X",file_len); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ʧܣMd5:%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X%02X,%02X,%02X,%02X,%02X,%02X",md5[0],md5[1],md5[2],md5[3],md5[4],md5[5],md5[6],md5[7],md5[8],md5[9],md5[10],md5[11],md5[12],md5[13],md5[14],md5[15]); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"UDP Md5:%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X,%02X",\ + file_info[8],file_info[9],\ + file_info[10],file_info[11],\ + file_info[12],file_info[13],\ + file_info[14],file_info[15],\ + file_info[16],file_info[17],\ + file_info[18],file_info[19],\ + file_info[21],file_info[21],\ + file_info[22],file_info[23]); + return 0x01; + } + + /*ļ - ȫһ飬ҵԵ*/ + LOGIC_FILE_Analysis(&Lfile_stat,file_len); + + }else { + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"߼ļ־λ:%08X",temp); + } + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--------------------"); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸%d",Lfile_stat.device_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--BUS豸ڣ%d",Lfile_stat.Bus_device_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--Polling豸ڣ%d",Lfile_stat.Polling_device_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--Active豸ڣ%d",Lfile_stat.Active_device_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--ͨ豸ڣ%d",Lfile_stat.Nor_device_num); + + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--------------------"); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"豸%d",Lfile_stat.active_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--------------------"); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"ӳ%d",Lfile_stat.voicemap_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"Ѳ%d",Lfile_stat.devcheckmap_num); + Dbg_Println(DBG_BIT_LOGIC_STATUS_bit,"--------------------"); + + /*߼е豸гʼ*/ + memset((void *)&BUS485_Info,0,sizeof(BLV_BUS_Manage_G)); + memset((void *)&Poll485_Info,0,sizeof(BLV_POLL_Manage_G)); + memset((void *)&Act485_Info,0,sizeof(BLV_ACTIVE_Manage_G)); + + + SRAM_Write_DW(SRAM_Device_List_Start_Addr,SRAM_BUS_Device_List_Addr); + //BUS豸 + for(uint8_t i=0;i> (32-(n)))) + +#define FF(a, b, c, d, x, s, ac) { (a) += F ((b), (c), (d)) + (x) + (UINT4)(ac); (a) = ROTATE_LEFT ((a), (s)); (a) += (b); } +#define GG(a, b, c, d, x, s, ac) { (a) += G ((b), (c), (d)) + (x) + (UINT4)(ac); (a) = ROTATE_LEFT ((a), (s)); (a) += (b); } +#define HH(a, b, c, d, x, s, ac) { (a) += H ((b), (c), (d)) + (x) + (UINT4)(ac); (a) = ROTATE_LEFT ((a), (s)); (a) += (b); } +#define II(a, b, c, d, x, s, ac) { (a) += I ((b), (c), (d)) + (x) + (UINT4)(ac); (a) = ROTATE_LEFT ((a), (s)); (a) += (b); } + +void Encode(unsigned char *output, UINT4 *input, unsigned int len) +{ + unsigned int i, j; + + for (i = 0, j = 0; j < len; i++, j += 4) { + output[j] = (unsigned char)(input[i] & 0xff); + output[j+1] = (unsigned char)((input[i] >> 8) & 0xff); + output[j+2] = (unsigned char)((input[i] >> 16) & 0xff); + output[j+3] = (unsigned char)((input[i] >> 24) & 0xff); + } +} + +void MD5Init(MD5_CTX *context) +{ + context->count[0] = context->count[1] = 0; + context->state[0] = 0x67452301; + context->state[1] = 0xefcdab89; + context->state[2] = 0x98badcfe; + context->state[3] = 0x10325476; +} + +void Decode(UINT4 *output, unsigned char *input, unsigned int len) +{ + unsigned int i, j; + + for (i = 0, j = 0; j < len; i++, j += 4) { + output[i] = ((UINT4)input[j]) | (((UINT4)input[j+1]) << 8) | (((UINT4)input[j+2]) << 16) | (((UINT4)input[j+3]) << 24); + } + +} + +void MD5Transform (UINT4 state[4], unsigned char block[64]) +{ + UINT4 a = state[0], b = state[1], c = state[2], d = state[3], x[16]; + Decode (x, block, 64); + FF (a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */ + FF (d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */ + FF (c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */ + FF (b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */ + FF (a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */ + FF (d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */ + FF (c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */ + FF (b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */ + FF (a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */ + FF (d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */ + FF (c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */ + FF (b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */ + FF (a, b, c, d, x[12], S11, 0x6b901122); /* 13 */ + FF (d, a, b, c, x[13], S12, 0xfd987193); /* 14 */ + FF (c, d, a, b, x[14], S13, 0xa679438e); /* 15 */ + FF (b, c, d, a, x[15], S14, 0x49b40821); /* 16 */ + GG (a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */ + GG (d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */ + GG (c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */ + GG (b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */ + GG (a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */ + GG (d, a, b, c, x[10], S22, 0x2441453); /* 22 */ + GG (c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */ + GG (b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */ + GG (a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */ + GG (d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */ + GG (c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */ + GG (b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */ + GG (a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ + GG (d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */ + GG (c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */ + GG (b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */ + HH (a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */ + HH (d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */ + HH (c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */ + HH (b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */ + HH (a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */ + HH (d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */ + HH (c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */ + HH (b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */ + HH (a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */ + HH (d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */ + HH (c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */ + HH (b, c, d, a, x[ 6], S34, 0x4881d05); /* 44 */ + HH (a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */ + HH (d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */ + HH (c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */ + HH (b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */ + II (a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */ + II (d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */ + II (c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */ + II (b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */ + II (a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */ + II (d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */ + II (c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */ + II (b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */ + II (a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */ + II (d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */ + II (c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */ + II (b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */ + II (a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */ + II (d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */ + II (c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */ + II (b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */ + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + memset ((POINTER)x, 0, sizeof (x)); +} + +void MD5Update(MD5_CTX *context, unsigned char *input, unsigned int inputLen) +{ + unsigned int i, index, partLen; + + index = (unsigned int)((context->count[0] >> 3) & 0x3F); + if ((context->count[0] += ((UINT4)inputLen << 3)) < ((UINT4)inputLen << 3)) context->count[1]++; + context->count[1] += ((UINT4)inputLen >> 29); + + partLen = 64 - index; + + if (inputLen >= partLen) { + memcpy((POINTER)&context->buffer[index], (POINTER)input, partLen); + MD5Transform(context->state, context->buffer); + + for (i = partLen; i + 63 < inputLen; i += 64) + MD5Transform (context->state, &input[i]); + index = 0; + } else i = 0; + + memcpy((POINTER)&context->buffer[index], (POINTER)&input[i], inputLen-i); +} + +void MD5_SRAM_Update(MD5_CTX *context, uint32_t add, unsigned int inputLen) +{ + unsigned int i, index, partLen; + uint32_t addr = add; + + index = (unsigned int)((context->count[0] >> 3) & 0x3F); + if ((context->count[0] += ((UINT4)inputLen << 3)) < ((UINT4)inputLen << 3)) context->count[1]++; + context->count[1] += ((UINT4)inputLen >> 29); + + partLen = 64 - index; + + if (inputLen >= partLen) { + // memcpy((POINTER)&context->buffer[index], (POINTER)input, partLen); + SRAM_DMA_Read_Buff((POINTER)&context->buffer[index], partLen, addr); + addr += partLen; + + MD5Transform(context->state, context->buffer); + unsigned char block[64]; + for (i = partLen; i + 63 < inputLen; i += 64) + { + WDT_Feed(); //ӿŹ + SRAM_DMA_Read_Buff(block, 64, addr); + addr += 64; + MD5Transform (context->state, block); + } + index = 0; + } else i = 0; + +// memcpy((POINTER)&context->buffer[index], (POINTER)&input[i], inputLen-i); + SRAM_DMA_Read_Buff((POINTER)&context->buffer[index], inputLen-i, addr); +} + +void MD5_FLASH_Update(MD5_CTX *context, uint32_t add, unsigned int inputLen) +{ + unsigned int i, index, partLen; + uint32_t addr = add; + + index = (unsigned int)((context->count[0] >> 3) & 0x3F); + if ((context->count[0] += ((UINT4)inputLen << 3)) < ((UINT4)inputLen << 3)) context->count[1]++; + context->count[1] += ((UINT4)inputLen >> 29); + + partLen = 64 - index; + + if (inputLen >= partLen) + { + Flash_Read((POINTER)&context->buffer[index], partLen, addr); + addr += partLen; + + MD5Transform(context->state, context->buffer); + unsigned char block[64]; + for (i = partLen; i + 63 < inputLen; i += 64) + { + WDT_Feed(); //ӿŹ + Flash_Read(block, 64, addr); + addr += 64; + MD5Transform (context->state, block); + } + index = 0; + } else i = 0; + + Flash_Read((POINTER)&context->buffer[index], inputLen-i, addr); +} + +void MD5Final(unsigned char digest[16], MD5_CTX *context) +{ + unsigned char bits[8]; + unsigned int index, padLen; + + Encode (bits, context->count, 8); + index = (unsigned int)((context->count[0] >> 3) & 0x3f); + padLen = (index < 56) ? (56 - index) : (120 - index); + MD5Update (context, PADDING, padLen); + MD5Update (context, bits, 8); + Encode (digest, context->state, 16); + memset ((POINTER)context, 0, sizeof (*context)); +} + +void MD5Digest(char *pszInput, unsigned int nInputSize, char *pszOutPut) +{ + MD5_CTX context; + //unsigned int len = strlen (pszInput); + unsigned int len = nInputSize; + + MD5Init (&context); + MD5Update (&context, (unsigned char *)pszInput, len); + MD5Final ((unsigned char *)pszOutPut, &context); +} + +void MD5Digest_SRAM(uint32_t add, unsigned int nInputSize, char *pszOutPut) +{ + MD5_CTX context; + //unsigned int len = strlen (pszInput); + unsigned int len = nInputSize; + + MD5Init(&context); + MD5_SRAM_Update(&context, add, len); + MD5Final((unsigned char *)pszOutPut, &context); +} + +void MD5Digest_FLASH(uint32_t add, unsigned int nInputSize, char *pszOutPut) +{ + MD5_CTX context; + unsigned int len = nInputSize; + + MD5Init(&context); + MD5_FLASH_Update(&context, add, len); + MD5Final((unsigned char *)pszOutPut, &context); +} + diff --git a/MCU_Driver/rtc.c b/MCU_Driver/rtc.c new file mode 100644 index 0000000..22ad595 --- /dev/null +++ b/MCU_Driver/rtc.c @@ -0,0 +1,292 @@ +/* + * rtc.c + * + * Created on: Jul 29, 2025 + * Author: cc + */ +#include "includes.h" +#include +#include + +S_RTC RTC_Raw_Data = { + .year = 0, + .month = 1, + .day = 1, + .week = 0, + .hour = 0, + .minute = 0, + .second = 0, +}; + +S_RTC MCU_RTC_Data = { + .year = 0, + .month = 1, + .day = 1, + .week = 0, + .hour = 0, + .minute = 0, + .second = 0, +}; + +S_RTC Net_RTC_Data; //2024-08-03 ʱ +TIME_INFO_T g_time_info; + +uint32_t Mcu_GetTime_tick = 0; +uint32_t Log_Time_ms = 0; + +/******************************************************************************* +* Function Name : RTC_Init +* Description : RTCʼ - עBLV-C1PûRTCܣֻʹϵͳʱģRTCʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void RTC_Init(void) +{ + memset(&RTC_Raw_Data,0,sizeof(S_RTC)); + memset(&MCU_RTC_Data,0,sizeof(S_RTC)); + memset(&Net_RTC_Data,0,sizeof(S_RTC)); + memset(&g_time_info,0,sizeof(TIME_INFO_T)); + + RTC_Raw_Data.year = 0x00; + RTC_Raw_Data.month = 0x01; + RTC_Raw_Data.day = 0x01; + RTC_Raw_Data.week = 0x00; + RTC_Raw_Data.hour = 0x00; + RTC_Raw_Data.minute = 0x00; + RTC_Raw_Data.second = 0x00; + + MCU_RTC_Data.year = 0x00; + MCU_RTC_Data.month = 0x01; + MCU_RTC_Data.day = 0x01; + MCU_RTC_Data.week = 0x00; + MCU_RTC_Data.hour = 0x00; + MCU_RTC_Data.minute = 0x00; + MCU_RTC_Data.second = 0x00; + +} + +/******************************************************************************* +* Function Name : HEX_data_conversion_to_DEC +* Description : ʮƱʮתΪʵʵʮ 0x20 -> 20 +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t HEX_Conversion_To_DEC(uint8_t c_num) +{ + uint8_t rev_num = 0; + + rev_num = (c_num/16)*10 + (c_num%16); + + return rev_num; +} + +/******************************************************************************* +* Function Name : HEX_data_conversion_to_DEC +* Description : ʮתΪʮƷʽ 20 -> 0x20 +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t DEV_Conversion_To_HEX(uint8_t c_num) +{ + uint8_t rev_num = 0; + + rev_num = (c_num/10)*16 + (c_num%10); + + return rev_num; +} + +/******************************************************************************* +* Function Name : RTC_Conversion_To_UTC +* Description : RTCʱתΪUTCʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t RTC_Conversion_To_Unix(S_RTC *rtc_time) +{ +// uint32_t timestamp = 0; +// struct tm test_time; +// +// test_time.tm_year = HEX_Conversion_To_DEC(rtc_time->year) + 2000 - 1900; +// if(rtc_time->month != 0x00) +// { +// test_time.tm_mon = HEX_Conversion_To_DEC(rtc_time->month) - 1; +// }else { +// test_time.tm_mon = 1; +// } +// +// test_time.tm_mday = HEX_Conversion_To_DEC(rtc_time->day); +// test_time.tm_hour = HEX_Conversion_To_DEC(rtc_time->hour); +// test_time.tm_min = HEX_Conversion_To_DEC(rtc_time->minute); +// test_time.tm_sec = HEX_Conversion_To_DEC(rtc_time->second); +// test_time.tm_isdst = -1; +// +// timestamp = mktime(&test_time); //תı־UTCʱ +// +// /*ʱ仹Ҫȥ8Сʱ*/ +// timestamp -= 8*3600; +// +// return timestamp; + + return 0x00; +} + +/******************************************************************************* +* Function Name : UTC_Conversion_To_RTC +* Description : UTCʱתΪRTCʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Unix_Conversion_To_RTC(S_RTC *rtc_time,uint32_t utc_tick) +{ +// uint8_t temp = 0; +// time_t temp_tick = utc_tick + 8*3600; /*ʱ任ɱ׼Ҫ8Сʱ*/ +// struct tm *test_time; +// +// test_time = localtime(&temp_tick); +// +// temp = ( 1900 + test_time->tm_year ) - 2000; +// rtc_time->year = DEV_Conversion_To_HEX(temp); +// temp = 1 + test_time->tm_mon; +// rtc_time->month = DEV_Conversion_To_HEX(temp); +// temp = test_time->tm_mday; +// rtc_time->day = DEV_Conversion_To_HEX(temp); +// +// temp = test_time->tm_hour; +// rtc_time->hour = DEV_Conversion_To_HEX(temp); +// temp = test_time->tm_min; +// rtc_time->minute = DEV_Conversion_To_HEX(temp); +// temp = test_time->tm_sec; +// rtc_time->second = DEV_Conversion_To_HEX(temp); +// +// temp = test_time->tm_wday; +// rtc_time->week = DEV_Conversion_To_HEX(temp); + +} + +/******************************************************************************* +* Function Name : RTC_ReadDate +* Description : RTCʱȡ - BLV_C1PûRTCܣֶֻʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t RTC_ReadDate(S_RTC *psRTC) +{ + + if(g_time_info.time_select == 0x02){ + /* CSIOʱȡ ʼ*/ + + psRTC->year = MCU_RTC_Data.year; + psRTC->month = MCU_RTC_Data.month; + psRTC->day = MCU_RTC_Data.day; + psRTC->hour = MCU_RTC_Data.hour; + psRTC->minute = MCU_RTC_Data.minute; + psRTC->second = MCU_RTC_Data.second; + psRTC->week = MCU_RTC_Data.week; + + /* CSIOʱȡ */ + }else{ + /* ʱ ʼ */ + + //ĵǰʱ+ؼ + uint32_t rtc_tick = 0; + + rtc_tick = RTC_Conversion_To_Unix(&MCU_RTC_Data); + //rtc_tick += rtc_hour*3600+rtc_min*60+rtc_sec; + rtc_tick += SysTick_1s - Mcu_GetTime_tick; + Unix_Conversion_To_RTC(psRTC,rtc_tick); + + /* ʱ */ + } + + return 0; +} + +/******************************************************************************* +* Function Name : RTC_WriteDate +* Description : RTCʱ - BLV_C1PûRTCܣֶֻʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t RTC_WriteDate(S_RTC SetRTC) +{ + //2Сʱѯʵĵǰʱ䣬ؼ + MCU_RTC_Data.year = SetRTC.year; + MCU_RTC_Data.month = SetRTC.month; + MCU_RTC_Data.day = SetRTC.day; + MCU_RTC_Data.hour = SetRTC.hour; + MCU_RTC_Data.minute = SetRTC.minute; + MCU_RTC_Data.second = SetRTC.second; + + Mcu_GetTime_tick = SysTick_1s; //¼ǰʱ + + return 0; +} + +/******************************************************************************* +* Function Name : NetRTC_WriteDate +* Description : RTCʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t NetRTC_WriteDate(S_RTC SetRTC) +{ + Net_RTC_Data.year = SetRTC.year; + Net_RTC_Data.month = SetRTC.month; + Net_RTC_Data.day = SetRTC.day; + Net_RTC_Data.hour = SetRTC.hour; + Net_RTC_Data.minute = SetRTC.minute; + Net_RTC_Data.second = SetRTC.second; + Net_RTC_Data.week = SetRTC.week; + + g_time_info.Mcu_GetTime_tick = SysTick_1s; //¼ǰʱ + + return 0; +} + +/******************************************************************************* +* Function Name : RTC_TASK +* Description : RTC - BLV_C1PûRTCܣֶֻʱ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void RTC_TASK(void) +{ + static uint32_t RTC_Tick = 0; + uint8_t r_minute = 0; + if(SysTick_1ms - RTC_Tick >= 1000) + { + r_minute = RTC_Raw_Data.minute; + RTC_Tick = SysTick_1ms; + RTC_ReadDate(&RTC_Raw_Data); + + if(r_minute != RTC_Raw_Data.minute) + { + Log_Time_ms = SysTick_1ms; //ÿʱ + } + if(server_info.sync_tick==0x01) + { + server_info.sync_tick = 0x02; + } + } +} + +/******************************************************************************* +* Function Name : RTC_TimeDate_Correct_Figure +* Description : RTCʱǷΪЧ A~F +* Return : 0x00:0x01:ݲȷ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t RTC_TimeDate_Correct_Figure(uint8_t data) +{ + uint8_t temp_num = data; + + if( ((temp_num & 0x0F) < 0x0A) ){ + temp_num >>= 4; + if( ((temp_num & 0x0F) < 0x0A) ){ + return 0x00; + } + } + + return 0x01; +} + + + + + + + + + + + diff --git a/MCU_Driver/rw_logging.c b/MCU_Driver/rw_logging.c new file mode 100644 index 0000000..1c7d970 --- /dev/null +++ b/MCU_Driver/rw_logging.c @@ -0,0 +1,340 @@ +/* + * rw_logging.c + * + * Created on: Jul 29, 2025 + * Author: cc + */ +#include "includes.h" +#include + +/*ȡSRAM־ǰдַ*/ +__attribute__((section(".non_0_wait"))) uint32_t Get_Log_Current_Address(void) +{ + uint32_t Last_addr = 0; + uint8_t temp_d = 0; + + temp_d = SRAM_Read_Byte(SRAM_LOG_Start_Address+3); + Last_addr = temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_LOG_Start_Address+2); + Last_addr |= temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_LOG_Start_Address+1); + Last_addr |= temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_LOG_Start_Address); + Last_addr |= temp_d; + + if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address; + return Last_addr; +} + +/*SRAM־ǰдַ*/ +__attribute__((section(".non_0_wait"))) void Set_Log_Current_Address(uint32_t W_addr) +{ + uint32_t Last_addr = W_addr; + uint8_t temp = 0; + + if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address; + + temp = Last_addr & 0xFF; + SRAM_Write_Byte(temp,SRAM_LOG_Start_Address); + temp = (Last_addr >> 8) & 0xFF; + SRAM_Write_Byte(temp,SRAM_LOG_Start_Address+1); + temp = (Last_addr >> 16) & 0xFF; + SRAM_Write_Byte(temp,SRAM_LOG_Start_Address+2); + temp = (Last_addr >> 24) & 0xFF; + SRAM_Write_Byte(temp,SRAM_LOG_Start_Address+3); +} + +/*SRAMTFTPǰ־ַ*/ +__attribute__((section(".non_0_wait"))) void SRAM_Set_TFTP_READ_LOG_Address(uint32_t r_addr) +{ + uint32_t Last_addr = r_addr; + uint8_t temp = 0; + + /*жϵַǷϷ*/ + if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address; + + temp = Last_addr & 0xFF; + SRAM_Write_Byte(temp,SRAM_TFTP_LOG_READ_Address); + temp = (Last_addr >> 8) & 0xFF; + SRAM_Write_Byte(temp,SRAM_TFTP_LOG_READ_Address+1); + temp = (Last_addr >> 16) & 0xFF; + SRAM_Write_Byte(temp,SRAM_TFTP_LOG_READ_Address+2); + temp = (Last_addr >> 24) & 0xFF; + SRAM_Write_Byte(temp,SRAM_TFTP_LOG_READ_Address+3); +} + +/*ȡSRAMTFTPǰ־ַ*/ +__attribute__((section(".non_0_wait"))) uint32_t SRAM_Get_TFTP_READ_Log_Address(void) +{ + uint32_t Last_addr = 0; + uint8_t temp_d = 0; + + temp_d = SRAM_Read_Byte(SRAM_TFTP_LOG_READ_Address+3); + Last_addr = temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_TFTP_LOG_READ_Address+2); + Last_addr |= temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_TFTP_LOG_READ_Address+1); + Last_addr |= temp_d; + Last_addr <<= 8; + temp_d = SRAM_Read_Byte(SRAM_TFTP_LOG_READ_Address); + Last_addr |= temp_d; + + if((Last_addr < SRAM_LOG_DATA_Address) || (Last_addr > SRAM_LOG_End_Address)) Last_addr = SRAM_LOG_DATA_Address; + return Last_addr; +} + +/******************************************************************************* +* Function Name : ־湦 +* Description : ־ÿһСʱSRAMе־ݽзװ + װֻǼϰͷβǰʱ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Log_write_sram(uint8_t data_type,uint8_t *buff,uint16_t len) +{ + uint16_t temp_date = 0; + uint32_t Last_add = 0; + uint32_t Log_Hour_Tick = SysTick_1ms - Log_Time_ms; //2021-09-23 Log_Time_msñжндֹֹȫֱжwhileͬʱд + Log_Hour_Tick += HEX_Conversion_To_DEC(RTC_Raw_Data.minute)*60000; + Log_Hour_Tick += HEX_Conversion_To_DEC(RTC_Raw_Data.hour)*3600000; + + uint8_t temp = 0; + uint16_t data_len = len; + + if(data_len >= Log_Data_Len_MAX) data_len = Log_Data_Len_MAX; //޶ݳ + uint16_t write_len = S_Log_Data + data_len + 1; + /*һȡ־дַ*/ + Last_add = Get_Log_Current_Address(); + + //ǰַǷЧҿԽ־ + if((Last_add + write_len) >= SRAM_LOG_End_Address) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit," SRAM Space is not enough"); + Last_add = SRAM_LOG_DATA_Address; + } + + /*ڶָʽ־*/ + SRAM_Write_Byte(LOG_Data_Hand,Last_add + S_Log_Hand); //ͷ + temp = SRAM_Read_Byte(SRAM_Flash_Serial_Number); + SRAM_Write_Byte(temp,Last_add + S_Log_SN); //к + temp++; + SRAM_Write_Byte(temp,SRAM_Flash_Serial_Number); //кˢ£ + SRAM_Write_Word(write_len,Last_add + S_Log_Len); //ݳ 2Byte + SRAM_Write_Byte(0x00,Last_add + S_Log_Check); //Уֵ + + temp_date = (HEX_Conversion_To_DEC(RTC_Raw_Data.year) << 10) + (HEX_Conversion_To_DEC(RTC_Raw_Data.month) << 5) + HEX_Conversion_To_DEC(RTC_Raw_Data.day); + + temp = (temp_date >> 8) & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Date_H); //H - ꣺4bit £4bit + temp = temp_date & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Date_L); //L - գ4bit ʱ4bit + SRAM_Write_Byte(data_type,Last_add + S_Log_Type); // + temp = Log_Hour_Tick & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Time8B); //ʱ + temp = (Log_Hour_Tick >> 8) & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Time16B); + temp = (Log_Hour_Tick >> 16) & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Time24B); + temp = (Log_Hour_Tick >> 24) & 0xFF; + SRAM_Write_Byte(temp,Last_add + S_Log_Time32B); + + SRAM_DMA_Write_Buff(buff,data_len,Last_add + S_Log_Data); // + SRAM_Write_Byte(Log_Data_End,Last_add + S_Log_Data + data_len); //β + + /*У*/ + temp = Log_CheckSum(Last_add,write_len); + SRAM_Write_Byte(temp,Last_add + S_Log_Check); //Уֵ + + /*ˢ־дַ*/ + Last_add = Last_add + write_len; + Set_Log_Current_Address(Last_add); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"SRAM LOG Addr : %08X",Last_add); + return 0; +} + +/******************************************************************************* +* Function Name : Retain_Flash_Register_Data +* Description : ĿĴֵ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Retain_Flash_Register_Data(void) +{ + uint8_t temp = 0,temp1 = 0; + uint16_t i = 0; + + memset(Global_Large_Buff,0,Register_OFFSET_LEN); + + Flash_Read(Global_Large_Buff,Register_OFFSET_LEN,FLASH_Register_Start_ADDRESS); + + for(i = 0;i= 2000) + { + polling_tick = SysTick_1ms; + + if( (DevActionGlobal.DevActionU64Cond.EleState != DevActionGlobal.Last_EleState) + || (DevActionGlobal.DimGlobalValue != DevActionGlobal.Last_DimGlobalValue) + || (DevActionGlobal.CCTValue != DevActionGlobal.Last_CCTValue) + || (DevActionGlobal.SleepMode_State != DevActionGlobal.Last_SleepMode_State) + || (DevActionGlobal.SleepLight_State != DevActionGlobal.Last_SleepLight_State) + || (DevActionGlobal.Person_Detected != DevActionGlobal.Last_Person_Detected) + || (DevActionGlobal.CardState != DevActionGlobal.Last_CardState) + || (DevActionGlobal.Rs485CardType != DevActionGlobal.Last_Rs485CardType) + || (DevActionGlobal.DevActionU64Cond.NeightState != DevActionGlobal.Last_NeightState) ) + { + DevActionGlobal.Last_EleState = DevActionGlobal.DevActionU64Cond.EleState; + DevActionGlobal.Last_DimGlobalValue = DevActionGlobal.DimGlobalValue ; + DevActionGlobal.Last_CCTValue = DevActionGlobal.CCTValue; + DevActionGlobal.Last_SleepMode_State = DevActionGlobal.SleepMode_State; + DevActionGlobal.Last_SleepLight_State = DevActionGlobal.SleepLight_State; + DevActionGlobal.Last_Person_Detected = DevActionGlobal.Person_Detected; + DevActionGlobal.Last_CardState = DevActionGlobal.CardState; + DevActionGlobal.Last_Rs485CardType = DevActionGlobal.Rs485CardType; + + log_len = 0x00; + log_buff[log_len++] = 0xA8; //־λ + log_buff[log_len++] = 0x00; //ݳ + log_buff[log_len++] = 0x00; //Уλ + + log_buff[log_len++] = DevActionGlobal.Last_EleState; //ȡ״̬ + log_buff[log_len++] = (DevActionGlobal.Last_DimGlobalValue & 0xFF); //ȫ + log_buff[log_len++] = ((DevActionGlobal.Last_DimGlobalValue >> 8) & 0xFF); //ȫ + log_buff[log_len++] = (DevActionGlobal.Last_CCTValue & 0xFF); //ȫɫ + log_buff[log_len++] = ((DevActionGlobal.Last_CCTValue >> 8) & 0xFF); //ȫɫ + log_buff[log_len++] = DevActionGlobal.Last_SleepMode_State; //˯ģʽ + log_buff[log_len++] = DevActionGlobal.Last_SleepLight_State; //˯ߵƹ״̬ + log_buff[log_len++] = DevActionGlobal.Last_Person_Detected; //޿ȡУ״̬ + log_buff[log_len++] = DevActionGlobal.Last_CardState; + log_buff[log_len++] = DevActionGlobal.Last_Rs485CardType; + log_buff[log_len++] = DevActionGlobal.Last_NeightState; + + log_buff[1] = log_len; //ݳ + log_buff[2] = Data_CheckSum(log_buff,log_len); //Уֵ + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"%s %d",__func__,DevActionGlobal.Last_Person_Detected); + + SRAM_DMA_Write_Buff(log_buff,log_len,SRAM_PowerOn_Restore_StartAddr ); + } + } +} + +/*ϵ󣬶ȡⲿSRAMеIJϢ */ +__attribute__((section(".non_0_wait"))) uint8_t SRAM_PowerOn_Restore_ParaInfo(void) +{ + uint8_t log_len = 0; + uint8_t log_buff[22]; + uint16_t temp_val = 0; + memset(log_buff,0,22); + + SRAM_DMA_Read_Buff(log_buff,20,SRAM_PowerOn_Restore_StartAddr ); + + if(log_buff[0] == 0xA8) //У־λ + { + if(log_buff[1] == 0x0E) //Уݳ + { + if(Data_CheckSum(log_buff,0x0E) == 0x00) + { + log_len = 0x03; + DevActionGlobal.Last_EleState = log_buff[log_len++]; + + temp_val = log_buff[log_len++]; + temp_val <<= 8; + temp_val |= log_buff[log_len++]; + DevActionGlobal.Last_DimGlobalValue = temp_val; + + temp_val = log_buff[log_len++]; + temp_val <<= 8; + temp_val |= log_buff[log_len++]; + DevActionGlobal.Last_CCTValue = temp_val; + + DevActionGlobal.Last_SleepMode_State = log_buff[log_len++]; + + DevActionGlobal.Last_SleepLight_State = log_buff[log_len++]; + + DevActionGlobal.Last_Person_Detected = log_buff[log_len++]; + + DevActionGlobal.Last_CardState = log_buff[log_len++]; + + DevActionGlobal.Last_Rs485CardType = log_buff[log_len++]; + + DevActionGlobal.Last_NeightState = log_buff[log_len++]; + + DevActionGlobal.DevActionU64Cond.EleState = DevActionGlobal.Last_EleState; + DevActionGlobal.DimGlobalValue = DevActionGlobal.Last_DimGlobalValue; + DevActionGlobal.CCTValue = DevActionGlobal.Last_CCTValue; + DevActionGlobal.SleepMode_State = DevActionGlobal.Last_SleepMode_State; + DevActionGlobal.SleepLight_State = DevActionGlobal.Last_SleepLight_State; + DevActionGlobal.Person_Detected = DevActionGlobal.Last_Person_Detected; + DevActionGlobal.CardState= DevActionGlobal.Last_CardState; + DevActionGlobal.Rs485CardType= DevActionGlobal.Last_Rs485CardType; + DevActionGlobal.DevActionU64Cond.NeightState = DevActionGlobal.Last_NeightState; + + + + DevActionGlobal.sram_save_flag = 0xA8; + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_EleState:%d ",DevActionGlobal.Last_EleState); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_DimGlobalValue:%d ",DevActionGlobal.Last_DimGlobalValue); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_CCTValue:%d ",DevActionGlobal.Last_CCTValue); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_SleepMode_State:%d ",DevActionGlobal.Last_SleepMode_State); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_SleepLight_State:%d ",DevActionGlobal.Last_SleepLight_State); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_Person_Detected:%d ",DevActionGlobal.Last_Person_Detected); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_CardState:%d ",DevActionGlobal.Last_CardState); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"Last_NeightState:%d ",DevActionGlobal.Last_NeightState); + + return 0x00; + } + } + } + + return 0x01; +} + + + diff --git a/MCU_Driver/spi_flash.c b/MCU_Driver/spi_flash.c new file mode 100644 index 0000000..5c58887 --- /dev/null +++ b/MCU_Driver/spi_flash.c @@ -0,0 +1,496 @@ +/* + * spi_flash.c + * + * Created on: May 20, 2025 + * Author: cc + */ + +#include "spi_flash.h" +#include "debug.h" + +uint8_t Temp_Flash_Buff[4100]; //FLash д뻺BUFF + +__attribute__((section(".non_0_wait"))) void SPI_FLASH_Init(void) +{ + /* SPI Flash SPI SRAM SPI + * SPI Flash ųʼ + * */ + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"SPI Flash ID:0x%04x\r\n",Flash_ReadID()); +} + +/******************************************************************************* +* Function Name : Flash_ReadSR +* Description : P25Q40H Flashȡ״̬Ĵ +* Input : None +* Return : P25Q40H Flash״̬Ĵֵ + BIT7 6 5 4 3 2 1 0 + SPR0 BP4 BP3 BP2 BP1 BP0 WEL WIP + SPR:Ĭ0,״̬Ĵλ,WPʹ + BP4,BP3,BP2,BP1,BP0:FLASHд + WEL:дʹ + BUSY:æλ(1,æ;0,) + Ĭ:0x00 +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Flash_ReadSR(void) +{ + uint8_t byte = 0; + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_ReadStatusReg); //Ͷȡ״̬Ĵ + byte = SPI0_MasterRecvByte(); + Flash_CS_H; + return byte; +} + +/******************************************************************************* +* Function Name : Flash_WriteSR +* Description : P25Q40H Flashд״̬Ĵ +* Input : + sr_val:д״̬Ĵֵ + BIT7 6 5 4 3 2 1 0 + SPR0 BP4 BP3 BP2 BP1 BP0 WEL WIP + + ֻSPR0,BP3,BP2,BP1,BP0(bit 7,5,4,3,2)д!!! +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_WriteSR(uint8_t sr_val) +{ + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_WriteStatusReg); + SPI0_MasterSendByte(sr_val); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_Write_Enable +* Description : P25Q40H дʹ -- WELλ +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Write_Enable(void) +{ + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_WriteEnable); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_Write_Disable +* Description : P25Q40H дֹ -- WEL +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Write_Disable(void) +{ + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_WriteDisable); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_ReadID +* Description : P25Q40H Flash ȡоƬID +* Input : None +* Return : ֵ£ + 0x8512:ʾоƬͺΪP25Q40H + 0x8511:ʾоƬͺΪP25Q20H + 0x8510:ʾоƬͺΪP25Q10H + 0x8509:ʾоƬͺΪP25Q05H +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t Flash_ReadID(void) +{ + uint16_t temp=0; + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_ReadManufactureID); + SPI0_MasterRecvByte(); + SPI0_MasterRecvByte(); + SPI0_MasterRecvByte(); + temp |= SPI0_MasterRecvByte()<<8; + temp |= SPI0_MasterRecvByte(); + Flash_CS_H; + return temp; +} + +/******************************************************************************* +* Function Name : Flash_Wait_Busy +* Description : ȴ +* Input : None +* Return : 1ȴʱڷæ״̬ + 0״̬ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t Flash_Wait_Busy(void) +{ + uint8_t temp=0; + uint16_t i=0; + temp = Flash_ReadSR(); + while((temp&0x01)==0x01) + { + FEED_DOG(); //ι + Delay_Us(100); + temp = Flash_ReadSR(); + i++; + if(i>3000) return 1; + }; + return 0; +} + +/******************************************************************************* +* Function Name : Flash_PowerDown +* Description : Flash ģʽ +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_PowerDown(void) +{ + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_PowerDown); + Delay_Us(3); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_PowerDown +* Description : Flash ѵģʽ +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Wakeup(void) +{ + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_ReleasePowerDown); + Delay_Us(3); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_Erase_Chip +* Description : оƬ +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Erase_Chip(void) +{ + Flash_Write_Enable(); + Flash_Wait_Busy(); + Flash_CS_L; + SPI0_MasterSendByte(P24Q40H_ChipErase); + Flash_CS_H; + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Erase_Block +* Description : +* Input : BLK_ID(0~31) 2M +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Erase_Block(uint32_t BLK_ID) +{ + uint8_t flash_buff[5]; + + BLK_ID*=0x10000; //64K + flash_buff[0] = P24Q40H_BlockErase; + flash_buff[1] = (uint8_t)((BLK_ID >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((BLK_ID >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((BLK_ID) & 0xFF); + flash_buff[4] = 0x00; + + Flash_Write_Enable(); + Flash_Wait_Busy(); + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + Flash_CS_H; + + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Erase_Sector +* Description : +* Input : DST_Addr(0~511) 2M +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Erase_Sector(uint32_t DST_ID) +{ + uint8_t flash_buff[5]; + + DST_ID*=4096; + flash_buff[0] = P24Q40H_SectorErase; + flash_buff[1] = (uint8_t)((DST_ID >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((DST_ID >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((DST_ID) & 0xFF); + flash_buff[4] = 0x00; + + Flash_Write_Enable(); + Flash_Wait_Busy(); + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + Flash_CS_H; + + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Erase_Page +* Description : ҳ +* Input : Page_IDҳ(0~8191) +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Erase_Page(uint32_t Page_ID) +{ + uint8_t flash_buff[5]; + + Page_ID*=256; + flash_buff[0] = P24Q40H_PageErase; + flash_buff[1] = (uint8_t)((Page_ID >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((Page_ID >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((Page_ID) & 0xFF); + flash_buff[4] = 0x00; + + Flash_Write_Enable(); + Flash_Wait_Busy(); + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + Flash_CS_H; + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Erase_Page +* Description : ҳ +* Input : Page_addr:ַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Erase_Pageaddr(uint32_t Page_addr) +{ + uint8_t flash_buff[5]; + + flash_buff[0] = P24Q40H_PageErase; + flash_buff[1] = (uint8_t)((Page_addr >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((Page_addr >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((Page_addr) & 0xFF); + flash_buff[4] = 0x00; + + Flash_Write_Enable(); + Flash_Wait_Busy(); + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + Flash_CS_H; + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Read +* Description : P25Q40H Flash ַָʼȡָȵ +* Input : + pBufferݴ洢 + NumByteToReadҪȡֽ(65535) + ReadAddrȡʼַ(24bit) +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Read(uint8_t* pBuffer,uint16_t NumByteToRead,uint32_t ReadAddr) +{ + uint8_t flash_buff[5]; + + flash_buff[0] = P24Q40H_ReadData; + flash_buff[1] = (uint8_t)((ReadAddr >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((ReadAddr >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((ReadAddr) & 0xFF); + flash_buff[4] = 0x00; + + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + SPI0_DMARecv(pBuffer,NumByteToRead); + Flash_CS_H; +} + +/******************************************************************************* +* Function Name : Flash_Write_Page +* Description : P25Q40H Flash ַָʼдָȵ +* Input : + pBufferݴ洢 + NumByteToReadҪдֽ(256),Ӧóҳʣֽ!!! + ReadAddrȡʼַ(24bit) +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Write_Page(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr) +{ + uint8_t flash_buff[5]; + + flash_buff[0] = P24Q40H_PageProgram; + flash_buff[1] = (uint8_t)((writeAddr >> 16) & 0xFF); + flash_buff[2] = (uint8_t)((writeAddr >> 8) & 0xFF); + flash_buff[3] = (uint8_t)((writeAddr) & 0xFF); + flash_buff[4] = 0x00; + + Flash_Write_Enable(); + Flash_CS_L; + SPI0_DMATrans(flash_buff,0x04); + SPI0_DMATrans(pBuffer,NumByteToWrite); + Flash_CS_H; + Flash_Wait_Busy(); +} + +/******************************************************************************* +* Function Name : Flash_Write_NoCheck +* Description : ޼дP25Q40H FLASH +ע⣺ȷдĵַΧڵȫΪ0XFF,ڷ0XFFдݽʧ! + Զҳ + ַָʼдָȵ,ҪȷַԽ! +* Input : + pBufferݴ洢 + NumByteToReadҪдֽ(65535) + ReadAddrȡʼַ(24bit) +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Write_NoCheck(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t writeAddr) +{ + uint16_t pageremain; + pageremain=256-writeAddr%256; //ҳʣֽ + if(NumByteToWrite<=pageremain) pageremain=NumByteToWrite;//256ֽ + while(1) + { + FEED_DOG(); //ι + + Flash_Write_Page(pBuffer,pageremain,writeAddr); + if(pageremain == NumByteToWrite) break; //д + else { + pBuffer+=pageremain; + writeAddr+=pageremain; + + NumByteToWrite-=pageremain; + if(NumByteToWrite>256) pageremain=256; + else pageremain=NumByteToWrite; + } + }; +} + +/******************************************************************************* +* Function Name : Flash_Write +* Description : ޼дP25Q40H FLASH +ע⣺ȷдĵַΧڵȫΪ0XFF,ڷ0XFFдݽʧ! + Զҳ + ַָʼдָȵ,ҪȷַԽ! +* Input : + pBufferݴ洢 + NumByteToReadҪдֽ(65535) + ReadAddrȡʼַ(24bit) +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void Flash_Write(uint8_t* pBuffer,uint16_t NumByteToWrite,uint32_t WriteAddr) +{ + uint32_t secpos; + uint16_t secoff,secremain,i; + uint8_t* Write_Buff; + + if(NumByteToWrite <= 256*2) + { + + Write_Buff = Temp_Flash_Buff; + + secpos = WriteAddr/256; //ҳַ + secoff = WriteAddr%256; //ڵƫ + secremain = 256 - secoff; //ʣռ + + if(NumByteToWrite<=secremain) secremain = NumByteToWrite; //ǰҳʣռԴ + + while(1) + { + FEED_DOG(); //ι + + Flash_Read(Write_Buff,256,secpos*256); //ȡ + + for(i=0;i 256) secremain = 256; //һҳд + else secremain = NumByteToWrite; //һҳд + } + } + } + else + { + Write_Buff = Temp_Flash_Buff; + + secpos = WriteAddr/4096; //ַ + secoff = WriteAddr%4096; //ڵƫ + secremain = 4096 - secoff; //ʣռ + + if(NumByteToWrite<=secremain) secremain = NumByteToWrite; //ǰʣռԴ + + while(1) + { + FEED_DOG(); //ι + + Flash_Read(Write_Buff,2048,secpos*4096); //ȡ + Flash_Read(Write_Buff+2048,2048,secpos*4096+2048); //ȡ + + for(i=0;i 4096) secremain = 4096; //һд + else secremain = NumByteToWrite; //һд + } + } + } +} + + + + + diff --git a/MCU_Driver/spi_sram.c b/MCU_Driver/spi_sram.c new file mode 100644 index 0000000..93946d5 --- /dev/null +++ b/MCU_Driver/spi_sram.c @@ -0,0 +1,258 @@ +/* + * spi.c + * + * Created on: May 16, 2025 + * Author: cc + */ +#include "spi_sram.h" +#include "debug.h" +#include + +__attribute__((section(".non_0_wait"))) void SPI_SRAM_Init(void) +{ + GPIOA_ModeCfg(GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_11, GPIO_ModeOut_PP); + GPIOA_ModeCfg(GPIO_Pin_5, GPIO_ModeIN_Floating); + + GPIO_PinRemapConfig(GPIO_PartialRemap2_SPI0,ENABLE); + + /*Եó SPI߲30MHZ ֲдSPIͨѶΪ50MHZ 24MHZ*/ + SPI0_MasterInit(24000000); + SPI0_DataMode(Mode0_HighBitINFront); + + SRAM_CE_H; + + /*ȡSRAMоƬID*/ + SRAM_Read_ID_Opeartion(); +} + +/******************************************************************************* +* Function Name : SRAM_Write_Byte +* Description : SRAMдֽ +* Input : + wdate : Ҫдֽ + add ֽдĵַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_Write_Byte(uint8_t wdate,uint32_t add) +{ + uint8_t Hadd16=0x00,Hadd8=0x00,Ladd=0x00; + Ladd=add; + Hadd8=add>>8; + Hadd16=add>>16; + + if(add >= SRAM_ADDRESS_MAX) return ; + + SRAM_CE_L; + SPI0_MasterSendByte(SRAM_CMD_Write); + SPI0_MasterSendByte(Hadd16); + SPI0_MasterSendByte(Hadd8); + SPI0_MasterSendByte(Ladd); + SPI0_MasterSendByte(wdate); + + SRAM_CE_H; +} + +/******************************************************************************* +* Function Name : SRAM_Read_Byte +* Description : SRAMֽ +* Input : + add ȡֽڵĵַ +* Return : ضȡֽ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t SRAM_Read_Byte(uint32_t add) +{ + uint8_t Hadd8=0x00,Hadd16=0x00,Ladd=0x00,rdate=0x00; + Ladd=add; + Hadd8=add>>8; + Hadd16=add>>16; + + if(add >= SRAM_ADDRESS_MAX) return 0x00; + + SRAM_CE_L; + SPI0_MasterSendByte(SRAM_CMD_Read); + SPI0_MasterSendByte(Hadd16); + SPI0_MasterSendByte(Hadd8); + SPI0_MasterSendByte(Ladd); + rdate = SPI0_MasterRecvByte(); + SRAM_CE_H; + + return rdate; +} + +/******************************************************************************* +* Function Name : SRAM_Write_Word +* Description : SRAMдuint16_t -- Сģʽ +* Input : + wdate : Ҫдֽ + add ֽдĵַ +* Return : ضȡֽ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_Write_Word(uint16_t wdate,uint32_t add) +{ + SRAM_Write_Byte((uint8_t)(wdate & 0xFF),add); + SRAM_Write_Byte((uint8_t)((wdate >> 8) & 0xFF),add + 1); +} + +/******************************************************************************* +* Function Name : SRAM_Read_Word +* Description : SRAMдuint16_t -- Сģʽ +* Input : + add ȡֵĵַ +* Return : ضȡ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint16_t SRAM_Read_Word(uint32_t add) +{ + uint16_t rev = 0; + rev = SRAM_Read_Byte(add + 1); + rev <<= 8; + rev |= SRAM_Read_Byte(add); + return rev; +} + +/******************************************************************************* +* Function Name : SRAM_Write_DW +* Description : SRAMдuint32_t -- Сģʽ +* Input : + wdate : Ҫд˫ + add ˫дĵַ +* Return : ضȡ˫ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_Write_DW(uint32_t wdate,uint32_t add) +{ + SRAM_Write_Byte((uint8_t)(wdate & 0xFF),add); + SRAM_Write_Byte((uint8_t)((wdate >> 8) & 0xFF),add + 1); + SRAM_Write_Byte((uint8_t)((wdate >> 16) & 0xFF),add + 2); + SRAM_Write_Byte((uint8_t)((wdate >> 24) & 0xFF),add + 3); +} + +/******************************************************************************* +* Function Name : SRAM_Read_DW +* Description : SRAMдuint32_t -- Сģʽ +* Input : + add ȡ˫ֵĵַ +* Return : ضȡ˫ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint32_t SRAM_Read_DW(uint32_t add) +{ + uint32_t rev = 0; + + rev = SRAM_Read_Byte(add + 3); + rev <<= 8; + rev |= SRAM_Read_Byte(add + 2); + rev <<= 8; + rev |= SRAM_Read_Byte(add + 1); + rev <<= 8; + rev |= SRAM_Read_Byte(add); + + return rev; +} + +/******************************************************************************* +* Function Name : SRAM_Read_ID_Opeartion +* Description : SRAM ȡоƬID +* Input : NULL +* Return : ضȡ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t SRAM_Read_ID_Opeartion(void) +{ + uint8_t spi_addr[5]; + uint8_t read_id[9]; + + memset(spi_addr,0,0x05); + memset(read_id,0,0x04); + + spi_addr[0] = SRAM_CMD_Read_ID; + spi_addr[1] = 0x00 ; + spi_addr[2] = 0x00 ; + spi_addr[3] = 0x00 ; + + SRAM_CE_L; + SPI0_DMATrans(spi_addr,0x04); + SPI0_DMARecv(read_id,0x08); + SRAM_CE_H; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM MFID:%02X",read_id[0]); + if(read_id[1] == 0x5D) + { + Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%02X - Known Good Die PASS",read_id[1]); + }else { + Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%02X - Known Good Die FAIL",read_id[1]); + } + Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit, "SRAM EID:",&read_id[2],0x06); + + return 0; +} + +/******************************************************************************* +* Function Name : SRAM_Reset_Operation +* Description : SRAM λ - ͨλ +* Input : NULL +* Return : NULL +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_Reset_Operation(void) +{ + SRAM_CE_L; + SPI0_MasterSendByte(SRAM_CMD_Reset_Enable); + SRAM_CE_H; + //Delay_Ms(2); + SRAM_CE_L; + SPI0_MasterSendByte(SRAM_CMD_Reset); + SRAM_CE_H; +} + +/******************************************************************************* +* Function Name : SRAM_DMA_Write_Buff +* Description : SRAM DMAʽд +* Input : + wbuff : Ҫд + len : дݵij -- 4095ֽڳ + add ֽдĵַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add) +{ + uint8_t spi_addr[5]; + + if(add + len >= SRAM_ADDRESS_MAX) return ; + + memset(spi_addr,0,0x05); + + spi_addr[0] = SRAM_CMD_Write; + spi_addr[1] = (add >> 16) & 0xFF ; + spi_addr[2] = (add >> 8) & 0xFF ; + spi_addr[3] = (add) & 0xFF ; + + SRAM_CE_L; + SPI0_DMATrans(spi_addr,0x04); + SPI0_DMATrans(wbuff,len); + SRAM_CE_H; +} + +/******************************************************************************* +* Function Name : SRAM_DMA_Read_Buff +* Description : SRAM DMAʽȡ +* Input : + rbuff : Ҫȡ + len : ȡݵij -- 4095ֽڳ + add ֽдĵַ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add) +{ + uint8_t spi_addr[5]; + + if(add + len >= SRAM_ADDRESS_MAX) return ; + + memset(spi_addr,0,0x05); + + spi_addr[0] = SRAM_CMD_Read; + spi_addr[1] = (add >> 16) & 0xFF ; + spi_addr[2] = (add >> 8) & 0xFF ; + spi_addr[3] = (add) & 0xFF ; + + SRAM_CE_L; + SPI0_DMATrans(spi_addr,0x04); + SPI0_DMARecv(rbuff,len); + SRAM_CE_H; +} + diff --git a/MCU_Driver/timer.c b/MCU_Driver/timer.c new file mode 100644 index 0000000..d210eb5 --- /dev/null +++ b/MCU_Driver/timer.c @@ -0,0 +1,51 @@ +/* + * timer.c + * + * Created on: May 16, 2025 + * Author: cc + */ +#include "timer.h" +#include +#include + + + +void TIMER0_Init(void) +{ + TMR0_DeInit(); + TMR0_TimerInit(SystemCoreClock / 10000); + TMR0_ITCfg(RB_TMR_IF_CYC_END, ENABLE); + NVIC_EnableIRQ(TIM0_IRQn); + TMR0_Enable(); +} + +volatile uint32_t Time0_100us = 0; +volatile uint32_t Time0_1ms = 0; + +void __attribute__((interrupt("WCH-Interrupt-fast"))) TIM0_IRQHandler() +{ + static uint8_t NUM_1 = 0; + + TMR0_ClearITFlag(RB_TMR_IF_CYC_END); + + Time0_100us++; + NUM_1++; + + if(NUM_1 >= 10){ + NUM_1 = 0; + Time0_1ms++; + } +} + +void Timer0_Task(void) +{ + static uint32_t timer0_tick = 0; + + if(Time0_1ms - timer0_tick >= 1000 ){ + timer0_tick = Time0_1ms; + + printf("Run:%d ..",timer0_tick); + } +} + + diff --git a/MCU_Driver/uart.c b/MCU_Driver/uart.c new file mode 100644 index 0000000..31fbe6b --- /dev/null +++ b/MCU_Driver/uart.c @@ -0,0 +1,878 @@ +/* + * uart.c + * + * Created on: May 14, 2025 + * Author: cc + */ + +#include "uart.h" +#include "debug.h" +#include "watchdog.h" +#include "blv_rs485_protocol.h" +#include "sram_mem_addr.h" +#include "spi_sram.h" +#include + +UART_t g_uart[UART_MAX]; + +void UART0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void UART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void UART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void UART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + + +/********************************************************************* + * @fn UARTx_Init + * @brief UARTʼע⴮2ͨѶPB22,PB23 - Boot,RST + * @param uart_id - ID + * @param buad - + * @param prt_cf - ڽջص + * @return none + */ +__attribute__((section(".non_0_wait"))) void UARTx_Init(UART_IDX uart_id, uint32_t buad) { + + switch (uart_id) { + case UART_0: + /* ô1IOģʽ */ + UART0_BaudRateCfg(buad); + R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART0_LCR = RB_LCR_WORD_SZ; + R8_UART0_IER = RB_IER_TXD_EN; + + GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating); + + UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART0_IRQn); + + memset(&g_uart[UART_0],0,sizeof(UART_t)); + Set_Uart_recvTimeout(&g_uart[UART_0],buad); + + break; + case UART_1: + /* ô1IOģʽ */ + UART1_BaudRateCfg(buad); + R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; + + GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating); + + UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART1_IRQn); + + memset(&g_uart[UART_1],0,sizeof(UART_t)); + Set_Uart_recvTimeout(&g_uart[UART_1],buad); + + break; + case UART_2: + UART2_BaudRateCfg(buad); + R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART2_LCR = RB_LCR_WORD_SZ; + R8_UART2_IER = RB_IER_TXD_EN; + GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating); + + UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART2_IRQn); + + memset(&g_uart[UART_2],0,sizeof(UART_t)); + Set_Uart_recvTimeout(&g_uart[UART_2],buad); + + break; + case UART_3: + UART3_BaudRateCfg(buad); + R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART3_LCR = RB_LCR_WORD_SZ; + R8_UART3_IER = RB_IER_TXD_EN; + GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating); + + UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART3_IRQn); + + memset(&g_uart[UART_3],0,sizeof(UART_t)); + Set_Uart_recvTimeout(&g_uart[UART_3],buad); + + break; + + } +} + +__attribute__((section(".non_0_wait"))) void Set_Uart_recvTimeout(UART_t *set_uart,uint32_t baud) +{ + if(baud == 115200) + { + set_uart->RecvTimeout = Recv_115200_TimeOut; + }else if(baud == 9600) + { + set_uart->RecvTimeout = Recv_9600_TimeOut; + }else if(baud == 2400) + { + set_uart->RecvTimeout = Recv_2400_TimeOut; + }else + { + set_uart->RecvTimeout = 20; + } +} + +/********************************************************************* + * @fn USART1_IRQHandler + * + * @brief USART1жϺ + * + * @return none + */ +void UART0_IRQHandler(void) +{ + switch( UART0_GetITFlag() ) + { + case UART_II_THR_EMPTY: + + break; + case UART_II_RECV_RDY: + case UART_II_RECV_TOUT: + if( (g_uart[UART_0].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_0].RecvLen = 0x00; + g_uart[UART_0].RecvBuffer[g_uart[UART_0].RecvLen] = UART0_RecvByte(); + g_uart[UART_0].RecvLen += 1; + g_uart[UART_0].Receiving = 0x01; + g_uart[UART_0].RecvIdleTiming = SysTick_1ms; + break; + } + +} + +/********************************************************************* + * @fn USART1_IRQHandler + * + * @brief USART1жϺ + * + * @return none + */ +void UART1_IRQHandler(void) +{ + switch( UART1_GetITFlag() ) + { + case UART_II_THR_EMPTY: + + break; + case UART_II_RECV_RDY: + case UART_II_RECV_TOUT: + if( (g_uart[UART_1].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_1].RecvLen = 0x00; + g_uart[UART_1].RecvBuffer[g_uart[UART_1].RecvLen] = UART1_RecvByte(); + g_uart[UART_1].RecvLen += 1; + g_uart[UART_1].Receiving = 0x01; + g_uart[UART_1].RecvIdleTiming = SysTick_1ms; + break; + } +} + +/********************************************************************* + * @fn UART2_IRQHandler + * + * @brief USART2жϺ + * + * @return none + */ +void UART2_IRQHandler(void) +{ + switch( UART2_GetITFlag() ) + { + case UART_II_THR_EMPTY: + + break; + case UART_II_RECV_RDY: + case UART_II_RECV_TOUT: + if( (g_uart[UART_2].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_2].RecvLen = 0x00; + g_uart[UART_2].RecvBuffer[g_uart[UART_2].RecvLen] = UART2_RecvByte(); + g_uart[UART_2].RecvLen += 1; + g_uart[UART_2].Receiving = 0x01; + g_uart[UART_2].RecvIdleTiming = SysTick_1ms; + break; + } +} + +/********************************************************************* + * @fn USART3_IRQHandler + * + * @brief USART3жϺ + * + * @return none + */ +void UART3_IRQHandler(void) +{ + switch( UART3_GetITFlag() ) + { + case UART_II_THR_EMPTY: + + break; + case UART_II_RECV_RDY: + case UART_II_RECV_TOUT: + if( (g_uart[UART_3].RecvLen + 1) >= USART_BUFFER_SIZE ) g_uart[UART_3].RecvLen = 0x00; + g_uart[UART_3].RecvBuffer[g_uart[UART_3].RecvLen] = UART3_RecvByte(); + g_uart[UART_3].RecvLen += 1; + g_uart[UART_3].Receiving = 0x01; + g_uart[UART_3].RecvIdleTiming = SysTick_1ms; + break; + } +} + +/********************************************************************* + * @fn USART1_RECEIVE + * + * @brief USART1 + * + * @return none + */ +__attribute__((section(".non_0_wait"))) void UART0_RECEIVE(void) +{ + if(g_uart[UART_0].Receiving == 0x01) + { + if(SysTick_1ms - g_uart[UART_0].RecvIdleTiming >= g_uart[UART_0].RecvTimeout) + { + g_uart[UART_0].RecvIdleTiming = SysTick_1ms; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART_0 Len %d ",g_uart[UART_0].RecvLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"UART_0 Buff:", g_uart[UART_0].RecvBuffer,g_uart[UART_0].RecvLen); + + + + g_uart[UART_0].RecvLen = 0; + g_uart[UART_0].Receiving = 0; + } + } +} + +/********************************************************************* + * @fn USART1_RECEIVE + * + * @brief USART1 + * + * @return none + */ +__attribute__((section(".non_0_wait"))) void UART1_RECEIVE(void) +{ + if(g_uart[UART_1].Receiving == 0x01) + { + if(SysTick_1ms - g_uart[UART_1].RecvIdleTiming >= g_uart[UART_1].RecvTimeout) + { + g_uart[UART_1].RecvIdleTiming = SysTick_1ms; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART_1 Len %d ",g_uart[UART_1].RecvLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"UART_1 Buff:", g_uart[UART_1].RecvBuffer,g_uart[UART_1].RecvLen); + + + + g_uart[UART_1].RecvLen = 0; + g_uart[UART_1].Receiving = 0; + } + } +} + + + +/********************************************************************* + * @fn UART2_RECEIVE + * + * @brief USART2 + * + * @return none + */ +__attribute__((section(".non_0_wait"))) void UART2_RECEIVE(void) +{ + if(g_uart[UART_2].Receiving == 1) + { + if(SysTick_1ms - g_uart[UART_2].RecvIdleTiming > g_uart[UART_2].RecvTimeout) + { + g_uart[UART_2].RecvIdleTiming = SysTick_1ms; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART_2 Len %d ",g_uart[UART_2].RecvLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"UART_2 Buff:", g_uart[UART_2].RecvBuffer,g_uart[UART_2].RecvLen); + + + + g_uart[UART_2].RecvLen = 0; + g_uart[UART_2].Receiving = 0; + } + } +} + + + +/********************************************************************* + * @fn USART3_RECEIVE + * + * @brief UART3 + * + * @return none + */ +__attribute__((section(".non_0_wait"))) void UART3_RECEIVE(void) +{ + if(g_uart[UART_3].Receiving == 1) + { + if(SysTick_1ms - g_uart[UART_3].RecvIdleTiming > g_uart[UART_3].RecvTimeout) + { + g_uart[UART_3].RecvIdleTiming = SysTick_1ms; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"UART_3 Len %d ",g_uart[UART_3].RecvLen); + Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit,"UART_3 Buff:", g_uart[UART_3].RecvBuffer,g_uart[UART_3].RecvLen); + + + + g_uart[UART_3].RecvLen = 0; + g_uart[UART_3].Receiving = 0; + } + } +} + +/********************************************************************* + * @fn UART0_ChangeBaud + * + * @brief UART0л + * + * @return none + */ +uint8_t UART0_ChangeBaud(uint32_t baudrate) +{ + uint16_t delay_num = 0; + + while(1) + { + if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP ) + { + /*Ϊ*/ + __disable_irq(); + + UART0_Reset(); + + GPIO_PinRemapConfig(GPIO_NoRemap_UART0,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_9, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_8, GPIO_ModeIN_Floating); + + UART0_BaudRateCfg(baudrate); + R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART0_LCR = RB_LCR_WORD_SZ; + R8_UART0_IER = RB_IER_TXD_EN; + + UART0_CLR_RXFIFO(); + UART0_CLR_TXFIFO(); + + UART0_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART0_IRQn); + + Set_Uart_recvTimeout(&g_uart[UART_0],baudrate); + + __enable_irq(); + + return 0; + } + + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + return 1; +} + +/********************************************************************* + * @fn UART1_ChangeBaud + * + * @brief UART1л + * + * @return none + */ +uint8_t UART1_ChangeBaud(uint32_t baudrate) +{ + uint16_t delay_num = 0; + + while(1) + { + if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP ) + { + /*Ϊ*/ + __disable_irq(); + + UART1_Reset(); + + GPIO_PinRemapConfig(GPIO_NoRemap_UART1,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_11, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_10, GPIO_ModeIN_Floating); + + UART1_BaudRateCfg(baudrate); + R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; + + UART1_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART1_IRQn); + + Set_Uart_recvTimeout(&g_uart[UART_1],baudrate); + + __enable_irq(); + + return 0; + } + + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + return 1; +} + +/********************************************************************* + * @fn UART2_ChangeBaud + * + * @brief UART2л + * + * @return none + */ +uint8_t UART2_ChangeBaud(uint32_t baudrate) +{ + uint16_t delay_num = 0; + + while(1) + { + if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP ) + { + /*Ϊ*/ + __disable_irq(); + + UART2_Reset(); + + GPIO_PinRemapConfig(GPIO_PartialRemap1_UART2,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_14, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_12, GPIO_ModeIN_Floating); + + UART2_BaudRateCfg(baudrate); + R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART2_LCR = RB_LCR_WORD_SZ; + R8_UART2_IER = RB_IER_TXD_EN; + + UART2_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART2_IRQn); + + Set_Uart_recvTimeout(&g_uart[UART_2],baudrate); + + __enable_irq(); + + return 0; + } + + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + return 1; +} + +/********************************************************************* + * @fn UART3_ChangeBaud + * + * @brief UART3л + * + * @return none + */ +uint8_t UART3_ChangeBaud(uint32_t baudrate) +{ + uint16_t delay_num = 0; + + while(1) + { + if( UART0_GetLinSTA() & RB_LSR_TX_ALL_EMP ) + { + /*Ϊ*/ + __disable_irq(); + + UART3_Reset(); + + GPIO_PinRemapConfig(GPIO_PartialRemap1_UART3,ENABLE); + GPIOB_ModeCfg(GPIO_Pin_19, GPIO_ModeOut_PP); + GPIOB_ModeCfg(GPIO_Pin_18, GPIO_ModeIN_Floating); + + UART3_BaudRateCfg(baudrate); + R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART3_LCR = RB_LCR_WORD_SZ; + R8_UART3_IER = RB_IER_TXD_EN; + + UART3_INTCfg(ENABLE, RB_IER_RECV_RDY | RB_IER_THR_EMPTY); + NVIC_EnableIRQ(UART3_IRQn); + + Set_Uart_recvTimeout(&g_uart[UART_3],baudrate); + + __enable_irq(); + + return 0; + } + + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + return 1; +} + +/******************************************************************************* +* Function Name : Uart0_Flush +* Description : 0ȴ +* Input : over_time -- ȴʱʱ +* Return : None +*******************************************************************************/ +void Uart0_Flush(uint16_t over_time) +{ + uint16_t delay_num = 0; + + //ȴ - 50ms + while(1) + { + WDT_Feed(); //ֹŹλ + if( (R8_UART0_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > over_time) break; + } +} + +/******************************************************************************* +* Function Name : Uart1_Flush +* Description : 1ȴ +* Input : over_time -- ȴʱʱ +* Return : None +*******************************************************************************/ +void Uart1_Flush(uint16_t over_time) +{ + uint16_t delay_num = 0; + + //ȴ - 50ms + while(1) + { + WDT_Feed(); //ֹŹλ + if( (R8_UART1_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > over_time) break; + } +} + +/******************************************************************************* +* Function Name : Uart2_Flush +* Description : 2ȴ +* Input : over_time -- ȴʱʱ +* Return : None +*******************************************************************************/ +void Uart2_Flush(uint16_t over_time) +{ + uint16_t delay_num = 0; + + //ȴ - 50ms + while(1) + { + WDT_Feed(); //ֹŹλ + if( (R8_UART2_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > over_time) break; + } +} + +/******************************************************************************* +* Function Name : Uart3_Flush +* Description : 3ȴ +* Input : over_time -- ȴʱʱ +* Return : None +*******************************************************************************/ +void Uart3_Flush(uint16_t over_time) +{ + uint16_t delay_num = 0; + + //ȴ - 50ms + while(1) + { + WDT_Feed(); //ֹŹλ + if( (R8_UART3_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > over_time) break; + } +} + +/******************************************************************************* +* Function Name : Uart_SendString +* Description : ڷͺ +* Input : +* uart_id - ͵Ĵں +* buff - +* len - ݳ +* Return : None +*******************************************************************************/ +void Uart_SendString(uint8_t uart_id,uint8_t* buff,uint16_t len) +{ + switch(uart_id) + { + case UART_0: + UART0_SendString(buff,len); + break; + case UART_1: + UART1_SendString(buff,len); + break; + case UART_2: + UART2_SendString(buff,len); + break; + case UART_3: + UART3_SendString(buff,len); + break; + default: + break; + } +} + +/******************************************************************************* +* Function Name : MCU485_SendString_1 +* Description : 485_1 ͺ +* Input : + buf - + l - ݳ +* Return : None +*******************************************************************************/ +void MCU485_SendString_1(uint8_t *buf, uint16_t len) +{ + uint16_t delay_num = 0; + + MCU485_EN1_H; + + UART1_SendString(buf,len); + + //ȴ - 50ms + while(1) + { + WDT_Feed(); + if( (R8_UART1_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + MCU485_EN1_L; +} + +/******************************************************************************* +* Function Name : MCU485_SendString_2 +* Description : 485_2 ͺ +* Input : + buf - + len - ݳ +* Return : None +*******************************************************************************/ +void MCU485_SendString_2(uint8_t *buf, uint16_t len) +{ + uint16_t delay_num = 0; + + MCU485_EN2_H; + + UART2_SendString(buf,len); + + //ȴ - 50ms + while(1) + { + WDT_Feed(); + if( (R8_UART2_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + MCU485_EN2_L; +} + +/******************************************************************************* +* Function Name : MCU485_SendString_3 +* Description : 485_3 ͺ +* Input : + buf - + len - ݳ +* Return : None +*******************************************************************************/ +void MCU485_SendString_3(uint8_t *buf, uint16_t len) +{ + uint16_t delay_num = 0; + + MCU485_EN3_H; + + UART3_SendString(buf,len); + + //ȴ - 50ms + while(1) + { + WDT_Feed(); + if( (R8_UART3_LSR & RB_LSR_TX_ALL_EMP) != 0x00 ) break; //жϷFIFOΪ,ͬʱFIFOΪ + Delay_Us(100); + delay_num++; + if(delay_num > 500) break; + } + + MCU485_EN3_L; +} + +/******************************************************************************* +* Function Name : MCU485_SendString +* Description : 485ͺ +* Input : uart_id - ͵Ĵں + buff - + len -- ݳ +* Return : None +*******************************************************************************/ +void MCU485_SendString(uint8_t uart_id,uint8_t* buff,uint16_t len) +{ + switch(uart_id) + { + case UART_1: + if(Poll485_Info.port_mode == Port_Monitoring_mode ) //ѯ˿ + { + //Udp_Internal_SeriaNet_Uploading2(Polling_Port,Poll485_Info.baud,buff,len); + } + MCU485_SendString_1(buff,len); + break; + case UART_2: + if(Act485_Info.port_mode == Port_Monitoring_mode ) //ѯ˿ + { + //Udp_Internal_SeriaNet_Uploading2(Active_Port,Act485_Info.baud,buff,len); + } + MCU485_SendString_2(buff,len); + break; + case UART_3: + if(BUS485_Info.port_mode == Port_Monitoring_mode ) //ѯ˿ + { + //Udp_Internal_SeriaNet_Uploading2(Bus_port,BUS485_Info.baud,buff,len); + } + MCU485_SendString_3(buff,len); + break; + } +} + +/******************************************************************************* +* Function Name : MCU485_SendString +* Description : 485ͺ +* Input : uart_id - ͵Ĵں + data_addr - SRAMзݵַ + len -- ݳ +* Return : None +*******************************************************************************/ +void MCU485_SendSRAMData(uint8_t uart_id,uint32_t data_addr,uint16_t len) +{ + uint16_t buff_len = len; + uint8_t send_buff[buff_len]; + + memset(send_buff,0,sizeof(send_buff)); + + SRAM_DMA_Read_Buff(send_buff,buff_len,data_addr); //ȡ + + MCU485_SendString(uart_id,send_buff,buff_len); +} + +/******************************************************************************* +* Function Name : Write_Uart_SendBuff +* Description : дuartͻ +* Input : uart_id - ͵Ĵں + uart_baud - + buff - + len -- ݳ +*******************************************************************************/ +void Write_Uart_SendBuff(uint8_t uart_id,uint8_t uart_outime,uint8_t* buff,uint16_t len) +{ + switch(uart_id) + { + case Polling_Port: //ѯ + uart_id = UART_0; + break; + case Active_Port: // + uart_id = UART_2; + break; + case Bus_port: //bus + uart_id = UART_3; + break; + } + switch(uart_id) + { + case UART_0: + /*ݳ*/ + SRAM_Write_Word(len,g_uart[UART_0].TX_Buffer_WriteAddr); + + /*ݷ - ȴظʱ , λS*/ + SRAM_Write_Byte(uart_outime,g_uart[UART_0].TX_Buffer_WriteAddr+2); + /**/ + SRAM_DMA_Write_Buff(buff,len,g_uart[UART_0].TX_Buffer_WriteAddr+3); + + g_uart[UART_0].TX_Buffer_WriteAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_0].TX_Buffer_WriteAddr > SRAM_UART0_SendBuffer_End_Addr) g_uart[UART_0].TX_Buffer_WriteAddr = SRAM_UART0_SendBuffer_Start_Addr; + break; + case UART_1: + /*ݳ*/ + SRAM_Write_Word(len,g_uart[UART_1].TX_Buffer_WriteAddr); + /*ݷ - ȴظʱ , λS*/ + SRAM_Write_Byte(uart_outime,g_uart[UART_1].TX_Buffer_WriteAddr+2); + /**/ + SRAM_DMA_Write_Buff(buff,len,g_uart[UART_1].TX_Buffer_WriteAddr+3); + + g_uart[UART_1].TX_Buffer_WriteAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_1].TX_Buffer_WriteAddr > SRAM_UART1_SendBuffer_End_Addr) g_uart[UART_1].TX_Buffer_WriteAddr = SRAM_UART1_SendBuffer_Start_Addr; + break; + case UART_2: + /*ݳ*/ + SRAM_Write_Word(len,g_uart[UART_2].TX_Buffer_WriteAddr); + /*ݷ - ȴظʱ , λS*/ + SRAM_Write_Byte(uart_outime,g_uart[UART_2].TX_Buffer_WriteAddr+2); + /**/ + SRAM_DMA_Write_Buff(buff,len,g_uart[UART_2].TX_Buffer_WriteAddr+3); + + g_uart[UART_2].TX_Buffer_WriteAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_2].TX_Buffer_WriteAddr > SRAM_UART2_SendBuffer_End_Addr) g_uart[UART_2].TX_Buffer_WriteAddr = SRAM_UART2_SendBuffer_Start_Addr; + break; + case UART_3: + /*ݳ*/ + SRAM_Write_Word(len,g_uart[UART_3].TX_Buffer_WriteAddr); + /*ݷ - ȴظʱ , λS*/ + SRAM_Write_Byte(uart_outime,g_uart[UART_3].TX_Buffer_WriteAddr+2); + /**/ + SRAM_DMA_Write_Buff(buff,len,g_uart[UART_3].TX_Buffer_WriteAddr+3); + + g_uart[UART_3].TX_Buffer_WriteAddr += SRAM_Uart_Buffer_Size; + if(g_uart[UART_3].TX_Buffer_WriteAddr > SRAM_UART3_SendBuffer_End_Addr) g_uart[UART_3].TX_Buffer_WriteAddr = SRAM_UART3_SendBuffer_Start_Addr; + break; + default: + break; + } +} + + + + + + + + + + + + + + + + + diff --git a/MCU_Driver/watchdog.c b/MCU_Driver/watchdog.c new file mode 100644 index 0000000..af7275f --- /dev/null +++ b/MCU_Driver/watchdog.c @@ -0,0 +1,42 @@ +/* + * watchdog.c + * + * Created on: Nov 12, 2025 + * Author: cc + */ +#include "watchdog.h" + +/******************************************************************************* +* Function Name : WDT_Init +* Description : Źʼ ŹһʱΪ4ms +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WDT_Init(void) +{ +// WWDG_ResetCfg(ENABLE); +// WWDG_SetCounter(WDT_NUM); +} + +/******************************************************************************* +* Function Name : WDT_Feed +* Description : Źι +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WDT_Feed(void) +{ + //WWDG_ClearFlag(); +// WWDG_SetCounter(WDT_NUM); +} + +/******************************************************************************* +* Function Name : WDT_Reinit +* Description : Źȥʼ ŹһʱΪ4ms +* Input : None +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WDT_Reinit(void) +{ + +} diff --git a/NetLib/eth_driver.c b/NetLib/eth_driver.c new file mode 100644 index 0000000..0dd4041 --- /dev/null +++ b/NetLib/eth_driver.c @@ -0,0 +1,698 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : eth_driver.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/05 +* Description : eth program body. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#include +#include "eth_driver.h" +#include "net_config.h" + +__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/ +__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */ + +__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */ +__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */ + +__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */ +__attribute__((__aligned__(4))) uint8_t RemoteIp[4]; /* DNS information table, 4-byte alignment */ +const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW, + WCHNET_NUM_UDP, + WCHNET_NUM_TCP, + WCHNET_NUM_TCP_LISTEN, + WCHNET_NUM_TCP_SEG, + WCHNET_NUM_IP_REASSDATA, + WCHNET_NUM_PBUF, + WCHNET_NUM_POOL_BUF + }; +const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF), + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF) + }; +__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE]; +__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE]; +__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE]; + +uint16_t gPHYAddress; +volatile uint32_t LocalTime; +volatile uint8_t PhyWaitNegotiationSuc = 0; +ETH_DMADESCTypeDef *pDMARxSet; +ETH_DMADESCTypeDef *pDMATxSet; + +volatile uint8_t LinkSta = 0; //0:Link down 1:Link up +uint8_t LinkVaildFlag = 0; //0:invalid 1:valid +uint8_t AccelerateLinkFlag = 0; //0:invalid 1:valid +uint8_t LinkProcessingStep = 0; +uint32_t LinkProcessingTime = 0; +uint32_t TaskExecutionTime = 0; +void ETH_LinkDownCfg(void); +/********************************************************************* + * @fn WCHNET_TimeIsr + * + * @brief + * + * @return none. + */ +void WCHNET_TimeIsr( uint16_t timperiod ) +{ + LocalTime += timperiod; +} + +/********************************************************************* + * @fn WCHNET_QueryPhySta + * + * @brief Query external PHY status + * + * @return none. + */ + +void WCHNET_QueryPhySta(void) +{ + if(PhyWaitNegotiationSuc) + { + ETH_PHYLink(); + } +} + +/********************************************************************* + * @fn WCHNET_CheckPHYPN + * + * @brief check PHY PN polarity + * + * @return none. + */ +void WCHNET_CheckPHYPN(uint16_t time) +{ + uint16_t phy_stat; + //check PHY PN + if((LinkProcessingStep == 0)||(LocalTime >= LinkProcessingTime)) + { + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 ); + phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS1); + if(phy_stat & (1<<4)) + { + if(LinkProcessingStep == 0) + { + LinkProcessingStep = 1; + LinkProcessingTime = LocalTime + time; + } + else { + LinkProcessingStep = 0; + LinkProcessingTime = 0; + phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_ANER); + if((time == 200) || ((phy_stat & 1) == 0)) + { + phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_CONTROL1); + phy_stat |= 1; + ETH_WritePHYRegister(gPHYAddress, PHY_CONTROL1, phy_stat ); + } + } + } + else { + LinkProcessingStep = 0; + LinkProcessingTime = 0; + } + } +} + +/********************************************************************* + * @fn WCHNET_AccelerateLink + * + * @brief accelerate Link processing + * + * @return none. + */ +void WCHNET_AccelerateLink(void) +{ + uint16_t phy_stat; + if(AccelerateLinkFlag == 0) + { + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, 99 ); + phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x19); + if((phy_stat & 0xf) == 3) + { + AccelerateLinkFlag = 1; + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 ); + phy_stat = 0x4; + ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat ); + } + } +} + +/********************************************************************* + * @fn WCHNET_CheckLinkVaild + * + * @brief check whether Link is valid + * + * @return none. + */ +void WCHNET_CheckLinkVaild(void) +{ + uint16_t phy_stat, phy_bcr; + + if(LinkVaildFlag == 0) + { + phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR); + if((phy_bcr & (1<<13)) == 0) //Do nothing if Link mode is 10M. + { + LinkVaildFlag = 1; + LinkProcessingTime = 0; + return; + } + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, 99 ); + phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1b); + if((phy_stat & (1<<2)) == 0) + { + LinkProcessingTime++; + if(LinkProcessingTime == 5) + { + LinkProcessingTime = 0; + phy_stat = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR); + ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset ); + Delay_Us(100); + ETH_WritePHYRegister(gPHYAddress, PHY_BCR, phy_stat ); + ETH_LinkDownCfg(); + } + } + else { + LinkVaildFlag = 1; + LinkProcessingTime = 0; + } + } +} + +/********************************************************************* + * @fn WCHNET_LinkProcessing + * + * @brief process Link stage task + * + * @return none. + */ +void WCHNET_LinkProcessing(void) +{ + u16 phy_bcr; + + if(LocalTime >= TaskExecutionTime) + { + TaskExecutionTime = LocalTime + 10; //execution cycle:10ms + if(LinkSta == 0) //Link down + { + phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR); + if(phy_bcr & PHY_AutoNegotiation) //auto-negotiation is enabled + { + WCHNET_CheckPHYPN(300); //check PHY PN + WCHNET_AccelerateLink(); //accelerate Link processing + } + else { //auto-negotiation is disabled + if((phy_bcr & (1<<13)) == 0) // 10M + { + WCHNET_CheckPHYPN(200); //check PHY PN + } + } + } + else { //Link up + WCHNET_CheckLinkVaild(); //check whether Link is valid + } + } +} + +/********************************************************************* + * @fn WCHNET_MainTask + * + * @brief library main task function + * + * @param none. + * + * @return none. + */ +void WCHNET_MainTask(void) +{ + WCHNET_NetInput( ); /* Ethernet data input */ + WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */ + WCHNET_QueryPhySta(); + WCHNET_LinkProcessing(); +} + +/********************************************************************* + * @fn ETH_LinkUpCfg + * + * @brief When the PHY is connected, configure the relevant functions. + * + * @param none. + * + * @return none. + */ +void ETH_LinkUpCfg(void) +{ + uint16_t phy_stat; + + LinkSta = 1; + AccelerateLinkFlag = 0; + LinkProcessingStep = 0; + LinkProcessingTime = 0; + PhyWaitNegotiationSuc = 0; + ETH_Start( ); + + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 ); + phy_stat = 0x0; + ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat ); +} + +/********************************************************************* + * @fn ETH_LinkDownCfg + * + * @brief When the PHY is disconnected, configure the relevant functions. + * + * @param none. + * + * @return none. + */ +void ETH_LinkDownCfg(void) +{ + LinkSta = 0; + LinkVaildFlag = 0; + LinkProcessingTime = 0; +} + +/********************************************************************* + * @fn ETH_PHYLink + * + * @brief Configure MAC parameters after the PHY Link is successful. + * + * @param none. + * + * @return none. + */ +void ETH_PHYLink( void ) +{ + uint32_t phy_stat, phy_anlpar, phy_bcr; + + phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR ); + phy_anlpar = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_ANLPAR); + phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR); + WCHNET_PhyStatus( phy_stat ); + + if(phy_stat & PHY_Linked_Status) //LinkUp + { + if(phy_bcr & PHY_AutoNegotiation) + { + if(phy_anlpar == 0) + { + ETH_LinkUpCfg(); + } + else { + if(phy_stat & PHY_AutoNego_Complete) + { + ETH_LinkUpCfg(); + } + else{ + PhyWaitNegotiationSuc = 1; + } + } + } + else { + ETH_LinkUpCfg(); + } + } + else { //LinkDown + /*Link down*/ + ETH_LinkDownCfg(); + } +} + +/********************************************************************* + * @fn ETH_CheckPhyInterruptStatus + * + * @brief MAC check PHY interrupt status. + * + * @param none. + * + * @return none. + */ +void ETH_CheckPhyInterruptStatus( void ) +{ + uint16_t phyIntStat; + + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE17 ); + phyIntStat = ETH_ReadPHYRegister( gPHYAddress, PHY_WOL_STATUS); + + if(phyIntStat & WOL_DONE_INT) + { + /* Wol done */ + } + else /* Link status change*/ + { + ETH_PHYLink(); + } + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 ); + phyIntStat = ETH_ReadPHYRegister( gPHYAddress, 0x1E); /* Clear the Interrupt status */ +} + +/********************************************************************* + * @fn PHY_InterruptInit + * + * @brief Configure PHY interrupt function + * + * @param none. + * + * @return none. + */ +void PHY_InterruptInit(void) +{ + uint16_t RegValue; + + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE7 ); + /* Configure interrupt function */ + RegValue = ETH_ReadPHYRegister(gPHYAddress, PHY_INTERRUPT_MASK); + RegValue |= 0x01 << 13; + ETH_WritePHYRegister(gPHYAddress, PHY_INTERRUPT_MASK, RegValue ); + /* Clear the Interrupt status */ + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 ); + ETH_ReadPHYRegister( gPHYAddress, PHY_INTERRUPT_IND); +} + +/********************************************************************* + * @fn PHY_LEDCfg + * + * @brief Configure PHY LED function + * + * @param none. + * + * @return none. + */ +void PHY_LEDCfg(void) +{ + uint16_t RegValue; + + ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE7 ); + //turn on LED--PHY + RegValue = ETH_ReadPHYRegister(gPHYAddress, PHY_INTERRUPT_MASK); + RegValue |= 1<<9; + ETH_WritePHYRegister(gPHYAddress, PHY_INTERRUPT_MASK, RegValue ); + + //link_ledӳ䵽PB17 + R32_AFIO_PCFR1 |= 1<<30; + + //act_ledӳ䵽PB6 + R32_AFIO_PCFR2 |= 1<<1; + + //turn on LED--MCU һĴCH564RM V1.1ֲûжӦ˵ʳ + ETH_LED_CTRL = 0x05; +} + +/********************************************************************* + * @fn ETH_RegInit + * + * @brief ETH register initialization. + * + * @param ETH_InitStruct:initialization struct. + * PHYAddress:PHY address. + * + * @return Initialization status. + */ +uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress ) +{ + uint32_t tmpreg = 0; + + /*---------------------- Physical layer configuration -------------------*/ + /* Set the SMI interface clock, set as the main frequency divided by 42 */ + tmpreg = ETH->MACMIIAR; + tmpreg &= MACMIIAR_CR_MASK; + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + ETH->MACMIIAR = (uint32_t)tmpreg; + + /*------------------------ MAC register configuration ----------------------- --------------------*/ + tmpreg = ETH->MACCR; + tmpreg &= MACCR_CLEAR_MASK; + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_DeferralCheck | + (1 << 20)); + /* Write MAC Control Register */ + ETH->MACCR = (uint32_t)tmpreg; + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_MASK; + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + ETH->MACFCR = (uint32_t)tmpreg; + + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + tmpreg = ETH->DMAOMR; + tmpreg &= DMAOMR_CLEAR_MASK; + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames); + ETH->DMAOMR = (uint32_t)tmpreg; + + /* Reset the physical layer */ + ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset); + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_Configuration + * + * @brief Ethernet configure. + * + * @return none + */ +void ETH_Configuration( uint8_t *macAddr ) +{ + ETH_InitTypeDef ETH_InitStructure; + uint16_t timeout = 10000; + + /* Configure Ethernet for normal operating mode*/ + ETH->PHY_CR |= 1<<31; + ETH->PHY_CR &= ~(1<<30); + + gPHYAddress = PHY_ADDRESS; + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + do{ + Delay_Us(10); + if( !--timeout ) break; + }while(ETH->DMABMR & ETH_DMABMR_SR); + + /* ETHERNET Configuration */ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + /* Fill ETH_InitStructure parameters */ + /*------------------------ MAC -----------------------------------*/ +#if HARDWARE_CHECKSUM_CONFIG + ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; +#endif + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + /* Filter function configuration */ + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + /*------------------------ DMA -----------------------------------*/ + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable; + /* Configure Ethernet */ + ETH_RegInit( Ð_InitStructure, gPHYAddress ); + + /* Configure MAC address */ + ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]); + ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24)); + + /* Mask the interrupt that Tx good frame count counter reaches half the maximum value */ + ETH->MMCTIMR = ETH_MMCTIMR_TGFM; + /* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */ + /* Mask the interrupt that Rx crc error counter reaches half the maximum value */ + ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM; + + PHY_InterruptInit(); + + ETH_DMAITConfig(ETH_DMA_IT_NIS |\ + ETH_DMA_IT_R |\ + ETH_DMA_IT_T |\ + ETH_DMA_IT_AIS |\ + ETH_DMA_IT_RBU |\ + ETH_DMA_IT_PHYSR,\ + ENABLE); +} + +/********************************************************************* + * @fn ETH_TxPktChainMode + * + * @brief Ethernet sends data frames in chain mode. + * + * @param len Send data length + * pBuff send buffer pointer + * + * @return Send status. + */ +uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff ) +{ + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff; + + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ +#if HARDWARE_CHECKSUM_CONFIG + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full; +#else + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; +#endif + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + + /* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */ + /* Chained Mode */ + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn WCHNET_ETHIsr + * + * @brief Ethernet Interrupt Service Routine + * + * @return none + */ +void WCHNET_ETHIsr(void) +{ + uint32_t intStat; + + intStat = ETH->DMASR; + if (intStat & ETH_DMA_FLAG_AIS) + { + if (intStat & ETH_DMA_FLAG_RBU) + { + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_RBU); + } + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_AIS); + } + + if( intStat & ETH_DMA_FLAG_NIS ) + { + if( intStat & ETH_DMA_FLAG_R ) + { + /*If you don't use the Ethernet library, + * you can do some data processing operations here*/ + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_R); + } + if( intStat & ETH_DMA_FLAG_T ) + { + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_T); + } + if( intStat & ETH_DMA_FLAG_PHYSR) + { + ETH_CheckPhyInterruptStatus( ); + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_PHYSR); + } + ETH_DMAClearITPendingBit(ETH_DMA_FLAG_NIS); + } +} + +/********************************************************************* + * @fn ETH_Init + * + * @brief Ethernet initialization. + * + * @return none + */ +void ETH_Init( uint8_t *macAddr ) +{ + ETH_Configuration( macAddr ); + PHY_LEDCfg(); + ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB); + ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB); + pDMARxSet = DMARxDscrTab; + pDMATxSet = DMATxDscrTab; + NVIC_EnableIRQ(ETH_IRQn); + NVIC_SetPriority(ETH_IRQn, 0); +} + +/********************************************************************* + * @fn ETH_LibInit + * + * @brief Ethernet library initialization program + * + * @return command status + */ +uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr ) +{ + uint8_t s; + struct _WCH_CFG cfg; + + memset(&cfg,0,sizeof(cfg)); + cfg.TxBufSize = ETH_TX_BUF_SZE; + cfg.TCPMss = WCHNET_TCP_MSS; + cfg.HeapSize = WCHNET_MEM_HEAP_SIZE; + cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE; + cfg.MiscConfig0 = WCHNET_MISC_CONFIG0; + cfg.MiscConfig1 = WCHNET_MISC_CONFIG1; + cfg.net_send = ETH_TxPktChainMode; + cfg.CheckValid = WCHNET_CFG_VALID; + s = WCHNET_ConfigLIB(&cfg); + if( s ){ + return (s); + } + s = WCHNET_Init(ip,gwip,mask,macaddr); + ETH_Init( macaddr ); + return (s); +} + +/******************************** endfile @ eth_driver ******************************/ diff --git a/NetLib/eth_driver.h b/NetLib/eth_driver.h new file mode 100644 index 0000000..590f13e --- /dev/null +++ b/NetLib/eth_driver.h @@ -0,0 +1,55 @@ +/********************************** (C) COPYRIGHT ************* ****************** +* File Name : eth_driver.h +* Author : WCH +* Version : V1.3.0 +* Date : 2024/05/05 +* Description : This file contains the headers of the ETH Driver. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __ETH_DRIVER__ +#define __ETH_DRIVER__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "debug.h" +#include "wchnet.h" + +#define PHY_ADDRESS 1 + +#define ROM_CFG_USERADR_ID 0X30CC + +#define PHY_ANLPAR_SELECTOR_FIELD 0x1F +#define PHY_ANLPAR_SELECTOR_VALUE 0x01 /* 5B'00001 */ + +#ifndef WCHNETTIMERPERIOD +#define WCHNETTIMERPERIOD 10 /* Timer period, in Ms. */ +#endif + +extern ETH_DMADESCTypeDef *DMATxDescToSet; +extern ETH_DMADESCTypeDef *DMARxDescToGet; +extern SOCK_INF SocketInf[ ]; +extern uint8_t RemoteIp[4]; + +#define ETH_LED_CTRL (*((volatile uint32_t *)0x40400158)) + +void ETH_PHYLink( void ); +void WCHNET_ETHIsr( void ); +void WCHNET_MainTask( void ); +void ETH_LedConfiguration(void); +void ETH_Init( uint8_t *macAddr ); +void ETH_LedLinkSet( uint8_t mode ); +void ETH_LedDataSet( uint8_t mode ); +void WCHNET_TimeIsr( uint16_t timperiod ); +void ETH_Configuration( uint8_t *macAddr ); +uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/NetLib/libCH56xNET.a b/NetLib/libCH56xNET.a new file mode 100644 index 0000000..8648959 Binary files /dev/null and b/NetLib/libCH56xNET.a differ diff --git a/NetLib/net_config.h b/NetLib/net_config.h new file mode 100644 index 0000000..a65fce2 --- /dev/null +++ b/NetLib/net_config.h @@ -0,0 +1,170 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : net_config.h +* Author : WCH +* Version : V1.30 +* Date : 2024/05/05 +* Description : This file contains the configurations of +* Ethernet protocol stack library +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __NET_CONFIG_H__ +#define __NET_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/********************************************************************* + * socket configuration, IPRAW + UDP + TCP + TCP_LISTEN = number of sockets + */ +#define WCHNET_NUM_IPRAW 1 /* Number of IPRAW connections */ + +#define WCHNET_NUM_UDP 4 /* The number of UDP connections */ + +#define WCHNET_NUM_TCP 1 /* Number of TCP connections */ + +#define WCHNET_NUM_TCP_LISTEN 1 /* Number of TCP listening */ + +/* The number of sockets, the maximum is 31 */ +#define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN) + +#define WCHNET_TCP_MSS 768 /* Size of TCP MSS Ĭ:1460*/ + +#define WCHNET_NUM_POOL_BUF (WCHNET_NUM_TCP*2+2) /* The number of POOL BUFs, the number of receive queues */ + +/********************************************************************* + * MAC queue configuration + */ +#define ETH_TXBUFNB 2 /* The number of descriptors sent by the MAC */ + +#define ETH_RXBUFNB 4 /* Number of MAC received descriptors */ + +#ifndef ETH_MAX_PACKET_SIZE +#define ETH_RX_BUF_SZE 1520 /* MAC receive buffer length, an integer multiple of 4 */ +#define ETH_TX_BUF_SZE 1520 /* MAC send buffer length, an integer multiple of 4 */ +#else +#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE +#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE +#endif + +/********************************************************************* + * Functional configuration + */ +#define WCHNET_PING_ENABLE 1 /* PING is enabled, PING is enabled by default */ + +#define TCP_RETRY_COUNT 20 /* The number of TCP retransmissions, the default value is 20 */ + +#define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */ + +#define SOCKET_SEND_RETRY 1 /* Send failed retry configuration, 1: enable, 0: disable */ + +#define HARDWARE_CHECKSUM_CONFIG 0 /* Hardware checksum checking and insertion configuration, 1: enable, 0: disable */ + +#define FINE_DHCP_PERIOD 8 /* Fine DHCP period, the default value is 8, the unit is 250ms */ + +#define CFG0_TCP_SEND_COPY 1 /* TCP send buffer copy, 1: copy, 0: not copy */ + +#define CFG0_TCP_RECV_COPY 1 /* TCP receive replication optimization, internal debugging use */ + +#define CFG0_TCP_OLD_DELETE 0 /* Delete oldest TCP connection, 1: enable, 0: disable */ + +#define CFG0_IP_REASS_PBUFS 0 /* Number of reassembled IP PBUFs */ + +#define CFG0_TCP_DEALY_ACK_DISABLE 1 /* 1: disable TCP delay ACK 0: enable TCP delay ACK */ + +/********************************************************************* + * Memory related configuration + */ +/* If you want to achieve a higher transmission speed, + * try to increase RECE_BUF_LEN to (WCHNET_TCP_MSS*4) + * and increase WCHNET_NUM_TCP_SEG to (WCHNET_NUM_TCP*4)*/ +#define RECE_BUF_LEN (WCHNET_TCP_MSS*2) /* socket receive buffer size */ + +#define WCHNET_NUM_PBUF WCHNET_NUM_POOL_BUF /* Number of PBUF structures */ + +#define WCHNET_NUM_TCP_SEG (WCHNET_NUM_TCP*2) /* The number of TCP segments used to send */ + +#define WCHNET_MEM_HEAP_SIZE (((WCHNET_TCP_MSS+0x10+54+8)*WCHNET_NUM_TCP_SEG)+ETH_TX_BUF_SZE+64+2*0x18) /* memory heap size */ + +#define WCHNET_NUM_ARP_TABLE 50 /* Number of ARP lists */ + +#define WCHNET_MEM_ALIGNMENT 4 /* 4 byte alignment */ + +#if CFG0_IP_REASS_PBUFS +#define WCHNET_NUM_IP_REASSDATA 2 /* Number of reassembled IP structures */ +/*1: When using the fragmentation function, + * ensure that the size of WCHNET_SIZE_POOL_BUF is large enough to store a single fragmented packet*/ +#define WCHNET_SIZE_POOL_BUF (((1500 + 14 + 4) + 3) & ~3) /* Buffer size for receiving a single packet */ +/*2: When creating a socket that can receive fragmented packets, + * ensure that "RecvBufLen" member of the "struct _SOCK_INF" structure + * (the parameter initialized when calling WCHNET_SocketCreat) is sufficient + * to receive a complete fragmented packet */ +#else +#define WCHNET_NUM_IP_REASSDATA 0 /* Number of reassembled IP structures */ +#define WCHNET_SIZE_POOL_BUF (((WCHNET_TCP_MSS + 40 + 14 + 4) + 3) & ~3) /* Buffer size for receiving a single packet */ +#endif + +/* Check receive buffer */ +#if(WCHNET_NUM_POOL_BUF * WCHNET_SIZE_POOL_BUF < ETH_RX_BUF_SZE) + #error "WCHNET_NUM_POOL_BUF or WCHNET_TCP_MSS Error" + #error "Please Increase WCHNET_NUM_POOL_BUF or WCHNET_TCP_MSS to make sure the receive buffer is sufficient" +#endif +/* Check the configuration of the SOCKET quantity */ +#if( WCHNET_NUM_TCP_LISTEN && !WCHNET_NUM_TCP ) + #error "WCHNET_NUM_TCP Error,Please Configure WCHNET_NUM_TCP >= 1" +#endif +/* Check byte alignment must be a multiple of 4 */ +#if((WCHNET_MEM_ALIGNMENT % 4) || (WCHNET_MEM_ALIGNMENT == 0)) + #error "WCHNET_MEM_ALIGNMENT Error,Please Configure WCHNET_MEM_ALIGNMENT = 4 * N, N >=1" +#endif +/* TCP maximum segment length */ +#if((WCHNET_TCP_MSS > 1460) || (WCHNET_TCP_MSS < 60)) + #error "WCHNET_TCP_MSS Error,Please Configure WCHNET_TCP_MSS >= 60 && WCHNET_TCP_MSS <= 1460" +#endif +/* Number of ARP cache tables */ +#if((WCHNET_NUM_ARP_TABLE > 0X7F) || (WCHNET_NUM_ARP_TABLE < 1)) + #error "WCHNET_NUM_ARP_TABLE Error,Please Configure WCHNET_NUM_ARP_TABLE >= 1 && WCHNET_NUM_ARP_TABLE <= 0X7F" +#endif +/* Check POOL BUF configuration */ +#if(WCHNET_NUM_POOL_BUF < 1) + #error "WCHNET_NUM_POOL_BUF Error,Please Configure WCHNET_NUM_POOL_BUF >= 1" +#endif +/* Check PBUF structure configuration */ +#if(WCHNET_NUM_PBUF < 1) + #error "WCHNET_NUM_PBUF Error,Please Configure WCHNET_NUM_PBUF >= 1" +#endif +/* Check IP Assignment Configuration */ +#if(CFG0_IP_REASS_PBUFS && ((WCHNET_NUM_IP_REASSDATA > 10) || (WCHNET_NUM_IP_REASSDATA < 1))) + #error "WCHNET_NUM_IP_REASSDATA Error,Please Configure WCHNET_NUM_IP_REASSDATA < 10 && WCHNET_NUM_IP_REASSDATA >= 1 " +#endif +/* Check the number of reassembled IP PBUFs */ +#if(CFG0_IP_REASS_PBUFS > WCHNET_NUM_POOL_BUF) + #error "WCHNET_NUM_POOL_BUF Error,Please Configure CFG0_IP_REASS_PBUFS < WCHNET_NUM_POOL_BUF" +#endif +/* Check Timer period, in Ms. */ +#if(WCHNETTIMERPERIOD > 50) + #error "WCHNETTIMERPERIOD Error,Please Configure WCHNETTIMERPERIOD < 50" +#endif + +/* Configuration value 0 */ +#define WCHNET_MISC_CONFIG0 (((CFG0_TCP_SEND_COPY) << 0) |\ + ((CFG0_TCP_RECV_COPY) << 1) |\ + ((CFG0_TCP_OLD_DELETE) << 2) |\ + ((CFG0_IP_REASS_PBUFS) << 3) |\ + ((CFG0_TCP_DEALY_ACK_DISABLE) << 8)) +/* Configuration value 1 */ +#define WCHNET_MISC_CONFIG1 (((WCHNET_MAX_SOCKET_NUM)<<0)|\ + ((WCHNET_PING_ENABLE) << 13) |\ + ((TCP_RETRY_COUNT) << 14) |\ + ((TCP_RETRY_PERIOD) << 19) |\ + ((SOCKET_SEND_RETRY) << 25) |\ + ((HARDWARE_CHECKSUM_CONFIG) << 26)|\ + ((FINE_DHCP_PERIOD) << 27)) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/NetLib/net_function.c b/NetLib/net_function.c new file mode 100644 index 0000000..f3ad12d --- /dev/null +++ b/NetLib/net_function.c @@ -0,0 +1,1095 @@ +/* + * net_function.c + * + * Created on: 2025521 + * Author: cc + */ +#include "includes.h" +#include +#include + +uint8_t MACAddr[6]; //MAC address +uint8_t IPAddr[4] = {172, 16, 4, 100}; //IP address +uint8_t GWIPAddr[4] = {172, 16, 4, 254}; //Gateway IP address +uint8_t IPMask[4] = {255, 255, 0, 0}; //subnet mask +uint8_t DESIP[4] = {172, 16, 4, 55}; //destination IP address +uint16_t desport = 1000; //destination port +uint16_t srcport = 1000; //source port + +uint8_t SocketId; +uint8_t socket[WCHNET_MAX_SOCKET_NUM]; //Save the currently connected socket +uint8_t SocketRecvBuf[WCHNET_MAX_SOCKET_NUM][RECE_BUF_LEN]; //socket receive buffer + +//豸Ϣ +WCHNET_INFO_T g_netinfo = { + .device_ip = {192,168,1,200}, + .gateway = {192,168,1,1}, + .subnet = {255,255,0,0}, + .mac_addr = {0x34,0xD0,0xB8,0x11,0x11,0x11}, + .SocketId = {0,0,0,0}, +}; + +DEVICE_NET_APPINFO server_info = { + .net_sta = 0, + +}; + +TFTP_LOG tftp_log; + +void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/******************************************************************************* +* Function Name : mStopIfError +* Description : check if error. +* Input : +* iError - error constants. +*******************************************************************************/ +void mStopIfError(uint8_t iError) +{ + if (iError == WCHNET_ERR_SUCCESS) return; + + printf("Error: %X\r\n", (uint16_t) iError); +} + + +/******************************************************************************* +* Function Name : TIM2_Init +* Description : Initializes TIM2. +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void TIM2_Init(void) +{ + TMR2_ClrCurrentCount(); + R32_TMR2_CNT_END = SystemCoreClock / 1000 * WCHNETTIMERPERIOD; + R8_TMR2_CTRL_MOD = RB_TMR_COUNT_EN; + TMR2_ITCfg(ENABLE, RB_TMR_IE_CYC_END); + NVIC_EnableIRQ(TIM2_IRQn); +} + +/******************************************************************************* +* Function Name : ETH_IRQHandler +* Description : This function handles ETH exception. +*******************************************************************************/ +void ETH_IRQHandler(void) +{ + WCHNET_ETHIsr(); +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles TIM2 exception. +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ + WCHNET_TimeIsr(WCHNETTIMERPERIOD); + TMR2_ClearITFlag(RB_TMR_IF_CYC_END); +} + +/******************************************************************************* +* Function Name : WCHNET_CreateUdpSocket +* Description : UDP׽ +* Input : +* S - socketֵ +* SourPort - socketԴ˿ +* cb - socketص +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_CreateUdpSocket(uint8_t* S, uint16_t SourPort, pSockRecv cb) +{ + uint8_t i; + SOCK_INF TmpSocketInf; /* ʱsocket */ + + memset((void *)&TmpSocketInf,0,sizeof(SOCK_INF)); /* ڲὫ˱ƣýʱȫ */ + TmpSocketInf.IPAddr[0] = 0xFF; + TmpSocketInf.IPAddr[1] = 0xFF; + TmpSocketInf.IPAddr[2] = 0xFF; + TmpSocketInf.IPAddr[3] = 0xFF; + TmpSocketInf.DesPort = SourPort; /* ĿĶ˿ */ + TmpSocketInf.SourPort = SourPort; /* Դ˿ */ + TmpSocketInf.ProtoType = PROTO_TYPE_UDP; /* socket */ + TmpSocketInf.RecvBufLen = RECE_BUF_LEN; /* socket ջ */ + TmpSocketInf.AppCallBack = cb; /* ýջص */ + + i = WCHNET_SocketCreat(S, &TmpSocketInf); /* socketصsocketSocketId */ + mStopIfError(i); + WCHNET_ModifyRecvBuf(SocketId, (uint32_t) SocketRecvBuf[SocketId], RECE_BUF_LEN); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"%s - %d",__func__, *S); +} + +/******************************************************************************* +* Function Name : WCHNET_CreateTcpSocket +* Description : TCP׽ +* Input : +* S - socketֵ +* Return : None +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_CreateTcpSocket(uint8_t* S) +{ + uint8_t i; + SOCK_INF TmpSocketInf; + + memset((void *) &TmpSocketInf, 0, sizeof(SOCK_INF)); + memcpy((void *) TmpSocketInf.IPAddr, DESIP, 4); + TmpSocketInf.DesPort = desport; + TmpSocketInf.SourPort = srcport; + TmpSocketInf.ProtoType = PROTO_TYPE_TCP; + TmpSocketInf.RecvStartPoint = (uint32_t) SocketRecvBuf[0]; + TmpSocketInf.RecvBufLen = RECE_BUF_LEN; + i = WCHNET_SocketCreat(S, &TmpSocketInf); + printf("TCP SocketId %d\r\n", *S); + mStopIfError(i); + i = WCHNET_SocketConnect(*S); //make a TCP connection + mStopIfError(i); +} + +void UDPSocket1_AppCallBack( struct _SOCK_INF * SocketInf,uint32_t ipaddr,uint16_t port,uint8_t *buff,uint32_t len) +{ + uint8_t ip[4]; + + ip[0] = ipaddr; + ip[1] = ipaddr>>8; + ip[2] = ipaddr>>16; + ip[3] = ipaddr>>24; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ip:%d.%d.%d.%d, port:%d",ip[0], ip[1], ip[2], ip[3], port); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"Socket1 len:%ld",len); + + Dbg_Print_Buff(DBG_BIT_NET_STATUS_bit,"data :",buff,len); + //Udp_Internal_Analysis(buff, len, ip, port); + + if(buff[0] == 0xAA) + { + switch(buff[1]) + { + case 0x55: //ɵķЭ + //Udp_Internal_Analysis(buff, len, ip, port); + break; + case 0x66: //UDPЭ - 2022-05-31 + //UDP_NetServer_Data_Analysis(buff, len, ip, port); + break; + } + + } +} + +/******************************************************************************* +* Function Name : WCHNET_DataLoopback +* Description : Data loopback function. +* Input : +* id - socket id. +* Return : None +*******************************************************************************/ +void WCHNET_DataLoopback(uint8_t id) +{ + uint8_t i; + uint32_t len; + uint32_t endAddr = SocketInf[id].RecvStartPoint + SocketInf[id].RecvBufLen; //Receive buffer end address + + if ((SocketInf[id].RecvReadPoint + SocketInf[id].RecvRemLen) > endAddr) { //Calculate the length of the received data + len = endAddr - SocketInf[id].RecvReadPoint; + } + else { + len = SocketInf[id].RecvRemLen; + } + i = WCHNET_SocketSend(id, (uint8_t *) SocketInf[id].RecvReadPoint, &len); //send data + if (i == WCHNET_ERR_SUCCESS) { + WCHNET_SocketRecv(id, NULL, &len); //Clear sent data + } + +} + +/******************************************************************************* +* Function Name : WCHNET_HandleSockInt +* Description : Socket Interrupt Handle +* Input : +* socketid - socket id. +* intstat - interrupt status +* Return : None +*******************************************************************************/ +void WCHNET_HandleSockInt(uint8_t socketid, uint8_t intstat) +{ + uint8_t i; + + if (intstat & SINT_STAT_RECV) //receive data + { + WCHNET_DataLoopback(socketid); //Data loopback + } + if (intstat & SINT_STAT_CONNECT) //connect successfully + { +#if KEEPALIVE_ENABLE + WCHNET_SocketSetKeepLive(socketid, ENABLE); +#endif + + for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) { + if (socket[i] == 0xff) { //save connected socket id + socket[i] = socketid; + + //ҪעҪ׽ID 鷶ΧĻ·ջ +// if(socketid < WCHNET_MAX_SOCKET_NUM) +// { +// WCHNET_ModifyRecvBuf(socketid, (uint32_t) SocketRecvBuf[socketid], RECE_BUF_LEN); +// } + break; + } + } + printf("TCP Connect Success\r\n"); + printf("socket id: %d\r\n", socket[i]); + } + if (intstat & SINT_STAT_DISCONNECT) //disconnect + { + for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) { //delete disconnected socket id + if (socket[i] == socketid) { + socket[i] = 0xff; + break; + } + } + printf("TCP Disconnect\r\n"); + } + if (intstat & SINT_STAT_TIM_OUT) //timeout disconnect + { + for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) { //delete disconnected socket id + if (socket[i] == socketid) { + socket[i] = 0xff; + break; + } + } + printf("TCP Timeout\r\n"); + } +} + +/******************************************************************************* +* Function Name : WCHNET_Get_PHY_Linked_Status +* Description : ȡPHY·״̬ +* Return PHY״̬ 0x00 - PHY Link Succ,0x01 - PHY Link Fail +*******************************************************************************/ +uint8_t WCHNET_Get_PHY_Linked_Status(void) +{ + uint16_t rev = 0; + rev = WCHNET_GetPHYStatus(); + + if(rev & PHY_Linked_Status) return 0x00; + + return 0x01; +} + +/******************************************************************************* +* Function Name : WCHNET_HandleGlobalInt +* Description : Global Interrupt Handle +*******************************************************************************/ +void WCHNET_HandleGlobalInt(void) +{ + uint8_t intstat; + uint16_t i; + uint8_t socketint; + + intstat = WCHNET_GetGlobalInt(); //get global interrupt flag + if (intstat & GINT_STAT_UNREACH) //Unreachable interrupt + { + printf("GINT_STAT_UNREACH\r\n"); + } + if (intstat & GINT_STAT_IP_CONFLI) //IP conflict + { + printf("GINT_STAT_IP_CONFLI\r\n"); + } + if (intstat & GINT_STAT_PHY_CHANGE) //PHY status change + { + i = WCHNET_GetPHYStatus(); + if (i & PHY_Linked_Status) Dbg_Println(DBG_BIT_NET_STATUS_bit,"PHY Link Success"); + else{ + //Ѱγ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"PHYϿ,³ʼ"); + server_info.init_flag = 0; //PHYϿ,³ʼ + LOG_SYS_PHY_Change_Record(0x00); //߰γ + } + } + if (intstat & GINT_STAT_SOCKET) { //socket related interrupt + for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) { + socketint = WCHNET_GetSocketInt(i); + if (socketint) + WCHNET_HandleSockInt(i, socketint); + } + } +} + +/******************************************************************************* +* Function Name : WCHNET_DHCPCallBack +* Description : DHCPCallBack +* Input : + status - status returned by DHCP + arg - Data returned by DHCP +* Return : DHCP status +*******************************************************************************/ +uint8_t WCHNET_DHCPCallBack(uint8_t status, void *arg) +{ + uint8_t *p; + uint8_t tmp[4] = {0, 0, 0, 0}; + + if(!status) + { + p = arg; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP Success"); + /*If the obtained IP is the same as the last IP, exit this function.*/ + if(!memcmp(g_netinfo.device_ip, p ,sizeof(IPAddr))) { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP ȡIP뵱ǰIPͬ!"); + return ETH_SUCCESS; + } + /*Determine whether it is the first successful IP acquisition*/ + if(memcmp(g_netinfo.device_ip, tmp ,sizeof(IPAddr))){ + /*The obtained IP is different from the last value, + * then disconnect the last connection.*/ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP ȡIP뵱ǰIPͬ ϿTCP\r\n"); + + WCHNET_SocketClose(SocketId, TCP_CLOSE_NORMAL); //رǿͷ׽DHCPײйأɾᵼ³쳣 + } + memcpy(g_netinfo.device_ip, p, 4); + memcpy(g_netinfo.gateway, &p[4], 4); + memcpy(g_netinfo.subnet, &p[8], 4); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"IPAddr = %d.%d.%d.%d ", g_netinfo.device_ip[0], g_netinfo.device_ip[1], g_netinfo.device_ip[2], g_netinfo.device_ip[3]); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"GWIPAddr = %d.%d.%d.%d ", g_netinfo.gateway[0], g_netinfo.gateway[1], g_netinfo.gateway[2], g_netinfo.gateway[3]); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"IPMask = %d.%d.%d.%d ", g_netinfo.subnet[0], g_netinfo.subnet[1], g_netinfo.subnet[2], g_netinfo.subnet[3]); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DNS2: %d.%d.%d.%d ", p[16], p[17], p[18], p[19]); + + WCHNET_DHCPStop(); //رDHCP + + server_info.net_retry_num = 0; + + server_info.net_sta = NET_SOCKET_WAIT; + server_info.wait_cot = SysTick_1ms; + + return ETH_SUCCESS; + } + else + { + /*DHCPȡʧ */ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP Fail %02x ", status); + /*Determine whether it is the first successful IP acquisition*/ + if(memcmp(IPAddr, tmp ,sizeof(IPAddr))){ + /*The obtained IP is different from the last value*/ + //WCHNET_SocketClose(SocketId, TCP_CLOSE_NORMAL); + } + return ETH_ERROR; + } +} + +/******************************************************************************* +* Function Name : WCHNET_DNSCallBack_1 +* Description : ƶ˷ص +* Input : + name - DNS + ipaddr - DNSIP +* Return : DHCP status +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_DNSCallBack_1(const char *name, uint8_t *ipaddr, void *callback_arg) +{ + if(ipaddr == NULL) + { + server_info.net_retry_num++; + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + server_info.net_sta = NET_TFTP; //ʧܣһ + + WCHNET_DNSStop(); //stop DNS,and release socket + } + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS Fail\r\n"); + return; + } + + server_info.dis_ip[0] = ipaddr[0]; + server_info.dis_ip[1] = ipaddr[1]; + server_info.dis_ip[2] = ipaddr[2]; + server_info.dis_ip[3] = ipaddr[3]; + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"Host Name = %s\r\n", name); + Dbg_Print(DBG_BIT_NET_STATUS_bit,"IP= %d.%d.%d.%d\r\n", ipaddr[0], ipaddr[1], ipaddr[2], ipaddr[3]); + + if(callback_arg != NULL) + { + Dbg_Print(DBG_BIT_NET_STATUS_bit,"callback_arg = %02x\r\n", (*(uint8_t *)callback_arg)); + } + + WCHNET_DNSStop(); //stop DNS,and release socket + + server_info.server_dns_flag = 0x01; //ɹ־λ + server_info.net_sta = NET_TFTP; //ɹһ +} + + +/******************************************************************************* +* Function Name : WCHNET_DNSCallBack_2 +* Description : TFTPص - ʱ +* Input : + name - DNS + ipaddr - DNSIP +* Return : DHCP status +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_DNSCallBack_2(const char *name, uint8_t *ipaddr, void *callback_arg) +{ + if(ipaddr == NULL) + { + server_info.net_retry_num++; + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + server_info.net_sta = NET_COMPLETE; + server_info.init_flag = 0x01; + } + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS Fail\r\n"); + return; + } + + server_info.tftp_ip[0] = ipaddr[0]; + server_info.tftp_ip[1] = ipaddr[1]; + server_info.tftp_ip[2] = ipaddr[2]; + server_info.tftp_ip[3] = ipaddr[3]; + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"Host Name = %s\r\n", name); + Dbg_Print(DBG_BIT_NET_STATUS_bit,"IP= %d.%d.%d.%d\r\n", ipaddr[0], ipaddr[1], ipaddr[2], ipaddr[3]); + if(callback_arg != NULL) + { + Dbg_Print(DBG_BIT_NET_STATUS_bit,"callback_arg = %02x\r\n", (*(uint8_t *)callback_arg)); + } + + WCHNET_DNSStop(); //stop DNS,and release socket + + server_info.tftp_dns_flag = 0x01; //ɹ־λ + server_info.net_sta = NET_COMPLETE; + server_info.init_flag = 0x01; +} + +/******************************************************************************* +* Function Name : WCHNET_DNSCallBack_3 +* Description : TFTPص - TFTPǰ +* Input : + name - DNS + ipaddr - DNSIP +* Return : DHCP status +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_DNSCallBack_3(const char *name, uint8_t *ipaddr, void *callback_arg) +{ + if(ipaddr == NULL) + { + server_info.net_retry_num++; + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + + } + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS Fail\r\n"); + return; + } + + server_info.tftp_ip[0] = ipaddr[0]; + server_info.tftp_ip[1] = ipaddr[1]; + server_info.tftp_ip[2] = ipaddr[2]; + server_info.tftp_ip[3] = ipaddr[3]; + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"Host Name = %s\r\n", name); + Dbg_Print(DBG_BIT_NET_STATUS_bit,"IP= %d.%d.%d.%d\r\n", ipaddr[0], ipaddr[1], ipaddr[2], ipaddr[3]); + if(callback_arg != NULL) + { + Dbg_Print(DBG_BIT_NET_STATUS_bit,"callback_arg = %02x\r\n", (*(uint8_t *)callback_arg)); + } + + WCHNET_DNSStop(); //stop DNS,and release socket + + server_info.tftp_dns_flag = 0x01; //ɹ־λ +} + +/******************************************************************************* +* Function Name : is_valid_domain +* Description : ж +* Input : + domain - Ҫжϵ +* Return : 0x00:ϸ0x01:Ƿ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) uint8_t is_valid_domain(const char *domain) +{ + const char *c = domain; + int parts = 0; + int dashes = 0; + + //Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_0:%s",domain); + + // Ƿĵַ + if (strstr(domain, "..") || strstr(domain, "--")) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_1"); + return 0x01; + } + + // ÿַ + while (*c) + { + if (isalpha(*c) || isdigit(*c) || *c == '-' || *c == '.') + { + if (*c == '-') + { + // ڿͷβַ + if (c == domain || *(c + 1) == '\0' || dashes == 0) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_2"); + return 0x01; + } + dashes = 0; + } + else + { + dashes = 1; + } + } + else + { + // Ƿַ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_3:%c",*c); + return 0x01; + } + + if (*c == '.') + { + parts++; // ָ + if (c == domain || *(c + 1) == '\0') + { + // ڿͷβ֮Ϊ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_4"); + return 0x01; + } + } + c++; + } + + // Ҫ֣ example.com + Dbg_Println(DBG_BIT_NET_STATUS_bit,"is_valid_domain_5:%d",parts); + + if(parts > 1) + { + return 0x00; //ϸ + }else { + return 0x01; //Ƿ + } +} + +/******************************************************************************* +* Function Name : NetWork_Parameter_Get +* Description : ȡʼԼʼ +* Input : None +* Output : None +* Return : None +* : ʼ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void NetWork_Parameter_Get(void) +{ + uint8_t Arge_Flag = 0; + uint32_t temp = 0; + + /*жǷʹòΪĬIPַ*/ + Arge_Flag = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_NetInfo_EN_OFFSET + 1); + if(Arge_Flag == 0x01) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"NET ʹPCò!"); + SRAM_DMA_Read_Buff(g_netinfo.device_ip, 4, SRAM_Register_Start_ADDRESS + Register_NetIP_OFFSET); + SRAM_DMA_Read_Buff(g_netinfo.gateway,4,SRAM_Register_Start_ADDRESS + Register_NetGateway_OFFSET); + SRAM_DMA_Read_Buff(g_netinfo.subnet,4,SRAM_Register_Start_ADDRESS + Register_NetMask_OFFSET); + SRAM_DMA_Read_Buff(g_netinfo.dns_server_ip,4,SRAM_Register_Start_ADDRESS + Register_DNSServerIP_OFFSET); + }else { + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"NET ʹñĬϲ!"); + //MCUʼIP + g_netinfo.device_ip[0] = 192; + g_netinfo.device_ip[1] = 168; + g_netinfo.device_ip[2] = MACAddr[4]; + g_netinfo.device_ip[3] = MACAddr[5]; + //MCUʼ + g_netinfo.gateway[0] = 192; + g_netinfo.gateway[1] = 168; + g_netinfo.gateway[2] = MACAddr[4]; + g_netinfo.gateway[3] = 1; + //MCUʼ + g_netinfo.subnet[0] = 255; + g_netinfo.subnet[1] = 255; + g_netinfo.subnet[2] = 0; + g_netinfo.subnet[3] = 0; + //MCU DNSַ + g_netinfo.dns_server_ip[0] = 223; + g_netinfo.dns_server_ip[1] = 5; + g_netinfo.dns_server_ip[2] = 5; + g_netinfo.dns_server_ip[3] = 5; + } + + /*DHCP*/ + if(SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_NetInfo_EN_OFFSET) != 0x02) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCPʹ!"); + server_info.dhcp_en = 0x01; + }else{ /**/ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP!"); + server_info.dhcp_en = 0x00; + } + + /*жϵǰʹñطƶ˷*/ + temp = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_NetInfo_EN_OFFSET + 2); + + if(temp == 0x01) //ʹñض˷ + { + server_info.server_select = 0x01; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ʹñض˷"); + }else //ʹƶ˶˷ + { + server_info.server_select = 0x00; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ʹƶ˶˷"); + } + + memset(&tftp_log,0,sizeof(TFTP_LOG)); + + SRAM_DMA_Read_Buff((uint8_t*)&tftp_log.Time,2,SRAM_Register_Start_ADDRESS + Register_TFTPLOGTime_OFFSET); + SRAM_DMA_Read_Buff((uint8_t*)&tftp_log.Port,2,SRAM_Register_Start_ADDRESS + Register_TFTPLOGPort_OFFSET); + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"tftp log port:%d time:%dh",tftp_log.Port,tftp_log.Time); + + if((tftp_log.Port == 0xFFFF) || (tftp_log.Port == 0x00)) + { + tftp_log.Port = TFTP_Destination_Port; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"tftp log default port:%d",tftp_log.Port); + } + + if((tftp_log.Time == 0x00) || (tftp_log.Time > 720)) + { + tftp_log.Time = 720; //1 + Dbg_Println(DBG_BIT_NET_STATUS_bit,"tftp log default time:%dh",tftp_log.Time); + } + + tftp_log.DN_Lens = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_TFTPDmLens_OFFSET); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"tftp log domain name lens:%d",tftp_log.DN_Lens); + if(tftp_log.DN_Lens < DOMAINNAME_MAX) + { + SRAM_DMA_Read_Buff((uint8_t*)tftp_log.DomainName,tftp_log.DN_Lens,SRAM_Register_Start_ADDRESS + Register_TFTPDmName_OFFSET); + tftp_log.DomainName[tftp_log.DN_Lens] = '\0'; + } + + if((tftp_log.DN_Lens == 0x00) || (is_valid_domain(tftp_log.DomainName) != 0x00)) //ϷʹĬ + { + tftp_log.DN_Lens = sizeof(TFTPSERVER_NAME_DNS); + if(tftp_log.DN_Lens < DOMAINNAME_MAX) + { + memcpy(tftp_log.DomainName,(char*)TFTPSERVER_NAME_DNS,sizeof(TFTPSERVER_NAME_DNS)); + tftp_log.DomainName[tftp_log.DN_Lens] = '\0'; + } + Dbg_Println(DBG_BIT_NET_STATUS_bit,"tftp domain name err,use default:%s",tftp_log.DomainName); + } + + //ȡжʱ + server_info.udp_online_time = SRAM_Read_DW(SRAM_Register_Start_ADDRESS + Register_NetOfflineTime_OFFSET); + if( (server_info.udp_online_time < 1000) || (server_info.udp_online_time > 7200000) ) + { + server_info.udp_online_time = 600000; + } + + //ȡUDP ϱʱ + temp = SRAM_Read_DW(SRAM_Register_Start_ADDRESS + Register_UDPPeriodicTime_OFFSET); + if( (temp < 10000) || (temp > 7200000) ) + { + server_info.udp_periodic_time = 60; + }else { + server_info.udp_periodic_time = temp / 1000; + } + + //ȡ˿ + temp = SRAM_Read_DW(SRAM_Register_Start_ADDRESS + Register_WebServerPort_OFFSET); + if( (temp == 0x00) || (temp >= 0xFFFF) ) + { + //˿ڲϷʹĬ϶˿ 3339 + server_info.dis_port = SERVER_COMM_Port; + }else { + server_info.dis_port = temp & 0xFFFF; + } + + temp = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_BLVServerDmName_OFFSET); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"BLVServerDmName lens:%d",temp); + if(temp < DOMAINNAME_MAX) + { + memset(server_info.ServerDename,0,sizeof(server_info.ServerDename)); + SRAM_DMA_Read_Buff((uint8_t*)server_info.ServerDename,temp,SRAM_Register_Start_ADDRESS + Register_BLVServerDmName_OFFSET); + server_info.ServerDename[temp] = '\0'; + } + + if((temp == 0x00) || (is_valid_domain((char *)server_info.ServerDename) != 0x00)) //ϷʹĬ + { + temp = sizeof(SERVER_NAME_DNS); + if(temp < DOMAINNAME_MAX) + { + memcpy(server_info.ServerDename,(char*)SERVER_NAME_DNS,sizeof(SERVER_NAME_DNS)); + server_info.ServerDename[temp] = '\0'; + } + Dbg_Println(DBG_BIT_NET_STATUS_bit,"BLVServerDmName err,use default:%s",server_info.ServerDename); + } + + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"MCUʼIPַ : %d.%d.%d.%d",g_netinfo.device_ip[0],g_netinfo.device_ip[1],g_netinfo.device_ip[2],g_netinfo.device_ip[3]); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"MCUʼ : %d.%d.%d.%d",g_netinfo.gateway[0],g_netinfo.gateway[1],g_netinfo.gateway[2],g_netinfo.gateway[3]); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"MCUʼ : %d.%d.%d.%d",g_netinfo.subnet[0],g_netinfo.subnet[1],g_netinfo.subnet[2],g_netinfo.subnet[3]); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"MCU DNSַ : %d.%d.%d.%d",g_netinfo.dns_server_ip[0],g_netinfo.dns_server_ip[1],g_netinfo.dns_server_ip[2],g_netinfo.dns_server_ip[3]); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"TFTP Log Domain name:%s ",tftp_log.DomainName); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"BLVServerDmName : %s:%d ",server_info.ServerDename,server_info.dis_port); + Dbg_Println(DBG_BIT_NET_STATUS_bit,"online_time:%d periodic_time:%d",server_info.udp_online_time,server_info.udp_periodic_time); + LOG_SYS_NET_Argc_Init_Record(g_netinfo.device_ip,g_netinfo.gateway,g_netinfo.subnet,g_netinfo.dns_server_ip,Arge_Flag,server_info.dhcp_en,server_info.server_select); +} + +/******************************************************************************* +* Function Name : WCHNET_SocketInf_Printf +* Description : WCH ׽ Ϣӡ +*******************************************************************************/ +__attribute__((section(".non_0_wait"))) void WCHNET_SocketInf_Printf(void) +{ + for(uint8_t i=0;i 30000) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"PHYЭʧܣ׼³ʼ"); + server_info.net_sta = NET_WAIT_MAC_RESTART; + } + break; + }else { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"߲Ѳ룬ֱ׽"); + + WCHNET_CreateUdpSocket(&g_netinfo.SocketId[SocketIdnex_BLVSeriver], 3341, UDPSocket1_AppCallBack); //׽,ȴ÷ + server_info.online_state = 1; //2023-10-07 + server_info.wait_cot = SysTick_1ms; + server_info.net_sta = NET_CON_WAIT; + LOG_SYS_PHY_Change_Record(0x01); //߲ + } + break; + case NET_WAIT_MAC_RESTART: + if(SysTick_1ms - server_info.wait_cot > 2000) + { + server_info.wait_cot = SysTick_1ms; + Dbg_Println(DBG_BIT_NET_STATUS_bit,""); + server_info.net_sta = NET_INIT; + } + break; + case NET_CON_WAIT: + if(SysTick_1ms - server_info.wait_cot > 200) + { + server_info.wait_cot = SysTick_1ms; + if(server_info.dhcp_en == 0x01) + { + server_info.net_sta = NET_DHCP; + }else { + server_info.net_sta = NET_DNS; + } + } + break; + case NET_DHCP: //DHCPip + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP..."); + + WCHNET_DHCPSetHostname("BLV_RCU"); + WCHNET_DHCPStart(WCHNET_DHCPCallBack); /* DHCP */ + + server_info.wait_cot = SysTick_1ms; + server_info.net_sta = NET_DHCP_WAIT; + break; + case NET_DHCP_WAIT: + if(SysTick_1ms - server_info.wait_cot >= 20000) + { + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCP ʱ%dms", SysTick_1ms - server_info.wait_cot); + server_info.wait_cot = SysTick_1ms; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCPȡʧ!"); + WCHNET_DHCPStop(); + server_info.net_retry_num++; + server_info.net_sta = NET_DHCP; + + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"DHCPԴѴ!"); + server_info.net_sta = NET_INIT; //DHCPʧܣֱ³ʼ; + + WCHNET_SocketClose(g_netinfo.SocketId[SocketIdnex_BLVSeriver],0x00); + } + } + + /* ٴڼγߣPHYӶϿ³ʼ + * - ³ʼǰҪֹͣDHCP + * */ + break; + case NET_SOCKET_WAIT: + if(SysTick_1ms - server_info.wait_cot >= 200) + { + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DHCPɹ´ͨѶ׽\n"); + WCHNET_CreateUdpSocket(&g_netinfo.SocketId[SocketIdnex_BLVSeriver], 3341, UDPSocket1_AppCallBack); //׽,ȴ÷ + WCHNET_SocketInf_Printf(); + server_info.net_sta = NET_DNS; + } + break; + case NET_DNS: + if(server_info.server_select == 0x00) + { + /* */ + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%s Flag:%d...\n",server_info.ServerDename,server_info.net_retry_flag); + + //Set DNS server IP address, and DNS server port is 53 + if(server_info.net_retry_flag == 0x00) { + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%d.%d.%d.%d\n",g_netinfo.dns_server_ip[0],\ + g_netinfo.dns_server_ip[1],\ + g_netinfo.dns_server_ip[2],\ + g_netinfo.dns_server_ip[3]); + + WCHNET_InitDNS(g_netinfo.dns_server_ip, Net_DNS_Port); + }else if(server_info.net_retry_flag == 0x01) { + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%d.%d.%d.%d\n",g_netinfo.dns_server2_ip[0],\ + g_netinfo.dns_server2_ip[1],\ + g_netinfo.dns_server2_ip[2],\ + g_netinfo.dns_server2_ip[3]); + + WCHNET_InitDNS(g_netinfo.dns_server2_ip, Net_DNS_Port); + } + + server_info.dns_sta = 0x01; + WCHNET_HostNameGetIp(server_info.ServerDename, RemoteIp, WCHNET_DNSCallBack_1, NULL); //Start DNS + + server_info.wait_cot = SysTick_1ms; + server_info.net_sta = NET_DNS_WAIT; + }else if(server_info.server_select == 0x01) + { + /*ñط - ֱ÷IPַһ־λʱû*/ + + server_info.dis_ip[0] = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_WebServerIP_OFFSET + 0); + server_info.dis_ip[1] = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_WebServerIP_OFFSET + 1); + server_info.dis_ip[2] = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_WebServerIP_OFFSET + 2); + server_info.dis_ip[3] = SRAM_Read_Byte(SRAM_Register_Start_ADDRESS + Register_WebServerIP_OFFSET + 3); + + server_info.server_dns_flag = 0x00; + server_info.net_sta = NET_TFTP; + + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ñط:%d.%d.%d.%d",server_info.dis_ip[0],server_info.dis_ip[1],server_info.dis_ip[2],server_info.dis_ip[3]); + } + break; + case NET_TFTP: + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%s Flag:%d...\n",tftp_log.DomainName,server_info.net_retry_flag); + + //Set DNS server IP address, and DNS server port is 53 + if(server_info.net_retry_flag == 0x00) { + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%d.%d.%d.%d\n",g_netinfo.dns_server_ip[0],\ + g_netinfo.dns_server_ip[1],\ + g_netinfo.dns_server_ip[2],\ + g_netinfo.dns_server_ip[3]); + + WCHNET_InitDNS(g_netinfo.dns_server_ip, Net_DNS_Port); + }else if(server_info.net_retry_flag == 0x01) { + + Dbg_Print(DBG_BIT_NET_STATUS_bit,"DNS:%d.%d.%d.%d\n",g_netinfo.dns_server2_ip[0],\ + g_netinfo.dns_server2_ip[1],\ + g_netinfo.dns_server2_ip[2],\ + g_netinfo.dns_server2_ip[3]); + + WCHNET_InitDNS(g_netinfo.dns_server2_ip, Net_DNS_Port); + } + + server_info.dns_sta = 0x02; + WCHNET_HostNameGetIp(tftp_log.DomainName, RemoteIp, WCHNET_DNSCallBack_2, NULL); //Start DNS + server_info.wait_cot = SysTick_1ms; + server_info.net_sta = NET_DNS_WAIT; + + break; + case NET_DNS_WAIT: + if(SysTick_1ms - server_info.wait_cot >= 5000) + { + server_info.wait_cot = SysTick_1ms; + + switch(server_info.dns_sta) + { + case 0x01: + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + + if(server_info.net_retry_flag == 0x00) + { + //DNSһ + server_info.net_retry_flag = 0x01; + server_info.net_sta = NET_DNS; + }else { + //ǽˣһ + server_info.net_retry_flag = 0x00; + server_info.net_sta = NET_TFTP; + } + + WCHNET_DNSStop(); //stop DNS,and release socket + }else { + server_info.net_retry_num++; + server_info.net_sta = NET_DNS; + + WCHNET_DNSStop(); //stop DNS,and release socket + } + break; + + case 0x02: + if(server_info.net_retry_num >= 3) + { + server_info.net_retry_num = 0; + + if(server_info.net_retry_flag == 0x00) + { + //DNSһ + server_info.net_retry_flag = 0x01; + server_info.net_sta = NET_TFTP; + }else { + //ǽ + server_info.net_retry_flag = 0x00; + server_info.net_sta = NET_COMPLETE; + server_info.init_flag = 0x01; + WCHNET_SocketInf_Printf(); + } + + WCHNET_DNSStop(); //stop DNS,and release socket + }else { + server_info.net_retry_num++; + server_info.net_sta = NET_TFTP; + + WCHNET_DNSStop(); //stop DNS,and release socket + } + break; + default: //Ӽ + break; + } + } + + /* ٴڼγߣPHYӶϿ³ʼ + * - ³ʼǰҪֹͣDNS + * */ + break; + case NET_COMPLETE: + + + //Udp_Internal_Task(); //ã + + if(SysTick_1s - server_info.con_tick > 10) + { + //ʹ + server_info.con_tick = SysTick_1s; + Dbg_Println(DBG_BIT_NET_STATUS_bit,"紦...\n"); + } + +// if(server_info.con_flag==0x01) //2023-05-27 +// { +// if(SysTick_1s - server_info.con_tick > 10) +// { +// server_info.con_flag = 0x00; +// server_info.con_tick = SysTick_1s; +// server_info.init_flag = 0x00; +// Dbg_Print(DBG_BIT_NET_STATUS_bit,"ֱʱ\n"); +// } +// } + + if(server_info.init_flag == 0x00) //Ҫ³ʼ + { + Dbg_Print(DBG_BIT_NET_STATUS_bit,"Ҫ³ʼرMAC\n"); + + server_info.online_state = 0; + server_info.wait_cot = SysTick_1ms; + server_info.net_sta = NET_WAIT_MAC_RESTART; + + + /*ͷ׽*/ + Dbg_Println(DBG_BIT_NET_STATUS_bit,"ͷ׽"); + WCHNET_SocketClose(g_netinfo.SocketId[SocketIdnex_BLVSeriver],0x00); + + } + break; + + } +} + + + + + diff --git a/NetLib/net_function.h b/NetLib/net_function.h new file mode 100644 index 0000000..eb61115 --- /dev/null +++ b/NetLib/net_function.h @@ -0,0 +1,160 @@ +/* + * net_function.h + * + * Created on: May 21, 2025 + * Author: cc + */ + +#ifndef NET_FUNCTION_H_ +#define NET_FUNCTION_H_ + +#include "ch564.h" +#include "eth_driver.h" +#include "net_config.h" +#include "debug.h" + +#define KEEPALIVE_ENABLE 0 //Enable keep alive function ʹTCP +#define NET_Socket_Num_Max 4 //Ӧòഴ4׽֣ ׽:WCHNET_MAX_SOCKET_NUM +#define DOMAINNAME_MAX 64 // + +#define SERVER_NAME_DNS "www.boonlive-rcu.com" //ƶ˷ - Ĭʹ +#define TFTPSERVER_NAME_DNS "blv-tftp-log.blv-oa.com" //TFTP־ - Ĭʹ +#define SERVER_COMM_Port 3339 + +#define SocketIdnex_BLVSeriver 0x00 //׽洢± + +#define Net_DNS_Port 53 //DNS˿ + +typedef enum +{ + NET_INIT = 0, + NET_PHY_WAIT, + NET_DHCP, + NET_DHCP_WAIT, + NET_TFTP, + NET_DNS, + NET_DNS_WAIT, + NET_WAIT, + NET_COMPLETE, + + NET_WAIT_MAC_RESTART, + //NET_START_TO_INIT, + NET_CON_WAIT, + NET_SOCKET_WAIT, +}NET_STA; + +enum UDP_INTERNAL_STA{ + STA_INIT = 0, + STA_INIT_WAIT = 1, + STA_INIT_IDLE = 2, + STA_Realy_Upgrade = 3, + STA_INIT_CONNECT, + STA_LOG, + STA_SEND_WAIT, + STA_SEND_LOG, + STA_SEND_RETRY, + STA_END, +}; + +typedef struct +{ + uint8_t device_ip[4]; // 豸 IP + uint8_t gateway[4]; // صַ + uint8_t subnet[4]; // + uint8_t mac_addr[6]; // ʹõMACַ + uint8_t dns_server_ip[4]; // DNSIPַ + uint8_t dns_server2_ip[4]; // DNSIPַ + uint8_t SocketId[NET_Socket_Num_Max]; + +}WCHNET_INFO_T; + +typedef struct +{ + uint8_t init_flag:1; //ʼɱ־λ + uint8_t register_flag:1; //ע־λ + uint8_t search_ack_flag:1; //ͱ־λ + uint8_t dhcp_en:1; //DHCPǷ + uint8_t dns_sta:4; //DNS״̬ + + uint8_t dhcp_flg:1; //DHCPipɹ־ + uint8_t dns_flg:1; //DNSȡipɹ־ + uint8_t Udp_Internal_sta:4; //UDP״̬״̬ + uint8_t PHY_State:2; //NET PHY״̬ 0x00:ǰδӣ0x01:ǰDNS״̬ + + uint8_t register_num:4; //ע + uint8_t dns_fail:4; //DNSʧܼлDNSʹ + + uint8_t server_dns_flag:1; //DNSɹ + uint8_t tftp_dns_flag:1; //DNSɹtftp + uint8_t mqtt_dns_flag:1; //MQTTɹ־λ + uint8_t online_state:3; //״̬ 0: 1: 2:ط 3:ƶ˷ + uint8_t sync_tick:2; //ͬʱ + + uint8_t udp_dns_flag:1; //udp־λ + uint8_t server_select:1; //ѡ 0x00:Ĭƶ˷,0x01:ط + uint8_t net_retry_flag:1; //Ա־λ - + uint8_t net_retry_num:5; //Դ - DHCPԴDNSԴ + + uint8_t con_flag:1; //ֱ + uint8_t rcu_reboot_flag:1; //RCU־λ + uint8_t udp_scan_cnt:6; //udpɨ + + uint8_t active_cmd_flag; //־λ + + uint8_t net_sta; //״̬ǰ״̬ + uint8_t udp_sta; //UDP״̬ + uint8_t ServerDename[DOMAINNAME_MAX]; // + uint8_t dis_ip[4]; //ƶ˷ipַ + uint8_t tftp_ip[4]; //TFTP + uint8_t goal_ip[4]; //Ŀip, + + uint8_t udp_send_flag; //ͱ + uint8_t udp_retry_cnt; //ط + uint8_t udp_retry_num; //ط + uint16_t local_port; //ض˿ + uint16_t goal_port; //Ŀport + uint16_t dis_port; //ƶ˷˿ + uint16_t frame_no; //͵֡ + uint16_t ack_frame; //ACK֡ + + uint16_t udp_timesync_cnt; //ʱͬ - 1sһ + uint16_t udp_periodic_cnt; //ϱ - 1sһ + uint16_t udp_periodic_time; //ϱʱ - λ:S + + uint32_t udp_retry_tick; //طʱʱ + uint32_t udp_retry_time; //طʱʱ + + uint32_t con_tick; //ֱʱ 2023-05-27 + + uint32_t udp_idle_tick; //UDPʱ + uint32_t udp_online_tick; //UDPʱ + uint32_t udp_online_time; //UDPжʱ + + uint32_t wait_cot; //ȴ + uint32_t register_tick; //עʱ + uint32_t search_ack_tick; //ͼʱ + +}DEVICE_NET_APPINFO; + +/*TFTP LOGض*/ +#define TFTP_Destination_Port 69 //TFTP˿ +#define TFTP_LOG_Local_Port 65500 //TFTP LOG䱾ض˿ + + +typedef struct +{ + uint16_t Port; //TFTP LOG䱾ض˿ + uint16_t Time; //־ϱʱ + uint8_t DN_Lens; //TFTP־ + char DomainName[DOMAINNAME_MAX]; //TFTP־ +}TFTP_LOG; + +extern WCHNET_INFO_T g_netinfo; +extern DEVICE_NET_APPINFO server_info; + +uint8_t WCHNET_LIB_Init(void); +void WCHNET_HandleGlobalInt(void); + +void NetWork_Task(void); + +#endif /* NET_FUNCTION_H_ */ diff --git a/NetLib/wchnet.h b/NetLib/wchnet.h new file mode 100644 index 0000000..f1c124c --- /dev/null +++ b/NetLib/wchnet.h @@ -0,0 +1,605 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : wchnet.h + * Author : WCH + * Version : V1.90 + * Date : 2023/05/12 + * Description : This file contains the headers of +* the Ethernet protocol stack library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __WCHNET_H__ +#define __WCHNET_H__ + +#include "stdint.h" +#ifndef NET_LIB +#include "net_config.h" +#endif +#ifdef __cplusplus +extern "C" { +#endif + +#define WCHNET_LIB_VER 0x1A //the library version number +#define WCHNET_CFG_VALID 0x12345678 //Configuration value valid flag + +/* LED state @LED_STAT */ +#define LED_ON 0 +#define LED_OFF 1 + +/* PHY state @PHY_STAT */ +#define PHY_LINK_SUCCESS (1 << 2) //PHY connection success +#define PHY_AUTO_SUCCESS (1 << 5) //PHY auto negotiation completed + +/* Library initialization state @CFG_INIT_STAT */ +#define INIT_OK 0x00 +#define INIT_ERR_RX_BUF_SIZE 0x01 +#define INIT_ERR_TCP_MSS 0x02 +#define INIT_ERR_HEAP_SIZE 0x03 +#define INIT_ERR_ARP_TABLE_NEM 0x04 +#define INIT_ERR_MISC_CONFIG0 0x05 +#define INIT_ERR_MISC_CONFIG1 0x06 +#define INIT_ERR_FUNC_SEND 0x09 +#define INIT_ERR_CHECK_VALID 0xFF + +/* Socket protocol type */ +#define PROTO_TYPE_IP_RAW 0 //IP layer raw data +#define PROTO_TYPE_UDP 2 //UDP protocol +#define PROTO_TYPE_TCP 3 //TCP protocol + +/* interrupt status */ +/* The following are the states + * that GLOB_INT will generate */ +#define GINT_STAT_UNREACH (1 << 0) //unreachable interrupt +#define GINT_STAT_IP_CONFLI (1 << 1) //IP conflict interrupt +#define GINT_STAT_PHY_CHANGE (1 << 2) //PHY state change interrupt +#define GINT_STAT_SOCKET (1 << 4) //socket related interrupt + +/* The following are the states + * that Sn_INT will generate*/ +#define SINT_STAT_RECV (1 << 2) //the socket receives data or the receive buffer is not empty +#define SINT_STAT_CONNECT (1 << 3) //connect successfully,generated in TCP mode +#define SINT_STAT_DISCONNECT (1 << 4) //disconnect,generated in TCP mode +#define SINT_STAT_TIM_OUT (1 << 6) //timeout disconnect,generated in TCP mode + + +/* Definitions for error constants. @ERR_T */ +#define ERR_T +#define WCHNET_ERR_SUCCESS 0x00 //No error, everything OK +#define WCHNET_ERR_BUSY 0x10 //busy +#define WCHNET_ERR_MEM 0x11 //Out of memory error +#define WCHNET_ERR_BUF 0x12 //Buffer error +#define WCHNET_ERR_TIMEOUT 0x13 //Timeout +#define WCHNET_ERR_RTE 0x14 //Routing problem +#define WCHNET_ERR_ABRT 0x15 //Connection aborted +#define WCHNET_ERR_RST 0x16 //Connection reset +#define WCHNET_ERR_CLSD 0x17 //Connection closed +#define WCHNET_ERR_CONN 0x18 //Not connected +#define WCHNET_ERR_VAL 0x19 //Illegal value +#define WCHNET_ERR_ARG 0x1a //Illegal argument +#define WCHNET_ERR_USE 0x1b //Address in use +#define WCHNET_ERR_IF 0x1c //Low-level netif error +#define WCHNET_ERR_ISCONN 0x1d //Already connected +#define WCHNET_ERR_INPROGRESS 0x1e //Operation in progress +#define WCHNET_ERR_SOCKET_MEM 0X20 //Socket information error +#define WCHNET_ERR_UNSUPPORT_PROTO 0X21 //unsupported protocol type +#define WCHNET_RET_ABORT 0x5F //command process fail +#define WCHNET_ERR_UNKNOW 0xFA //unknow + +/* unreachable condition related codes */ +#define UNREACH_CODE_HOST 0 //host unreachable +#define UNREACH_CODE_NET 1 //network unreachable +#define UNREACH_CODE_PROTOCOL 2 //protocol unreachable +#define UNREACH_CODE_PROT 3 //port unreachable +/*For other values, please refer to the RFC792 document*/ + +/* TCP disconnect related codes */ +#define TCP_CLOSE_NORMAL 0 //normal disconnect,a four-way handshake +#define TCP_CLOSE_RST 1 //reset the connection and close +#define TCP_CLOSE_ABANDON 2 //drop connection, and no termination message is sent + +/* socket state code */ +#define SOCK_STAT_CLOSED 0X00 //socket close +#define SOCK_STAT_OPEN 0X05 //socket open + +/* TCP state code */ +#define TCP_CLOSED 0 //TCP close +#define TCP_LISTEN 1 //TCP listening +#define TCP_SYN_SENT 2 //SYN send, connect request +#define TCP_SYN_RCVD 3 //SYN received, connection request received +#define TCP_ESTABLISHED 4 //TCP connection establishment +#define TCP_FIN_WAIT_1 5 //WAIT_1 state +#define TCP_FIN_WAIT_2 6 //WAIT_2 state +#define TCP_CLOSE_WAIT 7 //wait to close +#define TCP_CLOSING 8 //closing +#define TCP_LAST_ACK 9 //LAST_ACK +#define TCP_TIME_WAIT 10 //2MSL wait + +/* The following values are fixed and cannot be changed */ +#define WCHNET_MEM_ALIGN_SIZE(size) (((size) + WCHNET_MEM_ALIGNMENT - 1) & ~(WCHNET_MEM_ALIGNMENT - 1)) +#define WCHNET_SIZE_IPRAW_PCB 0x1C //IPRAW PCB size +#define WCHNET_SIZE_UDP_PCB 0x20 //UDP PCB size +#define WCHNET_SIZE_TCP_PCB 0xB4 //TCP PCB size +#define WCHNET_SIZE_TCP_PCB_LISTEN 0x24 //TCP LISTEN PCB size +#define WCHNET_SIZE_IP_REASSDATA 0x20 //IP reassembled Management +#define WCHNET_SIZE_PBUF 0x10 //Packet Buf +#define WCHNET_SIZE_TCP_SEG 0x14 //TCP SEG structure +#define WCHNET_SIZE_MEM 0x08 //sizeof(struct mem) +#define WCHNET_SIZE_ARP_TABLE 0x18 //sizeof ARP table + +#define WCHNET_MEMP_SIZE ((WCHNET_MEM_ALIGNMENT - 1) + \ + (WCHNET_NUM_IPRAW * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB)) + \ + (WCHNET_NUM_UDP * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB)) + \ + (WCHNET_NUM_TCP * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB)) + \ + (WCHNET_NUM_TCP_LISTEN * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN)) + \ + (WCHNET_NUM_TCP_SEG * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG)) + \ + (WCHNET_NUM_IP_REASSDATA * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA)) + \ + (WCHNET_NUM_PBUF * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF)) + \ + (WCHNET_NUM_POOL_BUF * (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)))) + +#define HEAP_MEM_ALIGN_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_MEM)) +#define WCHNET_RAM_HEAP_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_MEM_HEAP_SIZE) + HEAP_MEM_ALIGN_SIZE ) +#define WCHNET_RAM_ARP_TABLE_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_ARP_TABLE) * WCHNET_NUM_ARP_TABLE) + +typedef struct +{ + uint32_t length; + uint32_t buffer; +}ETHFrameType; + +/* LED callback type */ +typedef void (*led_callback)( uint8_t setbit ); + +/* net send callback type */ +typedef uint32_t (*eth_tx_set )( uint16_t len, uint32_t *pBuff ); + +/* net receive callback type */ +typedef uint32_t (*eth_rx_set )( ETHFrameType *pkt ); + +/* DNS callback type */ +typedef void (*dns_callback)( const char *name, uint8_t *ipaddr, void *callback_arg ); + +/* DHCP callback type */ +typedef uint8_t (*dhcp_callback)( uint8_t status, void * ); + +/* socket receive callback type */ +struct _SOCK_INF; +typedef void (*pSockRecv)( struct _SOCK_INF *, uint32_t, uint16_t, uint8_t *, uint32_t); + +/* Socket information struct */ +typedef struct _SOCK_INF +{ + uint32_t IntStatus; //interrupt state + uint32_t SockIndex; //Socket index value + uint32_t RecvStartPoint; //Start pointer of the receive buffer + uint32_t RecvBufLen; //Receive buffer length + uint32_t RecvCurPoint; //current pointer to receive buffer + uint32_t RecvReadPoint; //The read pointer of the receive buffer + uint32_t RecvRemLen; //The length of the remaining data in the receive buffer + uint32_t ProtoType; //protocol type + uint32_t SockStatus; //Low byte Socket state, the next low byte is TCP state, only meaningful in TCP mode + uint32_t DesPort; //destination port + uint32_t SourPort; //Source port, protocol type in IPRAW mode + uint8_t IPAddr[4]; //Socket destination IP address + void *Resv1; //Reserved, for internal use, for saving individual PCBs + void *Resv2; //Reserved, used internally, used by TCP Server + pSockRecv AppCallBack; //receive callback function +} SOCK_INF; + +struct _WCH_CFG +{ + uint32_t TxBufSize; //MAC send buffer size, reserved for use + uint32_t TCPMss; //TCP MSS size + uint32_t HeapSize; //heap memory size + uint32_t ARPTableNum; //Number of ARP lists + uint32_t MiscConfig0; //Miscellaneous Configuration 0 + /* Bit 0 TCP send buffer copy 1: copy, 0: not copy */ + /* Bit 1 TCP receive replication optimization, used for internal debugging */ + /* bit 2 delete oldest TCP connection 1: enable, 0: disable */ + /* Bits 3-7 Number of PBUFs of IP segments */ + /* Bit 8 TCP Delay ACK disable */ + uint32_t MiscConfig1; //Miscellaneous Configuration 1 + /* Bits 0-7 Number of Sockets*/ + /* Bits 8-12 Reserved */ + /* Bit 13 PING enable, 1: On 0: Off */ + /* Bits 14-18 TCP retransmission times */ + /* Bits 19-23 TCP retransmission period, in 50 milliseconds */ + /* bit 25 send failed retry, 1: enable, 0: disable */ + /* bit 26 Select whether to perform IPv4 checksum check on + * the TCP/UDP/ICMP header of the received frame payload by hardware, + * and calculate and insert the checksum of the IP header and payload of the sent frame by hardware.*/ + /* Bits 27-31 period (in 250 milliseconds) of Fine DHCP periodic process */ + led_callback led_link; //PHY Link Status Indicator + led_callback led_data; //Ethernet communication indicator + eth_tx_set net_send; //Ethernet send + eth_rx_set net_recv; //Ethernet receive + uint32_t CheckValid; //Configuration value valid flag, fixed value @WCHNET_CFG_VALID +}; + +struct _NET_SYS +{ + uint8_t IPAddr[4]; //IP address + uint8_t GWIPAddr[4]; //Gateway IP address + uint8_t MASKAddr[4]; //subnet mask + uint8_t MacAddr[8]; //MAC address + uint8_t UnreachIPAddr[4]; //Unreachable IP address + uint32_t RetranCount; //number of retries,default is 10 times + uint32_t RetranPeriod; //Retry period, unit MS, default 500MS + uint32_t PHYStat; //PHY state code + uint32_t NetStat; //The status of the Ethernet, including whether it is open, etc. + uint32_t MackFilt; //MAC filtering, the default is to receive broadcasts, receive local MAC + uint32_t GlobIntStatus; //global interrupt + uint32_t UnreachCode; //unreachable code + uint32_t UnreachProto; //unreachable protocol + uint32_t UnreachPort; //unreachable port + uint32_t SendFlag; + uint32_t Flags; +}; + +/* KEEP LIVE configuration structure */ +struct _KEEP_CFG +{ + uint32_t KLIdle; //KEEPLIVE idle time, in ms + uint32_t KLIntvl; //KEEPLIVE period, in ms + uint32_t KLCount; //KEEPLIVE times +}; + +/** + * @brief Library initialization . + * + * @param ip - IP address pointer + * @param gwip - Gateway address pointer + * @param mask - Subnet mask pointer + * @param macaddr - MAC address pointer + * + * @return @ERR_T + */ +uint8_t WCHNET_Init(const uint8_t *ip, const uint8_t *gwip, const uint8_t *mask, const uint8_t *macaddr); + +/** + * @brief get library version + * + * @param None + * + * @return library version + */ +uint8_t WCHNET_GetVer(void); + +/** + * @brief Get MAC address. + * + * @param(in) macaddr - MAC address + * + * @param(out) MAC address + * + * @return None + */ +void WCHNET_GetMacAddr(uint8_t *macaddr); + +/** + * @brief Library parameter configuration. + * + * @param cfg - Configuration parameter @_WCH_CFG + * + * @return Library configuration initialization state @CFG_INIT_STAT + */ +uint8_t WCHNET_ConfigLIB(struct _WCH_CFG *cfg); + +/** + * @brief Handle periodic tasks in the protocol stack + * + * @param None + * + * @return None + */ +void WCHNET_PeriodicHandle(void); + +/** + * @brief Ethernet data input. Always called in the main program, + * or called after the reception interrupt is detected. + * + * @param + * + * @return None + */ +void WCHNET_NetInput( void ); + +/** + * @brief Ethernet interrupt service function. Called after + * Ethernet interrupt is generated. + * + * @param None + * + * @return None + */ +void WCHNET_ETHIsr(void); + +/** + * @brief Get PHY status + * + * @param None + * + * @return PHY status @PHY_STAT + */ +uint8_t WCHNET_GetPHYStatus(void); + +/** + * @brief Query global interrupt status. + * + * @param None + * + * @return GLOB_INT + */ +uint8_t WCHNET_QueryGlobalInt(void); + +/** + * @brief Read global interrupt and clear it. + * + * @param None + * + * @return GLOB_INT + */ +uint8_t WCHNET_GetGlobalInt(void); + +/** + * @brief create socket + * + * @param(in) *socketid - socket variable pointer + * @param socinf - Configuration parameters for creating sockets @SOCK_INF + * + * @param(out) *socketid - socket value + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketCreat( uint8_t *socketid, SOCK_INF *socinf); + +/** + * @brief Socket sends data. + * + * @param socketid - socket id value + * @param *buf - the first address of send buffer + * @param(in) *len - pointer to the length of the data expected to be sent + * + * @param(out) *len - pointer to the length of the data sent actually + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketSend( uint8_t socketid, uint8_t *buf, uint32_t *len); + +/** + * @brief Socket receives data. + * + * @param socketid - socket id value + * @param *buf - the first address of receive buffer + * @param(in) *len - pointer to the length of the data expected to be read + * + * @param(out) *buf - the first address of data buffer + * @param(out) *len - pointer to the length of the data read actually + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketRecv( uint8_t socketid, uint8_t *buf, uint32_t *len); + +/** + * @brief Get socket interrupt, and clear socket interrupt. + * + * @param socketid - socket id value + * + * @return Sn_INT + */ +uint8_t WCHNET_GetSocketInt( uint8_t socketid ); + +/** + * @brief Get the length of the data received by socket. + * + * @param socketid - socket id value + * @param(in) *bufaddr - the first address of receive buffer + * + * @param(out) *bufaddr - the first address of data buffer + * + * @return the length of the data + */ +uint32_t WCHNET_SocketRecvLen( uint8_t socketid, uint32_t *bufaddr); + +/** + * @brief TCP connect. Used in TCP Client mode. + * + * @param socketid - socket id value + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketConnect( uint8_t socketid); + +/** + * @brief TCP listen. Used in TCP SERVER mode. + * + * @param socketid - socket id value + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketListen( uint8_t socketid); + +/** + * @brief Close socket. + * + * @param socketid - socket id value + * @param mode - the way of disconnection.Used in TCP connection. + * @TCP disconnect related codes + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketClose( uint8_t socketid, uint8_t mode ); + +/** + * @brief Modify socket receive buffer. + * + * @param socketid - socket id value + * @param bufaddr - Address of the receive buffer + * @param bufsize - Size of the receive buffer + * + * @return None + */ +void WCHNET_ModifyRecvBuf( uint8_t socketid, uint32_t bufaddr, uint32_t bufsize); + +/** + * @brief UDP send, specify the target IP and target port + * + * @param socketid - socket id value + * @param *buf - Address of the sent data + * @param(in) *slen - Address of the sent length + * @param *sip - destination IP address + * @param port - destination port + * + * @param(out) *slen - actual length sent + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketUdpSendTo( uint8_t socketid, uint8_t *buf, uint32_t *slen, uint8_t *sip, uint16_t port); + +/** + * @brief Convert ASCII address to network address. + * + * @param *cp - ASCII address to be converted, such as "192.168.1.2" + * @param(in) *addr - First address of the memory stored in the converted network address + * @param(out) *addr - Converted network address, such as 0xC0A80102 + * @return 0 - Success. Others - Failure. + */ +uint8_t WCHNET_Aton(const char *cp, uint8_t *addr); + +/** + * @brief Convert network address to ASCII address. + * + * @param *ipaddr - socket id value + * + * @return Converted ASCII address + */ +uint8_t *WCHNET_Ntoa( uint8_t *ipaddr); + +/** + * @brief Set socket TTL. + * + * @param socketid - socket id value + * @param ttl - TTL value + * + * @return @ERR_T + */ +uint8_t WCHNET_SetSocketTTL( uint8_t socketid, uint8_t ttl); + +/** + * @brief Start TCP retry sending immediately. + * + * @param socketid - TTL value + * + * @return None + */ +void WCHNET_RetrySendUnack( uint8_t socketid); + +/** + * @brief Query the packets that are not sent successfully. + * + * @param socketid - TTL value + * @param(in) *addrlist - pointer to the address of the address list + * @param lislen - Length of the list + * + * @param(out) *addrlist - Address list of the data packets that are not sent successfully + * + * @return Number of unsent and unacknowledged segments + */ +uint8_t WCHNET_QueryUnack( uint8_t socketid, uint32_t *addrlist, uint16_t lislen ); + +/** + * @brief Start DHCP. + * + * @param dhcp - Application layer callback function + * + * @return @ERR_T + */ +uint8_t WCHNET_DHCPStart( dhcp_callback dhcp ); + +/** + * @brief Stop DHCP. + * + * @param None + * + * @return @ERR_T + */ +uint8_t WCHNET_DHCPStop( void ); + +/** + * @brief Configure DHCP host name. + * + * @param *name - First address of DHCP host name + * + * @return 0 - Success. Others - Failure. + */ +uint8_t WCHNET_DHCPSetHostname(char *name); + +/** + * @brief Initialize the resolver: set up the UDP pcb and configure the default server + * + * @param *dnsip - the IP address of dns server + * @param port - the port number of dns server + * + * @return None + */ +void WCHNET_InitDNS( uint8_t *dnsip, uint16_t port); + +/** + * @brief Stop DNS. + * + * @param None + * + * @return None + */ +void WCHNET_DNSStop(void); + +/** + * Resolve a hostname (string) into an IP address. + * + * @param hostname - the hostname that is to be queried + * @param addr - pointer to a struct ip_addr where to store the address if it is already + * cached in the dns_table (only valid if ERR_OK is returned!) + * @param found - a callback function to be called on success, failure or timeout (only if + * ERR_INPROGRESS is returned!) + * @param arg - argument to pass to the callback function + * + * @return @ERR_T + * WCHNET_ERR_SUCCESS if hostname is a valid IP address string or the host name is already in the local names table. + * ERR_INPROGRESS enqueue a request to be sent to the DNS server for resolution if no errors are present. + */ +uint8_t WCHNET_HostNameGetIp( const char *hostname, uint8_t *addr, dns_callback found, void *arg ); + +/** + * @brief Configure KEEP LIVE parameter. + * + * @param *cfg - KEEPLIVE configuration parameter + * + * @return None + */ +void WCHNET_ConfigKeepLive( struct _KEEP_CFG *cfg ); + +/** + * @brief Configure socket KEEP LIVE enable. + * + * @param socketid - socket id value + * @param enable - 1: Enabled. 0: Disabled. + * + * @return @ERR_T + */ +uint8_t WCHNET_SocketSetKeepLive( uint8_t socketid, uint8_t enable ); + +/** + * @brief Configure PHY state + * + * @param phy_stat - PHY state + * + * @return None + */ +void WCHNET_PhyStatus( uint32_t phy_stat ); + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/Peripheral/inc/ch564.h b/Peripheral/inc/ch564.h new file mode 100644 index 0000000..41abecc --- /dev/null +++ b/Peripheral/inc/ch564.h @@ -0,0 +1,1865 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : CH564 Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_H +#define __CH564_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define HSE_VALUE ((uint32_t)25000000) /* Value of the External oscillator in Hz */ +#define HSI_VALUE ((uint32_t)20000000) /* Value of the Internal oscillator in Hz */ + +/* HSE HSI and PLL stabilization time(us) */ +#define HSE_STARTUP_TIME ((uint32_t)2500) +#define HSI_STARTUP_TIME ((uint32_t)12) +#define PLL_STARTUP_TIME ((uint32_t)35) + + +/* CH564 Standard Peripheral Library version number */ +#define __CH564_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */ +#define __CH564_STDPERIPH_VERSION_SUB (0x02) /* [7:0] sub version */ +#define __CH564_STDPERIPH_VERSION ((__CH564_STDPERIPH_VERSION_MAIN << 8)\ + | (__CH564_STDPERIPH_VERSION_SUB << 0)) + +/* ********************************************************************************************************************* */ +/* Base types & constants */ + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif +#ifndef NULL +#define NULL 0 +#endif + +#ifndef VOID +#define VOID void +#endif +#ifndef CONST +#define CONST const +#endif +#ifndef BOOL +typedef unsigned char BOOL; +#endif +#ifndef BOOLEAN +typedef unsigned char BOOLEAN; +#endif +#ifndef CHAR +typedef char CHAR; +#endif +#ifndef INT8 +typedef char INT8; +#endif +#ifndef INT16 +typedef short INT16; +#endif +#ifndef INT32 +typedef long INT32; +#endif +#ifndef UINT8 +typedef unsigned char UINT8; +#endif +#ifndef UINT16 +typedef unsigned short UINT16; +#endif +#ifndef UINT32 +typedef unsigned long UINT32; +#endif +#ifndef UINT8V +typedef unsigned char volatile UINT8V; +#endif +#ifndef UINT16V +typedef unsigned short volatile UINT16V; +#endif +#ifndef UINT32V +typedef unsigned long volatile UINT32V; +#endif + +#ifndef PVOID +typedef void *PVOID; +#endif +#ifndef PCHAR +typedef char *PCHAR; +#endif +#ifndef PCHAR +typedef const char *PCCHAR; +#endif +#ifndef PINT8 +typedef char *PINT8; +#endif +#ifndef PINT16 +typedef short *PINT16; +#endif +#ifndef PINT32 +typedef long *PINT32; +#endif +#ifndef PUINT8 +typedef unsigned char *PUINT8; +#endif +#ifndef PUINT16 +typedef unsigned short *PUINT16; +#endif +#ifndef PUINT32 +typedef unsigned long *PUINT32; +#endif +#ifndef PUINT8V +typedef volatile unsigned char *PUINT8V; +#endif +#ifndef PUINT16V +typedef volatile unsigned short *PUINT16V; +#endif +#ifndef PUINT32V +typedef volatile unsigned long *PUINT32V; +#endif + +/* ********************************************************************************************************************* */ +/* Base macros */ + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#if DEBUG +#define PRINT(X...) printf(X) +#else +#define PRINT(X...) +#endif + +/* Calculate the byte offset of a field in a structure of type */ +#define FIELD_OFFSET(Type, Field) ((UINT16)&(((Type *)0)->Field)) + +/* Calculate the size of a field in a structure of type */ +#define FIELD_SIZE(Type, Field) (sizeof(((Type *)0)->Field)) + +/* An expression that yields the type of a field in a struct */ +#define FIELD_TYPE(Type, Field) (((Type *)0)->Field) + +/* Return the number of elements in a statically sized array */ +#define NUMBER_OF(Array) (sizeof(Array)/sizeof((Array)[0])) +#define NUMBER_OF_FIELD(Type, Field) (NUMBER_OF(FIELD_TYPE(Type, Field))) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = 3, /* 3 HardFault Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + /****** RISC-V specific Interrupt Numbers *********************************************************/ + IIC_EV_IRQn = 16, /* 16 IIC Event Interrupt */ + IIC_ER_IRQn = 17, /* 17 IIC Error Interrupt */ + ETH_IRQn = 18, /* 18 ETH Global Interrupt */ + USBPD_IRQn = 19, /* 19 USBPD Global Interrupt */ + TIM0_IRQn = 20, /* 20 TIM0 Global Interrupt */ + TIM1_IRQn = 21, /* 21 TIM1 Global Interrupt */ + TIM2_IRQn = 22, /* 22 TIM2 Global Interrupt */ + TIM3_IRQn = 23, /* 23 TIM3 Global Interrupt */ + SPI0_IRQn = 24, /* 24 SPI0 Global Interrupt */ + SPI1_IRQn = 25, /* 25 SPI1 Global Interrupt */ + UART0_IRQn = 26, /* 26 UART0 Global Interrupt */ + UART1_IRQn = 27, /* 27 UART1 Global Interrupt */ + PA_IRQn = 28, /* 28 PA External Interrupt */ + PB_IRQn = 29, /* 29 PB External Interrupt */ + PD_IRQn = 30, /* 30 PC External Interrupt */ + ADC_IRQn = 31, /* 31 ADC Global Interrupt */ + SLV_IRQn = 32, /* 32 Slave Parallel Port Global Interrupt */ + USBHS_HOST_IRQn = 33, /* 33 USBHOST Global Interrupt */ + USBHS_DEV_IRQn = 34, /* 34 USBDEVICE Global Interrupt */ + UART2_IRQn = 35, /* 35 UART0 Global Interrupt */ + UART3_IRQn = 36, /* 36 UART1 Global Interrupt */ + ETHWakeUp_IRQn = 37, /* 37 ETH Wake up Interrupt */ + USBHSWakeUp_IRQn = 38, /* 38 USBHS Wake up Interrupt */ + USBPDWakeUp_IRQn = 39, /* 39 USBPD Wake up Interrupt */ +} IRQn_Type; + +#include +#include "core_riscv.h" +#include "system_ch564.h" + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint8_t SAFE_ACCESS_SIG; + uint8_t RESERVED0; + __IO uint8_t SAFE_ACCESS_ID; + __IO uint8_t WDOG_CLEAR; + __IO uint8_t GLOB_MEM_CFG; + __IO uint8_t GLOB_LOCK_PORT; + __IO uint8_t GLOB_RST_CFG; + __IO uint8_t GLOB_RESET_KEEP; + uint8_t RESERVED1; + __IO uint8_t PLL_OUT_DIV; + uint16_t RESERVED2; + __IO uint8_t SLP_CLK_OFF0; + __IO uint8_t SLP_CLK_OFF1; + __IO uint8_t SLP_WAKE_CTRL; + __IO uint8_t SLP_CTRL_PLL; +} RCC_Typedef; + +/* General Purpose Input Output */ +typedef struct +{ + __IO uint32_t DIR; + __IO uint32_t PIN; + __IO uint32_t OUT; + __IO uint32_t CLR; + __IO uint32_t PU; + __IO uint32_t PD; +} GPIO_Typedef; + +/* Alternate Function IO */ +typedef struct +{ + __IO uint32_t PCFR1; + __IO uint32_t RESERVED1[7]; + __IO uint32_t PCFR2; +} AFIO_Typedef; + +/* External Interrupts */ +typedef struct +{ + __IO uint32_t STATUS; + __IO uint32_t ENABLE; + __IO uint32_t MODE; + __IO uint32_t POLAR; +} EXTI_Typedef; + +/* Timer */ +typedef struct +{ + __IO uint8_t CTRL_MOD; + __IO uint8_t CTRL_DMA; + __IO uint8_t INTER_EN; + uint8_t RESERVED0[3]; + __IO uint8_t INT_FLAG; + __IO uint8_t FIFO_COUNT; + __IO uint32_t COUNT; + __IO uint32_t CNT_END; + __IO uint32_t FIFO; + union + { + __IO uint32_t TMR0_DMA_NOW; + __IO uint32_t TMR1_DMA_NOW; + __IO uint32_t TMR2_DMA_NOW; + uint32_t RESERVED1; + }; + union + { + __IO uint32_t TMR0_DMA_BEG; + __IO uint32_t TMR1_DMA_BEG; + __IO uint32_t TMR2_DMA_BEG; + uint32_t RESERVED2; + }; + union + { + __IO uint32_t TMR0_DMA_END; + __IO uint32_t TMR1_DMA_END; + __IO uint32_t TMR2_DMA_END; + uint32_t RESERVED3; + }; + +} TIM_Typedef; + +/* Analog-to-Digital Converter */ +typedef struct +{ + __IO uint8_t CTRL_MOD; + __IO uint8_t CTRL_DMA; + __IO uint8_t INTER_EN; + __IO uint8_t CLOCK_DIV; + __IO uint16_t DATA; + __IO uint8_t INT_FLAG; + __IO uint8_t FIFO_COUNT; + __IO uint32_t CTRL; + __IO uint16_t CMP_VALUE; + uint16_t RESERVED0; + __IO uint16_t FIFO; + uint16_t RESERVED1; + __IO uint32_t DMA_NOW; + __IO uint32_t DMA_BEG; + __IO uint32_t DMA_END; +} ADC_Typedef; + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct +{ + union + { + __IO uint8_t RBR; + __IO uint8_t THR; + __IO uint8_t DLL; + __IO uint8_t ADR; + }; + union + { + __IO uint8_t IER; + __IO uint8_t DLM; + }; + union + { + __IO uint8_t IIR; + __IO uint8_t FCR; + }; + __IO uint8_t LCR; + __IO uint8_t MCR; + __IO uint8_t LSR; + __IO uint8_t MSR; + __IO uint8_t DIV; + __IO uint8_t DMA_CTRL; + __IO uint8_t DMA_IF; + uint16_t RESERVED0; + __IO uint32_t DMA_WR_NOW_ADDR; + __IO uint32_t DMA_WR_START_ADDR; + __IO uint32_t DMA_WR_END_ADDR; + __IO uint32_t DMA_RD_NOW_ADDR; + __IO uint32_t DMA_RD_START_ADDR; + __IO uint32_t DMA_RD_END_ADDR; +} UART_Typedef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; +} I2C_Typedef; + +/* Serial Peripheral Interface */ +typedef struct +{ + union + { + __IO uint32_t CONTROL_R32; + struct + { + __IO uint8_t CTRL_MOD; + __IO uint8_t CTRL_DMA; + __IO uint8_t INTER_EN; + union + { + __IO uint8_t CLOCK_DIV; + __IO uint8_t SLAVE_PRE; + }; + }; + }; + union + { + __IO uint32_t STATUS_R32; + struct + { + __IO uint8_t BUFFER; + __IO uint8_t RUN_FLAG; + __IO uint8_t INT_FLAG; + __IO uint8_t FIFO_COUNT; + }; + }; + __IO uint8_t RESET_CMD; + __IO uint8_t BUSY; + uint16_t RESERVED0; + __IO uint16_t TOTAL_CNT; + uint16_t RESERVED1; + union + { + __IO uint32_t FIFO_R32; + struct + { + __IO uint8_t FIFO; + uint16_t RESERVED2; + __IO uint8_t FIFO_COUNT1; + }; + }; + union + { + __IO uint32_t SPI0_DMA_NOW; + uint32_t RESERVED3; + }; + union + { + __IO uint32_t SPI0_DMA_BEG; + uint32_t RESERVED4; + }; + union + { + __IO uint32_t SPI0_DMA_END; + uint32_t RESERVED5; + }; +} SPI_Typedef; + +/* passive parallel port (computing) */ +typedef struct +{ + __IO uint8_t CONFIG; + uint8_t RESERVED0; + __IO uint8_t DOUT; + __IO uint8_t STATUS; + uint8_t RESERVED1[42]; + __IO uint8_t INT_FLAG_SLV; + __IO uint8_t INT_SLV_DIN; + uint8_t RESERVED2[316]; + __IO uint8_t DMA_EN_SLV; + __IO uint8_t DMA_MODE_CTRL_SLV; + __IO uint8_t DMA_MODE_EN_SLV; + uint8_t RESERVED3; + __IO uint8_t DMA_INT_FLAG_SLV; + uint8_t RESERVED4[3]; + __IO uint32_t WR_DMA_START_ADDR_SLV; + __IO uint32_t WR_DMA_END_ADDR_SLV; + uint32_t RESERVED5; + __IO uint32_t RD_DMA_START_ADDR_SLV; + __IO uint32_t RD_DMA_END_ADDR_SLV; + __IO uint32_t DMA_END_NOW_SLV; + __IO uint8_t DMA_CMD0_SLV; + __IO uint8_t DMA_CMD1_SLV; + uint16_t RESERVED6; + __IO uint8_t SLV_RESET_CMD; + __IO uint8_t SLV_BUSY; + uint8_t RESERVED7[10]; + __IO uint8_t OTHER_DATA; + uint8_t RESERVED9[3]; + __IO uint16_t DMA_DEC_LEN; + __IO uint16_t DMA_DEC_OFFSET; +} SLV_Typedef; + +/* XBUS */ +typedef struct +{ + __IO uint8_t CONFIG; + uint8_t RESERVED0; + __IO uint8_t CYCLE; + __IO uint8_t SETUP_HOLD; +} XBUS_Typedef; + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[8]; + __IO uint32_t PHY_CR; + __IO uint32_t CHKSUM_CR; + __IO uint32_t IP_PDR; + __IO uint32_t CHKSUM_HR; + __IO uint32_t CHKSUM_PR; + uint32_t RESERVED3[27]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED4[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED5[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + __IO uint32_t MMCRAFCR; + __IO uint32_t ETH_STATE; + uint32_t RESERVED7[8]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED8[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED9[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED10[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_Typedef; + +/* USB Power Delivery */ +typedef struct +{ + union + { + __IO uint32_t CONFIG_R32; + struct + { + __IO uint16_t CONFIG; + __IO uint16_t BMC_CLK_CNT; + }; + }; + union + { + __IO uint32_t CONTROL_R32; + struct + { + union + { + __IO uint16_t CONTROL_R16; + struct + { + __IO uint8_t CONTROL; + __IO uint8_t TX_SEL; + }; + }; + __IO uint16_t BMC_TX_SZ; + }; + }; + union + { + __IO uint32_t STATUS_R32; + struct + { + union + { + __IO uint16_t STATUS_16; + struct + { + __IO uint8_t DATA_BUF; + __IO uint8_t STATUS; + }; + }; + __IO uint16_t BMC_BYTE_CNT; + }; + }; + union + { + __IO uint32_t PORT_R32; + struct + { + __IO uint16_t PORT_CC1; + __IO uint16_t PORT_CC2; + }; + }; + union + { + __IO uint32_t DMA_R32; + struct + { + __IO uint16_t DMA; + uint16_t RESERVED0; + }; + }; +} USBPD_Typedef; + +/* USB High-Speed Device */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t BASE_MODE; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint8_t WAKE_CR; + __IO uint8_t TEST_MODE; + __IO uint16_t LPM_DATA; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint8_t MIS_ST; + __IO uint8_t reserve1; + __IO uint16_t FRAME_NO; + __IO uint16_t USB_BUS; + __IO uint16_t UEP_TX_EN; + __IO uint16_t UEP_RX_EN; + __IO uint16_t UEP_T_TOG_AUTO; + __IO uint16_t UEP_R_TOG_AUTO; + __IO uint16_t UEP_T_BURST; + __IO uint16_t UEP_R_BURST; + __IO uint32_t UEP_AF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP0_MAX_LEN; + __IO uint32_t UEP1_MAX_LEN; + __IO uint32_t UEP2_MAX_LEN; + __IO uint32_t UEP3_MAX_LEN; + __IO uint32_t UEP4_MAX_LEN; + __IO uint32_t UEP5_MAX_LEN; + __IO uint32_t UEP6_MAX_LEN; + __IO uint32_t UEP7_MAX_LEN; + __IO uint16_t UEP0_RX_LEN; + __IO uint16_t UEP0_RX_SIZE; + __IO uint16_t UEP1_RX_LEN; + __IO uint16_t UEP1_RX_SIZE; + __IO uint16_t UEP2_RX_LEN; + __IO uint16_t UEP2_RX_SIZE; + __IO uint16_t UEP3_RX_LEN; + __IO uint16_t UEP3_RX_SIZE; + __IO uint16_t UEP4_RX_LEN; + __IO uint16_t UEP4_RX_SIZE; + __IO uint16_t UEP5_RX_LEN; + __IO uint16_t UEP5_RX_SIZE; + __IO uint16_t UEP6_RX_LEN; + __IO uint16_t UEP6_RX_SIZE; + __IO uint16_t UEP7_RX_LEN; + __IO uint16_t UEP7_RX_SIZE; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP_TX_ISO; + __IO uint16_t UEP_RX_ISO; +} USBHSD_TypeDef; + +typedef struct +{ + __IO uint8_t CFG; + __IO uint8_t RESERVE1; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint32_t CONTROL; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint8_t MIS_ST; + __IO uint8_t RESERVE2; + __IO uint32_t LPM; + __IO uint32_t SPLIT; + __IO uint32_t FRAME; + __IO uint32_t HOST_TX_LEN; + __IO uint32_t RX_LEN; + __IO uint32_t HOST_RX_MAX_LEN; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t PORT_CTRL; + __IO uint8_t PORT_CFG; + __IO uint8_t RESERVE3; + __IO uint8_t PORT_INT_EN; + __IO uint8_t PORT_TEST_CT; + __IO uint16_t PORT_STATUS; + __IO uint8_t PORT_STATUS_CHG; + __IO uint32_t RESERVE4; + __IO uint32_t ROOT_BC_CR; +} USBHSH_TypeDef; + +typedef struct +{ + __IO uint32_t CAL_CR; +} USBHSI_TypeDef; + +/* Expansion Registers */ +typedef struct +{ + __IO uint32_t CTLR0; + uint32_t RESERVED0[3]; + __IO uint32_t CTLR1; + uint32_t RESERVED1[5]; + __IO uint32_t CTLR2; +} EXTEN_Typedef; + +/* Flash Registers */ +typedef struct +{ + __IO uint8_t DATA; + uint8_t RESERVED0; + __IO uint8_t CTRL; + __IO uint16_t FLASHA_KEY_BUF; +} FLASH_Typedef; + +/* Debug Registers */ +typedef struct +{ + __IO uint32_t CR; +} DBG_Typedef; + +#define RCC_BASE ((uint32_t)0x40400000) +#define GPIOA_BASE ((uint32_t)0x40400080) +#define GPIOB_BASE ((uint32_t)0x404000A0) +#define GPIOD_BASE ((uint32_t)0x404000C0) +#define AFIO_BASE ((uint32_t)0x40400140) +#define EXTIA_BASE ((uint32_t)0x40400050) +#define EXTIB_BASE ((uint32_t)0x40400060) +#define EXTID_BASE ((uint32_t)0x40400070) +#define TIM0_BASE ((uint32_t)0x40408000) +#define TIM1_BASE ((uint32_t)0x40408400) +#define TIM2_BASE ((uint32_t)0x40408800) +#define TIM3_BASE ((uint32_t)0x40408C00) +#define ADC_BASE ((uint32_t)0x4040A000) +#define UART0_BASE ((uint32_t)0x4040D000) +#define UART1_BASE ((uint32_t)0x4040D800) +#define UART2_BASE ((uint32_t)0x40409000) +#define UART3_BASE ((uint32_t)0x40409800) +#define I2C_BASE ((uint32_t)0x4040F000) +#define SPI0_BASE ((uint32_t)0x4040C000) +#define SPI1_BASE ((uint32_t)0x4040C800) +#define SLV_BASE ((uint32_t)0x40400014) +#define XBUS_BASE ((uint32_t)0x40400010) +#define ETH_BASE ((uint32_t)0x40406000) +#define USBPD_BASE ((uint32_t)0x4040E000) +#define USBHSD_BASE ((uint32_t)0x40404000) +#define USBHSH_BASE ((uint32_t)0x40404800) +#define USB_HSI_BASE ((uint32_t)0x40005000) +#define EXTEN_BASE ((uint32_t)0x40400144) +#define FLASH_BASE ((uint32_t)0x40400018) + +#define RCC ((RCC_Typedef *)RCC_BASE) +#define GPIOA ((GPIO_Typedef *)GPIOA_BASE) +#define GPIOB ((GPIO_Typedef *)GPIOB_BASE) +#define GPIOD ((GPIO_Typedef *)GPIOD_BASE) +#define AFIO ((AFIO_Typedef *)AFIO_BASE) +#define EXTIA ((EXTI_Typedef *)EXTIA_BASE) +#define EXTIB ((EXTI_Typedef *)EXTIB_BASE) +#define EXTID ((EXTI_Typedef *)EXTID_BASE) +#define TIM0 ((TIM_Typedef *)TIM0_BASE) +#define TIM1 ((TIM_Typedef *)TIM1_BASE) +#define TIM2 ((TIM_Typedef *)TIM2_BASE) +#define TIM3 ((TIM_Typedef *)TIM3_BASE) +#define ADC ((ADC_Typedef *)ADC_BASE) +#define UART0 ((UART_Typedef *)UART0_BASE) +#define UART1 ((UART_Typedef *)UART1_BASE) +#define UART2 ((UART_Typedef *)UART2_BASE) +#define UART3 ((UART_Typedef *)UART3_BASE) +#define I2C ((I2C_Typedef *)I2C_BASE) +#define SPI0 ((SPI_Typedef *)SPI0_BASE) +#define SPI1 ((SPI_Typedef *)SPI1_BASE) +#define SLV ((SLV_Typedef *)SLV_BASE) +#define XBUS ((XBUS_Typedef *)XBUS_BASE) +#define ETH ((ETH_Typedef *)ETH_BASE) +#define USBPD ((USBPD_Typedef *)USBPD_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHSD_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHSH_BASE) +#define USB_HSI ((USBHSI_TypeDef *) USB_HSI_BASE) +#define EXTEN ((EXTEN_Typedef *)EXTEN_BASE) +#define FLASH ((FLASH_Typedef *)FLASH_BASE) +#define DBG ((DBG_Typedef *)DBG_BASE) + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE + + +/******************************************************************************/ + +// Address Space +// CODE: 00000000H - 000FFFFFH, 1MB +// SFR: 00400000H - 0040FFFFH, 64KB +// DATA: 00808000H - 0081FFFFH, 96KB/64KB/32KB +// XBUS: 00C00000H - 00CFFFFFH, 1MB +// OTHER: 00E00000H - FFFFFFFFH, undefined +// +// SFR: 00400000H - 0040FFFFH, 64KB +// SYS: +1000H - 1FFFH, include base config, interrupt, GPIO, etc... +// USB: +4000H - 5FFFH +// ETH: +6000H - 7FFFH +// TMR0: +8000H - 83FFH +// TMR1: +8400H - 87FFH +// TMR2: +8800H - 8BFFH +// TMR3: +8C00H - 8FFFH +// ADC: +A000H - AFFFH +// SPI0: +C000H - C7FFH +// SPI1: +C800H - CFFFH +// UART0: +D000H - D7FFH +// UART1: +D800H - DFFFH + +// Register Bit Attribute / Bit Access Type +// RF: Read only for Fixed value +// RO: Read Only (internal change) +// RZ: Read only with auto clear Zero +// WO: Write Only (read zero or different) +// WA: Write only under safe Accessing mode (read zero or different) +// WZ: Write only with auto clear Zero +// RW: Read / Write +// RWA: Read / Write under safe Accessing mode +// RW1: Read / Write 1 to Clear + +/* Register name rule: +R32_* for 32 bits register (UINT32,ULONG) +R16_* for 16 bits register (UINT16,USHORT) +R8_* for 8 bits register (UINT8,UCHAR) +RB_* for bit or bit mask of 8 bit register +BA_* for base address point +Others for register address offset */ + +/* ********************************************************************************************************************* */ +/* System: safe accessing register */ +#define R32_SAFE_ACCESS (*((volatile uint32_t *)0x40400000)) // RW, safe accessing +#define R8_SAFE_ACCESS_SIG (*((volatile uint8_t *)0x40400000)) // WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode +#define RB_SAFE_ACC_MODE 0x03 // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11) +#define RB_SAFE_ACC_TIMER 0x70 // RO, safe accessing timer bit mask (16*clock number) +#define R8_SAFE_ACCESS_ID (*((volatile uint8_t *)0x40400002)) // RF, safe accessing ID register, always 0x01 +#define R8_WDOG_CLEAR (*((volatile uint8_t *)0x40400003)) // WO, clear watch-dog + +/* System: global configuration register */ +#define R32_GLOBAL_CONFIG (*((volatile uint32_t *)0x40400004)) // RW, global configuration +#define R8_GLOB_MEM_CFG (*((volatile uint8_t *)0x40400004)) // RWA, global memory configuration, SAM and bit7:6 must write 1:0 +#define RB_GLOB_MEM_CFG 0x03 // RWA, global memory config: 10=C96K/D32K, 11=C32K/D96K, 00/01=C64K/D64K +#define RB_GLOB_CFG_FLAG 0x80 // RO, global config flag +#define R8_GLOB_LOCK_PORT (*((volatile uint8_t *)0x40400005)) // RWA, lock port configuration, SAM and bit7:6 must write 0:0 +#define RB_GLOB_LOCK_PA 0x01 // RWA, lock GPIO PA +#define RB_GLOB_LOCK_PB 0x02 // RWA, lock GPIO PB +#define RB_GLOB_LOCK_PD 0x08 // RWA, lock GPIO PD +#define R8_GLOB_RST_CFG (*((volatile uint8_t *)0x40400006)) // RWA, global reset configuration, SAM and bit7:6 must write 0:1 +#define RB_GLOB_FORCE_RST 0x01 // WA/WZ, force global reset, high action, auto clear +#define RB_GLOB_WDOG_EN 0x02 // RWA, watch-dog enable +#define R8_GLOB_RESET_KEEP (*((volatile uint8_t *)0x40400007)) // RW, value keeper during global reset + +/* System: PLL configuration register */ +#define R32_PLL_CONFIG (*((volatile uint32_t *)0x40400008)) // RWA, PLL configuration, SAM +#define R8_PLL_OUT_DIV (*((volatile uint8_t *)0x40400009)) // RWA, PLL output clock divider, SAM and bit7:6 must write 1:0 +#define RB_PLL_ETH_DIV 0x0F // RWA, PLL ethernet clock divider +#define RB_PLL_SYS_DIV 0x30 // RWA, PLL system clock divider + +/* System: sleep control register */ +#define R32_SLEEP_CONTROL (*((volatile uint32_t *)0x4040000C)) // RWA, sleep control, SAM +#define R8_SLP_CLK_OFF0 (*((volatile uint8_t *)0x4040000C)) // RWA, sleep clock off control byte 0, SAM +#define RB_SLP_CLK_TMR0 0x01 // RWA, sleep TMR0 clock +#define RB_SLP_CLK_TMR1 0x02 // RWA, sleep TMR1 clock +#define RB_SLP_CLK_TMR2 0x04 // RWA, sleep TMR2 clock +#define RB_SLP_CLK_TMR3 0x08 // RWA, sleep TMR3 clock +#define RB_SLP_CLK_SPI0 0x10 // RWA, sleep SPI0 clock +#define RB_SLP_CLK_SPI1 0x20 // RWA, sleep SPI1 clock +#define RB_SLP_CLK_UART0 0x40 // RWA, sleep UART0 clock +#define RB_SLP_CLK_UART1 0x80 // RWA, sleep UART1 clock +#define R8_SLP_CLK_OFF1 (*((volatile uint8_t *)0x4040000D)) // RWA, sleep clock off control byte 1, SAM +#define RB_SLP_CLK_UTMI 0x02 // RWA, sleep UTMI clock +#define RB_SLP_CLK_I2C 0x04 // RWA, sleep I2C clock +#define RB_SLP_CLK_USBPD 0x08 // RWA, sleep USBPD clock +#define RB_SLP_CLK_ADC 0x10 // RWA, sleep ADC clock +#define RB_SLP_CLK_GPIO 0x20 // RWA, sleep GPIO clock +#define RB_SLP_CLK_USB 0x40 // RWA, sleep USB clock +#define RB_SLP_CLK_ETH 0x80 // RWA, sleep Ethernet clock +#define R8_SLP_WAKE_CTRL (*((volatile uint8_t *)0x4040000E)) // RWA, wake control, SAM +#define RB_SLP_PA_WAKE 0x01 // RWA，enable PA waking +#define RB_SLP_PB_WAKE 0x02 // RWA，enable PB waking +#define RB_SLP_USBPD_WAKE 0x04 // RWA，enable USBPD waking +#define RB_SLP_PD_WAKE 0x08 // RWA，enable PD waking +#define RB_SLP_USB_WAKE 0x10 // RWA，enable USB waking +#define RB_SLP_WOL_WAKE 0x40 // RWA，enable Ethernet WOL waking +#define RB_SLP_ETH_PWR_DN 0x80 // RWA，Ethernet module power control +#define R8_SLP_CTRL_PLL (*((volatile uint8_t *)0x4040000F)) // WA, PLL sleep control, SAM and write 0x6A to sleep CPU or write 0x95 to sleep PLL +#define R8_SLP_STATUS (*((volatile uint8_t *)0x4040000F)) // RO, sleep status +#define RB_SLP_WOL_STATUS 0x01 // RO, current ethernet WOL status +#define RB_SLP_CLK_UART2 0x02 // RWA, sleep UART2 clock +#define RB_SLP_CLK_UART3 0x04 // RWA, sleep UART3 clock +/* System: external bus configuration register */ +#define R32_EXT_BUS_CFG (*((volatile uint32_t *)0x40400010)) // RW, external bus configuration +#define R8_XBUS_CONFIG (*((volatile uint8_t *)0x40400010)) // RW, external bus configuration +#define RB_XBUS_ENABLE 0x01 // RWA, external bus enable +#define RB_XBUS_EN_32BIT 0x02 // RW, enable 16bit or 32bit external bus +#define RB_XBUS_ADDR_OE 0x0C // RWA, bus address output enable: 00=none,01=PA[5:0],10=PA[11:0],11=PA[19:0] +#define R8_XBUS_CYCLE (*((volatile uint8_t *)0x40400012)) // RW, external bus total cycle (clock number), only low 5 bit +#define R8_XBUS_SETUP_HOLD (*((volatile uint8_t *)0x40400013)) // RW, external bus setup and hold config +#define RB_XBUS_HOLD 0x1F // RW, external bus hold time bit mask (clock number) +#define RB_XBUS_SETUP 0x80 // RW, external bus setup time: 0=1 clock, 1=2 clocks + +/* System: parallel slave configuration register */ +#define R32_PARA_SLV_CFG (*((volatile uint32_t *)0x40400014)) // RW, parallel slave configuration +#define R8_SLV_CONFIG (*((volatile uint8_t *)0x40400014)) // RWA, parallel slave configuration, SAM +#define RB_SLV_ENABLE 0x01 // RWA, parallel slave enable +#define RB_SLV_IE_CMD 0x02 // RWA, enable interrupt for slave writing command event +#define RB_SLV_IE_WR 0x04 // RWA, enable interrupt for slave writing event +#define RB_SLV_IE_RD 0x08 // RWA, enable interrupt for slave reading event +#define R8_SLV_DOUT (*((volatile uint8_t *)0x40400016)) // RW, parallel slave data to output +#define R8_SLV_STATUS (*((volatile uint8_t *)0x40400017)) // RW, parallel slave status to output, only low 7 bit + +/* Interrupt vector register */ +#define R32_INT_VEC_CTRL (*((volatile uint32_t *)0x40400020)) // RWA, interrupt vector control, SAM +#define R8_INT_VEC_IRQ (*((volatile uint8_t *)0x40400020)) // RWA, IRQ normal interrupt vector control, SAM +#define RB_IV_IRQ_TMR0 0x01 // RWA, TMR0 IRQ vector enable +#define RB_IV_IRQ_SPI0 0x02 // RWA, SPI0 IRQ vector enable +#define RB_IV_IRQ_PB 0x04 // RWA, GPIO PB IRQ vector enable +#define R8_INT_VEC_FIQ (*((volatile uint8_t *)0x40400021)) // RWA, FIQ fast interrupt vector control, SAM +#define RB_IV_FIQ_TMR0 0x01 // RWA, TMR0 FIQ vector enable +#define RB_IV_FIQ_SPI0 0x02 // RWA, SPI0 FIQ vector enable +#define RB_IV_FIQ_PB 0x04 // RWA, GPIO PB FIQ vector enable +#define R32_INT_VEC_TMR0 (*((volatile uint32_t *)0x40400024)) // RWA, interrupt vector for TMR0, SAM +#define R32_INT_VEC_SPI0 (*((volatile uint32_t *)0x40400028)) // RWA, interrupt vector for SPI0, SAM +#define R32_INT_VEC_PB (*((volatile uint32_t *)0x4040002C)) // RWA, interrupt vector for GPIO PB, SAM + +/* Interrupt flag register */ +#define R32_INT_FLAG (*((volatile uint32_t *)0x40400040)) // RW, interrupt flag +#define R8_INT_FLAG_0 (*((volatile uint8_t *)0x40400040)) // RO, interrupt flag byte 0 +#define RB_IF_TMR0 0x01 // RO, interrupt flag of TMR0 +#define RB_IF_TMR1 0x02 // RO, interrupt flag of TMR1 +#define RB_IF_TMR2 0x04 // RO, interrupt flag of TMR2 +#define RB_IF_TMR3 0x08 // RO, interrupt flag of TMR3 +#define RB_IF_SPI0 0x10 // RO, interrupt flag of SPI0 +#define RB_IF_SPI1 0x20 // RO, interrupt flag of SPI1 +#define RB_IF_UART0 0x40 // RO, interrupt flag of UART0 +#define RB_IF_UART1 0x80 // RO, interrupt flag of UART1 +#define R8_INT_FLAG_1 (*((volatile uint8_t *)0x40400041)) // RO, interrupt flag byte 1 +#define RB_IF_PA 0x01 // RO, interrupt flag of GPIO PA +#define RB_IF_PB 0x02 // RO, interrupt flag of GPIO PB +#define RB_INT_WOL_STATUS 0x04 // RO, current ethernet WOL status +#define RB_IF_PD 0x08 // RO, interrupt flag of GPIO PD +#define RB_IF_ADC 0x10 // RO, interrupt flag of ADC +#define RB_IF_SLV 0x20 // RO, interrupt flag of parallel slave +#define RB_IF_USB 0x40 // RO, interrupt flag of USB +#define RB_IF_ETH 0x80 // RO, interrupt flag of ethernet +#define R8_INT_FLAG_SLV (*((volatile uint8_t *)0x40400042)) // RW1, parallel slave interrupt flag +#define RB_IF_SLV_CMD0 0x10 // RO, parallel slave command raw flag +#define RB_IF_SLV_CMD 0x20 // RO, parallel slave command synchro flag +#define RB_IF_SLV_WR 0x40 // RW1, interrupt flag of parallel slave writing event +#define RB_IF_SLV_RD 0x80 // RW1, interrupt flag of parallel slave reading event +#define R8_INT_SLV_DIN (*((volatile uint8_t *)0x40400043)) // RO, parallel slave data input +/*SLV DMA enable register*/ +#define R8_DMA_EN_SLV (*((volatile uint8_t *)0x40400180)) //SLV DMA enable register +#define RB_DMA_EN_SLV 0x01 //SLV DMA mode enable control bit +#define RB_DMA_RESP_IE_SLV 0x02 //SLV DMA error transmission interrupts enable control bit +#define RB_DMA_END_IE_SLV 0x04 //SLV DMA error transmission end enable control bit +#define RB_DMA_LOOP_EN_SLV 0x08 //SLV DMA cyclic address mode control bits +#define RB_DMA_FIFO_OV_IE_SLV 0x10 //The FIFO full state interrupts the enable bit +#define RB_DMA_OTHER_IE_SLV 0x20 //when in compatibility mode, Transmission of non-DMA datastate interrupts the enable bit +#define RB_DMA_WR_8BIT 0x40 //selection of transfer data length for DMA write operations +/*SLV DMA mode control register*/ +#define R8_DMA_MODE_CTRL_SLV (*((volatile uint8_t *)0x40400181)) //SLV DMA mode control register +#define CMD0_WR_MODE 0x40 //DMA transfer command word 0 read and write type +#define CMD1_WR_MODE 0x80 //DMA transfer command word 1 read and write type +/*SLV DMA mode enable register*/ +#define R8_DMA_MODE_EN_SLV (*((volatile uint8_t *)0x40400182)) //SLV DMA mode enable register +#define CMD0_EN 0x01 //DMA transfer command word 0 control bit +#define CMD1_EN 0x02 //DMA transfer command word 1 control bit +#define DMA_CMD_MODE1 0x08 //DMA transfer command word mode1 +/*SLV DMA interrupt flag register*/ +#define R8_DMA_INT_FLAG_SLV (*((volatile uint8_t *)0x40400184)) //SLV DMA interrupt flag register +#define WR_DMA_END_IF 0x01 //DMA receive mode transmission end flag bit +#define WR_DMA_RESP_IF 0x02 //DMA receive mode transmission error flag bit +#define RD_DMA_END_IF 0x04 //DMA occurrence mode transmission end flag bit +#define RD_DMA_RESP_IF 0x08 //DMA occurrence mode transmission error flag bit +#define WR_DMA_OV_IF 0x10 //input FIFO full flag +#define WR_OTHER_IF 0x20 //data are written to the flag bit +#define DATA_IN_FIFO_EMPTY 0x40 //Whether DATA_IN_FIFO is empty +/*DMA receive mode start address register*/ +#define R32_WR_DMA_START_ADDR_SLV (*((volatile uint32_t *)0x40400188)) //DMA receive mode start address register +#define MASK_WR_DMA_START_ADDR_SLV 0x0003ffff //DMA receive mode start address +/*DMA receive mode end address register*/ +#define R32_WR_DMA_END_ADDR_SLV (*((volatile uint32_t *)0x4040018c)) //DMA receive mode end address register +#define MASK_WR_DMA_START_ADDR_SLV 0x0003ffff //DMA receive mode end address +/*DMA send mode start address register*/ +#define R32_RD_DMA_START_ADDR_SLV (*((volatile uint32_t *)0x40400194)) //DMA send mode start address register +#define MASK_RD_DMA_START_ADDR_SLV 0x0003ffff //DMA send mode start address +/*DMA send mode end address register*/ +#define R32_RD_DMA_END_ADDR_SLV (*((volatile uint32_t *)0x40400198)) //DMA send mode end address register +#define MASK_RD_DMA_START_ADDR_SLV 0x0003ffff //DMA send mode end address +/*DMA current address register*/ +#define R32_DMA_END_NOW_SLV (*((volatile uint32_t *)0x4040019c)) //DMA current address register +#define MASK_DMA_NOW_ADDR_SLV 0x0003ffff //DMA current address +/*DMA mode command word0 register*/ +#define R8_DMA_CMD0_SLV (*((volatile uint8_t *)0x404001a0)) //DMA mode command word0 register +/*DMA mode command word1 register*/ +#define R8_DMA_CMD1_SLV (*((volatile uint8_t *)0x404001a1)) //DMA mode command word1 register +/*DMA reset the command word register*/ +#define R8_SLV_RESET_CMD (*((volatile uint8_t *)0x404001a4)) //DMA reset the command word register +/*SLV busy flag register*/ +#define R8_SLV_BUSY (*((volatile uint8_t *)0x404001a5)) //SLV busy flag register +#define RB_SLV_BUSY 0x01 //SLV busy flag +/*Non-DMA writes to the data register*/ +#define R8_OTHER_DATA (*((volatile uint8_t *)0x404001b0)) //Non-DMA writes to the data register +/*DMA parses length register*/ +#define R16_DMA_DEC_LEN (*((volatile uint16_t *)0x404001b4)) //DMA parses length register +/*DMA resolves the offset address register*/ +#define R16_DMA_DEC_OFFSET (*((volatile uint16_t *)0x404001b6)) //DMA resolves the offset address register + + +/* GPIO PA interrupt register */ +#define R32_INT_STATUS_PA (*((volatile uint32_t *)0x40400050)) // RW1, GPIO PA interrupt flag +#define R8_INT_STATUS_PA_1 (*((volatile uint8_t *)0x40400051)) // RW1, GPIO PA interrupt flag byte 1 +#define R8_INT_STATUS_PA_2 (*((volatile uint8_t *)0x40400052)) // RW1, GPIO PA interrupt flag byte 2 +#define R32_INT_ENABLE_PA (*((volatile uint32_t *)0x40400054)) // RW, GPIO PA interrupt enable +#define R8_INT_ENABLE_PA_1 (*((volatile uint8_t *)0x40400055)) // RW, GPIO PA interrupt enable byte 1 +#define R8_INT_ENABLE_PA_2 (*((volatile uint8_t *)0x40400056)) // RW, GPIO PA interrupt enable byte 2 +#define R32_INT_MODE_PA (*((volatile uint32_t *)0x40400058)) // RW, GPIO PA interrupt mode: 0=level action, 1=edge action +#define R8_INT_MODE_PA_1 (*((volatile uint8_t *)0x40400059)) // RW, GPIO PA interrupt mode byte 1 +#define R8_INT_MODE_PA_2 (*((volatile uint8_t *)0x4040005A)) // RW, GPIO PA interrupt mode byte 2 +#define R32_INT_POLAR_PA (*((volatile uint32_t *)0x4040005C)) // RW, GPIO PA interrupt polarity: 0=normal/low level/fall edge, 1=invert/high level/rise edge +#define R8_INT_POLAR_PA_1 (*((volatile uint8_t *)0x4040005D)) // RW, GPIO PA interrupt polarity byte 1 +#define R8_INT_POLAR_PA_2 (*((volatile uint8_t *)0x4040005E)) // RW, GPIO PA interrupt polarity byte 2 + +/* GPIO PB interrupt register */ +#define R32_INT_STATUS_PB (*((volatile uint32_t *)0x40400060)) // RW1, GPIO PB interrupt flag +#define R8_INT_STATUS_PB_0 (*((volatile uint8_t *)0x40400060)) // RW1, GPIO PB interrupt flag byte 0 +#define R8_INT_STATUS_PB_1 (*((volatile uint8_t *)0x40400061)) // RW1, GPIO PB interrupt flag byte 1 +#define R8_INT_STATUS_PB_2 (*((volatile uint8_t *)0x40400062)) // RW1, GPIO PB interrupt flag byte 2 +#define R32_INT_ENABLE_PB (*((volatile uint32_t *)0x40400064)) // RW, GPIO PB interrupt enable +#define R8_INT_ENABLE_PB_0 (*((volatile uint8_t *)0x40400064)) // RW, GPIO PB interrupt enable byte 0 +#define R8_INT_ENABLE_PB_1 (*((volatile uint8_t *)0x40400065)) // RW, GPIO PB interrupt enable byte 1 +#define R8_INT_ENABLE_PB_2 (*((volatile uint8_t *)0x40400066)) // RW, GPIO PB interrupt enable byte 2 +#define R32_INT_MODE_PB (*((volatile uint32_t *)0x40400068)) // RW, GPIO PB interrupt mode: 0=level action, 1=edge action +#define R8_INT_MODE_PB_0 (*((volatile uint8_t *)0x40400068)) // RW, GPIO PB interrupt mode byte 0 +#define R8_INT_MODE_PB_1 (*((volatile uint8_t *)0x40400069)) // RW, GPIO PB interrupt mode byte 1 +#define R8_INT_MODE_PB_2 (*((volatile uint8_t *)0x4040006A)) // RW, GPIO PB interrupt mode byte 2 +#define R32_INT_POLAR_PB (*((volatile uint32_t *)0x4040006C)) // RW, GPIO PB interrupt polarity: 0=normal/low level/fall edge, 1=invert/high level/rise edge +#define R8_INT_POLAR_PB_0 (*((volatile uint8_t *)0x4040006C)) // RW, GPIO PB interrupt polarity byte 0 +#define R8_INT_POLAR_PB_1 (*((volatile uint8_t *)0x4040006D)) // RW, GPIO PB interrupt polarity byte 1 +#define R8_INT_POLAR_PB_2 (*((volatile uint8_t *)0x4040006E)) // RW, GPIO PB interrupt polarity byte 2 + +/* GPIO PD interrupt register */ +#define R32_INT_STATUS_PD (*((volatile uint32_t *)0x40400070)) // RW1, GPIO PD interrupt flag +#define R8_INT_STATUS_PD_0 (*((volatile uint8_t *)0x40400070)) // RW1, GPIO PD interrupt flag byte 0 +#define R8_INT_STATUS_PD_3 (*((volatile uint8_t *)0x40400073)) // RW1, GPIO PD interrupt flag byte 3 +#define R32_INT_ENABLE_PD (*((volatile uint32_t *)0x40400074)) // RW, GPIO PD interrupt enable +#define R8_INT_ENABLE_PD_0 (*((volatile uint8_t *)0x40400074)) // RW, GPIO PD interrupt enable byte 0 +#define R8_INT_ENABLE_PD_3 (*((volatile uint8_t *)0x40400077)) // RW, GPIO PD interrupt enable byte 3 +#define R32_INT_MODE_PD (*((volatile uint32_t *)0x40400078)) // RW, GPIO PD interrupt mode: 0=level action, 1=edge action +#define R8_INT_MODE_PD_0 (*((volatile uint8_t *)0x40400078)) // RW, GPIO PD interrupt mode byte 0 +#define R8_INT_MODE_PD_3 (*((volatile uint8_t *)0x4040007B)) // RW, GPIO PD interrupt mode byte 3 +#define R32_INT_POLAR_PD (*((volatile uint32_t *)0x4040007C)) // RW, GPIO PD interrupt polarity: 0=normal/low level/fall edge, 1=invert/high level/rise edge +#define R8_INT_POLAR_PD_0 (*((volatile uint8_t *)0x4040007C)) // RW, GPIO PD interrupt polarity byte 0 +#define R8_INT_POLAR_PD_3 (*((volatile uint8_t *)0x4040007F)) // RW, GPIO PD interrupt polarity byte 3 + +/* GPIO interrupt register address offset and bit define */ +#define BA_INT_PA ((volatile uint8_t *)0x40400050) // point GPIO PA interrupt base address +#define BA_INT_PB ((volatile uint8_t *)0x40400060) // point GPIO PB interrupt base address +#define BA_INT_PD ((volatile uint8_t *)0x40400070) // point GPIO PD interrupt base address +#define INT_GPIO_STATUS 0x00 +#define INT_GPIO_STATUS_0 0x00 +#define INT_GPIO_STATUS_1 0x01 +#define INT_GPIO_STATUS_2 0x02 +#define INT_GPIO_ENABLE 0x04 +#define INT_GPIO_ENABLE_0 0x04 +#define INT_GPIO_ENABLE_1 0x05 +#define INT_GPIO_ENABLE_2 0x06 +#define INT_GPIO_MODE 0x08 +#define INT_GPIO_MODE_0 0x08 +#define INT_GPIO_MODE_1 0x09 +#define INT_GPIO_MODE_2 0x0A +#define INT_GPIO_POLAR 0x0C +#define INT_GPIO_POLAR_0 0x0C +#define INT_GPIO_POLAR_1 0x0D +#define INT_GPIO_POLAR_2 0x0E + +/* GPIO PA register */ +#define R32_PA_DIR (*((volatile uint32_t *)0x40400080)) // RW, GPIO PA I/O direction: 0=in, 1=out +#define R8_PA_DIR_0 (*((volatile uint8_t *)0x40400080)) // RW, GPIO PA I/O direction byte 0 +#define R8_PA_DIR_1 (*((volatile uint8_t *)0x40400081)) // RW, GPIO PA I/O direction byte 1 +#define R8_PA_DIR_2 (*((volatile uint8_t *)0x40400082)) // RW, GPIO PA I/O direction byte 2 +#define R32_PA_PIN (*((volatile uint32_t *)0x40400084)) // RO, GPIO PA input +#define R8_PA_PIN_0 (*((volatile uint8_t *)0x40400084)) // RO, GPIO PA input byte 0 +#define R8_PA_PIN_1 (*((volatile uint8_t *)0x40400085)) // RO, GPIO PA input byte 1 +#define R8_PA_PIN_2 (*((volatile uint8_t *)0x40400086)) // RO, GPIO PA input byte 2 +#define R32_PA_OUT (*((volatile uint32_t *)0x40400088)) // RW, GPIO PA output +#define R8_PA_OUT_0 (*((volatile uint8_t *)0x40400088)) // RW, GPIO PA output byte 0 +#define R8_PA_OUT_1 (*((volatile uint8_t *)0x40400089)) // RW, GPIO PA output byte 1 +#define R8_PA_OUT_2 (*((volatile uint8_t *)0x4040008A)) // RW, GPIO PA output byte 2 +#define R32_PA_CLR (*((volatile uint32_t *)0x4040008C)) // WZ, GPIO PA clear output: 0=keep, 1=clear +#define R8_PA_CLR_0 (*((volatile uint8_t *)0x4040008C)) // WZ, GPIO PA clear output byte 0 +#define R8_PA_CLR_1 (*((volatile uint8_t *)0x4040008D)) // WZ, GPIO PA clear output byte 1 +#define R8_PA_CLR_2 (*((volatile uint8_t *)0x4040008E)) // WZ, GPIO PA clear output byte 2 +#define R32_PA_PU (*((volatile uint32_t *)0x40400090)) // RW, GPIO PA pullup resistance enable +#define R8_PA_PU_0 (*((volatile uint8_t *)0x40400090)) // RW, GPIO PA pullup resistance enable byte 0 +#define R8_PA_PU_1 (*((volatile uint8_t *)0x40400091)) // RW, GPIO PA pullup resistance enable byte 1 +#define R8_PA_PU_2 (*((volatile uint8_t *)0x40400092)) // RW, GPIO PA pullup resistance enable byte 2 +#define R32_PA_PD (*((volatile uint32_t *)0x40400094)) // RW, GPIO PA output open-drain & input pulldown resistance enable +#define R8_PA_PD_0 (*((volatile uint8_t *)0x40400094)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 0 +#define R8_PA_PD_1 (*((volatile uint8_t *)0x40400095)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 1 +#define R8_PA_PD_2 (*((volatile uint8_t *)0x40400096)) // RW, GPIO PA output open-drain & input pulldown resistance enable byte 2 + +/* GPIO PB register */ +#define R32_PB_DIR (*((volatile uint32_t *)0x404000A0)) // RW, GPIO PB I/O direction: 0=in, 1=out +#define R8_PB_DIR_0 (*((volatile uint8_t *)0x404000A0)) // RW, GPIO PB I/O direction byte 0 +#define R8_PB_DIR_1 (*((volatile uint8_t *)0x404000A1)) // RW, GPIO PB I/O direction byte 1 +#define R8_PB_DIR_2 (*((volatile uint8_t *)0x404000A2)) // RW, GPIO PB I/O direction byte 2 +#define R32_PB_PIN (*((volatile uint32_t *)0x404000A4)) // RO, GPIO PB input +#define R8_PB_PIN_0 (*((volatile uint8_t *)0x404000A4)) // RO, GPIO PB input byte 0 +#define R8_PB_PIN_1 (*((volatile uint8_t *)0x404000A5)) // RO, GPIO PB input byte 1 +#define R8_PB_PIN_2 (*((volatile uint8_t *)0x404000A6)) // RO, GPIO PB input byte 2 +#define R32_PB_OUT (*((volatile uint32_t *)0x404000A8)) // RW, GPIO PB output +#define R8_PB_OUT_0 (*((volatile uint8_t *)0x404000A8)) // RW, GPIO PB output byte 0 +#define R8_PB_OUT_1 (*((volatile uint8_t *)0x404000A9)) // RW, GPIO PB output byte 1 +#define R8_PB_OUT_2 (*((volatile uint8_t *)0x404000AA)) // RW, GPIO PB output byte 2 +#define R32_PB_CLR (*((volatile uint32_t *)0x404000AC)) // WZ, GPIO PB clear output: 0=keep, 1=clear +#define R8_PB_CLR_0 (*((volatile uint8_t *)0x404000AC)) // WZ, GPIO PB clear output byte 0 +#define R8_PB_CLR_1 (*((volatile uint8_t *)0x404000AD)) // WZ, GPIO PB clear output byte 1 +#define R8_PB_CLR_2 (*((volatile uint8_t *)0x404000AE)) // WZ, GPIO PB clear output byte 2 +#define R32_PB_PU (*((volatile uint32_t *)0x404000B0)) // RW, GPIO PB pullup resistance enable +#define R8_PB_PU_0 (*((volatile uint8_t *)0x404000B0)) // RW, GPIO PB pullup resistance enable byte 0 +#define R8_PB_PU_1 (*((volatile uint8_t *)0x404000B1)) // RW, GPIO PB pullup resistance enable byte 1 +#define R8_PB_PU_2 (*((volatile uint8_t *)0x404000B2)) // RW, GPIO PB pullup resistance enable byte 2 +#define R32_PB_PD (*((volatile uint32_t *)0x404000B4)) // RW, GPIO PB output open-drain & input pulldown resistance enable +#define R8_PB_PD_0 (*((volatile uint8_t *)0x404000B4)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 0 +#define R8_PB_PD_1 (*((volatile uint8_t *)0x404000B5)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 1 +#define R8_PB_PD_2 (*((volatile uint8_t *)0x404000B6)) // RW, GPIO PB output open-drain & input pulldown resistance enable byte 2 + +/* GPIO PD register */ +#define R32_PD_DIR (*((volatile uint32_t *)0x404000C0)) // RW, GPIO PD I/O direction: 0=in, 1=out +#define R8_PD_DIR_0 (*((volatile uint8_t *)0x404000C0)) // RW, GPIO PD I/O direction byte 0 +#define R8_PD_DIR_1 (*((volatile uint8_t *)0x404000C1)) // RW, GPIO PD I/O direction byte 1 +#define R8_PD_DIR_2 (*((volatile uint8_t *)0x404000C2)) // RW, GPIO PD I/O direction byte 2 +#define R8_PD_DIR_3 (*((volatile uint8_t *)0x404000C3)) // RW, GPIO PD I/O direction byte 3 +#define R32_PD_PIN (*((volatile uint32_t *)0x404000C4)) // RO, GPIO PD input +#define R8_PD_PIN_0 (*((volatile uint8_t *)0x404000C4)) // RO, GPIO PD input byte 0 +#define R8_PD_PIN_1 (*((volatile uint8_t *)0x404000C5)) // RO, GPIO PD input byte 1 +#define R8_PD_PIN_2 (*((volatile uint8_t *)0x404000C6)) // RO, GPIO PD input byte 2 +#define R8_PD_PIN_3 (*((volatile uint8_t *)0x404000C7)) // RO, GPIO PD input byte 3 +#define R32_PD_OUT (*((volatile uint32_t *)0x404000C8)) // RW, GPIO PD output +#define R8_PD_OUT_0 (*((volatile uint8_t *)0x404000C8)) // RW, GPIO PD output byte 0 +#define R8_PD_OUT_1 (*((volatile uint8_t *)0x404000C9)) // RW, GPIO PD output byte 1 +#define R8_PD_OUT_2 (*((volatile uint8_t *)0x404000CA)) // RW, GPIO PD output byte 2 +#define R8_PD_OUT_3 (*((volatile uint8_t *)0x404000CB)) // RW, GPIO PD output byte 3 +#define R32_PD_PU (*((volatile uint32_t *)0x404000D0)) // RW, GPIO PD pullup resistance enable +#define R8_PD_PU_0 (*((volatile uint8_t *)0x404000D0)) // RW, GPIO PD pullup resistance enable 0 +#define R8_PD_PU_1 (*((volatile uint8_t *)0x404000D1)) // RW, GPIO PD pullup resistance enable 1 +#define R8_PD_PU_2 (*((volatile uint8_t *)0x404000D2)) // RW, GPIO PD pullup resistance enable 2 +#define R8_PD_PU_3 (*((volatile uint8_t *)0x404000D3)) // RW, GPIO PD pullup resistance enable 3 +#define R32_PD_PD (*((volatile uint32_t *)0x404000D4)) // RW, GPIO PD pulldown resistance enable +#define R8_PD_PD_0 (*((volatile uint8_t *)0x404000D4)) // RW, GPIO PD pulldown resistance enable 0 +#define R8_PD_PD_1 (*((volatile uint8_t *)0x404000D5)) // RW, GPIO PD pulldown resistance enable 1 +#define R8_PD_PD_2 (*((volatile uint8_t *)0x404000D6)) // RW, GPIO PD pulldown resistance enable 2 +#define R8_PD_PD_3 (*((volatile uint8_t *)0x404000D7)) // RW, GPIO PD pulldown resistance enable 3 + +/* GPIO register address offset and bit define */ +#define BA_PA ((volatile uint8_t *)0x40400080) // point GPIO PA base address +#define BA_PB ((volatile uint8_t *)0x404000A0) // point GPIO PB base address +#define BA_PD ((volatile uint8_t *)0x404000C0) // point GPIO PD base address +#define GPIO_DIR 0x00 +#define GPIO_DIR_0 0x00 +#define GPIO_DIR_1 0x01 +#define GPIO_DIR_2 0x02 +#define GPIO_DIR_3 0x03 +#define GPIO_PIN 0x04 +#define GPIO_PIN_0 0x04 +#define GPIO_PIN_1 0x05 +#define GPIO_PIN_2 0x06 +#define GPIO_PIN_3 0x07 +#define GPIO_OUT 0x08 +#define GPIO_OUT_0 0x08 +#define GPIO_OUT_1 0x09 +#define GPIO_OUT_2 0x0A +#define GPIO_OUT_3 0x0B +#define GPIO_CLR 0x0C +#define GPIO_CLR_0 0x0C +#define GPIO_CLR_1 0x0D +#define GPIO_CLR_2 0x0E +#define GPIO_CLR_3 0x0F +#define GPIO_PU 0x10 +#define GPIO_PU_0 0x10 +#define GPIO_PU_1 0x11 +#define GPIO_PU_2 0x12 +#define GPIO_PU_3 0x13 +#define GPIO_PD 0x14 +#define GPIO_PD_0 0x14 +#define GPIO_PD_1 0x15 +#define GPIO_PD_2 0x16 +#define GPIO_PD_3 0x17 +#define RB_PD_15_8 0x01 // RW, GPIO PD[15:8] pullup resistance enable together +#define RB_PD_23_16 0x01 // RW, GPIO PD[23:16] pullup resistance enable together +#define RB_PD_31_24 0x01 // RW, GPIO PD[31:24] pullup resistance enable together + +/*AF remap and debug I/O configuration register (AFIO_PCFR1)*/ +#define R32_AFIO_PCFR1 (*((volatile uint32_t *)0x40400140)) //AF remap and debug I/O configuration register (AFIO_PCFR1) +#define MASK_LINK_LED_RM 0xc0000000 //LINK LED remapping +#define MASK_SLV_RW_RM 0x30000000 //SLV remapping +#define MASK_SLV_DATA_RM 0x0c000000 //SLV data remapping +#define MASK_SLV_ADDR1_RM 0x03000000 //SLV address1 remapping +#define MASK_SLV_ADDR_RM 0x00c00000 //SLV command data selection input pin remapping +#define MASK_SLV_CS_RM 0x00300000 //SLV piece selection pin remapping +#define MASK_SLV_INTERRUPT_RM 0x000c0000 //SLV interrupt pin remapping +#define MASK_I2C_RM 0x00030000 //I2C remapping +#define MASK_UART2_MODEM_RM 0x0000c000 //UART2 MODEM remapping +#define MASK_UART1_MODEM_RM 0x00003000 //UART1 MODEM remapping +#define MASK_UART0_MODEM_RM 0x00000c00 //UART0 MODEM remapping +#define MASK_UART3_RM 0x00000300 //UART3 remapping +#define MASK_UART2_RM 0x000000c0 //UART2 remapping +#define MASK_UART1_RM 0x00000030 //UART1 remapping +#define MASK_UART0_RM 0x0000000c //UART0 remapping +#define MASK_SPI0_RM 0x00000003 //SPI0 remapping +/*AF remap and debug I/O configuration register (AFIO_PCFR2)*/ +#define R32_AFIO_PCFR2 (*((volatile uint32_t *)0x40400160)) //AF remap and debug I/O configuration register (AFIO_PCFR2) +#define UART3_MODEM 0x000c0000 //UART3 MODEM remapping +#define TNOW3_RM 0x00030000 //TNOW3 remapping +#define TNOW2_RM 0x0000c000 //TNOW2 remapping +#define TNOW1_RM 0x00003000 //TNOW1 remapping +#define TNOW0_RM 0x00000c00 //TNOW0 remapping +#define SPI1_RM 0x00000300 //UART3 remapping +#define BUSY_RM 0x00000040 //BUSY remapping +#define TIMER1_RM 0x00000020 //TIMER1 remapping +#define TIMER0_RM 0x00000010 //TIMER0 remapping +#define RST_RM 0x0000000c //reset pin remapping +#define ACT_LED_RM 0x00000003 //active led remapping + +/*Configure the extended control register 0*/ +#define R32_EXTEN_CTLR0 (*((volatile uint32_t *)0x40400144)) //Configure the extended control register 0 +#define RB_CORE_PROT_STATUS 0x40000000 //Core protected moed status bit +#define RB_CORE_HALT_INT_EN 0x02000000 //Kernel error interrupt enabled +#define RB_RST_DLEAY_EN 0x01000000 //reset time extension control bit +#define RB_XI_STATUS 0x00800000 //XI STATUS +#define RB_USBPLLON 0x00400000 //USBPLL clock enable bit +#define RB_FLASH_PRE_EN 0x00200000 //flash clock pre-divisor enable +#define RB_ETHRST 0x00080000 //ethernet reset control +#define RB_DIG_ETH_PHY_RST 0x00020000 //ethernet phy digital module reset control +#define RB_ANA_ETH_PHY_RST 0x00010000 //ethernet phy analog module reset control +#define RB_USBPLLCLK 0x0000c000 //USBPLL input clock frequency selection +#define RB_RST_CMD_EN 0x00002000 //global reset enabled +#define RB_BUSY_EN 0x00001000 //the busy signal output of spi and slv enabled +#define RB_TNOW3_EN 0x00000800 //the TNOW signal output of the UART3 is enabled +#define RB_TNOW2_EN 0x00000400 //the TNOW signal output of the UART2 is enabled +#define RB_TNOW1_EN 0x00000200 //the TNOW signal output of the UART1 is enabled +#define RB_TNOW0_EN 0x00000100 //the TNOW signal output of the UART0 is enabled +#define RB_SW 0x00000080 //select the systemitem clock source +#define RB_USBPLLSRC 0x00000060 //USBPLL reference clock source +#define RB_SW_CFG 0x00000001 //Serial wire JTAG configuration +/*Configure the extended control register 1*/ +#define R32_EXTEN_CTLR1 (*((volatile uint32_t *)0x40400154)) //Configure the extended control register 1 +#define RB_VIO_PWN_INT_EN 0x00800000 //Enables an outage when the VIO power is down +#define RB_VIO_PWN_RST_EN 0x00400000 //Enable system reset when the VIO power is down +#define RB_VIO_PWN_IO_EN 0x00200000 //Enable the IO port of the peripheral to input a high levelwhen the VIO power is down +#define RB_LDO_SLP_EN 0x00100000 //Enable the LDO to go into sleep mode when the VIO power isdown +#define RB_CLKSEL 0x00080000 //Clock signal selection +#define RB_HSE_STATUS 0x00008000 //External crystal current level status +#define RB_VIO_RDY 0x00000080 //VIO status +#define RB_HSION 0x00000040 //Internal High Speed clock enable +#define RB_HSEON 0x00000020 //External High Speed clock enable +/*Configure the extended control register 2*/ +#define R32_EXTEN_CTLR2 (*((volatile uint32_t *)0x4040016c)) //Configure the extended control register 2 +#define RB_XIXO_GPIO_EN 0x02000000 //XI/XO pin open-drain_ouput control bit +#define RB_XO_OE 0x01000000 //XO ouput enable bit +#define RB_XI_OE 0x00800000 //XI ouput enable bit +#define RB_USBPD_IN_HVT1 0x00000002 //PD PIN PB19 high threshold input mode +#define RB_USBPD_IN_HVT0 0x00000001 //PD PIN PB18 high threshold input mode + +/*flash data manipulation register */ +#define R8_SPI_FLASH_DATA (*((volatile uint8_t *)0x40400018)) //flash data manipulation register +/*Flash control register*/ +#define R8_SPI_FLASH_CTRL (*((volatile uint8_t *)0x4040001a)) //Flash control register +#define RB_FLASH_RD_EN 0x04 //The software reads the FLASH function enable bit +#define RB_FLASH_OE 0x02 //Flash output enable +#define RB_FLASH_CS 0x01 //Flash slice bit selection was enabled +/*CodeFlash key buffer register*/ +#define R16_FLASHA_KEY_BUF (*((volatile uint16_t *)0x40400168)) //CodeFlash key buffer register +#define R16_FLASHB_KEY_BUF (*((volatile uint16_t *)0x4040016A)) //CodeFlash key buffer register + +/* GPIO alias name */ +#define TWP0 (1 << 4) // PA4 +#define TWP1 (1 << 5) // PA5 +#define TACK (1 << 6) // PA6 +#define TDO (1 << 7) // PA7 +#define TRST (1 << 9) // PA9 +#define TDI (1 << 13) // PA13 +#define TCK (1 << 14) // PA14 +#define TMS (1 << 15) // PA15 +#define UID (1 << 8) // PA8 +#define SLVI (1 << 9) // PA9 +#define PIN_PARA_A0 (1 << 10) // PA10 +#define PIN_PARA_PCS (1 << 11) // PA11 +#define TNOW0 (1 << 7) // PA7 +#define DTR0 (1 << 7) // PA7 +#define RTS0 (1 << 8) // PA8 +#define CTS0 (1 << 12) // PA12 +#define DSR0 (1 << 13) // PA13 +#define RI0 (1 << 14) // PA14 +#define DCD0 (1 << 15) // PA15 +#define CTS1 (1 << 16) // PA16 +#define RTS1 (1 << 17) // PA17 +#define TNOW1 (1 << 17) // PA17 +#define ELED (1 << 13) // PA13 +#define ELINK (1 << 18) // PA18 +#define VBUS (1 << 19) // PA19 +#define PRD (1 << 20) // PA20 +#define PIN_PARA_RD (1 << 20) +#define PWR_314 (1 << 21) // PA21 +#define PIN_PARA_WR (1 << 21) +#define CTS0X (1 << 0) // PB0 +#define DSR0X (1 << 1) // PB1 +#define RI0X (1 << 2) // PB2 +#define DCD0X (1 << 3) // PB3 +#define DTR0X (1 << 4) // PB4 +#define RTS0X (1 << 5) // PB5 +#define TRAN0 (1 << 0) // PB0 +#define RECV0 (1 << 1) // PB1 +#define TRAN1 (1 << 2) // PB2 +#define RECV1 (1 << 3) // PB3 +#define PWM0 (1 << 0) // PB0 +#define CAT0 (1 << 1) // PB1 +/* note: PB1/CAT0 will input from PECL if RB_MISC_PECL_EN=1 and TMR0.RB_TMR_OUT_EN=1 */ +#define PWM1 (1 << 2) // PB2 +#define CAT1 (1 << 3) // PB3 +#define PWM2 (1 << 4) // PB4 +#define CAT2 (1 << 5) // PB5 +#define PWM3 (1 << 6) // PB6 +#define CAT3 (1 << 6) // PB6 +#define RXD0 (1 << 8) // PB8 +#define TXD0 (1 << 9) // PB9 +#define RXD1 (1 << 10) // PB10 +/* note: PB10/RXD1 will input from PECL if RB_MISC_PECL_EN=1 and TMR0.RB_TMR_OUT_EN=0 */ +#define RXTX1 (1 << 10) // PB10 +#define TXD1 (1 << 11) // PB11 + +#define SCS (1 << 12) // PB12 +#define SCK0 (1 << 13) // PB13 +#define MOSI (1 << 14) // PB14 +#define MISO (1 << 15) // PB15 +#define SDX0 (1 << 15) // PB15 +#define ADCS (1 << 16) // PB16 +#define SCK1 (1 << 17) // PB17 +#define SDO (1 << 18) // PB18 +#define SDI (1 << 19) // PB19 +#define SDX1 (1 << 19) // PB19 +#define RXD2 (1 << 28) // PD28 +#define TXD2 (1 << 29) // PD29 +#define RXD3 (1 << 22) // PD22 +#define TXD3 (1 << 23) + +/* ADC register */ +#define R32_ADC_CONTROL (*((volatile uint32_t *)0x4040A000)) // RW, ADC control +#define R8_ADC_CTRL_MOD (*((volatile uint8_t *)0x4040A000)) // RW, ADC mode control +#define R8_ADC_CTRL_DMA (*((volatile uint8_t *)0x4040A001)) // RW, ADC DMA control and etc. +#define R8_ADC_INTER_EN (*((volatile uint8_t *)0x4040A002)) // RW, ADC interrupt enable +#define R8_ADC_CLOCK_DIV (*((volatile uint8_t *)0x4040A003)) // RW, ADC clock divisor +#define R32_ADC_STATUS (*((volatile uint32_t *)0x4040A004)) // RW, ADC status +#define R16_ADC_DATA (*((volatile uint16_t *)0x4040A004)) // RO, ADC result data +#define R8_ADC_INT_FLAG (*((volatile uint8_t *)0x4040A006)) // RW1, ADC interrupt flag +#define R8_ADC_FIFO_COUNT (*((volatile uint8_t *)0x4040A007)) // RO, ADC FIFO count status +#define R32_ADC_CTRL (*((volatile uint8_t *)0x4040A008)) // RO, ADC control register +#define R16_ADC_CMP_VALUE (*((volatile uint16_t *)0x4040A00C)) // RW, ADC comparison reference value +#define R16_ADC_FIFO (*((volatile uint16_t *)0x4040A010)) // RO, ADC FIFO register +#define R32_ADC_DMA_NOW (*((volatile uint32_t *)0x4040A014)) // RW, ADC DMA current address +#define R32_ADC_DMA_BEG (*((volatile uint32_t *)0x4040A018)) // RW, ADC DMA begin address +#define R32_ADC_DMA_END (*((volatile uint32_t *)0x4040A01C)) // RW, ADC DMA end address + +/* ADC register address offset and bit define */ +#define ADC_FIFO_SIZE 8 // ADC FIFO size (depth) +#define BA_ADC ((volatile uint8_t *)0x4040A000) // point ADC base address +#define ADC_CTRL_MOD 0 +#define RB_ADC_CYCLE_CLK 0x0F // RW, ADC cycle bit mask (clock number): 0=manual sample, other=set cycle for auto sample +#define RB_ADC_CHAN_MOD 0x30 // RW, ADC channel control mode: 00=0#, 01=1#, 10=2#, 11=auto flip 0#/1# +#define RB_ADC_SAMPLE_WID 0x40 // RW, ADC sample pulse width: 0=1 clock, 1=2 clock +#define RB_ADC_POWER_ON 0x80 // RW, ADC module enable +#define ADC_CTRL_DMA 1 +#define RB_ADC_DMA_ENABLE 0x01 // RW, ADC DMA enable +#define RB_ADC_DMA_BURST 0x02 // RW, ADC DMA burst enable +#define RB_ADC_DMA_LOOP 0x04 // RW, ADC DMA address loop enable +#define RB_ADC_CHAN_OE 0x40 // WO, ADC channel control output enable +#define RB_ADC_MAN_SAMPLE 0x80 // RW, ADC manual sample control, high action +#define ADC_INTER_EN 2 +#define RB_ADC_IE_ADC_CMP 0x01 // RW, enable interrupt for current ADC comparison action +#define RB_ADC_IE_ADC_END 0x02 // RW, enable interrupt for current ADC end +#define RB_ADC_IE_FIFO_HF 0x04 // RW, enable interrupt for ADC FIFO half +#define RB_ADC_IE_DMA_END 0x08 // RW, enable interrupt for ADC DMA completion +#define RB_ADC_IE_FIFO_OV 0x10 // RW, enable interrupt for ADC FIFO overflow +#define RB_ADC_IE_DMA_ERR 0x20 // RW, enable interrupt for ADC DMA respond error +#define RB_ADC_CMP_MOD_EQ 0x40 // RW, ADC equal comparison enable: 0=exclude equal, 1=include equal +#define RB_ADC_CMP_MOD_GT 0x80 // RW, ADC comparison mode: 0=less action, 1=great action +#define ADC_CLOCK_DIV 3 +#define ADC_DATA 4 +#define ADC_INT_FLAG 6 +#define RB_ADC_IF_ADC_CMP 0x01 // RW1, interrupt flag for current ADC comparison action +#define RB_ADC_IF_ADC_END 0x02 // RW1, interrupt flag for current ADC end +#define RB_ADC_IF_FIFO_HF 0x04 // RW1, interrupt flag for ADC FIFO half +#define RB_ADC_IF_DMA_END 0x08 // RW1, interrupt flag for ADC DMA completion +#define RB_ADC_IF_FIFO_OV 0x10 // RW1, interrupt flag for ADC FIFO overflow +#define RB_ADC_IF_DMA_ERR 0x20 // RW1, interrupt flag for ADC DMA respond error +#define RB_ADC_EOC_FLAG 0x40 // RO, current ADC converter end indicator +#define RB_ADC_CHAN_INDEX 0x80 // RO, current ADC channel number for auto flip: 0=0#/2#, 1=1# +#define ADC_FIFO_COUNT 7 +#define ADC_CTRL 8 +#define MASK_ADC_CTL_MOD1 0x0000000f //Corresponding channel +#define MASK_ADC_SMAPLE_TIME 0x01fffff0 //ADC sampling and calibration time +#define MASK_ADC_CYCLE_BIT_4_6 0x0e000000 //Position 4-6 of the automatic sampling period +#define MASK_ADC_BIT_MODE 0x10000000 //ADC resolution selection bit +#define ADC_CMP_VALUE 0x0C +#define ADC_FIFO 0x10 +#define MASK_ADC_DMA_ADDR 0x0003ffff + +/* UART0 register */ +#define R8_UART0_RBR (*((volatile uint8_t *)0x4040D000)) // RO, UART0 receiver buffer, receiving byte +#define R8_UART0_THR (*((volatile uint8_t *)0x4040D000)) // WO, UART0 transmitter holding, transmittal byte +#define R8_UART0_IER (*((volatile uint8_t *)0x4040D001)) // RW, UART0 interrupt enable +#define R8_UART0_IIR (*((volatile uint8_t *)0x4040D002)) // RO, UART0 interrupt identification +#define R8_UART0_FCR (*((volatile uint8_t *)0x4040D002)) // WO, UART0 FIFO control +#define R8_UART0_LCR (*((volatile uint8_t *)0x4040D003)) // RW, UART0 line control +#define R8_UART0_MCR (*((volatile uint8_t *)0x4040D004)) // RW, UART0 modem control +#define R8_UART0_LSR (*((volatile uint8_t *)0x4040D005)) // RO, UART0 line status +#define R8_UART0_MSR (*((volatile uint8_t *)0x4040D006)) // RO, UART0 modem status +#define R8_UART0_DIV (*((volatile uint8_t *)0x4040D007)) // RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART0_DMA_CTRL (*((volatile uint8_t *)0x4040d008)) // RW, DMA Control register +#define R8_UART0_DMA_IF (*((volatile uint8_t *)0x4040d009)) // RW, DMA status register +#define R32_UART0_DMA_WR_NOW_ADDR (*((volatile uint32_t *)0x4040d00c)) //DMA receive mode current address register +#define R32_UART0_DMA_WR_START_ADDR (*((volatile uint32_t *)0x4040d010)) //DMA receive mode start address register +#define R32_UART0_DMA_WR_END_ADDR (*((volatile uint32_t *)0x4040d014)) //DMA received mode end address register +#define R32_UART0_DMA_RD_NOW_ADDR (*((volatile uint32_t *)0x4040d018)) //DMA send mode current address register +#define R32_UART0_DMA_RD_START_ADDR (*((volatile uint32_t *)0x4040d01c)) //DMA send mode start address register +#define R32_UART0_DMA_RD_END_ADDR (*((volatile uint32_t *)0x4040d020)) //DMA send mode end address register +#define R8_UART0_DLL (*((volatile uint8_t *)0x4040D000)) // RW, UART0 divisor latch LSB byte +#define R8_UART0_DLM (*((volatile uint8_t *)0x4040D001)) // RW, UART0 divisor latch MSB byte + +/* UART1 register */ +#define R8_UART1_RBR (*((volatile uint8_t *)0x4040D800)) // RO, UART1 receiver buffer, receiving byte +#define R8_UART1_THR (*((volatile uint8_t *)0x4040D800)) // WO, UART1 transmitter holding, transmittal byte +#define R8_UART1_IER (*((volatile uint8_t *)0x4040D801)) // RW, UART1 interrupt enable +#define R8_UART1_IIR (*((volatile uint8_t *)0x4040D802)) // RO, UART1 interrupt identification +#define R8_UART1_FCR (*((volatile uint8_t *)0x4040D802)) // WO, UART1 FIFO control +#define R8_UART1_LCR (*((volatile uint8_t *)0x4040D803)) // RW, UART1 line control +#define R8_UART1_MCR (*((volatile uint8_t *)0x4040D804)) // RW, UART1 modem control +#define R8_UART1_LSR (*((volatile uint8_t *)0x4040D805)) // RO, UART1 line status +#define R8_UART1_MSR (*((volatile uint8_t *)0x4040D806)) // RO, UART1 modem status +#define R8_UART1_DIV (*((volatile uint8_t *)0x4040D807)) // RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART1_DMA_CTRL (*((volatile uint8_t *)0x4040d808)) // RW, DMA Control register +#define R8_UART1_DMA_IF (*((volatile uint8_t *)0x4040d809)) // RW, DMA status register +#define R32_UART1_DMA_WR_NOW_ADDR (*((volatile uint32_t *)0x4040d80c)) //DMA receive mode current address register +#define R32_UART1_DMA_WR_START_ADDR (*((volatile uint32_t *)0x4040d810)) //DMA receive mode start address register +#define R32_UART1_DMA_WR_END_ADDR (*((volatile uint32_t *)0x4040d814)) //DMA received mode end address register +#define R32_UART1_DMA_RD_NOW_ADDR (*((volatile uint32_t *)0x4040d818)) //DMA send mode current address register +#define R32_UART1_DMA_RD_START_ADDR (*((volatile uint32_t *)0x4040d81c)) //DMA send mode start address register +#define R32_UART1_DMA_RD_END_ADDR (*((volatile uint32_t *)0x4040d820)) //DMA send mode end address register +#define R8_UART1_DLL (*((volatile uint8_t *)0x4040D800)) // RW, UART1 divisor latch LSB byte +#define R8_UART1_DLM (*((volatile uint8_t *)0x4040D801)) // RW, UART1 divisor latch MSB byte + +/* UART2 register */ +#define R8_UART2_RBR (*((volatile uint8_t *)0x40409000)) // RO, UART2 receiver buffer, receiving byte +#define R8_UART2_THR (*((volatile uint8_t *)0x40409000)) // WO, UART2 transmitter holding, transmittal byte +#define R8_UART2_IER (*((volatile uint8_t *)0x40409001)) // RW, UART2 interrupt enable +#define R8_UART2_IIR (*((volatile uint8_t *)0x40409002)) // RO, UART2 interrupt identification +#define R8_UART2_FCR (*((volatile uint8_t *)0x40409002)) // WO, UART2 FIFO control +#define R8_UART2_LCR (*((volatile uint8_t *)0x40409003)) // RW, UART2 line control +#define R8_UART2_MCR (*((volatile uint8_t *)0x40409004)) // RW, UART2 modem control +#define R8_UART2_LSR (*((volatile uint8_t *)0x40409005)) // RO, UART2 line status +#define R8_UART2_MSR (*((volatile uint8_t *)0x40409006)) // RO, UART2 modem status +#define R8_UART2_DIV (*((volatile uint8_t *)0x40409007)) // RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART2_DMA_CTRL (*((volatile uint8_t *)0x40409008)) // RW, DMA Control register +#define R8_UART2_DMA_IF (*((volatile uint8_t *)0x40409009)) // RW, DMA status register +#define R32_UART2_DMA_WR_NOW_ADDR (*((volatile uint32_t *)0x4040900c)) //DMA receive mode current address register +#define R32_UART2_DMA_WR_START_ADDR (*((volatile uint32_t *)0x40409010)) //DMA receive mode start address register +#define R32_UART2_DMA_WR_END_ADDR (*((volatile uint32_t *)0x40409014)) //DMA received mode end address register +#define R32_UART2_DMA_RD_NOW_ADDR (*((volatile uint32_t *)0x40409018)) //DMA send mode current address register +#define R32_UART2_DMA_RD_START_ADDR (*((volatile uint32_t *)0x4040901c)) //DMA send mode start address register +#define R32_UART2_DMA_RD_END_ADDR (*((volatile uint32_t *)0x40409020)) //DMA send mode end address register +#define R8_UART2_DLL (*((volatile uint8_t *)0x40409000)) // RW, UART2 divisor latch LSB byte +#define R8_UART2_DLM (*((volatile uint8_t *)0x40409001)) // RW, UART2 divisor latch MSB byte + + +/* UART3 register */ +#define R8_UART3_RBR (*((volatile uint8_t *)0x40409800)) // RO, UART3 receiver buffer, receiving byte +#define R8_UART3_THR (*((volatile uint8_t *)0x40409800)) // WO, UART3 transmitter holding, transmittal byte +#define R8_UART3_IER (*((volatile uint8_t *)0x40409801)) // RW, UART3 interrupt enable +#define R8_UART3_IIR (*((volatile uint8_t *)0x40409802)) // RO, UART3 interrupt identification +#define R8_UART3_FCR (*((volatile uint8_t *)0x40409802)) // WO, UART3 FIFO control +#define R8_UART3_LCR (*((volatile uint8_t *)0x40409803)) // RW, UART3 line control +#define R8_UART3_MCR (*((volatile uint8_t *)0x40409804)) // RW, UART3 modem control +#define R8_UART3_LSR (*((volatile uint8_t *)0x40409805)) // RO, UART3 line status +#define R8_UART3_MSR (*((volatile uint8_t *)0x40409806)) // RO, UART3 modem status +#define R8_UART3_DIV (*((volatile uint8_t *)0x40409807)) // RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 +#define R8_UART3_DMA_CTRL (*((volatile uint8_t *)0x40409808)) // RW, DMA Control register +#define R8_UART3_DMA_IF (*((volatile uint8_t *)0x40409809)) // RW, DMA status register +#define R32_UART3_DMA_WR_NOW_ADDR (*((volatile uint32_t *)0x4040980c)) //DMA receive mode current address register +#define R32_UART3_DMA_WR_START_ADDR (*((volatile uint32_t *)0x40409810)) //DMA receive mode start address register +#define R32_UART3_DMA_WR_END_ADDR (*((volatile uint32_t *)0x40409814)) //DMA received mode end address register +#define R32_UART3_DMA_RD_NOW_ADDR (*((volatile uint32_t *)0x40409818)) //DMA send mode current address register +#define R32_UART3_DMA_RD_START_ADDR (*((volatile uint32_t *)0x4040981c)) //DMA send mode start address register +#define R32_UART3_DMA_RD_END_ADDR (*((volatile uint32_t *)0x40409820)) //DMA send mode end address register +#define R8_UART3_DLL (*((volatile uint8_t *)0x40409800)) // RW, UART3 divisor latch LSB byte +#define R8_UART3_DLM (*((volatile uint8_t *)0x40409801)) // RW, UART3 divisor latch MSB byte + + +/* UART register address offset and bit define */ +#define UART_FIFO_SIZE 16 // UART0 FIFO size (depth) +#define UART_RECV_RDY_SZ 14 // the max FIFO trigger level for UART0 receiver data available +#define BA_UART0 ((volatile uint8_t *)0x4040D000) // point UART0 base address +#define BA_UART1 ((volatile uint8_t *)0x4040D800) // point UART1 base address +#define BA_UART2 ((volatile uint8_t *)0x40409000) // point UART2 base address +#define BA_UART3 ((volatile uint8_t *)0x40409800) // point UART3 base address +#define UART_RBR 0 +#define UART_THR 0 +#define UART_IER 1 +#define RB_IER_RECV_RDY 0x01 // RW, UART interrupt enable for receiver data ready +#define RB_IER_THR_EMPTY 0x02 // RW, UART interrupt enable for THR empty +#define RB_IER_LINE_STAT 0x04 // RW, UART interrupt enable for receiver line status +#define RB_IER_MODEM_CHG 0x08 // RW, UART interrupt enable for modem status change +#define RB_IER_MODEM_IO 0x10 // RW, UART0 modem pin selection: 0=from/to GPIO PA, 1=from/to GPIO PB +#define RB_IER_IRDA_MOD 0x10 // RW, UART1 IrDA mode enable +#define RB_IER_MOUT_EN 0x20 // RW, UART modem output pin enable +#define RB_IER_TXD_EN 0x40 // RW, UART TXD pin enable +#define RB_IER_RESET 0x80 // WZ, UART software reset control, high action, auto clear +#define UART_IIR 2 +#define RB_IIR_NO_INT 0x01 // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt +#define RB_IIR_INT_MASK 0x0F // RO, UART interrupt flag bit mask +#define RB_IIR_FIFO_ID 0xC0 // RO, UART FIFO enabled flag +#define UART_FCR 2 +#define RB_FCR_FIFO_EN 0x01 // WO, UART FIFO enable +#define RB_FCR_RX_FIFO_CLR 0x02 // WZ, clear UART receiver FIFO, high action, auto clear +#define RB_FCR_TX_FIFO_CLR 0x04 // WZ, clear UART transmitter FIFO, high action, auto clear +#define RB_FCR_FIFO_TRIG 0xC0 // WO, UART0/1 receiver FIFO trigger level: 00-1byte, 01-4/8bytes, 10-8/16bytes, 11-14/28bytes +#define UART_LCR 3 +#define RB_LCR_WORD_SZ 0x03 // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit +#define RB_LCR_STOP_BIT 0x04 // RW, UART stop bit length: 0-1bit, 1-2bit +#define RB_LCR_PAR_EN 0x08 // RW, UART parity enable +#define RB_LCR_PAR_MOD 0x30 // RW, UART pariry mode: 00-odd, 01-even, 10-mark, 11-space +#define RB_LCR_BREAK_EN 0x40 // RW, UART break control enable +#define RB_LCR_DLAB 0x80 // RW, UART divisor latch access bit +#define UART_MCR 4 +#define RB_MCR_DTR 0x01 // RW, UART control DTR +#define RB_MCR_RTS 0x02 // RW, UART control RTS +#define RB_MCR_OUT1 0x04 // RW, UART control OUT1 +#define RB_MCR_OUT2 0x08 // RW, UART control OUT2 +#define RB_MCR_LOOP 0x10 // RW, UART0 enable local loop back +#define RB_MCR_RXTX 0x10 // RW, UART1 enable RXTX for half-duplex (TXD auto three-state output on RXD pin) +#define RB_MCR_AU_FLOW_EN 0x20 // RW, UART enable autoflow control +#define RB_MCR_TNOW 0x40 // RW, UART enable TNOW output on DTR or RTS pin +#define RB_MCR_HALF 0x80 // RW, UART enable half-duplex +#define UART_LSR 5 +#define RB_LSR_DATA_RDY 0x01 // RO, UART receiver fifo data ready status +#define RB_LSR_OVER_ERR 0x02 // RZ, UART receiver overrun error +#define RB_LSR_PAR_ERR 0x04 // RZ, UART receiver parity error +#define RB_LSR_FRAME_ERR 0x08 // RZ, UART receiver frame error +#define RB_LSR_BREAK_ERR 0x10 // RZ, UART receiver break error +#define RB_LSR_TX_FIFO_EMP 0x20 // RO, UART transmitter fifo empty status +#define RB_LSR_TX_ALL_EMP 0x40 // RO, UART transmitter all empty status +#define RB_LSR_ERR_RX_FIFO 0x80 // RO, error in UART receiver fifo +#define UART_MSR 6 +#define RB_MSR_CTS_CHG 0x01 // RZ, UART CTS changed status, high action +#define RB_MSR_DSR_CHG 0x02 // RZ, UART DSR changed status, high action +#define RB_MSR_RI_CHG 0x04 // RZ, UART RI changed status, high action +#define RB_MSR_DCD_CHG 0x08 // RZ, UART DCD changed status, high action +#define RB_MSR_CTS 0x10 // RO, UART CTS action status +#define RB_MSR_DSR 0x20 // RO, UART DSR action status +#define RB_MSR_RI 0x40 // RO, UART RI action status +#define RB_MSR_DCD 0x80 // RO, UART DCD action status +#define UART_ADR 7 +#define UART_DIV 7 +#define UART0_DMA_CTRL 8 +#define RB_DMA_WR_EN 0x01 //DMA enabled when receiving data +#define RB_DMA_WR_LOOP_EN 0x02 //DMA loop mode enabled when receiving data +#define RB_DMA_WR_END_EN 0x04 //the end of DMA interrupt when receiving data is enabled +#define RB_DMA_RD_EN 0x10 //DMA enabled when sending data +#define RB_DMA_RD_LOOP_EN 0x20 //DMA loop mode enabled when sending data +#define RB_DMA_RD_END_EN 0x40 //the end of DMA interrupt when sending data is enabled +#define UART0_DMA_IF 9 +#define RB_DMA_IF_PAR_ERR 0x02 //DMA parity error flag +#define RB_DMA_IF_TX_END 0x04 //DMA end flag when data is sended +#define RB_DMA_IF_FRAME_ERR 0x02 //DMA frame error flag +#define RB_DMA_IF_RX_END 0x01 //DMA end flag when data is received +#define UART_DLL 0 +#define UART_DLM 1 +#define MASK_UART_DMA_ADDR 0x0003ffff + +/* UART interrupt identification values for IIR bits 3:0 */ +#define UART_II_SLV_ADDR 0x0E // RO, UART1 slave address match +#define UART_II_LINE_STAT 0x06 // RO, UART interrupt by receiver line status +#define UART_II_RECV_RDY 0x04 // RO, UART interrupt by receiver data available +#define UART_II_RECV_TOUT 0x0C // RO, UART interrupt by receiver fifo timeout +#define UART_II_THR_EMPTY 0x02 // RO, UART interrupt by THR empty +#define UART_II_MODEM_CHG 0x00 // RO, UART interrupt by modem status change +#define UART_II_NO_INTER 0x01 // RO, no UART interrupt is pending + +/* SPI0 register */ +#define R32_SPI0_CONTROL (*((volatile uint32_t *)0x4040C000)) // RW, SPI0 control +#define R8_SPI0_CTRL_MOD (*((volatile uint8_t *)0x4040C000)) // RW, SPI0 mode control +#define R8_SPI0_CTRL_DMA (*((volatile uint8_t *)0x4040C001)) // RW, SPI0 DMA control +#define R8_SPI0_INTER_EN (*((volatile uint8_t *)0x4040C002)) // RW, SPI0 interrupt enable +#define R8_SPI0_CLOCK_DIV (*((volatile uint8_t *)0x4040C003)) // RW, SPI0 master clock divisor +#define R8_SPI0_SLAVE_PRE (*((volatile uint8_t *)0x4040C003)) // RW, SPI0 slave preset value +#define R32_SPI0_STATUS (*((volatile uint32_t *)0x4040C004)) // RW, SPI0 status +#define R8_SPI0_BUFFER (*((volatile uint8_t *)0x4040C004)) // RW, SPI0 data buffer +#define R8_SPI0_RUN_FLAG (*((volatile uint8_t *)0x4040C005)) // RO, SPI0 work flag +#define R8_SPI0_INT_FLAG (*((volatile uint8_t *)0x4040C006)) // RW1, SPI0 interrupt flag +#define R8_SPI0_FIFO_COUNT (*((volatile uint8_t *)0x4040C007)) // RO, SPI0 FIFO count status +#define R8_SPI0_RESET_CMD (*((volatile uint8_t *)0x4040c008)) //SPI0 reset command word register +#define R16_SPI0_TOTAL_CNT (*((volatile uint16_t *)0x4040C00C)) // RW, SPI0 total byte count, only low 12 bit +#define R32_SPI0_FIFO (*((volatile uint32_t *)0x4040C010)) // RW, SPI0 FIFO register +#define R8_SPI0_FIFO (*((volatile uint8_t *)0x4040C010)) // RO/WO, SPI0 FIFO register +#define R8_SPI0_FIFO_COUNT1 (*((volatile uint8_t *)0x4040C013)) // RO, SPI0 FIFO count status +#define R32_SPI0_DMA_NOW (*((volatile uint32_t *)0x4040C014)) // RW, SPI0 DMA current address +#define R32_SPI0_DMA_BEG (*((volatile uint32_t *)0x4040C018)) // RW, SPI0 DMA begin address +#define R32_SPI0_DMA_END (*((volatile uint32_t *)0x4040C01C)) // RW, SPI0 DMA end address + +/* SPI1 register */ +#define R32_SPI1_CONTROL (*((volatile uint32_t *)0x4040C800)) // RW, SPI1 control +#define R8_SPI1_CTRL_MOD (*((volatile uint8_t *)0x4040C800)) // RW, SPI1 mode control +#define R8_SPI1_CTRL_DMA (*((volatile uint8_t *)0x4040C801)) // RW, SPI1 DMA control +#define R8_SPI1_INTER_EN (*((volatile uint8_t *)0x4040C802)) // RW, SPI1 interrupt enable +#define R8_SPI1_CLOCK_DIV (*((volatile uint8_t *)0x4040C803)) // RW, SPI1 master clock divisor +#define R32_SPI1_STATUS (*((volatile uint32_t *)0x4040C804)) // RW, SPI1 status +#define R8_SPI1_BUFFER (*((volatile uint8_t *)0x4040C804)) // RW, SPI1 data buffer +#define R8_SPI1_RUN_FLAG (*((volatile uint8_t *)0x4040C805)) // RO, SPI1 work flag +#define R8_SPI1_INT_FLAG (*((volatile uint8_t *)0x4040C806)) // RW1, SPI1 interrupt flag +#define R8_SPI1_FIFO_COUNT (*((volatile uint8_t *)0x4040C807)) // RO, SPI1 FIFO count status +#define R16_SPI1_TOTAL_CNT (*((volatile uint16_t *)0x4040C80C)) // RW, SPI1 total byte count, only low 12 bit +#define R32_SPI1_FIFO (*((volatile uint32_t *)0x4040C810)) // RW, SPI1 FIFO register +#define R8_SPI1_FIFO (*((volatile uint8_t *)0x4040C810)) // RO/WO, SPI1 FIFO register +#define R8_SPI1_FIFO_COUNT1 (*((volatile uint8_t *)0x4040C813)) // RO, SPI1 FIFO count status + +/* SPI register address offset and bit define */ +#define SPI0_FIFO_SIZE 32 // SPI0 FIFO size (depth) +#define SPI1_FIFO_SIZE 16 // SPI1 FIFO size (depth) +#define BA_SPI0 ((volatile uint8_t *)0x4040C000) // point SPI0 base address +#define BA_SPI1 ((volatile uint8_t *)0x4040C800) // point SPI1 base address +#define SPI_CTRL_MOD 0 +#define RB_SPI_MODE_SLAVE 0x01 // RW, SPI slave mode: 0=master/host, 1=slave/device +#define RB_SPI_ALL_CLEAR 0x02 // RW, force clear SPI FIFO and count +#define RB_SPI_2WIRE_MOD 0x04 // RW, SPI enable 2 wire mode: 0=3wire(SCK,MOSI,MISO), 1=2wire(SCK,MISO=SDX) +#define RB_SPI_MST_SCK_MOD 0x08 // RW, SPI master clock mode: 0=mode 0, 1=mode 3 +#define RB_SPI_SLV_CMD_MOD 0x08 // RW, SPI slave command mode: 0=byte stream, 1=first byte command +#define RB_SPI_FIFO_DIR 0x10 // RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) +#define RB_SPI_SCK_OE 0x20 // RW, SPI SCK output enable +#define RB_SPI_MOSI_OE 0x40 // RW, SPI MOSI output enable +#define RB_SPI1_SDO_OE 0x40 // RW, SPI1 SDO output enable +#define RB_SPI_MISO_OE 0x80 // RW, SPI MISO output enable +#define RB_SPI1_SDI_OE 0x80 // RW, SPI1 SDI output enable, SPI1 enable 2 wire mode: 0=3wire(SCK1,SDO,SDI), 1=2wire(SCK1,SDX1) +#define SPI_CTRL_DMA 1 +#define RB_SPI_DMA_ENABLE 0x01 // RW, SPI DMA enable +#define RB_SPI_DMA_BURST 0x02 // RW, SPI DMA burst enable +#define RB_SPI_DMA_LOOP 0x04 // RW, SPI DMA address loop enable +#define RB_SPI_HS_HOST 0x80 // RW, High speed host receive mode control bit +#define SPI_INTER_EN 2 +#define RB_SPI_IE_CNT_END 0x01 // RW, enable interrupt for SPI total byte count end +#define RB_SPI_IE_BYTE_END 0x02 // RW, enable interrupt for SPI byte exchanged +#define RB_SPI_IE_FIFO_HF 0x04 // RW, enable interrupt for SPI FIFO half +#define RB_SPI_IE_DMA_END 0x08 // RW, enable interrupt for SPI DMA completion +#define RB_SPI_IE_FIFO_OV 0x10 // RW, enable interrupt for SPI FIFO overflow +#define RB_SPI_IE_DMA_ERR 0x20 // RW, enable interrupt for SPI DMA respond error +#define RB_SPI_IE_FST_BYTE 0x80 // RW, enable interrupt for SPI slave mode first byte received +#define SPI_CLOCK_DIV 3 +#define SPI_SLAVE_PRESET 3 +#define SPI_BUFFER 4 +#define SPI_RUN_FLAG 5 +#define RB_SPI_SLV_CMD_ACT 0x10 // RO, SPI slave command flag +#define RB_SPI_FIFO_READY 0x20 // RO, SPI FIFO ready status +#define RB_SPI_SLV_CS_LOAD 0x40 // RO, SPI slave chip-select loading status +#define RB_SPI_SLV_SELECT 0x80 // RO, SPI slave selection status +#define SPI_INT_FLAG 6 +#define RB_SPI_IF_CNT_END 0x01 // RW1, interrupt flag for SPI total byte count end +#define RB_SPI_IF_BYTE_END 0x02 // RW1, interrupt flag for SPI byte exchanged +#define RB_SPI_IF_FIFO_HF 0x04 // RW1, interrupt flag for SPI FIFO half +#define RB_SPI_IF_DMA_END 0x08 // RW1, interrupt flag for SPI DMA completion +#define RB_SPI_IF_FIFO_OV 0x10 // RW1, interrupt flag for SPI FIFO overflow +#define RB_SPI_IF_DMA_ERR 0x20 // RW1, interrupt flag for SPI DMA respond error +#define RB_SPI_FREE 0x40 // RO, current SPI free status +#define RB_SPI_IF_FST_BYTE 0x80 // RW1, interrupt flag for SPI slave mode first byte received +#define SPI_FIFO_COUNT 7 +#define SPI_TOTAL_CNT 0x0C +#define SPI_FIFO 0x10 +#define SPI0_DMA_NOW 20 +#define MASK_SPI0_DMA_ADDR 0x0003ffff //SPI DMA current address + +/* Timer0 register */ +#define R32_TMR0_CONTROL (*((volatile uint32_t *)0x40408000)) // RW, TMR0 control +#define R8_TMR0_CTRL_MOD (*((volatile uint8_t *)0x40408000)) // RW, TMR0 mode control +#define R8_TMR0_CTRL_DMA (*((volatile uint8_t *)0x40408001)) // RW, TMR0 DMA control +#define R8_TMR0_INTER_EN (*((volatile uint8_t *)0x40408002)) // RW, TMR0 interrupt enable +#define R32_TMR0_STATUS (*((volatile uint32_t *)0x40408004)) // RW, TMR0 status +#define R8_TMR0_INT_FLAG (*((volatile uint8_t *)0x40408006)) // RW1, TMR0 interrupt flag +#define R8_TMR0_FIFO_COUNT (*((volatile uint8_t *)0x40408007)) // RO, TMR0 FIFO count status +#define R32_TMR0_COUNT (*((volatile uint32_t *)0x40408008)) // RO, TMR0 current count +#define R16_TMR0_COUNT (*((volatile uint16_t *)0x40408008)) // RO, TMR0 current count +#define R8_TMR0_COUNT (*((volatile uint8_t *)0x40408008)) // RO, TMR0 current count +#define R32_TMR0_CNT_END (*((volatile uint32_t *)0x4040800C)) // RW, TMR0 end count value, only low 28 bit +#define R32_TMR0_FIFO (*((volatile uint32_t *)0x40408010)) // RO/WO, TMR0 FIFO register, only low 28 bit +#define R16_TMR0_FIFO (*((volatile uint16_t *)0x40408010)) // RO/WO, TMR0 FIFO register +#define R8_TMR0_FIFO (*((volatile uint8_t *)0x40408010)) // RO/WO, TMR0 FIFO register +#define R32_TMR0_DMA_NOW (*((volatile uint32_t *)0x40408014)) // RW, TMR0 DMA current address +#define R32_TMR0_DMA_BEG (*((volatile uint32_t *)0x40408018)) // RW, TMR0 DMA begin address +#define R32_TMR0_DMA_END (*((volatile uint32_t *)0x4040801C)) // RW, TMR0 DMA end address + +/* Timer1 register */ +#define R32_TMR1_CONTROL (*((volatile uint32_t *)0x40408400)) // RW, TMR1 control +#define R8_TMR1_CTRL_MOD (*((volatile uint8_t *)0x40408400)) // RW, TMR1 mode control +#define R8_TMR1_CTRL_DMA (*((volatile uint8_t *)0x40408401)) // RW, TMR1 DMA control +#define R8_TMR1_INTER_EN (*((volatile uint8_t *)0x40408402)) // RW, TMR1 interrupt enable +#define R8_TMR1_NRZI_CK_DIV (*((volatile uint8_t *)0x40408403)) // RW, TMR1 NRZI clock divisor, only low 4 bit, from 0 to 15 +#define R32_TMR1_STATUS (*((volatile uint32_t *)0x40408404)) // RW, TMR1 status +#define R8_TMR1_NRZI_STATUS (*((volatile uint8_t *)0x40408404)) // RO, TMR1 NRZI status +#define R8_TMR1_INT_FLAG (*((volatile uint8_t *)0x40408406)) // RW1, TMR1 interrupt flag +#define R8_TMR1_FIFO_COUNT (*((volatile uint8_t *)0x40408407)) // RO, TMR1 FIFO count status +#define R32_TMR1_COUNT (*((volatile uint32_t *)0x40408408)) // RO, TMR1 current count +#define R16_TMR1_COUNT (*((volatile uint16_t *)0x40408408)) // RO, TMR1 current count +#define R8_TMR1_COUNT (*((volatile uint8_t *)0x40408408)) // RO, TMR1 current count +#define R32_TMR1_CNT_END (*((volatile uint32_t *)0x4040840C)) // RW, TMR1 end count value, only low 28 bit +#define R32_TMR1_FIFO (*((volatile uint32_t *)0x40408410)) // RO/WO, TMR1 FIFO register, only low 28 bit +#define R16_TMR1_FIFO (*((volatile uint16_t *)0x40408410)) // RO/WO, TMR1 FIFO register +#define R8_TMR1_FIFO (*((volatile uint8_t *)0x40408410)) // RO/WO, TMR1 FIFO register +#define R32_TMR1_DMA_NOW (*((volatile uint32_t *)0x40408414)) // RW, TMR1 DMA current address +#define R32_TMR1_DMA_BEG (*((volatile uint32_t *)0x40408418)) // RW, TMR1 DMA begin address +#define R32_TMR1_DMA_END (*((volatile uint32_t *)0x4040841C)) // RW, TMR1 DMA end address + +/* Timer2 register */ +#define R32_TMR2_CONTROL (*((volatile uint32_t *)0x40408800)) // RW, TMR2 control +#define R8_TMR2_CTRL_MOD (*((volatile uint8_t *)0x40408800)) // RW, TMR2 mode control +#define R8_TMR2_CTRL_DMA (*((volatile uint8_t *)0x40408801)) // RW, TMR2 DMA control +#define R8_TMR2_INTER_EN (*((volatile uint8_t *)0x40408802)) // RW, TMR2 interrupt enable +#define R32_TMR2_STATUS (*((volatile uint32_t *)0x40408804)) // RW, TMR2 status +#define R8_TMR2_INT_FLAG (*((volatile uint8_t *)0x40408806)) // RW1, TMR2 interrupt flag +#define R8_TMR2_FIFO_COUNT (*((volatile uint8_t *)0x40408807)) // RO, TMR2 FIFO count status +#define R32_TMR2_COUNT (*((volatile uint32_t *)0x40408808)) // RO, TMR2 current count +#define R16_TMR2_COUNT (*((volatile uint16_t *)0x40408808)) // RO, TMR2 current count +#define R8_TMR2_COUNT (*((volatile uint8_t *)0x40408808)) // RO, TMR2 current count +#define R32_TMR2_CNT_END (*((volatile uint32_t *)0x4040880C)) // RW, TMR2 end count value, only low 28 bit +#define R32_TMR2_FIFO (*((volatile uint32_t *)0x40408810)) // RO/WO, TMR2 FIFO register, only low 28 bit +#define R16_TMR2_FIFO (*((volatile uint16_t *)0x40408810)) // RO/WO, TMR2 FIFO register +#define R8_TMR2_FIFO (*((volatile uint8_t *)0x40408810)) // RO/WO, TMR2 FIFO register +#define R32_TMR2_DMA_NOW (*((volatile uint32_t *)0x40408814)) // RW, TMR2 DMA current address +#define R32_TMR2_DMA_BEG (*((volatile uint32_t *)0x40408818)) // RW, TMR2 DMA begin address +#define R32_TMR2_DMA_END (*((volatile uint32_t *)0x4040881C)) // RW, TMR2 DMA end address + +/* Timer3 register */ +#define R32_TMR3_CONTROL (*((volatile uint32_t *)0x40408C00)) // RW, TMR3 control +#define R8_TMR3_CTRL_MOD (*((volatile uint8_t *)0x40408C00)) // RW, TMR3 mode control +#define R8_TMR3_INTER_EN (*((volatile uint8_t *)0x40408C02)) // RW, TMR3 interrupt enable +#define R32_TMR3_STATUS (*((volatile uint32_t *)0x40408C04)) // RW, TMR3 status +#define R8_TMR3_INT_FLAG (*((volatile uint8_t *)0x40408C06)) // RW1, TMR3 interrupt flag +#define R8_TMR3_FIFO_COUNT (*((volatile uint8_t *)0x40408C07)) // RO, TMR3 FIFO count status +#define R32_TMR3_COUNT (*((volatile uint32_t *)0x40408C08)) // RO, TMR3 current count +#define R16_TMR3_COUNT (*((volatile uint16_t *)0x40408C08)) // RO, TMR3 current count +#define R8_TMR3_COUNT (*((volatile uint8_t *)0x40408C08)) // RO, TMR3 current count +#define R32_TMR3_CNT_END (*((volatile uint32_t *)0x40408C0C)) // RW, TMR3 end count value, only low 28 bit +#define R32_TMR3_FIFO (*((volatile uint32_t *)0x40408C10)) // RO/WO, TMR3 FIFO register, only low 28 bit +#define R16_TMR3_FIFO (*((volatile uint16_t *)0x40408C10)) // RO/WO, TMR3 FIFO register +#define R8_TMR3_FIFO (*((volatile uint8_t *)0x40408C10)) // RO/WO, TMR3 FIFO register + +/* Timer register address offset and bit define */ +#define TMR_FIFO_SIZE 8 // timer FIFO size (depth) +#define BA_TMR0 ((volatile uint8_t *)0x40408000) // point TMR0 base address +#define BA_TMR1 ((volatile uint8_t *)0x40408400) // point TMR1 base address +#define BA_TMR2 ((volatile uint8_t *)0x40408800) // point TMR2 base address +#define BA_TMR3 ((volatile uint8_t *)0x40408C00) // point TMR3 base address +#define TMR_CTRL_MOD 0 +#define RB_TMR_MODE_IN 0x01 // RW, timer in mode: 0=timer/PWM/count/NRZI encode, 1=catcher/NRZI decode +#define RB_TMR_ALL_CLEAR 0x02 // RW, force clear timer FIFO and count +#define RB_TMR_COUNT_EN 0x04 // RW, timer count enable +#define RB_TMR_OUT_EN 0x08 // RW, timer output enable +#define RB_TMR_OUT_POLAR 0x10 // RW, timer PWM/NRZI encode output polarity: 0=high action, 1=low action +#define RB_TMR_CAT_WIDTH 0x10 // RW, timer catcher input pulse min width selection: 0=16*clock, 1=8*clock +#define RB_TMR_MODE_NRZI 0x20 // RW, TMR0/TMR1 NRZI mode: 0=timer/PWM/catcher, 1=NRZI encode/decode +#define RB_TMR3_MODE_COUNT 0x20 // RW, TMR3 count mode: 0=timer/PWM/catcher/NRZI, 1=count +#define RB_TMR_PWM_REPEAT 0xC0 // RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 +#define RB_TMR_CATCH_EDGE 0xC0 // RW, timer catcher edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise +#define TMR_CTRL_DMA 1 +#define RB_TMR_DMA_ENABLE 0x01 // RW, timer DMA enable +#define RB_TMR_DMA_BURST 0x02 // RW, timer DMA burst enable +#define RB_TMR_DMA_LOOP 0x04 // RW, timer DMA address loop enable +#define TMR_INTER_EN 2 +#define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer catcher count timeout or PWM cycle end +#define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer catcher input action or PWM trigger or NRZI recv packet end/tran packet end +#define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half +#define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer DMA completion +#define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow +#define RB_TMR_IE_DMA_ERR 0x20 // RW, enable interrupt for timer DMA respond error +#define RB_TMR3_FORCE_EN 0x80 // RW, TMR3 force together timer0/1/2 count enable, independent of RB_TMR_COUNT_EN +#define TMR_NRZI_CK_DIV 3 +#define TMR_NRZI_STATUS 4 +#define RB_TMR_RECV_FREE 0x01 // RO, timer NRZI receiver free status, 0->1 then RB_TMR_IF_DATA_ACT for recv +#define RB_TMR_RECV_ERR 0x02 // RO, timer NRZI receiving error status, 0->1 then RB_TMR_IF_NRZI_AUX for recv +#define RB_TMR_TRAN_END 0x10 // RO, timer NRZI transmittal end status, 0->1 then RB_TMR_IF_DATA_ACT for tran +#define RB_TMR_TRAN_DOE 0x20 // RO, timer NRZI transmitter encode output enable status, 0->1 then RB_TMR_IF_NRZI_AUX for tran +#define TMR_INT_FLAG 6 +#define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer catcher count timeout or PWM cycle end +#define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer catcher input action or PWM trigger or NRZI recv packet end/tran packet end +#define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half +#define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer DMA completion +#define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow +#define RB_TMR_IF_DMA_ERR 0x20 // RW1, interrupt flag for timer DMA respond error +#define TMR_FIFO_COUNT 7 +#define TMR_COUNT 0x08 +#define TMR_CNT_END 0x0C +#define TMR_FIFO 0x10 +#define TMR_DMA_NOW 0x14 +#define TMR_DMA_BEG 0x18 +#define TMR_DMA_END 0x1C +#define MASK_TMR_DMA_ADDR 0x0003ffff + +#define BA_XBUS ((uint32_t *)0x60C00000) // point XBUS base address +#define SZ_XBUS 0x00100000 // XBUS size + +#include +#include +#include "ISP564.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BITS_CFG(REGISTER,bit,en) ((en) == ENABLE ? (REGISTER |= (uint32_t)(bit)) : (REGISTER &= (uint32_t)~(bit))) + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_adc.h b/Peripheral/inc/ch564_adc.h new file mode 100644 index 0000000..3e42e6b --- /dev/null +++ b/Peripheral/inc/ch564_adc.h @@ -0,0 +1,283 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_ADC_H +#define __CH564_ADC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +typedef enum +{ + ADC_Channel0 = 0x00, + ADC_Channel1, + ADC_Channel2, + ADC_Channel0_1, + ADC_Channel3, + ADC_Channel4, + ADC_Channel5, + ADC_Channel6, + ADC_ChannelREF, + ADC_ChannelCN +} ADCChannelTypedef; +/*********************************************************************************** + * @fn ADC_CMD + * + * @brief ADC Enable/Disable + * + * @param en + * - ENABLE + * - DISABLE + */ +#define ADC_CMD(en) \ + { \ + (en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_POWER_ON) : (R8_ADC_CTRL_MOD &= ~RB_ADC_POWER_ON); \ + } +/*********************************************************************************** + * @fn ADC_SET_SAMPLE_WIDTH_2CLK + * + * @brief ADC Sample time 2clk enable + * + * @param en + * - ENABLE + * - DISABLE + * @return none + */ +#define ADC_SET_SAMPLE_WIDTH_2CLK(en) \ + { \ + (en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_SAMPLE_WID) : (R8_ADC_CTRL_MOD &= RB_ADC_SAMPLE_WID); \ + } +/*********************************************************************************** + * @fn ADC_SET_SAMPLE_CYCLE + * + * @brief Config ADC sample cycle. + * + * @param val + * - val = 0:Manual Control + * - val = 0b000001 - 0b111111:Sampling every val clock + * @return none + */ +#define ADC_SET_SAMPLE_CYCLE(val) \ + ({ \ + R8_ADC_CTRL_MOD &= ~RB_ADC_CYCLE_CLK; \ + R8_ADC_CTRL_MOD |= (val) & RB_ADC_CYCLE_CLK; \ + R32_ADC_CTRL &= ~MASK_ADC_CYCLE_BIT_4_6; \ + R32_ADC_CTRL |= (((val) >> 4) << 25) & MASK_ADC_CYCLE_BIT_4_6; \ + }) +/*********************************************************************************** + * @fn ADC_DMA_CMD + * + * @brief Config the ADC DMA control and etc. + * + * @param RB_ADC_IE + * - RB_ADC_IE_ADC_CMP + * - RB_ADC_DMA_ENABLE + * - RB_ADC_DMA_BURST + * - RB_ADC_DMA_LOOP + * - RB_ADC_CHAN_OE + * - RB_ADC_MAN_SAMPLE + * + * en + * - ENABLE + * - DISABLE + * @return none + */ +#define ADC_DMA_CMD(RB_ADC_DMA, en) \ + ({ (en) == ENABLE ? (R8_ADC_CTRL_DMA |= (RB_ADC_DMA)) : (R8_ADC_CTRL_DMA &= ~(RB_ADC_DMA)); }) +/*********************************************************************************** + * @fn ADC_IT_CONFIG + * + * @brief ADC interrupt enable + * + * @param RB_ADC_IE + * - RB_ADC_IE_ADC_CMP + * - RB_ADC_IE_ADC_END + * - RB_ADC_IE_FIFO_HF + * - RB_ADC_IE_DMA_END + * - RB_ADC_IE_FIFO_OV + * - RB_ADC_IE_DMA_ERR + * - RB_ADC_CMP_MOD_EQ + * - RB_ADC_CMP_MOD_GT + * en + * - ENABLE + * - DISABLE + * @return none + */ +#define ADC_IT_CONFIG(RB_ADC_IE, en) \ + ({ (en) == ENABLE ? (R8_ADC_INTER_EN |= (RB_ADC_IE)) : (R8_ADC_INTER_EN &= ~(RB_ADC_IE)); }) +/*********************************************************************************** + * @fn ADC_SET_12BITRESOLUTION + * + * @brief ADC 12bit resolution enable + * + * @param en + * - ENABLE + * - DISABLE + * @return none + */ +#define ADC_SET_12BITRESOLUTION(en) \ + ({ (en) == ENABLE ? (R32_ADC_CTRL |= MASK_ADC_BIT_MODE) : (R32_ADC_CTRL &= ~MASK_ADC_BIT_MODE); }) +/*********************************************************************************** + * @fn ADC_SET_SAMPLE_TIME + * + * @brief Config ADC sample calibration time. + * + * @param val + * - ADC sample calibration time + * @return none + */ +#define ADC_SET_SAMPLE_TIME(val) \ + ({ \ + R32_ADC_CTRL &= ~MASK_ADC_SMAPLE_TIME; \ + R32_ADC_CTRL |= MASK_ADC_SMAPLE_TIME & ((val) << 4); \ + }) +/*********************************************************************************** + * @fn ADC_DMA_SET_RANGE + * + * @brief Config ADC DMA transport range + * + * @param startAddress + * - ADC DMA Handling Start Address + * endAddress + * - ADC DMA Handling End Address + * @return none + */ +#define ADC_DMA_SET_RANGE(startAddress, endAddress) \ + ({ \ + R32_ADC_DMA_BEG = (uint32_t)(startAddress) & MASK_ADC_DMA_ADDR; \ + R32_ADC_DMA_END = (uint32_t)(endAddress) & MASK_ADC_DMA_ADDR; \ + }) +/*********************************************************************************** + * @fn ADC_DMA_GET_CURRENT + * + * @brief Get ADC DMA current transport address + * + * @return R32_ADC_DMA_NOW + */ +#define ADC_DMA_GET_CURRENT() (R32_ADC_DMA_NOW & MASK_ADC_DMA_ADDR) +/*********************************************************************************** + * @fn ADC_DMA_GET_BEGIN + * + * @brief Get ADC DMA start transport address + * + * @return R32_ADC_DMA_BEG + */ +#define ADC_DMA_GET_BEGIN() (R32_ADC_DMA_BEG & MASK_ADC_DMA_ADDR) +/*********************************************************************************** + * @fn ADC_DMA_GET_END + * + * @brief Get ADC DMA end transport address + * + * @return R32_ADC_DMA_END + */ +#define ADC_DMA_GET_END() (R32_ADC_DMA_END & MASK_ADC_DMA_ADDR) +/*********************************************************************************** + * @fn ADC_GET_FIFO + * + * @brief Get ADC's FIFO content + * + * @return R16_ADC_FIFO + */ +#define ADC_GET_FIFO() (R16_ADC_FIFO) +/*********************************************************************************** + * @fn ADC_SET_COMPARE_VAL + * + * @brief Config ADC comparison reference value + * + * @param val + * - ADC comparison reference value + * @return none + */ +#define ADC_SET_COMPARE_VAL(val) ({ R16_ADC_CMP_VALUE = ADC_CMP_VALUE & (val); }) +/*********************************************************************************** + * @fn ADC_GET_FIFO_CNT + * + * @brief Get ADC's FIFO count + * + * @return R8_ADC_FIFO_COUNT + */ +#define ADC_GET_FIFO_CNT() (R8_ADC_FIFO_COUNT) +/*********************************************************************************** + * @fn ADC_GET_VAL + * + * @brief Get ADC's converted value + * + * @return R16_ADC_DATA + */ +#define ADC_GET_VAL() (R16_ADC_DATA) +/*********************************************************************************** + * @fn ADC_SET_DIV + * + * @brief Config ADC crossover coefficients + * + * @param val + * - ADC crossover coefficients + * @return none + */ +#define ADC_SET_DIV(value) ({ R8_ADC_CLOCK_DIV = (value); }) +/*********************************************************************************** + * @fn ADC_CLEAR_IT + * + * @brief Config ADC crossover coefficients + * + * @param RB_ADC_IF + * - RB_ADC_IF_ADC_CMP + * - RB_ADC_IF_ADC_END + * - RB_ADC_IF_FIFO_HF + * - RB_ADC_IF_DMA_END + * - RB_ADC_IF_FIFO_OV + * - RB_ADC_IF_DMA_ERR + * - RB_ADC_EOC_FLAG + * - RB_ADC_CHAN_INDEX + * en + * - ENABLE + * - DISABLE + */ +#define ADC_CLEAR_IT(RB_ADC_IF) ({ R8_ADC_INT_FLAG |= (RB_ADC_IF); }) +/*********************************************************************************** + * @fn ADC_GET_IT + * + * @brief Config ADC crossover coefficients + * + * @param RB_ADC_IF + * - RB_ADC_IF_ADC_CMP + * - RB_ADC_IF_ADC_END + * - RB_ADC_IF_FIFO_HF + * - RB_ADC_IF_DMA_END + * - RB_ADC_IF_FIFO_OV + * - RB_ADC_IF_DMA_ERR + * - RB_ADC_EOC_FLAG + * - RB_ADC_CHAN_INDEX + * @return 0:No Interrupt or interrupt flag + * + */ +#define ADC_GET_IT(RB_ADC_IF) (R8_ADC_INT_FLAG & (RB_ADC_IF)) +/*********************************************************************************** + * @fn ADC_MEASURE + * + * @brief Manually initiated measurements + * + * @return none + */ +#define ADC_MEASURE() ({ R8_ADC_CTRL_DMA |= RB_ADC_MAN_SAMPLE; }) + +void ADC_SelectChannel(ADCChannelTypedef adcChannel); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_eth.h b/Peripheral/inc/ch564_eth.h new file mode 100644 index 0000000..545477a --- /dev/null +++ b/Peripheral/inc/ch564_eth.h @@ -0,0 +1,1446 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_eth.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * ETH firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_ETH_H +#define __CH564_ETH_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch564.h" + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((unsigned int)0x00700000) +#define DMA_RPS_Mask ((unsigned int)0x000E0000) + +/* ETH Init structure definition */ +typedef struct { + uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ +}ETH_InitTypeDef; + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1536 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/* ETH DMA structure definition */ +typedef struct +{ + uint32_t volatile Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((unsigned int)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((unsigned int)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((unsigned int)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((unsigned int)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((unsigned int)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((unsigned int)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((unsigned int)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((unsigned int)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((unsigned int)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((unsigned int)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((unsigned int)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((unsigned int)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((unsigned int)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((unsigned int)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((unsigned int)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((unsigned int)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((unsigned int)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((unsigned int)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((unsigned int)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((unsigned int)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((unsigned int)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((unsigned int)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((unsigned int)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((unsigned int)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((unsigned int)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((unsigned int)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((unsigned int)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((unsigned int)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((unsigned int)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((unsigned int)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((unsigned int)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((unsigned int)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((unsigned int)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((unsigned int)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((unsigned int)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((unsigned int)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((unsigned int)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((unsigned int)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((unsigned int)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((unsigned int)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((unsigned int)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((unsigned int)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((unsigned int)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((unsigned int)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((unsigned int)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((unsigned int)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((unsigned int)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((unsigned int)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((unsigned int)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((unsigned int)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((unsigned int)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((unsigned int)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((unsigned int)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((unsigned int)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((unsigned int)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((unsigned int)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((unsigned int)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((unsigned int)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((unsigned int)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((unsigned int)0x004FFFFF) +#define PHY_WRITE_TO ((unsigned int)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((unsigned int)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((unsigned int)0x00FFFFFF) + +/********************* MACCR *********************/ + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((unsigned int)0x00000000) +#define ETH_Watchdog_Disable ((unsigned int)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((unsigned int)0x00000000) +#define ETH_Jabber_Disable ((unsigned int)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((unsigned int)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((unsigned int)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((unsigned int)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((unsigned int)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((unsigned int)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((unsigned int)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((unsigned int)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((unsigned int)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((unsigned int)0x00000000) +#define ETH_CarrierSense_Disable ((unsigned int)0x00010000) + +/* MAC speed */ +#define ETH_Speed_Mask ((unsigned int)0x00004000) + +/* MAC receive own */ +#define ETH_ReceiveOwn_Mask ((unsigned int)0x00002000) + +/* MAC Duplex Mode*/ +#define ETH_Duplex_Mode_Mask ((unsigned int)0x00000800) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((unsigned int)0x00000400) +#define ETH_ChecksumOffload_Disable ((unsigned int)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((unsigned int)0x00000000) +#define ETH_RetryTransmission_Disable ((unsigned int)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((unsigned int)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((unsigned int)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((unsigned int)0x00000000) +#define ETH_BackOffLimit_8 ((unsigned int)0x00000020) +#define ETH_BackOffLimit_4 ((unsigned int)0x00000040) +#define ETH_BackOffLimit_1 ((unsigned int)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((unsigned int)0x00000010) +#define ETH_DeferralCheck_Disable ((unsigned int)0x00000000) + +/********************* MACFFR *********************/ + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((unsigned int)0x80000000) +#define ETH_ReceiveAll_Disable ((unsigned int)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((unsigned int)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((unsigned int)0x00000300) +#define ETH_SourceAddrFilter_Disable ((unsigned int)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((unsigned int)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((unsigned int)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((unsigned int)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((unsigned int)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((unsigned int)0x00000001) +#define ETH_PromiscuousMode_Disable ((unsigned int)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((unsigned int)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((unsigned int)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((unsigned int)0x00000000) +#define ETH_MulticastFramesFilter_None ((unsigned int)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((unsigned int)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((unsigned int)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((unsigned int)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((unsigned int)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((unsigned int)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((unsigned int)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((unsigned int)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((unsigned int)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((unsigned int)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((unsigned int)0x00000002) +#define ETH_TransmitFlowControl_Disable ((unsigned int)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((unsigned int)0x00010000) +#define ETH_VLANTagComparison_16Bit ((unsigned int)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((unsigned int)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((unsigned int)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((unsigned int)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((unsigned int)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((unsigned int)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((unsigned int)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((unsigned int)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((unsigned int)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((unsigned int)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((unsigned int)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((unsigned int)0x00000000) +#define ETH_MAC_Address1 ((unsigned int)0x00000008) +#define ETH_MAC_Address2 ((unsigned int)0x00000010) +#define ETH_MAC_Address3 ((unsigned int)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((unsigned int)0x00000000) +#define ETH_MAC_AddressFilter_DA ((unsigned int)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((unsigned int)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((unsigned int)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((unsigned int)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((unsigned int)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((unsigned int)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((unsigned int)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((unsigned int)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((unsigned int)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((unsigned int)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((unsigned int)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((unsigned int)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((unsigned int)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((unsigned int)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((unsigned int)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((unsigned int)0x00200000) +#define ETH_TransmitStoreForward_Disable ((unsigned int)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((unsigned int)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((unsigned int)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((unsigned int)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((unsigned int)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((unsigned int)0x00000004) +#define ETH_SecondFrameOperate_Disable ((unsigned int)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((unsigned int)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((unsigned int)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((unsigned int)0x00010000) +#define ETH_FixedBurst_Disable ((unsigned int)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((unsigned int)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((unsigned int)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((unsigned int)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((unsigned int)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((unsigned int)0x00000002) + +/* DMA interrupt FLAG */ +#define ETH_DMA_FLAG_TST ((unsigned int)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((unsigned int)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((unsigned int)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((unsigned int)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((unsigned int)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((unsigned int)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_PHYSR ((unsigned int)0x00000800) /* PHY interrupt flag */ +#define ETH_DMA_FLAG_ET ((unsigned int)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((unsigned int)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((unsigned int)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((unsigned int)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((unsigned int)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((unsigned int)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((unsigned int)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((unsigned int)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((unsigned int)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((unsigned int)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((unsigned int)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_TST ((unsigned int)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((unsigned int)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((unsigned int)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((unsigned int)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((unsigned int)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_PHYSR ((unsigned int)0x00000800) /* PHY interrupt */ +#define ETH_DMA_IT_ET ((unsigned int)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((unsigned int)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((unsigned int)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((unsigned int)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((unsigned int)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((unsigned int)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((unsigned int)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((unsigned int)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((unsigned int)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((unsigned int)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((unsigned int)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((unsigned int)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((unsigned int)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((unsigned int)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((unsigned int)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((unsigned int)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((unsigned int)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((unsigned int)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((unsigned int)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((unsigned int)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((unsigned int)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((unsigned int)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((unsigned int)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((unsigned int)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((unsigned int)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((unsigned int)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((unsigned int)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((unsigned int)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((unsigned int)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((unsigned int)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((unsigned int)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((unsigned int)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((unsigned int)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((unsigned int)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((unsigned int)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((unsigned int)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((unsigned int)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((unsigned int)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((unsigned int)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((unsigned int)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((unsigned int)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ +#define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ +#define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ +#define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ +#define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ +#define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ +#define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ +#define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_PHYSTAT ((unsigned int)0x00000800) /* PHY interrupt status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ +#define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ +#define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ +#define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ +#define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ +#define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ +#define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ +#define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ +#define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ +#define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ +#define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ +#define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ +#define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ +#define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ +#define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ +#define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ +#define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ +#define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ +#define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ +#define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* +/* ETH MMC Register +/* +/******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + + +/******************************************************************************/ +/* +/* ETH Precise Clock Protocol Register +/* +/******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/******************************************************************************/ +/* +/* ETH DMA Register +/* +/******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ +#define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ +#define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ +#define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ +#define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ +#define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ +#define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ +#define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ +#define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ +#define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ +#define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ +#define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + +#define ETH_MAC_BASE ((uint32_t)0x40406000) +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/*PHY configure register*/ +#define ETH_PHY_CR_PHY_RSTN ((unsigned int)0x80000000) //read-write Ethernet PHY global reset signal +#define ETH_PHY_CR_PHY_PD ((unsigned int)0x40000000) //read-write PHY pd mode selection +#define ETH_PHY_CR_PHY_EEE ((unsigned int)0x20000000) //read-write PHY work mode selection +#define ETH_PHY_CR_DUPlEX ((unsigned int)0x00000400) //read-only Even Ethernet mode selection +#define ETH_PHY_CR_SPEED ((unsigned int)0x00000200) //read-only Even Ethernet speed selection +#define ETH_PHY_CR_PHYADDR_EN ((unsigned int)0x00000080) //read-write Reconfigure the PHY address +#define ETH_PHY_CR_REPHYADDR ((unsigned int)0x0000001f) //read-write when the bit 7 set 1,bit4-0 serves as the address of thePHY + +/*CHKSUM configure register*/ +#define ETH_CHKSUM_CR_CHKSUM_EN ((unsigned int)0x00000100) //read-write the software sets 1 at the beginning of frame calculationand write 0at the end of frame calculation +#define ETH_CHKSUM_CR_BYTE_EN2 ((unsigned int)0x000000f0) //read-write Participate in the ip header checksum tocalculate byte control bits +#define ETH_CHKSUM_CR_BYTE_EN1 ((unsigned int)0x0000000f) //read-write Participate in the ip header checksum tocalculate byte control bits + +/*IP packet register*/ +#define ETH_IP_PDR ((unsigned int)0xffffffff) //read-write IP data written by software,need to be used withETH_CHKSUM_CR + +/*IP packet Header Checksum register*/ +#define ETH_CHKSUM_HR_RESULT ((unsigned int)0x0000ffff) //read-write IP header checksum + +/*IP data Checksum register*/ +#define ETH_CHKSUM_PR_RESULT ((unsigned int)0x0000ffff) //read-write IP header checksum + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((unsigned int)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((unsigned int)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((unsigned int)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((unsigned int)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((unsigned int)0) +#define ETH_SUCCESS ((unsigned int)1) + + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_PHYIDR1 0x02 /*PHY Identifier Register*/ +#define PHY_PHYIDR2 0x03 /*PHY Identifier Register*/ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_ANNPTR 0x07 +#define PHY_ANLPNPR 0x08 +#define PHY_PAG_SEL 0x1F + +/****************Page 0********************/ +#define PHY_MMD_CONTROL 0x0D +#define PHY_MMD_ADDR 0x0E +#define PHY_FLASE_CAR_CNT 0x14 +#define PHY_RECV_ERR_CNT 0x15 +#define PHY_PWR_SAVE 0x18 +#define PHY_CONTROL1 0x19 +#define PHY_STATUS1 0x1A +#define PHY_ADDR 0x1B +#define PHY_MDI_MDIX 0x1C +#define PHY_INTERRUPT_IND 0x1E + +/****************Page 4********************/ +#define PHY_EEE_CAP0 0x10 +#define PHY_EEE_CAP1 0x15 +#define PHY_CRC_DET 0x17 +#define PHY_RX_CRCERR_CNT 0x18 +#define PHY_RX_PACKET_CNT 0x19 +#define PHY_BT100_ANA 0x1A + +/****************Page 7********************/ +#define PHY_EEEPC1R 0x00 +#define PHY_EEEPS1R 0x01 +#define PHY_EEECR 0x14 +#define PHY_EEEWER 0x16 +#define PHY_EEEAR 0x3C +#define PHY_EEELPAR 0x3D + +#define PHY_CUST_LED_SET 0x11 +#define PHY_EEE_LED_EN 0x12 +#define PHY_INTERRUPT_MASK 0x13 +#define PHY_LED_CONTROL 0x15 + +/****************Page 8********************/ +#define PHY_WKUPF_MASK0 0x10 +#define PHY_WKUPF_MASK1 0x11 +#define PHY_WKUPF_MASK2 0x12 +#define PHY_WKUPF_MASK3 0x13 +#define PHY_WKUPF_MASK4 0x14 +#define PHY_WKUPF_MASK5 0x15 +#define PHY_WKUPF_MASK6 0x16 +#define PHY_WKUPF_MASK7 0x17 + +/****************Page 16********************/ +#define PHY_WKCRC0 0x10 + +/****************Page 17********************/ +#define PHY_WOL_ABILITY 0x10 +#define PHY_WOL_RESET 0x11 +#define PHY_WOL_ISO_PMEB 0x13 +#define PHY_WOL_CTRL_SET 0x14 +#define PHY_WOL_STATUS 0x15 +#define PHY_WOL_PA_DBYTE0 0x16 +#define PHY_WOL_PA_DBYTE1 0x17 +#define PHY_WOL_PA_DBYTE2 0x18 + +/****************Page 18********************/ +#define PHY_UNI_PHY_ADDR0 0x10 +#define PHY_UNI_PHY_ADDR1 0x11 +#define PHY_UNI_PHY_ADDR2 0x12 +#define PHY_MULTICAST0 0x13 +#define PHY_MULTICAST1 0x14 +#define PHY_MULTICAST2 0x15 +#define PHY_MULTICAST3 0x16 + +#define PHY_REG_PAGE0 0x00 +#define PHY_REG_PAGE4 0x04 +#define PHY_REG_PAGE7 0x07 +#define PHY_REG_PAGE8 0x08 +#define PHY_REG_PAGE16 0x10 +#define PHY_REG_PAGE17 0x11 +#define PHY_REG_PAGE18 0x12 + +/***************INTERRUPT_IND******************/ +#define INTERRUPT_AUTO_NEGOTIATION_ERR ((uint16_t)0x8000) +#define INTERRUPT_SPEED_CHANGE ((uint16_t)0x4000) +#define INTERRUPT_DUPLEX_CHANGE ((uint16_t)0x2000) +#define INTERRUPT_LINK_CHANGE ((uint16_t)0x0800) +#define INTERRUPT_WOL_DONE ((uint16_t)0x0001) + +/***************PHY_WOL_STATUS******************/ +#define WOL_DONE_INT ((uint16_t)0x0001) + +void ETH_Start(void); + +void printf_dmasr (void); + +void ETH_DropRxPkt(void); + +void print_dmasr_rps(void); + +void print_dmasr_tps(void); + +void print_dmasr_tbus(void); + +void ETH_SoftwareReset(void); + +uint32_t ETH_GetRxPktSize(void); + +void ETH_MMCCountersReset(void); + +void ETH_FlushTransmitFIFO(void); + +void delay_clk (uint32_t nCount); + +void ETH_ResumeDMAReception(void); + +FlagStatus ETH_GetlinkStaus (void); + +void ETH_ResumeDMATransmission(void); + +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); + +void ETH_InitiatePauseControlFrame(void); + +uint32_t ETH_GetReceiveProcessState(void); + +uint32_t ETH_GetTransmitProcessState(void); + +FlagStatus ETH_GetSoftwareResetStatus(void); + +uint32_t ETH_GetCurrentTxBufferAddress(void); + +uint32_t ETH_GetCurrentRxBufferAddress(void); + +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); + +FlagStatus ETH_GetFlowControlBusyStatus(void); + +uint32_t ETH_GetCurrentTxDescStartAddress(void); + +uint32_t ETH_GetCurrentRxDescStartAddress(void); + +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); + +void ETH_PowerDownCmd(FunctionalState NewState); + +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); + +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); + +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); + +void ETH_MACReceptionCmd(FunctionalState NewState); + +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); + +void ETH_DMAReceptionCmd(FunctionalState NewState); + +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); + +void ETH_MMCResetOnReadCmd(FunctionalState NewState); + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); + +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); + +void ETH_MACTransmissionCmd(FunctionalState NewState); + +void ETH_DMATransmissionCmd(FunctionalState NewState); + +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); + +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); + +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); + +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); + +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); + +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); + +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); + +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); + +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); + +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); + +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); + +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); + +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); + +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); + +void ETH_BackPressureActivationCmd(FunctionalState NewState); + +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); + +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); + +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); + +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); + +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); + +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); + +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); + +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); + +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); + +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); + +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); + +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); + +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); + +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); + +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); + +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); + +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); + +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); + +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); + +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); + +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); + +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); + +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); + +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); + +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); + +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); + +void ETH_InitializePTPTimeStamp(void); + +void ETH_EnablePTPTimeStampAddend(void); + +void ETH_EnablePTPTimeStampUpdate(void); + +void ETH_SetPTPTimeStampAddend(uint32_t Value); + +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +void ETH_EnablePTPTimeStampInterruptTrigger(void); + +void ETH_PTPTimeStampCmd(FunctionalState NewState); + +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); + +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); + +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); + +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); + +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); + +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); + +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); + + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch564_gpio.h b/Peripheral/inc/ch564_gpio.h new file mode 100644 index 0000000..08da89a --- /dev/null +++ b/Peripheral/inc/ch564_gpio.h @@ -0,0 +1,237 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_gpio.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_GPIO_H +#define __CH564_GPIO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +#define GPIO_Pin_0 (0x00000001)/*!< Pin 0 selected */ +#define GPIO_Pin_1 (0x00000002)/*!< Pin 1 selected */ +#define GPIO_Pin_2 (0x00000004)/*!< Pin 2 selected */ +#define GPIO_Pin_3 (0x00000008)/*!< Pin 3 selected */ +#define GPIO_Pin_4 (0x00000010)/*!< Pin 4 selected */ +#define GPIO_Pin_5 (0x00000020)/*!< Pin 5 selected */ +#define GPIO_Pin_6 (0x00000040)/*!< Pin 6 selected */ +#define GPIO_Pin_7 (0x00000080)/*!< Pin 7 selected */ +#define GPIO_Pin_8 (0x00000100)/*!< Pin 8 selected */ +#define GPIO_Pin_9 (0x00000200)/*!< Pin 9 selected */ +#define GPIO_Pin_10 (0x00000400)/*!< Pin 10 selected */ +#define GPIO_Pin_11 (0x00000800)/*!< Pin 11 selected */ +#define GPIO_Pin_12 (0x00001000)/*!< Pin 12 selected */ +#define GPIO_Pin_13 (0x00002000)/*!< Pin 13 selected */ +#define GPIO_Pin_14 (0x00004000)/*!< Pin 14 selected */ +#define GPIO_Pin_15 (0x00008000)/*!< Pin 15 selected */ +#define GPIO_Pin_16 (0x00010000)/*!< Pin 16 selected */ +#define GPIO_Pin_17 (0x00020000)/*!< Pin 17 selected */ +#define GPIO_Pin_18 (0x00040000)/*!< Pin 18 selected */ +#define GPIO_Pin_19 (0x00080000)/*!< Pin 19 selected */ +#define GPIO_Pin_20 (0x00100000)/*!< Pin 20 selected */ +#define GPIO_Pin_21 (0x00200000)/*!< Pin 21 selected */ +#define GPIO_Pin_22 (0x00400000)/*!< Pin 22 selected */ +#define GPIO_Pin_23 (0x00800000)/*!< Pin 23 selected */ +#define GPIO_Pin_24 (0x01000000)/*!< Pin 24 selected */ +#define GPIO_Pin_25 (0x02000000)/*!< Pin 25 selected */ +#define GPIO_Pin_26 (0x04000000)/*!< Pin 26 selected */ +#define GPIO_Pin_27 (0x08000000)/*!< Pin 27 selected */ +#define GPIO_Pin_28 (0x10000000)/*!< Pin 28 selected */ +#define GPIO_Pin_29 (0x20000000)/*!< Pin 29 selected */ +#define GPIO_Pin_30 (0x40000000)/*!< Pin 30 selected */ +#define GPIO_Pin_31 (0x80000000)/*!< Pin 31 selected */ +#define GPIO_Pin_All (0xFFFFFFFF)/*!< All pins selected */ + +#define GPIO_NoRemap_SPI0 (0x00020000) +#define GPIO_PartialRemap1_SPI0 (0x00020001) +#define GPIO_PartialRemap2_SPI0 (0x00020002) +#define GPIO_FullRemap_SPI0 (0x00020003) + +#define GPIO_NoRemap_UART0 (0x00220000) +#define GPIO_PartialRemap2_UART0 (0x00220002) +#define GPIO_FullRemap_UART0 (0x00220003) + +#define GPIO_NoRemap_UART1 (0x00420000) +#define GPIO_PartialRemap1_UART1 (0x00420001) +#define GPIO_FullRemap_UART1 (0x00420003) + +#define GPIO_NoRemap_UART2 (0x00620000) +#define GPIO_PartialRemap1_UART2 (0x00620001) +#define GPIO_PartialRemap2_UART2 (0x00620002) +#define GPIO_FullRemap_UART2 (0x00620003) + +#define GPIO_NoRemap_UART3 (0x00820000) +#define GPIO_PartialRemap1_UART3 (0x00820001) +#define GPIO_FullRemap_UART3 (0x00820003) + +#define GPIO_NoRemap_UART0_MODEM (0x00a20000) +#define GPIO_PartialRemap1_UART0_MODEM (0x00a20001) +#define GPIO_PartialRemap2_UART0_MODEM (0x00a20002) +#define GPIO_FullRemap_UART0_MODEM (0x00a20003) + +#define GPIO_NoRemap_UART1_MODEM (0x00c20000) +#define GPIO_PartialRemap1_UART1_MODEM (0x00c20001) +#define GPIO_PartialRemap2_UART1_MODEM (0x00c20002) +#define GPIO_FullRemap_UART1_MODEM (0x00c20003) + +#define GPIO_NoRemap_UART2_MODEM (0x00e20000) +#define GPIO_PartialRemap2_UART2_MODEM (0x00e20002) +#define GPIO_FullRemap_UART2_MODEM (0x00e20003) + +#define GPIO_NoRemap_I2C (0x01020000) +#define GPIO_PartialRemap1_I2C (0x01020001) + +#define GPIO_NoRemap_SLV_INTERUPT (0x01220000) +#define GPIO_PartialRemap1_SLV_INTERUPT (0x01220001) +#define GPIO_PartialRemap2_SLV_INTERUPT (0x01220002) +#define GPIO_FullRemap_SLV_INTERUPT (0x01220003) + +#define GPIO_NoRemap_SLV_CS (0x01420000) +#define GPIO_PartialRemap1_SLV_CS (0x01420001) + +#define GPIO_NoRemap_SLV_ADDR (0x01620000) +#define GPIO_PartialRemap1_SLV_ADDR (0x01620001) +#define GPIO_PartialRemap2_SLV_ADDR (0x01620002) + +#define GPIO_NoRemap_SLV_ADDR1 (0x01820000) +#define GPIO_PartialRemap2_SLV_ADDR1 (0x01820002) +#define GPIO_FullRemap_SLV_ADDR1 (0x01820003) + +#define GPIO_NoRemap_SLV_DATA (0x01a20000) +#define GPIO_PartialRemap1_SLV_DATA (0x01a20001) + +#define GPIO_NoRemap_SLV_RW (0x01c20000) +#define GPIO_NolRemap_SLV_RW GPIO_NoRemap_SLV_RW +#define GPIO_PartialRemap1_SLV_RW (0x01c20001) + +#define GPIO_NoRemap_LINK_LED (0x01e20000) +#define GPIO_PartialRemap1_LINK_LED (0x01e20001) +#define GPIO_PartialRemap2_LINK_LED (0x01e20002) +#define GPIO_FullRemap_LINK_LED (0x01e20003) + +#define GPIO_NoRemap_ACT_LED (0x80020000) +#define GPIO_PartialRemap1_ACT_LED (0x80020001) +#define GPIO_PartialRemap2_ACT_LED (0x80020002) +#define GPIO_FullRemap_ACT_LED (0x80020003) + +#define GPIO_NoRemap_RST (0x80220000) +#define GPIO_PartialRemap1_RST (0x80220001) +#define GPIO_PartialRemap2_RST (0x80220002) +#define GPIO_FullRemap_RST (0x80220003) + +#define GPIO_NoRemap_TIMER0 (0x80410000) +#define GPIO_FullRemap_TIMER0 (0x80410001) + +#define GPIO_NoRemap_TIMER1 (0x80510000) +#define GPIO_FullRemap_TIMER1 (0x80510001) + +#define GPIO_NoRemap_BUSY (0x80610000) +#define GPIO_FullRemap_BUSY (0x80610001) + +#define GPIO_NoRemap_SPI1 (0x80820000) +#define GPIO_FullRemap_SPI1 (0x80820003) + +#define GPIO_NoRemap_TNOW0 (0x80a20000) +#define GPIO_FullRemap_TNOW0 (0x80a20003) + +#define GPIO_NoRemap_TNOW1 (0x80c20000) +#define GPIO_FullRemap_TNOW1 (0x80c20003) + +#define GPIO_NoRemap_TNOW2 (0x80e20000) +#define GPIO_FullRemap_TNOW2 (0x80e20003) + +#define GPIO_NoRemap_TNOW3 (0x81020000) +#define GPIO_FullRemap_TNOW3 (0x81020003) + +#define GPIO_NoRemap_UART3_MODEM (0x81220000) +#define GPIO_FullRemap_UART3_MODEM (0x81220003) + +/** + * @brief GPIO mode structure configuration + */ +typedef enum +{ + GPIO_ModeIN_Floating = 0, + GPIO_ModeIN_PU, + GPIO_ModeIN_PD, + GPIO_ModeOut_PP, + GPIO_ModeOut_OP +} GPIOModeTypeDef; + +/** + * @brief GPIO interrupt structure configuration + */ +typedef enum +{ + GPIO_ITMode_LowLevel = 0, // Low level trigger + GPIO_ITMode_HighLevel, // High level trigger + GPIO_ITMode_FallEdge, // Falling edge trigger + GPIO_ITMode_RiseEdge, // Rising edge trigger + GPIO_ITMode_None +} GPIOITModeTpDef; + +/** + * @brief GPIO MCO structure configuration + */ +typedef enum +{ + MCO_125 = 0, + MCO_25 = 4, + MCO_2d5 = 0xC, +} MCOMode; + +void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOA port pin mode configuration */ +void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */ +void GPIOD_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */ +#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin) /* GPIOA port pin output set low */ +#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin) /* GPIOA port pin output set high */ +#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin) /* GPIOB port pin output set low */ +#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin) /* GPIOB port pin output set high */ +#define GPIOD_ResetBits(pin) (R32_PD_OUT &= ~pin) /* GPIOA port pin output set low */ +#define GPIOD_SetBits(pin) (R32_PD_OUT |= pin) /* GPIOA port pin output set high */ +#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin) /* GPIOA port pin output level flip */ +#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin) /* GPIOB port pin output level flip */ +#define GPIOD_InverseBits(pin) (R32_PD_OUT ^= pin) /* GPIOB port pin output level flip */ +#define GPIOA_ReadPort() (R32_PA_PIN) /* The 32-bit data returned by the GPIOA port, the lower 16 bits are valid */ +#define GPIOB_ReadPort() (R32_PB_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */ +#define GPIOD_ReadPort() (R32_PD_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */ +#define GPIOA_ReadPortPin(pin) (R32_PA_PIN & pin) /* GPIOA port pin status, 0-pin low level, (!0)-pin high level */ +#define GPIOB_ReadPortPin(pin) (R32_PB_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */ +#define GPIOD_ReadPortPin(pin) (R32_PD_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */ +void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOA pin interrupt mode configuration */ +void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */ +void GPIOD_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */ +#define GPIOA_ReadITFlagPort() (R32_INT_STATUS_PA) /* Read GPIOA port interrupt flag status */ +#define GPIOB_ReadITFlagPort() (R32_INT_STATUS_PB) /* Read GPIOB port interrupt flag status */ +#define GPIOD_ReadITFlagPort() (R32_INT_STATUS_PD) /* Read GPIOD port interrupt flag status */ + +/*************************************Read Interrupt Bit Flag************************************/ +#define GPIOA_ReadITFLAGBit(pin) (R32_INT_STATUS_PA & pin) +#define GPIOB_ReadITFLAGBit(pin) (R32_INT_STATUS_PB & pin) +#define GPIOD_ReadITFLAGBit(pin) (R32_INT_STATUS_PD & pin) + +/*************************************Clear Interrupt Bit Flag************************************/ +#define GPIOA_ClearITFlagbit(pin) (R32_INT_STATUS_PA |= pin) +#define GPIOB_ClearITFlagbit(pin) (R32_INT_STATUS_PB |= pin) +#define GPIOD_ClearITFlagbit(pin) (R32_INT_STATUS_PD |= pin) + +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewSTA); +void GPIO_IPD_Unused(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_i2c.h b/Peripheral/inc/ch564_i2c.h new file mode 100644 index 0000000..270d3cb --- /dev/null +++ b/Peripheral/inc/ch564_i2c.h @@ -0,0 +1,188 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_i2c.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * I2C firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_I2C_H +#define __CH564_I2C_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* STAR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* STAR1 register flags */ +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + + /****************I2C Master Events (Events grouped in order of communication)********************/ + +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + /******************I2C Slave Events (Events grouped in order of communication)******************/ + +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +void I2C_DeInit(I2C_Typedef *I2Cx); +void I2C_Init(I2C_Typedef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); +void I2C_Cmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_Typedef *I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_Typedef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_Typedef *I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_Typedef *I2Cx); +void I2C_Send7bitAddress(I2C_Typedef *I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_Typedef *I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_NACKPosition); +void I2C_TransmitPEC(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_Typedef *I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_Typedef *I2Cx); +void I2C_ARPCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_Typedef *I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_Typedef *I2Cx, uint16_t I2C_DutyCycle); + +/**************************************************************************************** + * I2C State Monitoring Functions + ****************************************************************************************/ + +ErrorStatus I2C_CheckEvent(I2C_Typedef *I2Cx, uint32_t I2C_EVENT); +uint32_t I2C_GetLastEvent(I2C_Typedef *I2Cx); +FlagStatus I2C_GetFlagStatus(I2C_Typedef *I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_Typedef *I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_Typedef *I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_Typedef *I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_pwr.h b/Peripheral/inc/ch564_pwr.h new file mode 100644 index 0000000..9158d0a --- /dev/null +++ b/Peripheral/inc/ch564_pwr.h @@ -0,0 +1,67 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_pwr.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * PWR firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_PWR_H +#define __CH564_PWR_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +#define WDOG_ENABLE() \ +{ \ + R8_SAFE_ACCESS_SIG = 0x57; \ + R8_SAFE_ACCESS_SIG = 0xA8; \ + R8_GLOB_RST_CFG |= (0x40 | RB_GLOB_WDOG_EN); \ + R8_SAFE_ACCESS_SIG = 0x00; \ +} +#define WDOG_DISABLE() \ +{ \ + R8_SAFE_ACCESS_SIG = 0x57; \ + R8_SAFE_ACCESS_SIG = 0xA8; \ + R8_GLOB_RST_CFG = 0x40; \ + R8_SAFE_ACCESS_SIG = 0x00; \ +} +#define FEED_DOG() (R8_WDOG_CLEAR = 0) +#define VIO_PWN_INT_CMD(cmd) \ +{ \ + cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_INT_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_INT_EN); \ +} +#define VIO_PWN_RST_CMD(cmd) \ +{ \ + cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_RST_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_RST_EN); \ +} +#define VIO_PWN_IO_CMD(cmd) \ +{ \ + cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_IO_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_IO_EN); \ +} +#define LDO_DORMENCY_EN(cmd) \ +{ \ + cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_LDO_SLP_EN) : (R32_EXTEN_CTLR1 &= ~RB_LDO_SLP_EN); \ +} + + + +void PWR_Sleep(uint8_t PWR_STOPEntry); +void PWR_DeepSleep(uint8_t PWR_STOPEntry); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_rcc.h b/Peripheral/inc/ch564_rcc.h new file mode 100644 index 0000000..41d02db --- /dev/null +++ b/Peripheral/inc/ch564_rcc.h @@ -0,0 +1,133 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_rcc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * RCC firmware library. + ********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH564_RCC_H +#define __CH564_RCC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +#define RCC_UNLOCK_SAFE_ACCESS() \ +({ \ + R8_SAFE_ACCESS_SIG = 0x57; \ + R8_SAFE_ACCESS_SIG = 0xA8; \ + __NOP(); \ +}) + +#define RCC_LOCK_SAFE_ACCESS() ({ R8_SAFE_ACCESS_SIG = 0x0; }) +#define RCC_GET_ID_SAFELY() (R8_SAFE_ACCESS_ID) +#define RCC_CLEAR_WDOG() ({ R8_WDOG_CLEAR = 0; }) + +#define HSI_ON() (R32_EXTEN_CTLR1 |= RB_HSION) +#define HSE_ON() (R32_EXTEN_CTLR1 |= RB_HSEON) +#define HSE_GET_STTATEUS() ((R32_EXTEN_CTLR1 & 0x8000) != 0 ? 1 : 0) +#define HSI_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSION) +#define HSE_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSEON) +#define USB_PLL_ON() \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 |= (RB_USBPLLON); \ + RCC_LOCK_SAFE_ACCESS(); \ +} +#define USB_PLL_OFF() \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \ + RCC_LOCK_SAFE_ACCESS(); \ +} +#define USB_PLL_MUL_15 0x0000c000 +#define USB_PLL_MUL_16 0x00008000 +#define USB_PLL_MUL_20 0x00004000 +#define USB_PLL_MUL_24 0x00000000 +#define USB_PLL_MUL_SELECT(USB_PLL_MUL) \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 &= ~USB_PLL_MUL_15; \ + R32_EXTEN_CTLR0 |= (USB_PLL_MUL); \ + RCC_LOCK_SAFE_ACCESS(); \ +} +#define USB_PLL_SOURCE_HSI 0x00000060 +#define USB_PLL_SOURCE_HSE 0x00000020 +#define USB_PLL_SOURCE_ETH_PLL_OUT 0x00000040 +#define USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE) \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 &= ~USB_PLL_SOURCE_HSI; \ + R32_EXTEN_CTLR0 |= (USB_PLL_SOURCE); \ + RCC_LOCK_SAFE_ACCESS(); \ +} + +#define CLKSEL_HSI() \ +{ \ + R32_EXTEN_CTLR1 &= ~(RB_CLKSEL); \ +} +#define CLKSEL_HSE() \ +{ \ + R32_EXTEN_CTLR1 |= (RB_CLKSEL); \ +} +#define USB_PLL_ON() \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 |= (RB_USBPLLON); \ + RCC_LOCK_SAFE_ACCESS(); \ +} +#define USB_PLL_OFF() \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \ + RCC_LOCK_SAFE_ACCESS(); \ +} +#define SYSCLK_SOURCE_USBPLL 0 +#define SYSCLK_SOURCE_HSI_HSE 1 +#define SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE) \ +{ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + ((SYSCLK_SOURCE) == SYSCLK_SOURCE_HSI_HSE) ? (R32_EXTEN_CTLR0 |= (RB_SW)) : (R32_EXTEN_CTLR0 &= ~(RB_SW)); \ + RCC_LOCK_SAFE_ACCESS(); \ +} + +#define RCC_GET_GLOB_RST_KEEP() (R8_GLOB_RESET_KEEP) +#define RCC_SET_GLOB_RST_KEEP(val) (R8_GLOB_RESET_KEEP = (val);) +#define RCC_SET_PLL_SYS_OUT_DIV(val) \ +({ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + R8_PLL_OUT_DIV = 0x04 | ((val) << 4); \ + RCC_LOCK_SAFE_ACCESS(); \ +}) +#define RCC_FLASH_CLK_PRE_DIV(sta) \ +({ \ + RCC_UNLOCK_SAFE_ACCESS(); \ + ((sta) == ENABLE) ? (R32_EXTEN_CTLR0 |= 0x00200000) : (R32_EXTEN_CTLR0 &= ~0x00200000) RCC_LOCK_SAFE_ACCESS(); \ +}) + +typedef enum +{ + Code16k_Data128k = 0x0, + Code48k_Data96k = 0x1, + Code80k_Data64k = 0x2 +} GlobMem_Cfg; + +void RCC_SetGlobalMemCFG(GlobMem_Cfg Cfg); +void RCC_LockPort(uint8_t globport, FunctionalState NewSTA); +void RCC_GlobleRstCFG(uint8_t cfg, FunctionalState NewSTA); +void RCC_SlpClkOff(volatile uint8_t *reg, uint8_t slpclk, FunctionalState NewSTA); +void RCC_SlpWakeCtrl(uint8_t slpwake, FunctionalState NewSTA); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_slv.h b/Peripheral/inc/ch564_slv.h new file mode 100644 index 0000000..7467176 --- /dev/null +++ b/Peripheral/inc/ch564_slv.h @@ -0,0 +1,69 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_slv.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * SLV firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_SLV_H +#define __CH564_SLV_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +typedef enum +{ + slv_data, + slv_cmd, + slv_timeout +} SLV_STA; + +#define SLV_CFG(cfglist, en) (BITS_CFG(R8_SLV_CONFIG, cfglist, en)) +#define SLV_SEND_DATA(data) (R8_SLV_DOUT = (data)) +#define SLV_SEND_STA(status) (R8_SLV_STATUS = (status)) +#define SLV_GET_IF(RB_IF_SLV) (R8_INT_FLAG_SLV & (RB_IF_SLV)) +#define SLV_CLEAR_IF(RB_IF_SLV) (R8_INT_FLAG_SLV |= (RB_IF_SLV)) +#define SLV_GET_DATA() (R8_INT_SLV_DIN) +#define SLV_DMA_CFG(cfglist, en) (BITS_CFG(R8_DMA_EN_SLV, cfglist, en)) +#define SLV_SET_MODE_CTRL(cfglist, en) (BITS_CFG(R8_DMA_MODE_CTRL_SLV, cfglist, en)) +#define SLV_SET_MODE_EN(cfglist, en) (BITS_CFG(R8_DMA_MODE_EN_SLV, cfglist, en)) + +#define SLV_DMA_GET_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV & (slv_dma_if)) +#define SLV_DMA_CLEAR_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV |= (slv_dma_if)) +#define SLV_DMA_START_ADDR_RD(address) (R32_RD_DMA_START_ADDR_SLV = (uint32_t)(address)) + +#define SLV_DMA_END_ADDR_RD(address) (R32_RD_DMA_END_ADDR_SLV = (uint32_t)(address)) + +#define SLV_DMA_START_ADDR_WR(address) (R32_WR_DMA_START_ADDR_SLV = (uint32_t)(address)) + +#define SLV_DMA_END_ADDR_WR(address) (R32_WR_DMA_END_ADDR_SLV = (uint32_t)(address)) + +#define SLV_DMA_GET_NOW_ADDR() (R32_DMA_END_NOW_SLV) + +#define SLV_SET_DMA_CMD0(cmd) (R8_DMA_CMD0_SLV = (cmd)) + +#define SLV_SET_DMA_CMD1(cmd) (R8_DMA_CMD1_SLV = (cmd)) +#define SLV_SET_RST_CMD(cmd) (R8_SLV_RESET_CMD = (cmd)) + +#define SLV_GET_OTHER_DATA() (R8_OTHER_DATA) +#define SLV_GET_DMA_DEC_LEN() (R16_DMA_DEC_LEN) +#define SLV_GET_DMA_DEC_OFFSET() (R16_DMA_DEC_OFFSET) + +SLV_STA SLV_Read(uint8_t *dataAddress, uint16_t dataSize, uint16_t timeout); +ErrorStatus SLV_SendDATA(uint8_t *data, uint16_t datasize); +ErrorStatus SLV_SendSTA(uint8_t *sta, uint16_t datasize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_spi.h b/Peripheral/inc/ch564_spi.h new file mode 100644 index 0000000..8ae6357 --- /dev/null +++ b/Peripheral/inc/ch564_spi.h @@ -0,0 +1,141 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_spi.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * SPI firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_SPI_H +#define __CH564_SPI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +/** + * @brief SPI0 interrupt bit define + */ +#define SPI0_IT_FST_BYTE RB_SPI_IE_FST_BYTE +#define SPI0_IT_FIFO_OV RB_SPI_IE_FIFO_OV +#define SPI0_IT_DMA_END RB_SPI_IE_DMA_END +#define SPI0_IT_FIFO_HF RB_SPI_IE_FIFO_HF +#define SPI0_IT_BYTE_END RB_SPI_IE_BYTE_END +#define SPI0_IT_CNT_END RB_SPI_IE_CNT_END + +#define SPI_MAX_DELAY 0xffff + +/** + * @brief Configuration data mode + */ +typedef enum +{ + Mode0_HighBitINFront, + Mode3_HighBitINFront, +} ModeBitOrderTypeDef; + +/** + * @brief Configuration SPI slave mode + */ +typedef enum +{ + Mode_DataStream = 0, + Mose_FirstCmd, +} Slave_ModeTypeDef; + +/**************** SPI0 */ +void SPI0_MasterInit(uint32_t clockRate); +void SPI0_DataMode(ModeBitOrderTypeDef mode); + +void SPI0_MasterSendByte(uint8_t data); +uint8_t SPI0_MasterRecvByte(void); + +void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len); +void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len); + +void SPI0_DMATrans(uint8_t *pbuf, uint32_t len); +void SPI0_DMARecv(uint8_t *pbuf, uint32_t len); +void SPI0_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len); + +void SPI0_SlaveInit(); +#define SetFirst0Data(data) (R8_SPI0_SLAVE_PRE = (data)) +void SPI0_SlaveSendByte(uint8_t data); +uint8_t SPI0_SlaveRecvByte(void); + +uint8_t SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts); +uint8_t SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts); + +// refer to SPI0 interrupt bit define +#define SPI0_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI0_CTRL_MOD, cfglist, en) +#define SPI0_ITCfg(cfglist, en) BITS_CFG(R8_SPI0_INTER_EN, cfglist, en) +#define SPI0_SET_CLOCK_DIV(div) (R8_SPI0_CLOCK_DIV = (div)) +#define SPI0_GetITFlag(f) (R8_SPI0_INT_FLAG & (f)) +#define SPI0_ClearITFlag(f) (R8_SPI0_INT_FLAG = (f)) +#define SPI0_SET_RST(dat) (R8_SPI0_RESET_CMD = (dat)) +#define SPI0_GET_RST() (R8_SPI0_RESET_CMD) +#define SPI0_GET_BUSY() (R8_SPI0_BUSY) +#define SPI0_GET_BUFFER() (R8_SPI0_BUFFER) +#define SPI0_SET_BUFFER(dat) (R8_SPI0_BUFFER = (dat)) +#define SPI0_CLEAR_FIFO() (R8_SPI0_CTRL_MOD |= RB_SPI_ALL_CLEAR); +#define SPI0_GET_FIFO() (R8_SPI0_FIFO) +#define SPI0_SET_FIFO(dat) (R8_SPI0_FIFO = (dat)) +#define SPI0_SET_FIFO_CNT(cnt) (R8_SPI0_FIFO_COUNT = (cnt)) +#define SPI0_GET_FIFO_CNT() (R8_SPI0_FIFO_COUNT) +#define SPI0_SET_TOTAL_CNT(cnt) (R16_SPI0_TOTAL_CNT = (cnt) ) +#define SPI0_GET_TOTAL_CNT() (R16_SPI0_TOTAL_CNT) + +#define SPI0_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI0_CTRL_DMA, cfglist, en) +#define SPI0_SET_DMA_RANGE(start, end) \ +({ \ + R32_SPI0_DMA_BEG = (uint32_t)(start) & MASK_SPI0_DMA_ADDR; \ + R32_SPI0_DMA_END = (uint32_t)(end) & MASK_SPI0_DMA_ADDR; \ +}) + +/**************** SPI1 */ +void SPI1_MasterInit(uint32_t clockRate); +void SPI1_DataMode(ModeBitOrderTypeDef mode); + +void SPI1_MasterSendByte(uint8_t data); +uint8_t SPI1_MasterRecvByte(void); + +void SPI1_MasterTrans(uint8_t *pbuf, uint16_t len); +void SPI1_MasterRecv(uint8_t *pbuf, uint16_t len); + +void SPI1_SlaveInit(); +#define SetFirst1Data(data) (R8_SPI1_SLAVE_PRE = (data)) +void SPI1_SlaveSendByte(uint8_t data); +uint8_t SPI1_SlaveRecvByte(void); + +uint8_t SPI1_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts); +uint8_t SPI1_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts); + +// refer to SPI1 interrupt bit define +#define SPI1_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI1_CTRL_MOD, cfglist, en) +#define SPI1_ITCfg(cfglist, en) BITS_CFG(R8_SPI1_INTER_EN, cfglist, en) +#define SPI1_SET_CLOCK_DIV(div) (R8_SPI1_CLOCK_DIV = (div)) +#define SPI1_GetITFlag(f) (R8_SPI1_INT_FLAG & (f)) +#define SPI1_ClearITFlag(f) (R8_SPI1_INT_FLAG = (f)) +#define SPI1_GET_BUFFER() (R8_SPI1_BUFFER) +#define SPI1_SET_BUFFER(dat) (R8_SPI1_BUFFER = (dat)) +#define SPI1_CLEAR_FIFO() (R8_SPI1_CTRL_MOD |= RB_SPI_ALL_CLEAR); +#define SPI1_GET_FIFO() (R8_SPI1_FIFO) +#define SPI1_SET_FIFO(dat) (R8_SPI1_FIFO = (dat)) +#define SPI1_SET_FIFO_CNT(cnt) (R8_SPI1_FIFO_COUNT = (cnt)) +#define SPI1_GET_FIFO_CNT() (R8_SPI1_FIFO_COUNT) +#define SPI1_SET_TOTAL_CNT(cnt) (R16_SPI1_TOTAL_CNT = (cnt)) +#define SPI1_GET_TOTAL_CNT() (R16_SPI1_TOTAL_CNT) + +#define SPI1_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI1_CTRL_DMA, (cfglist), (en)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_tim.h b/Peripheral/inc/ch564_tim.h new file mode 100644 index 0000000..028889e --- /dev/null +++ b/Peripheral/inc/ch564_tim.h @@ -0,0 +1,231 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_TIM_H +#define __CH564_TIM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +/** + * @brief Pulse Width Modulation Effective Output Words + */ +typedef enum +{ + PWM_Times_1 = 0, // PWM effective output repeats 1 times + PWM_Times_4 = 1, // PWM effective output repeats 4 times + PWM_Times_8 = 2, // PWM effective output repeats 8 times + PWM_Times_16 = 3, // PWM effective output repeats 16 times +} PWM_RepeatTsTypeDef; + +/** + * @brief Input Capture Edge Mode + */ +typedef enum +{ + CAP_NULL = 0, // not capture + Edge_To_Edge = 1, // between any edge + FallEdge_To_FallEdge = 2, // falling edge to falling edge + RiseEdge_To_RiseEdge = 3, // rising edge to rising edge +} CapModeTypeDef; + +/** + * @brief Input Capture Edge Mode + */ +typedef enum +{ + clock16 = 0, + clock8 +} CapWidthTypedef; + +/** + * @brief Direct access memory loop mode + */ +typedef enum +{ + Mode_Single = 0, // single mode + Mode_LOOP = 1, // cycle mode + Mode_Burst = 2, + Mode_Burst_Loop = 3 +} DMAModeTypeDef; + +/** + * @brief PWM output polarity + */ +typedef enum +{ + high_on_low = 0, // Default low level, high level is active + low_on_high = 1, // Default high level, low level active +} PWM_PolarTypeDef; + +/****************** TMR0 */ +// Timing and counting +void TMR0_TimerInit(uint32_t arr); /* Timing function initialization */ +#define TMR0_DeInit() (R8_TMR0_CTRL_MOD = 0) +#define TMR0_GetCurrentCount() R32_TMR0_COUNT /* Get the current count value, 67108864 */ +#define TMR0_ClrCurrentCount() {R8_TMR0_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR0_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;} +#define TMR0_SET_CNT_END(cnt_end) ({R32_TMR0_CNT_END = (cnt_end);}) + +// Pulse Width Modulation Function +#define TMR0_PWMCycleCfg(cyc) \ + (R32_TMR0_CNT_END = (cyc)) /* PWM0 channel output waveform period configuration, maximum 67108864 */ +void TMR0_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM0 output initialization */ +#define TMR0_PWMActDataWidth(d) (R32_TMR0_FIFO = (d)) /* PWM0 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR0_CAPTimeoutCfg(cyc) \ + (R32_TMR0_CNT_END = (cyc)) /* CAP0 capture level timeout configuration, maximum 33554432 */ +void TMR0_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */ +#define TMR0_CAPGetData() R32_TMR0_FIFO /* Get pulse data */ +#define TMR0_CAPDataCounter() R8_TMR0_FIFO_COUNT /* Get the number of currently captured data */ +void TMR0_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */ + +#define TMR0_Disable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR0 */ +#define TMR0_Enable() (R8_TMR0_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR0 */ +// refer to TMR0 interrupt bit define +#define TMR0_ITCfg(cfglist, en) \ + BITS_CFG(R8_TMR0_INTER_EN, (cfglist), (en)) /* TMR0 corresponding interrupt bit on and off */ +// refer to TMR0 interrupt bit define +#define TMR0_ClearITFlag(f) (R8_TMR0_INT_FLAG = (f)) /* Clear interrupt flag */ +#define TMR0_GetITFlag(f) (R8_TMR0_INT_FLAG & (f)) /* Query interrupt flag status */ + +#define TMR0_DMA_SET_RANGE(start, end) \ +({ \ + R32_TMR0_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \ + R32_TMR0_DMA_END = (end)&MASK_TMR_DMA_ADDR; \ +}) +#define TMR0_DMA_GET_BEG() (R32_TMR0_DMA_BEG) +#define TMR0_DMA_GET_END() (R32_TMR0_DMA_END) +#define TMR0_DMA_GET_NOW() (R32_TMR0_DMA_NOW) + +/****************** TMR1 */ +// Timing and counting +void TMR1_TimerInit(uint32_t arr); /* Timing function initialization */ +#define TMR1_DeInit() (R8_TMR1_CTRL_MOD = 0) +#define TMR1_GetCurrentCount() R32_TMR1_COUNT /* Get the current count value, 67108864 */ +#define TMR1_ClrCurrentCount() {R8_TMR1_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR1_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;} +#define TMR1_SET_CNT_END(cnt_end) ({R32_TMR1_CNT_END = (cnt_end);}) + +// Pulse Width Modulation Function +#define TMR1_PWMCycleCfg(cyc) \ + (R32_TMR1_CNT_END = (cyc)) /* PWM1 channel output waveform period configuration, maximum 67108864 */ +void TMR1_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM1 output initialization */ +#define TMR1_PWMActDataWidth(d) (R32_TMR1_FIFO = (d)) /* PWM1 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR1_CAPTimeoutCfg(cyc) \ + (R32_TMR1_CNT_END = (cyc)) /* CAP1 capture level timeout configuration, maximum 33554432 */ +void TMR1_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */ +#define TMR1_CAPGetData() R32_TMR1_FIFO /* Get pulse data */ +#define TMR1_CAPDataCounter() R8_TMR1_FIFO_COUNT /* Get the number of currently captured data */ + +void TMR1_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */ + +#define TMR1_Disable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR1 */ +#define TMR1_Enable() (R8_TMR1_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR1 */ +// refer to TMR1 interrupt bit define +#define TMR1_ITCfg(cfglist, en) \ + BITS_CFG(R8_TMR1_INTER_EN, (cfglist), (en)) /* TMR1 corresponding interrupt bit on and off */ +// refer to TMR1 interrupt bit define +#define TMR1_ClearITFlag(f) (R8_TMR1_INT_FLAG = (f)) /* Clear interrupt flag */ +#define TMR1_GetITFlag(f) (R8_TMR1_INT_FLAG & (f)) /* Query interrupt flag status */ + +#define TMR1_DMA_SET_RANGE(start, end) \ +({ \ + R32_TMR1_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \ + R32_TMR1_DMA_END = (end)&MASK_TMR_DMA_ADDR; \ +}) +#define TMR1_DMA_GET_BEG() (R32_TMR1_DMA_BEG) +#define TMR1_DMA_GET_END() (R32_TMR1_DMA_END) +#define TMR1_DMA_GET_NOW() (R32_TMR1_DMA_NOW) +/****************** TMR2 */ +// Timing and counting +void TMR2_TimerInit(uint32_t arr); /* Timing function initialization */ +#define TMR2_DeInit() (R8_TMR2_CTRL_MOD = 0) +#define TMR2_GetCurrentCount() R32_TMR2_COUNT /* Get the current count value, 67108864 */ +#define TMR2_ClrCurrentCount() {R8_TMR2_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR2_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;} +#define TMR2_SET_CNT_END(cnt_end) ({R32_TMR2_CNT_END = (cnt_end);}) + +// Pulse Width Modulation Function +#define TMR2_PWMCycleCfg(cyc) \ + (R32_TMR2_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */ +void TMR2_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */ +#define TMR2_PWMActDataWidth(d) (R32_TMR2_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR2_CAPTimeoutCfg(cyc) \ + (R32_TMR2_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */ +void TMR2_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */ +#define TMR2_CAPGetData() R32_TMR2_FIFO /* Get pulse data */ +#define TMR2_CAPDataCounter() R8_TMR2_FIFO_COUNT /* Get the number of currently captured data */ + +void TMR2_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */ + +#define TMR2_Disable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR2 */ +#define TMR2_Enable() (R8_TMR2_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR2 */ +// refer to TMR2 interrupt bit define +#define TMR2_ITCfg(cfglist, en) \ + BITS_CFG(R8_TMR2_INTER_EN, (cfglist), (en)) /* TMR2 corresponding interrupt bit on and off */ +// refer to TMR2 interrupt bit define +#define TMR2_ClearITFlag(f) (R8_TMR2_INT_FLAG = (f)) /* Clear interrupt flag */ +#define TMR2_GetITFlag(f) (R8_TMR2_INT_FLAG & (f)) /* Query interrupt flag status */ + +#define TMR2_DMA_SET_RANGE(start, end) \ +({ \ + R32_TMR2_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \ + R32_TMR2_DMA_END = (end)&MASK_TMR_DMA_ADDR; \ +}) +#define TMR2_DMA_GET_BEG() (R32_TMR2_DMA_BEG) +#define TMR2_DMA_GET_END() (R32_TMR2_DMA_END) +#define TMR2_DMA_GET_NOW() (R32_TMR2_DMA_NOW) +/****************** TMR3 */ +// Timing and counting +void TMR3_TimerInit(uint32_t arr); /* Timing function initialization */ +#define TMR3_DeInit() (R8_TMR3_CTRL_MOD = 0) +void TMR3_EXTSignalCounterInit(uint32_t arr, CapModeTypeDef capedge, + CapWidthTypedef capwidth); /* External signal counting function initialization */ +#define TMR3_GetCurrentCount() R32_TMR3_COUNT /* Get the current count value, 67108864 */ +#define TMR3_ClrCurrentCount() {R8_TMR3_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR3_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;} + +#define TMR3_SET_CNT_END(cnt_end) ({R32_TMR3_CNT_END = (cnt_end);}) + +// Pulse Width Modulation Function +#define TMR3_PWMCycleCfg(cyc) \ + (R32_TMR3_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */ +void TMR3_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */ +#define TMR3_PWMActDataWidth(d) (R32_TMR3_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */ + +// Catch pulse width +#define TMR3_CAPTimeoutCfg(cyc) \ + (R32_TMR3_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */ +void TMR3_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */ +#define TMR3_CAPGetData() R32_TMR3_FIFO /* Get pulse data */ +#define TMR3_CAPDataCounter() R8_TMR3_FIFO_COUNT /* Get the number of currently captured data */ + +#define TMR3_Disable() (R8_TMR3_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR3 */ +#define TMR3_Enable() (R8_TMR3_CTRL_MOD |= RB_TMR_COUNT_EN) /* Close TMR3 */ +// refer to TMR3 interrupt bit define +#define TMR3_ITCfg(cfglist, en) \ + BITS_CFG(R8_TMR3_INTER_EN, (cfglist), (en)) /* TMR3 corresponding interrupt bit on and off */ +// refer to TMR3 interrupt bit define +#define TMR3_ClearITFlag(f) (R8_TMR3_INT_FLAG = (f)) /* Clear interrupt flag */ +#define TMR3_GetITFlag(f) (R8_TMR3_INT_FLAG & (f)) /* Query interrupt flag status */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_uart.h b/Peripheral/inc/ch564_uart.h new file mode 100644 index 0000000..ec32dff --- /dev/null +++ b/Peripheral/inc/ch564_uart.h @@ -0,0 +1,259 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_uart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * UART firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_UART_H +#define __CH564_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch564.h" + +/** + * @brief Line Error Status Definition + */ +#define STA_ERR_BREAK RB_LSR_BREAK_ERR // Data Interval Error +#define STA_ERR_FRAME RB_LSR_FRAME_ERR // DataFrame error +#define STA_ERR_PAR RB_LSR_PAR_ERR // Parity bit error +#define STA_ERR_FIFOOV RB_LSR_OVER_ERR // Receive Data Overflow + +#define STA_TXFIFO_EMP RB_LSR_TX_FIFO_EMP // The current send FIFO is empty, you can continue to fill the send data +#define STA_TXALL_EMP RB_LSR_TX_ALL_EMP // All currently sent data has been sent +#define STA_RECV_DATA RB_LSR_DATA_RDY // Data is currently received + +/** + * @brief Serial port byte trigger configuration + */ +typedef enum { + UART_1BYTE_TRIG = 0, // 1 byte trigger + UART_2BYTE_TRIG = 1, // 2 byte trigger + UART_4BYTE_TRIG = 2, // 4 byte trigger + UART_7BYTE_TRIG = 3, // 7 byte trigger + +} UARTByteTRIGTypeDef; + +/****************** UART0 */ +void UART0_DefInit (void); /* Serial port default initialization configuration */ +void UART0_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */ +void UART0_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */ +void UART0_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */ +void UART0_Reset (void); /* Serial port software reset */ + +#define UART0_SET_DLV(dlv) ({ R8_UART0_DIV = (dlv); }) + +#define UART0_CLR_RXFIFO() (R8_UART0_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART0_CLR_TXFIFO() (R8_UART0_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART0_GetITFlag() (R8_UART0_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */ + +#define UART0_SET_FCR(cfglist, en) BITS_CFG (R8_UART0_FCR, (cfglist), (en)) +#define UART0_SET_LCR(cfglist, en) BITS_CFG (R8_UART0_LCR, (cfglist), (en)) +#define UART0_SET_MCR(cfglist, en) BITS_CFG (R8_UART0_MCR, (cfglist), (en)) + +#define UART0_SET_RTS() UART0_SET_MCR(RB_MCR_RTS,ENABLE) +#define UART0_SET_DTR() UART0_SET_MCR(RB_MCR_DTR,ENABLE) +#define UART0_RESET_RTS() UART0_SET_MCR(RB_MCR_RTS,DISABLE) +#define UART0_RESET_DTR() UART0_SET_MCR(RB_MCR_DTR,DISABLE) + +// please refer to LINE error and status define +#define UART0_GetLinSTA() (R8_UART0_LSR) /* Get the current communication status */ +#define UART0_GetMSRSTA() (R8_UART0_MSR) /* Get the current flow control status, only applicable to UART0 */ + +#define UART0_DMACFG(cfglist, en) BITS_CFG (R8_UART0_DMA_CTRL, (cfglist), (en)) +#define UART0_DMA_SET_RD_RANGE(start, end) \ + ({ \ + R32_UART0_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART0_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART0_DMA_GET_RD_CURRENT_ADDR() (R32_UART0_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_GET_RD_BEG_ADDR() (R32_UART0_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_GET_RD_END_ADDR() (R32_UART0_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_SET_WR_RANGE(start, end) \ + ({ \ + R32_UART0_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART0_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART0_DMA_GET_WR_CURRENT_ADDR() (R32_UART0_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_GET_WR_BEG_ADDR() (R32_UART0_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_GET_WR_END_ADDR() (R32_UART0_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR) +#define UART0_DMA_GET_IT_FLAG(dmaif) (R8_UART0_DMA_IF & (dmaif)) + +#define UART0_SendByte(b) (R8_UART0_THR = (b)) /* Serial port single byte transmission */ +void UART0_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */ +void UART0_Send_DMA (uint8_t *buf, uint32_t lenth); +void UART0_Recv_DMA (uint8_t *buf, uint32_t lenth); +#define UART0_RecvByte() (R8_UART0_RBR) /* Serial port read single byte */ +uint16_t UART0_RecvString (uint8_t *buf); /* Serial port read multibyte */ +void UART0_DTRDSR_Cfg(FunctionalState en); +void UART0_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en); + +/****************** UART1 */ +void UART1_DefInit (void); /* Serial port default initialization configuration */ +void UART1_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */ +void UART1_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */ +void UART1_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */ +void UART1_Reset (void); /* Serial port software reset */ + +#define UART1_SET_DLV(dlv) ({ R8_UART1_DIV = dlv; }) + +#define UART1_CLR_RXFIFO() (R8_UART1_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART1_CLR_TXFIFO() (R8_UART1_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART1_GetITFlag() (R8_UART1_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */ + +#define UART1_SET_FCR(cfglist, en) BITS_CFG (R8_UART1_FCR, (cfglist), (en)) +#define UART1_SET_LCR(cfglist, en) BITS_CFG (R8_UART1_LCR, (cfglist), (en)) +#define UART1_SET_MCR(cfglist, en) BITS_CFG (R8_UART1_MCR, (cfglist), (en)) + +#define UART1_SET_RTS() UART1_SET_MCR(RB_MCR_RTS,ENABLE) +#define UART1_RESET_RTS() UART1_SET_MCR(RB_MCR_RTS,DISABLE) + +// please refer to LINE error and status define +#define UART1_GetLinSTA() (R8_UART1_LSR) /* Get the current communication status */ +#define UART1_GetMSRSTA() (R8_UART1_MSR) /* Get the current flow control status, only applicable to UART1 */ + +#define UART1_DMACFG(cfglist, en) BITS_CFG (R8_UART1_DMA_CTRL, (cfglist), (en)) +#define UART1_DMA_SET_RD_RANGE(start, end) \ + ({ \ + R32_UART1_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART1_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART1_DMA_GET_RD_CURRENT_ADDR() (R32_UART1_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_GET_RD_BEG_ADDR() (R32_UART1_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_GET_RD_END_ADDR() (R32_UART1_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_SET_WR_RANGE(start, end) \ + ({ \ + R32_UART1_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART1_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART1_DMA_GET_WR_CURRENT_ADDR() (R32_UART1_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_GET_WR_BEG_ADDR() (R32_UART1_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_GET_WR_END_ADDR() (R32_UART1_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR) +#define UART1_DMA_GET_IT_FLAG(dmaif) (R8_UART1_DMA_IF & (dmaif)) + +#define UART1_SendByte(b) (R8_UART1_THR = (b)) /* Serial port single byte transmission */ +void UART1_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */ +void UART1_Send_DMA (uint8_t *buf, uint32_t lenth); +void UART1_Recv_DMA (uint8_t *buf, uint32_t lenth); +#define UART1_RecvByte() (R8_UART1_RBR) /* Serial port read single byte */ +uint16_t UART1_RecvString (uint8_t *buf); /* Serial port read multibyte */ +void UART1_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en); + +/****************** UART2 */ +void UART2_DefInit (void); /* Serial port default initialization configuration */ +void UART2_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */ +void UART2_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */ +void UART2_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */ +void UART2_Reset (void); /* Serial port software reset */ + +#define UART2_SET_DLV(dlv) ({ R8_UART2_DIV = (dlv); }) + +#define UART2_CLR_RXFIFO() (R8_UART2_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART2_CLR_TXFIFO() (R8_UART2_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART2_GetITFlag() (R8_UART2_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */ + +#define UART2_SET_FCR(cfglist, en) BITS_CFG (R8_UART2_FCR, (cfglist), (en)) +#define UART2_SET_LCR(cfglist, en) BITS_CFG (R8_UART2_LCR, (cfglist), (en)) +#define UART2_SET_MCR(cfglist, en) BITS_CFG (R8_UART2_MCR, (cfglist), (en)) + +#define UART2_SET_RTS() UART2_SET_MCR(RB_MCR_RTS,ENABLE) +#define UART2_RESET_RTS() UART2_SET_MCR(RB_MCR_RTS,DISABLE) + +// please refer to LINE error and status define +#define UART2_GetLinSTA() (R8_UART2_LSR) /* Get the current communication status */ +#define UART2_GetMSRSTA() (R8_UART2_MSR) /* Get the current flow control status, only applicable to UART2 */ + +#define UART2_DMACFG(cfglist, en) BITS_CFG (R8_UART2_DMA_CTRL, (cfglist), (en)) +#define UART2_DMA_SET_RD_RANGE(start, end) \ + ({ \ + R32_UART2_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART2_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART2_DMA_GET_RD_CURRENT_ADDR() (R32_UART2_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_GET_RD_BEG_ADDR() (R32_UART2_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_GET_RD_END_ADDR() (R32_UART2_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_SET_WR_RANGE(start, end) \ + ({ \ + R32_UART2_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART2_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART2_DMA_GET_WR_CURRENT_ADDR() (R32_UART2_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_GET_WR_BEG_ADDR() (R32_UART2_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_GET_WR_END_ADDR() (R32_UART2_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR) +#define UART2_DMA_GET_IT_FLAG(dmaif) (R8_UART2_DMA_IF & (dmaif)) + +#define UART2_SendByte(b) (R8_UART2_THR = (b)) /* Serial port single byte transmission */ +void UART2_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */ +void UART2_Send_DMA (uint8_t *buf, uint32_t lenth); +void UART2_Recv_DMA (uint8_t *buf, uint32_t lenth); +#define UART2_RecvByte() (R8_UART2_RBR) /* Serial port read single byte */ +uint16_t UART2_RecvString (uint8_t *buf); /* Serial port read multibyte */ +void UART2_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en); + +/****************** UART3 */ +void UART3_DefInit (void); /* Serial port default initialization configuration */ +void UART3_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */ +void UART3_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */ +void UART3_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */ +void UART3_Reset (void); /* Serial port software reset */ + +#define UART3_SET_DLV(dlv) ({ R8_UART3_DIV = dlv; }) + +#define UART3_CLR_RXFIFO() (R8_UART3_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */ +#define UART3_CLR_TXFIFO() (R8_UART3_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */ + +#define UART3_GetITFlag() (R8_UART3_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */ + +#define UART3_SET_FCR(cfglist, en) BITS_CFG (R8_UART3_FCR, (cfglist), (en)) +#define UART3_SET_LCR(cfglist, en) BITS_CFG (R8_UART3_LCR, (cfglist), (en)) +#define UART3_SET_MCR(cfglist, en) BITS_CFG (R8_UART3_MCR, (cfglist), (en)) + +#define UART3_SET_RTS() UART3_SET_MCR(RB_MCR_RTS,ENABLE) +#define UART3_RESET_RTS() UART3_SET_MCR(RB_MCR_RTS,DISABLE) + +// please refer to LINE error and status define +#define UART3_GetLinSTA() (R8_UART3_LSR) /* Get the current communication status */ +#define UART3_GetMSRSTA() (R8_UART3_MSR) /* Get the current flow control status, only applicable to UART3 */ + +#define UART3_DMACFG(cfglist, en) BITS_CFG (R8_UART3_DMA_CTRL, (cfglist), (en)) +#define UART3_DMA_SET_RD_RANGE(start, end) \ + ({ \ + R32_UART3_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART3_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART3_DMA_GET_RD_CURRENT_ADDR() (R32_UART3_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_GET_RD_BEG_ADDR() (R32_UART3_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_GET_RD_END_ADDR() (R32_UART3_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_SET_WR_RANGE(start, end) \ + ({ \ + R32_UART3_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \ + R32_UART3_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \ + }) +#define UART3_DMA_GET_WR_CURRENT_ADDR() (R32_UART3_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_GET_WR_BEG_ADDR() (R32_UART3_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_GET_WR_END_ADDR() (R32_UART3_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR) +#define UART3_DMA_GET_IT_FLAG(dmaif) (R8_UART3_DMA_IF & (dmaif)) + +#define UART3_SendByte(b) (R8_UART3_THR = (b)) /* Serial port single byte transmission */ +void UART3_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */ +void UART3_Send_DMA (uint8_t *buf, uint32_t lenth); +void UART3_Recv_DMA (uint8_t *buf, uint32_t lenth); +#define UART3_RecvByte() (R8_UART3_RBR) /* Serial port read single byte */ +uint16_t UART3_RecvString (uint8_t *buf); /* Serial port read multibyte */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_usb.h b/Peripheral/inc/ch564_usb.h new file mode 100644 index 0000000..137d91a --- /dev/null +++ b/Peripheral/inc/ch564_usb.h @@ -0,0 +1,659 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_usb.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * USB firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_USB_H +#define __CH564_USB_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + +/*******************************************************************************/ +/* USBHS Related Register Macro Definition */ + +/* USBHS Device Register Definition */ +/* Bit definition for USB_CTRL register */ +#define DEV_LPM_EN 0x80 /* LPM enable */ +#define DEV_EN 0x20 /* USB device enabled */ +#define DEV_DMA_EN 0x10 /* DMA transfer enabled */ +#define PHY_SUSPENDM 0x08 /* USB PHY suspend */ +#define USB_ALL_CLR 0x04 /* clear all interrupt flags */ +#define SIE_RESET 0x02 /* USB protocol processor reset */ +#define LINK_RESET 0x01 + +/* Bit definition for usb_BASE_MODE register */ +#define EXP_SPD_MASK 0x03 /* bit[0:1] controls the desired device speed */ +#define EXP_FS_SPD 0x00 /* Full-speed mode */ +#define EXP_HS_SPD 0x01 /* High-speed mode */ +#define EXP_LOW_SPD 0x02 /* Low-speed mode */ + +/* Bit definition for USB_INT_EN register */ +#define FIFO_OVER_IE 0x80 /* USB Overflow interrupt enable */ +#define LINK_RDY_IE 0x40 /* USB connection interrupt enable */ +#define RX_SOF_IE 0x20 /* Receive SOF packet interrupt enable */ +#define RTX_ACT_IE 0x10 /* USB transfer end interrupt enabled */ +#define LPM_ACT_IE 0x08 /* LMP transfer end interrupt enabled */ +#define BUS_SLEEP_IE 0x04 /* USB bus sleep interrupt enabled */ +#define BUS_SUSP_IE 0x02 /* USB bus pause interrupt enabled */ +#define BUS_REST_IE 0x01 /* USB bus reset interrupt enabled */ + +/* Bit definition for USB_DEV_AD register */ +#define MASK_USB_ADDR 0x7f + +/* Bit definition for USB_WAKE_CR register */ +#define RB_RMT_WAKE 0x01 /* remote wake up */ + +/* Bit definition for USB_TEST_MODE register */ +#define RB_TEST_EN 0x80 /* test mode enable */ +#define RB_TEST_SE0NAK 0x08 /* test mode,output SEO */ +#define RB_TEST_PKT 0x04 /* test mode,output a packet */ +#define RB_TEST_K 0x02 /* test mode,output K */ +#define RB_TEST_J 0x01 /* test mode,output J */ + +/* Bit definition for USB_LPM_DATA register */ +#define LPM_BUSY 0x8000 +#define LPM_DATA 0x07ff /* read-only power management data */ + +/* Bit definition for USB_INT_FG register */ +#define FIFO_OVER_IF 0x80 /* read-write USB Overflow interrupt flag */ +#define LINK_RDY_IF 0x40 /* read-write USB connection interrupt flag */ +#define RX_SOF_IF 0x20 /* read-write Receive SOF packet interrupt flag */ +#define RTX_ACT_IF 0x10 /* read-only USB transmission end interrupt flag */ +#define LPM_ACT_IF 0x08 /* read-write LPM transmission end interrupt flag */ +#define BUS_SLEEP_IF 0x04 /* read-write USB bus sleep interrupt flag */ +#define BUS_SUSP_IF 0x02 /* read-write USB bus suspend interrupt flag */ +#define BUS_REST_IF 0x01 /* read-write USB bus reset interrupt flag */ + +/* Bit definition for USB_INT_ST register */ +#define RB_UIS_EP_DIR 0x10 /* Endpoint data transmission direction */ +#define RB_UIS_EP_ID_MASK 0x07 /* The endpoint number at which the data transfer occurs */ + +/* Bit definition for USB_MIS_ST register */ +#define RB_UMS_HS_MOD 0x80 /* whether the host is high-speed */ +#define RB_UMS_SUSP_REQ 0x10 /* USB suspends the request */ +#define RB_UMS_FREE 0x08 /* USB free status */ +#define RB_UMS_SLEEP 0x04 /* USB sleep status */ +#define RB_UMS_SUSPEND 0x02 /* USB suspend status */ +#define RB_UMS_READY 0x01 /* USB connection status */ + +/* Bit definition for USB_FRAMME_NO register */ +#define MICRO_FRAME 0xe000 /* Received micro frame number */ +#define FRAME_NO 0x07ff /* Received frame number */ + +/* Bit definition for USB_BUS register */ +#define USB_DM_ST 0x0008 /* read-only UDM status */ +#define USB_DP_ST 0x0004 /* read-only UDP status */ +#define USB_WAKEUP 0x0001 /* read-only USB wakeup */ + +/* Bit definition for DEV_UEP_TX_EN & DEV_UEP_RX_EN register */ +#define RB_EP0_EN 0x0001 +#define RB_EP1_EN 0x0002 +#define RB_EP2_EN 0x0004 +#define RB_EP3_EN 0x0008 +#define RB_EP4_EN 0x0010 +#define RB_EP5_EN 0x0020 +#define RB_EP6_EN 0x0040 +#define RB_EP7_EN 0x0080 +#define RB_EP8_EN 0x0100 +#define RB_EP9_EN 0x0200 +#define RB_EP10_EN 0x0400 +#define RB_EP11_EN 0x0800 +#define RB_EP12_EN 0x1000 +#define RB_EP13_EN 0x2000 +#define RB_EP14_EN 0x4000 +#define RB_EP15_EN 0x8000 + +/* Bit definition for DEV_UEP_T_TOG_AUTO register */ +#define EP0_T_TOG_AUTO 0x01 +#define EP1_T_TOG_AUTO 0x02 +#define EP2_T_TOG_AUTO 0x04 +#define EP3_T_TOG_AUTO 0x08 +#define EP4_T_TOG_AUTO 0x10 +#define EP5_T_TOG_AUTO 0x20 +#define EP6_T_TOG_AUTO 0x40 +#define EP7_T_TOG_AUTO 0x80 + +/* Bit definition for DEV_UEP_R_TOG_AUTO register */ +#define EP0_R_TOG_AUTO 0x01 +#define EP1_R_TOG_AUTO 0x02 +#define EP2_R_TOG_AUTO 0x04 +#define EP3_R_TOG_AUTO 0x08 +#define EP4_R_TOG_AUTO 0x10 +#define EP5_R_TOG_AUTO 0x20 +#define EP6_R_TOG_AUTO 0x40 +#define EP7_R_TOG_AUTO 0x80 + +/* Bit definition for DEV_UEP_T_BURST register */ +#define EP0_T_BURST_EN 0x01 +#define EP1_T_BURST_EN 0x02 +#define EP2_T_BURST_EN 0x04 +#define EP3_T_BURST_EN 0x08 +#define EP4_T_BURST_EN 0x10 +#define EP5_T_BURST_EN 0x20 +#define EP6_T_BURST_EN 0x40 +#define EP7_T_BURST_EN 0x80 + +/* Bit definition for DEV_UEP_T_BURST_MODE register */ +#define EP0_T_BURST_MODE 0x01 +#define EP1_T_BURST_MODE 0x02 +#define EP2_T_BURST_MODE 0x04 +#define EP3_T_BURST_MODE 0x08 +#define EP4_T_BURST_MODE 0x10 +#define EP5_T_BURST_MODE 0x20 +#define EP6_T_BURST_MODE 0x40 +#define EP7_T_BURST_MODE 0x80 + +/* Bit definition for DEV_UEP_R_BURST register */ +#define EP0_R_BURST_EN 0x01 +#define EP1_R_BURST_EN 0x02 +#define EP2_R_BURST_EN 0x04 +#define EP3_R_BURST_EN 0x08 +#define EP4_R_BURST_EN 0x10 +#define EP5_R_BURST_EN 0x20 +#define EP6_R_BURST_EN 0x40 +#define EP7_R_BURST_EN 0x80 + +/* Bit definition for DEV_UEP_R_RES_MODE register */ +#define EP0_R_RES_MODE 0x01 +#define EP1_R_RES_MODE 0x02 +#define EP2_R_RES_MODE 0x04 +#define EP3_R_RES_MODE 0x08 +#define EP4_R_RES_MODE 0x10 +#define EP5_R_RES_MODE 0x20 +#define EP6_R_RES_MODE 0x40 +#define EP7_R_RES_MODE 0x80 + +/* Bit definition for DEV_UEP_AF_MODE register */ +#define EP1_T_AF 0x02 +#define EP2_T_AF 0x04 +#define EP3_T_AF 0x08 +#define EP4_T_AF 0x10 +#define EP5_T_AF 0x20 +#define EP6_T_AF 0x40 +#define EP7_T_AF 0x80 + +/* Bit definition for UEPx_TX_CTRL register */ +#define USBHS_UEP_T_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */ +#define USBHS_UEP_T_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */ +#define USBHS_UEP_T_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */ +#define USBHS_UEP_T_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */ +#define USBHS_UEP_T_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */ +#define USBHS_UEP_T_TOG_MASK 0x0C /* Synchronization trigger bit mask */ +#define USBHS_UEP_T_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */ +#define USBHS_UEP_T_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */ +#define USBHS_UEP_T_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */ +#define USBHS_UEP_T_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */ +#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */ + +/* Bit definition for UEPx_RX_CTRL register */ +#define USBHS_UEP_R_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */ +#define USBHS_UEP_R_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */ +#define USBHS_UEP_R_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */ +#define USBHS_UEP_R_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */ +#define USBHS_UEP_R_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */ +#define USBHS_UEP_R_TOG_MASK 0x0C /* Synchronization trigger bit mask */ +#define USBHS_UEP_R_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */ +#define USBHS_UEP_R_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */ +#define USBHS_UEP_R_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */ +#define USBHS_UEP_R_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */ +#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */ +#define USBHS_UEP_ENDP_R_DONE 0x80 /* Writing 0 clears the interrupt */ +#define USBHS_RB_SETUP_IS 0x08 /* Indicates whether the reception of endpoint 0 is a Setup transaction */ +#define USBHS_ENDP_R_TOG_MATCH 0x10 + +/* Bit definition for DEV_UEP_T_ISO register */ +#define EP1_T_ISO 0x02 +#define EP2_T_ISO 0x04 +#define EP3_T_ISO 0x08 +#define EP4_T_ISO 0x10 +#define EP5_T_ISO 0x20 +#define EP6_T_ISO 0x40 +#define EP7_T_ISO 0x80 + +/* Bit definition for DEV_UEP_R_ISO register */ +#define EP1_R_ISO 0x02 +#define EP2_R_ISO 0x04 +#define EP3_R_ISO 0x08 +#define EP4_R_ISO 0x10 +#define EP5_R_ISO 0x20 +#define EP6_R_ISO 0x40 +#define EP7_R_ISO 0x80 + +/* USBHS Host Register Definition */ +/* Bit definition for UHOST_CTRL register */ +#define root_LPM_EN (1<<7) +#define ROOT_FORCE_FS (1<<6) +#define ROOT_SOF_EN (1<<5) +#define ROOT_DMA_EN (1<<4) +#define ROOT_PHY_SUSPENDM (1<<3) +#define ROOT_ALL_CLR (1<<2) +#define ROOT_SIE_RESET (1<<1) +#define ROOT_LINK_RESET (1<<0) + +/* Bit definition for UH_INT_EN register */ +#define FIFO_OV_IE (1<<7) +#define TX_HALT_IE (1<<6) +#define SOF_ACT_IE (1<<5) +#define USB_ACT_IE (1<<4) +#define RESUME_ACT_IE (1<<3) +#define WKUP_ACT_IE (1<<2) + +/* Bit definition for UH_CONTROL register */ +#define RX_NO_RES (1<<23) +#define TX_NO_RES (1<<22) +#define RX_NO_DATA (1<<21) +#define TX_NO_DATA (1<<20) +#define TX_LOW_SPD (1<<19) +#define SPLIT_VALID (1<<18) +#define LPM_VALID (1<<17) +#define HOST_ACTION (1<<16) +#define BUF_MODE (1<<10) +#define TOG_MASK (3<<8) +#define TOG_MDATA (3<<8) +#define TOG_DATA2 (2<<8) +#define TOG_DATA1 (1<<8) +#define TOG_DATA0 (0<<8) + +/* Bit definition for UH_INT_FLAG register */ +#define RB_FIFO_OV_IF (1<<7) +#define RB_TX_HALT_IF (1<<6) +#define RB_SOF_ACT_IF (1<<5) +#define RB_USB_ACT_IF (1<<4) +#define RB_RESUME_ACT_IF (1<<3) +#define RB_WKUP_IF (1<<2) + +/* Bit definition for UH_INT_ST register */ +#define PORT_RX_RESUME (1<<4) +#define USB_PID_MASK 0x0f +#define USB_PID_TOUT 0x0 +#define USB_PID_ACK 0x2 +#define USB_PID_NAK 0xa +#define USB_PID_STALL 0xe +#define USB_PID_NYET 0x6 +#define USB_PID_DATA0 0x3 +#define USB_PID_DATA1 0xb +#define USB_PID_DATA2 0x7 +#define USB_PID_MDATA 0xf + +#define USB_PID_PRE 0xc +#define USB_PID_ERR 0xc +#define USB_PID_SPLIT 0x8 +#define USB_PID_PING 0x4 +#define USB_PID_SOF 0x5 +#define USB_PID_SETUP 0xd +#define USB_PID_IN 0x9 +#define USB_PID_OUT 0x1 + +/* Bit definition for UH_MIS_ST register */ +#define RB_BUS_SE0 (1<<7) +#define RB_BUS_J (1<<6) +#define RB_LINESTATE_MASK (0x3<<4) +#define RB_USB_WAKEUP (1<<3) +#define RB_SOF_ST (1<<2) +#define RB_SOF_PRE (1<<1) +#define RB_SOF_FREE (1<<0) + +/* Bit definition for UH_FRAME register */ +#define SOF_CNT_CLR (1<<25) +#define SOF_CNT_EN (1<<24) + +/* Bit definition for PORT_CTRL register */ +#define BUS_RST_LONG (1<<16) +#define PORT_SLEEP_BESL (0xf<<12) +#define CLR_PORT_SLEEP (1<<8) +#define CLR_PORT_CONNECT (1<<5) +#define CLR_PORT_EN (1<<4) +#define SET_PORT_SLEEP (1<<3) +#define CLR_PORT_SUSP (1<<2) +#define SET_PORT_SUSP (1<<1) +#define SET_PORT_RESET (1<<0) + +/* Bit definition for PORT_CFG register */ +#define PORT_15K_RPD (1<<7) +#define PORT_HOST_MODE (1<<0)//1: HOST function +#define PORT_DEVICE_MODE (0<<0)//0: DEVICE function + +/* Bit definition for PORT_INT_EN register */ +#define PORT_SLP_IE (1<<5) +#define PORT_RESET_IE (1<<4) +#define PORT_SUSP_IE (1<<2) +#define PORT_EN_IE (1<<1) +#define PORT_CONNECT_IE (1<<0) + +/* Bit definition for PORT_TEST_CT register */ +#define TEST_FORCE_EN (1<<2) +#define TEST_K (1<<1) +#define TEST_J (1<<0) + +/* Bit definition for PORT_STATUS register */ +#define PORT_TEST (1<<11) +#define PORT_SPD_MASK (3<<9) +#define PORT_HIGH_SPD (1<<10) +#define PORT_LOW_SPD (1<<9) +#define PORT_FULL_SPD (0<<9) +#define PORT_SLP (1<<5) +#define PORT_RESETTING (1<<4) +#define PORT_OVC (1<<3) +#define PORT_SUSP (1<<2) +#define PORT_EN (1<<1) +#define PORT_CONNECT (1<<0) + +/* Bit definition for PORT_STATUS_CHG register */ +#define PORT_SLP_IF (1<<5) +#define PORT_RESET_IF (1<<4) +#define PORT_SUSP_IF (1<<2) +#define PORT_EN_IF (1<<1) +#define PORT_CONNECT_IF (1<<0) + +/* Bit definition for ROOT_BC_CR register */ +#define UDM_VSRC_ACT (1<<10) +#define UDM_BC_CMPE (1<<9) +#define UDP_BC_CMPE (1<<8) +#define BC_AUTO_MODE (1<<6) +#define UDM_BC_VSRC (1<<5) +#define UDP_BC_VSRC (1<<4) +#define UDM_BC_CMPO (1<<1) +#define UDP_BC_CMPO (1<<0) + +/* Bit definition for HSI_CAL_CR register */ +#define CLK_SEL (1<<21) +#define SOF_FREE (1<<3) +#define SFT_RST (1<<2) +#define CAL_EN (1<<1) +#define CAL_RST (1<<0) + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_usbpd.h b/Peripheral/inc/ch564_usbpd.h new file mode 100644 index 0000000..1b3c10a --- /dev/null +++ b/Peripheral/inc/ch564_usbpd.h @@ -0,0 +1,321 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_usbpd.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * USBPD firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_USBPD_H +#define __CH564_USBPD_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +/* Register Bit Definition */ +/* USBPD->CONFIG */ +#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ +#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ +#define CC_SEL (1<<2) /* Select PD communication port */ +#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ +#define PD_RST_EN (1<<4) /* PD mode reset command enable */ +#define WAKE_POLAR (1<<5) /* PD port wake-up level */ +#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ +#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ +#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ +#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ +#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ +#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ + +/* USBPD->CONTROL */ +#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ +#define BMC_START (1<<1) /* BMC send start signal */ +#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ +#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ +#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ +#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ +#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ +#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ + +/* USBPD->TX_SEL */ +#define TX_SEL1 (0<<0) +#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ +#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ +#define TX_SEL2_Mask (3<<2) +#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ +#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ +#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ +#define TX_SEL3_Mask (3<<4) +#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ +#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ +#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ +#define TX_SEL4_Mask (3<<6) +#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ +#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ +#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ + +/* USBPD->STATUS */ +#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ +#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ +#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ +#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ +#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ +#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ +#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ +#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ +#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ +#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ +#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ + +/* USBPD->PORT_CC1 */ +/* USBPD->PORT_CC2 */ +#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ +#define CC_PD (1<<1) /* CC port pull-down resistor enable */ +#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ +#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ +#define CC_PU_330 (1<<2) /* 01-330uA */ +#define CC_PU_180 (2<<2) /* 10-180uA */ +#define CC_PU_80 (3<<2) /* 11-80uA */ +#define CC_LVE (1<<4) /* CC port output low voltage enable */ +#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ +#define CC_NO_CMP (0<<5) /* 000-closed */ +#define CC_CMP_22 (2<<5) /* 010-0.22V */ +#define CC_CMP_45 (3<<5) /* 011-0.45V */ +#define CC_CMP_55 (4<<5) /* 100-0.55V */ +#define CC_CMP_66 (5<<5) /* 101-0.66V */ +#define CC_CMP_95 (6<<5) /* 110-0.95V */ +#define CC_CMP_123 (7<<5) /* 111-1.23V */ + +/********************************************************* + * PD pin PC14/PC15 high threshold input mode: + * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication + * 0-Normal GPIO threshold input + * *******************************************************/ +#define USBPD_PHY_V33 (1<<8) +/********************************************************** +* PD transceiver PHY pull-up limit configuration bits: +* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V +* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V +* ********************************************************/ + +/* Control Message Types */ +#define DEF_TYPE_RESERVED 0x00 +#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ +#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_PING 0x05 /* Send By: Source */ +#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ +#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ +#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ +#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ +#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ +#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ +#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ +#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ +#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ +#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ +#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ +#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ + +/* Data Message Types */ +#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ +#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ +#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ +#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ +#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ +#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ +#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ +#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ +#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ +#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ +#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ +#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ +#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ + +/* Vendor Define Message Command */ +#define DEF_VDM_DISC_IDENT 0x01 +#define DEF_VDM_DISC_SVID 0x02 +#define DEF_VDM_DISC_MODE 0x03 +#define DEF_VDM_ENTER_MODE 0x04 +#define DEF_VDM_EXIT_MODE 0x05 +#define DEF_VDM_ATTENTION 0x06 +#define DEF_VDM_DP_S_UPDATE 0x10 +#define DEF_VDM_DP_CONFIG 0x11 + +/* PD Revision */ +#define DEF_PD_REVISION_10 0x00 +#define DEF_PD_REVISION_20 0x01 +#define DEF_PD_REVISION_30 0x02 + + +/* PD PHY Channel */ +#define DEF_PD_CC1 0x00 +#define DEF_PD_CC2 0x01 + +#define PIN_CC1 GPIO_Pin_18 +#define PIN_CC2 GPIO_Pin_19 + +/* PD Tx Status */ +#define DEF_PD_TX_OK 0x00 +#define DEF_PD_TX_FAIL 0x01 + +/* PDO INDEX */ +#define PDO_INDEX_1 1 +#define PDO_INDEX_2 2 +#define PDO_INDEX_3 3 +#define PDO_INDEX_4 4 +#define PDO_INDEX_5 5 + +/******************************************************************************/ + +#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ +#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ +#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ +#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ +#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ +#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ + +#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ +#define PD_RX_SOP0 0x01 /* SOP0 received */ +#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ +#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ + +#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ +#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ +#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ +#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ +#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ + + +#define bCC_CMP_22 0X01 +#define bCC_CMP_45 0X02 +#define bCC_CMP_55 0X04 +#define bCC_CMP_66 0X08 +#define bCC_CMP_95 0X10 +#define bCC_CMP_123 0X20 +#define bCC_CMP_220 0X40 + +/******************************************************************************/ +/* PD State Machine */ +typedef enum +{ + STA_IDLE = 0, /* 0: No task status */ + STA_DISCONNECT, /* 1: Disconnection */ + STA_SRC_CONNECT, /* 2: SRC connect */ + STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ + STA_RX_SRC_CAP, /* 4: SRC_CAP received */ + STA_TX_REQ, /* 5: Send REQUEST */ + STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ + STA_RX_ACCEPT, /* 7: ACCEPT received */ + STA_RX_REJECT, /* 8: REJECT received */ + STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ + STA_RX_PS_RDY, /* 10: PS_RDY received */ + STA_SINK_CONNECT, /* 11: SNK access */ + STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ + STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ + STA_RX_REQ, /* 14: REQUEST received */ + STA_TX_ACCEPT, /* 15: Send ACCEPT */ + STA_TX_REJECT, /* 16: Send REJECT */ + STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ + STA_TX_PS_RDY, /* 18: Send PS_RDY */ + STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ + STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ + STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ + STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ + STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ + STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ + STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ + STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ + STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ + STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ + STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ + STA_MODE_SWITCH, /* 30: Mode switching */ + STA_TX_SOFTRST, /* 31: Sending a software reset */ + STA_TX_HRST, /* 32: Send hardware reset */ + STA_PHY_RST, /* 33: PHY reset */ + STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ +} CC_STATUS; + +/******************************************************************************/ +/* PD Message Header Struct */ +typedef union +{ + struct _Message_Header + { + UINT8 MsgType: 5; /* Message Type */ + UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ + UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ + UINT8 PRRole: 1; /* 0-Sink; 1-Source */ + UINT8 MsgID: 3; + UINT8 NumDO: 3; + UINT8 Ext: 1; + }Message_Header; + UINT16 Data; +}_Message_Header; + +/******************************************************************************/ +/* Bit definition */ +typedef union +{ + struct _BITS_ + { + UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ + UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ + UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ + UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ + UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ + UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ + UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ + UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ + UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ + UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ + UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ + UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ + UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ + UINT8 Recv: 3; + }Bit; + UINT16 Bit_Flag; +}_BIT_FLAG; + +/* PD control-related structures */ +typedef struct _PD_CONTROL +{ + CC_STATUS PD_State; /* PD communication status machine */ + CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ + UINT8 Msg_ID; /* ID of the message sent */ + UINT8 Det_Timer; /* PD connection status detection timing */ + UINT8 Det_Cnt; /* Number of PD connection status detections */ + UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ + UINT8 HPD_Det_Timer; /* HPD connection detection timing */ + UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ + UINT16 PD_Comm_Timer; /* PD shared timing variables */ + UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ + UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ + UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ + UINT8 Err_Op_Cnt; /* Exception operation count */ + UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ + _BIT_FLAG Flag; /* Flag byte bit definition */ +}PD_CONTROL, *pPD_CONTROL; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch564_xbus.h b/Peripheral/inc/ch564_xbus.h new file mode 100644 index 0000000..7b6ccc7 --- /dev/null +++ b/Peripheral/inc/ch564_xbus.h @@ -0,0 +1,46 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_xbus.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file contains all the functions prototypes for the + * XBUS firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH564_XBUS_H +#define __CH564_XBUS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ch564.h" + +typedef enum +{ + NoOutput = 0x0, + AddrNum_6bit, + AddrNum_12bit, + AddrNum_ALL +} XbusOutputADDrBit; + +typedef enum +{ + Setuptime_1clk, + Setuptime_2clk, +} XbusSetupTime; + +#define SET_XBUS_CYCLE(val) (R8_XBUS_CYCLE = XBUS_CYCLE_VALUE_MASK & (val)) + +void XbusInit(XbusOutputADDrBit AddrBit, FunctionalState Bit32En, FunctionalState Stat); +void XbusHoldInit(XbusSetupTime setuptm, uint8_t holdtm); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/src/ch564_adc.c b/Peripheral/src/ch564_adc.c new file mode 100644 index 0000000..52165dc --- /dev/null +++ b/Peripheral/src/ch564_adc.c @@ -0,0 +1,37 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the ADC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_adc.h" + +/********************************************************************* + * @fn ADC_SelectChannel + * + * @brief The function sets the ADC channel for conversion. + * + * @param adcChannel The adcChannel parameter is of type ADCChannelTypedef, which is likely an + * enumeration or a typedef for an integer value representing the desired ADC channel. + * + * @return none + */ +void ADC_SelectChannel(ADCChannelTypedef adcChannel) +{ + if (adcChannel <= ADC_Channel0_1) + { + R32_ADC_CTRL &= ~MASK_ADC_CTL_MOD1; + R8_ADC_CTRL_MOD &= ~RB_ADC_CHAN_MOD; + R8_ADC_CTRL_MOD |= adcChannel << 4; + } + else + { + R32_ADC_CTRL &= ~MASK_ADC_CTL_MOD1; + R32_ADC_CTRL |= adcChannel - 1; + } +} diff --git a/Peripheral/src/ch564_eth.c b/Peripheral/src/ch564_eth.c new file mode 100644 index 0000000..6e49ed2 --- /dev/null +++ b/Peripheral/src/ch564_eth.c @@ -0,0 +1,2487 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch564_eth.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/05 +* Description : This file provides all the ETH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch564_eth.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; +} + +/********************************************************************* + * @fn ETH_Start + * + * @brief Enables ENET MAC and DMA reception/transmission. + * + * @return none + */ +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_MACReceptionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +/********************************************************************* + * @fn ETH_HandleTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * + * @param ppkt - pointer to the application's packet buffer to transmit. + * FrameLength - Tx Packet size. + * + * @return ETH_ERROR - in case of Tx desc owned by DMA. + * ETH_SUCCESS - for correct transmission. + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandleRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt. + * + * @param ppkt - pointer to the application packet receive buffer. + * + * @return ETH_ERROR - if there is error in reception + * framelength - received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn ETH_GetRxPktSize + * + * @brief Get the size of received the received packet. + * + * @return framelength - received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + return frameLength; +} + +/********************************************************************* + * @fn ETH_DropRxPkt + * + * @brief Drop a Received packet. + * + * @return none + */ +void ETH_DropRxPkt(void) +{ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/********************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * + * @return ETH_ERROR - in case of timeout. + * MAC MIIDR register value - Data read from the selected PHY register. + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg &= ~ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + return (uint16_t)(ETH->MACMIIDR); +} + +/********************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write to a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * PHYValue - the value to write. + * + * @return ETH_ERROR - in case of timeout. + * ETH_SUCCESS - for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg |= ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIDR = PHYValue; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + + if(timeout >= PHY_WRITE_TO) + { + return ETH_ERROR; + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_PHYLoopBackCmd + * + * @brief Enables or disables the PHY loopBack mode. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * NewState - new state of the PHY loopBack mode. + * + * @return ETH_ERROR - in case of bad PHY configuration. + * ETH_SUCCESS - for correct PHY configuration. + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if(NewState != DISABLE) + { + tmpreg |= PHY_Loopback; + } + else + { + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/********************************************************************* + * @fn ETH_MACTransmissionCmd + * + * @brief Enables or disables the MAC transmission. + * + * @param NewState - new state of the MAC transmission. + * + * @return none + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/********************************************************************* + * @fn ETH_MACReceptionCmd + * + * @brief Enables or disables the MAC reception. + * + * @param NewState - new state of the MAC reception. + * + * @return none + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/********************************************************************* + * @fn ETH_GetFlowControlBusyStatus + * + * @brief Enables or disables the MAC reception. + * + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_InitiatePauseControlFrame + * + * @brief Initiate a Pause Control Frame (Full-duplex only). + * + * @return none + */ +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/********************************************************************* + * @fn ETH_BackPressureActivationCmd + * + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * + * @param NewState - new state of the MAC BackPressure operation activation. + * + * @return none + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/********************************************************************* + * @fn ETH_GetMACFlagStatus + * + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * + * @param ETH_MAC_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMACITStatus + * + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_MACITConfig + * + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * NewState - new state of the specified ETHERNET MAC interrupts. + * + * @return none + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/********************************************************************* + * @fn ETH_MACAddressConfig + * + * @brief Configures the selected MAC address. + * + * @param MacAddr - The MAC addres to configure. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/********************************************************************* + * @fn ETH_GetMACAddress + * + * @brief Get the selected MAC address. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); + + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/********************************************************************* + * @fn ETH_MACAddressPerfectFilterCmd + * + * @brief Enables or disables the Address filter module uses the specified. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * NewState - new state of the specified ETHERNET MAC address use. + * + * @return none + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); + } +} + +/********************************************************************* + * @fn ETH_MACAddressFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Filter - specifies the used frame received field for comparaison. + * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the + * SA fields of the received frame. + * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the + * DA fields of the received frame. + * + * @return none + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + if(Filter != ETH_MAC_AddressFilter_DA) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); + } +} + +/********************************************************************* + * @fn ETH_MACAddressMaskBytesFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * MaskByte - specifies the used address bytes for comparaison + * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. + * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. + * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. + * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. + * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. + * + * @return none + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} + +/********************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list + * TxBuff - Pointer on the first TxBuffer list + * TxBuffCount - Number of the used Tx desc in the list + * + * @return none + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMATxDescRingInit + * + * @brief Initializes the DMA Tx descriptors in ring mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * TxBuff1 - Pointer on the first TxBuffer1 list. + * TxBuff2 - Pointer on the first TxBuffer2 list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (TxBuffCount - 1)) + { + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * ETH_DMATxDescFlag - specifies the flag to check. + * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine + * ETH_DMATxDesc_IC - Interrupt on completetion + * ETH_DMATxDesc_LS - Last Segment + * ETH_DMATxDesc_FS - First Segment + * ETH_DMATxDesc_DC - Disable CRC + * ETH_DMATxDesc_DP - Disable Pad + * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable + * ETH_DMATxDesc_TER - Transmit End of Ring + * ETH_DMATxDesc_TCH - Second Address Chained + * ETH_DMATxDesc_TTSS - Tx Time Stamp Status + * ETH_DMATxDesc_IHE - IP Header Error + * ETH_DMATxDesc_ES - Error summary + * ETH_DMATxDesc_JT - Jabber Timeout + * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush + * ETH_DMATxDesc_PCE - Payload Checksum Error + * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission + * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver + * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision + * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions + * ETH_DMATxDesc_VF - VLAN Frame + * ETH_DMATxDesc_CC - Collision Count + * ETH_DMATxDesc_ED - Excessive Deferral + * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory + * ETH_DMATxDesc_DB - Deferred Bit + * + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescCollisionCount + * + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * + * @param pointer on a DMA Tx descriptor. + * + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/********************************************************************* + * @fn ETH_SetDMATxDescOwnBit + * + * @brief Set the specified DMA Tx Desc Own bit. + * + * @param DMATxDesc - Pointer on a Tx desc + * + * @return none + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_DMATxDescTransmitITConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param Pointer on a Tx desc. + * NewState - new state of the DMA Tx Desc transmit interrupt. + * + * @return none + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescFrameSegmentConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param PDMATxDesc - Pointer on a Tx desc. + * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. + * + * @return none + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/********************************************************************* + * @fn ETH_DMATxDescChecksumInsertionConfig + * + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. + * + * @return none + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/********************************************************************* + * @fn ETH_DMATxDescCRCCmd + * + * @brief Enables or disables the DMA Tx Desc CRC. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc CRC. + * + * @return none + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Tx Desc end of ring. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc end of ring. + * + * @return none + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescSecondAddressChainedCmd + * + * @brief Enables or disables the DMA Tx Desc second address chained. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc second address chained. + * + * @return none + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescShortFramePaddingCmd + * + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @return none + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescTimeStampCmd + * + * @brief Enables or disables the DMA Tx Desc time stamp. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc time stamp. + * + * @return none + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescBufferSizeConfig + * + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc - Pointer on a Tx desc. + * BufferSize1 - specifies the Tx desc buffer1 size. + * RxBuff2 - Pointer on the first RxBuffer2 list + * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). + * + * @return none + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/********************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_DMARxDescRingInit + * + * @brief Initializes the DMA Rx descriptors in ring mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff1 - Pointer on the first RxBuffer1 list. + * RxBuff2 - Pointer on the first RxBuffer2 list + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (RxBuffCount - 1)) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * ETH_DMARxDescFlag - specifies the flag to check. + * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine + * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame + * ETH_DMARxDesc_ES - Error summary + * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame + * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame + * ETH_DMARxDesc_LE - Frame size not matching with length field + * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow + * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame + * ETH_DMARxDesc_FS - First descriptor of the frame + * ETH_DMARxDesc_LS - Last descriptor of the frame + * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * ETH_DMARxDesc_LC - Late collision occurred during reception + * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 + * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception + * ETH_DMARxDesc_RE - Receive error: error reported by MII interface + * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits + * ETH_DMARxDesc_CE - CRC error + * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetDMARxDescOwnBit + * + * @brief Set the specified DMA Rx Desc Own bit. + * + * @param DMARxDesc - Pointer on a Rx desc + * + * @return none + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFrameLength + * + * @brief Returns the specified DMA Rx Desc frame length. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor + * + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/********************************************************************* + * @fn ETH_DMARxDescReceiveITConfig + * + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * + * @param DMARxDesc - Pointer on a Rx desc + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/********************************************************************* + * @fn ETH_DMARxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Rx Desc end of ring. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc end of ring. + * + * @return none + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/********************************************************************* + * @fn ETH_DMARxDescSecondAddressChainedCmd + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc second address chained. + * + * @return none + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/********************************************************************* + * @fn ETH_GetDMARxDescBufferSize + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. + * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 + * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 + * + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/********************************************************************* + * @fn ETH_SoftwareReset + * + * @brief Resets all MAC subsystem internal registers and logic. + * + * @return none + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/********************************************************************* + * @fn ETH_GetSoftwareResetStatus + * + * @brief Checks whether the ETHERNET software reset bit is set or not. + * + * @return The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetlinkStaus + * + * @brief Checks whether the internal 10BASE-T PHY is link or not. + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetlinkStaus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) + { + bitstatus = PHY_10BASE_T_LINKED; + } + else + { + bitstatus = PHY_10BASE_T_NOT_LINKED; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMAFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * + * @param ETH_DMA_FLAG - specifies the flag to check. + * ETH_DMA_FLAG_TST - Time-stamp trigger flag + * ETH_DMA_FLAG_PMT - PMT flag + * ETH_DMA_FLAG_MMC - MMC flag + * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access + * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr + * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ET - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Underflow flag + * ETH_DMA_FLAG_RO - Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearFlag + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_FLAG - specifies the flag to clear. + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ETI - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Transmit Underflow flag + * ETH_DMA_FLAG_RO - Receive Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return none + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + ETH->DMASR = (uint32_t)ETH_DMA_FLAG; +} + +/********************************************************************* + * @fn ETH_GetDMAITStatus + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_TST - Time-stamp trigger interrupt + * ETH_DMA_IT_PMT - PMT interrupt + * ETH_DMA_IT_MMC - MMC interrupt + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clears the ETHERNET"s DMA IT pending bit. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ETI - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Transmit Underflow interrupt + * ETH_DMA_IT_RO - Receive Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return none + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + ETH->DMASR = (uint32_t)ETH_DMA_IT; +} + +/********************************************************************* + * @fn ETH_GetTransmitProcessState + * + * @brief Returns the ETHERNET DMA Transmit Process State. + * + * @return The new ETHERNET DMA Transmit Process State - + * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued + * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor + * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status + * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory + * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe + * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/********************************************************************* + * @fn ETH_GetReceiveProcessState + * + * @brief Returns the ETHERNET DMA Receive Process State. + * + * @return The new ETHERNET DMA Receive Process State: + * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued + * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor + * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet + * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable + * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor + * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/********************************************************************* + * @fn ETH_FlushTransmitFIFO + * + * @brief Clears the ETHERNET transmit FIFO. + * + * @return none + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/********************************************************************* + * @fn ETH_GetFlushTransmitFIFOStatus + * + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * + * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMATransmissionCmd + * + * @brief Enables or disables the DMA transmission. + * + * @param NewState - new state of the DMA transmission. + * + * @return none + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/********************************************************************* + * @fn ETH_DMAReceptionCmd + * + * @brief Enables or disables the DMA reception. + * + * @param NewState - new state of the DMA reception. + * + * @return none + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/********************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * + * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * NewState - new state of the specified ETHERNET DMA interrupts. + * + * @return new state of the specified ETHERNET DMA interrupts. + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); + } +} + +/********************************************************************* + * @fn ETH_GetDMAOverflowStatus + * + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * + * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetRxOverflowMissedFrameCounter + * + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/********************************************************************* + * @fn ETH_GetBufferUnavailableMissedFrameCounter + * + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHTDR register value. + * + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHRDR register value. + * + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return (DMATxDescToSet->Buffer1Addr); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/********************************************************************* + * @fn ETH_ResumeDMATransmission + * + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * + * @return none + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResumeDMAReception + * + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. + * + * @return none + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResetWakeUpFrameFilterRegisterPointer + * + * @brief Reset Wakeup frame filter register pointer. + * + * @return none + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/********************************************************************* + * @fn ETH_SetWakeUpFrameFilterRegister + * + * @brief Populates the remote wakeup frame registers. + * + * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * + * @return none + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->MACRWUFFR = Buffer[i]; + } +} + +/********************************************************************* + * @fn ETH_GlobalUnicastWakeUpCmd + * + * @brief Enables or disables any unicast packet filtered by the MAC address. + * + * @param NewState - new state of the MAC Global Unicast Wake-Up. + * + * @return none + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/********************************************************************* + * @fn ETH_GetPMTFlagStatus + * + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * + * @param ETH_PMT_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_WakeUpFrameDetectionCmd + * + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * + * @param NewState - new state of the MAC Wake-Up Frame Detection. + * + * @return none + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/********************************************************************* + * @fn ETH_MagicPacketDetectionCmd + * + * @brief Enables or disables the MAC Magic Packet Detection. + * + * @param NewState - new state of the MAC Magic Packet Detection. + * + * @return none + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/********************************************************************* + * @fn ETH_PowerDownCmd + * + * @brief Enables or disables the MAC Power Down. + * + * @param NewState - new state of the MAC Power Down. + * + * @return none + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterFreezeCmd + * + * @brief Enables or disables the MMC Counter Freeze. + * + * @param NewState - new state of the MMC Counter Freeze. + * + * @return none + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/********************************************************************* + * @fn ETH_MMCResetOnReadCmd + * + * @brief Enables or disables the MMC Reset On Read. + * + * @param NewState - new state of the MMC Reset On Read. + * + * @return none + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterRolloverCmd + * + * @brief Enables or disables the MMC Counter Stop Rollover. + * + * @param NewState - new state of the MMC Counter Stop Rollover. + * + * @return none + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/********************************************************************* + * @fn ETH_MMCCountersReset + * + * @brief Resets the MMC Counters. + * + * @return none + */ +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/********************************************************************* + * @fn ETH_MMCITConfig + * + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. + * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. + * NewState - new state of the specified ETHERNET MMC interrupts. + * + * @return none + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + ETH_MMC_IT &= 0xEFFFFFFF; + + if(NewState != DISABLE) + { + ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + if(NewState != DISABLE) + { + ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/********************************************************************* + * @fn ETH_GetMMCITStatus + * + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . + * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. + * + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMMCRegister + * + * @brief Get the specified ETHERNET MMC register value. + * + * @param ETH_MMCReg - specifies the ETHERNET MMC register. + * ETH_MMCCR - MMC CR register + * ETH_MMCRIR - MMC RIR register + * ETH_MMCTIR - MMC TIR register + * ETH_MMCRIMR - MMC RIMR register + * ETH_MMCTIMR - MMC TIMR register + * ETH_MMCTGFSCCR - MMC TGFSCCR register + * ETH_MMCTGFMSCCR - MMC TGFMSCCR register + * ETH_MMCTGFCR - MMC TGFCR register + * ETH_MMCRFCECR - MMC RFCECR register + * ETH_MMCRFAECR - MMC RFAECR register + * ETH_MMCRGUFCR - MMC RGUFCRregister + * + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampAddend + * + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampInterruptTrigger + * + * @brief Enable the PTP Time Stamp interrupt trigger + * + * @return none + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampUpdate + * + * @brief Updated the PTP system time with the Time Stamp Update register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/********************************************************************* + * @fn ETH_InitializePTPTimeStamp + * + * @brief Initialize the PTP Time Stamp. + * + * @return none + */ +void ETH_InitializePTPTimeStamp(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/********************************************************************* + * @fn ETH_PTPUpdateMethodConfig + * + * @brief Selects the PTP Update method. + * + * @param UpdateMethod - the PTP Update method. + * + * @return none + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + if(UpdateMethod != ETH_PTP_CoarseUpdate) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/********************************************************************* + * @fn ETH_PTPTimeStampCmd + * + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * + * @param NewState - new state of the PTP time stamp for transmit and receive frames. + * + * @return none + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/********************************************************************* + * @fn ETH_GetPTPFlagStatus + * + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * + * @param The new state of ETHERNET PTP Flag (SET or RESET). + * + * @return none + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetPTPSubSecondIncrement + * + * @brief Sets the system time Sub-Second Increment value. + * + * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. + * + * @return none + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + ETH->PTPSSIR = SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampUpdate + * + * @brief Sets the Time Stamp update sign and values. + * + * @param Sign - specifies the PTP Time update value sign. + * SecondValue - specifies the PTP Time update second value. + * SubSecondValue - specifies the PTP Time update sub-second value. + * + * @return none + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + ETH->PTPTSHUR = SecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampAddend + * + * @brief Sets the Time Stamp Addend value. + * + * @param Value - specifies the PTP Time Stamp Addend Register value. + * + * @return none + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/********************************************************************* + * @fn ETH_SetPTPTargetTime + * + * @brief Sets the Target Time registers values. + * + * @param HighValue - specifies the PTP Target Time High Register value. + * LowValue - specifies the PTP Target Time Low Register value. + * + * @return none + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + ETH->PTPTTHR = HighValue; + ETH->PTPTTLR = LowValue; +} + +/********************************************************************* + * @fn ETH_GetPTPRegister + * + * @brief Get the specified ETHERNET PTP register value. + * + * @param ETH_PTPReg - specifies the ETHERNET PTP register. + * ETH_PTPTSCR - Sub-Second Increment Register + * ETH_PTPSSIR - Sub-Second Increment Register + * ETH_PTPTSHR - Time Stamp High Register + * ETH_PTPTSLR - Time Stamp Low Register + * ETH_PTPTSHUR - Time Stamp High Update Register + * ETH_PTPTSLUR - Time Stamp Low Update Register + * ETH_PTPTSAR - Time Stamp Addend Register + * ETH_PTPTTHR - Target Time High Register + * ETH_PTPTTLR - Target Time Low Register + * + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/********************************************************************* + * @fn ETH_DMAPTPTxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. + * TxBuff - Pointer on the first TxBuffer list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMAPTPRxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_HandlePTPTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet buffer to transmit. + * FrameLength - Tx Packet size. + * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. + * + * @return none. + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + do + { + timeout++; + } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandlePTPRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet receive buffer. + * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. + * + * @return ETH_ERROR - if there is error in reception. + * framelength - received packet size if packet reception is correct. + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief Delay time. + * + * @return none + */ +void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) +{ + if(clock_polarity) + { + ETH->MACCR |= (uint32_t)(1 << 1); + } + else + { + ETH->MACCR &= ~(uint32_t)(1 << 1); + } + if(delay_time <= 7) + { + ETH->MACCR |= (uint32_t)(delay_time << 29); + } +} + diff --git a/Peripheral/src/ch564_gpio.c b/Peripheral/src/ch564_gpio.c new file mode 100644 index 0000000..dfe6982 --- /dev/null +++ b/Peripheral/src/ch564_gpio.c @@ -0,0 +1,409 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_gpio.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_gpio.h" +#include "ISP564.h" + +/******************************************************************************* + * @fn GPIOA_ModeCfg + * + * @brief GPIOA port pin mode configuration + * + * @param pin - PA0-PA15 + * GPIO_Pin_0 - GPIO_Pin_15 + * mode - + * GPIO_ModeIN_Floating - Floating input/high impedance input + * GPIO_ModeIN_PU - input with pull-up resistor + * GPIO_ModeIN_PD - input with pull-down resistor + * GPIO_ModeOut_OP - Drain output + * GPIO_ModeOut_PP - Push-pull output + * + * @return none + */ + +void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode) +{ + + switch (mode) + { + case GPIO_ModeIN_Floating: + R32_PA_PD &= ~pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU: + R32_PA_PD &= ~pin; + R32_PA_PU |= pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD: + R32_PA_PD |= pin; + R32_PA_PU &= ~pin; + R32_PA_DIR &= ~pin; + break; + + case GPIO_ModeOut_OP: + R32_PA_PD |= pin; + R32_PA_DIR |= pin; + break; + + case GPIO_ModeOut_PP: + R32_PA_DIR |= pin; + R32_PA_PU &= ~pin; + R32_PA_PD &= ~pin; + break; + + default: + break; + } +} + +/******************************************************************************* + * @fn GPIOB_ModeCfg + * + * @brief GPIOB port pin mode configuration + * + * @param pin - PB0-PB15 + * GPIO_Pin_0 - GPIO_Pin_15 + * mode - + * GPIO_ModeIN_Floating - Floating input/high impedance input + * GPIO_ModeIN_PU - input with pull-up resistor + * GPIO_ModeIN_PD - input with pull-down resistor + * GPIO_ModeOut_OP - Drain output + * GPIO_ModeOut_PP - Push-pull output + * + * @return none + */ + +void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode) +{ + switch (mode) + { + case GPIO_ModeIN_Floating: + R32_PB_PD &= ~pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU: + R32_PB_PD &= ~pin; + R32_PB_PU |= pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD: + R32_PB_PD |= pin; + R32_PB_PU &= ~pin; + R32_PB_DIR &= ~pin; + break; + + case GPIO_ModeOut_OP: + R32_PB_PD |= pin; + R32_PB_DIR |= pin; + break; + + case GPIO_ModeOut_PP: + R32_PB_DIR |= pin; + R32_PB_PU &= ~pin; + R32_PB_PD &= ~pin; + break; + + default: + break; + } +} + +/******************************************************************************* + * @fn GPIOD_ModeCfg + * + * @brief GPIOD port pin mode configuration + * + * @param pin - PD0-PD15 + * GPIO_Pin_0 - GPIO_Pin_15 + * mode - + * GPIO_ModeIN_Floating - Floating input/high impedance input + * GPIO_ModeIN_PU - input with pull-up resistor + * GPIO_ModeIN_PD - input with pull-down resistor + * GPIO_ModeOut_OP - Drain output + * GPIO_ModeOut_PP - Push-pull output + * + * @return none + */ + +void GPIOD_ModeCfg(uint32_t pin, GPIOModeTypeDef mode) +{ + switch (mode) + { + case GPIO_ModeIN_Floating: + R32_PD_PD &= ~pin; + R32_PD_PU &= ~pin; + R32_PD_DIR &= ~pin; + break; + + case GPIO_ModeIN_PU: + R32_PD_PD &= ~pin; + R32_PD_PU |= pin; + R32_PD_DIR &= ~pin; + break; + + case GPIO_ModeIN_PD: + R32_PD_PD |= pin; + R32_PD_PU &= ~pin; + R32_PD_DIR &= ~pin; + break; + + case GPIO_ModeOut_OP: + R32_PD_PD |= pin; + R32_PD_DIR |= pin; + break; + + case GPIO_ModeOut_PP: + R32_PD_DIR |= pin; + R32_PD_PU &= ~pin; + R32_PD_PD &= ~pin; + break; + + default: + break; + } +} + +/******************************************************************************* + * @fn GPIOA_ITModeCfg + * + * @brief GPIOA pin interrupt mode configuration + * + * @param pin - PAx + * mode - + * GPIO_ITMode_LowLevel - Low level trigger + * GPIO_ITMode_HighLevel - High level trigger + * GPIO_ITMode_FallEdge - Falling edge trigger + * GPIO_ITMode_RiseEdge - Rising edge trigger + * + * @return none + */ +void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode) +{ + switch (mode) + { + case GPIO_ITMode_FallEdge: + R32_INT_MODE_PA |= pin; + R32_INT_POLAR_PA &= ~pin; + R32_INT_ENABLE_PA |= pin; + break; + + case GPIO_ITMode_RiseEdge: + R32_INT_MODE_PA |= pin; + R32_INT_POLAR_PA |= pin; + R32_INT_ENABLE_PA |= pin; + break; + + case GPIO_ITMode_HighLevel: + R32_INT_MODE_PA &= ~pin; + R32_INT_POLAR_PA |= pin; + R32_INT_ENABLE_PA |= pin; + break; + + case GPIO_ITMode_LowLevel: + R32_INT_MODE_PA &= ~pin; + R32_INT_POLAR_PA &= ~pin; + R32_INT_ENABLE_PA |= pin; + break; + + case GPIO_ITMode_None: + R32_INT_ENABLE_PA |= pin; + R32_INT_ENABLE_PA &= ~pin; + break; + + default: + break; + } + R32_INT_STATUS_PA = pin; +} + +/******************************************************************************* + * @fn GPIOB_ITModeCfg + * + * @brief GPIOB pin interrupt mode configuration + * + * @param pin - PBx + * mode - + * GPIO_ITMode_LowLevel - Low level trigger + * GPIO_ITMode_HighLevel - High level trigger + * GPIO_ITMode_FallEdge - Falling edge trigger + * GPIO_ITMode_RiseEdge - Rising edge trigger + * + * @return none + */ +void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode) +{ + switch (mode) + { + case GPIO_ITMode_FallEdge: + R32_INT_MODE_PB |= pin; + R32_INT_POLAR_PB &= ~pin; + R32_INT_ENABLE_PB |= pin; + break; + + case GPIO_ITMode_RiseEdge: + R32_INT_MODE_PB |= pin; + R32_INT_POLAR_PB |= pin; + R32_INT_ENABLE_PB |= pin; + break; + + case GPIO_ITMode_HighLevel: + R32_INT_MODE_PB &= ~pin; + R32_INT_POLAR_PB |= pin; + R32_INT_ENABLE_PB |= pin; + break; + + case GPIO_ITMode_LowLevel: + R32_INT_MODE_PB &= ~pin; + R32_INT_POLAR_PB &= ~pin; + R32_INT_ENABLE_PB |= pin; + break; + + case GPIO_ITMode_None: + R32_INT_ENABLE_PB |= pin; + R32_INT_ENABLE_PB &= ~pin; + break; + + default: + break; + } + R32_INT_STATUS_PB = pin; +} + +/******************************************************************************* + * @fn GPIOD_ITModeCfg + * + * @brief GPIOD pin interrupt mode configuration + * + * @param pin - PDx + * mode - + * GPIO_ITMode_LowLevel - Low level trigger + * GPIO_ITMode_HighLevel - High level trigger + * GPIO_ITMode_FallEdge - Falling edge trigger + * GPIO_ITMode_RiseEdge - Rising edge trigger + * + * @return none + */ +void GPIOD_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode) +{ + switch (mode) + { + case GPIO_ITMode_FallEdge: + R32_INT_MODE_PD |= pin; + R32_INT_POLAR_PD &= ~pin; + R32_INT_ENABLE_PD |= pin; + break; + + case GPIO_ITMode_RiseEdge: + R32_INT_MODE_PD |= pin; + R32_INT_POLAR_PD |= pin; + R32_INT_ENABLE_PD |= pin; + break; + + case GPIO_ITMode_HighLevel: + R32_INT_MODE_PD &= ~pin; + R32_INT_POLAR_PD |= pin; + R32_INT_ENABLE_PD |= pin; + break; + + case GPIO_ITMode_LowLevel: + R32_INT_MODE_PD &= ~pin; + R32_INT_POLAR_PD &= ~pin; + R32_INT_ENABLE_PD |= pin; + break; + + case GPIO_ITMode_None: + R32_INT_ENABLE_PD |= pin; + R32_INT_ENABLE_PD &= ~pin; + break; + + default: + break; + } + R32_INT_STATUS_PD = pin; +} + +/******************************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Remap GPIO function + * + * @param GPIO_Remap - GPIO_Remap_x + * NewSTA - ENABLE + * - DISABLE + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewSTA) +{ + uint32_t tempr = R32_AFIO_PCFR1; + /*GPIO_Remap fomat: + bit[31]: Choose register R32_AFIO_PCFR1(0x0) or R32_AFIO_PCFR2(0x80000000) to be write + bit[24:20]: Position of bits low anchor + bit[19:16]: Size of bits + bit[15:0]: Specific value of remap + */ + if (GPIO_Remap & 0x80000000) + { + tempr = R32_AFIO_PCFR2; + } + /*Clear bits*/ + tempr &= ~((~(0xffffffff << ((GPIO_Remap >> 16) & 0xf))) << ((GPIO_Remap >> 20) & 0x1f)); + /*Write bits*/ + if (NewSTA == ENABLE) + { + tempr |= (GPIO_Remap & (~(0xffffffff << ((GPIO_Remap >> 16) & 0xf)))) << ((GPIO_Remap >> 20) & 0x1f); + } + if (GPIO_Remap & 0x80000000) + R32_AFIO_PCFR2 = tempr; + else + R32_AFIO_PCFR1 = tempr; +} + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + uint32_t ChipID; + GetCHIPID(&ChipID); + switch (ChipID & 0xffffff0f) + { + case 0x56410508: + GPIOD_ModeCfg(0xFFFFFFFF, GPIO_ModeIN_PD); + GPIOB_ModeCfg(GPIO_Pin_22, GPIO_ModeIN_PD); + GPIOA_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_7 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_17 | + GPIO_Pin_18 | GPIO_Pin_19), + GPIO_ModeIN_PD); + break; + + case 0x56430508: + GPIOD_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_20), GPIO_ModeIN_PD); + GPIOB_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_6 | GPIO_Pin_17 | GPIO_Pin_18 | GPIO_Pin_19 | 0xFF00), GPIO_ModeIN_PD); + GPIOA_ModeCfg(0xFFFFFFFF ^ (GPIO_Pin_7 | GPIO_Pin_12 | GPIO_Pin_11), GPIO_ModeIN_PD); + break; + + default: + break; + } +} diff --git a/Peripheral/src/ch564_i2c.c b/Peripheral/src/ch564_i2c.c new file mode 100644 index 0000000..ef07d8e --- /dev/null +++ b/Peripheral/src/ch564_i2c.c @@ -0,0 +1,930 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_i2c.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the I2C firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_i2c.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_Typedef *I2Cx) +{ + if (I2Cx == I2C) + { + R8_SLP_CLK_OFF1 &= ~RB_SLP_CLK_I2C; + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_Typedef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + pclk1 = SystemCoreClock; + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if (result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + } + else + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if ((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_Typedef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_Typedef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_Typedef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_Typedef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_Typedef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if (I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_Typedef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * + * @return none + */ +void I2C_NACKPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_NACKPosition) +{ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_PECPosition) +{ + if (I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_Typedef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_Typedef *I2Cx, FunctionalState NewState) +{ + if (NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_Typedef *I2Cx, uint16_t I2C_DutyCycle) +{ + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EV4. + * I2C_EVENT_MASTER_MODE_SELECT - EV5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EV7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9. + * + * @return none + */ +ErrorStatus I2C_CheckEvent(I2C_Typedef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_Typedef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return none + */ +FlagStatus I2C_GetFlagStatus(I2C_Typedef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if (i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if (((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * + * @return none + */ +void I2C_ClearFlag(I2C_Typedef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_Typedef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if (((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_Typedef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/Peripheral/src/ch564_pwr.c b/Peripheral/src/ch564_pwr.c new file mode 100644 index 0000000..c8fa397 --- /dev/null +++ b/Peripheral/src/ch564_pwr.c @@ -0,0 +1,45 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_pwr.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the PWR firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_pwr.h" + +/******************************************************************************* + * @fn LowPower_Idle + * + * @brief Low power consumption - Idle mode + * + * @return none + */ +void PWR_Sleep(uint8_t PWR_STOPEntry) +{ + PFIC->SCTLR &= ~(1 << 2); // Set the SleepDeep field of the core PFIC SCTLR register to 0 + if (PWR_STOPEntry == PWR_STOPEntry_WFE){ + __WFE(); // Execute __WFE() after setting the wake-up condition + } + else + __WFI(); // Execute __WFI() after setting the wake-up condition +} + +/******************************************************************************* + * @fn LowPower_Halt + * + * @brief Low power consumption - Halt mode + * + * @return none + */ +void PWR_DeepSleep(uint8_t PWR_STOPEntry) +{ + PFIC->SCTLR |= 1 << 2; // Set the SleepDeep field of the core PFIC SCTLR register to 1 + if (PWR_STOPEntry == PWR_STOPEntry_WFE) + __WFE(); // Execute __WFE() after setting the wake-up condition + else + __WFI(); // Execute __WFI() after setting the wake-up condition +} diff --git a/Peripheral/src/ch564_rcc.c b/Peripheral/src/ch564_rcc.c new file mode 100644 index 0000000..9cfd54b --- /dev/null +++ b/Peripheral/src/ch564_rcc.c @@ -0,0 +1,142 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the RCC firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_rcc.h" + +/********************************************************************* + * @fn RCC_SetGlobleMem + * + * @brief Config the different memory assignment + * + * @param Cfg - Three choice of memory assignment + * Code16k_Data128k - assign 16k memory for code 128k memory for data + * Code48k_Data96k - assign 48k memory for code 96k memory for data + * Code80k_Data64k - assign 80k memory for code 64k memory for data + * + * @return none + */ +void RCC_SetGlobalMemCFG(GlobMem_Cfg Cfg) +{ + RCC_UNLOCK_SAFE_ACCESS(); + R8_GLOB_MEM_CFG = Cfg; + RCC_LOCK_SAFE_ACCESS(); +} + +/********************************************************************* + * @fn RCC_LockPort + * + * @brief Choose a port and decide whether lock or not + * + * @param globport - choose port + * - RB_GLOB_LOCK_PA + * - RB_GLOB_LOCK_PB + * - RB_GLOB_LOCK_PD + * NewSTA - Enable or disable + * - ENABLE + * - DISABLE + * @return none + */ +void RCC_LockPort(uint8_t globport, FunctionalState NewSTA) +{ + uint8_t temp = R8_GLOB_LOCK_PORT; + NewSTA == ENABLE ? (temp |= globport) : (temp &= ~globport); + R8_GLOB_LOCK_PORT = 0x3f & temp; +} + +/********************************************************************* + * @fn RCC_GlobleRstCFG + * + * @brief Choose Reset function + * + * @param globrst - choose port + * - RB_GLOB_FORCE_RST + * - RB_GLOB_WDOG_EN + * NewSTA - Enable or disable + * - ENABLE + * - DISABLE + * @return none + */ +void RCC_GlobleRstCFG(uint8_t globrst, FunctionalState NewSTA) +{ + uint8_t temp = R8_GLOB_RST_CFG; + NewSTA == ENABLE ? (temp = 0x40 | globrst) : (temp = (0x0F & (~globrst))|0x40); + RCC_UNLOCK_SAFE_ACCESS(); + R8_GLOB_RST_CFG = temp; + RCC_LOCK_SAFE_ACCESS(); +} + +/********************************************************************* + * @fn RCC_SlpClkOff + * + * @brief Choose peripherals' clock to be on or off + * + * @param reg - register pointer to write + * - R8_SLP_CLK_OFF0 + * - R8_SLP_CLK_OFF1 + * - R8_SLP_CTRL_PLL + * slpclk - choose periph clock + * - RB_SLP_CLK_TMR0 + * - RB_SLP_CLK_TMR1 + * - RB_SLP_CLK_TMR2 + * - RB_SLP_CLK_TMR3 + * - RB_SLP_CLK_SPI0 + * - RB_SLP_CLK_SPI1 + * - RB_SLP_CLK_UART0 + * - RB_SLP_CLK_UART1 + * + * - RB_SLP_CLK_UTMI + * - RB_SLP_CLK_I2C + * - RB_SLP_CLK_UDP + * - RB_SLP_CLK_ADC + * - RB_SLP_CLK_GPIO + * - RB_SLP_CLK_USB + * - RB_SLP_CLK_ETH + * + * - RB_SLP_CTRL_PLL_UART2 + * - RB_SLP_CTRL_PLL_UART3 + * NewSTA - Enable or disable + * - ENABLE + * - DISABLE + * @return none + */ +void RCC_SlpClkOff(volatile uint8_t *reg, uint8_t slpclk, FunctionalState NewSTA) +{ + if (reg != &R8_SLP_CLK_OFF0 && reg != &R8_SLP_CLK_OFF1 && reg != &R8_SLP_CTRL_PLL) + return; + RCC_UNLOCK_SAFE_ACCESS(); + NewSTA == ENABLE ? (*reg |= slpclk) : (*reg &= ~slpclk); + RCC_LOCK_SAFE_ACCESS(); +} + +/********************************************************************* + * @fn RCC_SlpWakeCtrl + * + * @brief Choose Reset function + * + * @param slpwake - choose periph to wake the device + * - RB_SLP_PA_WAKE + * - RB_SLP_PB_WAKE + * - RB_SLP_PD_WAKE + * - RB_SLP_USB_WAKE + * - RB_SLP_AP_WAK_USB + * - RB_SLP_WOL_WAKE + * - RB_SLP_ETH_PWR_DN + * NewSTA - Enable or disable + * - ENABLE + * - DISABLE + * @return none + */ +void RCC_SlpWakeCtrl(uint8_t slpwake, FunctionalState NewSTA) +{ + RCC_UNLOCK_SAFE_ACCESS(); + NewSTA == ENABLE ? (R8_SLP_WAKE_CTRL |= slpwake) : (R8_SLP_WAKE_CTRL &= ~slpwake); + RCC_LOCK_SAFE_ACCESS(); +} diff --git a/Peripheral/src/ch564_slv.c b/Peripheral/src/ch564_slv.c new file mode 100644 index 0000000..c3d266a --- /dev/null +++ b/Peripheral/src/ch564_slv.c @@ -0,0 +1,129 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_slv.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the SLV firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_slv.h" + +/********************************************************************** + * @fn SLV_Read + * @brief The function SLV_Read reads data from a slave device with a specified data size and timeout. + * + * @param dataAddress A pointer to the memory location where the received data will be stored. + * dataSize The dataSize parameter represents the number of bytes to be read from the SLV + * (slave) device. + * timeout The "timeout" parameter is the maximum amount of time (in milliseconds) that the + * function will wait for data to be received before returning with a timeout error. + * + * @return a value of type SLV_STA. + * --slv_data data read right now is a data + * --slv_cmd data read right now is a command + * --slv_timeout read data timeout + */ +SLV_STA SLV_Read(uint8_t *dataAddress, uint16_t dataSize, uint16_t timeout) +{ + SLV_STA SLV_TYPE; + + SLV_TYPE = slv_data; + + while (dataSize--) + { + uint16_t t = timeout; + while (t--) + { + if (SLV_GET_IF(RB_IF_SLV_WR)) + { + if (SLV_GET_IF(RB_IF_SLV_CMD)) + SLV_TYPE = slv_cmd; + else + SLV_TYPE = slv_data; + } + + *(dataAddress++) = SLV_GET_DATA(); + } + if (t == 0) + { + SLV_TYPE = slv_timeout; + break; + } + } + + return SLV_TYPE; +} + +/********************************************************************** + * @fn SLV_SendDATA + * + * @brief The function SLV_SendDATA sends data over a communication interface and returns the status of the + * operation. + * + * @param data The "data" parameter is a pointer to an array of uint8_t (unsigned 8-bit integer) + * values. It represents the data that needs to be sent. + * datasize The parameter "datasize" is the size of the data array that is being sent. It + * represents the number of elements in the array. + * + * @return ErrorStatus value. If the timeout value reaches 0 before the condition "R8_INT_FLAG_SLV & + * RB_IF_SLV_RD" is true, the function will return NoREADY. Otherwise, it will return READY. + */ +ErrorStatus SLV_SendDATA(uint8_t *data, uint16_t datasize) +{ + uint16_t timeout; + + while (datasize--) + { + timeout = 100; + SLV_SEND_DATA(*(data++)); + while (timeout--) + { + if (SLV_GET_IF(RB_IF_SLV_RD)) + { + break; + } + } + if (timeout == 0) + { + return NoREADY; + } + } + return READY; +} + +/********************************************************************** + * @fn SLV_SendSTA + * + * @brief The function SLV_SendSTA sends a series of data bytes to a slave device and returns a status + * indicating if the operation was successful or not. + * + * @param sta A pointer to an array of uint8_t values that represent the data to be sent. + * datasize datasize is the number of bytes in the sta array that need to be sent. + * + * @return ErrorStatus. + */ +ErrorStatus SLV_SendSTA(uint8_t *sta, uint16_t datasize) +{ + uint16_t timeout; + + while (datasize--) + { + timeout = 100; + SLV_SEND_STA(*(sta++)); + while (timeout--) + { + if (SLV_GET_IF(RB_IF_SLV_RD)) + { + break; + } + } + if (timeout == 0) + { + return NoREADY; + } + } + return READY; +} diff --git a/Peripheral/src/ch564_spi.c b/Peripheral/src/ch564_spi.c new file mode 100644 index 0000000..d08c75d --- /dev/null +++ b/Peripheral/src/ch564_spi.c @@ -0,0 +1,678 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_spi.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the SPI firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_spi.h" +#include "debug.h" + +uint32_t spi_comm_tick = 0; +#define SPICOMM_TIMEOUT 10 + +static void delay() +{ + for (uint16_t i = 0; i < (SystemCoreClock / 1000000) * 1000; i++); +} + +/******************************************************************************* + * @fn SPI0_MasterDefInit + * + * @brief Host mode default initialization + * + * @return none + */ +void SPI0_MasterInit(uint32_t clockRate) +{ + SPI0_MODE_CFG(RB_SPI_MODE_SLAVE, DISABLE); + SPI0_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR | RB_SPI_FIFO_DIR, ENABLE); + SPI0_MODE_CFG(RB_SPI_MISO_OE | RB_SPI_ALL_CLEAR, DISABLE); + SPI0_SET_CLOCK_DIV((SystemCoreClock / clockRate) < 2 ? (2) : (SystemCoreClock / clockRate)); + SPI0_SET_DMA_MODE(0xff, DISABLE); +} + +/******************************************************************************* + * @fn SPI0_DataMode + * + * @brief Set data flow mode + * + * @param mode - data flow mode + * + * @return none + */ +void SPI0_DataMode(ModeBitOrderTypeDef mode) +{ + switch (mode) + { + case Mode0_HighBitINFront: // Mode 0, high bit first + SPI0_MODE_CFG(RB_SPI_MST_SCK_MOD, DISABLE); + break; + case Mode3_HighBitINFront: // Mode 3, high bit first + SPI0_MODE_CFG(RB_SPI_MST_SCK_MOD, ENABLE); + break; + default: + break; + } +} + +/******************************************************************************* + * @fn SPI0_MasterSendByte + * + * @brief Send a single byte (buffer) + * + * @param data - send bytes + * + * @return none + */ +void SPI0_MasterSendByte(uint8_t data) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); + SPI0_SET_TOTAL_CNT(1); + SPI0_SET_FIFO(data); + spi_comm_tick = SysTick_100us; + while (SPI0_GET_TOTAL_CNT() != 0) + { + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } +} + +/******************************************************************************* + * @fn SPI0_MasterRecvByte + * + * @brief Receive a single byte (buffer) + * + * @return bytes received + */ +uint8_t SPI0_MasterRecvByte(void) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); + SPI0_SET_TOTAL_CNT(1); + SPI0_SET_BUFFER(0xff); + spi_comm_tick = SysTick_100us; + while (!SPI0_GET_FIFO_CNT()) + { + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } + return (SPI0_GET_FIFO()); +} + +/******************************************************************************* + * @fn SPI0_MasterTrans + * + * @brief Continuously send multiple bytes using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + */ +void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI0_ClearITFlag(RB_SPI_IF_CNT_END); + spi_comm_tick = SysTick_100us; + while (sendlen) + { + if (SPI0_GET_FIFO_CNT() < SPI0_FIFO_SIZE) + { + SPI0_SET_FIFO(*pbuf); + pbuf++; + sendlen--; + } + + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } + spi_comm_tick = SysTick_100us; + while (SPI0_GET_TOTAL_CNT() != 0) // Wait for all the data in the FIFO to be sent + { + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } +} + +/******************************************************************************* + * @fn SPI0_MasterRecv + * + * @brief Receive multiple bytes continuously using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + **/ +void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len) +{ + uint16_t readlen; + + readlen = len; + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set data direction to input + SPI0_SET_TOTAL_CNT(len); // Set the length of the data to be received, the FIFO direction will start the + // transmission if the input length is not 0 + R8_SPI0_INT_FLAG = RB_SPI_IF_CNT_END; + SPI0_SET_BUFFER(0xff); + + spi_comm_tick = SysTick_100us; + while (readlen) + { + if (SPI0_GET_FIFO_CNT()) + { + *pbuf = SPI0_GET_FIFO(); + SPI0_SET_BUFFER(0xff); + pbuf++; + readlen--; + } + + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } +} + +/******************************************************************************* + * @fn SPI0_MasterTransRecv + * + * @brief Continuously send/receive multiple bytes + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + */ +void SPI0_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI0_ClearITFlag(RB_SPI_IF_CNT_END); + + spi_comm_tick = SysTick_100us; + while (sendlen) + { + if (SPI0_GET_FIFO_CNT() == 0) + { + SPI0_SET_FIFO(*ptbuf); + while (SPI0_GET_FIFO_CNT() != 0); + ptbuf++; + *prbuf = SPI0_GET_BUFFER(); + prbuf++; + sendlen--; + } + + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } + +} + +/******************************************************************************* + * @fn SPI0_DMATrans + * + * @brief Continuously send data in DMA mode + * + * @param pbuf: The starting address of the data to be sent + * + * @return none + */ +void SPI0_DMATrans(uint8_t *pbuf, uint32_t len) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); + + SPI0_SET_DMA_RANGE(pbuf, pbuf + len); + SPI0_SET_TOTAL_CNT(len); + SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, ENABLE); + spi_comm_tick = SysTick_100us; + while (SPI0_GET_TOTAL_CNT()) + { + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } + SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, DISABLE); + + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); +} + +/******************************************************************************* + * @fn SPI0_DMARecv + * + * @brief Receive data continuously in DMA mode + * + * @param pbuf: The starting address for storing the data to be received + * + * @return none + **/ +void SPI0_DMARecv(uint8_t *pbuf, uint32_t len) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); + SPI0_SET_DMA_RANGE(pbuf, pbuf + len); + SPI0_SET_TOTAL_CNT(len); + SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, ENABLE); + spi_comm_tick = SysTick_100us; + while (SPI0_GET_TOTAL_CNT()) + { + if(SysTick_100us - spi_comm_tick >= SPICOMM_TIMEOUT) break; + } + SPI0_SET_DMA_MODE(RB_SPI_DMA_ENABLE, DISABLE); +} + +/******************************************************************************* + * @fn SPI0_SlaveInit + * + * @brief Device mode default initialization + * + * @return none + */ +void SPI0_SlaveInit(uint32_t clockRate) +{ + SPI0_MODE_CFG(RB_SPI_MODE_SLAVE | RB_SPI_ALL_CLEAR, ENABLE); + SPI0_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_ALL_CLEAR | RB_SPI_SCK_OE, DISABLE); + SPI0_MODE_CFG(RB_SPI_MISO_OE, ENABLE); + + SPI0_SET_DMA_MODE(0xff, DISABLE); +} + +/******************************************************************************* + * @fn SPI0_SlaveRecvByte + * + * @brief Slave mode, receive one byte of data + * + * @return received data + */ +uint8_t SPI0_SlaveRecvByte(void) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data + while (!SPI0_GET_FIFO_CNT()); + return SPI0_GET_FIFO(); +} + +/******************************************************************************* + * @fn SPI0_SlaveRecvByte + * + * @brief Slave mode, send one byte of data + * + * @param data: data will be sent + * + * @return received data + **/ +void SPI0_SlaveSendByte(uint8_t data) +{ + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set to output mode, send data + SPI0_SET_FIFO(data); + SPI0_SET_TOTAL_CNT(1); + while (SPI0_GET_FIFO_CNT()); +} + +/******************************************************************************* + * @fn SPI0_SlaveRecv + * + * @brief Slave mode, receive multi-byte data + * + * @param pbuf: Receive data storage starting address + * + * @return 0/1 0 means receive failed,1 means receive success. + **/ +uint8_t SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len, uint16_t timeouts) +{ + uint16_t revlen; + + revlen = len; + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data + SPI0_SET_TOTAL_CNT(revlen); // Assign a value to the SPI send and receive data total length register + while (revlen && timeouts) + { + if (!(timeouts & SPI_MAX_DELAY)) + { + delay(); + timeouts--; + } + if (SPI0_GET_FIFO_CNT()) // Byte count in the current FIFO + { + *pbuf = SPI0_GET_FIFO(); + pbuf++; + revlen--; + } + } + if (!revlen) + { + return 0; + } + else + { + return 1; + } +} + +/******************************************************************************* + * @fn SPI0_SlaveTrans + * + * @brief Slave mode, send multi-byte data + * + * @param pbuf: The first address of the data content to be sent + * + * @return 0/1 0 means receive failed,1 means receive success. + */ +uint8_t SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len, uint16_t timeouts) +{ + uint16_t sendlen; + + sendlen = len; + SPI0_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI0_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + while (sendlen) + { + if (!(timeouts & SPI_MAX_DELAY)) + { + delay(); + timeouts--; + } + if (SPI0_GET_FIFO_CNT() < SPI0_FIFO_SIZE) // Compare the byte count size in the current FIFO + { + SPI0_SET_FIFO(*pbuf); + pbuf++; + sendlen--; + } + } + if (!sendlen) + { + return 0; + } + else + { + return 1; + } +} + +/******************************************************************************* + * @fn SPI1_MasterDefInit + * + * @brief Host mode default initialization + * + * @return none + */ +void SPI1_MasterInit(uint32_t clockRate) +{ + SPI1_MODE_CFG(RB_SPI_MODE_SLAVE, DISABLE); + SPI1_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR, ENABLE); + SPI1_MODE_CFG(RB_SPI_MISO_OE | RB_SPI_ALL_CLEAR, DISABLE); + SPI1_SET_CLOCK_DIV((SystemCoreClock / clockRate) < 2 ? (2) : (SystemCoreClock / clockRate)); + SPI1_SET_DMA_MODE(0xff, DISABLE); +} + +/******************************************************************************* + * @fn SPI1_DataMode + * + * @brief Set data flow mode + * + * @param mode - data flow mode + * + * @return none + */ +void SPI1_DataMode(ModeBitOrderTypeDef mode) +{ + switch (mode) + { + case Mode0_HighBitINFront: // Mode 0, high bit first + SPI1_MODE_CFG(RB_SPI_MST_SCK_MOD, DISABLE); + break; + case Mode3_HighBitINFront: // Mode 3, high bit first + SPI1_MODE_CFG(RB_SPI_MST_SCK_MOD, ENABLE); + break; + default: + break; + } +} + +/******************************************************************************* + * @fn SPI1_MasterSendByte + * + * @brief Send a single byte (buffer) + * + * @param data - send bytes + * + * @return none + */ +void SPI1_MasterSendByte(uint8_t data) +{ + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); + SPI1_SET_TOTAL_CNT(1); + SPI1_SET_FIFO(data); + + while (SPI1_GET_TOTAL_CNT() != 0); +} + +/******************************************************************************* + * @fn SPI1_MasterRecvByte + * + * @brief Receive a single byte (buffer) + * + * @return bytes received + */ +uint8_t SPI1_MasterRecvByte(void) +{ + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); + SPI1_SET_TOTAL_CNT(1); + SPI1_SET_FIFO(0xff); + while (!SPI1_GET_FIFO_CNT()); + return (SPI1_GET_FIFO()); +} + +/******************************************************************************* + * @fn SPI1_MasterTrans + * + * @brief Continuously send multiple bytes using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + */ +void SPI1_MasterTrans(uint8_t *pbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI1_ClearITFlag(RB_SPI_IF_CNT_END); + while (sendlen) + { + if (SPI1_GET_FIFO_CNT() < SPI1_FIFO_SIZE) + { + SPI1_SET_FIFO(*pbuf); + pbuf++; + sendlen--; + } + } + while (SPI1_GET_TOTAL_CNT() != 0); // Wait for all the data in the FIFO to be sent + +} + +/******************************************************************************* + * @fn SPI1_MasterRecv + * + * @brief Receive multiple bytes continuously using FIFO + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + **/ +void SPI1_MasterRecv(uint8_t *pbuf, uint16_t len) +{ + uint16_t readlen; + + readlen = len; + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set data direction to input + SPI1_SET_TOTAL_CNT(len); // Set the length of the data to be received, the FIFO direction will start the + // transmission if the input length is not 0 + R8_SPI1_INT_FLAG = RB_SPI_IF_CNT_END; + SPI1_SET_FIFO(0xff); + while (readlen) + { + if (SPI1_GET_FIFO_CNT()) + { + *pbuf = SPI1_GET_FIFO(); + SPI1_SET_FIFO(0xff); + pbuf++; + readlen--; + } + } +} + +/******************************************************************************* + * @fn SPI1_MasterTransRecv + * + * @brief Continuously send/receive multiple bytes + * + * @param pbuf: The first address of the data content to be sent + * + * @return none + */ +void SPI1_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len) +{ + uint16_t sendlen; + + sendlen = len; + SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI1_ClearITFlag(RB_SPI_IF_CNT_END); + while (sendlen) + { + if (SPI1_GET_FIFO_CNT() == 0) + { + SPI1_SET_FIFO(*ptbuf); + while (SPI1_GET_FIFO_CNT() != 0); + ptbuf++; + *prbuf = SPI1_GET_BUFFER(); + prbuf++; + sendlen--; + } + } +} + +/******************************************************************************* + * @fn SPI1_SlaveInit + * + * @brief Device mode default initialization + * + * @return none + */ +void SPI1_SlaveInit(uint32_t clockRate) +{ + SPI1_MODE_CFG(RB_SPI_MODE_SLAVE | RB_SPI_ALL_CLEAR, ENABLE); + SPI1_MODE_CFG(RB_SPI_MOSI_OE | RB_SPI_SCK_OE | RB_SPI_ALL_CLEAR, DISABLE); + SPI1_MODE_CFG(RB_SPI_MISO_OE, ENABLE); + + SPI1_SET_DMA_MODE(0xff, DISABLE); +} + +/******************************************************************************* + * @fn SPI1_SlaveRecvByte + * + * @brief Slave mode, receive one byte of data + * + * @return received data + */ +uint8_t SPI1_SlaveRecvByte(void) +{ + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data + while (!SPI1_GET_FIFO_CNT()); + return SPI1_GET_FIFO(); +} + +/******************************************************************************* + * @fn SPI1_SlaveRecvByte + * + * @brief Slave mode, send one byte of data + * + * @param data: data will be sent + * + * @return send data + **/ +void SPI1_SlaveSendByte(uint8_t data) +{ + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set to output mode, send data + SPI1_SET_FIFO(data); + SPI1_SET_TOTAL_CNT(1); + while (SPI1_GET_FIFO_CNT()); +} + +/******************************************************************************* + * @fn SPI1_SlaveRecv + * + * @brief Slave mode, receive multi-byte data + * + * @param pbuf: Receive data storage starting address + * + * @return 0/1 0 means receive failed,1 means receive success. + **/ +uint8_t SPI1_SlaveRecv(uint8_t *pbuf, uint16_t len, uint16_t timeouts) +{ + uint16_t revlen; + + revlen = len; + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, ENABLE); // Set to input mode, receive data + SPI1_SET_TOTAL_CNT(revlen); // Assign a value to the SPI send and receive data total length register + while (revlen && timeouts) + { + if (!(timeouts & SPI_MAX_DELAY)) + { + delay(); + timeouts--; + } + if (SPI1_GET_FIFO_CNT()) // Byte count in the current FIFO + { + *pbuf = SPI1_GET_FIFO(); + pbuf++; + revlen--; + } + } + if (!revlen) + { + return 0; + } + else + { + return 1; + } +} + +/******************************************************************************* + * @fn SPI1_SlaveTrans + * + * @brief Slave mode, send multi-byte data + * + * @param pbuf: The first address of the data content to be sent + * + * @return 0/1 0 means receive failed,1 means receive success. + */ +uint8_t SPI1_SlaveTrans(uint8_t *pbuf, uint16_t len, uint16_t timeouts) +{ + uint16_t sendlen; + + sendlen = len; + SPI1_MODE_CFG(RB_SPI_FIFO_DIR, DISABLE); // Set data direction to output + SPI1_SET_TOTAL_CNT(sendlen); // Set the length of the data to be sent + while (sendlen) + { + if (!(timeouts & SPI_MAX_DELAY)) + { + delay(); + timeouts--; + } + if (SPI1_GET_FIFO_CNT() < SPI1_FIFO_SIZE) // Compare the byte count size in the current FIFO + { + SPI1_SET_FIFO(*pbuf); + pbuf++; + sendlen--; + } + } + if (!sendlen) + { + return 0; + } + else + { + return 1; + } +} diff --git a/Peripheral/src/ch564_tim.c b/Peripheral/src/ch564_tim.c new file mode 100644 index 0000000..ace4ee3 --- /dev/null +++ b/Peripheral/src/ch564_tim.c @@ -0,0 +1,377 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the TIM firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_tim.h" + +/******************************************************************************* + * @fn TMR0_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param arr - the Most End Value counting to + * + * @return none + */ +void TMR0_TimerInit(uint32_t arr) +{ + R32_TMR0_CNT_END = arr; +} + +/******************************************************************************* + * @fn TMR1_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param arr - the Most End Value counting to + * + * @return none + */ +void TMR1_TimerInit(uint32_t arr) +{ + R32_TMR1_CNT_END = arr; +} + +/******************************************************************************* + * @fn TMR2_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param arr - the Most End Value counting to + * + * @return none + */ +void TMR2_TimerInit(uint32_t arr) +{ + R32_TMR2_CNT_END = arr; +} + +/******************************************************************************* + * @fn TMR3_TimerInit + * + * @brief Counting Function on TIM PeriPheral + * + * @param arr - the Most End Value counting to + * + * @return none + */ +void TMR3_TimerInit(uint32_t arr) +{ + R32_TMR3_CNT_END = arr; +} + +/******************************************************************************* + * @fn TMR3_EXTSignalCounterInit + * + * @brief external signal count + * + * @param arr - the most end value contting to + * capedge - capture edge + * CAP_NULL + * Edge_To_Edge + * FallEdge_To_FallEdge + * RiseEdge_To_RiseEdge + * capwidth - the shortest width can be captured + * clock16 = 0, + * clock8 + * + * @return none + */ +void TMR3_EXTSignalCounterInit(uint32_t arr, CapModeTypeDef capedge, CapWidthTypedef capwidth) +{ + R32_TMR3_CNT_END = arr; + R8_TMR3_CTRL_MOD = RB_TMR_ALL_CLEAR; + R8_TMR3_CTRL_MOD = RB_TMR3_MODE_COUNT; + R8_TMR3_CTRL_MOD &= ~(0x03 << 6); + R8_TMR3_CTRL_MOD |= (capedge << 6); + R8_TMR3_CTRL_MOD &= ~(0x01 << 4); + R8_TMR3_CTRL_MOD |= (capwidth << 4); +} + +/******************************************************************************* + * @fn TMR0_PWMInit + * + * @brief PWM Output Init + * + * @param polarities - PWM output polarity + * high_on_low + * low_on_high + * repeattime - Number of repetitions of PWM + * PWM_Times_1 + * PWM_Times_4 + * PWM_Times_8 + * PWM_Times_16 + * + * @return none + */ +void TMR0_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime) +{ + uint8_t tmp = 0; + tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6); + R8_TMR0_CTRL_MOD = tmp; +} + +/********** ********************************************************************* + * @fn TMR1_PWMInit + * + * @brief PWM Output Init + * + * @param polarities - PWM output polarity + * high_on_low + * low_on_high + * repeattime - Number of repetitions of PWM + * PWM_Times_1 + * PWM_Times_4 + * PWM_Times_8 + * PWM_Times_16 + * + * @return none + */ +void TMR1_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime) +{ + uint8_t tmp = 0; + tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6); + R8_TMR1_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR2_PWMInit + * + * @brief PWM Output Init + * + * @param polarities - PWM output polarity + * high_on_low + * low_on_high + * repeattime - Number of repetitions of PWM + * PWM_Times_1 + * PWM_Times_4 + * PWM_Times_8 + * PWM_Times_16 + * + * @return none + */ +void TMR2_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime) +{ + uint8_t tmp = 0; + tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6); + R8_TMR2_CTRL_MOD = tmp; +} + +/********** ********************************************************************* + * @fn TMR3_PWMInit + * + * @brief PWM Output Init + * + * @param polarities - PWM output polarity + * high_on_low + * low_on_high + * repeattime - Number of repetitions of PWM + * PWM_Times_1 + * PWM_Times_4 + * PWM_Times_8 + * PWM_Times_16 + * + * @return none + */ +void TMR3_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime) +{ + uint8_t tmp = 0; + tmp = RB_TMR_OUT_EN | (polarities << 4) | (repeattime << 6); + R8_TMR3_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR0_CapInit + * + * @brief Timer capture function initialization + * + * @param capedge - capture edge + * CAP_NULL + * Edge_To_Edge + * FallEdge_To_FallEdge + * RiseEdge_To_RiseEdge + * capwidth - the shortest width can be captured + * clock16 = 0, + * clock8 + * + * @return none + */ +void TMR0_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt) +{ + uint8_t tmp = 0; + tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4); + R8_TMR0_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR1_CapInit + * + * @brief Timer capture function initialization + * + * @param capedge - capture edge + * CAP_NULL + * Edge_To_Edge + * FallEdge_To_FallEdge + * RiseEdge_To_RiseEdge + * capwidth - the shortest width can be captured + * clock16 = 0, + * clock8 + * + * @return none + */ +void TMR1_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt) +{ + uint8_t tmp = 0; + tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4); + R8_TMR1_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR2_CapInit + * + * @brief Timer capture function initialization + * + * @param capedge - capture edge + * CAP_NULL + * Edge_To_Edge + * FallEdge_To_FallEdge + * RiseEdge_To_RiseEdge + * capwidth - the shortest width can be captured + * clock16 = 0, + * clock8 + * + * @return none + */ +void TMR2_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt) +{ + uint8_t tmp = 0; + tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4); + R8_TMR2_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR3_CapInit + * + * @brief Timer capture function initialization + * + * @param capedge - capture edge + * CAP_NULL + * Edge_To_Edge + * FallEdge_To_FallEdge + * RiseEdge_To_RiseEdge + * capwidth - the shortest width can be captured + * clock16 = 0, + * clock8 + * + * @return none + */ +void TMR3_CapInit(CapModeTypeDef capedge, CapWidthTypedef widt) +{ + uint8_t tmp = 0; + tmp = RB_TMR_MODE_IN | (capedge << 6) | (widt << 4); + R8_TMR3_CTRL_MOD = tmp; +} + +/******************************************************************************* + * @fn TMR0_DMACfg + * + * @brief TMR DMA Configuration + * + * @param NewSTA + * - ENABLE/DISABLE + * startAddr + * - DMA start address + * endAddr + * - DMA end address + * DMAMode + * - DMA mode + * @return none + **/ +void TMR0_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode) +{ + if (NewSTA == DISABLE) + { + R8_TMR0_CTRL_DMA = 0; + } + else + { + TMR0_DMA_SET_RANGE(startAddr, endAddr); + if (DMAMode & Mode_LOOP) + R8_TMR0_CTRL_DMA |= RB_TMR_DMA_LOOP; + if (DMAMode & Mode_Burst) + R8_TMR0_CTRL_DMA |= RB_TMR_DMA_BURST; + R8_TMR0_CTRL_DMA |= RB_TMR_DMA_ENABLE; + } +} + +/******************************************************************************* + * @fn TMR1_DMACfg + * + * @brief TMR DMA Configuration + * + * @param NewSTA + * - ENABLE/DISABLE + * startAddr + * - DMA start address + * endAddr + * - DMA end address + * DMAMode + * - DMA mode + * @return none + **/ +void TMR1_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode) +{ + if (NewSTA == DISABLE) + { + R8_TMR1_CTRL_DMA = 0; + } + else + { + TMR1_DMA_SET_RANGE(startAddr, endAddr); + if (DMAMode & Mode_LOOP) + R8_TMR1_CTRL_DMA |= RB_TMR_DMA_LOOP; + if (DMAMode & Mode_Burst) + R8_TMR1_CTRL_DMA |= RB_TMR_DMA_BURST; + R8_TMR1_CTRL_DMA |= RB_TMR_DMA_ENABLE; + } +} + +/******************************************************************************* + * @fn TMR2_DMACfg + * + * @brief TMR DMA Configuration + * + * @param NewSTA + * - ENABLE/DISABLE + * startAddr + * - DMA start address + * endAddr + * - DMA end address + * DMAMode + * - DMA mode + * @return none + **/ + +void TMR2_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode) +{ + if (NewSTA == DISABLE) + { + R8_TMR2_CTRL_DMA = 0; + } + else + { + TMR2_DMA_SET_RANGE(startAddr, endAddr); + if (DMAMode & Mode_LOOP) + R8_TMR2_CTRL_DMA |= RB_TMR_DMA_LOOP; + if (DMAMode & Mode_Burst) + R8_TMR2_CTRL_DMA |= RB_TMR_DMA_BURST; + R8_TMR2_CTRL_DMA |= RB_TMR_DMA_ENABLE; + } +} diff --git a/Peripheral/src/ch564_uart.c b/Peripheral/src/ch564_uart.c new file mode 100644 index 0000000..0458e53 --- /dev/null +++ b/Peripheral/src/ch564_uart.c @@ -0,0 +1,818 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_uart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the UART firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_uart.h" + +static uint8_t Best_DIV; +/****************************************************************************** + * @fn Less_Loss_DIV_Calcu + * + * @brief Caculate the most fit DIV value + * + * @return none + */ +void Less_Loss_DIV_Calcu(uint64_t targetbaud) +{ + uint64_t extranum, result_keeper = 1; + extranum = targetbaud; + for (unsigned int i = 1; i < 128; i++) + { + if (!((SystemCoreClock * 2 / 16 / i) * 2 / targetbaud)) + break; + long tmpextra = (SystemCoreClock * 2 / 16 / i) % targetbaud; + tmpextra = tmpextra > targetbaud / 2 ? targetbaud - tmpextra : tmpextra; + + if (tmpextra < extranum) + { + result_keeper = i; + extranum = tmpextra; + } + } + Best_DIV = result_keeper; +} +/****************************************************************************** + * @fn UART0_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return none + */ +void UART0_DefInit(void) +{ + + UART0_BaudRateCfg(115200); + R8_UART0_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; // FIFO open, trigger point 14 bytes + R8_UART0_LCR = RB_LCR_WORD_SZ; + R8_UART0_IER = RB_IER_TXD_EN; + R8_UART0_MCR = RB_MCR_OUT1; +} + +/******************************************************************************* + * @fn UART1_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + *length setting, baud rate and frequency division coefficient + * + * @return none + **/ +void UART1_DefInit(void) +{ + UART1_BaudRateCfg(115200); + R8_UART1_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART1_LCR = RB_LCR_WORD_SZ; + R8_UART1_IER = RB_IER_TXD_EN; + R8_UART1_MCR = RB_MCR_OUT1; +} + +/******************************************************************************* + * @fn UART2_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return none + */ +void UART2_DefInit(void) +{ + + UART2_BaudRateCfg(115200); + R8_UART2_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART2_LCR = RB_LCR_WORD_SZ; + R8_UART2_IER = RB_IER_TXD_EN; + R8_UART2_MCR = RB_MCR_OUT1; +} + +/******************************************************************************* + * @fn UART3_DefInit + * + * @brief Serial port default initialization configuration: FIFO enabled, trigger point byte count, serial port data + * length setting, baud rate and frequency division coefficient + * + * @return none + */ +void UART3_DefInit(void) +{ + UART3_BaudRateCfg(115200); + R8_UART3_FCR = RB_FCR_FIFO_TRIG | RB_FCR_TX_FIFO_CLR | RB_FCR_RX_FIFO_CLR | RB_FCR_FIFO_EN; + // FIFO open, trigger point 14 bytes + R8_UART3_LCR = RB_LCR_WORD_SZ; + R8_UART3_IER = RB_IER_TXD_EN; + R8_UART3_MCR = RB_MCR_OUT1; +} + +/******************************************************************************* + * @fn UART0_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return none + */ +void UART0_BaudRateCfg(uint32_t baudrate) +{ + uint64_t x; + Less_Loss_DIV_Calcu(baudrate); + x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate; + x += 5; + x /= 10; + x = x == 0 ? 1 : x; + R8_UART0_LCR |= RB_LCR_DLAB; + UART0_SET_DLV(Best_DIV); + R8_UART0_DLM = x >> 8; + R8_UART0_DLL = x; + R8_UART0_LCR &= ~RB_LCR_DLAB; +} + +/******************************************************************************* + * @fn UART1_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return none + */ +void UART1_BaudRateCfg(uint32_t baudrate) +{ + uint64_t x; + Less_Loss_DIV_Calcu(baudrate); + x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate; + x += 5; + x /= 10; + x = x == 0 ? 1 : x; + R8_UART1_LCR |= RB_LCR_DLAB; + UART1_SET_DLV(Best_DIV); + R8_UART1_DLM = x >> 8; + R8_UART1_DLL = x; + R8_UART1_LCR &= ~RB_LCR_DLAB; +} + +/******************************************************************************* + * @fn UART2_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return none + */ +void UART2_BaudRateCfg(uint32_t baudrate) +{ + uint64_t x; + Less_Loss_DIV_Calcu(baudrate); + x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate; + x += 5; + x /= 10; + x = x == 0 ? 1 : x; + R8_UART2_LCR |= RB_LCR_DLAB; + UART2_SET_DLV(Best_DIV); + R8_UART2_DLM = x >> 8; + R8_UART2_DLL = x; + R8_UART2_LCR &= ~RB_LCR_DLAB; +} + +/******************************************************************************* + * @fn UART3_BaudRateCfg + * + * @brief Serial port baud rate configuration + * + * @return none + */ +void UART3_BaudRateCfg(uint32_t baudrate) +{ + uint64_t x; + Less_Loss_DIV_Calcu(baudrate); + x = 10 * (SystemCoreClock / Best_DIV) / 8 / baudrate; + x += 5; + x /= 10; + x = x == 0 ? 1 : x; + R8_UART3_LCR |= RB_LCR_DLAB; + UART3_SET_DLV(Best_DIV); + R8_UART3_DLM = x >> 8; + R8_UART3_DLL = x; + R8_UART3_LCR &= ~RB_LCR_DLAB; +} + +/******************************************************************************* + * @fn UART0_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param UARTByteTRIG - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return none + */ +void UART0_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG) +{ + R8_UART0_FCR = (R8_UART0_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6); +} + +/******************************************************************************* + * @fn UART1_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param UARTByteTRIG - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return none + **/ +void UART1_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG) +{ + R8_UART1_FCR = (R8_UART1_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6); +} + +/******************************************************************************* + * @fn UART2_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param UARTByteTRIG - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return none + */ +void UART2_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG) +{ + R8_UART2_FCR = (R8_UART2_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6); +} + +/******************************************************************************* + * @fn UART3_ByteTrigCfg + * + * @brief Serial byte trigger interrupt configuration + * + * @param UARTByteTRIG - trigger bytes + * refer to UARTByteTRIGTypeDef + * @return none + ***/ +void UART3_ByteTrigCfg(UARTByteTRIGTypeDef UARTByteTRIG) +{ + R8_UART3_FCR = (R8_UART3_FCR & ~RB_FCR_FIFO_TRIG) | (UARTByteTRIG << 6); +} + +/******************************************************************************* + * @fn UART0_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param NewSTA - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * @param RB_IER - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return none + **/ +void UART0_INTCfg(FunctionalState NewSTA, uint8_t RB_IER) +{ + if (NewSTA) + { + R8_UART0_IER |= RB_IER; + + R8_UART0_MCR |= RB_MCR_OUT2; + } + else + { + R8_UART0_IER &= ~RB_IER; + } +} + +/******************************************************************************* + * @fn UART1_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param NewSTA - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * @param RB_IER - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return none + **/ +void UART1_INTCfg(FunctionalState NewSTA, uint8_t RB_IER) +{ + if (NewSTA) + { + R8_UART1_IER |= RB_IER; + R8_UART1_MCR |= RB_MCR_OUT2; + } + else + { + R8_UART1_IER &= ~RB_IER; + } +} + +/******************************************************************************* + * @fn UART2_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param NewSTA - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * @param RB_IER - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return none + **/ +void UART2_INTCfg(FunctionalState NewSTA, uint8_t RB_IER) +{ + if (NewSTA) + { + R8_UART2_IER |= RB_IER; + R8_UART2_MCR |= RB_MCR_OUT2; + } + else + { + R8_UART2_IER &= ~RB_IER; + } +} + +/******************************************************************************* + * @fn UART3_INTCfg + * + * @brief Serial port interrupt configuration + * + * @param NewSTA - interrupt control status + * ENABLE - Enable the corresponding interrupt + * DISABLE - Disable the corresponding interrupt + * @param RB_IER - interrupt type + * RB_IER_MODEM_CHG - Modem input status change interrupt enable bit (supported on UART0 only) + * RB_IER_LINE_STAT - Receive Line Status Interrupt + * RB_IER_THR_EMPTY - Send Holding Register Empty Interrupt + * RB_IER_RECV_RDY - receive data interrupt + * @return none + **/ +void UART3_INTCfg(FunctionalState NewSTA, uint8_t RB_IER) +{ + if (NewSTA) + { + R8_UART3_IER |= RB_IER; + R8_UART3_MCR |= RB_MCR_OUT2; + } + else + { + R8_UART3_IER &= ~RB_IER; + } +} + +/******************************************************************************* + * @fn UART0_Reset + * + * @brief Serial port software reset + * + * @return none + **/ +void UART0_Reset(void) +{ + R8_UART0_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART1_Reset + * + * @brief Serial port software reset + * + * @return none + **/ +void UART1_Reset(void) +{ + R8_UART1_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART2_Reset + * + * @brief Serial port software reset + * + * @return none + **/ +void UART2_Reset(void) +{ + R8_UART2_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART3_Reset + * + * @brief Serial port software reset + * + * @return none + **/ +void UART3_Reset(void) +{ + R8_UART3_IER = RB_IER_RESET; +} + +/******************************************************************************* + * @fn UART0_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART0_SendString(uint8_t *buf, uint16_t length) +{ + uint16_t len = length; + + while (len) + { + if ((R8_UART0_LSR & RB_LSR_TX_FIFO_EMP)) + { + R8_UART0_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART1_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART1_SendString(uint8_t *buf, uint16_t length) +{ + uint16_t len = length; + + while (len) + { + if ((R8_UART1_LSR & RB_LSR_TX_FIFO_EMP)) + { + R8_UART1_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART2_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART2_SendString(uint8_t *buf, uint16_t length) +{ + uint16_t len = length; + + while (len) + { + if ((R8_UART2_LSR & RB_LSR_TX_FIFO_EMP)) + { + R8_UART2_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART3_SendString + * + * @brief Serial multi-byte transmission + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART3_SendString(uint8_t *buf, uint16_t length) +{ + uint16_t len = length; + + while (len) + { + if ((R8_UART3_LSR & RB_LSR_TX_FIFO_EMP)) + { + R8_UART3_THR = *buf++; + len--; + } + } +} + +/******************************************************************************* + * @fn UART0_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ +uint16_t UART0_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + if (!((R8_UART0_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR))) + { + while ((R8_UART0_LSR & RB_LSR_DATA_RDY) == 0) + ; + do + { + *buf++ = R8_UART0_RBR; + len++; + } while ((R8_UART0_LSR & RB_LSR_DATA_RDY)); + } + + return (len); +} + +/******************************************************************************* + * @fn UART1_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +uint16_t UART1_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + if (!((R8_UART1_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR))) + { + while ((R8_UART1_LSR & RB_LSR_DATA_RDY) == 0) + ; + do + { + *buf++ = R8_UART1_RBR; + len++; + } while ((R8_UART1_LSR & RB_LSR_DATA_RDY)); + } + + return (len); +} + +/******************************************************************************* + * @fn UART2_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +uint16_t UART2_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + if (!((R8_UART2_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR))) + { + while ((R8_UART2_LSR & RB_LSR_DATA_RDY) == 0) + ; + do + { + *buf++ = R8_UART2_RBR; + len++; + } while ((R8_UART2_LSR & RB_LSR_DATA_RDY)); + } + + return (len); +} + +/******************************************************************************* + * @fn UART3_RecvString + * + * @brief Serial port read multibyte + * + * @param buf - The first address of the read data storage buffer + * + * @return read data length + */ + +uint16_t UART3_RecvString(uint8_t *buf) +{ + uint16_t len = 0; + + if (!((R8_UART3_LSR) & (RB_LSR_OVER_ERR | RB_LSR_PAR_ERR | RB_LSR_FRAME_ERR | RB_LSR_BREAK_ERR))) + { + while ((R8_UART3_LSR & RB_LSR_DATA_RDY) == 0) + ; + do + { + *buf++ = R8_UART3_RBR; + len++; + } while ((R8_UART3_LSR & RB_LSR_DATA_RDY)); + } + return (len); +} + +/******************************************************************************* + * @fn UART0_Send_DMA + * + * @brief Serial multi-byte transmission via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART0_Send_DMA(uint8_t *buf, uint32_t lenth) +{ + UART0_DMA_SET_RD_RANGE(buf, buf + lenth); + UART0_DMACFG(RB_DMA_RD_EN, ENABLE); +} +/******************************************************************************* + * @fn UART1_Send_DMA + * + * @brief Serial multi-byte transmission via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART1_Send_DMA(uint8_t *buf, uint32_t lenth) +{ + UART1_DMA_SET_RD_RANGE(buf, buf + lenth); + UART1_DMACFG(RB_DMA_RD_EN, ENABLE); +} +/******************************************************************************* + * @fn UART2_Send_DMA + * + * @brief Serial multi-byte transmission via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART2_Send_DMA(uint8_t *buf, uint32_t lenth) +{ + UART2_DMA_SET_RD_RANGE(buf, buf + lenth); + UART2_DMACFG(RB_DMA_RD_EN, ENABLE); +} +/******************************************************************************* + * @fn UART3_Send_DMA + * + * @brief Serial multi-byte transmission via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART3_Send_DMA(uint8_t *buf, uint32_t lenth) +{ + UART3_DMA_SET_RD_RANGE(buf, buf + lenth); + UART3_DMACFG(RB_DMA_RD_EN, ENABLE); +} + +/******************************************************************************* + * @fn UART0_Recv_DMA + * + * @brief Serial multi-byte receive via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART0_Recv_DMA(uint8_t *buf, uint32_t lenth) +{ + UART0_DMA_SET_WR_RANGE(buf, buf + lenth); + UART0_DMACFG(RB_DMA_WR_EN, ENABLE); +} +/******************************************************************************* + * @fn UART1_Recv_DMA + * + * @brief Serial multi-byte receive via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART1_Recv_DMA(uint8_t *buf, uint32_t lenth) +{ + UART1_DMA_SET_WR_RANGE(buf, buf + lenth); + UART1_DMACFG(RB_DMA_WR_EN, ENABLE); +} +/******************************************************************************* + * @fn UART2_Recv_DMA + * + * @brief Serial multi-byte receive via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART2_Recv_DMA(uint8_t *buf, uint32_t lenth) +{ + UART2_DMA_SET_WR_RANGE(buf, buf + lenth); + UART2_DMACFG(RB_DMA_WR_EN, ENABLE); +} +/******************************************************************************* + * @fn UART3_Recv_DMA + * + * @brief Serial multi-byte receive via DMA + * + * @param buf - The first address of the data content to be sent + * length - length of data to be sent + * @return none + */ +void UART3_Recv_DMA(uint8_t *buf, uint32_t lenth) +{ + UART3_DMA_SET_WR_RANGE(buf, buf + lenth); + UART3_DMACFG(RB_DMA_WR_EN, ENABLE); +} + +/******************************************************************************* + * @fn UART0_DTRDSR_Cfg + * + * @brief Enable or disable DTR/DSR function + * + * @param en - ENABLE/DISABLE + * + * @return none + */ +void UART0_DTRDSR_Cfg (FunctionalState en) { + UART0_SET_MCR (RB_MCR_DTR, en); +} + +/******************************************************************************* + * @fn UART0_CTSRTS_Cfg + * + * @brief Enable or disable CTS/RTS function + * + * @param en - ENABLE/DISABLE + * + * @return none + */ +void UART0_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) { + if(GPIOx == GPIOA) + UART0_INTCfg (DISABLE, RB_IER_MODEM_IO); + else if(GPIOx == GPIOB) + UART0_INTCfg (ENABLE, RB_IER_MODEM_IO); + UART0_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG); + UART0_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE); +} + +/******************************************************************************* + * @fn UART1_CTSRTS_Cfg + * + * @brief Enable or disable CTS/RTS function + * + * @param en - ENABLE/DISABLE + * + * @return none + */ +void UART1_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) { + if(GPIOx == GPIOA) + UART1_INTCfg (DISABLE, RB_IER_MODEM_IO); + else if(GPIOx == GPIOB) + UART1_INTCfg (ENABLE, RB_IER_MODEM_IO); + UART1_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG); + UART1_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE); +} + +/******************************************************************************* + * @fn UART2_CTSRTS_Cfg + * + * @brief Enable or disable CTS/RTS function + * + * @param en - ENABLE/DISABLE + * + * @return none + */ +void UART2_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) { + if(GPIOx == GPIOA) + UART2_INTCfg (DISABLE, RB_IER_MODEM_IO); + else if(GPIOx == GPIOB) + UART2_INTCfg (ENABLE, RB_IER_MODEM_IO); + UART2_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG); + UART2_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE); +} + +/******************************************************************************* + * @fn UART3_CTSRTS_Cfg + * + * @brief Enable or disable CTS/RTS function + * + * @param en - ENABLE/DISABLE + * + * @return none + */ +void UART3_CTSRTS_Cfg (GPIO_Typedef* GPIOx, FunctionalState en, FunctionalState auto_ctrl_en) { + if(GPIOx == GPIOA) + UART3_INTCfg (DISABLE, RB_IER_MODEM_IO); + else if(GPIOx == GPIOB) + UART3_INTCfg (ENABLE, RB_IER_MODEM_IO); + UART3_INTCfg (en, RB_IER_MOUT_EN | RB_IER_MOUT_EN | RB_IER_MODEM_CHG); + UART3_SET_MCR ((auto_ctrl_en == ENABLE) ? RB_MCR_AU_FLOW_EN : 0, ENABLE); +} diff --git a/Peripheral/src/ch564_xbus.c b/Peripheral/src/ch564_xbus.c new file mode 100644 index 0000000..dc5cad5 --- /dev/null +++ b/Peripheral/src/ch564_xbus.c @@ -0,0 +1,62 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch564_xbus.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : This file provides all the XBUS firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch564_xbus.h" + +/********************************************************************** + * @fn XbusInit + * + * @brief The XbusInit function initializes the Xbus configuration by setting the address bit, enabling or + * disabling 32-bit mode, and enabling or disabling the Xbus. + * + * @param AddrBit The AddrBit parameter is of type XbusOutputADDrBit, which is likely an enumeration or + * a typedef for a specific type. It represents the address bit configuration for the Xbus module. + * NoOutput No Xbus address output + * - AddrNum_6bit PA[5:0] part of address output + * - AddrNum_12bit PA[11:0] part of address output + * - AddrNum_ALL PA[19:0] part of address output + * Bit32En The Bit32En parameter is used to enable or disable the 32-bit mode of the Xbus. If + * Bit32En is set to ENABLE, the 32-bit mode is enabled. If Bit32En is set to DISABLE, the 32-bit mode + * is disabled. + * Stat The "Stat" parameter is used to enable or disable the Xbus. If "Stat" is set to ENABLE, + * the Xbus will be enabled. If "Stat" is set to DISABLE, the Xbus will be disabled. + */ +void XbusInit(XbusOutputADDrBit AddrBit, FunctionalState Bit32En, FunctionalState Stat) +{ + + RCC_UNLOCK_SAFE_ACCESS(); + R8_XBUS_CONFIG = AddrBit << 2; + RCC_UNLOCK_SAFE_ACCESS(); + R8_XBUS_CONFIG |= (Bit32En == ENABLE ? 0 : RB_XBUS_EN_32BIT); + RCC_UNLOCK_SAFE_ACCESS(); + R8_XBUS_CONFIG |= (Stat == ENABLE ? 0 : RB_XBUS_ENABLE); + RCC_LOCK_SAFE_ACCESS(); /* lock, to prevent unexpected writing */ +} + +/********************************************************************** + * @fn XbusHoldInit + * + * @brief The function XbusHoldInit initializes the Xbus setup hold time and sets the hold time value based on + * the input parameters. + * + * @param setuptm The parameter "setuptm" is of type XbusSetupTime, which is an enumeration type. It + * represents the setup time for the XbusHoldInit function. The possible values for setuptm are: + * - Setuptime_1clk 1 clock cycle + * - Setuptime_2clk 2 clock cycle + * holdtm The holdtm parameter is a uint8_t variable that represents the hold time for the Xbus + * setup. It is used to set the R8_XBUS_SETUP_HOLD register. + */ +void XbusHoldInit(XbusSetupTime setuptm, uint8_t holdtm) +{ + holdtm = holdtm > 0x1f ? 0x1f : holdtm; + R8_XBUS_SETUP_HOLD = holdtm; + R8_XBUS_SETUP_HOLD |= setuptm == Setuptime_1clk ? 0 : 0x80; +} diff --git a/RCU_C1P_Module.wvproj b/RCU_C1P_Module.wvproj new file mode 100644 index 0000000..33ec8c5 --- /dev/null +++ b/RCU_C1P_Module.wvproj @@ -0,0 +1 @@ +?6`Ob9Kt!6;$ XA +#include + +uint32_t test_tick = 0; +uint8_t test_buff[10] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A}; + +/********************************************************************* + * @fn main + * + * @brief Main program. + * + * @return none + */ +int main(void) +{ + + SystemCoreClockUpdate(); + Systick_Init(); + + UARTx_Init(UART_0,512000); + UARTx_Init(UART_1,512000); + UARTx_Init(UART_2,512000); + UARTx_Init(UART_3,512000); + + SYS_LED_Init(); + + SPI_SRAM_Init(); + + SPI_FLASH_Init(); + + WCHNET_LIB_Init(); + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"MCU Start!! 2025-11-03-10:42\r\n"); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"SystemClk:%d\r\n", SystemCoreClock); + + while (1) + { + SYS_LED_Task(); + + UART0_RECEIVE(); + UART1_RECEIVE(); + UART2_RECEIVE(); + UART3_RECEIVE(); + + if(SysTick_1ms - test_tick >= 10000){ + test_tick = SysTick_1ms; + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"RUN PYH:%x...\r\n",ETH_ReadPHYRegister(PHY_ADDRESS, PHY_BSR)); + + } + + NetWork_Task(); + + WCHNET_MainTask(); + + if(WCHNET_QueryGlobalInt()) + { + WCHNET_HandleGlobalInt(); + } + } +} + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + /* MRS_HardFault˼· : https://www.cnblogs.com/wchmcu/p/17545931.html */ + uint32_t v_mepc,v_mcause,v_mtval; + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"hardfault\n"); + + v_mepc=__get_MEPC(); + v_mcause=__get_MCAUSE(); + v_mtval=__get_MTVAL(); + + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"mepc:%x\n",v_mepc); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"mcause:%x\n",v_mcause); + Dbg_Println(DBG_BIT_SYS_STATUS_bit,"mtval:%x\n",v_mtval); + while(1); +} + diff --git a/User/system_ch564.c b/User/system_ch564.c new file mode 100644 index 0000000..72838b6 --- /dev/null +++ b/User/system_ch564.c @@ -0,0 +1,420 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch564.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : CH564 Device Peripheral Access Layer System Source File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +#include "ch564.h" +#include "debug.h" + +/* + * Uncomment the line corresponding to the desired System clock (SYSCLK) + * frequency (after reset the HSI is used as SYSCLK source). + */ + +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_80MHz_HSI 80000000 +//#define SYSCLK_FREQ_60MHz_HSI 60000000 +//#define SYSCLK_FREQ_40MHz_HSI 40000000 +//#define SYSCLK_FREQ_20MHz_HSI HSI_VALUE +#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_80MHz_HSE 80000000 +//#define SYSCLK_FREQ_60MHz_HSE 60000000 +//#define SYSCLK_FREQ_40MHz_HSE 40000000 +//#define SYSCLK_FREQ_25MHz_HSE HSE_VALUE + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_80MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_80MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_60MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_60MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_40MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_40MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_20MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_20MHz_HSI; /* System Clock Frequency (Core Clock) */ + +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_80MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_80MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_60MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_60MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_40MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_40MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_25MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_25MHz_HSE; /* System Clock Frequency (Core Clock) */ +#endif + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI(void); +#elif defined SYSCLK_FREQ_80MHz_HSI +static void SetSysClockTo80_HSI(void); +#elif defined SYSCLK_FREQ_60MHz_HSI +static void SetSysClockTo60_HSI(void); +#elif defined SYSCLK_FREQ_40MHz_HSI +static void SetSysClockTo40_HSI(void); +#elif defined SYSCLK_FREQ_20MHz_HSI +static void SetSysClockTo20_HSI(void); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE(void); +#elif defined SYSCLK_FREQ_80MHz_HSE +static void SetSysClockTo80_HSE(void); +#elif defined SYSCLK_FREQ_60MHz_HSE +static void SetSysClockTo60_HSE(void); +#elif defined SYSCLK_FREQ_40MHz_HSE +static void SetSysClockTo40_HSE(void); +#elif defined SYSCLK_FREQ_25MHz_HSE +static void SetSysClockTo25_HSE(void); +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash + * Interface, update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit(void) +{ + if ( SystemCoreClock >= 60000000 ) + { + RCC_UNLOCK_SAFE_ACCESS(); + BITS_CFG( R32_EXTEN_CTLR0 , RB_FLASH_PRE_EN , ENABLE ); + BITS_CFG( R32_EXTEN_CTLR0 , RB_SW_CFG , DISABLE ); + RCC_LOCK_SAFE_ACCESS(); + } + else + { + RCC_UNLOCK_SAFE_ACCESS(); + BITS_CFG( R32_EXTEN_CTLR0 , RB_FLASH_PRE_EN , DISABLE ); + BITS_CFG( R32_EXTEN_CTLR0 , RB_SW_CFG , DISABLE ); + RCC_LOCK_SAFE_ACCESS(); + } + + SystemCoreClockUpdate(); + + HSI_ON(); + + /* Close ETH PHY */ + RCC_SlpWakeCtrl( RB_SLP_ETH_PWR_DN , DISABLE ); + Delay_Us( PLL_STARTUP_TIME ); + ETH->PHY_CR |= ( 1 << 31 ); + ETH->PHY_CR &= ~( 1 << 30 ); + ETH->PHY_CR |= ( 1 << 30 ); + Delay_Us( HSI_STARTUP_TIME ); + RCC_SlpWakeCtrl( RB_SLP_ETH_PWR_DN , ENABLE ); + + CLKSEL_HSI(); + SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_HSI_HSE ); + USB_PLL_OFF(); + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0; + + if ( R32_EXTEN_CTLR0 & RB_SW ) + { + if ( R32_EXTEN_CTLR1 & RB_CLKSEL ) + { + tmp = HSE_Value; + } + else + { + tmp = HSI_Value; + } + } + else + { + switch ( R32_EXTEN_CTLR0 & RB_USBPLLSRC ) + { + case 0x60: + tmp = HSI_Value; + break; + case 0x20: + tmp = HSE_Value; + break; + default: + tmp = HSE_Value * 20 / 25; + break; + } + + switch ( R32_EXTEN_CTLR0 & RB_USBPLLCLK ) + { + case 0x0: + tmp *= 24; + break; + case 0x4000: + tmp *= 20; + break; + case 0x8000: + tmp *= 16; + break; + case 0xC000: + tmp *= 15; + break; + default: + break; + } + tmp /= ( R8_PLL_OUT_DIV >> 4 ) + 1; + } + + SystemCoreClock = tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + SystemCoreClockUpdate(); + GPIO_IPD_Unused(); + +#ifdef SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_80MHz_HSI + SetSysClockTo80_HSI(); +#elif defined SYSCLK_FREQ_60MHz_HSI + SetSysClockTo60_HSI(); +#elif defined SYSCLK_FREQ_40MHz_HSI + SetSysClockTo40_HSI(); +#elif defined SYSCLK_FREQ_20MHz_HSI + SetSysClockTo20_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_80MHz_HSE + SetSysClockTo80_HSE(); +#elif defined SYSCLK_FREQ_60MHz_HSE + SetSysClockTo60_HSE(); +#elif defined SYSCLK_FREQ_40MHz_HSE + SetSysClockTo40_HSE(); +#elif defined SYSCLK_FREQ_25MHz_HSE + SetSysClockTo25_HSE(); +#endif +} + +#ifdef SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + RCC_SET_PLL_SYS_OUT_DIV( 0x3 ); + USB_PLL_MUL_SELECT( USB_PLL_MUL_24 ); + USB_PLL_SOURCE_SELECT( USB_PLL_SOURCE_HSI ); + USB_PLL_ON(); + Delay_Us( PLL_STARTUP_TIME ); + SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_USBPLL ); +} + +#elif defined SYSCLK_FREQ_80MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo80_HSI + * + * @brief Sets System clock frequency to 80MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo80_HSI(void) +{ + RCC_SET_PLL_SYS_OUT_DIV(0x5); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_HSI); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_60MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo60_HSI + * + * @brief Sets System clock frequency to 60MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo60_HSI(void) +{ + RCC_SET_PLL_SYS_OUT_DIV(0x7); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_HSI); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_40MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo8_HSI + * + * @brief Sets System clock frequency to 40MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo40_HSI(void) +{ + RCC_SET_PLL_SYS_OUT_DIV( 0xB ); + USB_PLL_MUL_SELECT( USB_PLL_MUL_24 ); + USB_PLL_SOURCE_SELECT( USB_PLL_SOURCE_HSI ); + USB_PLL_ON(); + Delay_Us( PLL_STARTUP_TIME ); + SYSCLK_SOURCE_SELECT( SYSCLK_SOURCE_USBPLL ); +} + +#elif defined SYSCLK_FREQ_20MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo20_HSI + * + * @brief Sets System clock frequency to 20MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo20_HSI(void) +{ + CLKSEL_HSI(); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_HSI_HSE); +} + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 24MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + HSE_ON(); + Delay_Us(HSE_STARTUP_TIME); + RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE); + RCC_SET_PLL_SYS_OUT_DIV(0x3); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_80MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo80_HSE + * + * @brief Sets System clock frequency to 80MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo80_HSE(void) +{ + HSE_ON(); + Delay_Us(HSE_STARTUP_TIME); + RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE); + RCC_SET_PLL_SYS_OUT_DIV(0x5); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_60MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo60_HSE + * + * @brief Sets System clock frequency to 60MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo60_HSE(void) +{ + HSE_ON(); + Delay_Us(HSE_STARTUP_TIME); + RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE); + RCC_SET_PLL_SYS_OUT_DIV(0x7); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_40MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo40_HSE + * + * @brief Sets System clock frequency to 40MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo40_HSE(void) +{ + HSE_ON(); + Delay_Us(HSE_STARTUP_TIME); + RCC_SlpWakeCtrl(RB_SLP_ETH_PWR_DN, DISABLE); + RCC_SET_PLL_SYS_OUT_DIV(0xB); + USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE_ETH_PLL_OUT); + USB_PLL_MUL_SELECT(USB_PLL_MUL_24); + USB_PLL_ON(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_USBPLL); +} + +#elif defined SYSCLK_FREQ_25MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo25_HSE + * + * @brief Sets System clock frequency to 25MHz and configure HCLK prescalers. + * + * @return none + */ +static void SetSysClockTo25_HSE(void) +{ + HSE_ON(); + Delay_Us(HSE_STARTUP_TIME); + CLKSEL_HSE(); + SystemCoreClock = HSE_VALUE; + Delay_Init(); + Delay_Us(PLL_STARTUP_TIME); + SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE_HSI_HSE); + +} + +#endif diff --git a/User/system_ch564.h b/User/system_ch564.h new file mode 100644 index 0000000..e348849 --- /dev/null +++ b/User/system_ch564.h @@ -0,0 +1,30 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch564.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/05/05 + * Description : CH564 Device Peripheral Access Layer System Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __SYSTEM_CH564_H +#define __SYSTEM_CH564_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif +