feat:新建项目文件
BLV主机C1P模块
This commit is contained in:
caocong
317
Core/core_riscv.c
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317
Core/core_riscv.c
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@@ -0,0 +1,317 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/05/05
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* Description : RISC-V V4J Core Peripheral Access Layer Source File for CH564
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "stdint.h"
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/* define compiler specific symbols */
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#if defined(__CC_ARM)
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#define __ASM __asm /* asm keyword for ARM Compiler */
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#define __INLINE __inline /* inline keyword for ARM Compiler */
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#elif defined(__ICCARM__)
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#define __ASM __asm /* asm keyword for IAR Compiler */
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#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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#elif defined(__GNUC__)
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#define __ASM __asm /* asm keyword for GNU Compiler */
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#define __INLINE inline /* inline keyword for GNU Compiler */
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#elif defined(__TASKING__)
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#define __ASM __asm /* asm keyword for TASKING Compiler */
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#define __INLINE inline /* inline keyword for TASKING Compiler */
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#endif
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/*********************************************************************
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* @fn __get_MSTATUS
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*
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* @brief Return the Machine Status Register
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*
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* @return mstatus value
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*/
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uint32_t __get_MSTATUS(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0," "mstatus" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSTATUS
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*
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* @brief Set the Machine Status Register
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*
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* @param value - set mstatus value
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*
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* @return none
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*/
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void __set_MSTATUS(uint32_t value)
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{
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__ASM volatile("csrw mstatus, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MISA
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*
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* @brief Return the Machine ISA Register
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*
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* @return misa value
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*/
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uint32_t __get_MISA(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""misa" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MISA
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*
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* @brief Set the Machine ISA Register
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*
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* @param value - set misa value
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*
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* @return none
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*/
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void __set_MISA(uint32_t value)
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{
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__ASM volatile("csrw misa, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVEC
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*
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* @brief Return the Machine Trap-Vector Base-Address Register
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*
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* @return mtvec value
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*/
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uint32_t __get_MTVEC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mtvec" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVEC
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*
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* @brief Set the Machine Trap-Vector Base-Address Register
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*
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* @param value - set mtvec value
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*
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* @return none
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*/
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void __set_MTVEC(uint32_t value)
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{
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__ASM volatile("csrw mtvec, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MSCRATCH
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*
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* @brief Return the Machine Seratch Register
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*
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* @return mscratch value
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*/
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uint32_t __get_MSCRATCH(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mscratch" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MSCRATCH
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*
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* @brief Set the Machine Seratch Register
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*
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* @param value - set mscratch value
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*
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* @return none
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*/
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void __set_MSCRATCH(uint32_t value)
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{
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__ASM volatile("csrw mscratch, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MEPC
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*
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* @brief Return the Machine Exception Program Register
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*
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* @return mepc value
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*/
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uint32_t __get_MEPC(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mepc" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Exception Program Register
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*
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* @return mepc value
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*/
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void __set_MEPC(uint32_t value)
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{
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__ASM volatile("csrw mepc, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MCAUSE
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*
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* @brief Return the Machine Cause Register
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*
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* @return mcause value
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*/
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uint32_t __get_MCAUSE(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mcause" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MEPC
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*
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* @brief Set the Machine Cause Register
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*
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* @return mcause value
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*/
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void __set_MCAUSE(uint32_t value)
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{
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__ASM volatile("csrw mcause, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MTVAL
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*
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* @brief Return the Machine Trap Value Register
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*
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* @return mtval value
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*/
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uint32_t __get_MTVAL(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mtval" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __set_MTVAL
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*
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* @brief Set the Machine Trap Value Register
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*
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* @return mtval value
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*/
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void __set_MTVAL(uint32_t value)
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{
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__ASM volatile("csrw mtval, %0" : : "r"(value));
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}
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/*********************************************************************
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* @fn __get_MVENDORID
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*
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* @brief Return Vendor ID Register
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*
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* @return mvendorid value
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*/
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uint32_t __get_MVENDORID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mvendorid" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __get_MARCHID
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*
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* @brief Return Machine Architecture ID Register
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*
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* @return marchid value
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*/
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uint32_t __get_MARCHID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""marchid" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __get_MIMPID
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*
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* @brief Return Machine Implementation ID Register
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*
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* @return mimpid value
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*/
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uint32_t __get_MIMPID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mimpid": "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __get_MHARTID
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*
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* @brief Return Hart ID Register
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*
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* @return mhartid value
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*/
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uint32_t __get_MHARTID(void)
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{
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uint32_t result;
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__ASM volatile("csrr %0,""mhartid" : "=r"(result));
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return (result);
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}
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/*********************************************************************
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* @fn __get_SP
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*
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* @brief Return SP Register
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*
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* @return SP value
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*/
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uint32_t __get_SP(void)
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{
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uint32_t result;
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__ASM volatile("mv %0,""sp" : "=r"(result):);
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return (result);
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}
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/*********************************************************************
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* @fn NVIC_SystemReset
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*
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* @brief Initiate a system reset request
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*
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* @return none
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*/
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__attribute__((noinline)) void NVIC_SystemReset(void)
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{
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asm("li t0, 0xa8");
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asm("jr t0");
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}
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686
Core/core_riscv.h
Normal file
686
Core/core_riscv.h
Normal file
@@ -0,0 +1,686 @@
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/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/05/05
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* Description : RISC-V V4J Core Peripheral Access Layer Header File for CH564
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||||
*********************************************************************************
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||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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||||
* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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||||
*******************************************************************************/
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#ifndef __CORE_RISCV_H__
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#define __CORE_RISCV_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* IO definitions */
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#ifdef __cplusplus
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#define __I volatile /* defines 'read only' permissions */
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#else
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#define __I volatile const /* defines 'read only' permissions */
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#endif
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#define __O volatile /* defines 'write only' permissions */
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#define __IO volatile /* defines 'read / write' permissions */
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/* Standard Peripheral Library old types (maintained for legacy purpose) */
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typedef __I uint64_t vuc64; /* Read Only */
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typedef __I uint32_t vuc32; /* Read Only */
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typedef __I uint16_t vuc16; /* Read Only */
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typedef __I uint8_t vuc8; /* Read Only */
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typedef const uint64_t uc64; /* Read Only */
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typedef const uint32_t uc32; /* Read Only */
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typedef const uint16_t uc16; /* Read Only */
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typedef const uint8_t uc8; /* Read Only */
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typedef __I int64_t vsc64; /* Read Only */
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typedef __I int32_t vsc32; /* Read Only */
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typedef __I int16_t vsc16; /* Read Only */
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typedef __I int8_t vsc8; /* Read Only */
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typedef const int64_t sc64; /* Read Only */
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typedef const int32_t sc32; /* Read Only */
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typedef const int16_t sc16; /* Read Only */
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typedef const int8_t sc8; /* Read Only */
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typedef __IO uint64_t vu64;
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typedef __IO uint32_t vuint32_t;
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typedef __IO uint16_t vu16;
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typedef __IO uint8_t vuint8_t;
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef __IO int64_t vs64;
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typedef __IO int32_t vs32;
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typedef __IO int16_t vs16;
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typedef __IO int8_t vs8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef enum
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{
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NoREADY = 0,
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READY = !NoREADY
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} ErrorStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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#define RV_STATIC_INLINE static inline
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/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
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typedef struct
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{
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||||
__I uint32_t ISR[8];
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||||
__I uint32_t IPR[8];
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__IO uint32_t ITHRESDR;
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__IO uint32_t RESERVED;
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__IO uint32_t CFGR;
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||||
__I uint32_t GISR;
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||||
__IO uint8_t VTFIDR[4];
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uint8_t RESERVED0[12];
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__IO uint32_t VTFADDR[4];
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uint8_t RESERVED1[0x90];
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__O uint32_t IENR[8];
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uint8_t RESERVED2[0x60];
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__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
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||||
__IO uint32_t SCTLR;
|
||||
} PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint32_t SR;
|
||||
__IO uint64_t CNT;
|
||||
__IO uint64_t CMP;
|
||||
} SysTick_Type;
|
||||
|
||||
#define PFIC ((PFIC_Type *)0xE000E000)
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
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||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
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||||
#define SysTick ((SysTick_Type *)0xE000F000)
|
||||
|
||||
/* CSR_Operation_Function */
|
||||
#define READ_CSR(reg) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
__asm volatile("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define WRITE_CSR(reg, val) \
|
||||
({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
__asm volatile("csrw " #reg ", %0" ::"i"(val)); \
|
||||
else \
|
||||
__asm volatile("csrw " #reg ", %0" ::"r"(val)); \
|
||||
})
|
||||
|
||||
#define SWAP_CSR(reg, val) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
__asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
|
||||
else \
|
||||
__asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define SET_CSR(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
__asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
__asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
#define CLEAR_CSR(reg, bit) \
|
||||
({ \
|
||||
unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
__asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
__asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; \
|
||||
})
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __enable_irq()
|
||||
{
|
||||
__asm volatile("csrs 0x800, %0" : : "r"(0x88));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __disable_irq()
|
||||
{
|
||||
__asm volatile("csrc 0x800, %0" : : "r"(0x88));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return ((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6:5] - Sub priority
|
||||
* bit[4:0] - Reserve
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||
* priority - bit[7:5] - Sub priority
|
||||
* bit[4:0] - Reserve
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1 << 3); // wfi
|
||||
__asm volatile("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _SEV
|
||||
*
|
||||
* @brief Set Event
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void _SEV(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1 << 3) | (1 << 5);
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1 << 5)) | (t & (1 << 5));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void _WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1 << 3);
|
||||
__asm volatile("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
_SEV();
|
||||
_WFE();
|
||||
_WFE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetVTFIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param addr - VTF interrupt service function base address.
|
||||
* IRQn - Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* NewState - DISABLE or ENABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
if (num > 3)
|
||||
return;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) | 0x1);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr & 0xFFFFFFFE) & (~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheEnable
|
||||
*
|
||||
* @brief Enable ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheEnable(void)
|
||||
{
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
CLEAR_CSR(0xBC2, 0x2);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheDisable
|
||||
*
|
||||
* @brief Disable ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheDisable(void)
|
||||
{
|
||||
SET_CSR(0xBC2, 0x2);
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheInvalidate
|
||||
*
|
||||
* @brief Invalidate ICache
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate(void)
|
||||
{
|
||||
WRITE_CSR(0xBD0, 0x4);
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn ICacheInvalidate_By_Address
|
||||
*
|
||||
* @brief Invalidate ICache By Address
|
||||
*
|
||||
* @param addr - operation address(addr%4 = 0)
|
||||
* size - operation size(unit 4Byte)
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE void ICacheInvalidate_By_Address(uint32_t *addr, uint32_t size)
|
||||
{
|
||||
uint32_t t;
|
||||
uint32_t temp;
|
||||
|
||||
for (t = 0; t < size; t++)
|
||||
{
|
||||
temp = (uint32_t)(addr + t);
|
||||
WRITE_CSR(0xBD0, (temp & 0xFFFFFFF8));
|
||||
__asm volatile("fence.i");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOADD_W
|
||||
*
|
||||
* @brief Atomic Add with 32bit value
|
||||
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ADDed
|
||||
*
|
||||
* @return return memory value + add value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoadd.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOAND_W
|
||||
*
|
||||
* @brief Atomic And with 32bit value
|
||||
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ANDed
|
||||
*
|
||||
* @return return memory value & and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoand.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAX_W
|
||||
*
|
||||
* @brief Atomic signed MAX with 32bit value
|
||||
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the bigger value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amomax.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAXU_W
|
||||
*
|
||||
* @brief Atomic unsigned MAX with 32bit value
|
||||
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amomaxu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMIN_W
|
||||
*
|
||||
* @brief Atomic signed MIN with 32bit value
|
||||
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amomin.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMINU_W
|
||||
*
|
||||
* @brief Atomic unsigned MIN with 32bit value
|
||||
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amominu.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOOR_W
|
||||
*
|
||||
* @brief Atomic OR with 32bit value
|
||||
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ORed
|
||||
*
|
||||
* @return return memory value | and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOSWAP_W
|
||||
*
|
||||
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* newval - New value to be stored into the address
|
||||
*
|
||||
* @return return the original value in memory
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("amoswap.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOXOR_W
|
||||
*
|
||||
* @brief Atomic XOR with 32bit value
|
||||
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be XORed
|
||||
*
|
||||
* @return return memory value ^ and value
|
||||
*/
|
||||
__attribute__((always_inline)) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile("amoxor.w %0, %2, %1" : "=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
extern void NVIC_SystemReset(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user