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BLV主机C1P模块
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caocong
2025-12-06 13:49:01 +08:00
commit d2d8800788
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MCU_Driver/spi_sram.c Normal file
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/*
* spi.c
*
* Created on: May 16, 2025
* Author: cc
*/
#include "spi_sram.h"
#include "debug.h"
#include <string.h>
__attribute__((section(".non_0_wait"))) void SPI_SRAM_Init(void)
{
GPIOA_ModeCfg(GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_11, GPIO_ModeOut_PP);
GPIOA_ModeCfg(GPIO_Pin_5, GPIO_ModeIN_Floating);
GPIO_PinRemapConfig(GPIO_PartialRemap2_SPI0,ENABLE);
/*<2A><><EFBFBD><EFBFBD><EFBFBD>Եó<D4B5><C3B3><EFBFBD><EFBFBD><EFBFBD> SPI<50><49><EFBFBD>߲<EFBFBD><DFB2><EFBFBD><EFBFBD><EFBFBD>30MHZ <20>ֲ<EFBFBD><D6B2><EFBFBD>д<EFBFBD><D0B4>SPI<50><49><EFBFBD><EFBFBD>ͨѶΪ50MHZ 24MHZ*/
SPI0_MasterInit(24000000);
SPI0_DataMode(Mode0_HighBitINFront);
SRAM_CE_H;
/*<2A><>ȡSRAMоƬID*/
SRAM_Read_ID_Opeartion();
}
/*******************************************************************************
* Function Name : SRAM_Write_Byte
* Description : SRAMд<4D>ֽ<EFBFBD>
* Input :
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_Write_Byte(uint8_t wdate,uint32_t add)
{
uint8_t Hadd16=0x00,Hadd8=0x00,Ladd=0x00;
Ladd=add;
Hadd8=add>>8;
Hadd16=add>>16;
if(add >= SRAM_ADDRESS_MAX) return ;
SRAM_CE_L;
SPI0_MasterSendByte(SRAM_CMD_Write);
SPI0_MasterSendByte(Hadd16);
SPI0_MasterSendByte(Hadd8);
SPI0_MasterSendByte(Ladd);
SPI0_MasterSendByte(wdate);
SRAM_CE_H;
}
/*******************************************************************************
* Function Name : SRAM_Read_Byte
* Description : SRAM<41><4D><EFBFBD>ֽ<EFBFBD>
* Input :
add <20><><EFBFBD><EFBFBD>ȡ<EFBFBD>ֽڵĵ<DAB5>ַ
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD>ֽ<EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint8_t SRAM_Read_Byte(uint32_t add)
{
uint8_t Hadd8=0x00,Hadd16=0x00,Ladd=0x00,rdate=0x00;
Ladd=add;
Hadd8=add>>8;
Hadd16=add>>16;
if(add >= SRAM_ADDRESS_MAX) return 0x00;
SRAM_CE_L;
SPI0_MasterSendByte(SRAM_CMD_Read);
SPI0_MasterSendByte(Hadd16);
SPI0_MasterSendByte(Hadd8);
SPI0_MasterSendByte(Ladd);
rdate = SPI0_MasterRecvByte();
SRAM_CE_H;
return rdate;
}
/*******************************************************************************
* Function Name : SRAM_Write_Word
* Description : SRAMдuint16_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD>ֽ<EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_Write_Word(uint16_t wdate,uint32_t add)
{
SRAM_Write_Byte((uint8_t)(wdate & 0xFF),add);
SRAM_Write_Byte((uint8_t)((wdate >> 8) & 0xFF),add + 1);
}
/*******************************************************************************
* Function Name : SRAM_Read_Word
* Description : SRAMдuint16_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
add <20><><EFBFBD><EFBFBD>ȡ<EFBFBD>ֵĵ<D6B5>ַ
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD><C8A1>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint16_t SRAM_Read_Word(uint32_t add)
{
uint16_t rev = 0;
rev = SRAM_Read_Byte(add + 1);
rev <<= 8;
rev |= SRAM_Read_Byte(add);
return rev;
}
/*******************************************************************************
* Function Name : SRAM_Write_DW
* Description : SRAMдuint32_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
wdate : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD>˫<EFBFBD><CBAB>
add <20><>˫<EFBFBD><CBAB>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ˫<C8A1><CBAB>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_Write_DW(uint32_t wdate,uint32_t add)
{
SRAM_Write_Byte((uint8_t)(wdate & 0xFF),add);
SRAM_Write_Byte((uint8_t)((wdate >> 8) & 0xFF),add + 1);
SRAM_Write_Byte((uint8_t)((wdate >> 16) & 0xFF),add + 2);
SRAM_Write_Byte((uint8_t)((wdate >> 24) & 0xFF),add + 3);
}
/*******************************************************************************
* Function Name : SRAM_Read_DW
* Description : SRAMдuint32_t<5F><74><EFBFBD><EFBFBD> -- <20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
add <20><><EFBFBD><EFBFBD>ȡ˫<C8A1>ֵĵ<D6B5>ַ
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ˫<C8A1><CBAB>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint32_t SRAM_Read_DW(uint32_t add)
{
uint32_t rev = 0;
rev = SRAM_Read_Byte(add + 3);
rev <<= 8;
rev |= SRAM_Read_Byte(add + 2);
rev <<= 8;
rev |= SRAM_Read_Byte(add + 1);
rev <<= 8;
rev |= SRAM_Read_Byte(add);
return rev;
}
/*******************************************************************************
* Function Name : SRAM_Read_ID_Opeartion
* Description : SRAM <20><>ȡоƬID
* Input : NULL
* Return : <20><><EFBFBD>ض<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
*******************************************************************************/
__attribute__((section(".non_0_wait"))) uint8_t SRAM_Read_ID_Opeartion(void)
{
uint8_t spi_addr[5];
uint8_t read_id[9];
memset(spi_addr,0,0x05);
memset(read_id,0,0x04);
spi_addr[0] = SRAM_CMD_Read_ID;
spi_addr[1] = 0x00 ;
spi_addr[2] = 0x00 ;
spi_addr[3] = 0x00 ;
SRAM_CE_L;
SPI0_DMATrans(spi_addr,0x04);
SPI0_DMARecv(read_id,0x08);
SRAM_CE_H;
Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM MFID:%02X",read_id[0]);
if(read_id[1] == 0x5D)
{
Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%02X - Known Good Die PASS",read_id[1]);
}else {
Dbg_Println(DBG_BIT_SYS_STATUS_bit, "SRAM KGD:%02X - Known Good Die FAIL",read_id[1]);
}
Dbg_Print_Buff(DBG_BIT_SYS_STATUS_bit, "SRAM EID:",&read_id[2],0x06);
return 0;
}
/*******************************************************************************
* Function Name : SRAM_Reset_Operation
* Description : SRAM <20><>λ - ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>λ
* Input : NULL
* Return : NULL
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_Reset_Operation(void)
{
SRAM_CE_L;
SPI0_MasterSendByte(SRAM_CMD_Reset_Enable);
SRAM_CE_H;
//Delay_Ms(2);
SRAM_CE_L;
SPI0_MasterSendByte(SRAM_CMD_Reset);
SRAM_CE_H;
}
/*******************************************************************************
* Function Name : SRAM_DMA_Write_Buff
* Description : SRAM DMA<4D><41>ʽд<CABD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* Input :
wbuff : <20><>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
len : д<><D0B4><EFBFBD><EFBFBD><EFBFBD>ݵij<DDB5><C4B3><EFBFBD> -- <20><><EFBFBD><EFBFBD>4095<39>ֽڳ<D6BD><DAB3><EFBFBD>
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_DMA_Write_Buff(uint8_t* wbuff,uint16_t len,uint32_t add)
{
uint8_t spi_addr[5];
if(add + len >= SRAM_ADDRESS_MAX) return ;
memset(spi_addr,0,0x05);
spi_addr[0] = SRAM_CMD_Write;
spi_addr[1] = (add >> 16) & 0xFF ;
spi_addr[2] = (add >> 8) & 0xFF ;
spi_addr[3] = (add) & 0xFF ;
SRAM_CE_L;
SPI0_DMATrans(spi_addr,0x04);
SPI0_DMATrans(wbuff,len);
SRAM_CE_H;
}
/*******************************************************************************
* Function Name : SRAM_DMA_Read_Buff
* Description : SRAM DMA<4D><41>ʽ<EFBFBD><CABD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
* Input :
rbuff : <20><>Ҫ<EFBFBD><D2AA>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
len : <20><>ȡ<EFBFBD><C8A1><EFBFBD>ݵij<DDB5><C4B3><EFBFBD> -- <20><><EFBFBD><EFBFBD>4095<39>ֽڳ<D6BD><DAB3><EFBFBD>
add <20><><EFBFBD>ֽ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ĵ<EFBFBD>ַ
* Return : None
*******************************************************************************/
__attribute__((section(".non_0_wait"))) void SRAM_DMA_Read_Buff(uint8_t* rbuff,uint16_t len,uint32_t add)
{
uint8_t spi_addr[5];
if(add + len >= SRAM_ADDRESS_MAX) return ;
memset(spi_addr,0,0x05);
spi_addr[0] = SRAM_CMD_Read;
spi_addr[1] = (add >> 16) & 0xFF ;
spi_addr[2] = (add >> 8) & 0xFF ;
spi_addr[3] = (add) & 0xFF ;
SRAM_CE_L;
SPI0_DMATrans(spi_addr,0x04);
SPI0_DMARecv(rbuff,len);
SRAM_CE_H;
}