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BLV主机C1P模块
This commit is contained in:
caocong
2025-12-06 13:49:01 +08:00
commit d2d8800788
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1865
Peripheral/inc/ch564.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_ADC_H
#define __CH564_ADC_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
typedef enum
{
ADC_Channel0 = 0x00,
ADC_Channel1,
ADC_Channel2,
ADC_Channel0_1,
ADC_Channel3,
ADC_Channel4,
ADC_Channel5,
ADC_Channel6,
ADC_ChannelREF,
ADC_ChannelCN
} ADCChannelTypedef;
/***********************************************************************************
* @fn ADC_CMD
*
* @brief ADC Enable/Disable
*
* @param en
* - ENABLE
* - DISABLE
*/
#define ADC_CMD(en) \
{ \
(en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_POWER_ON) : (R8_ADC_CTRL_MOD &= ~RB_ADC_POWER_ON); \
}
/***********************************************************************************
* @fn ADC_SET_SAMPLE_WIDTH_2CLK
*
* @brief ADC Sample time 2clk enable
*
* @param en
* - ENABLE
* - DISABLE
* @return none
*/
#define ADC_SET_SAMPLE_WIDTH_2CLK(en) \
{ \
(en) == ENABLE ? (R8_ADC_CTRL_MOD |= RB_ADC_SAMPLE_WID) : (R8_ADC_CTRL_MOD &= RB_ADC_SAMPLE_WID); \
}
/***********************************************************************************
* @fn ADC_SET_SAMPLE_CYCLE
*
* @brief Config ADC sample cycle.
*
* @param val
* - val = 0:Manual Control
* - val = 0b000001 - 0b111111:Sampling every val clock
* @return none
*/
#define ADC_SET_SAMPLE_CYCLE(val) \
({ \
R8_ADC_CTRL_MOD &= ~RB_ADC_CYCLE_CLK; \
R8_ADC_CTRL_MOD |= (val) & RB_ADC_CYCLE_CLK; \
R32_ADC_CTRL &= ~MASK_ADC_CYCLE_BIT_4_6; \
R32_ADC_CTRL |= (((val) >> 4) << 25) & MASK_ADC_CYCLE_BIT_4_6; \
})
/***********************************************************************************
* @fn ADC_DMA_CMD
*
* @brief Config the ADC DMA control and etc.
*
* @param RB_ADC_IE
* - RB_ADC_IE_ADC_CMP
* - RB_ADC_DMA_ENABLE
* - RB_ADC_DMA_BURST
* - RB_ADC_DMA_LOOP
* - RB_ADC_CHAN_OE
* - RB_ADC_MAN_SAMPLE
*
* en
* - ENABLE
* - DISABLE
* @return none
*/
#define ADC_DMA_CMD(RB_ADC_DMA, en) \
({ (en) == ENABLE ? (R8_ADC_CTRL_DMA |= (RB_ADC_DMA)) : (R8_ADC_CTRL_DMA &= ~(RB_ADC_DMA)); })
/***********************************************************************************
* @fn ADC_IT_CONFIG
*
* @brief ADC interrupt enable
*
* @param RB_ADC_IE
* - RB_ADC_IE_ADC_CMP
* - RB_ADC_IE_ADC_END
* - RB_ADC_IE_FIFO_HF
* - RB_ADC_IE_DMA_END
* - RB_ADC_IE_FIFO_OV
* - RB_ADC_IE_DMA_ERR
* - RB_ADC_CMP_MOD_EQ
* - RB_ADC_CMP_MOD_GT
* en
* - ENABLE
* - DISABLE
* @return none
*/
#define ADC_IT_CONFIG(RB_ADC_IE, en) \
({ (en) == ENABLE ? (R8_ADC_INTER_EN |= (RB_ADC_IE)) : (R8_ADC_INTER_EN &= ~(RB_ADC_IE)); })
/***********************************************************************************
* @fn ADC_SET_12BITRESOLUTION
*
* @brief ADC 12bit resolution enable
*
* @param en
* - ENABLE
* - DISABLE
* @return none
*/
#define ADC_SET_12BITRESOLUTION(en) \
({ (en) == ENABLE ? (R32_ADC_CTRL |= MASK_ADC_BIT_MODE) : (R32_ADC_CTRL &= ~MASK_ADC_BIT_MODE); })
/***********************************************************************************
* @fn ADC_SET_SAMPLE_TIME
*
* @brief Config ADC sample calibration time.
*
* @param val
* - ADC sample calibration time
* @return none
*/
#define ADC_SET_SAMPLE_TIME(val) \
({ \
R32_ADC_CTRL &= ~MASK_ADC_SMAPLE_TIME; \
R32_ADC_CTRL |= MASK_ADC_SMAPLE_TIME & ((val) << 4); \
})
/***********************************************************************************
* @fn ADC_DMA_SET_RANGE
*
* @brief Config ADC DMA transport range
*
* @param startAddress
* - ADC DMA Handling Start Address
* endAddress
* - ADC DMA Handling End Address
* @return none
*/
#define ADC_DMA_SET_RANGE(startAddress, endAddress) \
({ \
R32_ADC_DMA_BEG = (uint32_t)(startAddress) & MASK_ADC_DMA_ADDR; \
R32_ADC_DMA_END = (uint32_t)(endAddress) & MASK_ADC_DMA_ADDR; \
})
/***********************************************************************************
* @fn ADC_DMA_GET_CURRENT
*
* @brief Get ADC DMA current transport address
*
* @return R32_ADC_DMA_NOW
*/
#define ADC_DMA_GET_CURRENT() (R32_ADC_DMA_NOW & MASK_ADC_DMA_ADDR)
/***********************************************************************************
* @fn ADC_DMA_GET_BEGIN
*
* @brief Get ADC DMA start transport address
*
* @return R32_ADC_DMA_BEG
*/
#define ADC_DMA_GET_BEGIN() (R32_ADC_DMA_BEG & MASK_ADC_DMA_ADDR)
/***********************************************************************************
* @fn ADC_DMA_GET_END
*
* @brief Get ADC DMA end transport address
*
* @return R32_ADC_DMA_END
*/
#define ADC_DMA_GET_END() (R32_ADC_DMA_END & MASK_ADC_DMA_ADDR)
/***********************************************************************************
* @fn ADC_GET_FIFO
*
* @brief Get ADC's FIFO content
*
* @return R16_ADC_FIFO
*/
#define ADC_GET_FIFO() (R16_ADC_FIFO)
/***********************************************************************************
* @fn ADC_SET_COMPARE_VAL
*
* @brief Config ADC comparison reference value
*
* @param val
* - ADC comparison reference value
* @return none
*/
#define ADC_SET_COMPARE_VAL(val) ({ R16_ADC_CMP_VALUE = ADC_CMP_VALUE & (val); })
/***********************************************************************************
* @fn ADC_GET_FIFO_CNT
*
* @brief Get ADC's FIFO count
*
* @return R8_ADC_FIFO_COUNT
*/
#define ADC_GET_FIFO_CNT() (R8_ADC_FIFO_COUNT)
/***********************************************************************************
* @fn ADC_GET_VAL
*
* @brief Get ADC's converted value
*
* @return R16_ADC_DATA
*/
#define ADC_GET_VAL() (R16_ADC_DATA)
/***********************************************************************************
* @fn ADC_SET_DIV
*
* @brief Config ADC crossover coefficients
*
* @param val
* - ADC crossover coefficients
* @return none
*/
#define ADC_SET_DIV(value) ({ R8_ADC_CLOCK_DIV = (value); })
/***********************************************************************************
* @fn ADC_CLEAR_IT
*
* @brief Config ADC crossover coefficients
*
* @param RB_ADC_IF
* - RB_ADC_IF_ADC_CMP
* - RB_ADC_IF_ADC_END
* - RB_ADC_IF_FIFO_HF
* - RB_ADC_IF_DMA_END
* - RB_ADC_IF_FIFO_OV
* - RB_ADC_IF_DMA_ERR
* - RB_ADC_EOC_FLAG
* - RB_ADC_CHAN_INDEX
* en
* - ENABLE
* - DISABLE
*/
#define ADC_CLEAR_IT(RB_ADC_IF) ({ R8_ADC_INT_FLAG |= (RB_ADC_IF); })
/***********************************************************************************
* @fn ADC_GET_IT
*
* @brief Config ADC crossover coefficients
*
* @param RB_ADC_IF
* - RB_ADC_IF_ADC_CMP
* - RB_ADC_IF_ADC_END
* - RB_ADC_IF_FIFO_HF
* - RB_ADC_IF_DMA_END
* - RB_ADC_IF_FIFO_OV
* - RB_ADC_IF_DMA_ERR
* - RB_ADC_EOC_FLAG
* - RB_ADC_CHAN_INDEX
* @return 0:No Interrupt or interrupt flag
*
*/
#define ADC_GET_IT(RB_ADC_IF) (R8_ADC_INT_FLAG & (RB_ADC_IF))
/***********************************************************************************
* @fn ADC_MEASURE
*
* @brief Manually initiated measurements
*
* @return none
*/
#define ADC_MEASURE() ({ R8_ADC_CTRL_DMA |= RB_ADC_MAN_SAMPLE; })
void ADC_SelectChannel(ADCChannelTypedef adcChannel);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_GPIO_H
#define __CH564_GPIO_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
#define GPIO_Pin_0 (0x00000001)/*!< Pin 0 selected */
#define GPIO_Pin_1 (0x00000002)/*!< Pin 1 selected */
#define GPIO_Pin_2 (0x00000004)/*!< Pin 2 selected */
#define GPIO_Pin_3 (0x00000008)/*!< Pin 3 selected */
#define GPIO_Pin_4 (0x00000010)/*!< Pin 4 selected */
#define GPIO_Pin_5 (0x00000020)/*!< Pin 5 selected */
#define GPIO_Pin_6 (0x00000040)/*!< Pin 6 selected */
#define GPIO_Pin_7 (0x00000080)/*!< Pin 7 selected */
#define GPIO_Pin_8 (0x00000100)/*!< Pin 8 selected */
#define GPIO_Pin_9 (0x00000200)/*!< Pin 9 selected */
#define GPIO_Pin_10 (0x00000400)/*!< Pin 10 selected */
#define GPIO_Pin_11 (0x00000800)/*!< Pin 11 selected */
#define GPIO_Pin_12 (0x00001000)/*!< Pin 12 selected */
#define GPIO_Pin_13 (0x00002000)/*!< Pin 13 selected */
#define GPIO_Pin_14 (0x00004000)/*!< Pin 14 selected */
#define GPIO_Pin_15 (0x00008000)/*!< Pin 15 selected */
#define GPIO_Pin_16 (0x00010000)/*!< Pin 16 selected */
#define GPIO_Pin_17 (0x00020000)/*!< Pin 17 selected */
#define GPIO_Pin_18 (0x00040000)/*!< Pin 18 selected */
#define GPIO_Pin_19 (0x00080000)/*!< Pin 19 selected */
#define GPIO_Pin_20 (0x00100000)/*!< Pin 20 selected */
#define GPIO_Pin_21 (0x00200000)/*!< Pin 21 selected */
#define GPIO_Pin_22 (0x00400000)/*!< Pin 22 selected */
#define GPIO_Pin_23 (0x00800000)/*!< Pin 23 selected */
#define GPIO_Pin_24 (0x01000000)/*!< Pin 24 selected */
#define GPIO_Pin_25 (0x02000000)/*!< Pin 25 selected */
#define GPIO_Pin_26 (0x04000000)/*!< Pin 26 selected */
#define GPIO_Pin_27 (0x08000000)/*!< Pin 27 selected */
#define GPIO_Pin_28 (0x10000000)/*!< Pin 28 selected */
#define GPIO_Pin_29 (0x20000000)/*!< Pin 29 selected */
#define GPIO_Pin_30 (0x40000000)/*!< Pin 30 selected */
#define GPIO_Pin_31 (0x80000000)/*!< Pin 31 selected */
#define GPIO_Pin_All (0xFFFFFFFF)/*!< All pins selected */
#define GPIO_NoRemap_SPI0 (0x00020000)
#define GPIO_PartialRemap1_SPI0 (0x00020001)
#define GPIO_PartialRemap2_SPI0 (0x00020002)
#define GPIO_FullRemap_SPI0 (0x00020003)
#define GPIO_NoRemap_UART0 (0x00220000)
#define GPIO_PartialRemap2_UART0 (0x00220002)
#define GPIO_FullRemap_UART0 (0x00220003)
#define GPIO_NoRemap_UART1 (0x00420000)
#define GPIO_PartialRemap1_UART1 (0x00420001)
#define GPIO_FullRemap_UART1 (0x00420003)
#define GPIO_NoRemap_UART2 (0x00620000)
#define GPIO_PartialRemap1_UART2 (0x00620001)
#define GPIO_PartialRemap2_UART2 (0x00620002)
#define GPIO_FullRemap_UART2 (0x00620003)
#define GPIO_NoRemap_UART3 (0x00820000)
#define GPIO_PartialRemap1_UART3 (0x00820001)
#define GPIO_FullRemap_UART3 (0x00820003)
#define GPIO_NoRemap_UART0_MODEM (0x00a20000)
#define GPIO_PartialRemap1_UART0_MODEM (0x00a20001)
#define GPIO_PartialRemap2_UART0_MODEM (0x00a20002)
#define GPIO_FullRemap_UART0_MODEM (0x00a20003)
#define GPIO_NoRemap_UART1_MODEM (0x00c20000)
#define GPIO_PartialRemap1_UART1_MODEM (0x00c20001)
#define GPIO_PartialRemap2_UART1_MODEM (0x00c20002)
#define GPIO_FullRemap_UART1_MODEM (0x00c20003)
#define GPIO_NoRemap_UART2_MODEM (0x00e20000)
#define GPIO_PartialRemap2_UART2_MODEM (0x00e20002)
#define GPIO_FullRemap_UART2_MODEM (0x00e20003)
#define GPIO_NoRemap_I2C (0x01020000)
#define GPIO_PartialRemap1_I2C (0x01020001)
#define GPIO_NoRemap_SLV_INTERUPT (0x01220000)
#define GPIO_PartialRemap1_SLV_INTERUPT (0x01220001)
#define GPIO_PartialRemap2_SLV_INTERUPT (0x01220002)
#define GPIO_FullRemap_SLV_INTERUPT (0x01220003)
#define GPIO_NoRemap_SLV_CS (0x01420000)
#define GPIO_PartialRemap1_SLV_CS (0x01420001)
#define GPIO_NoRemap_SLV_ADDR (0x01620000)
#define GPIO_PartialRemap1_SLV_ADDR (0x01620001)
#define GPIO_PartialRemap2_SLV_ADDR (0x01620002)
#define GPIO_NoRemap_SLV_ADDR1 (0x01820000)
#define GPIO_PartialRemap2_SLV_ADDR1 (0x01820002)
#define GPIO_FullRemap_SLV_ADDR1 (0x01820003)
#define GPIO_NoRemap_SLV_DATA (0x01a20000)
#define GPIO_PartialRemap1_SLV_DATA (0x01a20001)
#define GPIO_NoRemap_SLV_RW (0x01c20000)
#define GPIO_NolRemap_SLV_RW GPIO_NoRemap_SLV_RW
#define GPIO_PartialRemap1_SLV_RW (0x01c20001)
#define GPIO_NoRemap_LINK_LED (0x01e20000)
#define GPIO_PartialRemap1_LINK_LED (0x01e20001)
#define GPIO_PartialRemap2_LINK_LED (0x01e20002)
#define GPIO_FullRemap_LINK_LED (0x01e20003)
#define GPIO_NoRemap_ACT_LED (0x80020000)
#define GPIO_PartialRemap1_ACT_LED (0x80020001)
#define GPIO_PartialRemap2_ACT_LED (0x80020002)
#define GPIO_FullRemap_ACT_LED (0x80020003)
#define GPIO_NoRemap_RST (0x80220000)
#define GPIO_PartialRemap1_RST (0x80220001)
#define GPIO_PartialRemap2_RST (0x80220002)
#define GPIO_FullRemap_RST (0x80220003)
#define GPIO_NoRemap_TIMER0 (0x80410000)
#define GPIO_FullRemap_TIMER0 (0x80410001)
#define GPIO_NoRemap_TIMER1 (0x80510000)
#define GPIO_FullRemap_TIMER1 (0x80510001)
#define GPIO_NoRemap_BUSY (0x80610000)
#define GPIO_FullRemap_BUSY (0x80610001)
#define GPIO_NoRemap_SPI1 (0x80820000)
#define GPIO_FullRemap_SPI1 (0x80820003)
#define GPIO_NoRemap_TNOW0 (0x80a20000)
#define GPIO_FullRemap_TNOW0 (0x80a20003)
#define GPIO_NoRemap_TNOW1 (0x80c20000)
#define GPIO_FullRemap_TNOW1 (0x80c20003)
#define GPIO_NoRemap_TNOW2 (0x80e20000)
#define GPIO_FullRemap_TNOW2 (0x80e20003)
#define GPIO_NoRemap_TNOW3 (0x81020000)
#define GPIO_FullRemap_TNOW3 (0x81020003)
#define GPIO_NoRemap_UART3_MODEM (0x81220000)
#define GPIO_FullRemap_UART3_MODEM (0x81220003)
/**
* @brief GPIO mode structure configuration
*/
typedef enum
{
GPIO_ModeIN_Floating = 0,
GPIO_ModeIN_PU,
GPIO_ModeIN_PD,
GPIO_ModeOut_PP,
GPIO_ModeOut_OP
} GPIOModeTypeDef;
/**
* @brief GPIO interrupt structure configuration
*/
typedef enum
{
GPIO_ITMode_LowLevel = 0, // Low level trigger
GPIO_ITMode_HighLevel, // High level trigger
GPIO_ITMode_FallEdge, // Falling edge trigger
GPIO_ITMode_RiseEdge, // Rising edge trigger
GPIO_ITMode_None
} GPIOITModeTpDef;
/**
* @brief GPIO MCO structure configuration
*/
typedef enum
{
MCO_125 = 0,
MCO_25 = 4,
MCO_2d5 = 0xC,
} MCOMode;
void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOA port pin mode configuration */
void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */
void GPIOD_ModeCfg(uint32_t pin, GPIOModeTypeDef mode); /* GPIOB port pin mode configuration */
#define GPIOA_ResetBits(pin) (R32_PA_CLR |= pin) /* GPIOA port pin output set low */
#define GPIOA_SetBits(pin) (R32_PA_OUT |= pin) /* GPIOA port pin output set high */
#define GPIOB_ResetBits(pin) (R32_PB_CLR |= pin) /* GPIOB port pin output set low */
#define GPIOB_SetBits(pin) (R32_PB_OUT |= pin) /* GPIOB port pin output set high */
#define GPIOD_ResetBits(pin) (R32_PD_OUT &= ~pin) /* GPIOA port pin output set low */
#define GPIOD_SetBits(pin) (R32_PD_OUT |= pin) /* GPIOA port pin output set high */
#define GPIOA_InverseBits(pin) (R32_PA_OUT ^= pin) /* GPIOA port pin output level flip */
#define GPIOB_InverseBits(pin) (R32_PB_OUT ^= pin) /* GPIOB port pin output level flip */
#define GPIOD_InverseBits(pin) (R32_PD_OUT ^= pin) /* GPIOB port pin output level flip */
#define GPIOA_ReadPort() (R32_PA_PIN) /* The 32-bit data returned by the GPIOA port, the lower 16 bits are valid */
#define GPIOB_ReadPort() (R32_PB_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */
#define GPIOD_ReadPort() (R32_PD_PIN) /* The 32-bit data returned by the GPIOB port, the lower 24 bits are valid */
#define GPIOA_ReadPortPin(pin) (R32_PA_PIN & pin) /* GPIOA port pin status, 0-pin low level, (!0)-pin high level */
#define GPIOB_ReadPortPin(pin) (R32_PB_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */
#define GPIOD_ReadPortPin(pin) (R32_PD_PIN & pin) /* GPIOB port pin status, 0-pin low level, (!0)-pin high level */
void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOA pin interrupt mode configuration */
void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */
void GPIOD_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode); /* GPIOB pin interrupt mode configuration */
#define GPIOA_ReadITFlagPort() (R32_INT_STATUS_PA) /* Read GPIOA port interrupt flag status */
#define GPIOB_ReadITFlagPort() (R32_INT_STATUS_PB) /* Read GPIOB port interrupt flag status */
#define GPIOD_ReadITFlagPort() (R32_INT_STATUS_PD) /* Read GPIOD port interrupt flag status */
/*************************************Read Interrupt Bit Flag************************************/
#define GPIOA_ReadITFLAGBit(pin) (R32_INT_STATUS_PA & pin)
#define GPIOB_ReadITFLAGBit(pin) (R32_INT_STATUS_PB & pin)
#define GPIOD_ReadITFLAGBit(pin) (R32_INT_STATUS_PD & pin)
/*************************************Clear Interrupt Bit Flag************************************/
#define GPIOA_ClearITFlagbit(pin) (R32_INT_STATUS_PA |= pin)
#define GPIOB_ClearITFlagbit(pin) (R32_INT_STATUS_PB |= pin)
#define GPIOD_ClearITFlagbit(pin) (R32_INT_STATUS_PD |= pin)
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewSTA);
void GPIO_IPD_Unused(void);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_i2c.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_I2C_H
#define __CH564_I2C_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/* I2C Init structure definition */
typedef struct
{
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /* Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
} I2C_InitTypeDef;
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
/* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
/* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
/* STAR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* STAR1 register flags */
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
/****************I2C Master Events (Events grouped in order of communication)********************/
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_Typedef *I2Cx);
void I2C_Init(I2C_Typedef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
void I2C_Cmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_Typedef *I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_Typedef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_Typedef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_Typedef *I2Cx);
void I2C_Send7bitAddress(I2C_Typedef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_Typedef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_TransmitPEC(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_Typedef *I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_Typedef *I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_Typedef *I2Cx);
void I2C_ARPCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_Typedef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_Typedef *I2Cx, uint16_t I2C_DutyCycle);
/****************************************************************************************
* I2C State Monitoring Functions
****************************************************************************************/
ErrorStatus I2C_CheckEvent(I2C_Typedef *I2Cx, uint32_t I2C_EVENT);
uint32_t I2C_GetLastEvent(I2C_Typedef *I2Cx);
FlagStatus I2C_GetFlagStatus(I2C_Typedef *I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_Typedef *I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_Typedef *I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_Typedef *I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* PWR firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_PWR_H
#define __CH564_PWR_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define WDOG_ENABLE() \
{ \
R8_SAFE_ACCESS_SIG = 0x57; \
R8_SAFE_ACCESS_SIG = 0xA8; \
R8_GLOB_RST_CFG |= (0x40 | RB_GLOB_WDOG_EN); \
R8_SAFE_ACCESS_SIG = 0x00; \
}
#define WDOG_DISABLE() \
{ \
R8_SAFE_ACCESS_SIG = 0x57; \
R8_SAFE_ACCESS_SIG = 0xA8; \
R8_GLOB_RST_CFG = 0x40; \
R8_SAFE_ACCESS_SIG = 0x00; \
}
#define FEED_DOG() (R8_WDOG_CLEAR = 0)
#define VIO_PWN_INT_CMD(cmd) \
{ \
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_INT_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_INT_EN); \
}
#define VIO_PWN_RST_CMD(cmd) \
{ \
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_RST_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_RST_EN); \
}
#define VIO_PWN_IO_CMD(cmd) \
{ \
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_VIO_PWN_IO_EN) : (R32_EXTEN_CTLR1 &= ~RB_VIO_PWN_IO_EN); \
}
#define LDO_DORMENCY_EN(cmd) \
{ \
cmd == ENABLE ? (R32_EXTEN_CTLR1 |= RB_LDO_SLP_EN) : (R32_EXTEN_CTLR1 &= ~RB_LDO_SLP_EN); \
}
void PWR_Sleep(uint8_t PWR_STOPEntry);
void PWR_DeepSleep(uint8_t PWR_STOPEntry);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* RCC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_RCC_H
#define __CH564_RCC_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
#define RCC_UNLOCK_SAFE_ACCESS() \
({ \
R8_SAFE_ACCESS_SIG = 0x57; \
R8_SAFE_ACCESS_SIG = 0xA8; \
__NOP(); \
})
#define RCC_LOCK_SAFE_ACCESS() ({ R8_SAFE_ACCESS_SIG = 0x0; })
#define RCC_GET_ID_SAFELY() (R8_SAFE_ACCESS_ID)
#define RCC_CLEAR_WDOG() ({ R8_WDOG_CLEAR = 0; })
#define HSI_ON() (R32_EXTEN_CTLR1 |= RB_HSION)
#define HSE_ON() (R32_EXTEN_CTLR1 |= RB_HSEON)
#define HSE_GET_STTATEUS() ((R32_EXTEN_CTLR1 & 0x8000) != 0 ? 1 : 0)
#define HSI_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSION)
#define HSE_OFF() (R32_EXTEN_CTLR1 &= ~RB_HSEON)
#define USB_PLL_ON() \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 |= (RB_USBPLLON); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define USB_PLL_OFF() \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define USB_PLL_MUL_15 0x0000c000
#define USB_PLL_MUL_16 0x00008000
#define USB_PLL_MUL_20 0x00004000
#define USB_PLL_MUL_24 0x00000000
#define USB_PLL_MUL_SELECT(USB_PLL_MUL) \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 &= ~USB_PLL_MUL_15; \
R32_EXTEN_CTLR0 |= (USB_PLL_MUL); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define USB_PLL_SOURCE_HSI 0x00000060
#define USB_PLL_SOURCE_HSE 0x00000020
#define USB_PLL_SOURCE_ETH_PLL_OUT 0x00000040
#define USB_PLL_SOURCE_SELECT(USB_PLL_SOURCE) \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 &= ~USB_PLL_SOURCE_HSI; \
R32_EXTEN_CTLR0 |= (USB_PLL_SOURCE); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define CLKSEL_HSI() \
{ \
R32_EXTEN_CTLR1 &= ~(RB_CLKSEL); \
}
#define CLKSEL_HSE() \
{ \
R32_EXTEN_CTLR1 |= (RB_CLKSEL); \
}
#define USB_PLL_ON() \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 |= (RB_USBPLLON); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define USB_PLL_OFF() \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
R32_EXTEN_CTLR0 &= ~(RB_USBPLLON); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define SYSCLK_SOURCE_USBPLL 0
#define SYSCLK_SOURCE_HSI_HSE 1
#define SYSCLK_SOURCE_SELECT(SYSCLK_SOURCE) \
{ \
RCC_UNLOCK_SAFE_ACCESS(); \
((SYSCLK_SOURCE) == SYSCLK_SOURCE_HSI_HSE) ? (R32_EXTEN_CTLR0 |= (RB_SW)) : (R32_EXTEN_CTLR0 &= ~(RB_SW)); \
RCC_LOCK_SAFE_ACCESS(); \
}
#define RCC_GET_GLOB_RST_KEEP() (R8_GLOB_RESET_KEEP)
#define RCC_SET_GLOB_RST_KEEP(val) (R8_GLOB_RESET_KEEP = (val);)
#define RCC_SET_PLL_SYS_OUT_DIV(val) \
({ \
RCC_UNLOCK_SAFE_ACCESS(); \
R8_PLL_OUT_DIV = 0x04 | ((val) << 4); \
RCC_LOCK_SAFE_ACCESS(); \
})
#define RCC_FLASH_CLK_PRE_DIV(sta) \
({ \
RCC_UNLOCK_SAFE_ACCESS(); \
((sta) == ENABLE) ? (R32_EXTEN_CTLR0 |= 0x00200000) : (R32_EXTEN_CTLR0 &= ~0x00200000) RCC_LOCK_SAFE_ACCESS(); \
})
typedef enum
{
Code16k_Data128k = 0x0,
Code48k_Data96k = 0x1,
Code80k_Data64k = 0x2
} GlobMem_Cfg;
void RCC_SetGlobalMemCFG(GlobMem_Cfg Cfg);
void RCC_LockPort(uint8_t globport, FunctionalState NewSTA);
void RCC_GlobleRstCFG(uint8_t cfg, FunctionalState NewSTA);
void RCC_SlpClkOff(volatile uint8_t *reg, uint8_t slpclk, FunctionalState NewSTA);
void RCC_SlpWakeCtrl(uint8_t slpwake, FunctionalState NewSTA);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_slv.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* SLV firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_SLV_H
#define __CH564_SLV_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
typedef enum
{
slv_data,
slv_cmd,
slv_timeout
} SLV_STA;
#define SLV_CFG(cfglist, en) (BITS_CFG(R8_SLV_CONFIG, cfglist, en))
#define SLV_SEND_DATA(data) (R8_SLV_DOUT = (data))
#define SLV_SEND_STA(status) (R8_SLV_STATUS = (status))
#define SLV_GET_IF(RB_IF_SLV) (R8_INT_FLAG_SLV & (RB_IF_SLV))
#define SLV_CLEAR_IF(RB_IF_SLV) (R8_INT_FLAG_SLV |= (RB_IF_SLV))
#define SLV_GET_DATA() (R8_INT_SLV_DIN)
#define SLV_DMA_CFG(cfglist, en) (BITS_CFG(R8_DMA_EN_SLV, cfglist, en))
#define SLV_SET_MODE_CTRL(cfglist, en) (BITS_CFG(R8_DMA_MODE_CTRL_SLV, cfglist, en))
#define SLV_SET_MODE_EN(cfglist, en) (BITS_CFG(R8_DMA_MODE_EN_SLV, cfglist, en))
#define SLV_DMA_GET_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV & (slv_dma_if))
#define SLV_DMA_CLEAR_IF(slv_dma_if) (R8_DMA_INT_FLAG_SLV |= (slv_dma_if))
#define SLV_DMA_START_ADDR_RD(address) (R32_RD_DMA_START_ADDR_SLV = (uint32_t)(address))
#define SLV_DMA_END_ADDR_RD(address) (R32_RD_DMA_END_ADDR_SLV = (uint32_t)(address))
#define SLV_DMA_START_ADDR_WR(address) (R32_WR_DMA_START_ADDR_SLV = (uint32_t)(address))
#define SLV_DMA_END_ADDR_WR(address) (R32_WR_DMA_END_ADDR_SLV = (uint32_t)(address))
#define SLV_DMA_GET_NOW_ADDR() (R32_DMA_END_NOW_SLV)
#define SLV_SET_DMA_CMD0(cmd) (R8_DMA_CMD0_SLV = (cmd))
#define SLV_SET_DMA_CMD1(cmd) (R8_DMA_CMD1_SLV = (cmd))
#define SLV_SET_RST_CMD(cmd) (R8_SLV_RESET_CMD = (cmd))
#define SLV_GET_OTHER_DATA() (R8_OTHER_DATA)
#define SLV_GET_DMA_DEC_LEN() (R16_DMA_DEC_LEN)
#define SLV_GET_DMA_DEC_OFFSET() (R16_DMA_DEC_OFFSET)
SLV_STA SLV_Read(uint8_t *dataAddress, uint16_t dataSize, uint16_t timeout);
ErrorStatus SLV_SendDATA(uint8_t *data, uint16_t datasize);
ErrorStatus SLV_SendSTA(uint8_t *sta, uint16_t datasize);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_SPI_H
#define __CH564_SPI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/**
* @brief SPI0 interrupt bit define
*/
#define SPI0_IT_FST_BYTE RB_SPI_IE_FST_BYTE
#define SPI0_IT_FIFO_OV RB_SPI_IE_FIFO_OV
#define SPI0_IT_DMA_END RB_SPI_IE_DMA_END
#define SPI0_IT_FIFO_HF RB_SPI_IE_FIFO_HF
#define SPI0_IT_BYTE_END RB_SPI_IE_BYTE_END
#define SPI0_IT_CNT_END RB_SPI_IE_CNT_END
#define SPI_MAX_DELAY 0xffff
/**
* @brief Configuration data mode
*/
typedef enum
{
Mode0_HighBitINFront,
Mode3_HighBitINFront,
} ModeBitOrderTypeDef;
/**
* @brief Configuration SPI slave mode
*/
typedef enum
{
Mode_DataStream = 0,
Mose_FirstCmd,
} Slave_ModeTypeDef;
/**************** SPI0 */
void SPI0_MasterInit(uint32_t clockRate);
void SPI0_DataMode(ModeBitOrderTypeDef mode);
void SPI0_MasterSendByte(uint8_t data);
uint8_t SPI0_MasterRecvByte(void);
void SPI0_MasterTrans(uint8_t *pbuf, uint16_t len);
void SPI0_MasterRecv(uint8_t *pbuf, uint16_t len);
void SPI0_DMATrans(uint8_t *pbuf, uint32_t len);
void SPI0_DMARecv(uint8_t *pbuf, uint32_t len);
void SPI0_MasterTransRecv(uint8_t *ptbuf, uint8_t *prbuf, uint16_t len);
void SPI0_SlaveInit();
#define SetFirst0Data(data) (R8_SPI0_SLAVE_PRE = (data))
void SPI0_SlaveSendByte(uint8_t data);
uint8_t SPI0_SlaveRecvByte(void);
uint8_t SPI0_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
uint8_t SPI0_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
// refer to SPI0 interrupt bit define
#define SPI0_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI0_CTRL_MOD, cfglist, en)
#define SPI0_ITCfg(cfglist, en) BITS_CFG(R8_SPI0_INTER_EN, cfglist, en)
#define SPI0_SET_CLOCK_DIV(div) (R8_SPI0_CLOCK_DIV = (div))
#define SPI0_GetITFlag(f) (R8_SPI0_INT_FLAG & (f))
#define SPI0_ClearITFlag(f) (R8_SPI0_INT_FLAG = (f))
#define SPI0_SET_RST(dat) (R8_SPI0_RESET_CMD = (dat))
#define SPI0_GET_RST() (R8_SPI0_RESET_CMD)
#define SPI0_GET_BUSY() (R8_SPI0_BUSY)
#define SPI0_GET_BUFFER() (R8_SPI0_BUFFER)
#define SPI0_SET_BUFFER(dat) (R8_SPI0_BUFFER = (dat))
#define SPI0_CLEAR_FIFO() (R8_SPI0_CTRL_MOD |= RB_SPI_ALL_CLEAR);
#define SPI0_GET_FIFO() (R8_SPI0_FIFO)
#define SPI0_SET_FIFO(dat) (R8_SPI0_FIFO = (dat))
#define SPI0_SET_FIFO_CNT(cnt) (R8_SPI0_FIFO_COUNT = (cnt))
#define SPI0_GET_FIFO_CNT() (R8_SPI0_FIFO_COUNT)
#define SPI0_SET_TOTAL_CNT(cnt) (R16_SPI0_TOTAL_CNT = (cnt) )
#define SPI0_GET_TOTAL_CNT() (R16_SPI0_TOTAL_CNT)
#define SPI0_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI0_CTRL_DMA, cfglist, en)
#define SPI0_SET_DMA_RANGE(start, end) \
({ \
R32_SPI0_DMA_BEG = (uint32_t)(start) & MASK_SPI0_DMA_ADDR; \
R32_SPI0_DMA_END = (uint32_t)(end) & MASK_SPI0_DMA_ADDR; \
})
/**************** SPI1 */
void SPI1_MasterInit(uint32_t clockRate);
void SPI1_DataMode(ModeBitOrderTypeDef mode);
void SPI1_MasterSendByte(uint8_t data);
uint8_t SPI1_MasterRecvByte(void);
void SPI1_MasterTrans(uint8_t *pbuf, uint16_t len);
void SPI1_MasterRecv(uint8_t *pbuf, uint16_t len);
void SPI1_SlaveInit();
#define SetFirst1Data(data) (R8_SPI1_SLAVE_PRE = (data))
void SPI1_SlaveSendByte(uint8_t data);
uint8_t SPI1_SlaveRecvByte(void);
uint8_t SPI1_SlaveTrans(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
uint8_t SPI1_SlaveRecv(uint8_t *pbuf, uint16_t len,uint16_t timeouts);
// refer to SPI1 interrupt bit define
#define SPI1_MODE_CFG(cfglist, en) BITS_CFG(R8_SPI1_CTRL_MOD, cfglist, en)
#define SPI1_ITCfg(cfglist, en) BITS_CFG(R8_SPI1_INTER_EN, cfglist, en)
#define SPI1_SET_CLOCK_DIV(div) (R8_SPI1_CLOCK_DIV = (div))
#define SPI1_GetITFlag(f) (R8_SPI1_INT_FLAG & (f))
#define SPI1_ClearITFlag(f) (R8_SPI1_INT_FLAG = (f))
#define SPI1_GET_BUFFER() (R8_SPI1_BUFFER)
#define SPI1_SET_BUFFER(dat) (R8_SPI1_BUFFER = (dat))
#define SPI1_CLEAR_FIFO() (R8_SPI1_CTRL_MOD |= RB_SPI_ALL_CLEAR);
#define SPI1_GET_FIFO() (R8_SPI1_FIFO)
#define SPI1_SET_FIFO(dat) (R8_SPI1_FIFO = (dat))
#define SPI1_SET_FIFO_CNT(cnt) (R8_SPI1_FIFO_COUNT = (cnt))
#define SPI1_GET_FIFO_CNT() (R8_SPI1_FIFO_COUNT)
#define SPI1_SET_TOTAL_CNT(cnt) (R16_SPI1_TOTAL_CNT = (cnt))
#define SPI1_GET_TOTAL_CNT() (R16_SPI1_TOTAL_CNT)
#define SPI1_SET_DMA_MODE(cfglist, en) BITS_CFG(R8_SPI1_CTRL_DMA, (cfglist), (en))
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_TIM_H
#define __CH564_TIM_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/**
* @brief Pulse Width Modulation Effective Output Words
*/
typedef enum
{
PWM_Times_1 = 0, // PWM effective output repeats 1 times
PWM_Times_4 = 1, // PWM effective output repeats 4 times
PWM_Times_8 = 2, // PWM effective output repeats 8 times
PWM_Times_16 = 3, // PWM effective output repeats 16 times
} PWM_RepeatTsTypeDef;
/**
* @brief Input Capture Edge Mode
*/
typedef enum
{
CAP_NULL = 0, // not capture
Edge_To_Edge = 1, // between any edge
FallEdge_To_FallEdge = 2, // falling edge to falling edge
RiseEdge_To_RiseEdge = 3, // rising edge to rising edge
} CapModeTypeDef;
/**
* @brief Input Capture Edge Mode
*/
typedef enum
{
clock16 = 0,
clock8
} CapWidthTypedef;
/**
* @brief Direct access memory loop mode
*/
typedef enum
{
Mode_Single = 0, // single mode
Mode_LOOP = 1, // cycle mode
Mode_Burst = 2,
Mode_Burst_Loop = 3
} DMAModeTypeDef;
/**
* @brief PWM output polarity
*/
typedef enum
{
high_on_low = 0, // Default low level, high level is active
low_on_high = 1, // Default high level, low level active
} PWM_PolarTypeDef;
/****************** TMR0 */
// Timing and counting
void TMR0_TimerInit(uint32_t arr); /* Timing function initialization */
#define TMR0_DeInit() (R8_TMR0_CTRL_MOD = 0)
#define TMR0_GetCurrentCount() R32_TMR0_COUNT /* Get the current count value, 67108864 */
#define TMR0_ClrCurrentCount() {R8_TMR0_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR0_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
#define TMR0_SET_CNT_END(cnt_end) ({R32_TMR0_CNT_END = (cnt_end);})
// Pulse Width Modulation Function
#define TMR0_PWMCycleCfg(cyc) \
(R32_TMR0_CNT_END = (cyc)) /* PWM0 channel output waveform period configuration, maximum 67108864 */
void TMR0_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM0 output initialization */
#define TMR0_PWMActDataWidth(d) (R32_TMR0_FIFO = (d)) /* PWM0 effective data pulse width, maximum 67108864 */
// Catch pulse width
#define TMR0_CAPTimeoutCfg(cyc) \
(R32_TMR0_CNT_END = (cyc)) /* CAP0 capture level timeout configuration, maximum 33554432 */
void TMR0_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
#define TMR0_CAPGetData() R32_TMR0_FIFO /* Get pulse data */
#define TMR0_CAPDataCounter() R8_TMR0_FIFO_COUNT /* Get the number of currently captured data */
void TMR0_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
#define TMR0_Disable() (R8_TMR0_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR0 */
#define TMR0_Enable() (R8_TMR0_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR0 */
// refer to TMR0 interrupt bit define
#define TMR0_ITCfg(cfglist, en) \
BITS_CFG(R8_TMR0_INTER_EN, (cfglist), (en)) /* TMR0 corresponding interrupt bit on and off */
// refer to TMR0 interrupt bit define
#define TMR0_ClearITFlag(f) (R8_TMR0_INT_FLAG = (f)) /* Clear interrupt flag */
#define TMR0_GetITFlag(f) (R8_TMR0_INT_FLAG & (f)) /* Query interrupt flag status */
#define TMR0_DMA_SET_RANGE(start, end) \
({ \
R32_TMR0_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
R32_TMR0_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
})
#define TMR0_DMA_GET_BEG() (R32_TMR0_DMA_BEG)
#define TMR0_DMA_GET_END() (R32_TMR0_DMA_END)
#define TMR0_DMA_GET_NOW() (R32_TMR0_DMA_NOW)
/****************** TMR1 */
// Timing and counting
void TMR1_TimerInit(uint32_t arr); /* Timing function initialization */
#define TMR1_DeInit() (R8_TMR1_CTRL_MOD = 0)
#define TMR1_GetCurrentCount() R32_TMR1_COUNT /* Get the current count value, 67108864 */
#define TMR1_ClrCurrentCount() {R8_TMR1_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR1_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
#define TMR1_SET_CNT_END(cnt_end) ({R32_TMR1_CNT_END = (cnt_end);})
// Pulse Width Modulation Function
#define TMR1_PWMCycleCfg(cyc) \
(R32_TMR1_CNT_END = (cyc)) /* PWM1 channel output waveform period configuration, maximum 67108864 */
void TMR1_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM1 output initialization */
#define TMR1_PWMActDataWidth(d) (R32_TMR1_FIFO = (d)) /* PWM1 effective data pulse width, maximum 67108864 */
// Catch pulse width
#define TMR1_CAPTimeoutCfg(cyc) \
(R32_TMR1_CNT_END = (cyc)) /* CAP1 capture level timeout configuration, maximum 33554432 */
void TMR1_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
#define TMR1_CAPGetData() R32_TMR1_FIFO /* Get pulse data */
#define TMR1_CAPDataCounter() R8_TMR1_FIFO_COUNT /* Get the number of currently captured data */
void TMR1_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
#define TMR1_Disable() (R8_TMR1_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR1 */
#define TMR1_Enable() (R8_TMR1_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR1 */
// refer to TMR1 interrupt bit define
#define TMR1_ITCfg(cfglist, en) \
BITS_CFG(R8_TMR1_INTER_EN, (cfglist), (en)) /* TMR1 corresponding interrupt bit on and off */
// refer to TMR1 interrupt bit define
#define TMR1_ClearITFlag(f) (R8_TMR1_INT_FLAG = (f)) /* Clear interrupt flag */
#define TMR1_GetITFlag(f) (R8_TMR1_INT_FLAG & (f)) /* Query interrupt flag status */
#define TMR1_DMA_SET_RANGE(start, end) \
({ \
R32_TMR1_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
R32_TMR1_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
})
#define TMR1_DMA_GET_BEG() (R32_TMR1_DMA_BEG)
#define TMR1_DMA_GET_END() (R32_TMR1_DMA_END)
#define TMR1_DMA_GET_NOW() (R32_TMR1_DMA_NOW)
/****************** TMR2 */
// Timing and counting
void TMR2_TimerInit(uint32_t arr); /* Timing function initialization */
#define TMR2_DeInit() (R8_TMR2_CTRL_MOD = 0)
#define TMR2_GetCurrentCount() R32_TMR2_COUNT /* Get the current count value, 67108864 */
#define TMR2_ClrCurrentCount() {R8_TMR2_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR2_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
#define TMR2_SET_CNT_END(cnt_end) ({R32_TMR2_CNT_END = (cnt_end);})
// Pulse Width Modulation Function
#define TMR2_PWMCycleCfg(cyc) \
(R32_TMR2_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */
void TMR2_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */
#define TMR2_PWMActDataWidth(d) (R32_TMR2_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */
// Catch pulse width
#define TMR2_CAPTimeoutCfg(cyc) \
(R32_TMR2_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */
void TMR2_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
#define TMR2_CAPGetData() R32_TMR2_FIFO /* Get pulse data */
#define TMR2_CAPDataCounter() R8_TMR2_FIFO_COUNT /* Get the number of currently captured data */
void TMR2_DMACfg(FunctionalState NewSTA, uint32_t startAddr, uint32_t endAddr, DMAModeTypeDef DMAMode); /* DMA configuration */
#define TMR2_Disable() (R8_TMR2_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR2 */
#define TMR2_Enable() (R8_TMR2_CTRL_MOD |= RB_TMR_COUNT_EN) /* Open TMR2 */
// refer to TMR2 interrupt bit define
#define TMR2_ITCfg(cfglist, en) \
BITS_CFG(R8_TMR2_INTER_EN, (cfglist), (en)) /* TMR2 corresponding interrupt bit on and off */
// refer to TMR2 interrupt bit define
#define TMR2_ClearITFlag(f) (R8_TMR2_INT_FLAG = (f)) /* Clear interrupt flag */
#define TMR2_GetITFlag(f) (R8_TMR2_INT_FLAG & (f)) /* Query interrupt flag status */
#define TMR2_DMA_SET_RANGE(start, end) \
({ \
R32_TMR2_DMA_BEG = (start)&MASK_TMR_DMA_ADDR; \
R32_TMR2_DMA_END = (end)&MASK_TMR_DMA_ADDR; \
})
#define TMR2_DMA_GET_BEG() (R32_TMR2_DMA_BEG)
#define TMR2_DMA_GET_END() (R32_TMR2_DMA_END)
#define TMR2_DMA_GET_NOW() (R32_TMR2_DMA_NOW)
/****************** TMR3 */
// Timing and counting
void TMR3_TimerInit(uint32_t arr); /* Timing function initialization */
#define TMR3_DeInit() (R8_TMR3_CTRL_MOD = 0)
void TMR3_EXTSignalCounterInit(uint32_t arr, CapModeTypeDef capedge,
CapWidthTypedef capwidth); /* External signal counting function initialization */
#define TMR3_GetCurrentCount() R32_TMR3_COUNT /* Get the current count value, 67108864 */
#define TMR3_ClrCurrentCount() {R8_TMR3_CTRL_MOD |= RB_TMR_ALL_CLEAR;R8_TMR3_CTRL_MOD &= ~RB_TMR_ALL_CLEAR;}
#define TMR3_SET_CNT_END(cnt_end) ({R32_TMR3_CNT_END = (cnt_end);})
// Pulse Width Modulation Function
#define TMR3_PWMCycleCfg(cyc) \
(R32_TMR3_CNT_END = (cyc)) /* PWM2 channel output waveform period configuration, maximum 67108864 */
void TMR3_PWMInit(PWM_PolarTypeDef polarities, PWM_RepeatTsTypeDef repeattime); /* PWM2 output initialization */
#define TMR3_PWMActDataWidth(d) (R32_TMR3_FIFO = (d)) /* PWM2 effective data pulse width, maximum 67108864 */
// Catch pulse width
#define TMR3_CAPTimeoutCfg(cyc) \
(R32_TMR3_CNT_END = (cyc)) /* CAP2 capture level timeout configuration, maximum 33554432 */
void TMR3_CapInit(CapModeTypeDef capedge,CapWidthTypedef widt); /* External signal capture function initialization */
#define TMR3_CAPGetData() R32_TMR3_FIFO /* Get pulse data */
#define TMR3_CAPDataCounter() R8_TMR3_FIFO_COUNT /* Get the number of currently captured data */
#define TMR3_Disable() (R8_TMR3_CTRL_MOD &= ~RB_TMR_COUNT_EN) /* Close TMR3 */
#define TMR3_Enable() (R8_TMR3_CTRL_MOD |= RB_TMR_COUNT_EN) /* Close TMR3 */
// refer to TMR3 interrupt bit define
#define TMR3_ITCfg(cfglist, en) \
BITS_CFG(R8_TMR3_INTER_EN, (cfglist), (en)) /* TMR3 corresponding interrupt bit on and off */
// refer to TMR3 interrupt bit define
#define TMR3_ClearITFlag(f) (R8_TMR3_INT_FLAG = (f)) /* Clear interrupt flag */
#define TMR3_GetITFlag(f) (R8_TMR3_INT_FLAG & (f)) /* Query interrupt flag status */
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_uart.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* UART firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_UART_H
#define __CH564_UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch564.h"
/**
* @brief Line Error Status Definition
*/
#define STA_ERR_BREAK RB_LSR_BREAK_ERR // Data Interval Error
#define STA_ERR_FRAME RB_LSR_FRAME_ERR // DataFrame error
#define STA_ERR_PAR RB_LSR_PAR_ERR // Parity bit error
#define STA_ERR_FIFOOV RB_LSR_OVER_ERR // Receive Data Overflow
#define STA_TXFIFO_EMP RB_LSR_TX_FIFO_EMP // The current send FIFO is empty, you can continue to fill the send data
#define STA_TXALL_EMP RB_LSR_TX_ALL_EMP // All currently sent data has been sent
#define STA_RECV_DATA RB_LSR_DATA_RDY // Data is currently received
/**
* @brief Serial port byte trigger configuration
*/
typedef enum {
UART_1BYTE_TRIG = 0, // 1 byte trigger
UART_2BYTE_TRIG = 1, // 2 byte trigger
UART_4BYTE_TRIG = 2, // 4 byte trigger
UART_7BYTE_TRIG = 3, // 7 byte trigger
} UARTByteTRIGTypeDef;
/****************** UART0 */
void UART0_DefInit (void); /* Serial port default initialization configuration */
void UART0_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
void UART0_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
void UART0_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
void UART0_Reset (void); /* Serial port software reset */
#define UART0_SET_DLV(dlv) ({ R8_UART0_DIV = (dlv); })
#define UART0_CLR_RXFIFO() (R8_UART0_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
#define UART0_CLR_TXFIFO() (R8_UART0_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
#define UART0_GetITFlag() (R8_UART0_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
#define UART0_SET_FCR(cfglist, en) BITS_CFG (R8_UART0_FCR, (cfglist), (en))
#define UART0_SET_LCR(cfglist, en) BITS_CFG (R8_UART0_LCR, (cfglist), (en))
#define UART0_SET_MCR(cfglist, en) BITS_CFG (R8_UART0_MCR, (cfglist), (en))
#define UART0_SET_RTS() UART0_SET_MCR(RB_MCR_RTS,ENABLE)
#define UART0_SET_DTR() UART0_SET_MCR(RB_MCR_DTR,ENABLE)
#define UART0_RESET_RTS() UART0_SET_MCR(RB_MCR_RTS,DISABLE)
#define UART0_RESET_DTR() UART0_SET_MCR(RB_MCR_DTR,DISABLE)
// please refer to LINE error and status define
#define UART0_GetLinSTA() (R8_UART0_LSR) /* Get the current communication status */
#define UART0_GetMSRSTA() (R8_UART0_MSR) /* Get the current flow control status, only applicable to UART0 */
#define UART0_DMACFG(cfglist, en) BITS_CFG (R8_UART0_DMA_CTRL, (cfglist), (en))
#define UART0_DMA_SET_RD_RANGE(start, end) \
({ \
R32_UART0_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART0_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART0_DMA_GET_RD_CURRENT_ADDR() (R32_UART0_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_GET_RD_BEG_ADDR() (R32_UART0_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_GET_RD_END_ADDR() (R32_UART0_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_SET_WR_RANGE(start, end) \
({ \
R32_UART0_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART0_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART0_DMA_GET_WR_CURRENT_ADDR() (R32_UART0_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_GET_WR_BEG_ADDR() (R32_UART0_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_GET_WR_END_ADDR() (R32_UART0_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
#define UART0_DMA_GET_IT_FLAG(dmaif) (R8_UART0_DMA_IF & (dmaif))
#define UART0_SendByte(b) (R8_UART0_THR = (b)) /* Serial port single byte transmission */
void UART0_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
void UART0_Send_DMA (uint8_t *buf, uint32_t lenth);
void UART0_Recv_DMA (uint8_t *buf, uint32_t lenth);
#define UART0_RecvByte() (R8_UART0_RBR) /* Serial port read single byte */
uint16_t UART0_RecvString (uint8_t *buf); /* Serial port read multibyte */
void UART0_DTRDSR_Cfg(FunctionalState en);
void UART0_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
/****************** UART1 */
void UART1_DefInit (void); /* Serial port default initialization configuration */
void UART1_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
void UART1_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
void UART1_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
void UART1_Reset (void); /* Serial port software reset */
#define UART1_SET_DLV(dlv) ({ R8_UART1_DIV = dlv; })
#define UART1_CLR_RXFIFO() (R8_UART1_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
#define UART1_CLR_TXFIFO() (R8_UART1_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
#define UART1_GetITFlag() (R8_UART1_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
#define UART1_SET_FCR(cfglist, en) BITS_CFG (R8_UART1_FCR, (cfglist), (en))
#define UART1_SET_LCR(cfglist, en) BITS_CFG (R8_UART1_LCR, (cfglist), (en))
#define UART1_SET_MCR(cfglist, en) BITS_CFG (R8_UART1_MCR, (cfglist), (en))
#define UART1_SET_RTS() UART1_SET_MCR(RB_MCR_RTS,ENABLE)
#define UART1_RESET_RTS() UART1_SET_MCR(RB_MCR_RTS,DISABLE)
// please refer to LINE error and status define
#define UART1_GetLinSTA() (R8_UART1_LSR) /* Get the current communication status */
#define UART1_GetMSRSTA() (R8_UART1_MSR) /* Get the current flow control status, only applicable to UART1 */
#define UART1_DMACFG(cfglist, en) BITS_CFG (R8_UART1_DMA_CTRL, (cfglist), (en))
#define UART1_DMA_SET_RD_RANGE(start, end) \
({ \
R32_UART1_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART1_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART1_DMA_GET_RD_CURRENT_ADDR() (R32_UART1_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_GET_RD_BEG_ADDR() (R32_UART1_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_GET_RD_END_ADDR() (R32_UART1_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_SET_WR_RANGE(start, end) \
({ \
R32_UART1_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART1_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART1_DMA_GET_WR_CURRENT_ADDR() (R32_UART1_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_GET_WR_BEG_ADDR() (R32_UART1_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_GET_WR_END_ADDR() (R32_UART1_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
#define UART1_DMA_GET_IT_FLAG(dmaif) (R8_UART1_DMA_IF & (dmaif))
#define UART1_SendByte(b) (R8_UART1_THR = (b)) /* Serial port single byte transmission */
void UART1_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
void UART1_Send_DMA (uint8_t *buf, uint32_t lenth);
void UART1_Recv_DMA (uint8_t *buf, uint32_t lenth);
#define UART1_RecvByte() (R8_UART1_RBR) /* Serial port read single byte */
uint16_t UART1_RecvString (uint8_t *buf); /* Serial port read multibyte */
void UART1_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
/****************** UART2 */
void UART2_DefInit (void); /* Serial port default initialization configuration */
void UART2_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
void UART2_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
void UART2_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
void UART2_Reset (void); /* Serial port software reset */
#define UART2_SET_DLV(dlv) ({ R8_UART2_DIV = (dlv); })
#define UART2_CLR_RXFIFO() (R8_UART2_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
#define UART2_CLR_TXFIFO() (R8_UART2_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
#define UART2_GetITFlag() (R8_UART2_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
#define UART2_SET_FCR(cfglist, en) BITS_CFG (R8_UART2_FCR, (cfglist), (en))
#define UART2_SET_LCR(cfglist, en) BITS_CFG (R8_UART2_LCR, (cfglist), (en))
#define UART2_SET_MCR(cfglist, en) BITS_CFG (R8_UART2_MCR, (cfglist), (en))
#define UART2_SET_RTS() UART2_SET_MCR(RB_MCR_RTS,ENABLE)
#define UART2_RESET_RTS() UART2_SET_MCR(RB_MCR_RTS,DISABLE)
// please refer to LINE error and status define
#define UART2_GetLinSTA() (R8_UART2_LSR) /* Get the current communication status */
#define UART2_GetMSRSTA() (R8_UART2_MSR) /* Get the current flow control status, only applicable to UART2 */
#define UART2_DMACFG(cfglist, en) BITS_CFG (R8_UART2_DMA_CTRL, (cfglist), (en))
#define UART2_DMA_SET_RD_RANGE(start, end) \
({ \
R32_UART2_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART2_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART2_DMA_GET_RD_CURRENT_ADDR() (R32_UART2_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_GET_RD_BEG_ADDR() (R32_UART2_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_GET_RD_END_ADDR() (R32_UART2_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_SET_WR_RANGE(start, end) \
({ \
R32_UART2_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART2_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART2_DMA_GET_WR_CURRENT_ADDR() (R32_UART2_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_GET_WR_BEG_ADDR() (R32_UART2_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_GET_WR_END_ADDR() (R32_UART2_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
#define UART2_DMA_GET_IT_FLAG(dmaif) (R8_UART2_DMA_IF & (dmaif))
#define UART2_SendByte(b) (R8_UART2_THR = (b)) /* Serial port single byte transmission */
void UART2_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
void UART2_Send_DMA (uint8_t *buf, uint32_t lenth);
void UART2_Recv_DMA (uint8_t *buf, uint32_t lenth);
#define UART2_RecvByte() (R8_UART2_RBR) /* Serial port read single byte */
uint16_t UART2_RecvString (uint8_t *buf); /* Serial port read multibyte */
void UART2_CTSRTS_Cfg(GPIO_Typedef* GPIOx, FunctionalState en,FunctionalState auto_ctrl_en);
/****************** UART3 */
void UART3_DefInit (void); /* Serial port default initialization configuration */
void UART3_BaudRateCfg (uint32_t baudrate); /* Serial port baud rate configuration */
void UART3_ByteTrigCfg (UARTByteTRIGTypeDef UARTByteTRIG); /* Serial byte trigger interrupt configuration */
void UART3_INTCfg (FunctionalState NewSTA, uint8_t RB_IER); /* Serial port interrupt configuration */
void UART3_Reset (void); /* Serial port software reset */
#define UART3_SET_DLV(dlv) ({ R8_UART3_DIV = dlv; })
#define UART3_CLR_RXFIFO() (R8_UART3_FCR |= RB_FCR_RX_FIFO_CLR) /* Clear the current receive FIFO */
#define UART3_CLR_TXFIFO() (R8_UART3_FCR |= RB_FCR_TX_FIFO_CLR) /* Clear the current transmit FIFO */
#define UART3_GetITFlag() (R8_UART3_IIR & (RB_IIR_NO_INT | RB_IIR_INT_MASK)) /* Get the current interrupt flag */
#define UART3_SET_FCR(cfglist, en) BITS_CFG (R8_UART3_FCR, (cfglist), (en))
#define UART3_SET_LCR(cfglist, en) BITS_CFG (R8_UART3_LCR, (cfglist), (en))
#define UART3_SET_MCR(cfglist, en) BITS_CFG (R8_UART3_MCR, (cfglist), (en))
#define UART3_SET_RTS() UART3_SET_MCR(RB_MCR_RTS,ENABLE)
#define UART3_RESET_RTS() UART3_SET_MCR(RB_MCR_RTS,DISABLE)
// please refer to LINE error and status define
#define UART3_GetLinSTA() (R8_UART3_LSR) /* Get the current communication status */
#define UART3_GetMSRSTA() (R8_UART3_MSR) /* Get the current flow control status, only applicable to UART3 */
#define UART3_DMACFG(cfglist, en) BITS_CFG (R8_UART3_DMA_CTRL, (cfglist), (en))
#define UART3_DMA_SET_RD_RANGE(start, end) \
({ \
R32_UART3_DMA_RD_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART3_DMA_RD_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART3_DMA_GET_RD_CURRENT_ADDR() (R32_UART3_DMA_RD_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_GET_RD_BEG_ADDR() (R32_UART3_DMA_RD_START_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_GET_RD_END_ADDR() (R32_UART3_DMA_RD_END_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_SET_WR_RANGE(start, end) \
({ \
R32_UART3_DMA_WR_START_ADDR = (uint32_t)(start)&MASK_UART_DMA_ADDR; \
R32_UART3_DMA_WR_END_ADDR = (uint32_t)(end)&MASK_UART_DMA_ADDR; \
})
#define UART3_DMA_GET_WR_CURRENT_ADDR() (R32_UART3_DMA_WR_NOW_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_GET_WR_BEG_ADDR() (R32_UART3_DMA_WR_START_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_GET_WR_END_ADDR() (R32_UART3_DMA_WR_END_ADDR & MASK_UART_DMA_ADDR)
#define UART3_DMA_GET_IT_FLAG(dmaif) (R8_UART3_DMA_IF & (dmaif))
#define UART3_SendByte(b) (R8_UART3_THR = (b)) /* Serial port single byte transmission */
void UART3_SendString (uint8_t *buf, uint16_t length); /* Serial multi-byte transmission */
void UART3_Send_DMA (uint8_t *buf, uint32_t lenth);
void UART3_Recv_DMA (uint8_t *buf, uint32_t lenth);
#define UART3_RecvByte() (R8_UART3_RBR) /* Serial port read single byte */
uint16_t UART3_RecvString (uint8_t *buf); /* Serial port read multibyte */
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* USB firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_USB_H
#define __CH564_USB_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/* USB standard device request code */
#ifndef USB_GET_DESCRIPTOR
#define USB_GET_STATUS 0x00
#define USB_CLEAR_FEATURE 0x01
#define USB_SET_FEATURE 0x03
#define USB_SET_ADDRESS 0x05
#define USB_GET_DESCRIPTOR 0x06
#define USB_SET_DESCRIPTOR 0x07
#define USB_GET_CONFIGURATION 0x08
#define USB_SET_CONFIGURATION 0x09
#define USB_GET_INTERFACE 0x0A
#define USB_SET_INTERFACE 0x0B
#define USB_SYNCH_FRAME 0x0C
#endif
#define DEF_STRING_DESC_LANG 0x00
#define DEF_STRING_DESC_MANU 0x01
#define DEF_STRING_DESC_PROD 0x02
#define DEF_STRING_DESC_SERN 0x03
/* USB hub class request code */
#ifndef HUB_GET_DESCRIPTOR
#define HUB_GET_STATUS 0x00
#define HUB_CLEAR_FEATURE 0x01
#define HUB_GET_STATE 0x02
#define HUB_SET_FEATURE 0x03
#define HUB_GET_DESCRIPTOR 0x06
#define HUB_SET_DESCRIPTOR 0x07
#endif
/* USB HID class request code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* USB CDC Class request code */
#ifndef CDC_GET_LINE_CODING
#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */
#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */
#endif
/* Bit Define for USB Request Type */
#ifndef USB_REQ_TYP_MASK
#define USB_REQ_TYP_IN 0x80
#define USB_REQ_TYP_OUT 0x00
#define USB_REQ_TYP_READ 0x80
#define USB_REQ_TYP_WRITE 0x00
#define USB_REQ_TYP_MASK 0x60
#define USB_REQ_TYP_STANDARD 0x00
#define USB_REQ_TYP_CLASS 0x20
#define USB_REQ_TYP_VENDOR 0x40
#define USB_REQ_TYP_RESERVED 0x60
#define USB_REQ_RECIP_MASK 0x1F
#define USB_REQ_RECIP_DEVICE 0x00
#define USB_REQ_RECIP_INTERF 0x01
#define USB_REQ_RECIP_ENDP 0x02
#define USB_REQ_RECIP_OTHER 0x03
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
#define USB_REQ_FEAT_ENDP_HALT 0x00
#endif
/* USB Descriptor Type */
#ifndef USB_DESCR_TYP_DEVICE
#define USB_DESCR_TYP_DEVICE 0x01
#define USB_DESCR_TYP_CONFIG 0x02
#define USB_DESCR_TYP_STRING 0x03
#define USB_DESCR_TYP_INTERF 0x04
#define USB_DESCR_TYP_ENDP 0x05
#define USB_DESCR_TYP_QUALIF 0x06
#define USB_DESCR_TYP_SPEED 0x07
#define USB_DESCR_TYP_OTG 0x09
#define USB_DESCR_TYP_BOS 0X0F
#define USB_DESCR_TYP_HID 0x21
#define USB_DESCR_TYP_REPORT 0x22
#define USB_DESCR_TYP_PHYSIC 0x23
#define USB_DESCR_TYP_CS_INTF 0x24
#define USB_DESCR_TYP_CS_ENDP 0x25
#define USB_DESCR_TYP_HUB 0x29
#endif
/* USB Device Class */
#ifndef USB_DEV_CLASS_HUB
#define USB_DEV_CLASS_RESERVED 0x00
#define USB_DEV_CLASS_AUDIO 0x01
#define USB_DEV_CLASS_COMMUNIC 0x02
#define USB_DEV_CLASS_HID 0x03
#define USB_DEV_CLASS_MONITOR 0x04
#define USB_DEV_CLASS_PHYSIC_IF 0x05
#define USB_DEV_CLASS_POWER 0x06
#define USB_DEV_CLASS_IMAGE 0x06
#define USB_DEV_CLASS_PRINTER 0x07
#define USB_DEV_CLASS_STORAGE 0x08
#define USB_DEV_CLASS_HUB 0x09
#define USB_DEV_CLASS_VEN_SPEC 0xFF
#endif
/* USB Hub Class Request */
#ifndef HUB_GET_HUB_DESCRIPTOR
#define HUB_CLEAR_HUB_FEATURE 0x20
#define HUB_CLEAR_PORT_FEATURE 0x23
#define HUB_GET_BUS_STATE 0xA3
#define HUB_GET_HUB_DESCRIPTOR 0xA0
#define HUB_GET_HUB_STATUS 0xA0
#define HUB_GET_PORT_STATUS 0xA3
#define HUB_SET_HUB_DESCRIPTOR 0x20
#define HUB_SET_HUB_FEATURE 0x20
#define HUB_SET_PORT_FEATURE 0x23
#endif
/* Hub Class Feature Selectors */
#ifndef HUB_PORT_RESET
#define HUB_C_HUB_LOCAL_POWER 0
#define HUB_C_HUB_OVER_CURRENT 1
#define HUB_PORT_CONNECTION 0
#define HUB_PORT_ENABLE 1
#define HUB_PORT_SUSPEND 2
#define HUB_PORT_OVER_CURRENT 3
#define HUB_PORT_RESET 4
#define HUB_PORT_POWER 8
#define HUB_PORT_LOW_SPEED 9
#define HUB_C_PORT_CONNECTION 16
#define HUB_C_PORT_ENABLE 17
#define HUB_C_PORT_SUSPEND 18
#define HUB_C_PORT_OVER_CURRENT 19
#define HUB_C_PORT_RESET 20
#endif
/* USB UDisk */
#ifndef USB_BO_CBW_SIZE
#define USB_BO_CBW_SIZE 0x1F
#define USB_BO_CSW_SIZE 0x0D
#endif
#ifndef USB_BO_CBW_SIG0
#define USB_BO_CBW_SIG0 0x55
#define USB_BO_CBW_SIG1 0x53
#define USB_BO_CBW_SIG2 0x42
#define USB_BO_CBW_SIG3 0x43
#define USB_BO_CSW_SIG0 0x55
#define USB_BO_CSW_SIG1 0x53
#define USB_BO_CSW_SIG2 0x42
#define USB_BO_CSW_SIG3 0x53
#endif
/*******************************************************************************/
/* USBHS Related Register Macro Definition */
/* USBHS Device Register Definition */
/* Bit definition for USB_CTRL register */
#define DEV_LPM_EN 0x80 /* LPM enable */
#define DEV_EN 0x20 /* USB device enabled */
#define DEV_DMA_EN 0x10 /* DMA transfer enabled */
#define PHY_SUSPENDM 0x08 /* USB PHY suspend */
#define USB_ALL_CLR 0x04 /* clear all interrupt flags */
#define SIE_RESET 0x02 /* USB protocol processor reset */
#define LINK_RESET 0x01
/* Bit definition for usb_BASE_MODE register */
#define EXP_SPD_MASK 0x03 /* bit[0:1] controls the desired device speed */
#define EXP_FS_SPD 0x00 /* Full-speed mode */
#define EXP_HS_SPD 0x01 /* High-speed mode */
#define EXP_LOW_SPD 0x02 /* Low-speed mode */
/* Bit definition for USB_INT_EN register */
#define FIFO_OVER_IE 0x80 /* USB Overflow interrupt enable */
#define LINK_RDY_IE 0x40 /* USB connection interrupt enable */
#define RX_SOF_IE 0x20 /* Receive SOF packet interrupt enable */
#define RTX_ACT_IE 0x10 /* USB transfer end interrupt enabled */
#define LPM_ACT_IE 0x08 /* LMP transfer end interrupt enabled */
#define BUS_SLEEP_IE 0x04 /* USB bus sleep interrupt enabled */
#define BUS_SUSP_IE 0x02 /* USB bus pause interrupt enabled */
#define BUS_REST_IE 0x01 /* USB bus reset interrupt enabled */
/* Bit definition for USB_DEV_AD register */
#define MASK_USB_ADDR 0x7f
/* Bit definition for USB_WAKE_CR register */
#define RB_RMT_WAKE 0x01 /* remote wake up */
/* Bit definition for USB_TEST_MODE register */
#define RB_TEST_EN 0x80 /* test mode enable */
#define RB_TEST_SE0NAK 0x08 /* test mode,output SEO */
#define RB_TEST_PKT 0x04 /* test mode,output a packet */
#define RB_TEST_K 0x02 /* test mode,output K */
#define RB_TEST_J 0x01 /* test mode,output J */
/* Bit definition for USB_LPM_DATA register */
#define LPM_BUSY 0x8000
#define LPM_DATA 0x07ff /* read-only power management data */
/* Bit definition for USB_INT_FG register */
#define FIFO_OVER_IF 0x80 /* read-write USB Overflow interrupt flag */
#define LINK_RDY_IF 0x40 /* read-write USB connection interrupt flag */
#define RX_SOF_IF 0x20 /* read-write Receive SOF packet interrupt flag */
#define RTX_ACT_IF 0x10 /* read-only USB transmission end interrupt flag */
#define LPM_ACT_IF 0x08 /* read-write LPM transmission end interrupt flag */
#define BUS_SLEEP_IF 0x04 /* read-write USB bus sleep interrupt flag */
#define BUS_SUSP_IF 0x02 /* read-write USB bus suspend interrupt flag */
#define BUS_REST_IF 0x01 /* read-write USB bus reset interrupt flag */
/* Bit definition for USB_INT_ST register */
#define RB_UIS_EP_DIR 0x10 /* Endpoint data transmission direction */
#define RB_UIS_EP_ID_MASK 0x07 /* The endpoint number at which the data transfer occurs */
/* Bit definition for USB_MIS_ST register */
#define RB_UMS_HS_MOD 0x80 /* whether the host is high-speed */
#define RB_UMS_SUSP_REQ 0x10 /* USB suspends the request */
#define RB_UMS_FREE 0x08 /* USB free status */
#define RB_UMS_SLEEP 0x04 /* USB sleep status */
#define RB_UMS_SUSPEND 0x02 /* USB suspend status */
#define RB_UMS_READY 0x01 /* USB connection status */
/* Bit definition for USB_FRAMME_NO register */
#define MICRO_FRAME 0xe000 /* Received micro frame number */
#define FRAME_NO 0x07ff /* Received frame number */
/* Bit definition for USB_BUS register */
#define USB_DM_ST 0x0008 /* read-only UDM status */
#define USB_DP_ST 0x0004 /* read-only UDP status */
#define USB_WAKEUP 0x0001 /* read-only USB wakeup */
/* Bit definition for DEV_UEP_TX_EN & DEV_UEP_RX_EN register */
#define RB_EP0_EN 0x0001
#define RB_EP1_EN 0x0002
#define RB_EP2_EN 0x0004
#define RB_EP3_EN 0x0008
#define RB_EP4_EN 0x0010
#define RB_EP5_EN 0x0020
#define RB_EP6_EN 0x0040
#define RB_EP7_EN 0x0080
#define RB_EP8_EN 0x0100
#define RB_EP9_EN 0x0200
#define RB_EP10_EN 0x0400
#define RB_EP11_EN 0x0800
#define RB_EP12_EN 0x1000
#define RB_EP13_EN 0x2000
#define RB_EP14_EN 0x4000
#define RB_EP15_EN 0x8000
/* Bit definition for DEV_UEP_T_TOG_AUTO register */
#define EP0_T_TOG_AUTO 0x01
#define EP1_T_TOG_AUTO 0x02
#define EP2_T_TOG_AUTO 0x04
#define EP3_T_TOG_AUTO 0x08
#define EP4_T_TOG_AUTO 0x10
#define EP5_T_TOG_AUTO 0x20
#define EP6_T_TOG_AUTO 0x40
#define EP7_T_TOG_AUTO 0x80
/* Bit definition for DEV_UEP_R_TOG_AUTO register */
#define EP0_R_TOG_AUTO 0x01
#define EP1_R_TOG_AUTO 0x02
#define EP2_R_TOG_AUTO 0x04
#define EP3_R_TOG_AUTO 0x08
#define EP4_R_TOG_AUTO 0x10
#define EP5_R_TOG_AUTO 0x20
#define EP6_R_TOG_AUTO 0x40
#define EP7_R_TOG_AUTO 0x80
/* Bit definition for DEV_UEP_T_BURST register */
#define EP0_T_BURST_EN 0x01
#define EP1_T_BURST_EN 0x02
#define EP2_T_BURST_EN 0x04
#define EP3_T_BURST_EN 0x08
#define EP4_T_BURST_EN 0x10
#define EP5_T_BURST_EN 0x20
#define EP6_T_BURST_EN 0x40
#define EP7_T_BURST_EN 0x80
/* Bit definition for DEV_UEP_T_BURST_MODE register */
#define EP0_T_BURST_MODE 0x01
#define EP1_T_BURST_MODE 0x02
#define EP2_T_BURST_MODE 0x04
#define EP3_T_BURST_MODE 0x08
#define EP4_T_BURST_MODE 0x10
#define EP5_T_BURST_MODE 0x20
#define EP6_T_BURST_MODE 0x40
#define EP7_T_BURST_MODE 0x80
/* Bit definition for DEV_UEP_R_BURST register */
#define EP0_R_BURST_EN 0x01
#define EP1_R_BURST_EN 0x02
#define EP2_R_BURST_EN 0x04
#define EP3_R_BURST_EN 0x08
#define EP4_R_BURST_EN 0x10
#define EP5_R_BURST_EN 0x20
#define EP6_R_BURST_EN 0x40
#define EP7_R_BURST_EN 0x80
/* Bit definition for DEV_UEP_R_RES_MODE register */
#define EP0_R_RES_MODE 0x01
#define EP1_R_RES_MODE 0x02
#define EP2_R_RES_MODE 0x04
#define EP3_R_RES_MODE 0x08
#define EP4_R_RES_MODE 0x10
#define EP5_R_RES_MODE 0x20
#define EP6_R_RES_MODE 0x40
#define EP7_R_RES_MODE 0x80
/* Bit definition for DEV_UEP_AF_MODE register */
#define EP1_T_AF 0x02
#define EP2_T_AF 0x04
#define EP3_T_AF 0x08
#define EP4_T_AF 0x10
#define EP5_T_AF 0x20
#define EP6_T_AF 0x40
#define EP7_T_AF 0x80
/* Bit definition for UEPx_TX_CTRL register */
#define USBHS_UEP_T_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */
#define USBHS_UEP_T_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */
#define USBHS_UEP_T_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */
#define USBHS_UEP_T_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */
#define USBHS_UEP_T_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */
#define USBHS_UEP_T_TOG_MASK 0x0C /* Synchronization trigger bit mask */
#define USBHS_UEP_T_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */
#define USBHS_UEP_T_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */
#define USBHS_UEP_T_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */
#define USBHS_UEP_T_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */
#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */
/* Bit definition for UEPx_RX_CTRL register */
#define USBHS_UEP_R_RES_MASK 0x03 /* Response control mask for endpoint 0 transmission */
#define USBHS_UEP_R_RES_NAK 0x00 /* UEP0_TX_CTRL[0:1] = 00, reply NAK to host */
#define USBHS_UEP_R_RES_STALL 0x01 /* UEP0_TX_CTRL[0:1] = 01, reply STALL to host */
#define USBHS_UEP_R_RES_ACK 0x02 /* UEP0_TX_CTRL[0:1] = 10, reply ACK to host */
#define USBHS_UEP_R_RES_NYET 0x03 /* UEP0_TX_CTRL[0:1] = 11, reply NYET to host */
#define USBHS_UEP_R_TOG_MASK 0x0C /* Synchronization trigger bit mask */
#define USBHS_UEP_R_TOG_DATA0 0x00 /* UEP0_TX_CTRL[2:3] = 00, represents DATA0 */
#define USBHS_UEP_R_TOG_DATA1 0x04 /* UEP0_TX_CTRL[2:3] = 01, represents DATA1 */
#define USBHS_UEP_R_TOG_DATA2 0x08 /* UEP0_TX_CTRL[2:3] = 10, represents DATA2 */
#define USBHS_UEP_R_TOG_MDATA 0x0C /* UEP0_TX_CTRL[2:3] = 11, represents MDATA */
#define USBHS_UEP_ENDP_T_DONE 0x80 /* Writing 0 clears the interrupt */
#define USBHS_UEP_ENDP_R_DONE 0x80 /* Writing 0 clears the interrupt */
#define USBHS_RB_SETUP_IS 0x08 /* Indicates whether the reception of endpoint 0 is a Setup transaction */
#define USBHS_ENDP_R_TOG_MATCH 0x10
/* Bit definition for DEV_UEP_T_ISO register */
#define EP1_T_ISO 0x02
#define EP2_T_ISO 0x04
#define EP3_T_ISO 0x08
#define EP4_T_ISO 0x10
#define EP5_T_ISO 0x20
#define EP6_T_ISO 0x40
#define EP7_T_ISO 0x80
/* Bit definition for DEV_UEP_R_ISO register */
#define EP1_R_ISO 0x02
#define EP2_R_ISO 0x04
#define EP3_R_ISO 0x08
#define EP4_R_ISO 0x10
#define EP5_R_ISO 0x20
#define EP6_R_ISO 0x40
#define EP7_R_ISO 0x80
/* USBHS Host Register Definition */
/* Bit definition for UHOST_CTRL register */
#define root_LPM_EN (1<<7)
#define ROOT_FORCE_FS (1<<6)
#define ROOT_SOF_EN (1<<5)
#define ROOT_DMA_EN (1<<4)
#define ROOT_PHY_SUSPENDM (1<<3)
#define ROOT_ALL_CLR (1<<2)
#define ROOT_SIE_RESET (1<<1)
#define ROOT_LINK_RESET (1<<0)
/* Bit definition for UH_INT_EN register */
#define FIFO_OV_IE (1<<7)
#define TX_HALT_IE (1<<6)
#define SOF_ACT_IE (1<<5)
#define USB_ACT_IE (1<<4)
#define RESUME_ACT_IE (1<<3)
#define WKUP_ACT_IE (1<<2)
/* Bit definition for UH_CONTROL register */
#define RX_NO_RES (1<<23)
#define TX_NO_RES (1<<22)
#define RX_NO_DATA (1<<21)
#define TX_NO_DATA (1<<20)
#define TX_LOW_SPD (1<<19)
#define SPLIT_VALID (1<<18)
#define LPM_VALID (1<<17)
#define HOST_ACTION (1<<16)
#define BUF_MODE (1<<10)
#define TOG_MASK (3<<8)
#define TOG_MDATA (3<<8)
#define TOG_DATA2 (2<<8)
#define TOG_DATA1 (1<<8)
#define TOG_DATA0 (0<<8)
/* Bit definition for UH_INT_FLAG register */
#define RB_FIFO_OV_IF (1<<7)
#define RB_TX_HALT_IF (1<<6)
#define RB_SOF_ACT_IF (1<<5)
#define RB_USB_ACT_IF (1<<4)
#define RB_RESUME_ACT_IF (1<<3)
#define RB_WKUP_IF (1<<2)
/* Bit definition for UH_INT_ST register */
#define PORT_RX_RESUME (1<<4)
#define USB_PID_MASK 0x0f
#define USB_PID_TOUT 0x0
#define USB_PID_ACK 0x2
#define USB_PID_NAK 0xa
#define USB_PID_STALL 0xe
#define USB_PID_NYET 0x6
#define USB_PID_DATA0 0x3
#define USB_PID_DATA1 0xb
#define USB_PID_DATA2 0x7
#define USB_PID_MDATA 0xf
#define USB_PID_PRE 0xc
#define USB_PID_ERR 0xc
#define USB_PID_SPLIT 0x8
#define USB_PID_PING 0x4
#define USB_PID_SOF 0x5
#define USB_PID_SETUP 0xd
#define USB_PID_IN 0x9
#define USB_PID_OUT 0x1
/* Bit definition for UH_MIS_ST register */
#define RB_BUS_SE0 (1<<7)
#define RB_BUS_J (1<<6)
#define RB_LINESTATE_MASK (0x3<<4)
#define RB_USB_WAKEUP (1<<3)
#define RB_SOF_ST (1<<2)
#define RB_SOF_PRE (1<<1)
#define RB_SOF_FREE (1<<0)
/* Bit definition for UH_FRAME register */
#define SOF_CNT_CLR (1<<25)
#define SOF_CNT_EN (1<<24)
/* Bit definition for PORT_CTRL register */
#define BUS_RST_LONG (1<<16)
#define PORT_SLEEP_BESL (0xf<<12)
#define CLR_PORT_SLEEP (1<<8)
#define CLR_PORT_CONNECT (1<<5)
#define CLR_PORT_EN (1<<4)
#define SET_PORT_SLEEP (1<<3)
#define CLR_PORT_SUSP (1<<2)
#define SET_PORT_SUSP (1<<1)
#define SET_PORT_RESET (1<<0)
/* Bit definition for PORT_CFG register */
#define PORT_15K_RPD (1<<7)
#define PORT_HOST_MODE (1<<0)//1: HOST function
#define PORT_DEVICE_MODE (0<<0)//0: DEVICE function
/* Bit definition for PORT_INT_EN register */
#define PORT_SLP_IE (1<<5)
#define PORT_RESET_IE (1<<4)
#define PORT_SUSP_IE (1<<2)
#define PORT_EN_IE (1<<1)
#define PORT_CONNECT_IE (1<<0)
/* Bit definition for PORT_TEST_CT register */
#define TEST_FORCE_EN (1<<2)
#define TEST_K (1<<1)
#define TEST_J (1<<0)
/* Bit definition for PORT_STATUS register */
#define PORT_TEST (1<<11)
#define PORT_SPD_MASK (3<<9)
#define PORT_HIGH_SPD (1<<10)
#define PORT_LOW_SPD (1<<9)
#define PORT_FULL_SPD (0<<9)
#define PORT_SLP (1<<5)
#define PORT_RESETTING (1<<4)
#define PORT_OVC (1<<3)
#define PORT_SUSP (1<<2)
#define PORT_EN (1<<1)
#define PORT_CONNECT (1<<0)
/* Bit definition for PORT_STATUS_CHG register */
#define PORT_SLP_IF (1<<5)
#define PORT_RESET_IF (1<<4)
#define PORT_SUSP_IF (1<<2)
#define PORT_EN_IF (1<<1)
#define PORT_CONNECT_IF (1<<0)
/* Bit definition for ROOT_BC_CR register */
#define UDM_VSRC_ACT (1<<10)
#define UDM_BC_CMPE (1<<9)
#define UDP_BC_CMPE (1<<8)
#define BC_AUTO_MODE (1<<6)
#define UDM_BC_VSRC (1<<5)
#define UDP_BC_VSRC (1<<4)
#define UDM_BC_CMPO (1<<1)
#define UDP_BC_CMPO (1<<0)
/* Bit definition for HSI_CAL_CR register */
#define CLK_SEL (1<<21)
#define SOF_FREE (1<<3)
#define SFT_RST (1<<2)
#define CAL_EN (1<<1)
#define CAL_RST (1<<0)
/*******************************************************************************/
/* Struct Definition */
/* USB Setup Request */
typedef struct __attribute__((packed)) _USB_SETUP_REQ
{
uint8_t bRequestType;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
/* USB Device Descriptor */
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
/* USB Configuration Descriptor */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
/* USB Interface Descriptor */
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
/* USB Endpoint Descriptor */
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint8_t wMaxPacketSizeL;
uint8_t wMaxPacketSizeH;
uint8_t bInterval;
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
/* USB Configuration Descriptor Set */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
{
USB_CFG_DESCR cfg_descr;
USB_ITF_DESCR itf_descr;
USB_ENDP_DESCR endp_descr[ 1 ];
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
/* USB HUB Descriptor */
typedef struct __attribute__((packed)) _USB_HUB_DESCR
{
uint8_t bDescLength;
uint8_t bDescriptorType;
uint8_t bNbrPorts;
uint8_t wHubCharacteristicsL;
uint8_t wHubCharacteristicsH;
uint8_t bPwrOn2PwrGood;
uint8_t bHubContrCurrent;
uint8_t DeviceRemovable;
uint8_t PortPwrCtrlMask;
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
/* USB HID Descriptor */
typedef struct __attribute__((packed)) _USB_HID_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bDescriptorTypeX;
uint8_t wDescriptorLengthL;
uint8_t wDescriptorLengthH;
} USB_HID_DESCR, *PUSB_HID_DESCR;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCBW_DataLen;
uint8_t mCBW_Flag;
uint8_t mCBW_LUN;
uint8_t mCBW_CB_Len;
uint8_t mCBW_CB_Buf[ 16 ];
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCSW_Residue;
uint8_t mCSW_Status;
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_usbpd.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* USBPD firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_USBPD_H
#define __CH564_USBPD_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
/* Register Bit Definition */
/* USBPD->CONFIG */
#define PD_FILT_ED (1<<0) /* PD pin input filter enable */
#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */
#define CC_SEL (1<<2) /* Select PD communication port */
#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */
#define PD_RST_EN (1<<4) /* PD mode reset command enable */
#define WAKE_POLAR (1<<5) /* PD port wake-up level */
#define IE_PD_IO (1<<10) /* PD IO interrupt enable */
#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */
#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */
#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */
#define IE_RX_RESET (1<<14) /* Reset interrupt enable */
#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */
/* USBPD->CONTROL */
#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */
#define BMC_START (1<<1) /* BMC send start signal */
#define RX_STATE_0 (1<<2) /* PD received state bit 0 */
#define RX_STATE_1 (1<<3) /* PD received state bit 1 */
#define RX_STATE_2 (1<<4) /* PD received state bit 2 */
#define DATA_FLAG (1<<5) /* Cache data valid flag bit */
#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */
#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */
/* USBPD->TX_SEL */
#define TX_SEL1 (0<<0)
#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */
#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */
#define TX_SEL2_Mask (3<<2)
#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */
#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */
#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */
#define TX_SEL3_Mask (3<<4)
#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */
#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */
#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */
#define TX_SEL4_Mask (3<<6)
#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */
#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */
#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */
/* USBPD->STATUS */
#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */
#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */
#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */
#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */
#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */
#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */
#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */
#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */
#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */
#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */
#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */
/* USBPD->PORT_CC1 */
/* USBPD->PORT_CC2 */
#define PA_CC_AI (1<<0) /* CC port comparator analogue input */
#define CC_PD (1<<1) /* CC port pull-down resistor enable */
#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */
#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */
#define CC_PU_330 (1<<2) /* 01-330uA */
#define CC_PU_180 (2<<2) /* 10-180uA */
#define CC_PU_80 (3<<2) /* 11-80uA */
#define CC_LVE (1<<4) /* CC port output low voltage enable */
#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/
#define CC_NO_CMP (0<<5) /* 000-closed */
#define CC_CMP_22 (2<<5) /* 010-0.22V */
#define CC_CMP_45 (3<<5) /* 011-0.45V */
#define CC_CMP_55 (4<<5) /* 100-0.55V */
#define CC_CMP_66 (5<<5) /* 101-0.66V */
#define CC_CMP_95 (6<<5) /* 110-0.95V */
#define CC_CMP_123 (7<<5) /* 111-1.23V */
/*********************************************************
* PD pin PC14/PC15 high threshold input mode:
* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication
* 0-Normal GPIO threshold input
* *******************************************************/
#define USBPD_PHY_V33 (1<<8)
/**********************************************************
* PD transceiver PHY pull-up limit configuration bits:
* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V
* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V
* ********************************************************/
/* Control Message Types */
#define DEF_TYPE_RESERVED 0x00
#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */
#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_PING 0x05 /* Send By: Source */
#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */
#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */
#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */
#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */
#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */
#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */
#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */
#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */
#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */
#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */
#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */
/* Data Message Types */
#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */
#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */
#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */
#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */
#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */
#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */
#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */
#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */
#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */
#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */
/* Vendor Define Message Command */
#define DEF_VDM_DISC_IDENT 0x01
#define DEF_VDM_DISC_SVID 0x02
#define DEF_VDM_DISC_MODE 0x03
#define DEF_VDM_ENTER_MODE 0x04
#define DEF_VDM_EXIT_MODE 0x05
#define DEF_VDM_ATTENTION 0x06
#define DEF_VDM_DP_S_UPDATE 0x10
#define DEF_VDM_DP_CONFIG 0x11
/* PD Revision */
#define DEF_PD_REVISION_10 0x00
#define DEF_PD_REVISION_20 0x01
#define DEF_PD_REVISION_30 0x02
/* PD PHY Channel */
#define DEF_PD_CC1 0x00
#define DEF_PD_CC2 0x01
#define PIN_CC1 GPIO_Pin_18
#define PIN_CC2 GPIO_Pin_19
/* PD Tx Status */
#define DEF_PD_TX_OK 0x00
#define DEF_PD_TX_FAIL 0x01
/* PDO INDEX */
#define PDO_INDEX_1 1
#define PDO_INDEX_2 2
#define PDO_INDEX_3 3
#define PDO_INDEX_4 4
#define PDO_INDEX_5 5
/******************************************************************************/
#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */
#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */
#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */
#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */
#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */
#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */
#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */
#define PD_RX_SOP0 0x01 /* SOP0 received */
#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */
#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */
#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */
#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */
#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */
#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/
#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/
#define bCC_CMP_22 0X01
#define bCC_CMP_45 0X02
#define bCC_CMP_55 0X04
#define bCC_CMP_66 0X08
#define bCC_CMP_95 0X10
#define bCC_CMP_123 0X20
#define bCC_CMP_220 0X40
/******************************************************************************/
/* PD State Machine */
typedef enum
{
STA_IDLE = 0, /* 0: No task status */
STA_DISCONNECT, /* 1: Disconnection */
STA_SRC_CONNECT, /* 2: SRC connect */
STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */
STA_RX_SRC_CAP, /* 4: SRC_CAP received */
STA_TX_REQ, /* 5: Send REQUEST */
STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */
STA_RX_ACCEPT, /* 7: ACCEPT received */
STA_RX_REJECT, /* 8: REJECT received */
STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */
STA_RX_PS_RDY, /* 10: PS_RDY received */
STA_SINK_CONNECT, /* 11: SNK access */
STA_TX_SRC_CAP, /* 12: Send SRC_CAP */
STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */
STA_RX_REQ, /* 14: REQUEST received */
STA_TX_ACCEPT, /* 15: Send ACCEPT */
STA_TX_REJECT, /* 16: Send REJECT */
STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */
STA_TX_PS_RDY, /* 18: Send PS_RDY */
STA_TX_DR_SWAP, /* 19: Send DR_SWAP */
STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */
STA_TX_PR_SWAP, /* 21: Send PR_SWAP */
STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */
STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */
STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */
STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */
STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */
STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */
STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */
STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */
STA_MODE_SWITCH, /* 30: Mode switching */
STA_TX_SOFTRST, /* 31: Sending a software reset */
STA_TX_HRST, /* 32: Send hardware reset */
STA_PHY_RST, /* 33: PHY reset */
STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */
} CC_STATUS;
/******************************************************************************/
/* PD Message Header Struct */
typedef union
{
struct _Message_Header
{
UINT8 MsgType: 5; /* Message Type */
UINT8 PDRole: 1; /* 0-UFP; 1-DFP */
UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */
UINT8 PRRole: 1; /* 0-Sink; 1-Source */
UINT8 MsgID: 3;
UINT8 NumDO: 3;
UINT8 Ext: 1;
}Message_Header;
UINT16 Data;
}_Message_Header;
/******************************************************************************/
/* Bit definition */
typedef union
{
struct _BITS_
{
UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */
UINT8 Connected: 1; /* PD Physical Layer Connected Flag */
UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */
UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */
UINT8 PR_Role: 1; /* 0-Sink; 1-Source */
UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */
UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */
UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */
UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */
UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */
UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */
UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */
UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */
UINT8 Recv: 3;
}Bit;
UINT16 Bit_Flag;
}_BIT_FLAG;
/* PD control-related structures */
typedef struct _PD_CONTROL
{
CC_STATUS PD_State; /* PD communication status machine */
CC_STATUS PD_State_Last; /* PD communication status machine (last value) */
UINT8 Msg_ID; /* ID of the message sent */
UINT8 Det_Timer; /* PD connection status detection timing */
UINT8 Det_Cnt; /* Number of PD connection status detections */
UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */
UINT8 HPD_Det_Timer; /* HPD connection detection timing */
UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */
UINT16 PD_Comm_Timer; /* PD shared timing variables */
UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */
UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */
UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */
UINT8 Err_Op_Cnt; /* Exception operation count */
UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */
_BIT_FLAG Flag; /* Flag byte bit definition */
}PD_CONTROL, *pPD_CONTROL;
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch564_xbus.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/05
* Description : This file contains all the functions prototypes for the
* XBUS firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH564_XBUS_H
#define __CH564_XBUS_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ch564.h"
typedef enum
{
NoOutput = 0x0,
AddrNum_6bit,
AddrNum_12bit,
AddrNum_ALL
} XbusOutputADDrBit;
typedef enum
{
Setuptime_1clk,
Setuptime_2clk,
} XbusSetupTime;
#define SET_XBUS_CYCLE(val) (R8_XBUS_CYCLE = XBUS_CYCLE_VALUE_MASK & (val))
void XbusInit(XbusOutputADDrBit AddrBit, FunctionalState Bit32En, FunctionalState Stat);
void XbusHoldInit(XbusSetupTime setuptm, uint8_t holdtm);
#ifdef __cplusplus
}
#endif
#endif