699 lines
23 KiB
C
699 lines
23 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : eth_driver.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/05/05
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* Description : eth program body.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include <string.h>
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#include "eth_driver.h"
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#include "net_config.h"
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__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
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__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
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__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
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__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
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__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */
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__attribute__((__aligned__(4))) uint8_t RemoteIp[4]; /* DNS information table, 4-byte alignment */
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const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW,
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WCHNET_NUM_UDP,
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WCHNET_NUM_TCP,
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WCHNET_NUM_TCP_LISTEN,
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WCHNET_NUM_TCP_SEG,
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WCHNET_NUM_IP_REASSDATA,
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WCHNET_NUM_PBUF,
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WCHNET_NUM_POOL_BUF
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};
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const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF),
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WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)
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};
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__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE];
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__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE];
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__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE];
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uint16_t gPHYAddress;
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volatile uint32_t LocalTime;
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volatile uint8_t PhyWaitNegotiationSuc = 0;
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ETH_DMADESCTypeDef *pDMARxSet;
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ETH_DMADESCTypeDef *pDMATxSet;
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volatile uint8_t LinkSta = 0; //0:Link down 1:Link up
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uint8_t LinkVaildFlag = 0; //0:invalid 1:valid
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uint8_t AccelerateLinkFlag = 0; //0:invalid 1:valid
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uint8_t LinkProcessingStep = 0;
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uint32_t LinkProcessingTime = 0;
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uint32_t TaskExecutionTime = 0;
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void ETH_LinkDownCfg(void);
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/*********************************************************************
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* @fn WCHNET_TimeIsr
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*
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* @brief
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*
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* @return none.
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*/
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void WCHNET_TimeIsr( uint16_t timperiod )
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{
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LocalTime += timperiod;
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}
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/*********************************************************************
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* @fn WCHNET_QueryPhySta
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*
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* @brief Query external PHY status
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*
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* @return none.
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*/
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void WCHNET_QueryPhySta(void)
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{
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if(PhyWaitNegotiationSuc)
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{
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ETH_PHYLink();
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}
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}
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/*********************************************************************
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* @fn WCHNET_CheckPHYPN
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*
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* @brief check PHY PN polarity
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*
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* @return none.
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*/
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void WCHNET_CheckPHYPN(uint16_t time)
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{
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uint16_t phy_stat;
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//check PHY PN
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if((LinkProcessingStep == 0)||(LocalTime >= LinkProcessingTime))
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{
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 );
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phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS1);
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if(phy_stat & (1<<4))
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{
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if(LinkProcessingStep == 0)
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{
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LinkProcessingStep = 1;
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LinkProcessingTime = LocalTime + time;
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}
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else {
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LinkProcessingStep = 0;
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LinkProcessingTime = 0;
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phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_ANER);
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if((time == 200) || ((phy_stat & 1) == 0))
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{
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phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_CONTROL1);
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phy_stat |= 1;
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ETH_WritePHYRegister(gPHYAddress, PHY_CONTROL1, phy_stat );
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}
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}
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}
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else {
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LinkProcessingStep = 0;
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LinkProcessingTime = 0;
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}
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}
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}
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/*********************************************************************
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* @fn WCHNET_AccelerateLink
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*
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* @brief accelerate Link processing
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*
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* @return none.
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*/
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void WCHNET_AccelerateLink(void)
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{
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uint16_t phy_stat;
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if(AccelerateLinkFlag == 0)
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{
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, 99 );
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phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x19);
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if((phy_stat & 0xf) == 3)
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{
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AccelerateLinkFlag = 1;
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 );
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phy_stat = 0x4;
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ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
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}
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}
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}
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/*********************************************************************
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* @fn WCHNET_CheckLinkVaild
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*
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* @brief check whether Link is valid
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*
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* @return none.
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*/
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void WCHNET_CheckLinkVaild(void)
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{
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uint16_t phy_stat, phy_bcr;
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if(LinkVaildFlag == 0)
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{
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phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
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if((phy_bcr & (1<<13)) == 0) //Do nothing if Link mode is 10M.
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{
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LinkVaildFlag = 1;
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LinkProcessingTime = 0;
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return;
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}
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, 99 );
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phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1b);
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if((phy_stat & (1<<2)) == 0)
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{
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LinkProcessingTime++;
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if(LinkProcessingTime == 5)
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{
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LinkProcessingTime = 0;
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phy_stat = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR);
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ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset );
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Delay_Us(100);
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ETH_WritePHYRegister(gPHYAddress, PHY_BCR, phy_stat );
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ETH_LinkDownCfg();
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}
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}
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else {
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LinkVaildFlag = 1;
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LinkProcessingTime = 0;
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}
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}
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}
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/*********************************************************************
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* @fn WCHNET_LinkProcessing
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*
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* @brief process Link stage task
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*
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* @return none.
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*/
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void WCHNET_LinkProcessing(void)
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{
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u16 phy_bcr;
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if(LocalTime >= TaskExecutionTime)
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{
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TaskExecutionTime = LocalTime + 10; //execution cycle:10ms
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if(LinkSta == 0) //Link down
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{
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phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
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if(phy_bcr & PHY_AutoNegotiation) //auto-negotiation is enabled
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{
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WCHNET_CheckPHYPN(300); //check PHY PN
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WCHNET_AccelerateLink(); //accelerate Link processing
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}
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else { //auto-negotiation is disabled
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if((phy_bcr & (1<<13)) == 0) // 10M
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{
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WCHNET_CheckPHYPN(200); //check PHY PN
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}
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}
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}
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else { //Link up
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WCHNET_CheckLinkVaild(); //check whether Link is valid
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}
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}
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}
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/*********************************************************************
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* @fn WCHNET_MainTask
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*
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* @brief library main task function
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*
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* @param none.
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*
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* @return none.
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*/
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void WCHNET_MainTask(void)
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{
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WCHNET_NetInput( ); /* Ethernet data input */
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WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */
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WCHNET_QueryPhySta();
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WCHNET_LinkProcessing();
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}
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/*********************************************************************
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* @fn ETH_LinkUpCfg
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*
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* @brief When the PHY is connected, configure the relevant functions.
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*
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* @param none.
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*
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* @return none.
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*/
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void ETH_LinkUpCfg(void)
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{
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uint16_t phy_stat;
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LinkSta = 1;
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AccelerateLinkFlag = 0;
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LinkProcessingStep = 0;
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LinkProcessingTime = 0;
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PhyWaitNegotiationSuc = 0;
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ETH_Start( );
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 );
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phy_stat = 0x0;
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ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
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}
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/*********************************************************************
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* @fn ETH_LinkDownCfg
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*
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* @brief When the PHY is disconnected, configure the relevant functions.
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*
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* @param none.
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*
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* @return none.
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*/
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void ETH_LinkDownCfg(void)
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{
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LinkSta = 0;
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LinkVaildFlag = 0;
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LinkProcessingTime = 0;
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}
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/*********************************************************************
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* @fn ETH_PHYLink
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*
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* @brief Configure MAC parameters after the PHY Link is successful.
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*
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* @param none.
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*
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* @return none.
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*/
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void ETH_PHYLink( void )
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{
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uint32_t phy_stat, phy_anlpar, phy_bcr;
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phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
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phy_anlpar = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_ANLPAR);
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phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR);
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WCHNET_PhyStatus( phy_stat );
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if(phy_stat & PHY_Linked_Status) //LinkUp
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{
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if(phy_bcr & PHY_AutoNegotiation)
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{
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if(phy_anlpar == 0)
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{
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ETH_LinkUpCfg();
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}
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else {
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if(phy_stat & PHY_AutoNego_Complete)
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{
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ETH_LinkUpCfg();
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}
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else{
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PhyWaitNegotiationSuc = 1;
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}
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}
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}
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else {
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ETH_LinkUpCfg();
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}
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}
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else { //LinkDown
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/*Link down*/
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ETH_LinkDownCfg();
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}
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}
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/*********************************************************************
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* @fn ETH_CheckPhyInterruptStatus
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*
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* @brief MAC check PHY interrupt status.
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*
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* @param none.
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*
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* @return none.
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*/
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void ETH_CheckPhyInterruptStatus( void )
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{
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uint16_t phyIntStat;
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE17 );
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phyIntStat = ETH_ReadPHYRegister( gPHYAddress, PHY_WOL_STATUS);
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if(phyIntStat & WOL_DONE_INT)
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{
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/* Wol done */
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}
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else /* Link status change*/
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{
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ETH_PHYLink();
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}
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 );
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phyIntStat = ETH_ReadPHYRegister( gPHYAddress, 0x1E); /* Clear the Interrupt status */
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}
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/*********************************************************************
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* @fn PHY_InterruptInit
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*
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* @brief Configure PHY interrupt function
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*
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* @param none.
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*
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* @return none.
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*/
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void PHY_InterruptInit(void)
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{
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uint16_t RegValue;
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE7 );
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/* Configure interrupt function */
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RegValue = ETH_ReadPHYRegister(gPHYAddress, PHY_INTERRUPT_MASK);
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RegValue |= 0x01 << 13;
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ETH_WritePHYRegister(gPHYAddress, PHY_INTERRUPT_MASK, RegValue );
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/* Clear the Interrupt status */
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE0 );
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ETH_ReadPHYRegister( gPHYAddress, PHY_INTERRUPT_IND);
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}
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/*********************************************************************
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* @fn PHY_LEDCfg
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*
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* @brief Configure PHY LED function
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*
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* @param none.
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*
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* @return none.
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*/
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void PHY_LEDCfg(void)
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{
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uint16_t RegValue;
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ETH_WritePHYRegister(gPHYAddress, PHY_PAG_SEL, PHY_REG_PAGE7 );
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//turn on LED--PHY
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RegValue = ETH_ReadPHYRegister(gPHYAddress, PHY_INTERRUPT_MASK);
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RegValue |= 1<<9;
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ETH_WritePHYRegister(gPHYAddress, PHY_INTERRUPT_MASK, RegValue );
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//<2F><>link_led<65><64>ӳ<EFBFBD>䵽PB17
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R32_AFIO_PCFR1 |= 1<<30;
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//<2F><>act_led<65><64>ӳ<EFBFBD>䵽PB6
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R32_AFIO_PCFR2 |= 1<<1;
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//turn on LED--MCU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CH564RM V1.1<EFBFBD>ֲ<EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>ж<EFBFBD>Ӧ<EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʳ<EFBFBD><EFBFBD><EFBFBD>
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ETH_LED_CTRL = 0x05;
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}
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/*********************************************************************
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* @fn ETH_RegInit
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*
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* @brief ETH register initialization.
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*
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* @param ETH_InitStruct:initialization struct.
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* PHYAddress:PHY address.
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*
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* @return Initialization status.
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*/
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uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress )
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{
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uint32_t tmpreg = 0;
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/*---------------------- Physical layer configuration -------------------*/
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/* Set the SMI interface clock, set as the main frequency divided by 42 */
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tmpreg = ETH->MACMIIAR;
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tmpreg &= MACMIIAR_CR_MASK;
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tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
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ETH->MACMIIAR = (uint32_t)tmpreg;
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/*------------------------ MAC register configuration ----------------------- --------------------*/
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tmpreg = ETH->MACCR;
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tmpreg &= MACCR_CLEAR_MASK;
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tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
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ETH_InitStruct->ETH_Jabber |
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ETH_InitStruct->ETH_InterFrameGap |
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ETH_InitStruct->ETH_ChecksumOffload |
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ETH_InitStruct->ETH_AutomaticPadCRCStrip |
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ETH_InitStruct->ETH_DeferralCheck |
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(1 << 20));
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/* Write MAC Control Register */
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ETH->MACCR = (uint32_t)tmpreg;
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ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
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ETH_InitStruct->ETH_SourceAddrFilter |
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ETH_InitStruct->ETH_PassControlFrames |
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ETH_InitStruct->ETH_BroadcastFramesReception |
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ETH_InitStruct->ETH_DestinationAddrFilter |
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ETH_InitStruct->ETH_PromiscuousMode |
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ETH_InitStruct->ETH_MulticastFramesFilter |
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ETH_InitStruct->ETH_UnicastFramesFilter);
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/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
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/* Write to ETHERNET MACHTHR */
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ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
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/* Write to ETHERNET MACHTLR */
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ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
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/*----------------------- ETHERNET MACFCR Configuration --------------------*/
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/* Get the ETHERNET MACFCR value */
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tmpreg = ETH->MACFCR;
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/* Clear xx bits */
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tmpreg &= MACFCR_CLEAR_MASK;
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tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
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ETH_InitStruct->ETH_UnicastPauseFrameDetect |
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ETH_InitStruct->ETH_ReceiveFlowControl |
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ETH_InitStruct->ETH_TransmitFlowControl);
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ETH->MACFCR = (uint32_t)tmpreg;
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ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
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ETH_InitStruct->ETH_VLANTagIdentifier);
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tmpreg = ETH->DMAOMR;
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tmpreg &= DMAOMR_CLEAR_MASK;
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tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
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ETH_InitStruct->ETH_FlushReceivedFrame |
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ETH_InitStruct->ETH_TransmitStoreForward |
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ETH_InitStruct->ETH_ForwardErrorFrames |
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ETH_InitStruct->ETH_ForwardUndersizedGoodFrames);
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ETH->DMAOMR = (uint32_t)tmpreg;
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/* Reset the physical layer */
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ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset);
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return ETH_SUCCESS;
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}
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/*********************************************************************
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* @fn ETH_Configuration
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*
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* @brief Ethernet configure.
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*
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* @return none
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*/
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void ETH_Configuration( uint8_t *macAddr )
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{
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ETH_InitTypeDef ETH_InitStructure;
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uint16_t timeout = 10000;
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/* Configure Ethernet for normal operating mode*/
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ETH->PHY_CR |= 1<<31;
|
||
ETH->PHY_CR &= ~(1<<30);
|
||
|
||
gPHYAddress = PHY_ADDRESS;
|
||
|
||
/* Software reset */
|
||
ETH_SoftwareReset();
|
||
|
||
/* Wait for software reset */
|
||
do{
|
||
Delay_Us(10);
|
||
if( !--timeout ) break;
|
||
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||
|
||
/* ETHERNET Configuration */
|
||
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
|
||
ETH_StructInit(Ð_InitStructure);
|
||
/* Fill ETH_InitStructure parameters */
|
||
/*------------------------ MAC -----------------------------------*/
|
||
#if HARDWARE_CHECKSUM_CONFIG
|
||
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||
#endif
|
||
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||
/* Filter function configuration */
|
||
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
|
||
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Enable;
|
||
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||
/*------------------------ DMA -----------------------------------*/
|
||
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable;
|
||
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable;
|
||
/* Configure Ethernet */
|
||
ETH_RegInit( Ð_InitStructure, gPHYAddress );
|
||
|
||
/* Configure MAC address */
|
||
ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]);
|
||
ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24));
|
||
|
||
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
|
||
|
||
PHY_InterruptInit();
|
||
|
||
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||
ETH_DMA_IT_R |\
|
||
ETH_DMA_IT_T |\
|
||
ETH_DMA_IT_AIS |\
|
||
ETH_DMA_IT_RBU |\
|
||
ETH_DMA_IT_PHYSR,\
|
||
ENABLE);
|
||
}
|
||
|
||
/*********************************************************************
|
||
* @fn ETH_TxPktChainMode
|
||
*
|
||
* @brief Ethernet sends data frames in chain mode.
|
||
*
|
||
* @param len Send data length
|
||
* pBuff send buffer pointer
|
||
*
|
||
* @return Send status.
|
||
*/
|
||
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
|
||
{
|
||
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
|
||
{
|
||
/* Return ERROR: OWN bit set */
|
||
return ETH_ERROR;
|
||
}
|
||
/* Setting the Frame Length: bits[12:0] */
|
||
DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1);
|
||
DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff;
|
||
|
||
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
|
||
#if HARDWARE_CHECKSUM_CONFIG
|
||
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
|
||
#else
|
||
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
|
||
#endif
|
||
|
||
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
||
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||
|
||
/* Clear TBUS ETHERNET DMA flag */
|
||
ETH->DMASR = ETH_DMASR_TBUS;
|
||
/* Resume DMA transmission*/
|
||
ETH->DMATPDR = 0;
|
||
|
||
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||
/* Chained Mode */
|
||
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||
/* Return SUCCESS */
|
||
return ETH_SUCCESS;
|
||
}
|
||
|
||
/*********************************************************************
|
||
* @fn WCHNET_ETHIsr
|
||
*
|
||
* @brief Ethernet Interrupt Service Routine
|
||
*
|
||
* @return none
|
||
*/
|
||
void WCHNET_ETHIsr(void)
|
||
{
|
||
uint32_t intStat;
|
||
|
||
intStat = ETH->DMASR;
|
||
if (intStat & ETH_DMA_FLAG_AIS)
|
||
{
|
||
if (intStat & ETH_DMA_FLAG_RBU)
|
||
{
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_RBU);
|
||
}
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_AIS);
|
||
}
|
||
|
||
if( intStat & ETH_DMA_FLAG_NIS )
|
||
{
|
||
if( intStat & ETH_DMA_FLAG_R )
|
||
{
|
||
/*If you don't use the Ethernet library,
|
||
* you can do some data processing operations here*/
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_R);
|
||
}
|
||
if( intStat & ETH_DMA_FLAG_T )
|
||
{
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_T);
|
||
}
|
||
if( intStat & ETH_DMA_FLAG_PHYSR)
|
||
{
|
||
ETH_CheckPhyInterruptStatus( );
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_PHYSR);
|
||
}
|
||
ETH_DMAClearITPendingBit(ETH_DMA_FLAG_NIS);
|
||
}
|
||
}
|
||
|
||
/*********************************************************************
|
||
* @fn ETH_Init
|
||
*
|
||
* @brief Ethernet initialization.
|
||
*
|
||
* @return none
|
||
*/
|
||
void ETH_Init( uint8_t *macAddr )
|
||
{
|
||
ETH_Configuration( macAddr );
|
||
PHY_LEDCfg();
|
||
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||
pDMARxSet = DMARxDscrTab;
|
||
pDMATxSet = DMATxDscrTab;
|
||
NVIC_EnableIRQ(ETH_IRQn);
|
||
NVIC_SetPriority(ETH_IRQn, 0);
|
||
}
|
||
|
||
/*********************************************************************
|
||
* @fn ETH_LibInit
|
||
*
|
||
* @brief Ethernet library initialization program
|
||
*
|
||
* @return command status
|
||
*/
|
||
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr )
|
||
{
|
||
uint8_t s;
|
||
struct _WCH_CFG cfg;
|
||
|
||
memset(&cfg,0,sizeof(cfg));
|
||
cfg.TxBufSize = ETH_TX_BUF_SZE;
|
||
cfg.TCPMss = WCHNET_TCP_MSS;
|
||
cfg.HeapSize = WCHNET_MEM_HEAP_SIZE;
|
||
cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE;
|
||
cfg.MiscConfig0 = WCHNET_MISC_CONFIG0;
|
||
cfg.MiscConfig1 = WCHNET_MISC_CONFIG1;
|
||
cfg.net_send = ETH_TxPktChainMode;
|
||
cfg.CheckValid = WCHNET_CFG_VALID;
|
||
s = WCHNET_ConfigLIB(&cfg);
|
||
if( s ){
|
||
return (s);
|
||
}
|
||
s = WCHNET_Init(ip,gwip,mask,macaddr);
|
||
ETH_Init( macaddr );
|
||
return (s);
|
||
}
|
||
|
||
/******************************** endfile @ eth_driver ******************************/
|