1017 lines
25 KiB
C
1017 lines
25 KiB
C
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#include "includes.h"
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/****************************************************
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//define
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*****************************************************/
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volatile int R_CMPA_BUF,R_CMPB_BUF;
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//volatile int R_SIOTX_count,R_SIORX_count;
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volatile int R_SIORX_buf[10];
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/****************************************************
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//extern
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*****************************************************/
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extern void delay_nms(unsigned int t);
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/*************************************************************/
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//CORET Interrupt
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//If you use a touch library file that does not contain coret
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//you need to open this interrupt entry
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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//void CORETHandler(void)
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//{
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// // ISR content ...
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//}
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/*************************************************************/
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//SYSCON Interrupt
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SYSCONIntHandler(void)
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{
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// ISR content ...
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nop;
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if((SYSCON->MISR&ISOSC_ST)==ISOSC_ST) //ISOSC stable interrupt
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{
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SYSCON->ICR = ISOSC_ST;
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}
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else if((SYSCON->MISR&IMOSC_ST)==IMOSC_ST) //IMOSC stable interrupt
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{
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SYSCON->ICR = IMOSC_ST;
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}
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else if((SYSCON->MISR&EMOSC_ST)==EMOSC_ST) //EMOSC stable interrupt
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{
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SYSCON->ICR = EMOSC_ST;
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}
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else if((SYSCON->MISR&HFOSC_ST)==HFOSC_ST) //HFOSC stable interrupt
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{
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SYSCON->ICR = HFOSC_ST;
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}
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else if((SYSCON->MISR&SYSCLK_ST)==SYSCLK_ST) //SYSCLK change end & stable interrupt
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{
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SYSCON->ICR = SYSCLK_ST;
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}
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else if((SYSCON->MISR&IWDT_INT_ST)==IWDT_INT_ST) //IWDT alarm window interrupt
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{
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SYSCON->ICR = IWDT_INT_ST;
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// SYSCON->IWDCNT=0x5aul<<24;
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}
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else if((SYSCON->MISR&WKI_INT_ST)==WKI_INT_ST)
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{
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SYSCON->ICR = WKI_INT_ST;
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}
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else if((SYSCON->MISR&RAMERRINT_ST)==RAMERRINT_ST) //SRAM check fail interrupt
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{
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SYSCON->ICR = RAMERRINT_ST;
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}
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else if((SYSCON->MISR&LVD_INT_ST)==LVD_INT_ST) //LVD threshold interrupt
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{
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nop;
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SYSCON->ICR = LVD_INT_ST;
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}
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else if((SYSCON->MISR&HWD_ERR_ST)==HWD_ERR_ST) //Hardware Divider divisor = 0 interrupt
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{
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SYSCON->ICR = HWD_ERR_ST;
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}
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else if((SYSCON->MISR&EFL_ERR_ST)==EFL_ERR_ST) //Flash check fail interrupt
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{
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SYSCON->ICR = EFL_ERR_ST;
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}
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else if((SYSCON->MISR&OPTERR_INT)==OPTERR_INT) //Option load fail interrupt
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{
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SYSCON->ICR = OPTERR_INT;
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}
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else if((SYSCON->MISR&EM_CMLST_ST)==EM_CMLST_ST) //EMOSC clock monitor fail interrupt
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{
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SYSCON->ICR = EM_CMLST_ST;
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}
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else if((SYSCON->MISR&EM_EVTRG0_ST)==EM_EVTRG0_ST) //Event Trigger Channel 0 Interrupt
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{
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SYSCON->ICR = EM_EVTRG0_ST;
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}
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else if((SYSCON->MISR&EM_EVTRG1_ST)==EM_EVTRG1_ST) //Event Trigger Channel 1 Interrupt
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{
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SYSCON->ICR = EM_EVTRG1_ST;
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}
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else if((SYSCON->MISR&EM_EVTRG2_ST)==EM_EVTRG2_ST) //Event Trigger Channel 2 Interrupt
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{
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SYSCON->ICR = EM_EVTRG2_ST;
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}
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else if((SYSCON->MISR&EM_EVTRG3_ST)==EM_EVTRG3_ST) //Event Trigger Channel 3 Interrupt
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{
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SYSCON->ICR = EM_EVTRG3_ST;
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}
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else if((SYSCON->MISR&CMD_ERR_ST)==CMD_ERR_ST) //Command error interrupt
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{
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SYSCON->ICR = CMD_ERR_ST;
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}
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}
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/*************************************************************/
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//IFC Interrupt
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void IFCIntHandler(void)
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{
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// ISR content ...
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if(IFC->MISR&ERS_END_INT)
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{
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IFC->ICR=ERS_END_INT;
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}
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else if(IFC->MISR&RGM_END_INT)
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{
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IFC->ICR=RGM_END_INT;
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}
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else if(IFC->MISR&PEP_END_INT)
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{
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IFC->ICR=PEP_END_INT;
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}
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else if(IFC->MISR&PROT_ERR_INT)
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{
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IFC->ICR=PROT_ERR_INT;
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}
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else if(IFC->MISR&UDEF_ERR_INT)
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{
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IFC->ICR=UDEF_ERR_INT;
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}
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else if(IFC->MISR&ADDR_ERR_INT)
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{
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IFC->ICR=ADDR_ERR_INT;
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}
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else if(IFC->MISR&OVW_ERR_INT)
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{
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IFC->ICR=OVW_ERR_INT;
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}
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}
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/*************************************************************/
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//ADC Interrupt
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void ADCIntHandler(void)
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{
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// ISR content ...
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if((ADC0->SR&ADC12_EOC)==ADC12_EOC) //ADC EOC interrupt
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{
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ADC0->CSR = ADC12_EOC;
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}
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else if((ADC0->SR&ADC12_READY)==ADC12_READY) //ADC READY interrupt
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{
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ADC0->CSR = ADC12_READY;
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}
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else if((ADC0->SR&ADC12_OVR)==ADC12_OVR) //ADC OVR interrupt
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{
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ADC0->CSR = ADC12_OVR;
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}
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else if((ADC0->SR&ADC12_CMP0H)==ADC12_CMP0H) //ADC CMP0H interrupt
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{
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ADC0->CSR = ADC12_CMP0H;
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}
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else if((ADC0->SR&ADC12_CMP0L)==ADC12_CMP0L) //ADC CMP0L interrupt.
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{
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ADC0->CSR = ADC12_CMP0L;
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}
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else if((ADC0->SR&ADC12_CMP1H)==ADC12_CMP1H) //ADC CMP1H interrupt.
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{
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ADC0->CSR = ADC12_CMP1H;
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}
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else if((ADC0->SR&ADC12_CMP1L)==ADC12_CMP1L) //ADC CMP1L interrupt.
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{
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ADC0->CSR = ADC12_CMP1L;
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}
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else if((ADC0->SR&ADC12_SEQ_END0)==ADC12_SEQ_END0) //ADC SEQ0 interrupt,SEQ1~SEQ15 replace the parameter with ADC12_SEQ_END1~ADC12_SEQ_END15
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{
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ADC0->CSR = ADC12_SEQ_END0;
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}
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}
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/*************************************************************/
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//EPT0 Interrupt
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void EPT0IntHandler(void)
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{
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// ISR content ...
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if((EPT0->MISR&EPT_TRGEV0_INT)==EPT_TRGEV0_INT) //TRGEV0 interrupt
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{
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EPT0->ICR=EPT_TRGEV0_INT;
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}
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else if((EPT0->MISR&EPT_TRGEV1_INT)==EPT_TRGEV1_INT) //TRGEV1 interrupt
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{
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EPT0->ICR=EPT_TRGEV1_INT;
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}
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else if((EPT0->MISR&EPT_TRGEV2_INT)==EPT_TRGEV2_INT) //TRGEV2 interrupt
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{
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EPT0->ICR=EPT_TRGEV2_INT;
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}
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else if((EPT0->MISR&EPT_TRGEV3_INT)==EPT_TRGEV3_INT) //TRGEV3 interrupt
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{
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EPT0->ICR=EPT_TRGEV3_INT;
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}
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else if((EPT0->MISR&EPT_CAP_LD0)==EPT_CAP_LD0) //Capture Load to CMPA interrupt
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{
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EPT0->ICR=EPT_CAP_LD0;
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EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIRT);
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EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT);
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R_CMPA_BUF=EPT0->CMPA; //Low voltage counter
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}
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else if((EPT0->MISR&EPT_CAP_LD1)==EPT_CAP_LD1) //Capture Load to CMPB interrupt
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{
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EPT0->ICR=EPT_CAP_LD1;
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EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIRT);
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EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT);
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R_CMPB_BUF=EPT0->CMPB; //Duty counter
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}
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else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2) //Capture Load to CMPC interrupt
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{
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EPT0->ICR=EPT_CAP_LD2;
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}
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else if((EPT0->MISR&EPT_CAP_LD3)==EPT_CAP_LD3) //Capture Load to CMPD interrupt
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{
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EPT0->ICR=EPT_CAP_LD3;
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}
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else if((EPT0->MISR&EPT_CAU)==EPT_CAU) //Up-Counting phase CNT = CMPA interrupt
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{
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EPT0->ICR=EPT_CAU;
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}
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else if((EPT0->MISR&EPT_CAD)==EPT_CAD) //Down-Counting phase CNT = CMPA interrupt
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{
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EPT0->ICR=EPT_CAD;
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}
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else if((EPT0->MISR&EPT_CBU)==EPT_CBU) //Up-Counting phase CNT = CMPB interrupt
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{
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EPT0->ICR=EPT_CBU;
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}
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else if((EPT0->MISR&EPT_CBD)==EPT_CBD) //Down-Counting phase CNT = CMPB interrupt
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{
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EPT0->ICR=EPT_CBD;
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}
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else if((EPT0->MISR&EPT_CCU)==EPT_CCU) //Up-Counting phase CNT = CMPC interrupt
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{
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EPT0->ICR=EPT_CCU;
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}
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else if((EPT0->MISR&EPT_CCD)==EPT_CCD) //Down-Counting phase CNT = CMPC interrupt
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{
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EPT0->ICR=EPT_CCD;
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}
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else if((EPT0->MISR&EPT_CDU)==EPT_CDU) //Up-Counting phase CNT = CMPD interrupt
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{
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EPT0->ICR=EPT_CDU;
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}
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else if((EPT0->MISR&EPT_CDD)==EPT_CDD) //Down-Counting phase CNT = CMPD interrupt
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{
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EPT0->ICR=EPT_CDD;
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}
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else if((EPT0->MISR&EPT_PEND)==EPT_PEND) //End of cycle interrupt
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{
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EPT0->ICR=EPT_PEND;
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//EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(50,0,50,0,0);
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EPT_Stop();
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}
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//Emergency interruption
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if((EPT0->EMMISR&EPT_EP0_EMINT)==EPT_EP0_EMINT) //interrupt flag of EP0 event
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{
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EPT0->EMICR=EPT_EP0_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP1_EMINT)==EPT_EP1_EMINT) //interrupt flag of EP1 event
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{
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EPT0->EMICR=EPT_EP1_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP2_EMINT)==EPT_EP2_EMINT) //interrupt flag of EP2 event
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{
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EPT0->EMICR=EPT_EP2_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP3_EMINT)==EPT_EP3_EMINT) //interrupt flag of EP3 event
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{
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EPT0->EMICR=EPT_EP3_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP4_EMINT)==EPT_EP4_EMINT) //interrupt flag of EP4 event
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{
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EPT0->EMICR=EPT_EP4_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP5_EMINT)==EPT_EP5_EMINT) //interrupt flag of EP5 event
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{
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EPT0->EMICR=EPT_EP5_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT) //interrupt flag of EP6 event
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{
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EPT0->EMICR=EPT_EP6_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EP7_EMINT)==EPT_EP7_EMINT) //interrupt flag of EP7 event
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{
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EPT0->EMICR=EPT_EP7_EMINT;
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}
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else if((EPT0->EMMISR&EPT_CPU_FAULT_EMINT)==EPT_CPU_FAULT_EMINT) //interrupt flag of CPU_FAULT event
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{
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EPT0->EMICR=EPT_CPU_FAULT_EMINT;
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}
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else if((EPT0->EMMISR&EPT_MEM_FAULT_EMINT)==EPT_MEM_FAULT_EMINT) //interrupt flag of MEM_FAULT event
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{
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EPT0->EMICR=EPT_MEM_FAULT_EMINT;
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}
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else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT) //interrupt flag of EOM_FAULT event
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{
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|
|
EPT0->EMICR=EPT_EOM_FAULT_EMINT;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//WWDT Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void WWDTHandler(void)
|
|||
|
|
{
|
|||
|
|
WWDT->ICR=0X01;
|
|||
|
|
WWDT_CNT_Load(0xFF);
|
|||
|
|
if((WWDT->MISR&WWDT_EVI)==WWDT_EVI) //WWDT EVI interrupt
|
|||
|
|
{
|
|||
|
|
WWDT->ICR = WWDT_EVI;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//GPT0 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void GPT0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if((GPT0->MISR&GPT_INT_TRGEV0)==GPT_INT_TRGEV0) //TRGEV0 interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_TRGEV0;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_TRGEV1)==GPT_INT_TRGEV1) //TRGEV1 interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_TRGEV1;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CAPLD0)==GPT_INT_CAPLD0) //Capture Load to CMPA interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CAPLD0;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CAPLD1)==GPT_INT_CAPLD1) //Capture Load to CMPB interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CAPLD1;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CAU)==GPT_INT_CAU) //Up-Counting phase CNT = CMPA Interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CAU;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CAD)==GPT_INT_CAD) //Down-Counting phase CNT = CMPA Interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CAD;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CBU)==GPT_INT_CBU) //Up-Counting phase CNT = CMPB Interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CBU;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_CBD)==GPT_INT_CBD) //Down-Counting phase CNT = CMPB Interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_CBD;
|
|||
|
|
}
|
|||
|
|
else if((GPT0->MISR&GPT_INT_PEND)==GPT_INT_PEND) //End of cycle interrupt
|
|||
|
|
{
|
|||
|
|
GPT0->ICR = GPT_INT_PEND;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//RTC Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void RTCIntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if((RTC->MISR&ALRA_INT)==ALRA_INT) //Interrupt of alarm A
|
|||
|
|
{
|
|||
|
|
RTC->ICR=ALRA_INT;
|
|||
|
|
RTC->KEY=0XCA53;
|
|||
|
|
RTC->CR=RTC->CR|0x01;
|
|||
|
|
RTC->TIMR=(0x10<<16)|(0x00<<8)|(0x00); //Hour bit6->0:am 1:pm
|
|||
|
|
while(RTC->CR&0x02); //busy TIMR DATR ALRAR ALRBR Update done
|
|||
|
|
RTC->CR &= ~0x1;
|
|||
|
|
}
|
|||
|
|
else if((RTC->MISR&ALRB_INT)==ALRB_INT) //Interrupt of alarm B
|
|||
|
|
{
|
|||
|
|
RTC->ICR=ALRB_INT;
|
|||
|
|
}
|
|||
|
|
else if((RTC->MISR&CPRD_INT)==CPRD_INT) //Interrupt of alarm CPRD
|
|||
|
|
{
|
|||
|
|
RTC->ICR=CPRD_INT;
|
|||
|
|
}
|
|||
|
|
else if((RTC->MISR&RTC_TRGEV0_INT)==RTC_TRGEV0_INT) //Interrupt of trigger event 0
|
|||
|
|
{
|
|||
|
|
RTC->ICR=RTC_TRGEV0_INT;
|
|||
|
|
}
|
|||
|
|
else if((RTC->MISR&RTC_TRGEV1_INT)==RTC_TRGEV1_INT) //Interrupt of trigger event 1
|
|||
|
|
{
|
|||
|
|
RTC->ICR=RTC_TRGEV1_INT;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//UART0 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void UART0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
char inchar = 0;
|
|||
|
|
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((UART0->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
|
|||
|
|
{
|
|||
|
|
UART0->ISR=UART_RX_INT_S;
|
|||
|
|
inchar = CSP_UART_GET_DATA(UART0);
|
|||
|
|
UART0_RecvINT_Processing(inchar);
|
|||
|
|
}
|
|||
|
|
else if( (UART0->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
|
|||
|
|
{
|
|||
|
|
UART0->ISR=UART_TX_INT_S;
|
|||
|
|
//TxDataFlag = TRUE;
|
|||
|
|
}
|
|||
|
|
else if ((UART0->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART0->ISR=UART_RX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART0->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART0->ISR=UART_TX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART0->ISR&UART_TX_DONE_S)==UART_TX_DONE_S)
|
|||
|
|
{
|
|||
|
|
UART0->ISR=UART_TX_DONE_S;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//UART1 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void UART1IntHandler(void)
|
|||
|
|
{
|
|||
|
|
char inchar = 0;
|
|||
|
|
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((UART1->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
|
|||
|
|
{
|
|||
|
|
UART1->ISR=UART_RX_INT_S;
|
|||
|
|
inchar = CSP_UART_GET_DATA(UART1);
|
|||
|
|
UART1_RecvINT_Processing(inchar);
|
|||
|
|
}
|
|||
|
|
else if( (UART1->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
|
|||
|
|
{
|
|||
|
|
UART1->ISR=UART_TX_INT_S;
|
|||
|
|
//TxDataFlag = TRUE;
|
|||
|
|
RS485_Comming1 = 0x01;
|
|||
|
|
|
|||
|
|
if(RS485_Comm_Flag1 == 0x01){
|
|||
|
|
RS485_Comm_Start1 ++;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if ((UART1->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART1->ISR=UART_RX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART1->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART1->ISR=UART_TX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART1->ISR&UART_TX_DONE_S)==UART_TX_DONE_S)
|
|||
|
|
{
|
|||
|
|
UART1->ISR=UART_TX_DONE_S;
|
|||
|
|
|
|||
|
|
RS485_Comming1 = 0x00;
|
|||
|
|
if(RS485_Comm_Flag1 == 0x01){
|
|||
|
|
RS485_Comm_End1 ++;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//UART2 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void UART2IntHandler(void)
|
|||
|
|
{
|
|||
|
|
char inchar = 0;
|
|||
|
|
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((UART2->ISR&UART_RX_INT_S)==UART_RX_INT_S) //RX interrupt
|
|||
|
|
{
|
|||
|
|
UART2->ISR=UART_RX_INT_S;
|
|||
|
|
inchar = CSP_UART_GET_DATA(UART2);
|
|||
|
|
UART2_RecvINT_Processing(inchar);
|
|||
|
|
}
|
|||
|
|
else if( (UART2->ISR&UART_TX_INT_S)==UART_TX_INT_S ) //TX interrupt
|
|||
|
|
{
|
|||
|
|
UART2->ISR=UART_TX_INT_S;
|
|||
|
|
|
|||
|
|
RS485_Comming = 0x01;
|
|||
|
|
|
|||
|
|
if(RS485_Comm_Flag == 0x01){
|
|||
|
|
RS485_Comm_Start ++;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if ((UART2->ISR&UART_RX_IOV_S)==UART_RX_IOV_S) //RX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART2->ISR=UART_RX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART2->ISR&UART_TX_IOV_S)==UART_TX_IOV_S) //TX overrun interrupt
|
|||
|
|
{
|
|||
|
|
UART2->ISR=UART_TX_IOV_S;
|
|||
|
|
}
|
|||
|
|
else if ((UART2->ISR&UART_TX_DONE_S)==UART_TX_DONE_S)
|
|||
|
|
{
|
|||
|
|
UART2->ISR=UART_TX_DONE_S;
|
|||
|
|
|
|||
|
|
RS485_Comming = 0x00;
|
|||
|
|
if(RS485_Comm_Flag == 0x01){
|
|||
|
|
RS485_Comm_End ++;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//I2C Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void I2CIntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
//I2C_Slave_Receive(); //I2C slave receive function in interruption
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//SPI Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void SPI0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if((SPI0->MISR&SPI_PORIM)==SPI_PORIM) //Receive Overrun Interrupt
|
|||
|
|
{
|
|||
|
|
SPI0->ICR = SPI_PORIM;
|
|||
|
|
}
|
|||
|
|
else if((SPI0->MISR&SPI_RTIM)==SPI_RTIM) //Receive Timeout Interrupt
|
|||
|
|
{
|
|||
|
|
SPI0->ICR = SPI_RTIM;
|
|||
|
|
}
|
|||
|
|
else if((SPI0->MISR&SPI_RXIM)==SPI_RXIM) //Receive FIFO Interrupt,FIFO can be set 1/8,1/4,1/2 FIFO Interrupt
|
|||
|
|
{
|
|||
|
|
SPI0->ICR = SPI_RXIM;
|
|||
|
|
if(SPI0->DR==0xaa)
|
|||
|
|
{
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x11;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x12;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x13;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x14;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x15;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
/* while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x16;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x17;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
|
|||
|
|
while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
|
|||
|
|
SPI0->DR = 0x18;
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？*/
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
if(((SPI0->SR) & SSP_TFE)!=SSP_TFE)
|
|||
|
|
{
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
SPI0->DR=0x0; //FIFO=0
|
|||
|
|
while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM) //Transmit FIFO Interrupt
|
|||
|
|
{
|
|||
|
|
SPI0->ICR = SPI_TXIM;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//SIO Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void SIO0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
//The sequence is more than 16bit to send the program
|
|||
|
|
//1.disable interrupt in main loop 2.set the highest priority in the interrupt
|
|||
|
|
/*CK801->IPR[0]=0X40404040;
|
|||
|
|
CK801->IPR[1]=0X40404040;
|
|||
|
|
CK801->IPR[2]=0X40404040;
|
|||
|
|
CK801->IPR[3]=0X40404040;
|
|||
|
|
CK801->IPR[4]=0X40404040;
|
|||
|
|
CK801->IPR[5]=0X40404000;
|
|||
|
|
CK801->IPR[6]=0X40404040;
|
|||
|
|
CK801->IPR[7]=0X40404040;*/
|
|||
|
|
//TXBUFEMPT The sequence length exceeds 15bit needs to be updated into this interrupt
|
|||
|
|
if(SIO0->MISR&0X04)
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X04;
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
if(SIO0->MISR&0X01) //TXDNE 发送完成
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X01;
|
|||
|
|
//SIO0->TXBUF=0x00; //0:D0,1:D1,2:DL,3:DH;
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
//INTC_ICER_WRITE(SIO_INT);
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//The sequence is less than 16bit to send the program
|
|||
|
|
/*if(SIO0->MISR&0X01) //TXDNE
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X01;
|
|||
|
|
delay_nms(10);
|
|||
|
|
SIO0->TXBUF=(0x03<<30)|(0x02<<28)|(0x03<<26)|(0x02<<24)|(0x03<<22)|(0x02<<20)|(0x03<<18)|(0x02<<16)|
|
|||
|
|
(0x01<<14)|(0x00<<12)|(0x01<<10)|(0x00<<8)|(0x01<<6)|(0x00<<4)|(0x01<<2)|(0x0<<0); //0:D0,1:D1,2:DL,3:DH;
|
|||
|
|
}*/
|
|||
|
|
|
|||
|
|
if(SIO0->MISR&0X02) //RXDNE
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X02;
|
|||
|
|
// if(R_SIORX_count>=1)
|
|||
|
|
// {
|
|||
|
|
// R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF&0xff000000; //8bit
|
|||
|
|
// nop;
|
|||
|
|
// R_SIORX_count=0;
|
|||
|
|
// }
|
|||
|
|
}
|
|||
|
|
else if(SIO0->MISR&0X08) //RXBUFFULL
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X08;
|
|||
|
|
// if(R_SIORX_count<1)
|
|||
|
|
// {
|
|||
|
|
// R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF; //32bit
|
|||
|
|
// R_SIORX_count++;
|
|||
|
|
// }
|
|||
|
|
}
|
|||
|
|
else if(SIO0->MISR&0X010) //BREAK
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X10;
|
|||
|
|
}
|
|||
|
|
else if(SIO0->MISR&0X020) //TIMEOUT
|
|||
|
|
{
|
|||
|
|
SIO0->ICR=0X20;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//EXT0/16 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void EXI0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0) //EXT0 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN0;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN16)==EXI_PIN16) //EXT16 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN16;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//EXT1/17 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void EXI1IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1) //EXT1 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN1;
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN17)==EXI_PIN17) //EXT17 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN17;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//EXI2~3 18~19Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void EXI2to3IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2) //EXT2 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN2;
|
|||
|
|
// RLY_State_Multi_Control();
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3) //EXT3 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN3;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN18)==EXI_PIN18) //EXT18 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN18;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN19)==EXI_PIN19) //EXT19 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN19;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//EXI4~9 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void EXI4to9IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4) //EXT4 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN4;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5) //EXT5 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN5;
|
|||
|
|
|
|||
|
|
//2025-03-24，总线繁忙判断
|
|||
|
|
|
|||
|
|
BusBusy_Task();
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6) //EXT6 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN6;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7) //EXT7 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN7;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8) //EXT8 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN8;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9) //EXT9 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN9;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//EXI4 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void EXI10to15IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if ((SYSCON->EXIRS&EXI_PIN10)==EXI_PIN10) //EXT10 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN10;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN11)==EXI_PIN11) //EXT11 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN11;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN12)==EXI_PIN12) //EXT12 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN12;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN13)==EXI_PIN13) //EXT13 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN13;
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN14)==EXI_PIN14) //EXT14 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN14;
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else if ((SYSCON->EXIRS&EXI_PIN15)==EXI_PIN15) //EXT15 Interrupt
|
|||
|
|
{
|
|||
|
|
SYSCON->EXICR = EXI_PIN15;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//CONTA Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void CNTAIntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
//LPT Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void LPTIntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if((LPT->MISR&LPT_TRGEV0)==LPT_TRGEV0) //TRGEV0 interrupt
|
|||
|
|
{
|
|||
|
|
LPT->ICR = LPT_TRGEV0;
|
|||
|
|
}
|
|||
|
|
else if((LPT->MISR&LPT_MATCH)==LPT_MATCH) //MATCH interrupt
|
|||
|
|
{
|
|||
|
|
LPT->ICR = LPT_MATCH;
|
|||
|
|
}
|
|||
|
|
else if((LPT->MISR&LPT_PEND)==LPT_PEND) //PEND interrupt
|
|||
|
|
{
|
|||
|
|
LPT->ICR = LPT_PEND;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
/*************************************************************/
|
|||
|
|
//BT0 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
U8_T BT_TEMP_State = 1;
|
|||
|
|
void BT0IntHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
if((BT0->MISR&BT_PEND)==BT_PEND) //BT0 PEND interrupt
|
|||
|
|
{
|
|||
|
|
BT0->ICR = BT_PEND;
|
|||
|
|
|
|||
|
|
//BT_Stop_Low(BT0);
|
|||
|
|
|
|||
|
|
BT0->CR =BT0->CR & ~(0x01<<6);
|
|||
|
|
BT0->RSSR &=0X0;
|
|||
|
|
}
|
|||
|
|
else if((BT0->MISR&BT_CMP)==BT_CMP) //BT0 CMP Match interrupt
|
|||
|
|
{
|
|||
|
|
BT0->ICR = BT_CMP;
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else if((BT0->MISR&BT_OVF)==BT_OVF) //BT0 OVF interrupt
|
|||
|
|
{
|
|||
|
|
BT0->ICR = BT_OVF;
|
|||
|
|
}
|
|||
|
|
else if((BT0->MISR&BT_EVTRG)==BT_EVTRG) //BT0 Event trigger interrupt
|
|||
|
|
{
|
|||
|
|
BT0->ICR = BT_EVTRG;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
volatile U32_T SysTick_100us = 0;
|
|||
|
|
volatile U32_T SysTick_1ms = 0;
|
|||
|
|
|
|||
|
|
/*************************************************************/
|
|||
|
|
//BT1 Interrupt
|
|||
|
|
//EntryParameter:NONE
|
|||
|
|
//ReturnValue:NONE
|
|||
|
|
/*************************************************************/
|
|||
|
|
void BT1IntHandler(void)
|
|||
|
|
{
|
|||
|
|
static U8_T NUM = 0;
|
|||
|
|
// ISR content ...
|
|||
|
|
if((BT1->MISR&BT_PEND)==BT_PEND) //BT1 PEND interrupt
|
|||
|
|
{
|
|||
|
|
BT1->ICR = BT_PEND;
|
|||
|
|
}
|
|||
|
|
else if((BT1->MISR&BT_CMP)==BT_CMP) //BT1 CMP Match interrupt
|
|||
|
|
{
|
|||
|
|
BT1->ICR = BT_CMP;
|
|||
|
|
|
|||
|
|
NUM++;
|
|||
|
|
SysTick_100us++;
|
|||
|
|
|
|||
|
|
if(NUM >= 10){
|
|||
|
|
NUM = 0;
|
|||
|
|
SysTick_1ms++;
|
|||
|
|
|
|||
|
|
BusIdle_Task();
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
else if((BT1->MISR&BT_OVF)==BT_OVF) //BT1 OVF interrupt
|
|||
|
|
{
|
|||
|
|
BT1->ICR = BT_OVF;
|
|||
|
|
}
|
|||
|
|
else if((BT1->MISR&BT_EVTRG)==BT_EVTRG) //BT1 Event trigger interrupt
|
|||
|
|
{
|
|||
|
|
BT1->ICR = BT_EVTRG;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
/*************************************************************/
|
|||
|
|
/*************************************************************/
|
|||
|
|
/*************************************************************/
|
|||
|
|
//void TKEYIntHandler(void)
|
|||
|
|
//{
|
|||
|
|
// // ISR content ...
|
|||
|
|
//
|
|||
|
|
//}
|
|||
|
|
|
|||
|
|
void PriviledgeVioHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void SystemDesPtr(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void MisalignedHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void IllegalInstrHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void AccessErrHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void BreakPointHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void UnrecExecpHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Trap0Handler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Trap1Handler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Trap2Handler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Trap3Handler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void PendTrapHandler(void)
|
|||
|
|
{
|
|||
|
|
// ISR content ...
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/
|
|||
|
|
|