130 lines
6.0 KiB
C
130 lines
6.0 KiB
C
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/*
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******************************************************************************
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* @file apt32f102_ck801.h
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_ck801_H
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#define _apt32f102_ck801_H
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//----------------------------------------------------------------------------
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// Interrupt Controller
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//----------------------------------------------------------------------------
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//#define CK801_BASEADDR ((unsigned int) 0xE000E000)
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#define CK801_BASEADDR 0xE000E000
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#define INTC_ISER CK801_BASEADDR+0x100 //INTC interrupt enable register
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#define INTC_IWER CK801_BASEADDR+0x140 //INTC wake-up interrupt enable register
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#define INTC_ICER CK801_BASEADDR+0x180 //INTC interrupt enable clear register
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#define INTC_IWDR CK801_BASEADDR+0x1C0 //INTC wake-up interrupt enable clear register
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#define INTC_ISPR CK801_BASEADDR+0x200 //INTC interrupt pending register
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#define INTC_ICPR CK801_BASEADDR+0x280 //INTC interrupt pending clear register
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#define INTC_IABR CK801_BASEADDR+0x300 //INTC interrupt acknowledge status register
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#define INTC_IPR0 CK801_BASEADDR+0x400 //INTC interrupt priority register
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#define INTC_IPR1 CK801_BASEADDR+0x404 //INTC interrupt priority register
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#define INTC_IPR2 CK801_BASEADDR+0x408 //INTC interrupt priority register
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#define INTC_IPR3 CK801_BASEADDR+0x40C //INTC interrupt priority register
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#define INTC_IPR4 CK801_BASEADDR+0x410 //INTC interrupt priority register
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#define INTC_IPR5 CK801_BASEADDR+0x414 //INTC interrupt priority register
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#define INTC_IPR6 CK801_BASEADDR+0x418 //INTC interrupt priority register
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#define INTC_IPR7 CK801_BASEADDR+0x41C //INTC interrupt priority register
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#define INTC_ISR CK801_BASEADDR+0xC00 //INTC interrupt status register
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#define INTC_IPTR CK801_BASEADDR+0xC04 //INTC interrupt pending threshold register
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#define INTC_ISER_WRITE(val) *(volatile UINT32 *) (INTC_ISER ) = val
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#define INTC_IWER_WRITE(val) *(volatile UINT32 *) (INTC_IWER ) = val
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#define INTC_ICER_WRITE(val) *(volatile UINT32 *) (INTC_ICER ) = val
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#define INTC_IWDR_WRITE(val) *(volatile UINT32 *) (INTC_IWDR ) = val
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#define INTC_ISPR_WRITE(val) *(volatile UINT32 *) (INTC_ISPR ) = val
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#define INTC_ICPR_WRITE(val) *(volatile UINT32 *) (INTC_ICPR ) = val
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#define INTC_IABR_WRITE(val) *(volatile UINT32 *) (INTC_IABR ) = val
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#define INTC_IPR0_WRITE(val) *(volatile UINT32 *) (INTC_IPR0 ) = val
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#define INTC_IPR1_WRITE(val) *(volatile UINT32 *) (INTC_IPR1 ) = val
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#define INTC_IPR2_WRITE(val) *(volatile UINT32 *) (INTC_IPR2 ) = val
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#define INTC_IPR3_WRITE(val) *(volatile UINT32 *) (INTC_IPR3 ) = val
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#define INTC_IPR4_WRITE(val) *(volatile UINT32 *) (INTC_IPR4 ) = val
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#define INTC_IPR5_WRITE(val) *(volatile UINT32 *) (INTC_IPR5 ) = val
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#define INTC_IPR6_WRITE(val) *(volatile UINT32 *) (INTC_IPR6 ) = val
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#define INTC_IPR7_WRITE(val) *(volatile UINT32 *) (INTC_IPR7 ) = val
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#define INTC_ISR_WRITE(val) *(volatile UINT32 *) (INTC_ISR ) = val
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#define INTC_IPTR_WRITE(val) *(volatile UINT32 *) (INTC_IPTR ) = val
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#define INTC_ISER_READ(intc) (intc->ISER )
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#define INTC_IWER_READ(intc) (intc->IWER )
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#define INTC_ICER_READ(intc) (intc->ICER )
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#define INTC_IWDR_READ(intc) (intc->IWDR )
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#define INTC_ISPR_READ(intc) (intc->ISPR )
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#define INTC_ICPR_READ(intc) (intc->ICPR )
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#define INTC_IABR_READ(intc) (intc->IABR )
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#define INTC_IPR0_READ(intc) (intc->IPR0 )
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#define INTC_IPR1_READ(intc) (intc->IPR1 )
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#define INTC_IPR2_READ(intc) (intc->IPR2 )
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#define INTC_IPR3_READ(intc) (intc->IPR3 )
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#define INTC_IPR4_READ(intc) (intc->IPR4 )
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#define INTC_IPR5_READ(intc) (intc->IPR5 )
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#define INTC_IPR6_READ(intc) (intc->IPR6 )
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#define INTC_IPR7_READ(intc) (intc->IPR7 )
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#define INTC_ISR_READ(intc) (intc->ISR )
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#define INTC_IPTR_READ(intc) (intc->IPTR )
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typedef enum IRQn
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{
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ISR_Restart = -32,
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ISR_Misaligned_Access = -31,
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ISR_Access_Error = -30,
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ISR_Divided_By_Zero = -29,
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ISR_Illegal = -28,
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ISR_Privlege_Violation = -27,
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ISR_Trace_Exection = -26,
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ISR_Breakpoint_Exception = -25,
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ISR_Unrecoverable_Error = -24,
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ISR_Idly4_Error = -23,
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ISR_Auto_INT = -22,
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ISR_Auto_FINT = -21,
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ISR_Reserved_HAI = -20,
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ISR_Reserved_FP = -19,
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ISR_TLB_Ins_Empty = -18,
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ISR_TLB_Data_Empty = -17,
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INTC_CORETIM_IRQn = 0,
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INTC_TIME1_IRQn = 1,
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INTC_UART0_IRQn = 2,
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INTC_GPIOA2_IRQn = 8,
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} IRQn_Type;
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void INTC_Init(void);
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void force_interrupt(IRQn_Type IRQn);
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void CK_CPU_EnAllNormalIrq(void);
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void CK_CPU_DisAllNormalIrq(void);
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef uint32_t
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#define uint32_t unsigned int
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#endif
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#ifndef uint8_t
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#define uint8_t unsigned char
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#endif
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#endif
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/
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