221 lines
7.4 KiB
C
221 lines
7.4 KiB
C
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/*
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******************************************************************************
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* @file main.c
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_gpio_H
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#define _apt32f102_gpio_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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#define GPIO_RESET_VALUE (0x00000000)
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//--------------------------------------------------------------------------------
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//-----------------------------GPIO value enum define--------------------------
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//--------------------------------------------------------------------------------
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/**
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* @brief GPIO pin numbner
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*/
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typedef enum
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{
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PIN_0 = 0, /*!< Pin 0 selected */
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PIN_1 = 4, /*!< Pin 1 selected */
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PIN_2 = 8, /*!< Pin 2 selected */
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PIN_3 = 12, /*!< Pin 3 selected */
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PIN_4 = 16, /*!< Pin 4 selected */
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PIN_5 = 20, /*!< Pin 5 selected */
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PIN_6 = 24, /*!< Pin 6 selected */
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PIN_7 = 28, /*!< Pin 7 selected */
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PIN_8 = 0, /*!< Pin 8 selected */
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PIN_9 = 4, /*!< Pin 9 selected */
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PIN_10 = 8, /*!< Pin 10 selected */
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PIN_11 = 12, /*!< Pin 11 selected */
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PIN_12 = 16, /*!< Pin 12 selected */
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PIN_13 = 20, /*!< Pin 13 selected */
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PIN_14 = 24, /*!< Pin 13 selected */
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PIN_15 = 28, /*!< Pin 13 selected */
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}GPIO_Pin_TypeDef;
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/**
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* @brief GPIO high/low register
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*/
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typedef enum
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{
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LowByte = 0,
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HighByte = 1,
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}GPIO_byte_TypeDef;
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/**
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* @brief GPIO IO status
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*/
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typedef enum
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{
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Intput = 1,
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Output = 0,
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}GPIO_Dir_TypeDef;
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/**
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* @brief GPIO IO mode
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*/
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typedef enum
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{
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PUDR = 0, //pull high or low
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DSCR =1, //drive strenth
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OMCR =2, //open drain
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IECR =3, //int
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}GPIO_Mode_TypeDef;
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/**
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* @brief GPIO IO Group
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*/
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typedef enum
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{
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PA0 = 0,
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PB0 = 2,
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GPIOA = 0,
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GPIOB = 2,
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}GPIO_Group_TypeDef;
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/**
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* @brief GPIO exi number
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*/
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typedef enum
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{
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EXI0 = 0,
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EXI1 = 1,
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EXI2 = 2,
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EXI3 = 3,
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EXI4 = 4,
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EXI5 = 5,
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EXI6 = 6,
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EXI7 = 7,
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EXI8 = 8,
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EXI9 = 9,
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EXI10 = 10,
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EXI11 = 11,
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EXI12 = 12,
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EXI13 = 13,
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EXI14 = 14,
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EXI15 = 15,
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}GPIO_EXI_TypeDef;
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/**
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* @brief EXI PIN
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*/
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typedef enum
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{
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Selete_EXI_PIN0 = (CSP_REGISTER_T)(0),
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Selete_EXI_PIN1 = (CSP_REGISTER_T)(1),
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Selete_EXI_PIN2 = (CSP_REGISTER_T)(2),
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Selete_EXI_PIN3 = (CSP_REGISTER_T)(3),
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Selete_EXI_PIN4 = (CSP_REGISTER_T)(4),
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Selete_EXI_PIN5 = (CSP_REGISTER_T)(5),
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Selete_EXI_PIN6 = (CSP_REGISTER_T)(6),
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Selete_EXI_PIN7 = (CSP_REGISTER_T)(7),
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Selete_EXI_PIN8 = (CSP_REGISTER_T)(8),
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Selete_EXI_PIN9 = (CSP_REGISTER_T)(9),
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Selete_EXI_PIN10 = (CSP_REGISTER_T)(10),
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Selete_EXI_PIN11 = (CSP_REGISTER_T)(11),
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Selete_EXI_PIN12 = (CSP_REGISTER_T)(12),
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Selete_EXI_PIN13 = (CSP_REGISTER_T)(13),
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Selete_EXI_PIN14 = (CSP_REGISTER_T)(14),
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Selete_EXI_PIN15 = (CSP_REGISTER_T)(15),
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Selete_EXI_PIN16 = (CSP_REGISTER_T)(16),
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Selete_EXI_PIN17 = (CSP_REGISTER_T)(17),
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Selete_EXI_PIN18 = (CSP_REGISTER_T)(18),
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Selete_EXI_PIN19 = (CSP_REGISTER_T)(19)
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}GPIO_EXIPIN_TypeDef;
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/**
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* @brief GPIO INPUT MODE SETECTED
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*/
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typedef enum
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{
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INPUT_MODE_SETECTED_CMOS = 0,
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INPUT_MODE_SETECTED_TTL1 = 1,
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INPUT_MODE_SETECTED_TTL2 = 2
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}INPUT_MODE_SETECTED_TypeDef;
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#define nop asm ("nop")
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#define SetPA0(n) (GPIOA0->SODR = (1ul<<n))
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#define ClrPA0(n) (GPIOA0->CODR = (1ul<<n))
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#define SetPB0(n) (GPIOB0->SODR = (1ul<<n))
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#define ClrPB0(n) (GPIOB0->CODR = (1ul<<n))
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#define PA0in(n) (((GPIOA0->PSDR)>>n) & 1ul)
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#define PB0in(n) (((GPIOB0->PSDR)>>n) & 1ul)
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#define CSP_GPIO_SET_CONLR(cm,val) ((cm)->CONLR = val)
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#define CSP_GPIO_GET_CONLR(cm) ((cm)->CONLR)
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#define CSP_GPIO_SET_CONHR(cm,val) ((cm)->CONHR = val)
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#define CSP_GPIO_GET_CONHR(cm) ((cm)->CONHR)
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#define CSP_GPIO_SET_WODR(cm,val) ((cm)->WODR = val)
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#define CSP_GPIO_SET_SODR(cm,val) ((cm)->SODR = val)
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#define CSP_GPIO_SET_CODR(cm,val) ((cm)->CODR = val)
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#define CSP_GPIO_GET_PSDR(cm) ((cm)->PSDR)
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#define CSP_GPIO_SET_PUDR(cm,val) ((cm)->PUDR = val)
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#define CSP_GPIO_GET_PUDR(cm) ((cm)->PUDR)
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#define CSP_GPIO_SET_DSCR(cm,val) ((cm)->DSCR = val)
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#define CSP_GPIO_GET_DSCR(cm) ((cm)->DSCR)
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#define CSP_GPIO_SET_OMCR(cm,val) ((cm)->OMCR = val)
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#define CSP_GPIO_GET_OMCR(cm) ((cm)->OMCR)
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#define CSP_GPIO_SET_IECR(cm,val) ((cm)->IECR = val)
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#define CSP_GPIO_GET_IECR(cm) ((cm)->IECR)
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#define CSP_GPIO_SET_IGRP(cm,val) ((cm)->IGRP = val)
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#define CSP_GPIO_GET_IGRP(cm) ((cm)->IGRP)
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/******************************************************************************
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************************** Exported functions ************************
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******************************************************************************/
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extern void GPIOA0_DeInit(GPIO_Pin_TypeDef GPIO_Pin);
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extern void GPIO_DeInit(void);
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extern void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X);
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extern void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val);
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extern void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum);
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extern void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir);
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extern void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val);
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extern uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval);
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extern void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
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extern void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
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extern void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO);
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extern void GPIO_Debug_IO_12_13(void);
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extern void GPIO_Debug_IO_01_02(void);
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extern void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef EXIPIN_x);
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extern void GPIOA00_Set_ResetPin();
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extern void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
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extern void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
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/*************************************************************/
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#endif /**< apt32f102_gpio_H */
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/
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