feat:修改设备类型
feat:修改为红外转发设备，将中弘网关协议转换为主机红外协议
This commit is contained in:
yeyangwen
146
Source/drivers/apt32f102.c
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146
Source/drivers/apt32f102.c
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/*
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******************************************************************************
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* @file apt32f102.c
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* @author APT AE Team
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* @version V1.01
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* @date 2019/04/05
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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/**
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* @addtogroup Struct pointer assignment Functions
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* @{
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*/
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CSP_CK801_T *CK801 = (CSP_CK801_T *)CK801_BASEADDR ;
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CSP_IFC_T *IFC = (CSP_IFC_T *)APB_IFCBase ;
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CSP_SYSCON_T *SYSCON = (CSP_SYSCON_T *)APB_SYSCONBase ;
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CSP_TKEY_T *TKEY = (CSP_TKEY_T *)APB_TKEYBase ;
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CSP_TKEYBUF_T *TKEYBUF = (CSP_TKEYBUF_T *)APB_TKEYBUFBase;
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CSP_ADC12_T *ADC0 = (CSP_ADC12_T *)APB_ADC0Base ;
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CSP_GPIO_T *GPIOA0 = (CSP_GPIO_T *)APB_GPIOA0Base ; // A0
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CSP_GPIO_T *GPIOB0 = (CSP_GPIO_T *)APB_GPIOB0Base ; // B0
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CSP_IGRP_T *GPIOGRP = (CSP_IGRP_T *)APB_IGRPBase;
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CSP_UART_T *UART0 = (CSP_UART_T *)APB_UART0Base ;
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CSP_UART_T *UART1 = (CSP_UART_T *)APB_UART1Base ;
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CSP_UART_T *UART2 = (CSP_UART_T *)APB_UART2Base ;
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CSP_SSP_T *SPI0 = (CSP_SSP_T *)APB_SPI0Base ;
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CSP_I2C_T *I2C0 = (CSP_I2C_T *)APB_I2C0Base ;
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CSP_SIO_T *SIO0 = (CSP_SIO_T *)APB_SIO0Base ;
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CSP_CA_T *CA0 = (CSP_CA_T *)APB_CNTABase ;
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CSP_GPT_T *GPT0 = (CSP_GPT_T *)APB_GPT0Base;
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CSP_EPT_T *EPT0 = (CSP_EPT_T *)APB_EPT0Base ;
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CSP_ETCB_T *ETCB = (CSP_ETCB_T *)APB_ETCBBase ;
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CSP_RTC_T *RTC = (CSP_RTC_T *)APB_RTCBase ;
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CSP_LPT_T *LPT = (CSP_LPT_T *)APB_LPTBase ;
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CSP_WWDT_T *WWDT = (CSP_WWDT_T *)APB_WWDTBase ;
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CSP_BT_T *BT0 = (CSP_BT_T *)APB_BT0Base ;
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CSP_BT_T *BT1 = (CSP_BT_T *)APB_BT1Base ;
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CSP_CRC_T *CRC = (CSP_CRC_T *)AHB_CRCBase ;
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CSP_HWD_T *HWD = (CSP_HWD_T *)APB_HWDBase ;
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int __divsi3 ( int a, int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 0;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->QUOTIENT;
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}
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unsigned int __udivsi3 ( unsigned int a, unsigned int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 1;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->QUOTIENT;
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}
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int __modsi3 ( int a, int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 0;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->REMAIN;
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}
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unsigned int __umodsi3 ( unsigned int a, unsigned int b)
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{
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int PSR;
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__asm volatile(
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"mfcr %0 , psr \n\r"
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"psrclr ie \n\r"
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: "=r"(PSR)
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);
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HWD->CR = 1;
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HWD->DIVIDENT = a;
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HWD->DIVISOR = b;
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PSR |= 0x80000000;
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__asm volatile(
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"mtcr %0 , psr \n\r"
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:
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:"r"(PSR)
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);
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return HWD->REMAIN;
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}
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/
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275
Source/drivers/apt32f102_ck801.c
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275
Source/drivers/apt32f102_ck801.c
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@@ -0,0 +1,275 @@
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/*
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******************************************************************************
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* @file apt32f102_ck801.c
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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#include "apt32f102_ck801.h"
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void CK801_Init(void)
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{
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/* Initial the Interrupt source priority level registers */
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CK801->IPR[0] = 0xC0804000;
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CK801->IPR[1] = 0xC0004000;
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CK801->IPR[2] = 0xC0804000;
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CK801->IPR[3] = 0xC0804000;
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CK801->IPR[4] = 0xC0804000;
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CK801->IPR[5] = 0xC0804000;
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CK801->IPR[6] = 0xC0804000;
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CK801->IPR[7] = 0xC0804000;
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CK801->IPTR = 0x00000000;//disable threshold
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}
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void force_interrupt(IRQn_Type IRQn)
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{
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CK801->ISPR = (1 << (uint32_t)(IRQn));
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}
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void CK_CPU_EnAllNormalIrq(void)
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{
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asm ("psrset ee,ie");
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}
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void CK_CPU_DisAllNormalIrq(void)
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{
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asm ("psrclr ie");
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}
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/* ########################## NVIC functions #################################### */
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/**
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* @brief Enable Interrupt in NVIC Interrupt Controller
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*
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* @param IRQn The positive number of the external interrupt to enable
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*
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* Enable a device specific interupt in the NVIC interrupt controller.
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* The interrupt number cannot be a negative value.
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*/
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__INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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CK801->ISER = 1 << (uint32_t)(IRQn);
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}
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/**
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* @brief Disable the interrupt line for external interrupt specified
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*
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* @param IRQn The positive number of the external interrupt to disable
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*
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* Disable a device specific interupt in the NVIC interrupt controller.
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* The interrupt number cannot be a negative value.
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*/
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__INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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{
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CK801->ICER = 1 << (uint32_t)(IRQn);
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}
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/**
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* @brief Read the interrupt pending bit for a device specific interrupt source
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*
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* @param IRQn The number of the device specifc interrupt
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* @return always 0
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*/
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__INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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{
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return (uint32_t)(CK801->ISPR);
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}
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/**
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* @brief Set the pending bit for an external interrupt
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*
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* @param IRQn The number of the interrupt for set pending
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*
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* No effect.
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*/
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__INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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CK801->ISPR = (1 << (uint32_t)(IRQn));
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}
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/**
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* @brief Clear the pending bit for an external interrupt
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*
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* @param IRQn The number of the interrupt for clear pending
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*
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* No effect.
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*/
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__INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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CK801->ICPR = (1 << (uint32_t)(IRQn));
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}
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/**
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* @brief Read the active bit for an external interrupt
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*
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* @return always 0
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*
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*/
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__INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
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{
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return (CK801->IABR & (1 << IRQn));
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}
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__INLINE uint32_t NVIC_GetActiveVector(void)
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{
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unsigned int vectactive = 0;
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//isr low 8bits gives the active vector
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vectactive = (CK801 ->ISR & 0xff);
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return vectactive;
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}
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/**
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* @brief Set the priority for an interrupt
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*
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* @param IRQn The number of the interrupt for set priority
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* @param priority The priority to set ,the number rang: [0-3]
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*
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* Set the priority for the specified interrupt. The interrupt
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* number must be positive to specify an external (device specific)
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* interrupt.
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*/
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__INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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{
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uint32_t tmp = ((IRQn & 0x03) << 3);
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uint8_t index = IRQn>>2;
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if(IRQn >= 0) {
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CK801->IPR[index] &= ~(0xff << tmp);
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CK801->IPR[index] |= priority << (tmp+6);
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}
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}
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/**
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* @brief Read the priority for an interrupt
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*
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* @param IRQn The number of the interrupt for get priority
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* @return The priority for the interrupt
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*
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* Read the priority for the specified interrupt. The interrupt
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* number must be positive to specify an external (device specific)
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* interrupt.
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*/
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__INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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{
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uint32_t tmp = ((IRQn & 0x03) << 3);
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uint8_t index = IRQn>>2;
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return (uint32_t)(CK801->IPR[index])>>(tmp + 6);
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}
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/*###################################################################*/
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/*############# Threshold Enable & Set Threshold ###############*/
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/*###################################################################*/
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/************************************************************
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* @brief enable NVIC threshold
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* @name: NVIC_EnableThreshold
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* @no param
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*
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*/
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__INLINE void NVIC_EnableThreshold(void)
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{
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CK801 ->IPTR |= 0x80000000;
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}
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/************************************************************
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* @brief disnable NVIC threshold
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* @name: NVIC_DisableThreshold
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* @no param
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*
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*/
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__INLINE void NVIC_DisableThreshold(void)
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{
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CK801 ->IPTR &= ~0x80000000;
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}
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/************************************************************
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* @brief set NVIC Priothreshold
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* @name: NVIC_SetPrioThreshold
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* @param prioshreshold the priority of threshold[0,3]
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*
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*/
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__INLINE void NVIC_SetPrioThreshold(uint8_t prioshreshold)
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{
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CK801 -> IPTR &= 0xffffff00;
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CK801 -> IPTR |= (prioshreshold << 6);
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}
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/************************************************************
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* @brief set NVIC Vectthreshold
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* @name: NVIC_SetVectThreshold
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* @param vectthreshold the vector of threshold[0,31]
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*
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*/
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__INLINE void NVIC_SetVectThreshold(uint8_t vectthreshold)
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{
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CK801 -> IPTR &= 0xffff00ff;
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CK801 -> IPTR |= ((vectthreshold + 32) << 8);
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}
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/*###################################################################*/
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/*################ Low Power Wakeup Enable ###################*/
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/*###################################################################*/
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/*************************************************************
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* @name: NVIC_PowerWakeUp_Enable
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* @brief: enable the bit for Power wake up
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* @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn
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*/
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__INLINE void NVIC_PowerWakeUp_Enable(IRQn_Type irqn)
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{
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CK801->IWER |= (1 << irqn);
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}
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/*************************************************************
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* @name: NVIC_PowerWakeUp_Disable
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* @func: disable the bit for Power wake up
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* @param: irqn the irqnumber,eg:CK802_CORETIM_IRQn
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*/
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__INLINE void NVIC_PowerWakeUp_Disable(IRQn_Type irqn)
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{
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CK801->IWDR |= (1 << irqn);
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}
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/*************************************************************
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* @name: NVIC_PowerWakeUp_EnableAll
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* @func: enable all bits for Power wake up
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* @param: none
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*/
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__INLINE void NVIC_PowerWakeUp_EnableAll(void)
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{
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CK801->IWER = 0xffffffff;
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}
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/*************************************************************
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* @name: NVIC_PowerWakeUp_EnableAll
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* @func: disable all bits for Power wake up
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* @param: none
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*/
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__INLINE void NVIC_PowerWakeUp_DisableAll(void)
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{
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CK801->IWDR = 0xffffffff;
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}
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/
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