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feat:修改设备类型

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feat:修改为红外转发设备，将中弘网关协议转换为主机红外协议
This commit is contained in:
yeyangwen
2026-02-09 17:32:59 +08:00
parent 2285326a47
commit 5a726f7378
1421 changed files with 47158 additions and 21011 deletions
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Source/include/apt32f102.h Normal file
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/*
******************************************************************************
* @file apt32f102_initial.c
* @author APT AE Team
* @version V1.08
* @date 2018/11/01
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_H
#define _apt32f102_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102_types_local.h"
#include "apt32f102_ck801.h"
/**
@brief CK801 bits Structure
*/
typedef struct {
volatile unsigned int ReservedA[4]; //0xE000E000
volatile unsigned int CORET_CSR; //0xE000E010
volatile unsigned int CORET_RVR; //0xE000E014
volatile unsigned int CORET_CVR; //0xE000E018
volatile unsigned int CORET_CALIB; //0xE000E01C
volatile unsigned int ReservedB[56]; //0xE000E020
volatile unsigned int ISER; //0xE000E100
volatile unsigned int ReservedC[15]; //
volatile unsigned int IWER; //0xE000E140
volatile unsigned int ReservedD[15]; //
volatile unsigned int ICER; //0xE000E180
volatile unsigned int ReservedE[15]; //
volatile unsigned int IWDR; //0xE000E1C0
volatile unsigned int ReservedF[15]; //
volatile unsigned int ISPR; //0xE000E200
volatile unsigned int ReservedG[31]; //
volatile unsigned int ICPR; //0xE000E280
volatile unsigned int ReservedH[31]; //
volatile unsigned int IABR; //0xE000E300
volatile unsigned int ReservedI[63]; //
volatile unsigned int IPR[8]; //0xE000E400 ~ 0xE000E41C
volatile unsigned int ReservedJ[504]; //
volatile unsigned int ISR; //0xE000EC00
volatile unsigned int IPTR; //0xE000EC04
} CSP_CK801_T;
/**
@brief IFC bits Structure
*/
typedef volatile struct {
volatile unsigned int IDR ;
volatile unsigned int CEDR ;
volatile unsigned int SRR ;
volatile unsigned int CMR ;
volatile unsigned int CR ;
volatile unsigned int MR ;
volatile unsigned int FM_ADDR ;
volatile unsigned int Reserved ;
volatile unsigned int KR ;
volatile unsigned int IMCR ;
volatile unsigned int RISR ;
volatile unsigned int MISR ;
volatile unsigned int ICR ;
} CSP_IFC_T ;
/**
@brief SYSCON bits Structure
*/
typedef volatile struct { /*!< SYSCON Structure */
volatile unsigned int IDCCR; /*!< 0x000: Identification & System Controller Clock Control Register */
volatile unsigned int GCER; /*!< 0x004: System Controller General Control Enable Register */
volatile unsigned int GCDR; /*!< 0x008: System Controller General Control Disable Register */
volatile unsigned int GCSR; /*!< 0x00C: System Controller General Control Status Register */
volatile unsigned int CKST; /*!< 0x010*/
volatile unsigned int RAMCHK; /*!< 0x014*/
volatile unsigned int EFLCHK; /*!< 0x018*/
volatile unsigned int SCLKCR; /*!< 0x01C: System Controller System Clock Selection & Division Register */
volatile unsigned int PCLKCR; /*!< 0x020: System Controller Peripheral Clock Selection & Division Register */
volatile unsigned int _RSVD0; /*!< 0x024*/
volatile unsigned int PCER0; /*!< 0x028: System Controller Peripheral Clock Enable Register */
volatile unsigned int PCDR0; /*!< 0x02C: System Controller Peripheral Clock Disable Register */
volatile unsigned int PCSR0; /*!< 0x030: System Controller Peripheral Clock Status Register */
volatile unsigned int PCER1; /*!< 0x034: System Controller Peripheral Clock Enable Register */
volatile unsigned int PCDR1; /*!< 0x038: System Controller Peripheral Clock Disable Register */
volatile unsigned int PCSR1; /*!< 0x03C: System Controller Peripheral Clock Status Register */
volatile unsigned int OSTR; /*!< 0x040: System Controller External OSC Stable Time Control Register */
volatile unsigned int _RSVD1; /*!< 0x044: System Controller PLL Stable Time Control Register */
volatile unsigned int _RSVD2; /*!< 0x048: System Controller PLL PMS Value Control Register */
volatile unsigned int LVDCR; /*!< 0x04C: System Controller LVD Control Register */
volatile unsigned int CLCR; /*!< 0x050: System Controller IMOSC Fine Adjustment Register*/
volatile unsigned int PWRCR; /*!< 0x054: System Controller Power Control Register */
volatile unsigned int PWRKEY; /*!< 0x058: System Controller Power Control Register */
volatile unsigned int _RSVD3; /*!< 0x05C: */
volatile unsigned int _RSVD4; /*!< 0x060: */
volatile unsigned int OPT1; /*!< 0x064: System Controller OSC Trim Control Register */
volatile unsigned int OPT0; /*!< 0x068: System Controller Protection Control Register */
volatile unsigned int WKCR; /*!< 0x06C: System Controller Clock Quality Check Control Register */
volatile unsigned int _RSVD5; /*!< 0x070: System Controller Clock Quality Check Control Register */
volatile unsigned int IMER; /*!< 0x074: System Controller Interrupt Enable Register */
volatile unsigned int IMDR; /*!< 0x078: System Controller Interrupt Disable Register */
volatile unsigned int IMCR; /*!< 0x07C: System Controller Interrupt Mask Register */
volatile unsigned int IAR; /*!< 0x080: System Controller Interrupt Active Register */
volatile unsigned int ICR; /*!< 0x084: System Controller Clear Status Register */
volatile unsigned int RISR; /*!< 0x088: System Controller Raw Interrupt Status Register */
volatile unsigned int MISR; /*!< 0x08C: System Controller Raw Interrupt Status Register */
volatile unsigned int RSR; /*!< 0x090: System Controller Raw Interrupt Status Register */
volatile unsigned int EXIRT; /*!< 0x094: System Controller Reset Status Register */
volatile unsigned int EXIFT; /*!< 0x098: System Controller External Interrupt Mode 1 (Positive Edge) Register */
volatile unsigned int EXIER; /*!< 0x09C: System Controller External Interrupt Mode 2 (Negative Edge) Register */
volatile unsigned int EXIDR; /*!< 0x0A0: System Controller External Interrupt Enable Register */
volatile unsigned int EXIMR; /*!< 0x0A4: System Controller External Interrupt Disable Register */
volatile unsigned int EXIAR; /*!< 0x0A8: System Controller External Interrupt Mask Register */
volatile unsigned int EXICR; /*!< 0x0AC: System Controller External Interrupt Active Register */
volatile unsigned int EXIRS; /*!< 0x0B0: System Controller External Interrupt Clear Status Register */
volatile unsigned int IWDCR; /*!< 0x0B4: System Controller Independent Watchdog Control Register */
volatile unsigned int IWDCNT; /*!< 0x0B8: SystCem Controller Independent Watchdog Counter Value Register */
volatile unsigned int IWDEDR; /*!< 0x0BC: System Controller Independent Watchdog Enable/disable Register*/
volatile unsigned int IOMAP0; /*!< 0x0C0: Customer Information Content mirror of 1st byte*/
volatile unsigned int IOMAP1; /*!< 0x0C4: Customer Information Content mirror of 1st byte*/
volatile unsigned int CINF0; /*!< 0x0C8: Customer Information Content mirror of 1st byte*/
volatile unsigned int CINF1; /*!< 0x0CC: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF0; /*!< 0x0D0: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF1; /*!< 0x0D4: Customer Information Content mirror of 1st byte*/
volatile unsigned int FINF2; /*!< 0x0D8: Customer Information Content mirror of 1st byte*/
volatile unsigned int _RSVD6; /*!< 0x0DC: Customer Information Content mirror of 1st byte*/
volatile unsigned int ERRINF; /*!< 0x0E0:*/
volatile unsigned int UID0 ; /*!< 0x0E4: Customer Information Content mirror of 1st byte*/
volatile unsigned int UID1 ; /*!< 0x0E8: Customer Information Content mirror of 1st byte*/
volatile unsigned int UID2 ; /*!< 0x0EC: Customer Information Content mirror of 1st byte*/
volatile unsigned int PWROPT; /*!< 0x0F0: Power recovery timmming control */
volatile unsigned int EVTRG; /*!< 0x0F4: Trigger gen */
volatile unsigned int EVPS; /*!< 0x0F8: Trigger prs */
volatile unsigned int EVSWF; /*!< 0x0FC: Trigger software force */
volatile unsigned int UREG0; /*!< 0x100: User defined reg0 */
volatile unsigned int UREG1; /*!< 0x104: User defined reg1 */
volatile unsigned int UREG2; /*!< 0x108: User defined reg0 */
volatile unsigned int UREG3; /*!< 0x10C: User defined reg1 */
} CSP_SYSCON_T;
/**
@brief ETCB bits Structure
*/
typedef volatile struct
{
volatile unsigned int EN; /* ETCB Enable */
volatile unsigned int SWTRG; /* ETCB Software Trigger Generator */
volatile unsigned int CH0CON0; /* ETCB Channel 0 Control Register 0 */
volatile unsigned int CH0CON1; /* ETCB Channel 0 Control Register 1 */
volatile unsigned int CH1CON0; /* ETCB Channel 1 Control Register 0 */
volatile unsigned int CH1CON1; /* ETCB Channel 1 Control Register 1 */
volatile unsigned int CH2CON0; /* ETCB Channel 2 Control Register 0 */
volatile unsigned int CH2CON1; /* ETCB Channel 2 Control Register 1 */
volatile unsigned int _RSVD0;
volatile unsigned int _RSVD1;
volatile unsigned int _RSVD2;
volatile unsigned int _RSVD3;
volatile unsigned int CH3CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH4CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH5CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH6CON; /* ETCB Channel 3 Control Register */
volatile unsigned int CH7CON; /* ETCB Channel 3 Control Register */
} CSP_ETCB_T, *CSP_ETCB_PTR;
/**
@brief TKEY bits Structure
*/
typedef volatile struct
{
volatile unsigned int TCH_CCR; /* Control Register */
volatile unsigned int TCH_CON0; /* Control Register */
volatile unsigned int TCH_CON1; /* Control Register */
volatile unsigned int TCH_SCCR; /* Hardmacro control */
volatile unsigned int TCH_SENPRD; /* Sensing target value */
volatile unsigned int TCH_VALBUF; /* Reference value capture value*/
volatile unsigned int TCH_SENCNT; /* Sensing counter value*/
volatile unsigned int TCH_TCHCNT; /* Reference counter value*/
volatile unsigned int TCH_THR; /* Match Status */
volatile unsigned int Reserved0;
volatile unsigned int TCH_RISR; /* Interrupt Enable */
volatile unsigned int TCH_IER; /* Interrupt Clear */
volatile unsigned int TCH_ICR; /* Sensing target value */
volatile unsigned int TCH_RWSR; /* Reference value capture value*/
volatile unsigned int TCH_OVW_THR; /* Sensing counter value*/
volatile unsigned int TCH_OVF; /* Reference counter value*/
volatile unsigned int TCH_OVT; /* Match Status */
volatile unsigned int TCH_SYNCR; /* Interrupt Enable */
volatile unsigned int TCH_EVTRG; /* Interrupt Clear */
volatile unsigned int TCH_EVPS; /* Sensing target value */
volatile unsigned int TCH_EVSWF; /* Reference value capture value*/
} CSP_TKEY_T, *CSP_TKEY_PTR;
/**
@brief TKEY advance bits Structure
*/
typedef volatile struct
{
volatile unsigned int TCH_CHVAL[18]; /* Reference value capture value */
volatile unsigned int TCH_SEQCON[18]; /* SEQ Hardmacro control */
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;
/**
@brief ADC0 bits Structure
*/
typedef volatile struct
{
volatile unsigned int ECR; /**< Clock Enable Register */
volatile unsigned int DCR; /**< Clock Disable Register */
volatile unsigned int PMSR; /**< Power Management Status Register */
volatile unsigned int Reserved0;
volatile unsigned int CR; /**< Control Register */
volatile unsigned int MR; /**< Mode Register */
volatile unsigned int SHR;
volatile unsigned int CSR; /**< Clear Status Register */
volatile unsigned int SR; /**< Status Register */
volatile unsigned int IER; /**< Interrupt Enable Register */
volatile unsigned int IDR; /**< Interrupt Disable Register */
volatile unsigned int IMR; /**< Interrupt Mask Register */
volatile unsigned int SEQ[16]; /**< Conversion Mode Register 0~11 */
volatile unsigned int PRI; /**< Conversion Priority Register */
volatile unsigned int TDL0; /**< Trigger Delay control Register */
volatile unsigned int TDL1; /**< Trigger Delay control Register */
volatile unsigned int SYNCR; /**< Sync Control Register */
volatile unsigned int Reserved1; /**< Trigger Filter Control Register */
volatile unsigned int Reserved2; /**< Trigger Filter Window Register */
volatile unsigned int EVTRG; /**< Event Trigger Control Register */
volatile unsigned int EVPS; /**< Event Prescale Register */
volatile unsigned int EVSWF; /**< Event Softtrig Register */
volatile unsigned int ReservedD[27];
volatile unsigned int DR[16]; /**< Convert Data Register */
volatile unsigned int CMP0; /**< Comparison Data Register */
volatile unsigned int CMP1; /**< Comparison Data Register */
volatile unsigned int DRMASK;
} CSP_ADC12_T, *CSP_ADC12_PTR;
/**
@brief GPIOX bits Structure
*/
typedef volatile struct
{
volatile unsigned int CONLR; /**< Control Low Register */
volatile unsigned int CONHR; /**< Control High Register */
volatile unsigned int WODR; /**< Write Output Data Register */
volatile unsigned int SODR; /**< Set Output Data (bit-wise) Register */
volatile unsigned int CODR; /**< Clear Output Data (bit-wise) Register*/
volatile unsigned int ODSR; /**< Output Data Status Register */
volatile unsigned int PSDR; /**< Pin Data Status Register */
volatile unsigned int FLTEN;
volatile unsigned int PUDR; /**< IO Pullup_Pulldown Register */
volatile unsigned int DSCR; /**< Output Driving Strength Register */
volatile unsigned int OMCR; /**< Slew-rate, Open-Drain Control */
volatile unsigned int IECR; /**< EXI enable control */
volatile unsigned int IEER;
volatile unsigned int IEDR;
} CSP_GPIO_T, *CSP_GPIO_PTR;
typedef volatile struct
{
volatile unsigned int IGRPL; /**< EXI group control */
volatile unsigned int IGRPH; /**< EXI group control */
volatile unsigned int IGREX;
volatile unsigned int IO_CLKEN;
} CSP_IGRP_T, *CSP_IGRP_PTR;
/**
@brief UART0~UART1 bits Structure
*/
typedef volatile struct
{
volatile unsigned int DATA; /**< Write and Read Data Register */
volatile unsigned int SR; /**< Status Register */
volatile unsigned int CTRL; /**< Control Register */
volatile unsigned int ISR; /**< Interrupt Status Register */
volatile unsigned int BRDIV; /**< Baud Rate Generator Register */
volatile unsigned int ReservedA[20];
} CSP_UART_T, *CSP_UART_PTR;
/**
@brief SPI0 bits Structure
*/
typedef struct
{
volatile unsigned int CR0; /**< Control Register 0 */
volatile unsigned int CR1; /**< Control Register 1 */
volatile unsigned int DR; /**< Receive FIFO(read) and transmit FIFO data register(write) */
volatile unsigned int SR; /**< Status register */
volatile unsigned int CPSR; /**< Clock prescale register */
volatile unsigned int IMSCR; /**< Interrupt mask set and clear register */
volatile unsigned int RISR; /**< Raw interrupt status register */
volatile unsigned int MISR; /**< Masked interrupt status register */
volatile unsigned int ICR; /**< Interrupt clear register */
} CSP_SSP_T, *CSP_SSP_PTR;
/**
@brief SIO0 bits Structure
*/
typedef struct
{
volatile unsigned int CR;
volatile unsigned int TXCR0;
volatile unsigned int TXCR1;
volatile unsigned int TXBUF;
volatile unsigned int RXCR0;
volatile unsigned int RXCR1;
volatile unsigned int RXCR2;
volatile unsigned int RXBUF;
volatile unsigned int RISR;
volatile unsigned int MISR;
volatile unsigned int IMCR;
volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;
/**
@brief I2C0 bits Structure
*/
typedef volatile struct
{
unsigned int CR; /* I2C Control */
unsigned int TADDR; /* I2C Target Address */
unsigned int SADDR; /* I2C Slave Address */
unsigned int ReservedD;
unsigned int DATA_CMD; /* I2C Rx/Tx Data Buffer and Command */
unsigned int SS_SCLH; /* I2C Standard Speed SCL High Count */
unsigned int SS_SCLL; /* I2C Standard Speed SCL Low Count */
unsigned int FS_SCLH; /* I2C Fast mode and Fast Plus SCL High Count*/
unsigned int FS_SCLL; /* I2C Fast mode and Fast Plus SCL Low Count*/
unsigned int ReservedA; /* I2C High Speed SCL High Count */
unsigned int ReservedC; /* I2C High Speed SCL Low Count */
unsigned int RX_FLSEL; /* I2C Receive FIFO Threshold */
unsigned int TX_FLSEL; /* I2C Transmit FIFO Threshold */
unsigned int RX_FL; /* I2C Receive FIFO Level */
unsigned int TX_FL; /* I2C Transmit FIFO Level */
unsigned int ENABLE; /* I2C Enable */
unsigned int STATUS; /* I2C Status */
unsigned int ReservedB; /* I2C Enable Status */
unsigned int SDA_TSETUP; /* I2C SDA Setup Time */
unsigned int SDA_THOLD; /* I2C SDA hold time length */
unsigned int SPKLEN; /* I2C SS and FS Spike Suppression Limit */
//unsigned int HS_SPKLEN; /* I2C HS Spike Suppression Limit */
unsigned int ReservedE;
unsigned int MISR; /* I2C Masked Interrupt Status */
unsigned int IMSCR; /* I2C Interrupt Enable */
unsigned int RISR; /* I2C Raw Interrupt Status */
unsigned int ICR; /* I2C Interrupt Clear */
unsigned int ReservedF;
unsigned int SCL_TOUT; /* I2C SCL Stuck at Low Timeout */
unsigned int SDA_TOUT; /* I2C SDA Stuck at Low Timeout */
unsigned int TX_ABRT; /* I2C Transmit Abort Status */
unsigned int GCALL; /* I2C ACK General Call */
unsigned int NACK; /* I2C Generate SLV_DATA_NACK */
} CSP_I2C_T, *CSP_I2C_PTR;
/**
@brief CA0 bits Structure
*/
typedef struct
{
volatile unsigned int CADATAH; /**< DATA High Register */
volatile unsigned int CADATAL; /**< DATA Low Register */
volatile unsigned int CACON; /**< Control Register */
volatile unsigned int INTMASK; /**< Interrupt Mask CR */
} CSP_CA_T, *CSP_CA_PTR;
/**
@brief GPTX bits Structure
*/
typedef struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int GLDCR; //0x0014 Global load control reg
volatile unsigned int GLDCFG; //0x0018 Global load config
volatile unsigned int GLDCR2; //0x001C Global load control reg2
volatile unsigned int Reserved0; //0x0020
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int Reserved1; //0x0028
volatile unsigned int CMPA; //0x002C Compare Value A
volatile unsigned int CMPB; //0x0030 Compare Value B
volatile unsigned int Reserved2; //0x0034
volatile unsigned int Reserved3; //0x0038
volatile unsigned int CMPLDR; //0x003C Cmp reg load control
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int AQLDR; //0x0044 AQ reg load control
volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A
volatile unsigned int AQCRB; //0x004C Action qualify of ch-B
volatile unsigned int Reserved4; //0x0050
volatile unsigned int Reserved5; //0x0054
volatile unsigned int Reserved6; //0x0058
volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing
volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing
volatile unsigned int Reserved7; //0x0064
volatile unsigned int Reserved8; //0x0068
volatile unsigned int Reserved9; //0x006c
volatile unsigned int Reserved10; //0x0070
volatile unsigned int Reserved11; //0x0074
volatile unsigned int Reserved12; //0x0078
volatile unsigned int Reserved13; //0x007c
volatile unsigned int Reserved14; //0x0080
volatile unsigned int Reserved15; //0x0084
volatile unsigned int Reserved16; //0x0088
volatile unsigned int Reserved17; //0x008c
volatile unsigned int Reserved18; //0x0090
volatile unsigned int Reserved19; //0x0094
volatile unsigned int Reserved20; //0x0098
volatile unsigned int Reserved21; //0x009c
volatile unsigned int Reserved22; //0x00a0
volatile unsigned int Reserved23; //0x00a4
volatile unsigned int Reserved24; //0x00a8
volatile unsigned int Reserved25; //0x00ac
volatile unsigned int Reserved26; //0x00b0
volatile unsigned int Reserved27; //0x00b4
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVCNTINIT; //0x00C8
volatile unsigned int EVSWF; //0x00CC Event software forcing
volatile unsigned int RISR; //0x00D0 Interrupt RISR
volatile unsigned int MISR; //0x00D4 Interrupt MISR
volatile unsigned int IMCR; //0x00D8 Interrupt IMCR
volatile unsigned int ICR; //0x00DC Interrupt clear
volatile unsigned int REGLINK; //0x00E0 Register link
}CSP_GPT_T,*CSP_GPT_PTR;
/**
@brief EPT0 bits Structure
*/
typedef struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int GLDCR; //0x0014 Global load control reg
volatile unsigned int GLDCFG; //0x0018 Global load config
volatile unsigned int GLDCR2; //0x001C Global load control reg2
volatile unsigned int HRCFG; //0x0020
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int PHSR; //0x0028 Phase control reg
volatile unsigned int CMPA; //0x002C Compare Value A
volatile unsigned int CMPB; //0x0030 Compare Value B
volatile unsigned int CMPC; //0x0034 Compare Value C
volatile unsigned int CMPD; //0x0038 Compare Value D
volatile unsigned int CMPLDR; //0x003C Cmp reg load control
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int AQLDR; //0x0044 AQ reg load control
volatile unsigned int AQCRA; //0x0048 Action qualify of ch-A
volatile unsigned int AQCRB; //0x004C Action qualify of ch-B
volatile unsigned int AQCRC; //0x0050 Action qualify of ch-C
volatile unsigned int AQCRD; //0x0054 Action qualify of ch-D
volatile unsigned int AQTSCR; //0x0058 T event selection
volatile unsigned int AQOSF; //0x005C AQ output one-shot software forcing
volatile unsigned int AQCSF; //0x0060 AQ output conti-software forcing
volatile unsigned int DBLDR; //0x0064 Deadband control reg load control
volatile unsigned int DBCR; //0x0068 Deadband control reg
volatile unsigned int DPSCR; //0x006C Deadband clock prescaler
volatile unsigned int DBDTR; //0x0070 Deadband rising delay control
volatile unsigned int DBDTF; //0x0074 Deadband falling delay control
volatile unsigned int CPCR; //0x0078 Chop control
volatile unsigned int EMSRC; //0x007C EM source setting
volatile unsigned int EMSRC2; //0x0080 EM source setting
volatile unsigned int EMPOL; //0x0084 EM polarity setting
volatile unsigned int EMECR; //0x0088 EM enable control
volatile unsigned int EMOSR; //0x008C EM trip out status setting
volatile unsigned int Reserved; //0x0090 Reserved
volatile unsigned int EMSLSR; //0x0094 Softlock status
volatile unsigned int EMSLCLR; //0x0098 Softlock clear
volatile unsigned int EMHLSR; //0x009C Hardlock status
volatile unsigned int EMHLCLR; //0x00A0 Hardlock clear
volatile unsigned int EMFRCR; //0x00A4 Software forcing EM
volatile unsigned int EMRISR; //0x00A8 EM RISR
volatile unsigned int EMMISR; //0x00AC EM MISR
volatile unsigned int EMIMCR; //0x00B0 EM masking enable
volatile unsigned int EMICR; //0x00B4 EM pending clear
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVCNTINIT; //0x00C8
volatile unsigned int EVSWF; //0x00CC Event software forcing
volatile unsigned int RISR; //0x00D0 Interrupt RISR
volatile unsigned int MISR; //0x00D4 Interrupt MISR
volatile unsigned int IMCR; //0x00D8 Interrupt IMCR
volatile unsigned int ICR; //0x00DC Interrupt clear
volatile unsigned int REGLINK; //0x00E0 Register link
volatile unsigned int REGLINK2; //0x00E4 Register link2
volatile unsigned int REGPROT; //0x00E8 Register protection
} CSP_EPT_T, *CSP_EPT_PTR;
/**
@brief LPT bits Structure
*/
typedef volatile struct
{
volatile unsigned int CEDR; //0x0000 Clock control & ID
volatile unsigned int RSSR; //0x0004 Start & Stop Ctrl
volatile unsigned int PSCR; //0x0008 Clock prescaler
volatile unsigned int CR; //0x000C Control register
volatile unsigned int SYNCR; //0x0010 Synchronization control reg
volatile unsigned int PRDR; //0x0024 Period reg
volatile unsigned int CMP; //0x002C Compare Value A
volatile unsigned int CNT; //0x0040 Counter reg
volatile unsigned int TRGFTCR; //0x00B8 Trigger Filter control reg
volatile unsigned int TRGFTWR; //0x00BC Trigger filter window
volatile unsigned int EVTRG; //0x00C0 Event trigger setting
volatile unsigned int EVPS; //0x00C4 Event presaler
volatile unsigned int EVSWF; //0x00C8 Event software forcing
volatile unsigned int RISR; //0x00CC Interrupt RISR
volatile unsigned int MISR; //0x00D0 Interrupt MISR
volatile unsigned int IMCR; //0x00D4 Interrupt IMCR
volatile unsigned int ICR; //0x00D8 Interrupt clear
} CSP_LPT_T, *CSP_LPT_PTR;
/**
@brief BT0 bits Structure
*/
typedef struct
{
volatile unsigned int RSSR; //0x0000 Reset/Start Control
volatile unsigned int CR; //0x0004 General Control
volatile unsigned int PSCR; //0x0008 Prescaler
volatile unsigned int PRDR; //0x000C Period
volatile unsigned int CMP; //0X0010
volatile unsigned int CNT; //0x0014 Counter
volatile unsigned int EVTRG; //0x0018 Event Trigger
volatile unsigned int EVPS; //0x001C Event Prescaler
volatile unsigned int EVCNTINTI; //0x0020 Event Counter
volatile unsigned int EVSWF; //0x0024 Software force Event Trigger
volatile unsigned int RISR; //0x0028
volatile unsigned int IMCR; //0x002C
volatile unsigned int MISR; //0x0030
volatile unsigned int ICR; //0x0034
} CSP_BT_T, *CSP_BT_PTR;
/**
@brief CRC bits Structure
*/
typedef struct
{
volatile unsigned int IDR; /**< ID Register */
volatile unsigned int CEDR; /**< Clock Enable/Disable Register */
volatile unsigned int SRR; /**< Software Reset Register */
volatile unsigned int CR; /**< Control Register */
volatile unsigned int SEED; /**< Seed Value Register */
volatile unsigned int DATAIN; /**< Data in Value Register */
volatile unsigned int DATAOUT; /**< Data out Value Register */
// TBD... //
} CSP_CRC_T, *CSP_CRC_PTR;
/**
@brief RTC bits Structure
*/
typedef struct
{
volatile unsigned int TIMR; //0x0000 Time Control Register
volatile unsigned int DATR; //0x0004 Date Control Register
volatile unsigned int CR; //0x0008 Control Register
volatile unsigned int CCR; //0x000C Clock Control register
volatile unsigned int ALRAR; //0x0010 Alarm A
volatile unsigned int ALRBR; //0x0014 Alarm B
volatile unsigned int SSR; //0x0018 Sub second
volatile unsigned int CAL; //0x001C Calibration
volatile unsigned int RISR; //0x0020
volatile unsigned int IMCR; //0x0024
volatile unsigned int MISR; //0x0028
volatile unsigned int ICR; //0x002C
volatile unsigned int KEY; //0x0030
volatile unsigned int EVTRG; //0x0034
volatile unsigned int EVPS; //0x0038
volatile unsigned int EVSWF; //0x003C
} CSP_RTC_T, *CSP_RTC_PTR;
/**
@brief WWDT bits Structure
*/
typedef struct
{
volatile unsigned int CR;
volatile unsigned int CFGR;
volatile unsigned int RISR;
volatile unsigned int MISR;
volatile unsigned int IMCR;
volatile unsigned int ICR;
}CSP_WWDT_T,*CSP_WWDT_PTR;
/**
@brief HWD bits Structure
*/
typedef struct
{
volatile S32_T DIVIDENT;
volatile S32_T DIVISOR;
volatile S32_T QUOTIENT;
volatile S32_T REMAIN;
volatile unsigned int CR;
}CSP_HWD_T,*CSP_HWD_PTR;
#define FLASHBase 0x00000000
#define FLASHSize 0x00010000
#define FLASHLimit (FLASHBase + FLASHSize)
#define DFLASHBase 0x10000000
#define DFLASHSize 0x10001000
#define DFLASHLimit (FLASHBase + FLASHSize)
#ifdef REMAP
#define SRAMBase 0x00000000
#define SRAMSize 0x00000800
#define SRAMLimit (SRAMBase + SRAMSize)
#define MEMVectorBase 0x00000700
#define MEMVectorSize (0x50<<2)
#else
#define SRAMBase 0x20000000
#define SRAMSize 0x00001000
#define SRAMLimit (SRAMBase + SRAMSize)
#define MEMVectorBase 0x20000F00
#define MEMVectorSize (0x50<<2)
#endif
//--Peripheral Address Setting
#define APBPeriBase 0x40000000
//--Each Peripheral Address Setting
//#define APB_SFMBase (APBPeriBase + 0x10000)
#define APB_IFCBase (APBPeriBase + 0x10000)
#define APB_SYSCONBase (APBPeriBase + 0x11000)
#define APB_ETCBBase (APBPeriBase + 0x12000)
#define APB_TKEYBase (APBPeriBase + 0x20000)
#define APB_TKEYBUFBase (APBPeriBase + 0x21000)
#define APB_ADC0Base (APBPeriBase + 0x30000)
#define AHBGPIOBase 0x60000000
#define APB_GPIOA0Base (AHBGPIOBase + 0x0000) //A0
#define APB_GPIOB0Base (AHBGPIOBase + 0x2000) //B0
#define APB_IGRPBase (AHBGPIOBase + 0xF000)
#define APB_BT1Base (APBPeriBase + 0x52000)
#define APB_BT0Base (APBPeriBase + 0x51000)
#define APB_CNTABase (APBPeriBase + 0x50000)
#define APB_GPT0Base (APBPeriBase + 0x55000)
#define APB_EPT0Base (APBPeriBase + 0x59000)
#define APB_RTCBase (APBPeriBase + 0x60000)
#define APB_LPTBase (APBPeriBase + 0x61000)
#define APB_WWDTBase (APBPeriBase + 0x62000)
#define APB_UART0Base (APBPeriBase + 0x80000)
#define APB_UART1Base (APBPeriBase + 0x81000)
#define APB_UART2Base (APBPeriBase + 0x82000)
#define APB_SPI0Base (APBPeriBase + 0x90000)
#define APB_SIO0Base (APBPeriBase + 0xB0000)
#define APB_I2C0Base (APBPeriBase + 0xA0000)
#define AHB_CRCBase 0x50000000
#define APB_HWDBase 0x70000000
//--Interrupt Bit Position
#define CORET_INT (0x01ul<<0) //IRQ0
#define SYSCON_INT (0x01ul<<1) //IRQ1
#define IFC_INT (0x01ul<<2) //IRQ2
#define ADC_INT (0x01ul<<3) //IRQ3
#define EPT0_INT (0x01ul<<4) //IRQ4
//DUMMY //IRQ5
#define WWDT_INT (0x01ul<<6) //IRQ6
#define EXI0_INT (0x01ul<<7) //IRQ7
#define EXI1_INT (0x01ul<<8) //IRQ8
#define GPT0_INT (0x01ul<<9) //IRQ9
//DUMMY //IRQ10
//DUMMY //IRQ11
#define RTC_INT (0x01ul<<12) //IRQ12
#define UART0_INT (0x01ul<<13) //IRQ13
#define UART1_INT (0x01ul<<14) //IRQ14
#define UART2_INT (0x01ul<<15) //IRQ15
//DUMMY //IRQ16
#define I2C_INT (0x01ul<<17) //IRQ17
//DUMMY //IRQ18
#define SPI_INT (0x01ul<<19) //IRQ19
#define SIO_INT (0x01ul<<20) //IRQ20
#define EXI2_INT (0x01ul<<21) //IRQ21
#define EXI3_INT (0x01ul<<22) //IRQ22
#define EXI4_INT (0x01ul<<23) //IRQ23
#define CA_INT (0x01ul<<24) //IRQ24
#define TKEY_INT (0x01ul<<25) //IRQ25
#define LPT_INT (0x01ul<<26) //IRQ26
//DUMMY //IRQ27
#define BT0_INT (0x01ul<<28) //IRQ28
#define BT1_INT (0x01ul<<29) //IRQ29
//DUMMY //IRQ30
//DUMMY //IRQ31
extern CSP_CK801_T *CK801 ;
extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;
extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;
extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;
extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;
extern CSP_GPT_T *GPT0 ;
extern CSP_EPT_T *EPT0 ;
extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;
extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;
//ISR Define for generating special interrupt related ASM (CK802), with compile option -mistack
void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));
void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));
extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_adc.h
* @author APT AE Team
* @version V1.13
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_adc_H
#define _apt32f102_adc_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* ADC12 Registers reset value ************************
******************************************************************************/
#define ADC_ECR_RST (0x00000000ul) /**< ECR reset value */
#define ADC_DCR_RST (0x00000000ul) /**< DCR reset value */
#define ADC_PMSR_RST (0x00000000ul) /**< PMSR reset value */
#define ADC_CR_RST (0x80000000ul) /**< CR reset value */
#define ADC_MR_RST (0x00000000ul) /**< MR reset value */
#define ADC_CSR_RST (0x00000000ul) /**< CSR reset value */
#define ADC_SR_RST (0x00000000ul) /**< SR reset value */
#define ADC_IER_RST (0x00000000ul) /**< IER reset value */
#define ADC_IDR_RST (0x00000000ul) /**< IDR reset value */
#define ADC_IMR_RST (0x00000000ul) /**< IMR reset value */
#define ADC_SEQx_RST (0x00000000ul) /**< SEQx reset value */
#define ADC_DR_RST (0x00000000ul) /**< DR reset value */
#define ADC_CMP0_RST (0x00000000ul) /**< CMP0 reset value */
#define ADC_CMP1_RST (0x00000000ul) /**< CMP1 reset value */
/**
* @brief ADC12 Control register
*/
typedef enum
{
ADC12_SWRST = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Software Reset */
ADC12_ADCEN = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Enable */
ADC12_ADCDIS = ((CSP_REGISTER_T)(0x01ul << 2)), /**< ADC Disable */
ADC12_START = ((CSP_REGISTER_T)(0x01ul << 3)), /**< Start Conversion */
ADC12_STOP = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Stop Conversion */
ADC12_SWTRG = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Stop Conversion */
ADC12_AVGEN = ((CSP_REGISTER_T)(0x01ul << 12)), /**< Conversion data get average */
ADC12_AVGDIS = ((CSP_REGISTER_T)(0x00ul << 12)), /**< Conversion data get last one */
}ADC12_Control_TypeDef;
/**
* @brief ADC12 IMR register
*/
typedef enum
{
//CSR SR, IER, IDR, IMR Registers
ADC12_EOC = ((CSP_REGISTER_T)(0x01ul << 0)), /**< End Of Conversion */
ADC12_READY = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Ready to Start */
ADC12_OVR = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Over Run */
ADC12_CMP0H = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Higher than CMP1 */
ADC12_CMP0L = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Lower than CMP1 */
ADC12_CMP1H = ((CSP_REGISTER_T)(0x01ul << 6)), /**< Higher than CMP2 */
ADC12_CMP1L = ((CSP_REGISTER_T)(0x01ul << 7)), /**< Lower than CMP2 */
ADC12_SEQ_END0 = ((CSP_REGISTER_T)(0x01ul << 16)), /**< SEQ0 Convert end */
ADC12_SEQ_END1 = ((CSP_REGISTER_T)(0x01ul << 17)), /**< SEQ1 Convert end */
ADC12_SEQ_END2 = ((CSP_REGISTER_T)(0x01ul << 18)), /**< SEQ2 Convert end */
ADC12_SEQ_END3 = ((CSP_REGISTER_T)(0x01ul << 19)), /**< SEQ3 Convert end */
ADC12_SEQ_END4 = ((CSP_REGISTER_T)(0x01ul << 20)), /**< SEQ4 Convert end */
ADC12_SEQ_END5 = ((CSP_REGISTER_T)(0x01ul << 21)), /**< SEQ5 Convert end */
ADC12_SEQ_END6 = ((CSP_REGISTER_T)(0x01ul << 22)), /**< SEQ6 Convert end */
ADC12_SEQ_END7 = ((CSP_REGISTER_T)(0x01ul << 23)), /**< SEQ7 Convert end */
ADC12_SEQ_END8 = ((CSP_REGISTER_T)(0x01ul << 24)), /**< SEQ8 Convert end */
ADC12_SEQ_END9 = ((CSP_REGISTER_T)(0x01ul << 25)), /**< SEQ9 Convert end */
ADC12_SEQ_END10 = ((CSP_REGISTER_T)(0x01ul << 26)), /**< SEQ10 Convert end */
ADC12_SEQ_END11 = ((CSP_REGISTER_T)(0x01ul << 27)), /**< SEQ11 Convert end */
ADC12_SEQ_END12 = ((CSP_REGISTER_T)(0x01ul << 28)), /**< SEQ12 Convert end */
ADC12_SEQ_END13 = ((CSP_REGISTER_T)(0x01ul << 29)), /**< SEQ13 Convert end */
ADC12_SEQ_END14 = ((CSP_REGISTER_T)(0x01ul << 30)), /**< SEQ14 Convert end */
ADC12_SEQ_END15 = ((CSP_REGISTER_T)(0x01ul << 31)), /**< SEQ15 Convert end */
/* SR Register Only */
ADC12_ADCENS = ((CSP_REGISTER_T)(0x01ul << 8)), /**< ADC Enable Status */
ADC12_CTCVS = ((CSP_REGISTER_T)(0x01ul << 9)) /**< Continuous Conversion Status*/
}
ADC12_IMR_TypeDef;
/**
* @brief ADC12 CLK ENABLE AND DISABLE
*/
typedef enum
{
ADC_CLK_CR = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Clock */
ADC12_IPIDCODE_MASK = ((CSP_REGISTER_T)(0x3FFFFFFul << 4)), /**< ADC IPIDCODE mask */
ADC_DEBUG_MODE = ((CSP_REGISTER_T)(0x01ul << 31)) /**< Debug Mode Enable */
}
ADC12_CLK_TypeDef;
/**
* @brief ADC12 Bit slection
*/
typedef enum
{
ADC12_12BIT = 1, /**< 12bit mode */
ADC12_10BIT = 0, /**< 10bit mode */
ADC12_10BITor12BIT = ((CSP_REGISTER_T)(0x01ul<<31))
}ADC12_10bitor12bit_TypeDef;
/**
* @brief ADC12 Convertion mode
*/
typedef enum
{
One_shot_mode = 0,
Continuous_mode = 1,
CONTCV = (CSP_REGISTER_T)0x01<<31 //Continuous Conversion 0: One shot mode. 1: Continuous mode.
}ADC12_ConverMode_TypeDef;
/**
* @brief ADC12 NBRCMPx selection
*/
typedef enum
{
NBRCMP0_TypeDef = 0,
NBRCMP1_TypeDef = 1
}
ADC12_NBRCMPx_TypeDef;
/**
* @brief ADC12 NBRCMPx_HorL selection
*/
typedef enum
{
NBRCMPX_L_TypeDef = 0,
NBRCMPX_H_TypeDef = 1
}
ADC12_NBRCMPx_HorL_TypeDef;
/**
* @brief ADC12 SEQx register
*/
typedef enum
{
ADC12_ADCIN0 = (CSP_REGISTER_T)(0x0ul), /**< ADC Analog Input 0 */
ADC12_ADCIN1 = (CSP_REGISTER_T)(0x1ul), /**< ADC Analog Input 1 */
ADC12_ADCIN2 = (CSP_REGISTER_T)(0x2ul), /**< ADC Analog Input 2 */
ADC12_ADCIN3 = (CSP_REGISTER_T)(0x3ul), /**< ADC Analog Input 3 */
ADC12_ADCIN4 = (CSP_REGISTER_T)(0x4ul), /**< ADC Analog Input 4 */
ADC12_ADCIN5 = (CSP_REGISTER_T)(0x5ul), /**< ADC Analog Input 5 */
ADC12_ADCIN6 = (CSP_REGISTER_T)(0x6ul), /**< ADC Analog Input 6 */
ADC12_ADCIN7 = (CSP_REGISTER_T)(0x7ul), /**< ADC Analog Input 7 */
ADC12_ADCIN8 = (CSP_REGISTER_T)(0x8ul), /**< ADC Analog Input 8 */
ADC12_ADCIN9 = (CSP_REGISTER_T)(0x9ul), /**< ADC Analog Input 9 */
ADC12_ADCIN10 = (CSP_REGISTER_T)(0x0Aul), /**< ADC Analog Input 10 */
ADC12_ADCIN11 = (CSP_REGISTER_T)(0x0Bul), /**< ADC Analog Input 11 */
ADC12_ADCIN12 = (CSP_REGISTER_T)(0x0Cul), /**< ADC Analog Input 12 */
ADC12_ADCIN13 = (CSP_REGISTER_T)(0x0Dul), /**< ADC Analog Input 13 */
ADC12_ADCIN14 = (CSP_REGISTER_T)(0x0Eul), /**< ADC Analog Input 14 */
ADC12_ADCIN15 = (CSP_REGISTER_T)(0x0Ful), /**< ADC Analog Input 15 */
//ADC12_ADCIN16 = (CSP_REGISTER_T)(0x10ul), /**< ADC Analog Input 16 */
//ADC12_ADCIN17 = (CSP_REGISTER_T)(0x11ul), /**< ADC Analog Input 17 */
//ADC12_ADCIN18 = (CSP_REGISTER_T)(0x12ul), /**< ADC Analog Input 18 */
//ADC12_ADCIN19 = (CSP_REGISTER_T)(0x13ul), /**< ADC Analog Input 19 */
//ADC12_ADCIN20 = (CSP_REGISTER_T)(0x14ul), /**< ADC Analog Input 20 */
//ADC12_ADCIN21 = (CSP_REGISTER_T)(0x15ul), /**< ADC Analog Input 21 */
//ADC12_ADCIN22 = (CSP_REGISTER_T)(0x16ul), /**< ADC Analog Input 22 */
//ADC12_ADCIN23 = (CSP_REGISTER_T)(0x17ul), /**< ADC Analog Input 23 */
//ADC12_ADCIN24 = (CSP_REGISTER_T)(0x18ul), /**< ADC Analog Input 24 */
//ADC12_ADCIN25 = (CSP_REGISTER_T)(0x19ul), /**< ADC Analog Input 25 */
//ADC12_ADCIN26 = (CSP_REGISTER_T)(0x1Aul), /**< ADC Analog Input 26 */
//ADC12_ADCIN27 = (CSP_REGISTER_T)(0x1Bul) /**< ADC Analog Input 27 */
ADC12_INTVREF = (CSP_REGISTER_T)(0x1Cul),
ADC12_DIV4_VDD = (CSP_REGISTER_T)(0x1Dul),
ADC12_VSS = (CSP_REGISTER_T)(0x1Eul),
}
ADC12_InputSet_TypeDef;
/**
* @brief ADC12 Convertion repeat number
*/
typedef enum
{
ADC12_CV_RepeatNum1 = (CSP_REGISTER_T)(0x0ul<<8)|(0x0ul<<13), /**< ADC Convertion number 1 */
ADC12_CV_RepeatNum2 = (CSP_REGISTER_T)(0x1ul<<8)|(0x1ul<<13), /**< ADC Convertion number 2 */
ADC12_CV_RepeatNum4 = (CSP_REGISTER_T)(0x2ul<<8)|(0x2ul<<13), /**< ADC Convertion number 4 */
ADC12_CV_RepeatNum8 = (CSP_REGISTER_T)(0x3ul<<8)|(0x3ul<<13), /**< ADC Convertion number 8 */
ADC12_CV_RepeatNum16 = (CSP_REGISTER_T)(0x4ul<<8)|(0x4ul<<13), /**< ADC Convertion number 16 */
ADC12_CV_RepeatNum32 = (CSP_REGISTER_T)(0x5ul<<8)|(0x5ul<<13), /**< ADC Convertion number 32 */
ADC12_CV_RepeatNum64 = (CSP_REGISTER_T)(0x6ul<<8)|(0x6ul<<13), /**< ADC Convertion number 64 */
ADC12_CV_RepeatNum128 = (CSP_REGISTER_T)(0x7ul<<8)|(0x7ul<<13), /**< ADC Convertion number 128 */
ADC12_CV_RepeatNum256 = (CSP_REGISTER_T)(0x8ul<<8)|(0x8ul<<13), /**< ADC Convertion number 256 */
ADC12_CV_RepeatNum512 = (CSP_REGISTER_T)(0x9ul<<8)|(0x9ul<<13) /**< ADC Convertion number 512 */
}ADC12_CV_RepeatNum_TypeDef;
/**
* @brief ADC12 VREFP VREFN Selecte
*/
typedef enum
{
ADC12_VREFP_VDD_VREFN_VSS = 0,
ADC12_VREFP_EXIT_VREFN_VSS = 1,
ADC12_VREFP_FVR2048_VREFN_VSS = 2,
ADC12_VREFP_FVR4096_VREFN_VSS = 3,
//ADC12_VREFP_INTVREF0750_VREFN_VSS = 4,
ADC12_VREFP_INTVREF1000_VREFN_VSS = 5,
ADC12_VREFP_VDD_VREFN_EXIT = 6,
ADC12_VREFP_EXIT_VREFN_EXIT = 7,
ADC12_VREFP_FVR2048_VREFN_EXIT = 8,
ADC12_VREFP_FVR4096_VREFN_EXIT = 9,
//ADC12_VREFP_INTVREF0750_VREFN_EXIT = 10,
ADC12_VREFP_INTVREF1000_VREFN_EXIT = 11
}ADC12_VREFP_VREFN_Selected_TypeDef;
extern void ADC12_RESET_VALUE(void);
extern void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x );
extern void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState);
extern uint8_t ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit);
extern void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState);
extern void ADC12_Software_Reset(void);
extern void ADC12_CMD(FunctionalStatus NewState);
extern void ADC12_ready_wait(void);
extern void ADC12_EOC_wait(void);
extern void ADC12_SEQEND_wait(U8_T val);
extern U16_T ADC12_DATA_OUPUT(U16_T Data_index );
extern void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver );
extern void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X );
extern void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data );
extern void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx);
extern U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL);
extern void ADC_Int_Enable(void);
extern void ADC_Int_Disable(void);
extern void ADC12_CONFIG(void);
extern void adc12_SHR_SET(U8_T adc12_SHR);
#endif /**< apt32f102_adc_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_bt.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_bt_H
#define _apt32f102_bt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define BT_RESET_VALUE (0x00000000)
/**
* @brief bt pin numbner
*/
typedef enum
{
BT0_PA00 = 0, /*!< Pin 0 selected */
BT0_PA02 = 1, /*!< Pin 1 selected */
BT0_PA05 = 2, /*!< Pin 2 selected */
BT0_PB02 = 3, /*!< Pin 3 selected */
BT0_PB05 = 4, /*!< Pin 4 selected */
BT0_PA11 = 5, /*!< Pin 5 selected */
BT0_PA13 = 6, /*!< Pin 6 selected */
BT0_PA15 = 7, /*!< Pin 7 selected */
BT1_PA01 = 8, /*!< Pin 8 selected */
BT1_PA06 = 9, /*!< Pin 9 selected */
BT1_PA08 = 10, /*!< Pin 10 selected */
BT1_PA12 = 11, /*!< Pin 11 selected */
BT1_PA14 = 12, /*!< Pin 12 selected */
BT1_PB00 = 13, /*!< Pin 13 selected */
BT1_PB04 = 14, /*!< Pin 13 selected */
}BT_Pin_TypeDef;
/**
* @brief BT CLK EN register
*/
typedef enum
{
BTCLK_DIS = 0,
BTCLK_EN = 1,
}BT_CLK_TypeDef;
/**
* @brief BT START SHADOW register
*/
typedef enum
{
BT_SHADOW = (0<<3),
BT_IMMEDIATE= (1<<3),
}BT_SHDWSTP_TypeDef;
/**
* @brief BT OPM register
*/
typedef enum
{
BT_CONTINUOUS= (0<<4),
BT_ONCE= (1<<4),
}BT_OPM_TypeDef;
/**
* @brief BT EXTCKM register
*/
typedef enum
{
BT_PCLKDIV= (0<<5),
BT_EXTCKM= (1<<5),
}BT_EXTCKM_TypeDef;
/**
* @brief BT IDLEST register
*/
typedef enum
{
BT_IDLE_LOW= (0<<6),
BT_IDLE_HIGH= (1<<6),
}BT_IDLEST_TypeDef;
/**
* @brief BT STARTST register
*/
typedef enum
{
BT_START_LOW= (0<<7),
BT_START_HIGH= (1<<7),
}BT_STARTST_TypeDef;
/**
* @brief BT STARTST register
*/
typedef enum
{
BT_SYNC_DIS= (0<<8),
BT_SYNC_EN= (1<<8),
}BT_SYNCEN_TypeDef;
/**
* @brief BT OSTMDX register
*/
typedef enum
{
BT_OSTMDX_CONTINUOUS= (0<<10),
BT_OSTMDX_ONCE= (1<<10),
}BT_OSTMDX_TypeDef;
/**
* @brief BT AREARM register
*/
typedef enum
{
BT_AREARM_DIS= (0<<14),
BT_AREARM_EN= (1<<14),
}BT_AREARM_TypeDef;
/**
* @brief BT SYNCMD register
*/
typedef enum
{
BT_SYNCMD_DIS= (0<<15),
BT_SYNCMD_EN= (1<<15),
}BT_SYNCMD_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_CNTRLD_EN= (0<<16),
BT_CNTRLD_DIS= (1<<16),
}BT_CNTRLD_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_TRGSRC_DIS= (0<<0),
BT_TRGSRC_PEND= (1<<0),
BT_TRGSRC_CMP= (2<<0),
BT_TRGSRC_OVF= (3<<0),
}BT_TRGSRC_TypeDef;
/**
* @brief BT CNTRLD register
*/
typedef enum
{
BT_TRGOE_DIS= (0<<20),
BT_TRGOE_EN= (1<<20),
}BT_TRGOE_TypeDef;
/**
* @brief BT INT MASK SET/CLR Set
*/
typedef enum
{
BT_PEND = (0x01 << 0),
BT_CMP = (0x01 << 1),
BT_OVF = (0x01 << 2),
BT_EVTRG = (0x01 << 3),
}BT_IMSCR_TypeDef;
extern void BT_DeInit(CSP_BT_T *BTx);
extern void BT_IO_Init(BT_Pin_TypeDef BT_IONAME);
extern void BT_Start(CSP_BT_T *BTx);
extern void BT_Stop(CSP_BT_T *BTx);
extern void BT_Soft_Reset(CSP_BT_T *BTx);
extern void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM);
extern void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD,
BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD);
extern void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA);
extern void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA);
extern U16_T BT_PRDR_Read(CSP_BT_T *BTx);
extern U16_T BT_CMP_Read(CSP_BT_T *BTx);
extern U16_T BT_CNT_Read(CSP_BT_T *BTx);
extern void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE);
extern void BT_Soft_Tigger(CSP_BT_T *BTx);
extern void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X);
extern void BT0_INT_ENABLE(void);
extern void BT0_INT_DISABLE(void);
extern void BT1_INT_ENABLE(void);
extern void BT1_INT_DISABLE(void);
extern void BT_Stop_High(CSP_BT_T *BTx);
extern void BT_Stop_Low(CSP_BT_T *BTx);
#endif /**< apt32f102_bt_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ck801.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_ck801_H
#define _apt32f102_ck801_H
//----------------------------------------------------------------------------
// Interrupt Controller
//----------------------------------------------------------------------------
//#define CK801_BASEADDR ((unsigned int) 0xE000E000)
#define CK801_BASEADDR 0xE000E000
#define INTC_ISER CK801_BASEADDR+0x100 //INTC interrupt enable register
#define INTC_IWER CK801_BASEADDR+0x140 //INTC wake-up interrupt enable register
#define INTC_ICER CK801_BASEADDR+0x180 //INTC interrupt enable clear register
#define INTC_IWDR CK801_BASEADDR+0x1C0 //INTC wake-up interrupt enable clear register
#define INTC_ISPR CK801_BASEADDR+0x200 //INTC interrupt pending register
#define INTC_ICPR CK801_BASEADDR+0x280 //INTC interrupt pending clear register
#define INTC_IABR CK801_BASEADDR+0x300 //INTC interrupt acknowledge status register
#define INTC_IPR0 CK801_BASEADDR+0x400 //INTC interrupt priority register
#define INTC_IPR1 CK801_BASEADDR+0x404 //INTC interrupt priority register
#define INTC_IPR2 CK801_BASEADDR+0x408 //INTC interrupt priority register
#define INTC_IPR3 CK801_BASEADDR+0x40C //INTC interrupt priority register
#define INTC_IPR4 CK801_BASEADDR+0x410 //INTC interrupt priority register
#define INTC_IPR5 CK801_BASEADDR+0x414 //INTC interrupt priority register
#define INTC_IPR6 CK801_BASEADDR+0x418 //INTC interrupt priority register
#define INTC_IPR7 CK801_BASEADDR+0x41C //INTC interrupt priority register
#define INTC_ISR CK801_BASEADDR+0xC00 //INTC interrupt status register
#define INTC_IPTR CK801_BASEADDR+0xC04 //INTC interrupt pending threshold register
#define INTC_ISER_WRITE(val) *(volatile UINT32 *) (INTC_ISER ) = val
#define INTC_IWER_WRITE(val) *(volatile UINT32 *) (INTC_IWER ) = val
#define INTC_ICER_WRITE(val) *(volatile UINT32 *) (INTC_ICER ) = val
#define INTC_IWDR_WRITE(val) *(volatile UINT32 *) (INTC_IWDR ) = val
#define INTC_ISPR_WRITE(val) *(volatile UINT32 *) (INTC_ISPR ) = val
#define INTC_ICPR_WRITE(val) *(volatile UINT32 *) (INTC_ICPR ) = val
#define INTC_IABR_WRITE(val) *(volatile UINT32 *) (INTC_IABR ) = val
#define INTC_IPR0_WRITE(val) *(volatile UINT32 *) (INTC_IPR0 ) = val
#define INTC_IPR1_WRITE(val) *(volatile UINT32 *) (INTC_IPR1 ) = val
#define INTC_IPR2_WRITE(val) *(volatile UINT32 *) (INTC_IPR2 ) = val
#define INTC_IPR3_WRITE(val) *(volatile UINT32 *) (INTC_IPR3 ) = val
#define INTC_IPR4_WRITE(val) *(volatile UINT32 *) (INTC_IPR4 ) = val
#define INTC_IPR5_WRITE(val) *(volatile UINT32 *) (INTC_IPR5 ) = val
#define INTC_IPR6_WRITE(val) *(volatile UINT32 *) (INTC_IPR6 ) = val
#define INTC_IPR7_WRITE(val) *(volatile UINT32 *) (INTC_IPR7 ) = val
#define INTC_ISR_WRITE(val) *(volatile UINT32 *) (INTC_ISR ) = val
#define INTC_IPTR_WRITE(val) *(volatile UINT32 *) (INTC_IPTR ) = val
#define INTC_ISER_READ(intc) (intc->ISER )
#define INTC_IWER_READ(intc) (intc->IWER )
#define INTC_ICER_READ(intc) (intc->ICER )
#define INTC_IWDR_READ(intc) (intc->IWDR )
#define INTC_ISPR_READ(intc) (intc->ISPR )
#define INTC_ICPR_READ(intc) (intc->ICPR )
#define INTC_IABR_READ(intc) (intc->IABR )
#define INTC_IPR0_READ(intc) (intc->IPR0 )
#define INTC_IPR1_READ(intc) (intc->IPR1 )
#define INTC_IPR2_READ(intc) (intc->IPR2 )
#define INTC_IPR3_READ(intc) (intc->IPR3 )
#define INTC_IPR4_READ(intc) (intc->IPR4 )
#define INTC_IPR5_READ(intc) (intc->IPR5 )
#define INTC_IPR6_READ(intc) (intc->IPR6 )
#define INTC_IPR7_READ(intc) (intc->IPR7 )
#define INTC_ISR_READ(intc) (intc->ISR )
#define INTC_IPTR_READ(intc) (intc->IPTR )
typedef enum IRQn
{
ISR_Restart = -32,
ISR_Misaligned_Access = -31,
ISR_Access_Error = -30,
ISR_Divided_By_Zero = -29,
ISR_Illegal = -28,
ISR_Privlege_Violation = -27,
ISR_Trace_Exection = -26,
ISR_Breakpoint_Exception = -25,
ISR_Unrecoverable_Error = -24,
ISR_Idly4_Error = -23,
ISR_Auto_INT = -22,
ISR_Auto_FINT = -21,
ISR_Reserved_HAI = -20,
ISR_Reserved_FP = -19,
ISR_TLB_Ins_Empty = -18,
ISR_TLB_Data_Empty = -17,
INTC_CORETIM_IRQn = 0,
INTC_TIME1_IRQn = 1,
INTC_UART0_IRQn = 2,
INTC_GPIOA2_IRQn = 8,
} IRQn_Type;
void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);
void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef uint32_t
#define uint32_t unsigned int
#endif
#ifndef uint8_t
#define uint8_t unsigned char
#endif
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/******************************************************************************
* @file apt32f102_clkcalib.h
* @author APT AE Team
* @version V1.22
* @date 2021/11/22
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#include "apt32f102.h"
/**
* @brief CALIB OSC SELECTE SET
*/
typedef enum
{
CLK_HFOSC_48M = (0x0ul),
CLK_HFOSC_24M = (0x1ul),
CLK_HFOSC_12M = (0x2ul),
CLK_HFOSC_6M = (0x3ul),
CLK_IMOSC_5556K = (0x4ul),
CLK_IMOSC_4194K = (0x5ul),
CLK_IMOSC_2097K = (0x6ul),
CLK_IMOSC_131K = (0x7ul)
}CALIB_OSC_SELECTE_TypeDef;
extern U8_T std_clk_calib(CALIB_OSC_SELECTE_TypeDef OSC_CALIB_X);

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/*
******************************************************************************
* @file apt32f102_CORET.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_CORET_H
#define _apt32f102_CORET_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* syscon Registers Definition *************************
******************************************************************************/
#define CORET_CSR_RST ((CSP_REGISTER_T)0x00000004)
#define CORET_RVR_RST ((CSP_REGISTER_T)0x00000000)
#define CORET_CVR_RST ((CSP_REGISTER_T)0x00000000)
#define CORET_CALIB_RST ((CSP_REGISTER_T)0x00000000)
extern void CORET_DeInit(void);
extern void CORET_Int_Enable(void);
extern void CORET_Int_Disable(void);
extern void CORET_WakeUp_Enable(void);
extern void CORET_WakeUp_Disable(void);
extern void CORET_start(void);
extern void CORET_stop(void);
extern void CORET_CLKSOURCE_EX(void);
extern void CORET_CLKSOURCE_IN(void);
extern void CORET_TICKINT_Enable(void);
extern void CORET_TICKINT_Disable(void);
extern void CORET_reload(void);
#endif /**< apt32f102_coret_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_countera.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_countera_H
#define _apt32f102_countera_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define CA_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------countA value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief countA Period int
*/
typedef enum
{
Period_NA = 0, //Interrupt enable/disable for High/low period elapsed
Period_H = 1,
Period_L = 2,
Period_H_L = 3,
}CA_INT_TypeDef;
/**
* @brief countA DIV
*/
typedef enum
{
DIV1 = ((0 & 0x03ul)<<4) , //Counter A input clock frequency selection
DIV2 = ((1 & 0x03ul)<<4) ,
DIV4 = ((2 & 0x03ul)<<4) ,
DIV8 = ((3 & 0x03ul)<<4) ,
}CA_CLKDIV_TypeDef;
/**
* @brief countA mode
*/
typedef enum
{
ONESHOT_MODE = (0x00ul << 1), //Mode Selection:oneshotmode/repeat mode
REPEAT_MODE = (0x01ul << 1),
}CA_Mode_TypeDef;
/**
* @brief countA carrier setting
*/
typedef enum
{
CARRIER_OFF = (0x00ul << 25), //Carrier signal
CARRIER_ON = (0x01ul << 25),
}CA_CARRIER_TypeDef;
/**
* @brief Carrier Waveform Output Starting Polarity
*/
typedef enum
{
OSP_LOW = 0, //Carrier Waveform Output Starting Polarity
OSP_HIGH = 1,
}CA_OSP_TypeDef;
/**
* @brief Carrier register load
*/
typedef enum
{
HW_STROBE_0 = (0x01ul<<17), //Counter A data register Hardware/software load enable.
HW_STROBE_1 = (0x01ul<<18),
SW_STROBE = (0x01ul<<16),
}CA_STROBE_TypeDef;
/**
* @brief Carrier rem output signal
*/
typedef enum
{
ENVELOPE_0 = (0x00ul << 24), //REM output signal selection bit
ENVELOPE_1 = (0x01ul << 24),
}CA_ENVELOPE_TypeDef;
/**
* @brief Carrier PENDREM
*/
typedef enum
{
PENDREM_OFF = ((0 & 0x03ul)<<21),
PENDREM_1 = ((1 & 0x03ul)<<21),
PENDREM_2 = ((2 & 0x03ul)<<21),
}CA_PENDREM_TypeDef;
/**
* @brief Carrier ATCHREM
*/
typedef enum
{
MATCHREM_OFF = ((0 & 0x03ul)<<19),
MATCHREM_1 = ((1 & 0x03ul)<<19),
MATCHREM_2 = ((2 & 0x03ul)<<19),
}CA_MATCHREM_TypeDef;
/**
* @brief Carrier REMSTAT
*/
typedef enum
{
REMSTAT_0 = ((0 & 0x01ul)<<23),
REMSTAT_1 = ((1 & 0x01ul)<<23),
}CA_REMSTAT_TypeDef;
/**
* @brief counterA IO
*/
typedef enum
{
COUNTA_PB01 = 0,
COUNTA_PA05 = 1,
COUNTA_PA11 = 2,
}CA_COUNTAIO_TypeDef;
extern void COUNTA_Init(uint32_t Data_H,uint32_t Data_L,CA_INT_TypeDef INT_Mode,
CA_CLKDIV_TypeDef DIVx,CA_Mode_TypeDef Mode,CA_CARRIER_TypeDef Carrier,
CA_OSP_TypeDef OSP_Mode) ;
extern void COUNTA_Config(CA_STROBE_TypeDef STROBE,CA_PENDREM_TypeDef Pend_CON,
CA_MATCHREM_TypeDef Match_CON,CA_REMSTAT_TypeDef Stat_CON,CA_ENVELOPE_TypeDef ENVELOPE );
extern void COUNT_DeInit(void);
extern void COUNTA_Start(void);
extern void COUNTA_Stop(void);
extern void COUNTA_Int_Disable(void);
extern void COUNTA_Int_Enable(void);
extern void COUNTA_Wakeup_Disable(void);
extern void COUNTA_Wakeup_Enable(void);
extern void COUNTA_IO_Init(CA_COUNTAIO_TypeDef COUNTA_IO_G);
extern void COUNTA_Data_Update(uint32_t Data_H,uint32_t Data_L);
/*************************************************************/
#endif /**< apt32f102_countera_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_crc.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_crc_H
#define _apt32f102_crc_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define CRC_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------CRC value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief CRC COMPIN register
*/
typedef enum
{
XORIN_DIS = 0,
XORIN_EN = 1,
}CRC_COMPIN_TypeDef;
/**
* @brief CRC COMPOUT register
*/
typedef enum
{
XOROUT_DIS = (0<<1),
XOROUT_EN = (1<<1),
}CRC_COMPOUT_TypeDef;
/**
* @brief CRC ENDIANIN register
*/
typedef enum
{
REFIN_DIS = (0<<2),
REFIN_EN = (1<<2),
}CRC_ENDIANIN_TypeDef;
/**
* @brief CRC ENDIANOUT register
*/
typedef enum
{
REFOUT_DIS = (0<<3),
REFOUT_EN = (1<<3),
}CRC_ENDIANOUT_TypeDef;
/**
* @brief CRC poly register
*/
typedef enum
{
POLY_CCITT = (0<<4),
POLY_16 = (2<<4),
POLY_32 = (3<<4),
}CRC_POLY_TypeDef;
extern void CRC_CMD(FunctionalStatus NewState);
extern void CRC_Soft_Reset(void);
extern void CRC_Configure(CRC_COMPIN_TypeDef COMPINX,CRC_COMPOUT_TypeDef COMPOUTX,CRC_ENDIANIN_TypeDef ENDIANINX,
CRC_ENDIANOUT_TypeDef ENDIANOUT,CRC_POLY_TypeDef POLYX);
extern void CRC_Seed_Write(U32_T seed_data);
extern U32_T CRC_Seed_Read(void);
extern void CRC_Datain(U32_T data_in);
extern U32_T CRC_Result_Read(void);
extern U32_T Chip_CRC_CRC32(U32_T *data, U32_T words);
extern U32_T Chip_CRC_CRC16(U16_T *data, U32_T size);
extern U32_T Chip_CRC_CRC8(U8_T *data, U32_T size);
/*************************************************************/
#endif /**< apt32f102_crc_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ept.h
* @author APT AE Team
* @version V1.020
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_ept_H
#define _apt32f102_ept_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* ept Registers Definition *************************
******************************************************************************/
/**
* @brief EPT io Mode set
*/
typedef enum
{
EPT_IO_CHAX = 0,
EPT_IO_CHAY = 1,
EPT_IO_CHBX = 2,
EPT_IO_CHBY = 3,
EPT_IO_CHCX = 4,
EPT_IO_CHCY = 5,
EPT_IO_CHD = 6,
EPT_IO_EPI = 7
}EPT_IO_Mode_Type;
/**
* @brief EPT io NUM set
*/
typedef enum
{
IO_NUM_PA07 = 0X10,
IO_NUM_PA10 = 0X11,
IO_NUM_PA15 = 0X12,
IO_NUM_PB03 = 0X13,
IO_NUM_PB05 = 0X14,
IO_NUM_PA12 = 0X15,
IO_NUM_PB02 = 0X16,
IO_NUM_PA11 = 0X17,
IO_NUM_PA14 = 0X18,
IO_NUM_PB04 = 0X19,
IO_NUM_PA05 = 0X1A,
IO_NUM_PA08 = 0X1B,
IO_NUM_PA03 = 0X1C,
IO_NUM_PB00 = 0X1D,
IO_NUM_PA04 = 0X1E,
IO_NUM_PA09 = 0X1F,
IO_NUM_PA013 = 0X20
}EPT_IO_NUM_Type;
/**
* @brief EPT TCLK selected
*/
typedef enum
{
EPT_Selecte_PCLK = 0<<3,
EPT_Selecte_SYNCUSR3 = 1<<3
}EPT_TCLK_Selecte_Type;
/**
* @brief EPT TIN selected
*/
typedef enum
{
EPT_CGSRC_TIN_BT0OUT = 0,
EPT_CGSRC_TIN_BT1OUT = 1,
EPT_CGSRC_CHAX = 2, //设置CHAX CHBX后对应管脚将不能输出PWM
EPT_CGSRC_CHBX = 3,
EPT_CGSRC_DIS = 4
}EPT_CGSRC_TIN_Selecte_Type;
typedef enum
{
EPT_BURST_ENABLE = 1<<9,
EPT_BURST_DIABLE = 0<<9
}EPT_BURST_CMD_Type;
/**
* @brief EPT CNTMD selected
*/
typedef enum
{
EPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
EPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
EPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}EPT_CNTMD_SELECTE_Type;
/**
* @brief EPT OPM selected
*/
typedef enum
{
EPT_OPM_Once = ((CSP_REGISTER_T)(0x01ul << 6)),
EPT_OPM_Continue = ((CSP_REGISTER_T)(0x00ul << 6))
}EPT_OPM_SELECTE_Type;
/**
* @brief EPT CAP CMD
*/
typedef enum
{
EPT_CAP_EN = ((CSP_REGISTER_T)(0x01ul << 8)),
EPT_CAP_DIS = ((CSP_REGISTER_T)(0x00ul << 8))
}EPT_CAPLDEN_CMD_Type;
/**
* @brief EPT CAPMD selected
*/
typedef enum
{
EPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
EPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}EPT_CAPMD_SELECTE_Type;
/**
* @brief EPT CMPA RST CMD
*/
typedef enum
{
EPT_LDARST_EN = ((CSP_REGISTER_T)(0x00ul << 23)),
EPT_LDARST_DIS = ((CSP_REGISTER_T)(0x01ul << 23))
}EPT_LOAD_CMPA_RST_CMD_Type;
/**
* @brief EPT CMPB RST CMD
*/
typedef enum
{
EPT_LDBRST_EN = ((CSP_REGISTER_T)(0x00ul << 24)),
EPT_LDBRST_DIS = ((CSP_REGISTER_T)(0x01ul << 24))
}EPT_LOAD_CMPB_RST_CMD_Type;
/**
* @brief EPT CMPC RST CMD
*/
typedef enum
{
EPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
EPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}EPT_LOAD_CMPC_RST_CMD_Type;
/**
* @brief EPT CMPD RST CMD
*/
typedef enum
{
EPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
EPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}EPT_LOAD_CMPD_RST_CMD_Type;
/**
* @brief EPT FLT CMD
*/
typedef enum
{
EPT_FLT_DIS = ((CSP_REGISTER_T)(0x00ul << 10)),
EPT_FLT_EN = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_FLT_CMD_Type;
/**
* @brief EPT FLT CGFLT
*/
typedef enum
{
EPT_FLT_Bypass = ((CSP_REGISTER_T)(0x00ul << 13)),
EPT_FLT_2 = ((CSP_REGISTER_T)(0x01ul << 13)),
EPT_FLT_3 = ((CSP_REGISTER_T)(0x02ul << 13)),
EPT_FLT_4 = ((CSP_REGISTER_T)(0x03ul << 13)),
EPT_FLT_6 = ((CSP_REGISTER_T)(0x04ul << 13)),
EPT_FLT_8 = ((CSP_REGISTER_T)(0x05ul << 13)),
EPT_FLT_16 = ((CSP_REGISTER_T)(0x06ul << 13)),
EPT_FLT_32 = ((CSP_REGISTER_T)(0x07ul << 13))
}EPT_FLT_CGFLT_Type;
/**
* @brief EPT Triggle Mode
*/
typedef enum
{
EPT_Triggle_Continue = ((CSP_REGISTER_T)(0x00ul << 8)),
EPT_Triggle_Once = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_Triggle_Mode_Type;
/**
* @brief EPT Rearm select
*/
typedef enum
{
EPT_REARM_SYNCEN0 = ((CSP_REGISTER_T)(0x01ul << 16)),
EPT_REARM_SYNCEN1 = ((CSP_REGISTER_T)(0x02ul << 16)),
EPT_REARM_SYNCEN2 = ((CSP_REGISTER_T)(0x04ul << 16)),
EPT_REARM_SYNCEN3 = ((CSP_REGISTER_T)(0x08ul << 16)),
EPT_REARM_SYNCEN4 = ((CSP_REGISTER_T)(0x10ul << 16)),
EPT_REARM_SYNCEN5 = ((CSP_REGISTER_T)(0x20ul << 16))
}EPT_REARMX_Type;
/**
* @brief EPT Rearm select
*/
typedef enum
{
EPT_REARM_Selected_DIS = ((CSP_REGISTER_T)(0x00ul << 30)),
EPT_REARM_Selected_ZRO_AUTO = ((CSP_REGISTER_T)(0x01ul << 30)),
EPT_REARM_Selected_PRD_AUTO = ((CSP_REGISTER_T)(0x02ul << 30)),
EPT_REARM_Selected_ZRO_PRD_AUTO = ((CSP_REGISTER_T)(0x03ul << 30))
}EPT_REARM_MODE_Type;
/**
* @brief EPT Syncusr0 Trig select
*/
typedef enum
{
EPT_SYNCUSR0_REARMTrig_DIS = ((CSP_REGISTER_T)(0x00ul << 22)),
EPT_SYNCUSR0_REARMTrig_T1 = ((CSP_REGISTER_T)(0x01ul << 22)),
EPT_SYNCUSR0_REARMTrig_T2 = ((CSP_REGISTER_T)(0x02ul << 22)),
EPT_SYNCUSR0_REARMTrig_T1T2 = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_SYNCUSR0_REARMTrig_Selecte_Type;
/**
* @brief EPT TRGSRC0 ExtSync Selected
*/
typedef enum
{
EPT_TRGSRC0_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 24)),
EPT_TRGSRC0_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 24)),
EPT_TRGSRC0_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 24)),
EPT_TRGSRC0_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 24)),
EPT_TRGSRC0_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 24)),
EPT_TRGSRC0_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 24))
}EPT_TRGSRC0_ExtSync_Selected_Type;
/**
* @brief EPT TRGSRC1 ExtSync Selected
*/
typedef enum
{
EPT_TRGSRC1_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 27)),
EPT_TRGSRC1_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 27)),
EPT_TRGSRC1_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 27)),
EPT_TRGSRC1_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 27)),
EPT_TRGSRC1_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 27)),
EPT_TRGSRC1_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 27))
}EPT_TRGSRC1_ExtSync_Selected_Type;
/**
* @brief EPT PHSEN CMD
*/
typedef enum
{
EPT_PHSEN_DIS = ((CSP_REGISTER_T)(0x00ul << 8)),
EPT_PHSEN_EN = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_PHSEN_CMD_Type;
/**
* @brief EPT PHSDIR selecte
*/
typedef enum
{
EPT_PHSDIR_increase = ((CSP_REGISTER_T)(0x01ul << 31)),
EPT_PHSEN_decrease = ((CSP_REGISTER_T)(0x00ul << 31))
}EPT_PHSDIR_Type;
/**
* @brief EPT GLDCR Config
*/
typedef enum
{
EPT_GLDMD_Selecte_ZRO = ((CSP_REGISTER_T)(0x00ul << 1)),
EPT_GLDMD_Selecte_PRD = ((CSP_REGISTER_T)(0x01ul << 1)),
EPT_GLDMD_Selecte_ZRO_PRD = ((CSP_REGISTER_T)(0x02ul << 1)),
EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x03ul << 1)),
EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x04ul << 1)),
EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x05ul << 1)),
EPT_GLDMD_Selecte_SW = ((CSP_REGISTER_T)(0x0Ful << 1))
}EPT_GLDMD_Selecte_Type;
/**
* @brief EPT OSTMD Selecte
*/
typedef enum
{
EPT_GLD_OneShot_DIS = ((CSP_REGISTER_T)(0x00ul << 5)),
EPT_GLD_OneShot_EN = ((CSP_REGISTER_T)(0x01ul << 5))
}EPT_GLD_OneShot_CMD_Type;
/**
* @brief EPT PRDR Event Load
*/
typedef enum
{
EPT_PRDR_EventLoad_PEND = ((CSP_REGISTER_T)(0x00ul << 4)),
EPT_PRDR_EventLoad_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x01ul << 4)),
EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x02ul << 4)),
EPT_PRDR_EventLoad_Immediate = ((CSP_REGISTER_T)(0x03ul << 4))
} EPT_PRDR_EventLoad_Type;
/**
* @brief EPT CMPX Event load
*/
typedef enum
{
EPT_CMPX_EventLoad_DIS = 0,
EPT_CMPX_EventLoad_Immediate = 1,
EPT_CMPX_EventLoad_ZRO = 2,
EPT_CMPX_EventLoad_PRD = 3,
EPT_CMPX_EventLoad_ExiLoad_SYNC = 4
}EPT_CMPX_EventLoad_Type;
/**
* @brief EPT AQCRX Event load
*/
typedef enum
{
EPT_AQCRX_EventLoad_DIS = 0,
EPT_AQCRX_EventLoad_Immediate = 1,
EPT_AQCRX_EventLoad_ZRO = 2,
EPT_AQCRX_EventLoad_PRD = 3,
EPT_AQCRX_EventLoad_ExiLoad_SYNC = 4
}EPT_AQCRX_EventLoad_Type;
/**
* @brief EPT PWMX Selecte
*/
typedef enum
{
EPT_PWMA = 0,
EPT_PWMB = 1,
EPT_PWMC = 2,
EPT_PWMD = 3
}EPT_PWMX_Selecte_Type;
/**
* @brief EPT CA Selecte
*/
typedef enum
{
EPT_CA_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 20)),
EPT_CA_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 20)),
EPT_CA_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 20)),
EPT_CA_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 20))
}EPT_CA_Selecte_Type;
/**
* @brief EPT CB Selecte
*/
typedef enum
{
EPT_CB_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 22)),
EPT_CB_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 22)),
EPT_CB_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 22)),
EPT_CB_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_CB_Selecte_Type;
/**
* @brief EPT PWM ZRO Output
*/
typedef enum
{
EPT_PWM_ZRO_Event_Nochange = ((CSP_REGISTER_T)(0x00ul )),
EPT_PWM_ZRO_Event_OutLow = ((CSP_REGISTER_T)(0x01ul )),
EPT_PWM_ZRO_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul )),
EPT_PWM_ZRO_Event_Negate = ((CSP_REGISTER_T)(0x03ul ))
}EPT_PWM_ZRO_Output_Type;
/**
* @brief EPT PWM PRD Output
*/
typedef enum
{
EPT_PWM_PRD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<2 )),
EPT_PWM_PRD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<2 )),
EPT_PWM_PRD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<2 )),
EPT_PWM_PRD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<2 ))
}EPT_PWM_PRD_Output_Type;
/**
* @brief EPT PWM CAU Output
*/
typedef enum
{
EPT_PWM_CAU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<4 )),
EPT_PWM_CAU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<4 )),
EPT_PWM_CAU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<4 )),
EPT_PWM_CAU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<4 ))
}EPT_PWM_CAU_Output_Type;
/**
* @brief EPT PWM CAD Output
*/
typedef enum
{
EPT_PWM_CAD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<6 )),
EPT_PWM_CAD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<6 )),
EPT_PWM_CAD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<6 )),
EPT_PWM_CAD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<6 ))
}EPT_PWM_CAD_Output_Type;
/**
* @brief EPT PWM CBU Output
*/
typedef enum
{
EPT_PWM_CBU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<8 )),
EPT_PWM_CBU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<8 )),
EPT_PWM_CBU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<8 )),
EPT_PWM_CBU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<8 ))
}EPT_PWM_CBU_Output_Type;
/**
* @brief EPT PWM CBD Output
*/
typedef enum
{
EPT_PWM_CBD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<10 )),
EPT_PWM_CBD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<10 )),
EPT_PWM_CBD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<10 )),
EPT_PWM_CBD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<10 ))
}EPT_PWM_CBD_Output_Type;
/**
* @brief EPT PWM T1U Output
*/
typedef enum
{
EPT_PWM_T1U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<12 )),
EPT_PWM_T1U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<12 )),
EPT_PWM_T1U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<12 )),
EPT_PWM_T1U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<12 ))
}EPT_PWM_T1U_Output_Type;
/**
* @brief EPT PWM T1D Output
*/
typedef enum
{
EPT_PWM_T1D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<14 )),
EPT_PWM_T1D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<14 )),
EPT_PWM_T1D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<14 )),
EPT_PWM_T1D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<14 ))
}EPT_PWM_T1D_Output_Type;
/**
* @brief EPT PWM T2U Output
*/
typedef enum
{
EPT_PWM_T2U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<16 )),
EPT_PWM_T2U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<16 )),
EPT_PWM_T2U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<16 )),
EPT_PWM_T2U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<16 ))
}EPT_PWM_T2U_Output_Type;
/**
* @brief EPT PWM T2D Output
*/
typedef enum
{
EPT_PWM_T2D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<18 )),
EPT_PWM_T2D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<18 )),
EPT_PWM_T2D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<18 )),
EPT_PWM_T2D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<18 ))
}EPT_PWM_T2D_Output_Type;
/**
* @brief EPT CPCR CMD
*/
typedef enum
{
EPT_CPCR_ENALBE = ((CSP_REGISTER_T)(0x01ul<<16 )),
EPT_CPCR_Disable = ((CSP_REGISTER_T)(0x00ul<<16 ))
}EPT_CPCR_CMD_Type;
/**
* @brief EPT CPCR Source Selecte
*/
typedef enum
{
EPT_CPCR_Source_TCLK = ((CSP_REGISTER_T)(0)),
EPT_CPCR_Source_TIN_BT0OUT = ((CSP_REGISTER_T)(1)),
EPT_CPCR_Source_TIN_BT1OUT = ((CSP_REGISTER_T)(2))
}EPT_CPCR_Source_Selecte_Type;
/**
* @brief EPT CPCR CDUTY
*/
typedef enum
{
EPT_CDUTY_DIS = ((CSP_REGISTER_T)(0<<11)),
EPT_CDUTY_7_8 = ((CSP_REGISTER_T)(1<<11)),
EPT_CDUTY_6_8 = ((CSP_REGISTER_T)(2<<11)),
EPT_CDUTY_5_8 = ((CSP_REGISTER_T)(3<<11)),
EPT_CDUTY_4_8 = ((CSP_REGISTER_T)(4<<11)),
EPT_CDUTY_3_8 = ((CSP_REGISTER_T)(5<<11)),
EPT_CDUTY_2_8 = ((CSP_REGISTER_T)(6<<11)),
EPT_CDUTY_1_8 = ((CSP_REGISTER_T)(7<<11))
}EPT_CDUTY_Type;
/**
* @brief EPT EPX
*/
typedef enum
{
EPT_EP0 = 0,
EPT_EP1 = 1,
EPT_EP2 = 2,
EPT_EP3 = 3,
EPT_EP4 = 4,
EPT_EP5 = 5,
EPT_EP6 = 6,
EPT_EP7 = 7
}EPT_EPX_Type;
/**
* @brief EPT Input selecte
*/
typedef enum
{
EPT_Input_selecte_EPI0 = ((CSP_REGISTER_T)(1)),
EPT_Input_selecte_EPI1 = ((CSP_REGISTER_T)(2)),
EPT_Input_selecte_EPI2 = ((CSP_REGISTER_T)(3)),
EPT_Input_selecte_EPI3 = ((CSP_REGISTER_T)(4)),
EPT_Input_selecte_EPI4 = ((CSP_REGISTER_T)(5)),
EPT_Input_selecte_ORL0 = ((CSP_REGISTER_T)(0XE)),
EPT_Input_selecte_ORL1 = ((CSP_REGISTER_T)(0XF))
}EPT_Input_selecte_Type;
/**
* @brief EPT FLT PACE0
*/
typedef enum
{
EPT_FLT_PACE0_DIS = ((CSP_REGISTER_T)(0<<8)),
EPT_FLT_PACE0_2CLK = ((CSP_REGISTER_T)(1<<8)),
EPT_FLT_PACE0_3CLK = ((CSP_REGISTER_T)(2<<8)),
EPT_FLT_PACE0_4CLK = ((CSP_REGISTER_T)(3<<8))
}EPT_FLT_PACE0_Type;
/**
* @brief EPT FLT PACE1
*/
typedef enum
{
EPT_FLT_PACE1_DIS = ((CSP_REGISTER_T)(0<<10)),
EPT_FLT_PACE1_2CLK = ((CSP_REGISTER_T)(1<<10)),
EPT_FLT_PACE1_3CLK = ((CSP_REGISTER_T)(2<<10)),
EPT_FLT_PACE1_4CLK = ((CSP_REGISTER_T)(3<<10))
}EPT_FLT_PACE1_Type;
/**
* @brief EPT DB EventLoad
*/
typedef enum
{
EPT_DB_EventLoad_DIS = 0,
EPT_DB_EventLoad_Immediate = 1,
EPT_DB_EventLoad_ZRO = 2,
EPT_DB_EventLoad_PRD = 3,
EPT_DB_EventLoad_ZRO_PRD = 4
}EPT_DB_EventLoad_Type;
/**
* @brief EPT CHX Selecte
*/
typedef enum
{
EPT_CHA_Selecte = 0,
EPT_CHB_Selecte = 1,
EPT_CHC_Selecte = 2,
}EPT_CHX_Selecte_Type;
/**
* @brief EPT INSEL
*/
typedef enum
{
EPT_CHAINSEL_PWMA_RISE_FALL = ((CSP_REGISTER_T)(0<<4)),
EPT_CHAINSEL_PWMB_RISE_PWMA_FALL = ((CSP_REGISTER_T)(1<<4)),
EPT_CHAINSEL_PWMA_RISE_PWMB_FALL = ((CSP_REGISTER_T)(2<<4)),
EPT_CHAINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(3<<4)),
EPT_CHBINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(0<<12)),
EPT_CHBINSEL_PWMC_RISE_PWMB_FALL = ((CSP_REGISTER_T)(1<<12)),
EPT_CHBINSEL_PWMB_RISE_PWMC_FALL = ((CSP_REGISTER_T)(2<<12)),
EPT_CHBINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(3<<12)),
EPT_CHCINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(0<<20)),
EPT_CHCINSEL_PWMD_RISE_PWMC_FALL = ((CSP_REGISTER_T)(1<<20)),
EPT_CHCINSEL_PWMC_RISE_PWMD_FALL = ((CSP_REGISTER_T)(2<<20)),
EPT_CHCINSEL_PWMD_RISE_FALL = ((CSP_REGISTER_T)(3<<20))
}EPT_INSEL_Type;
/**
* @brief EPT OUTSEL
*/
typedef enum
{
EPT_CHA_OUTSEL_PWMA_PWMB_Bypass = ((CSP_REGISTER_T)(0)),
EPT_CHA_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1)),
EPT_CHA_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2)),
EPT_CHA_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3)),
EPT_CHB_OUTSEL_PWMB_PWMC_Bypass = ((CSP_REGISTER_T)(0<<8)),
EPT_CHB_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<8)),
EPT_CHB_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<8)),
EPT_CHB_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<8)),
EPT_CHC_OUTSEL_PWMC_PWMD_Bypass = ((CSP_REGISTER_T)(0<<16)),
EPT_CHC_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<16)),
EPT_CHC_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<16)),
EPT_CHC_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<16))
}EPT_OUTSEL_Type;
/**
* @brief EPT OUT POLARITY
*/
typedef enum
{
EPT_PA_PB_OUT_Direct = ((CSP_REGISTER_T)(0)),
EPT_PA_OUT_Reverse = ((CSP_REGISTER_T)(1)),
EPT_PB_OUT_Reverse = ((CSP_REGISTER_T)(2)),
EPT_PA_PB_OUT_Reverse = ((CSP_REGISTER_T)(3))
}EPT_OUT_POLARITY_Type;
/**
* @brief EPT OUT SWAP
*/
typedef enum
{
EPT_PAtoCHX_PBtoCHY = ((CSP_REGISTER_T)(0)),
EPT_PBtoCHX_PBtoCHY = ((CSP_REGISTER_T)(1)),
EPT_PAtoCHX_PAtoCHY = ((CSP_REGISTER_T)(2)),
EPT_PBtoCHX_PAtoCHY = ((CSP_REGISTER_T)(3))
}EPT_OUT_SWAP_Type;
/**
* @brief EPT TRGSRCX Selecte
*/
typedef enum
{
EPT_TRGSRC0 = 0,
EPT_TRGSRC1 = 1,
EPT_TRGSRC2 = 2,
EPT_TRGSRC3 = 3
}EPT_TRGSRCX_Select_Type;
/**
* @brief EPT EVTRG TRGSRCX SET
*/
typedef enum
{
EPT_EVTRG_TRGSRCX_DIS = ((CSP_REGISTER_T)(0x00ul )),
EPT_EVTRG_TRGSRCX_ZRO = ((CSP_REGISTER_T)(0x01ul )),
EPT_EVTRG_TRGSRCX_PRD = ((CSP_REGISTER_T)(0x02ul )),
EPT_EVTRG_TRGSRCX_ZROorPRD = ((CSP_REGISTER_T)(0x03ul )),
EPT_EVTRG_TRGSRCX_CMPAU = ((CSP_REGISTER_T)(0x04ul )),
EPT_EVTRG_TRGSRCX_CMPAD = ((CSP_REGISTER_T)(0x05ul )),
EPT_EVTRG_TRGSRCX_CMPBU = ((CSP_REGISTER_T)(0x06ul )),
EPT_EVTRG_TRGSRCX_CMPBD = ((CSP_REGISTER_T)(0x07ul )),
EPT_EVTRG_TRGSRCX_CMPCU = ((CSP_REGISTER_T)(0x08ul )),
EPT_EVTRG_TRGSRCX_CMPCD = ((CSP_REGISTER_T)(0x09ul )),
EPT_EVTRG_TRGSRCX_CMPDU = ((CSP_REGISTER_T)(0x0Aul )),
EPT_EVTRG_TRGSRCX_CMPDD = ((CSP_REGISTER_T)(0x0Bul )),
EPT_EVTRG_TRGSRC01_ExtSync = ((CSP_REGISTER_T)(0x0Cul )),
EPT_EVTRG_TRGSRC23_PeriodEnd = ((CSP_REGISTER_T)(0x0Cul )),
EPT_EVTRG_TRGSRCX_PE0 = ((CSP_REGISTER_T)(0x0Dul )),
EPT_EVTRG_TRGSRCX_PE1 = ((CSP_REGISTER_T)(0x0Eul )),
EPT_EVTRG_TRGSRCX_PE2 = ((CSP_REGISTER_T)(0x0Ful ))
}EPT_EVTRG_TRGSRCX_TypeDef;
typedef enum
{
EPT_TRGSRCX_EN = ((CSP_REGISTER_T)0x01ul),
EPT_TRGSRCX_DIS = ((CSP_REGISTER_T)0x00ul)
}EPT_TRGSRCX_CMD_TypeDef;
/**
* @brief EPT INT register
*/
typedef enum
{
//RISR IMCR MISR ICR
EPT_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 0)),
EPT_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 1)),
EPT_TRGEV2_INT = ((CSP_REGISTER_T)(0x01ul << 2)),
EPT_TRGEV3_INT = ((CSP_REGISTER_T)(0x01ul << 3)),
EPT_CAP_LD0 = ((CSP_REGISTER_T)(0x01ul << 4)),
EPT_CAP_LD1 = ((CSP_REGISTER_T)(0x01ul << 5)),
EPT_CAP_LD2 = ((CSP_REGISTER_T)(0x01ul << 6)),
EPT_CAP_LD3 = ((CSP_REGISTER_T)(0x01ul << 7)),
EPT_CAU = ((CSP_REGISTER_T)(0x01ul <<8)),
EPT_CAD = ((CSP_REGISTER_T)(0x01ul <<9)),
EPT_CBU = ((CSP_REGISTER_T)(0x01ul <<10)),
EPT_CBD = ((CSP_REGISTER_T)(0x01ul <<11)),
EPT_CCU = ((CSP_REGISTER_T)(0x01ul <<12)),
EPT_CCD = ((CSP_REGISTER_T)(0x01ul <<13)),
EPT_CDU = ((CSP_REGISTER_T)(0x01ul <<14)),
EPT_CDD = ((CSP_REGISTER_T)(0x01ul <<15)),
EPT_PEND = ((CSP_REGISTER_T)(0x01ul <<16))
}EPT_INT_TypeDef;
/**
* @brief EPT EMINT register
*/
typedef enum
{
//EMRISR EMIMCR EMMISR EMICR
EPT_EP0_EMINT = ((CSP_REGISTER_T)(0x01ul << 0)),
EPT_EP1_EMINT = ((CSP_REGISTER_T)(0x01ul << 1)),
EPT_EP2_EMINT = ((CSP_REGISTER_T)(0x01ul << 2)),
EPT_EP3_EMINT = ((CSP_REGISTER_T)(0x01ul << 3)),
EPT_EP4_EMINT = ((CSP_REGISTER_T)(0x01ul << 4)),
EPT_EP5_EMINT = ((CSP_REGISTER_T)(0x01ul << 5)),
EPT_EP6_EMINT = ((CSP_REGISTER_T)(0x01ul << 6)),
EPT_EP7_EMINT = ((CSP_REGISTER_T)(0x01ul << 7)),
EPT_CPU_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 8)),
EPT_MEM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 9)),
EPT_EOM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_EMINT_TypeDef;
/**
* @brief EPT LKCR TRG Source
*/
typedef enum
{
EPT_LKCR_TRG_EP0 = 0,
EPT_LKCR_TRG_EP1 = 2,
EPT_LKCR_TRG_EP2 = 4,
EPT_LKCR_TRG_EP3 = 6,
EPT_LKCR_TRG_EP4 = 8,
EPT_LKCR_TRG_EP5 = 10,
EPT_LKCR_TRG_EP6 = 12,
EPT_LKCR_TRG_EP7 = 14,
EPT_LKCR_TRG_CPU_FAULT = 15,
EPT_LKCR_TRG_MEM_FAULT = 16,
EPT_LKCR_TRG_EOM_FAULT = 17
}EPT_LKCR_TRG_Source_Type;
/**
* @brief EPT LKCR Mode Selecte
*/
typedef enum
{
EPT_LKCR_Mode_LOCK_DIS = ((CSP_REGISTER_T)0x00ul),
EPT_LKCR_Mode_SLOCK_EN = ((CSP_REGISTER_T)0x01ul),
EPT_LKCR_Mode_HLOCK_EN = ((CSP_REGISTER_T)0x02ul),
EPT_LKCR_TRG_X_FAULT_HLOCK_EN = ((CSP_REGISTER_T)0x03ul),
EPT_LKCR_TRG_X_FAULT_HLOCK_DIS = ((CSP_REGISTER_T)0x04ul),
}EPT_LKCR_Mode_Type;
/**
* @brief EPT OUTPUT Channel
*/
typedef enum
{
EPT_OUTPUT_Channel_CHAX = 0,
EPT_OUTPUT_Channel_CHBX = 2,
EPT_OUTPUT_Channel_CHCX = 4,
EPT_OUTPUT_Channel_CHD = 6,
EPT_OUTPUT_Channel_CHAY = 8,
EPT_OUTPUT_Channel_CHBY = 10,
EPT_OUTPUT_Channel_CHCY = 12
}EPT_OUTPUT_Channel_Type;
/**
* @brief EPT SHLOCK OUTPUT Statue
*/
typedef enum
{
EPT_SHLOCK_OUTPUT_HImpedance = 0,
EPT_SHLOCK_OUTPUT_High = 1,
EPT_SHLOCK_OUTPUT_Low = 2,
EPT_SHLOCK_OUTPUT_Nochange = 3
}EPT_SHLOCK_OUTPUT_Statue_Type;
/** @addtogroup EPT_Exported_functions
* @{
*/
extern void EPT_Software_Prg(void);
extern void EPT_Start(void);
extern void EPT_Stop(void);
extern void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X);
extern void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X
, U16_T EPT_PSCR);
extern void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD);
extern void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD
, EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD
, EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR);
extern void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected ,
EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN);
extern void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR);
extern void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX );
extern void EPT_Caputure_Rearm(void);
extern void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN);
extern void EPT_Globle_SwLoad_CMD(void);
extern void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV);
extern void EPT_PWMX_Output_Control(
EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X ,
EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output ,
EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output ,
EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output ,
EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output ,
EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output
);
extern void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte);
extern void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value);
extern void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x);
extern void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x);
extern void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X);
extern void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx);
extern void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL);
extern void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X);
extern void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X);
extern void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF);
extern void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD);
extern void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select);
extern void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_Vector_Int_Enable(void);
extern void EPT_Vector_Int_Disable(void);
extern void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X);
extern void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X);
#endif /**< apt32f102_ept_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_et.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_et_H
#define _apt32f102_et_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define ET_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------ET value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief ET SWTRG register
*/
typedef enum
{
ET_SWTRG_CH0 = 0,
ET_SWTRG_CH1 = (1<<1),
ET_SWTRG_CH2 = (1<<2),
ET_SWTRG_CH3 = (1<<3),
ET_SWTRG_CH4 = (1<<4),
ET_SWTRG_CH5 = (1<<5),
ET_SWTRG_CH6 = (1<<6),
ET_SWTRG_CH7 = (1<<7),
}CRC_ETSWTRG_TypeDef;
/**
* @brief SRCSEL register
*/
typedef enum
{
ET_SRC0 = 0,
ET_SRC1 = 1,
ET_SRC2 = 2,
}CRC_ESRCSEL_TypeDef;
/**
* @brief SRCSEL register
*/
typedef enum
{
ET_DST0 = 0,
ET_DST1 = 1,
ET_DST2 = 2,
}CRC_DSTSEL_TypeDef;
/**
* @brief SRCSEL register
*/
typedef enum
{
ET_CH3 = 0,
ET_CH4 = 1,
ET_CH5 = 2,
ET_CH6 = 3,
ET_CH7 = 4,
}CRC_ETCHX_TypeDef;
/**
* @brief TRIG MODE register
*/
typedef enum
{
TRG_HW = (0X00<<1),
TRG_SW = (0X01<<1),
}CRC_TRIGMODE_TypeDef;
//Source IP Event
#define ET_LPT_SYNC (0X0)
#define ET_EXI_SYNC0 (0X4)
#define ET_EXI_SYNC1 (0X5)
#define ET_EXI_SYNC2 (0X6)
#define ET_EXI_SYNC3 (0X7)
#define ET_EXI_SYNC4 (0X8)
#define ET_EXI_SYNC5 (0X9)
#define ET_RTC_SYNC0 (0XA)
#define ET_RTC_SYNC1 (0XB)
#define ET_BT_SYNC0 (0XC)
#define ET_BT_SYNC1 (0XD)
#define ET_EPT0_SYNC0 (0X10)
#define ET_EPT0_SYNC1 (0X11)
#define ET_EPT0_SYNC2 (0X12)
#define ET_EPT0_SYNC3 (0X13)
#define ET_GPT0_SYNC0 (0X20)
#define ET_GPT0_SYNC1 (0X21)
#define ET_ADC_SYNC0 (0X30)
#define ET_ADC_SYNC1 (0X31)
#define ET_TOUCH_SYNC (0X3C)
//Destination IP Event
#define ET_LPT_TRGSRC (0X0)
#define ET_BT0_TRGSRC0 (0X2)
#define ET_BT0_TRGSRC1 (0X3)
#define ET_BT1_TRGSRC0 (0X4)
#define ET_BT1_TRGSRC1 (0X5)
#define ET_ADC_TRGSRC0 (0X6)
#define ET_ADC_TRGSRC1 (0X7)
#define ET_ADC_TRGSRC2 (0X8)
#define ET_ADC_TRGSRC3 (0X9)
#define ET_ADC_TRGSRC4 (0XA)
#define ET_ADC_TRGSRC5 (0XB)
#define ET_EPT0_TRGSRC0 (0X10)
#define ET_EPT0_TRGSRC1 (0X11)
#define ET_EPT0_TRGSRC2 (0X12)
#define ET_EPT0_TRGSRC3 (0X13)
#define ET_EPT0_TRGSRC4 (0X14)
#define ET_EPT0_TRGSRC5 (0X15)
#define ET_GPT0_TRGSRC0 (0X24)
#define ET_GPT0_TRGSRC1 (0X25)
#define ET_GPT0_TRGSRC2 (0X26)
#define ET_GPT0_TRGSRC3 (0X27)
#define ET_GPT0_TRGSRC4 (0X28)
#define ET_GPT0_TRGSRC5 (0X29)
#define ET_TOUCH_TRGSRC (0X3C)
extern void ET_DeInit(void);
extern void ET_ENABLE(void);
extern void ET_DISABLE(void);
extern void ET_SWTRG_CMD(CRC_ETSWTRG_TypeDef ETSWTRG_X,FunctionalStatus NewState);
extern void ET_CH0_SRCSEL(CRC_ESRCSEL_TypeDef ESRCSEL_X,FunctionalStatus NewState,U8_T SRCSEL_X);
extern void ET_CH0_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CH1_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X);
extern void ET_CH1_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CH2_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X);
extern void ET_CH2_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CHx_CONTROL(CRC_ETCHX_TypeDef ETCHX,FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T SRCSEL_X,U8_T DSTSEL_X);
#endif /**< apt32f102_crc_H */

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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_gpio_H
#define _apt32f102_gpio_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define GPIO_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------GPIO value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief GPIO pin numbner
*/
typedef enum
{
PIN_0 = 0, /*!< Pin 0 selected */
PIN_1 = 4, /*!< Pin 1 selected */
PIN_2 = 8, /*!< Pin 2 selected */
PIN_3 = 12, /*!< Pin 3 selected */
PIN_4 = 16, /*!< Pin 4 selected */
PIN_5 = 20, /*!< Pin 5 selected */
PIN_6 = 24, /*!< Pin 6 selected */
PIN_7 = 28, /*!< Pin 7 selected */
PIN_8 = 0, /*!< Pin 8 selected */
PIN_9 = 4, /*!< Pin 9 selected */
PIN_10 = 8, /*!< Pin 10 selected */
PIN_11 = 12, /*!< Pin 11 selected */
PIN_12 = 16, /*!< Pin 12 selected */
PIN_13 = 20, /*!< Pin 13 selected */
PIN_14 = 24, /*!< Pin 13 selected */
PIN_15 = 28, /*!< Pin 13 selected */
}GPIO_Pin_TypeDef;
/**
* @brief GPIO high/low register
*/
typedef enum
{
LowByte = 0,
HighByte = 1,
}GPIO_byte_TypeDef;
/**
* @brief GPIO IO status
*/
typedef enum
{
Intput = 1,
Output = 0,
}GPIO_Dir_TypeDef;
/**
* @brief GPIO IO mode
*/
typedef enum
{
PUDR = 0, //pull high or low
DSCR =1, //drive strenth
OMCR =2, //open drain
IECR =3, //int
}GPIO_Mode_TypeDef;
/**
* @brief GPIO IO Group
*/
typedef enum
{
PA0 = 0,
PB0 = 2,
GPIOA = 0,
GPIOB = 2,
}GPIO_Group_TypeDef;
/**
* @brief GPIO exi number
*/
typedef enum
{
EXI0 = 0,
EXI1 = 1,
EXI2 = 2,
EXI3 = 3,
EXI4 = 4,
EXI5 = 5,
EXI6 = 6,
EXI7 = 7,
EXI8 = 8,
EXI9 = 9,
EXI10 = 10,
EXI11 = 11,
EXI12 = 12,
EXI13 = 13,
EXI14 = 14,
EXI15 = 15,
}GPIO_EXI_TypeDef;
/**
* @brief EXI PIN
*/
typedef enum
{
Selete_EXI_PIN0 = (CSP_REGISTER_T)(0),
Selete_EXI_PIN1 = (CSP_REGISTER_T)(1),
Selete_EXI_PIN2 = (CSP_REGISTER_T)(2),
Selete_EXI_PIN3 = (CSP_REGISTER_T)(3),
Selete_EXI_PIN4 = (CSP_REGISTER_T)(4),
Selete_EXI_PIN5 = (CSP_REGISTER_T)(5),
Selete_EXI_PIN6 = (CSP_REGISTER_T)(6),
Selete_EXI_PIN7 = (CSP_REGISTER_T)(7),
Selete_EXI_PIN8 = (CSP_REGISTER_T)(8),
Selete_EXI_PIN9 = (CSP_REGISTER_T)(9),
Selete_EXI_PIN10 = (CSP_REGISTER_T)(10),
Selete_EXI_PIN11 = (CSP_REGISTER_T)(11),
Selete_EXI_PIN12 = (CSP_REGISTER_T)(12),
Selete_EXI_PIN13 = (CSP_REGISTER_T)(13),
Selete_EXI_PIN14 = (CSP_REGISTER_T)(14),
Selete_EXI_PIN15 = (CSP_REGISTER_T)(15),
Selete_EXI_PIN16 = (CSP_REGISTER_T)(16),
Selete_EXI_PIN17 = (CSP_REGISTER_T)(17),
Selete_EXI_PIN18 = (CSP_REGISTER_T)(18),
Selete_EXI_PIN19 = (CSP_REGISTER_T)(19)
}GPIO_EXIPIN_TypeDef;
/**
* @brief GPIO INPUT MODE SETECTED
*/
typedef enum
{
INPUT_MODE_SETECTED_CMOS = 0,
INPUT_MODE_SETECTED_TTL1 = 1,
INPUT_MODE_SETECTED_TTL2 = 2
}INPUT_MODE_SETECTED_TypeDef;
#define nop asm ("nop")
#define SetPA0(n) (GPIOA0->SODR = (1ul<<n))
#define ClrPA0(n) (GPIOA0->CODR = (1ul<<n))
#define SetPB0(n) (GPIOB0->SODR = (1ul<<n))
#define ClrPB0(n) (GPIOB0->CODR = (1ul<<n))
#define PA0in(n) (((GPIOA0->PSDR)>>n) & 1ul)
#define PB0in(n) (((GPIOB0->PSDR)>>n) & 1ul)
#define CSP_GPIO_SET_CONLR(cm,val) ((cm)->CONLR = val)
#define CSP_GPIO_GET_CONLR(cm) ((cm)->CONLR)
#define CSP_GPIO_SET_CONHR(cm,val) ((cm)->CONHR = val)
#define CSP_GPIO_GET_CONHR(cm) ((cm)->CONHR)
#define CSP_GPIO_SET_WODR(cm,val) ((cm)->WODR = val)
#define CSP_GPIO_SET_SODR(cm,val) ((cm)->SODR = val)
#define CSP_GPIO_SET_CODR(cm,val) ((cm)->CODR = val)
#define CSP_GPIO_GET_PSDR(cm) ((cm)->PSDR)
#define CSP_GPIO_SET_PUDR(cm,val) ((cm)->PUDR = val)
#define CSP_GPIO_GET_PUDR(cm) ((cm)->PUDR)
#define CSP_GPIO_SET_DSCR(cm,val) ((cm)->DSCR = val)
#define CSP_GPIO_GET_DSCR(cm) ((cm)->DSCR)
#define CSP_GPIO_SET_OMCR(cm,val) ((cm)->OMCR = val)
#define CSP_GPIO_GET_OMCR(cm) ((cm)->OMCR)
#define CSP_GPIO_SET_IECR(cm,val) ((cm)->IECR = val)
#define CSP_GPIO_GET_IECR(cm) ((cm)->IECR)
#define CSP_GPIO_SET_IGRP(cm,val) ((cm)->IGRP = val)
#define CSP_GPIO_GET_IGRP(cm) ((cm)->IGRP)
/******************************************************************************
************************** Exported functions ************************
******************************************************************************/
extern void GPIOA0_DeInit(GPIO_Pin_TypeDef GPIO_Pin);
extern void GPIO_DeInit(void);
extern void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,uint8_t bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X);
extern void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val);
extern void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,uint8_t PinNum);
extern void GPIO_Init(CSP_GPIO_T *GPIOx,uint8_t PinNum,GPIO_Dir_TypeDef Dir);
extern void GPIO_Write_Low(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Write_High(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val);
extern uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,uint8_t bit);
extern uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Reverse(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_Set_Value(CSP_GPIO_T *GPIOx,uint8_t bitposi,uint8_t bitval);
extern void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_Debug_IO_12_13(void);
extern void GPIO_Debug_IO_01_02(void);
extern void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , uint8_t PinNum , GPIO_EXIPIN_TypeDef EXIPIN_x);
extern void GPIOA00_Set_ResetPin();
extern void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,uint8_t bit);
extern void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,uint8_t bit);
/*************************************************************/
#endif /**< apt32f102_gpio_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_gpt.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_gpt_H
#define _apt32f102_gpt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define GPT_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------GPT value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief GPT CLK EN register
*/
typedef enum
{
GPTCLK_DIS = 0,
GPTCLK_EN = 1,
}GPT_CLK_TypeDef;
/**
* @brief GPT CLK SOURCE register
*/
typedef enum
{
GPT_PCLK = (0<<3),
GPT_TRGUSR3 = (1<<3),
}GPT_CSS_TypeDef;
/**
* @brief GPT START SHADOW register
*/
typedef enum
{
GPT_SHADOW = (0<<6),
GPT_IMMEDIATE= (1<<6),
}GPT_SHDWSTP_TypeDef;
/**
* @brief GPT COUNT EDGE register
*/
typedef enum
{
DIR_INCREASE = (0<<3),
DIR_DECREASE= (1<<3),
}GPT_CNTDIR_TypeDef;
/**
* @brief GPT COUNT EDGE register
*/
typedef enum
{
GPT_INCREASE = (0<<0),
GPT_DECREASE= (1<<0),
GPT_IN_DECREASE= (2<<0),
}GPT_CNTMD_TypeDef;
/**
* @brief GPT START SYN EN register
*/
typedef enum
{
GPT_SWSYNDIS= (0<<2),
GPT_SWSYNEN= (1<<2),
}GPT_SWSYN_TypeDef;
/**
* @brief GPT ILDE IO Status register
*/
typedef enum
{
GPT_IDLE_Z= (0<<3),
GPT_IDLE_LOW= (1<<3),
}GPT_IDLEST_TypeDef;
/**
* @brief GPT PRDLD register
*/
typedef enum
{
GPT_PRDLD_PEND= (0<<4),
GPT_PRDLD_LOAD_SYNC= (1<<4),
GPT_PRDLD_ZERO_LOAD_SYNC= (2<<4),
GPT_PRDLD_IMMEDIATELY= (3<<4),
}GPT_PRDLD0_TypeDef;
/**
* @brief GPT CAPLDEN register
*/
typedef enum
{
GPT_CAP_DIS= (0<<8),
GPT_CAP_EN= (1<<8),
}GPT_CAPLDEN_TypeDef;
/**
* @brief GPT BURST register
*/
typedef enum
{
GPT_BURST_DIS= (0<<9),
GPT_BURST_EN= (1<<9),
}GPT_BURST_TypeDef;
/**
* @brief GPT BURST register
*/
typedef enum
{
GPT_CG_CHAX= (0<<11),
GPT_CG_CHBX= (1<<11),
}GPT_CGSRC_TypeDef;
/**
* @brief GPT CGFLT register
*/
typedef enum
{
GPT_CGFLT_00= (0<<13),
GPT_CGFLT_02= (1<<13),
GPT_CGFLT_03= (2<<13),
GPT_CGFLT_04= (3<<13),
GPT_CGFLT_06= (4<<13),
GPT_CGFLT_08= (5<<13),
GPT_CGFLT_16= (6<<13),
GPT_CGFLT_32= (7<<13),
}GPT_CGFLT_TypeDef;
/**
* @brief GPT PSCLD register
*/
typedef enum
{
GPT_PRDLD_ZERO= (0<<16),
GPT_PRDLD_PRD= (1<<16),
GPT_PRDLD_ZERO_PRD= (2<<16),
GPT_PRDLD_NONE= (3<<16),
}GPT_PSCLD_TypeDef;
/**
* @brief GPT CAPMD register
*/
typedef enum
{
GPT_CAPMD_CONTINUOUS= (0<<20),
GPT_CAPMD_ONCE= (1<<20),
}GPT_CAPMD_TypeDef;
/**
* @brief GPT LDARST register
*/
typedef enum
{
GPT_LDARST_EN= (0<<23),
GPT_LDARST_DIS= (1<<23),
}GPT_LDARST_TypeDef;
/**
* @brief GPT LDBRST register
*/
typedef enum
{
GPT_LDBRST_EN= (0<<24),
GPT_LDBRST_DIS= (1<<24),
}GPT_LDBRST_TypeDef;
/**
* @brief GPT OPM register
*/
typedef enum
{
GPT_OPM_CONTINUOUS= (0<<6),
GPT_OPM_ONCE= (1<<6),
}GPT_OPM_TypeDef;
/**
* @brief GPT CKS register
*/
typedef enum
{
GPT_CKS_PCLK= (0<<10),
GPT_CKS_PCLKDIV2= (1<<10),
}GPT_CKS_TypeDef;
/**
* @brief GPT WAVE register
*/
typedef enum
{
GPT_CAPTURE_MODE= (0<<18),
GPT_WAVE_MODE= (1<<18),
}GPT_WAVE_TypeDef;
/**
* @brief GPT SYNCEN register
*/
typedef enum
{
GPT_SYNCUSR0_EN= (1<<0),
GPT_SYNCUSR1_EN= (1<<1),
GPT_SYNCUSR2_EN= (1<<2),
GPT_SYNCUSR3_EN= (1<<3),
GPT_SYNCUSR4_EN= (1<<4),
GPT_SYNCUSR5_EN= (1<<5)
}GPT_SYNCENX_TypeDef;
/**
* @brief GPT OSTMDX register
*/
typedef enum
{
GPT_OSTMD0_CONTINUOUS= (0<<8),
GPT_OSTMD0_ONCE= (1<<8),
GPT_OSTMD1_CONTINUOUS= (0<<9),
GPT_OSTMD1_ONCE= (1<<9),
GPT_OSTMD2_CONTINUOUS= (0<<10),
GPT_OSTMD2_ONCE= (1<<10),
GPT_OSTMD3_CONTINUOUS= (0<<11),
GPT_OSTMD3_ONCE= (1<<11),
GPT_OSTMD4_CONTINUOUS= (0<<12),
GPT_OSTMD4_ONCE= (1<<12),
GPT_OSTMD5_CONTINUOUS= (0<<13),
GPT_OSTMD5_ONCE= (1<<13),
}GPT_OSTMDX_TypeDef;
/**
* @brief GPT TXREARM0 register
*/
typedef enum
{
GPT_TXREARM_DIS= (0<<22),
GPT_TXREARM_T1= (1<<22),
GPT_TXREARM_T2= (2<<22),
GPT_TXREARM_T1_T2= (3<<22),
}GPT_TXREARM0_TypeDef;
/**
* @brief GPT TRGO0SEL register
*/
typedef enum
{
GPT_TRGO0SEL_SR0= (0<<24),
GPT_TRGO0SEL_SR1= (1<<24),
GPT_TRGO0SEL_SR2= (2<<24),
GPT_TRGO0SEL_SR3= (3<<24),
GPT_TRGO0SEL_SR4= (4<<24),
GPT_TRGO0SEL_SR5= (5<<24),
GPT_TRGO0SEL_RSVD= (6<<24),
}GPT_TRGO0SEL_TypeDef;
/**
* @brief GPT TRGO0SEL register
*/
typedef enum
{
GPT_TRG10SEL_SR0= (0<<27),
GPT_TRG10SEL_SR1= (1<<27),
GPT_TRG10SEL_SR2= (2<<27),
GPT_TRG10SEL_SR3= (3<<27),
GPT_TRG10SEL_SR4= (4<<27),
GPT_TRG10SEL_SR5= (5<<27),
GPT_TRG10SEL_RSVD= (6<<27),
}GPT_TRGO1SEL_TypeDef;
/**
* @brief GPT AREARM register
*/
typedef enum
{
GPT_AREARM_DIS= (0<<30),
GPT_AREARM_ZERO= (1<<30),
GPT_AREARM_PRD= (2<<30),
GPT_AREARM_ZERO_PRD= (3<<30),
}GPT_AREARM_TypeDef;
/**
* @brief BT INT MASK SET/CLR Set
*/
typedef enum
{
GPT_TRGEV0 = (0x01 << 0),
GPT_TRGEV1 = (0x01 << 1),
GPT_TRGEV2 = (0x01 << 2),
GPT_TRGEV3 = (0x01 << 3),
}GPT_IMSCR_TypeDef;
/**
* @brief GPT IO Set
*/
typedef enum
{
GPT_CHA_PB01 = 0,
GPT_CHA_PA09 = 1,
GPT_CHA_PA010 = 2,
GPT_CHB_PA010 = 3,
GPT_CHB_PA011 = 4,
GPT_CHB_PB00 = 5,
GPT_CHB_PB01 = 6,
}GPT_IOSET_TypeDef;
/**
* @brief CMPA SHADOW/IMMEDIATE
*/
typedef enum
{
GPT_CMPA_SHADOW = (0x00 << 0),
GPT_CMPA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWCMPA_TypeDef;
/**
* @brief CMPB SHADOW/IMMEDIATE
*/
typedef enum
{
GPT_CMPB_SHADOW = (0x00 << 1),
GPT_CMPB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWCMPB_TypeDef;
/**
* @brief CMPA LOAD MODE
*/
typedef enum
{
GPT_LoadA_ZERO = (0x01 << 4),
GPT_LoadA_PRD = (0x02 << 4),
GPT_LoadA_EXT_SYNC = (0x04 << 4),
GPT_LoadA_NONE = (0x00 << 4),
}GPT_LDAMD_TypeDef;
/**
* @brief CMPB LOAD MODE
*/
typedef enum
{
GPT_LoadB_ZERO = (0x01 << 4),
GPT_LoadB_PRD = (0x02 << 4),
GPT_LoadB_EXT_SYNC = (0x04 << 4),
GPT_LoadB_NONE = (0x00 << 4),
}GPT_LDBMD_TypeDef;
/**
* @brief WAVEA SHADOW/IMMEDIATE
*/
typedef enum
{
GPT_WAVEA_SHADOW = (0x00 << 0),
GPT_WAVEA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWAQA_TypeDef;
/**
* @brief WAVEB SHADOW/IMMEDIATE
*/
typedef enum
{
GPT_WAVEB_SHADOW = (0x00 << 1),
GPT_WAVEB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWAQB_TypeDef;
/**
* @brief ACTIVE A LOAD MODE
*/
typedef enum
{
GPT_AQLDA_ZERO = (0x01 << 2),
GPT_AQLDA_PRD = (0x02 << 2),
GPT_AQLDA_EXT_SYNC = (0x04 << 2),
GPT_AQLDA_NONE = (0x00 << 2),
}GPT_AQLDA_TypeDef;
/**
* @brief ACTIVE B LOAD MODE
*/
typedef enum
{
GPT_AQLDB_ZERO = (0x01 << 5),
GPT_AQLDB_PRD = (0x02 << 5),
GPT_AQLDB_EXT_SYNC = (0x04 << 5),
GPT_AQLDB_NONE = (0x00 << 5),
}GPT_AQLDB_TypeDef;
/**
* @brief CASEL MODE
*/
typedef enum
{
GPT_CASEL_CMPA = (0x00 << 20),
GPT_CASEL_CMPB = (0x01 << 20),
}GPT_CASEL_TypeDef;
/**
* @brief CBSEL MODE
*/
typedef enum
{
GPT_CBSEL_CMPA = (0x00 << 22),
GPT_CBSEL_CMPB = (0x01 << 22),
}GPT_CBSEL_TypeDef;
/**
* @brief CBSEL MODE
*/
typedef enum
{
GPT_CHA = 0,
GPT_CHB = 1,
}GPT_GPTCHX_TypeDef;
/**
* @brief A FORCE ENABLE
*/
typedef enum
{
GPT_CHA_FORCE_DIS = 0,
GPT_CHA_FORCE_EN = 1,
}GPT_CHAFORCE_TypeDef;
/**
* @brief B FORCE ENABLE
*/
typedef enum
{
GPT_CHB_FORCE_DIS = 0<<4,
GPT_CHB_FORCE_EN = 1<<4,
}GPT_CHBFORCE_TypeDef;
/**
* @brief FORCE LOAD
*/
typedef enum
{
GPT_FORCELD_ZERO = (0<<16),
GPT_FORCELD_PRD = (1<<16),
GPT_FORCELD__ZERO_PRD = (3<<16),
}GPT_FORCELD_TypeDef;
/**
* @brief FORCE A
*/
typedef enum
{
GPT_FORCECHA_LOW = (1<<0),
GPT_FORCECHA_HIGH = (2<<0),
}GPT_FORCEA_TypeDef;
/**
* @brief FORCE B
*/
typedef enum
{
GPT_FORCECHB_LOW = (1<<2),
GPT_FORCECHB_HIGH = (2<<2),
}GPT_FORCEB_TypeDef;
/**
* @brief GPT SRCSEL register
*/
typedef enum
{
GPT_SRCSEL_DIS= (0<<0),
GPT_SRCSEL_TRGUSR0EN= (1<<0),
GPT_SRCSEL_TRGUSR1EN= (2<<0),
GPT_SRCSEL_TRGUSR2EN= (3<<0),
GPT_SRCSEL_TRGUSR3EN= (4<<0),
GPT_SRCSEL_TRGUSR4EN= (5<<0),
GPT_SRCSEL_TRGUSR5EN= (6<<0)
}GPT_SRCSEL_TypeDef;
/**
* @brief GPT BLKINV register
*/
typedef enum
{
GPT_BLKINV_DIS= (0<<4),
GPT_BLKINV_EN= (1<<4),
}GPT_BLKINV_TypeDef;
/**
* @brief GPT CROSSMD register
*/
typedef enum
{
GPT_ALIGNMD_PRD= (0<<5),
GPT_ALIGNMD_ZRO= (1<<5),
GPT_ALIGNMD_PRD_ZRO= (2<<5),
GPT_ALIGNMD_T1= (3<<5),
}GPT_ALIGNMD_TypeDef;
/**
* @brief GPT CROSSMD register
*/
typedef enum
{
GPT_CROSSMD_DIS= (0<<7),
GPT_CROSSMD_EN= (1<<7),
}GPT_CROSSMD_TypeDef;
/**
* @brief GPT TRGSRC0 register
*/
typedef enum
{
GPT_TRGSRC0_DIS= (0<<0),
GPT_TRGSRC0_ZRO= (1<<0),
GPT_TRGSRC0_PRD= (2<<0),
GPT_TRGSRC0_ZRO_PRD= (3<<0),
GPT_TRGSRC0_CMPA_INC= (4<<0),
GPT_TRGSRC0_CMPA_DEC= (5<<0),
GPT_TRGSRC0_CMPB_INC= (6<<0),
GPT_TRGSRC0_CMPB_DEC= (7<<0),
GPT_TRGSRC0_EXTSYNC= (0X0C<<0),
GPT_TRGSRC0_PE0= (0X0D<<0),
GPT_TRGSRC0_PE1= (0X0E<<0),
GPT_TRGSRC0_PE2= (0X0F<<0),
}GPT_TRGSRC0_TypeDef;
/**
* @brief GPT TRGSRC1 register
*/
typedef enum
{
GPT_TRGSRC1_DIS= (0<<4),
GPT_TRGSRC1_ZRO= (1<<4),
GPT_TRGSRC1_PRD= (2<<4),
GPT_TRGSRC1_ZRO_PRD= (3<<4),
GPT_TRGSRC1_CMPA_INC= (4<<4),
GPT_TRGSRC1_CMPA_DEC= (5<<4),
GPT_TRGSRC1_CMPB_INC= (6<<4),
GPT_TRGSRC1_CMPB_DEC= (7<<4),
GPT_TRGSRC1_EXTSYNC= (0X0C<<4),
GPT_TRGSRC1_PE0= (0X0D<<4),
GPT_TRGSRC1_PE1= (0X0E<<4),
GPT_TRGSRC1_PE2= (0X0F<<4),
}GPT_TRGSRC1_TypeDef;
/**
* @brief GPT CNT0INITEN register
*/
typedef enum
{
GPT_CNT0INIT_DIS= (0<<16),
GPT_CNT0INIT_EN= (1<<16),
}GPT_CNT0INIT_TypeDef;
/**
* @brief GPT CNT1INITEN register
*/
typedef enum
{
GPT_CNT1INIT_DIS= (0<<17),
GPT_CNT1INIT_EN= (1<<17),
}GPT_CNT1INIT_TypeDef;
/**
* @brief GPT ESYN0OE register
*/
typedef enum
{
GPT_ESYN0OE_DIS= (0<<20),
GPT_ESYN0OE_EN= (1<<20),
}GPT_ESYN0OE_TypeDef;
/**
* @brief GPT ESYN1OE register
*/
typedef enum
{
GPT_ESYN1OE_DIS= (0<<21),
GPT_ESYN1OE_EN= (1<<21),
}GPT_ESYN1OE_TypeDef;
/**
* @brief GPT CNTMD selected
*/
typedef enum
{
GPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
GPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
GPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}GPT_CNTMD_SELECTE_Type;
/**
* @brief GPT CAPMD selected
*/
typedef enum
{
GPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
GPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}GPT_CAPMD_SELECTE_Type;
/**
* @brief GPT CMPC RST CMD
*/
typedef enum
{
GPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
GPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}GPT_LOAD_CMPC_RST_CMD_Type;
/**
* @brief GPT CMPD RST CMD
*/
typedef enum
{
GPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
GPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}GPT_LOAD_CMPD_RST_CMD_Type;
#define CH_ZRO_NONE (0X00)
#define CH_ZRO_LOW (0X01)
#define CH_ZRO_HIGH (0X02)
#define CH_ZRO_REVS (0X03)
#define CH_PRD_NONE (0X00)
#define CH_PRD_LOW (0X01)
#define CH_PRD_HIGH (0X02)
#define CH_PRD_REVS (0X03)
#define CH_CAU_NONE (0X00)
#define CH_CAU_LOW (0X01)
#define CH_CAU_HIGH (0X02)
#define CH_CAU_REVS (0X03)
#define CH_CAD_NONE (0X00)
#define CH_CAD_LOW (0X01)
#define CH_CAD_HIGH (0X02)
#define CH_CAD_REVS (0X03)
#define CH_CBU_NONE (0X00)
#define CH_CBU_LOW (0X01)
#define CH_CBU_HIGH (0X02)
#define CH_CBU_REVS (0X03)
#define CH_CBD_NONE (0X00)
#define CH_CBD_LOW (0X01)
#define CH_CBD_HIGH (0X02)
#define CH_CBD_REVS (0X03)
#define CH_T1U_NONE (0X00)
#define CH_T1U_LOW (0X01)
#define CH_T1U_HIGH (0X02)
#define CH_T1U_REVS (0X03)
#define CH_T1D_NONE (0X00)
#define CH_T1D_LOW (0X01)
#define CH_T1D_HIGH (0X02)
#define CH_T1D_REVS (0X03)
#define CH_T2U_NONE (0X00)
#define CH_T2U_LOW (0X01)
#define CH_T2U_HIGH (0X02)
#define CH_T2U_REVS (0X03)
#define CH_T2D_NONE (0X00)
#define CH_T2D_LOW (0X01)
#define CH_T2D_HIGH (0X02)
#define CH_T2D_REVS (0X03)
#define FORCE_ACT_NONE 0
#define FORCE_ACT_LOW 1
#define FORCE_ACT_HIGH 2
#define FORCE_ACT_REVS 3
#define GPT_INT_TRGEV0 (0X01)
#define GPT_INT_TRGEV1 (0X01<<1)
#define GPT_INT_TRGEV2 (0X01<<2)
#define GPT_INT_TRGEV3 (0X01<<3)
#define GPT_INT_CAPLD0 (0X01<<4)
#define GPT_INT_CAPLD1 (0X01<<5)
#define GPT_INT_CAPLD2 (0X01<<6)
#define GPT_INT_CAPLD3 (0X01<<7)
#define GPT_INT_CAU (0X01<<8)
#define GPT_INT_CAD (0X01<<9)
#define GPT_INT_CBU (0X01<<10)
#define GPT_INT_CBD (0X01<<11)
#define GPT_INT_PEND (0X01<<16)
#define GPT_SYNCUSR0 (0X01)
#define GPT_SYNCUSR1 (0X01<<1)
#define GPT_SYNCUSR2 (0X01<<2)
#define GPT_SYNCUSR3 (0X01<<3)
#define GPT_SYNCUSR4 (0X01<<4)
#define GPT_SYNCUSR5 (0X01<<5)
#define GPT_DEBUG_MODE (0x01<<1)
extern void GPT_DeInit(void);
extern void GPT_IO_Init(GPT_IOSET_TypeDef IONAME);
extern void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX);
extern void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX);
extern void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX);
extern void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX);
extern void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX);
extern void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX);
extern void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX);
extern void GPT_Debug_Mode(FunctionalStatus NewState);
extern void GPT_Start(void);
extern void GPT_Stop(void);
extern void GPT_Soft_Reset(void);
extern void GPT_Cap_Rearm(void);
extern void GPT_REARM_Write(void);
extern U8_T GPT_REARM_Read(void);
extern void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA);
extern U16_T GPT_PRDR_Read(void);
extern U16_T GPT_CMPA_Read(void);
extern U16_T GPT_CMPB_Read(void);
extern U16_T GPT_CNT_Read(void);
extern void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X);
extern void GPT_INT_ENABLE(void);
extern void GPT_INT_DISABLE(void);
extern void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx);
extern void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA);
extern void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt);
extern void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
, GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP );
/*************************************************************/
#endif /**< apt32f102_gpt_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_hwdiv.h
* @author APT AE Team
* @version V1.02
* @date 2019/04/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_hwdiv_H
#define _apt32f102_hwdiv_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define HWDIV_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------HWDIV value enum define--------------------------
//--------------------------------------------------------------------------------
#define HWDIV_UNSIGN_BIT (0X01<<0)
extern U32_T HWDIV_Calc_Remain(void);
extern U32_T HWDIV_Calc_Quotient(void);
extern void HWDIV_Calc_UNSIGN(U32_T DIVIDENDx,U32_T DIVISOR_x);
extern void HWDIV_UNSIGN_CMD(FunctionalStatus NewState);
extern void HWDIV_DeInit(void);
extern void HWDIV_Calc_SIGN(long DIVIDENDx,long DIVISOR_x);
extern void HWDIV_Calc_float(float DIVIDENDx,float DIVISOR_x);
#endif /**< apt32f102_hwdiv_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_i2c.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_i2c_H
#define _apt32f102_i2c_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define BUFSIZE 32
/******************************************************************************
************************** I2C Structure Definition ***************************
******************************************************************************/
/**
*******************************************************************************
@brief description CSP_I2C_T and CSP_I2C_PTR
*******************************************************************************
*/
/******************************************************************************
************************** I2C Registers Definition ***************************
******************************************************************************/
/******************************************************************************
* CR : I2C Control Register
******************************************************************************/
#define I2C_MASTER_EN (0x01ul << 0) /**< I2C Master Mode */
#define I2C_MASTER_DIS (0x00ul << 0) /**< I2C Master Mode */
#define I2C_SS (0x01ul << 1) /**< I2C Standard Speed Mode */
#define I2C_FS (0x02ul << 1) /**< I2C Fast Speed Mode */
#define I2C_HS (0x03ul << 1) /**< I2C High Speed Mode */
#define I2C_10BIT_SLAVE (0x01ul << 3) /**< I2C 10bit or 7bit in Slave */
#define I2C_7BIT_SLAVE (0x00ul << 3) /**< I2C 10bit or 7bit in Slave */
#define I2C_10BIT_MASTER (0x01ul << 4) /**< I2C 10bit or 7bit in Master */
#define I2C_7BIT_MASTER (0x00ul << 4) /**< I2C 10bit or 7bit in Master */
#define I2C_RESTART_EN (0x01ul << 5) /**< I2C Restart Enable */
#define I2C_RESTART_DIS (0x00ul << 5) /**< I2C Restart Disable */
#define I2C_SLAVE_EN (0x00ul << 6) /**< I2C Slave Enable */
#define I2C_SLAVE_DIS (0x01ul << 6) /**< I2C Slave Disable */
#define I2C_STOPDET_IFADD (0x01ul << 7) /**< I2C STOPDET If Addressed */
#define I2C_STOPDET_ALS (0x00ul << 7) /**< I2C STOPDET Always */
#define I2C_TX_EMPTY_CTRL (0x01ul << 8) /**< I2C TX_EMPTY Control */
#define I2C_TX_EMPTY_DONE (0x00ul << 8) /**< I2C TX_EMPTY and Send Done */
#define I2C_RX_HOLD_CTRL (0x01ul << 9) /**< I2C Rx Hold Ctrl @FIFO Full */
#define I2C_RX_HOLD_NONE (0x00ul << 9) /**< I2C Rx Hold None @FIFO Full */
#define I2C_STOPDET_MM (0x01ul <<10) /**< I2C STOPDET only in Master */
#define I2C_BUSCLR_EN (0x01ul <<11) /**< I2C Enable Bus Clear Feature*/
#define I2C_BUSCLR_DIS (0x00ul <<11) /**< I2C Disable Bus Clear Feature*/
/******************************************************************************
* DATA_CMD : I2C Data and Command Register
******************************************************************************/
#define I2C_CMD_READ (0x01ul << 8) /**< I2C Read Command */
#define I2C_CMD_WRITE (0x00ul << 8) /**< I2C Write Command */
#define I2C_CMD_STOP (0x01ul << 9) /**< I2C Stop after this byte */
#define I2C_CMD_NONESTOP (0x00ul << 9) /**< I2C None Stop When FIFO Empty or Not */
#define I2C_CMD_RESTART0 (0x00ul <<10) /**< I2C Restart Mode0 */
#define I2C_CMD_RESTART1 (0x01ul <<10) /**< I2C Restart Mode1 */
//#define I2C_CMD_1stDATA (0x01ul <<11) /**< I2C First Data Byte */
#define I2C_DATA(val) (((val) & 0xFFul) << 0) /**< Data Writing Macro */
/*****************************************************************************
* ENABLE : I2C Enable Register
******************************************************************************/
#define I2C_ENABLE (0x01ul << 0) /**< I2C Enable */
#define I2C_DISABLE (0x00ul << 0) /**< I2C Enable */
#define I2C_ABORT (0x01ul << 1) /**< I2C Abort Transfer */
#define I2C_ABORT_OV (0x00ul << 1) /**< I2C Abort Transfer Over or No Abort */
//#define I2C_TX_CMD_BLOCK (0x01ul << 2) /**< I2C Block Transmission */
#define I2C_SDA_REC_EN (0x01ul << 3) /**< I2C Enable Stuck Recovery */
#define I2C_SDA_REC_DIS (0x00ul << 3) /**< I2C Enable Stuck Recovery */
/*****************************************************************************
* STATUS : I2C STATUS Register
******************************************************************************/
#define I2C_BUSY (0x01ul << 0) /**< I2C Activity */
#define I2C_FREE (0x00ul << 0) /**< I2C Activity */
#define I2C_TFNF (0x01ul << 1) /**< I2C Transmit FIFO Not Full */
#define I2C_TFNF_FULL (0x00ul << 1) /**< I2C Transmit FIFO Is Full */
#define I2C_TFE (0x01ul << 2) /**< I2C Transmit FIFO Empty */
#define I2C_TFE_NOT (0x00ul << 2) /**< I2C Transmit FIFO Not Empty */
#define I2C_RFNE (0x01ul << 3) /**< I2C Receive FIFO Not Empty */
#define I2C_RFNE_EMPTY (0x00ul << 3) /**< I2C Receive FIFO Is Empty */
#define I2C_RFF (0x01ul << 4) /**< I2C Receive FIFO Full */
#define I2C_MST_BUSY (0x01ul << 5) /**< I2C Master FSM Activity */
#define I2C_MST_FREE (0x00ul << 5) /**< I2C Master FSM Free */
#define I2C_SLV_BUSY (0x01ul << 6) /**< I2C Slave FSM Activity */
#define I2C_SLV_FREE (0x01ul << 6) /**< I2C Slave FSM Free */
#define I2C_REC_FREE (0x00ul << 6) /**< I2C Recovery No FAIL */
#define I2C_REC_FAIL (0x01ul << 11) /**< I2C Recovery FAIL */
/*****************************************************************************
* RISR/MISR/IMSCR/ICR : I2C Interrupt Mask/Status Register
******************************************************************************/
#define I2C_RX_UNDER (0x01ul << 0) /**< I2C Interrupt Status */
#define I2C_RX_OVER (0x01ul << 1) /**< I2C Interrupt Status */
#define I2C_RX_FULL (0x01ul << 2) /**< I2C Interrupt Status */
#define I2C_TX_OVER (0x01ul << 3) /**< I2C Interrupt Status */
#define I2C_TX_EMPTY (0x01ul << 4) /**< I2C Interrupt Status */
#define I2C_RD_REQ (0x01ul << 5) /**< I2C Interrupt Status */
#define I2C_TX_ABRT (0x01ul << 6) /**< I2C Interrupt Status */
#define I2C_RX_DONE (0x01ul << 7) /**< I2C Interrupt Status */
#define I2C_INT_BUSY (0x01ul << 8) /**< I2C Interrupt Status */
#define I2C_STOP_DET (0x01ul << 9) /**< I2C Interrupt Status */
#define I2C_START_DET (0x01ul <<10) /**< I2C Interrupt Status */
#define I2C_GEN_CALL (0x01ul <<11) /**< I2C Interrupt Status */
#define I2C_RESTART_DET (0x01ul <<12) /**< I2C Interrupt Status */
#define I2C_MST_ON_HOLD (0x01ul <<13) /**< I2C Interrupt Status */
#define I2C_SCL_SLOW (0x01ul <<14) /**< I2C Interrupt Status */
/*****************************************************************************
* SDA_HOLD/SETUP : I2C SDA hold/setup Timing Register
******************************************************************************/
#define I2C_TX_HOLD(val) (((val) & 0xFFul) << 0) /**< SDA TX Hold Delay */
#define I2C_RX_HOLD(val) (((val) & 0xFFul) <<16) /**< SDA RX Hold Delay */
#define I2C_SETUP(val) (((val) & 0xFFul) << 0) /**< SDA Setup Delay */
/*****************************************************************************
* I2C_SPKLEN : I2C Burr Interference Filter Control Register
******************************************************************************/
#define I2C_SPKLEN(val) (((val) & 0xFFul) << 0) /**<I2C Burr interference filter control register */
/*****************************************************************************
* SCL/SDA TOUT : I2C SCL/SDA Stuck Time Out
******************************************************************************/
#define I2C_SCL_TOUT(val) (((val) & 0xFFFFFFFFul) << 0) /**<I2C SCL Stuck Time Out */
#define I2C_SDA_TOUT(val) (((val) & 0xFFFFFFFFul) << 0) /**<I2C SDA Stuck Time Out */
/*****************************************************************************
* GCALL : I2C General Call Register
******************************************************************************/
#define I2C_GCALL_EN (0x01ul << 0) /**< I2C uses ACK to answer General Call */
#define I2C_GCALL_DIS (0x00ul << 0) /**< I2C does not generate a General Call interrupt */
/*****************************************************************************
* NACK : I2C Slave NACK Control Register
******************************************************************************/
#define I2C_NACK_DATA (0x01ul << 0) /**< I2C Generate a NACK after the data byte is received */
#define I2C_NACK_NORMAL (0x00ul << 0) /**< I2C Generate NACK/ACK as normal */
/**
* @brief I2C IO selection
*/
typedef enum
{
I2C_SDA_PA00= 0,
I2C_SDA_PA03 = 1,
I2C_SDA_PA07= 2,
I2C_SDA_PA013= 3,
I2C_SDA_PA014 = 4,
}I2C_SDA_TypeDef;
/**
* @brief I2C IO selection
*/
typedef enum
{
I2C_SCL_PB00 = 0,
I2C_SCL_PB02 = 1,
I2C_SCL_PA01 = 2,
I2C_SCL_PA04 = 3,
I2C_SCL_PA06 = 4,
I2C_SCL_PA015 = 5,
}I2C_SCL_TypeDef;
/**
* @brief I2C MODE
*/
typedef enum
{
STANDARD_MODE = (0x01ul << 1),
FAST_MODE=(0x02ul << 1),
}I2C_SPEEDMODE_TypeDef;
/**
* @brief I2C SLAVE BIT
*/
typedef enum
{
I2C_SLAVE_7BIT= (0x00ul << 3),
I2C_SLAVE_10BIT=(0x01ul << 3),
}I2C_SLAVEBITS_TypeDef;
/**
* @brief I2C MASTER BITS
*/
typedef enum
{
I2C_MASTRER_7BIT= (0x00ul << 4),
I2C_MASTRER_10BIT=(0x01ul << 4),
}I2C_MASTRERBITS_TypeDef;
/******************************************************************************
********************* I2C External Functions Declaration **********************
******************************************************************************/
extern void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADD,U16_T SS_SCLH,U16_T SS_SCLL);
extern void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX);
extern void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD);
extern void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE);
extern void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL);
extern void I2C_Stop(void);
extern void I2C_Enable(void);
extern void I2C_Disable(void);
extern void I2C_Abort_EN(void);
extern U8_T I2C_Abort_Status(void);
extern void I2C_SDA_Recover_EN(void);
extern void I2C_SDA_Recover_DIS(void);
extern void I2C_Int_Enable(void);
extern void I2C_Int_Disable(void);
extern void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data);
extern void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern U8_T I2C_READ_Byte(U8_T read_adds);
extern void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern void I2C_Slave_Receive(void);
extern void I2C_DeInit(void);
extern volatile uint8_t I2CWrBuffer[BUFSIZE];
extern volatile uint8_t I2CRdBuffer[BUFSIZE];
extern volatile U8_T f_ERROR;
extern void I2C_SLAVE_CONFIG(void);
#endif /**< apt32f102_i2c_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_ifc.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_ifc_H
#define _apt32f102_ifc_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************ ifc Registers Definition *************************
******************************************************************************/
#define IFC_CLK_EN (0x01ul)
#define IFC_CLK_DIS (0xfeul)
#define EnIFCClk (IFC->CEDR = (IFC_CLK_EN))
#define DisIFCClk (IFC->CEDR = (IFC_CLK_DIS))
#define USER_KEY (0x5A5A5A5Aul)
#define SetUserKey (IFC->KR = (USER_KEY))
#define StartOp (0x01ul)
#define IFC_CLKEN (0x01ul) //IFC CLKEN
#define IFC_SWRST (0x01ul) //IFC SWRST
#define HIDM0 ((0x0ul)<<8) //HID0
#define HIDM1 ((0x1ul)<<8) //HID1
#define HIDM2 ((0x2ul)<<8) //HID2
#define HIDM3 ((0x3ul)<<8) //HID3
// IFC Command
#define PROGRAM (0x01ul)
#define PAGE_ERASE (0x02ul)
#define CHIP_ERASE (0x04ul)
#define OPTION_ERASE (0x05ul)
#define PEP_ENABLE (0x06ul) //预编程设定
#define PAGE_BUF_CLR (0x07ul) //页缓存清除
#define DIS_SWD_SET (0x0Dul) //SWD 禁止重映射
#define EN_SWD_SET (0x0Eul) //SWD 使能重映射
#define USER_OPTION (0x0Ful) //User OPTION操作
#define USER_KEY (0x5A5A5A5Aul)
#define CSP_IFC_SET_KR(ifc, val) (ifc->KR = (val))
//
#define StartErase (IFC->CR=(StartOp))
#define EnChipErase (IFC->CMR=(CHIP_ERASE|HIDM1))
#define EnPageErase (IFC->CMR=(PAGE_ERASE|HIDM0))
/**
* @brief IFC page address
*/
typedef enum
{
PROM_PageAdd0 = ((CSP_REGISTER_T)0x00000000), //PROM 每页256BYTE
PROM_PageAdd1 = ((CSP_REGISTER_T)0x00000100),
PROM_PageAdd2 = ((CSP_REGISTER_T)0x00000200),
PROM_PageAdd3 = ((CSP_REGISTER_T)0x00000300),
PROM_PageAdd4 = ((CSP_REGISTER_T)0x00000400),
PROM_PageAdd5 = ((CSP_REGISTER_T)0x00000500),
PROM_PageAdd6 = ((CSP_REGISTER_T)0x00000600),
PROM_PageAdd7 = ((CSP_REGISTER_T)0x00000700),
PROM_PageAdd8 = ((CSP_REGISTER_T)0x00000800),
PROM_PageAdd9 = ((CSP_REGISTER_T)0x00000900),
PROM_PageAdd10 = ((CSP_REGISTER_T)0x00000A00),
PROM_PageAdd11 = ((CSP_REGISTER_T)0x00000B00),
PROM_PageAdd12 = ((CSP_REGISTER_T)0x00000C00),
PROM_PageAdd13 = ((CSP_REGISTER_T)0x00000D00),
PROM_PageAdd14 = ((CSP_REGISTER_T)0x00000E00),
PROM_PageAdd15 = ((CSP_REGISTER_T)0x00000F00),
PROM_PageAdd16 = ((CSP_REGISTER_T)0x00001000),
PROM_PageAdd17 = ((CSP_REGISTER_T)0x00001100),
PROM_PageAdd18 = ((CSP_REGISTER_T)0x00001200),
PROM_PageAdd19 = ((CSP_REGISTER_T)0x00001300),
PROM_PageAdd20 = ((CSP_REGISTER_T)0x00001400),
PROM_PageAdd21 = ((CSP_REGISTER_T)0x00001500),
PROM_PageAdd22 = ((CSP_REGISTER_T)0x00001600),
PROM_PageAdd23 = ((CSP_REGISTER_T)0x00001700),
PROM_PageAdd24 = ((CSP_REGISTER_T)0x00001800),
PROM_PageAdd25 = ((CSP_REGISTER_T)0x00001900),
PROM_PageAdd26 = ((CSP_REGISTER_T)0x00001A00),
PROM_PageAdd27 = ((CSP_REGISTER_T)0x00001B00),
PROM_PageAdd28 = ((CSP_REGISTER_T)0x00001C00),
PROM_PageAdd29 = ((CSP_REGISTER_T)0x00001D00),
PROM_PageAdd30 = ((CSP_REGISTER_T)0x00001E00),
PROM_PageAdd31 = ((CSP_REGISTER_T)0x00001F00),
PROM_PageAdd32 = ((CSP_REGISTER_T)0x00002000),
PROM_PageAdd33 = ((CSP_REGISTER_T)0x00002100),
PROM_PageAdd34 = ((CSP_REGISTER_T)0x00002200),
PROM_PageAdd35 = ((CSP_REGISTER_T)0x00002300),
PROM_PageAdd36 = ((CSP_REGISTER_T)0x00002400),
PROM_PageAdd37 = ((CSP_REGISTER_T)0x00002500),
PROM_PageAdd38 = ((CSP_REGISTER_T)0x00002600),
PROM_PageAdd39 = ((CSP_REGISTER_T)0x00002700),
PROM_PageAdd40 = ((CSP_REGISTER_T)0x00002800),
PROM_PageAdd41 = ((CSP_REGISTER_T)0x00002900),
PROM_PageAdd42 = ((CSP_REGISTER_T)0x00002A00),
PROM_PageAdd43 = ((CSP_REGISTER_T)0x00002B00),
PROM_PageAdd44 = ((CSP_REGISTER_T)0x00002C00),
PROM_PageAdd45 = ((CSP_REGISTER_T)0x00002D00),
PROM_PageAdd46 = ((CSP_REGISTER_T)0x00002E00),
PROM_PageAdd47 = ((CSP_REGISTER_T)0x00002F00),
PROM_PageAdd48 = ((CSP_REGISTER_T)0x00003000),
PROM_PageAdd49 = ((CSP_REGISTER_T)0x00003100),
PROM_PageAdd50 = ((CSP_REGISTER_T)0x00003200),
PROM_PageAdd51 = ((CSP_REGISTER_T)0x00003300),
PROM_PageAdd52 = ((CSP_REGISTER_T)0x00003400),
PROM_PageAdd53 = ((CSP_REGISTER_T)0x00003500),
PROM_PageAdd54 = ((CSP_REGISTER_T)0x00003600),
PROM_PageAdd55 = ((CSP_REGISTER_T)0x00003700),
PROM_PageAdd56 = ((CSP_REGISTER_T)0x00003800),
PROM_PageAdd57 = ((CSP_REGISTER_T)0x00003900),
PROM_PageAdd58 = ((CSP_REGISTER_T)0x00003A00),
PROM_PageAdd59 = ((CSP_REGISTER_T)0x00003B00),
PROM_PageAdd60 = ((CSP_REGISTER_T)0x00003C00),
PROM_PageAdd61 = ((CSP_REGISTER_T)0x00003D00),
PROM_PageAdd62 = ((CSP_REGISTER_T)0x00003E00),
PROM_PageAdd63 = ((CSP_REGISTER_T)0x00003F00),
PROM_PageAdd64 = ((CSP_REGISTER_T)0x00004000),
PROM_PageAdd65 = ((CSP_REGISTER_T)0x00004100),
PROM_PageAdd66 = ((CSP_REGISTER_T)0x00004200),
PROM_PageAdd67 = ((CSP_REGISTER_T)0x00004300),
PROM_PageAdd68 = ((CSP_REGISTER_T)0x00004400),
PROM_PageAdd69 = ((CSP_REGISTER_T)0x00004500),
PROM_PageAdd70 = ((CSP_REGISTER_T)0x00004600),
PROM_PageAdd71 = ((CSP_REGISTER_T)0x00004700),
PROM_PageAdd72 = ((CSP_REGISTER_T)0x00004800),
PROM_PageAdd73 = ((CSP_REGISTER_T)0x00004900),
PROM_PageAdd74 = ((CSP_REGISTER_T)0x00004A00),
PROM_PageAdd75 = ((CSP_REGISTER_T)0x00004B00),
PROM_PageAdd76 = ((CSP_REGISTER_T)0x00004C00),
PROM_PageAdd77 = ((CSP_REGISTER_T)0x00004D00),
PROM_PageAdd78 = ((CSP_REGISTER_T)0x00004E00),
PROM_PageAdd79 = ((CSP_REGISTER_T)0x00004F00),
PROM_PageAdd80 = ((CSP_REGISTER_T)0x00005000),
PROM_PageAdd81 = ((CSP_REGISTER_T)0x00005100),
PROM_PageAdd82 = ((CSP_REGISTER_T)0x00005200),
PROM_PageAdd83 = ((CSP_REGISTER_T)0x00005300),
PROM_PageAdd84 = ((CSP_REGISTER_T)0x00005400),
PROM_PageAdd85 = ((CSP_REGISTER_T)0x00005500),
PROM_PageAdd86 = ((CSP_REGISTER_T)0x00005600),
PROM_PageAdd87 = ((CSP_REGISTER_T)0x00005700),
PROM_PageAdd88 = ((CSP_REGISTER_T)0x00005800),
PROM_PageAdd89 = ((CSP_REGISTER_T)0x00005900),
PROM_PageAdd90 = ((CSP_REGISTER_T)0x00005A00),
PROM_PageAdd91 = ((CSP_REGISTER_T)0x00005B00),
PROM_PageAdd92 = ((CSP_REGISTER_T)0x00005C00),
PROM_PageAdd93 = ((CSP_REGISTER_T)0x00005D00),
PROM_PageAdd94 = ((CSP_REGISTER_T)0x00005E00),
PROM_PageAdd95 = ((CSP_REGISTER_T)0x00005F00),
PROM_PageAdd96 = ((CSP_REGISTER_T)0x00006000),
PROM_PageAdd97 = ((CSP_REGISTER_T)0x00006100),
PROM_PageAdd98 = ((CSP_REGISTER_T)0x00006200),
PROM_PageAdd99 = ((CSP_REGISTER_T)0x00006300),
PROM_PageAdd100 = ((CSP_REGISTER_T)0x00006400),
PROM_PageAdd101 = ((CSP_REGISTER_T)0x00006500),
PROM_PageAdd102 = ((CSP_REGISTER_T)0x00006600),
PROM_PageAdd103 = ((CSP_REGISTER_T)0x00006700),
PROM_PageAdd104 = ((CSP_REGISTER_T)0x00006800),
PROM_PageAdd105 = ((CSP_REGISTER_T)0x00006900),
PROM_PageAdd106 = ((CSP_REGISTER_T)0x00006A00),
PROM_PageAdd107 = ((CSP_REGISTER_T)0x00006B00),
PROM_PageAdd108 = ((CSP_REGISTER_T)0x00006C00),
PROM_PageAdd109 = ((CSP_REGISTER_T)0x00006D00),
PROM_PageAdd110 = ((CSP_REGISTER_T)0x00006E00),
PROM_PageAdd111 = ((CSP_REGISTER_T)0x00006F00),
PROM_PageAdd112 = ((CSP_REGISTER_T)0x00007000),
PROM_PageAdd113 = ((CSP_REGISTER_T)0x00007100),
PROM_PageAdd114 = ((CSP_REGISTER_T)0x00007200),
PROM_PageAdd115 = ((CSP_REGISTER_T)0x00007300),
PROM_PageAdd116 = ((CSP_REGISTER_T)0x00007400),
PROM_PageAdd117 = ((CSP_REGISTER_T)0x00007500),
PROM_PageAdd118 = ((CSP_REGISTER_T)0x00007600),
PROM_PageAdd119 = ((CSP_REGISTER_T)0x00007700),
PROM_PageAdd120 = ((CSP_REGISTER_T)0x00007800),
PROM_PageAdd121 = ((CSP_REGISTER_T)0x00007900),
PROM_PageAdd122 = ((CSP_REGISTER_T)0x00007A00),
PROM_PageAdd123 = ((CSP_REGISTER_T)0x00007B00),
PROM_PageAdd124 = ((CSP_REGISTER_T)0x00007C00),
PROM_PageAdd125 = ((CSP_REGISTER_T)0x00007D00),
PROM_PageAdd126 = ((CSP_REGISTER_T)0x00007E00),
PROM_PageAdd127 = ((CSP_REGISTER_T)0x00007F00),
PROM_PageAdd128 = ((CSP_REGISTER_T)0x00008000),
PROM_PageAdd129 = ((CSP_REGISTER_T)0x00008100),
PROM_PageAdd130 = ((CSP_REGISTER_T)0x00008200),
PROM_PageAdd131 = ((CSP_REGISTER_T)0x00008300),
PROM_PageAdd132 = ((CSP_REGISTER_T)0x00008400),
PROM_PageAdd133 = ((CSP_REGISTER_T)0x00008500),
PROM_PageAdd134 = ((CSP_REGISTER_T)0x00008600),
PROM_PageAdd135 = ((CSP_REGISTER_T)0x00008700),
PROM_PageAdd136 = ((CSP_REGISTER_T)0x00008800),
PROM_PageAdd137 = ((CSP_REGISTER_T)0x00008900),
PROM_PageAdd138 = ((CSP_REGISTER_T)0x00008A00),
PROM_PageAdd139 = ((CSP_REGISTER_T)0x00008B00),
PROM_PageAdd140 = ((CSP_REGISTER_T)0x00008C00),
PROM_PageAdd141 = ((CSP_REGISTER_T)0x00008D00),
PROM_PageAdd142 = ((CSP_REGISTER_T)0x00008E00),
PROM_PageAdd143 = ((CSP_REGISTER_T)0x00008F00),
PROM_PageAdd144 = ((CSP_REGISTER_T)0x00009000),
PROM_PageAdd145 = ((CSP_REGISTER_T)0x00009100),
PROM_PageAdd146 = ((CSP_REGISTER_T)0x00009200),
PROM_PageAdd147 = ((CSP_REGISTER_T)0x00009300),
PROM_PageAdd148 = ((CSP_REGISTER_T)0x00009400),
PROM_PageAdd149 = ((CSP_REGISTER_T)0x00009500),
PROM_PageAdd150 = ((CSP_REGISTER_T)0x00009600),
PROM_PageAdd151 = ((CSP_REGISTER_T)0x00009700),
PROM_PageAdd152 = ((CSP_REGISTER_T)0x00009800),
PROM_PageAdd153 = ((CSP_REGISTER_T)0x00009900),
PROM_PageAdd154 = ((CSP_REGISTER_T)0x00009A00),
PROM_PageAdd155 = ((CSP_REGISTER_T)0x00009B00),
PROM_PageAdd156 = ((CSP_REGISTER_T)0x00009C00),
PROM_PageAdd157 = ((CSP_REGISTER_T)0x00009D00),
PROM_PageAdd158 = ((CSP_REGISTER_T)0x00009E00),
PROM_PageAdd159 = ((CSP_REGISTER_T)0x00009F00),
PROM_PageAdd160 = ((CSP_REGISTER_T)0x0000A000),
PROM_PageAdd161 = ((CSP_REGISTER_T)0x0000A100),
PROM_PageAdd162 = ((CSP_REGISTER_T)0x0000A200),
PROM_PageAdd163 = ((CSP_REGISTER_T)0x0000A300),
PROM_PageAdd164 = ((CSP_REGISTER_T)0x0000A400),
PROM_PageAdd165 = ((CSP_REGISTER_T)0x0000A500),
PROM_PageAdd166 = ((CSP_REGISTER_T)0x0000A600),
PROM_PageAdd167 = ((CSP_REGISTER_T)0x0000A700),
PROM_PageAdd168 = ((CSP_REGISTER_T)0x0000A800),
PROM_PageAdd169 = ((CSP_REGISTER_T)0x0000A900),
PROM_PageAdd170 = ((CSP_REGISTER_T)0x0000AA00),
PROM_PageAdd171 = ((CSP_REGISTER_T)0x0000AB00),
PROM_PageAdd172 = ((CSP_REGISTER_T)0x0000AC00),
PROM_PageAdd173 = ((CSP_REGISTER_T)0x0000AD00),
PROM_PageAdd174 = ((CSP_REGISTER_T)0x0000AE00),
PROM_PageAdd175 = ((CSP_REGISTER_T)0x0000AF00),
PROM_PageAdd176 = ((CSP_REGISTER_T)0x0000B000),
PROM_PageAdd177 = ((CSP_REGISTER_T)0x0000B100),
PROM_PageAdd178 = ((CSP_REGISTER_T)0x0000B200),
PROM_PageAdd179 = ((CSP_REGISTER_T)0x0000B300),
PROM_PageAdd180 = ((CSP_REGISTER_T)0x0000B400),
PROM_PageAdd181 = ((CSP_REGISTER_T)0x0000B500),
PROM_PageAdd182 = ((CSP_REGISTER_T)0x0000B600),
PROM_PageAdd183 = ((CSP_REGISTER_T)0x0000B700),
PROM_PageAdd184 = ((CSP_REGISTER_T)0x0000B800),
PROM_PageAdd185 = ((CSP_REGISTER_T)0x0000B900),
PROM_PageAdd186 = ((CSP_REGISTER_T)0x0000BA00),
PROM_PageAdd187 = ((CSP_REGISTER_T)0x0000BB00),
PROM_PageAdd188 = ((CSP_REGISTER_T)0x0000BC00),
PROM_PageAdd189 = ((CSP_REGISTER_T)0x0000BD00),
PROM_PageAdd190 = ((CSP_REGISTER_T)0x0000BE00),
PROM_PageAdd191 = ((CSP_REGISTER_T)0x0000BF00),
PROM_PageAdd192 = ((CSP_REGISTER_T)0x0000C000),
PROM_PageAdd193 = ((CSP_REGISTER_T)0x0000C100),
PROM_PageAdd194 = ((CSP_REGISTER_T)0x0000C200),
PROM_PageAdd195 = ((CSP_REGISTER_T)0x0000C300),
PROM_PageAdd196 = ((CSP_REGISTER_T)0x0000C400),
PROM_PageAdd197 = ((CSP_REGISTER_T)0x0000C500),
PROM_PageAdd198 = ((CSP_REGISTER_T)0x0000C600),
PROM_PageAdd199 = ((CSP_REGISTER_T)0x0000C700),
PROM_PageAdd200 = ((CSP_REGISTER_T)0x0000C800),
PROM_PageAdd201 = ((CSP_REGISTER_T)0x0000C900),
PROM_PageAdd202 = ((CSP_REGISTER_T)0x0000CA00),
PROM_PageAdd203 = ((CSP_REGISTER_T)0x0000CB00),
PROM_PageAdd204 = ((CSP_REGISTER_T)0x0000CC00),
PROM_PageAdd205 = ((CSP_REGISTER_T)0x0000CD00),
PROM_PageAdd206 = ((CSP_REGISTER_T)0x0000CE00),
PROM_PageAdd207 = ((CSP_REGISTER_T)0x0000CF00),
PROM_PageAdd208 = ((CSP_REGISTER_T)0x0000D000),
PROM_PageAdd209 = ((CSP_REGISTER_T)0x0000D100),
PROM_PageAdd210 = ((CSP_REGISTER_T)0x0000D200),
PROM_PageAdd211 = ((CSP_REGISTER_T)0x0000D300),
PROM_PageAdd212 = ((CSP_REGISTER_T)0x0000D400),
PROM_PageAdd213 = ((CSP_REGISTER_T)0x0000D500),
PROM_PageAdd214 = ((CSP_REGISTER_T)0x0000D600),
PROM_PageAdd215 = ((CSP_REGISTER_T)0x0000D700),
PROM_PageAdd216 = ((CSP_REGISTER_T)0x0000D800),
PROM_PageAdd217 = ((CSP_REGISTER_T)0x0000D900),
PROM_PageAdd218 = ((CSP_REGISTER_T)0x0000DA00),
PROM_PageAdd219 = ((CSP_REGISTER_T)0x0000DB00),
PROM_PageAdd220 = ((CSP_REGISTER_T)0x0000DC00),
PROM_PageAdd221 = ((CSP_REGISTER_T)0x0000DD00),
PROM_PageAdd222 = ((CSP_REGISTER_T)0x0000DE00),
PROM_PageAdd223 = ((CSP_REGISTER_T)0x0000DF00),
PROM_PageAdd224 = ((CSP_REGISTER_T)0x0000E000),
PROM_PageAdd225 = ((CSP_REGISTER_T)0x0000E100),
PROM_PageAdd226 = ((CSP_REGISTER_T)0x0000E200),
PROM_PageAdd227 = ((CSP_REGISTER_T)0x0000E300),
PROM_PageAdd228 = ((CSP_REGISTER_T)0x0000E400),
PROM_PageAdd229 = ((CSP_REGISTER_T)0x0000E500),
PROM_PageAdd230 = ((CSP_REGISTER_T)0x0000E600),
PROM_PageAdd231 = ((CSP_REGISTER_T)0x0000E700),
PROM_PageAdd232 = ((CSP_REGISTER_T)0x0000E800),
PROM_PageAdd233 = ((CSP_REGISTER_T)0x0000E900),
PROM_PageAdd234 = ((CSP_REGISTER_T)0x0000EA00),
PROM_PageAdd235 = ((CSP_REGISTER_T)0x0000EB00),
PROM_PageAdd236 = ((CSP_REGISTER_T)0x0000EC00),
PROM_PageAdd237 = ((CSP_REGISTER_T)0x0000ED00),
PROM_PageAdd238 = ((CSP_REGISTER_T)0x0000EE00),
PROM_PageAdd239 = ((CSP_REGISTER_T)0x0000EF00),
PROM_PageAdd240 = ((CSP_REGISTER_T)0x0000F000),
PROM_PageAdd241 = ((CSP_REGISTER_T)0x0000F100),
PROM_PageAdd242 = ((CSP_REGISTER_T)0x0000F200),
PROM_PageAdd243 = ((CSP_REGISTER_T)0x0000F300),
PROM_PageAdd244 = ((CSP_REGISTER_T)0x0000F400),
PROM_PageAdd245 = ((CSP_REGISTER_T)0x0000F50),
PROM_PageAdd246 = ((CSP_REGISTER_T)0x0000F600),
PROM_PageAdd247 = ((CSP_REGISTER_T)0x0000F700),
PROM_PageAdd248 = ((CSP_REGISTER_T)0x0000F800),
PROM_PageAdd249 = ((CSP_REGISTER_T)0x0000F900),
PROM_PageAdd250 = ((CSP_REGISTER_T)0x0000FA00),
PROM_PageAdd251 = ((CSP_REGISTER_T)0x0000FB00),
PROM_PageAdd252 = ((CSP_REGISTER_T)0x0000FC00),
PROM_PageAdd253 = ((CSP_REGISTER_T)0x0000FD00),
PROM_PageAdd254 = ((CSP_REGISTER_T)0x0000FE00),
PROM_PageAdd255 = ((CSP_REGISTER_T)0x0000FF00),
DROM_PageAdd0 = ((CSP_REGISTER_T)0x10000000), //DROM 每页64BYTE
DROM_PageAdd1 = ((CSP_REGISTER_T)0x10000040),
DROM_PageAdd2 = ((CSP_REGISTER_T)0x10000080),
DROM_PageAdd3 = ((CSP_REGISTER_T)0x100000C0),
DROM_PageAdd4 = ((CSP_REGISTER_T)0x10000100),
DROM_PageAdd5 = ((CSP_REGISTER_T)0x10000140),
DROM_PageAdd6 = ((CSP_REGISTER_T)0x10000180),
DROM_PageAdd7 = ((CSP_REGISTER_T)0x100001C0),
DROM_PageAdd8 = ((CSP_REGISTER_T)0x10000200),
DROM_PageAdd9 = ((CSP_REGISTER_T)0x10000240),
DROM_PageAdd10 = ((CSP_REGISTER_T)0x10000280),
DROM_PageAdd11 = ((CSP_REGISTER_T)0x100002C0),
DROM_PageAdd12 = ((CSP_REGISTER_T)0x10000300),
DROM_PageAdd13 = ((CSP_REGISTER_T)0x10000340),
DROM_PageAdd14 = ((CSP_REGISTER_T)0x10000380),
DROM_PageAdd15 = ((CSP_REGISTER_T)0x100003C0),
DROM_PageAdd16 = ((CSP_REGISTER_T)0x10000400),
DROM_PageAdd17 = ((CSP_REGISTER_T)0x10000440),
DROM_PageAdd18 = ((CSP_REGISTER_T)0x10000480),
DROM_PageAdd19 = ((CSP_REGISTER_T)0x100004C0),
DROM_PageAdd20 = ((CSP_REGISTER_T)0x10000500),
DROM_PageAdd21 = ((CSP_REGISTER_T)0x10000540),
DROM_PageAdd22 = ((CSP_REGISTER_T)0x10000580),
DROM_PageAdd23 = ((CSP_REGISTER_T)0x100005C0),
DROM_PageAdd24 = ((CSP_REGISTER_T)0x10000600),
DROM_PageAdd25 = ((CSP_REGISTER_T)0x10000640),
DROM_PageAdd26 = ((CSP_REGISTER_T)0x10000680),
DROM_PageAdd27 = ((CSP_REGISTER_T)0x100006C0),
DROM_PageAdd28 = ((CSP_REGISTER_T)0x10000700),
DROM_PageAdd29 = ((CSP_REGISTER_T)0x10000740),
DROM_PageAdd30 = ((CSP_REGISTER_T)0x10000780),
DROM_PageAdd31 = ((CSP_REGISTER_T)0x100007C0)
}IFC_ROMSELETED_TypeDef;
/**
* @brief IFC INT mode
*/
typedef enum
{
ERS_END_INT = (0x01ul),
RGM_END_INT = ((0x01ul)<<1),
PEP_END_INT = ((0x01ul)<<2),
PROT_ERR_INT = ((0x01ul)<<12),
UDEF_ERR_INT = ((0x01ul)<<13),
ADDR_ERR_INT = ((0x01ul)<<14),
OVW_ERR_INT = ((0x01ul)<<15)
}IFC_INT_TypeDef;
extern void ChipErase(void);
extern void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAd);
extern void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x);
extern void IFC_Int_Enable(void);
extern void IFC_Int_Disable(void);
extern void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern volatile unsigned int R_INT_FlashAdd;
extern volatile unsigned char f_Drom_write_complete;
extern volatile unsigned char f_Drom_writing;
extern volatile unsigned char ifc_step;
extern void Page_ProgramData_U32(unsigned int FlashAdd,unsigned int DataSize,volatile U32_T *BufArry);
extern void ReadDataArry_U32(unsigned int RdStartAdd,unsigned int DataLength,volatile U32_T *DataArryPoint);
#endif /**< apt32f102_ifc_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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Source/include/apt32f102_lpt.h Normal file
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@@ -0,0 +1,280 @@
/*
******************************************************************************
* @file apt32f102_lpt.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_lpt_H
#define _apt32f102_lpt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define LPT_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------LPT value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief LPT CLK EN register
*/
typedef enum
{
LPTCLK_DIS = 0,
LPTCLK_EN = 1,
}LPT_CLK_TypeDef;
/**
* @brief LPT CLK source register
*/
typedef enum
{
LPT_PCLK_DIV4= (0<<2),
LPT_ISCLK = (1<<2),
LPT_IMCLK_DIV4 = (2<<2),
LPT_EMCLK = (3<<2),
LPT_IN_RISE = (4<<2),
LPT_IN_FALL = (5<<2),
}LPT_CSS_TypeDef;
/**
* @brief LPT START SHADOW register
*/
typedef enum
{
LPT_SHADOW = (0<<6),
LPT_IMMEDIATE= (1<<6),
}LPT_SHDWSTP_TypeDef;
/**
* @brief LPT CLK div register
*/
typedef enum
{
LPT_PSC_DIV0= 0,
LPT_PSC_DIV2= 1,
LPT_PSC_DIV4= 2,
LPT_PSC_DIV8= 3,
LPT_PSC_DIV16= 4,
LPT_PSC_DIV32= 5,
LPT_PSC_DIV64= 6,
LPT_PSC_DIV128= 7,
LPT_PSC_DIV256= 8,
LPT_PSC_DIV512= 9,
LPT_PSC_DIV1024= 0X0A,
LPT_PSC_DIV2048= 0X0B,
LPT_PSC_DIV4096= 0X0C,
}LPT_PSCDIV_TypeDef;
/**
* @brief LPT START SYN EN register
*/
typedef enum
{
LPT_SWSYNDIS= (0<<2),
LPT_SWSYNEN= (1<<2),
}LPT_SWSYN_TypeDef;
/**
* @brief LPT IO stop status register
*/
typedef enum
{
LPT_IDLE_Z= (0<<3), //High-impedance output
LPT_IDLE_LOW= (1<<3),
}LPT_IDLEST_TypeDef;
/**
* @brief LPT PRDLD register
*/
typedef enum
{
LPT_PRDLD_IMMEDIATELY= (0<<4),
LPT_PRDLD_DUTY_END= (1<<4),
}LPT_PRDLD_TypeDef;
/**
* @brief LPT POL register
*/
typedef enum
{
LPT_POL_HIGH= (0<<5),
LPT_POL_LOW= (1<<5),
}LPT_POL_TypeDef;
/**
* @brief LPT OPM register
*/
typedef enum
{
LPT_OPM_CONTINUOUS= (0<<6),
LPT_OPM_ONCE= (1<<6),
}LPT_OPM_TypeDef;
/**
* @brief LPT FLTIPSCLD register
*/
typedef enum
{
LPT_FLTIPSCLD_NULL= (0<<10),
LPT_FLTIPSCLD_EN= (1<<10),
}LPT_FLTIPSCLD_TypeDef;
/**
* @brief LPT FLTDEB register
*/
typedef enum
{
LPT_FLTDEB_00= (0<<13),
LPT_FLTDEB_02= (1<<13),
LPT_FLTDEB_03= (2<<13),
LPT_FLTDEB_04= (3<<13),
LPT_FLTDEB_06= (4<<13),
LPT_FLTDEB_08= (5<<13),
LPT_FLTDEB_16= (6<<13),
LPT_FLTDEB_32= (7<<13),
}LPT_FLTDEB_TypeDef;
/**
* @brief LPT PSCLD register
*/
typedef enum
{
LPT_PSCLD_0= (0<<16), //PSCR
LPT_PSCLD_1= (1<<16),
}LPT_PSCLD_TypeDef;
/**
* @brief LPT CMPLD register
*/
typedef enum
{
LPT_CMPLD_IMMEDIATELY= (0<<17),
LPT_CMPLD_DUTY_END= (1<<17),
}LPT_CMPLD_TypeDef;
/**
* @brief LPT TRGENX register
*/
typedef enum
{
LPT_TRGEN_DIS= (0<<0),
LPT_TRGEN_EN= (1<<0),
}LPT_TRGENX_TypeDef;
/**
* @brief LPT OSTMDX register
*/
typedef enum
{
LPT_OSTMD_CONTINUOUS= (0<<8),
LPT_OSTMD_ONCE= (1<<8),
}LPT_OSTMDX_TypeDef;
/**
* @brief LPT AREARM register
*/
typedef enum
{
LPT_AREARM_DIS= (0<<30),
LPT_AREARM_EN= (1<<30),
}LPT_AREARM_TypeDef;
/**
* @brief LPT SRCSEL register
*/
typedef enum
{
LPT_SRCSEL_DIS= (0<<0),
LPT_SRCSEL_EN= (1<<0),
}LPT_SRCSEL_TypeDef;
/**
* @brief LPT BLKINV register
*/
typedef enum
{
LPT_BLKINV_DIS= (0<<4),
LPT_BLKINV_EN= (1<<4),
}LPT_BLKINV_TypeDef;
/**
* @brief LPT CROSSMD register
*/
typedef enum
{
LPT_CROSSMD_DIS= (0<<7),
LPT_CROSSMD_EN= (1<<7),
}LPT_CROSSMD_TypeDef;
/**
* @brief LPT TRGSRC0 register
*/
typedef enum
{
LPT_TRGSRC0_DIS= (0<<0),
LPT_TRGSRC0_ZRO= (1<<0),
LPT_TRGSRC0_PRD= (2<<0),
LPT_TRGSRC0_ZRO_PRD= (3<<0),
LPT_TRGSRC0_CMP= (4<<0),
}LPT_TRGSRC0_TypeDef;
/**
* @brief LPT ESYN0OE register
*/
typedef enum
{
LPT_ESYN0OE_DIS= (0<<20),
LPT_ESYN0OE_EN= (1<<20),
}LPT_ESYN0OE_TypeDef;
/**
* @brief LPT INT MASK SET/CLR Set
*/
typedef enum
{
LPT_TRGEV0 = (0x01 << 0),
LPT_MATCH = (0x01 << 1),
LPT_PEND = (0x01 << 2),
}LPT_IMSCR_TypeDef;
/**
* @brief LPT IO Set
*/
typedef enum
{
LPT_OUT_PA09 = 0,
LPT_OUT_PB01 = 1,
LPT_IN_PA10 = 2,
}LPT_IOSET_TypeDef;
#define LPT_DEBUG_MODE (0X01<<1)
extern void LPT_DeInit(void);
extern void LPT_IO_Init(LPT_IOSET_TypeDef IONAME);
extern void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,
LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX);
extern void LPT_Debug_Mode(FunctionalStatus NewState);
extern void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA);
extern void LPT_CNT_Write(U16_T CNT_DATA);
extern U16_T LPT_PRDR_Read(void);
extern U16_T LPT_CMP_Read(void);
extern U16_T LPT_CNT_Read(void);
extern void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX);
extern void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX);
extern void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA);
extern void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA);
extern void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA);
extern void LPT_Soft_Trigger(void);
extern void LPT_Start(void);
extern void LPT_Stop(void);
extern void LPT_Soft_Reset(void);
extern void LPT_REARM_Write(void);
extern U8_T LPT_REARM_Read(void);
extern void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X);
extern void LPT_INT_ENABLE(void);
extern void LPT_INT_DISABLE(void);
/*************************************************************/
#endif /**< apt32f102_lpt_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_interrupt.c
* @author APT AE Team
* @version V1.10
* @date 2021/08/25
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_rtc_H
#define _apt32f102_rtc_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* rtc Registers Definition *************************
******************************************************************************/
/** @addtogroup RTC Registers Reset Value
* @{
*/
#define RTC_TIMR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_DATR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_CR_RST ((CSP_REGISTER_T)0x00000001)
#define RTC_CCR_RST ((CSP_REGISTER_T)0x00800000)
#define RTC_ALRAR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_ALRBR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_SSR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_CAL_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_IMCR_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_EVTRG_RST ((CSP_REGISTER_T)0x00000000)
#define RTC_EVPS_RST ((CSP_REGISTER_T)0x00000000)
//RTC KEY
#define RTC_KEY (0XCA53ul)
/**
* @brief RTC DIVS Control
*/
typedef enum
{
CLKSRC_ISOSC = (CSP_REGISTER_T)(0x00ul<<24),
CLKSRC_IMOSC_4div = (CSP_REGISTER_T)(0x01ul<<24),
CLKSRC_EMOSC = (CSP_REGISTER_T)(0x02ul<<24),
CLKSRC_EMOSC_4div = (CSP_REGISTER_T)(0x03ul<<24)
}RTC_CLKSRC_TypeDef;
/**
* @brief RTC INT register
*/
typedef enum
{
//RISR IMCR MISR ICR
ALRA_INT = ((CSP_REGISTER_T)(0x01ul << 0)),
ALRB_INT = ((CSP_REGISTER_T)(0x01ul << 1)),
CPRD_INT = ((CSP_REGISTER_T)(0x01ul << 2)),
RTC_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 3)),
RTC_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 4))
}RTC_INT_TypeDef;
/**
* @brief RTC Alarm SEC MIN DAY mask
*/
typedef enum
{
Alarm_Second_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 7)),
Alarm_Second_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 7)),
} RTC_Alarm_Second_mask_TypeDef;
typedef enum
{
Alarm_Minute_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 15)),
Alarm_Minute_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 15)),
} RTC_Alarm_Minute_mask_TypeDef;
typedef enum
{
Alarm_Hour_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 23)),
Alarm_Hour_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 23)),
} RTC_Alarm_Hour_mask_TypeDef;
typedef enum
{
Alarm_DataOrWeek_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 31)),
Alarm_DataOrWeek_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 31))
} RTC_Alarm_DataOrWeek_mask_TypeDef; ;
/**
* @brief RTC Alarm week data select
*/
typedef enum
{
Alarm_data_selecte = ((CSP_REGISTER_T)(0x00ul << 30)),
Alarm_week_selecte = ((CSP_REGISTER_T)(0x01ul << 30))
} RTC_Alarm_WeekData_select_TypeDef;
/**
* @brief RTC Alarm Register select
*/
typedef enum
{
Alarm_A = 0,
Alarm_B = 1
}RTC_Alarm_Register_select_TypeDef;
/**
* @brief RTC Alarm io output mode
*/
typedef enum
{
Alarm_A_pulse_output = ((CSP_REGISTER_T)(0x00ul << 10)),
Alarm_A_High = ((CSP_REGISTER_T)(0x01ul << 10)),
Alarm_A_Low = ((CSP_REGISTER_T)(0x02ul << 10)),
Alarm_B_pulse_output = ((CSP_REGISTER_T)(0x04ul << 10)),
Alarm_B_High = ((CSP_REGISTER_T)(0x05ul << 10)),
Alarm_B_Low = ((CSP_REGISTER_T)(0x06ul << 10)),
}Rtc_Output_Mode_TypeDef;
/**
* @brief RTC Alarm IO clock outpu
*/
typedef enum
{
COSEL_Cali_512hz = ((CSP_REGISTER_T)(0x00ul << 8)),
COSEL_Cali_1hz = ((CSP_REGISTER_T)(0x01ul << 8)),
COSEL_NoCali_512hz = ((CSP_REGISTER_T)(0x02ul << 8)),
COSEL_NoCali_1hz = ((CSP_REGISTER_T)(0x03ul << 8)),
}
Rtc_ClockOutput_Mode_TypeDef;
/**
* @brief RTC AlarmA cmd select
*/
typedef enum
{
Alarm_A_EN = ((CSP_REGISTER_T)(0x01ul << 3)),
Alarm_A_DIS = ((CSP_REGISTER_T)(0x00ul << 3)),
}RTC_AlarmA_CMD_TypeDef;
/**
* @brief RTC AlarmB cmd select
*/
typedef enum
{
Alarm_B_EN = ((CSP_REGISTER_T)(0x01ul << 4)),
Alarm_B_DIS = ((CSP_REGISTER_T)(0x00ul << 4)),
}RTC_AlarmB_CMD_TypeDef;
/**
* @brief RTC FMT mode select
*/
typedef enum
{
RTC_24H = ((CSP_REGISTER_T)(0x00ul << 5)),
RTC_12H = ((CSP_REGISTER_T)(0x01ul << 5)),
}RTC_FMT_MODE_TypeDef;
/**
* @brief RTC CPRD select
*/
typedef enum
{
CPRD_NONE = ((CSP_REGISTER_T)(0x00ul << 13)),
CPRD_05S = ((CSP_REGISTER_T)(0x01ul << 13)),
CPRD_1S = ((CSP_REGISTER_T)(0x02ul << 13)),
CPRD_1MIN = ((CSP_REGISTER_T)(0x03ul << 13)),
CPRD_1HOUR = ((CSP_REGISTER_T)(0x04ul << 13)),
CPRD_1DAY = ((CSP_REGISTER_T)(0x05ul << 13)),
CPRD_1MONTH = ((CSP_REGISTER_T)(0x06ul << 13)),
}RTC_CPRD_TypeDef;
/**
* @brief RTC EVTRG TRGSRC0 SET
*/
typedef enum
{
RTC_EVTRG_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x00ul )),
RTC_EVTRG_TRGSRC0_AlarmA = ((CSP_REGISTER_T)(0x01ul )),
RTC_EVTRG_TRGSRC0_AlarmB = ((CSP_REGISTER_T)(0x02ul )),
RTC_EVTRG_TRGSRC0_AlarmAB = ((CSP_REGISTER_T)(0x03ul )),
RTC_EVTRG_TRGSRC0_CPRD = ((CSP_REGISTER_T)(0x04ul )),
}RTC_EVTRG_TRGSRC0_TypeDef;
/**
* @brief RTC EVTRG TRGSRC1 SET
*/
typedef enum
{
RTC_EVTRG_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x00ul<<4 )),
RTC_EVTRG_TRGSRC1_AlarmA = ((CSP_REGISTER_T)(0x01ul<<4 )),
RTC_EVTRG_TRGSRC1_AlarmB = ((CSP_REGISTER_T)(0x02ul<<4 )),
RTC_EVTRG_TRGSRC1_AlarmAB = ((CSP_REGISTER_T)(0x03ul<<4 )),
RTC_EVTRG_TRGSRC1_CPRD = ((CSP_REGISTER_T)(0x04ul<<4 )),
}RTC_EVTRG_TRGSRC1_TypeDef;
typedef enum
{
RTC_TRGSRC0_EN = ((CSP_REGISTER_T)(0x00ul<<20 )),
RTC_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x01ul<<20 )),
RTC_TRGSRC1_EN = ((CSP_REGISTER_T)(0x00ul<<21 )),
RTC_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x01ul<<21 )),
}RTC_TRGSRCX_CMD_TypeDef;
typedef struct
{
volatile uint8_t u8Second; ///<闹钟分钟
volatile uint8_t u8Minute; ///<闹钟分钟
volatile uint8_t u8Hour; ///<闹钟小时
volatile uint8_t u8WeekOrData; ///<闹钟周
}RTC_Alarmset_T;
typedef struct
{
volatile uint8_t u8Second; ///<秒
volatile uint8_t u8Minute; ///<分
volatile uint8_t u8Hour; ///<时
volatile uint8_t u8DayOfWeek; ///<周
volatile uint8_t u8Day; ///<日
volatile uint8_t u8Month; ///<月
volatile uint8_t u8Year; ///<年
} RTC_time_t;
/** @addtogroup RTC_Exported_functions
* @{
*/
extern void RTC_RST_VALUE(void);
extern void RTCCLK_CONFIG(U16_T DIVS , U16_T DIVA , RTC_CLKSRC_TypeDef CLKSRC_X);
extern void RTC_ALM_IO_SET(Rtc_Output_Mode_TypeDef Rtc_Output_Mode_x );
extern void RTC_TIMR_DATR_SET(RTC_time_t *RTC_TimeDate);
extern void RTC_TIMR_DATR_Read(RTC_time_t *RTC_TimeDate);
extern void RTC_Alarm_TIMR_DATR_SET(RTC_Alarm_Register_select_TypeDef Alarm_x , RTC_Alarmset_T *RTC_AlarmA , RTC_Alarm_Second_mask_TypeDef RTC_Alarm_Second_x ,
RTC_Alarm_Minute_mask_TypeDef RTC_Alarm_Minute_x , RTC_Alarm_Hour_mask_TypeDef RTC_Alarm_Hour_x,
RTC_Alarm_DataOrWeek_mask_TypeDef RTC_Alarm_DataOrWeek_x,
RTC_Alarm_WeekData_select_TypeDef Alarm_x_selecte);
extern void RTC_Function_Config(RTC_FMT_MODE_TypeDef RTC_FMT_MODE , RTC_CPRD_TypeDef RTC_CPRD_x , Rtc_ClockOutput_Mode_TypeDef Rtc_ClockOutput_x);
extern void RTC_TRGSRC0_Config(RTC_EVTRG_TRGSRC0_TypeDef RTC_EVTRG_TRGSRC0_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev0Prd);
extern void RTC_TRGSRC1_Config(RTC_EVTRG_TRGSRC1_TypeDef RTC_EVTRG_TRGSRC1_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev1Prd);
extern void RTC_TRGSRC0_SWFTRG(void);
extern void RTC_TRGSRC1_SWFTRG(void);
extern void RTC_Start(void);
extern void RTC_Stop(void);
extern void RTC_AlarmA_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmA);
extern void RTC_AlarmB_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmB);
extern void RTC_Int_Enable(RTC_INT_TypeDef RTC_X_INT);
extern void RTC_Int_Disable(RTC_INT_TypeDef RTC_X_INT);
extern void RTC_Vector_Int_Enable(void);
extern void RTC_Vector_Int_Disable(void);
extern void RTC_WakeUp_Enable(void);
extern void RTC_WakeUp_Disable(void);
extern RTC_time_t RTC_TimeDate_buf;
extern RTC_Alarmset_T RTC_AlarmA_buf;
extern RTC_Alarmset_T RTC_AlarmB_buf;
#endif /**< apt32f102_rtc_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_sio.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_sio_H
#define _apt32f102_sio_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define SIO_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------SIO value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief SIO IO group register
*/
typedef enum
{
SIO_PA02 = 0,
SIO_PA03 = 1,
SIO_PA012 = 2,
SIO_PB01 = 3,
}SIO_IOG_TypeDef;
/**
* @brief SIO CLK EN register
*/
typedef enum
{
SIOCLK_DIS = 0,
SIOCLK_EN = 1,
}SIO_CLK_TypeDef;
/**
* @brief SIO TXDEB register
*/
typedef enum
{
SIO_TXDEB_1CYCLE = (0<<1),
SIO_TXDEB_2CYCLE = (1<<1),
SIO_TXDEB_3CYCLE = (2<<1),
SIO_TXDEB_4CYCLE = (3<<1),
SIO_TXDEB_5CYCLE = (4<<1),
SIO_TXDEB_6CYCLE = (5<<1),
SIO_TXDEB_7CYCLE = (6<<1),
SIO_TXDEB_8CYCLE = (7<<1),
}SIO_RXDEB_TypeDef;
/**
* @brief SIO IO IDLE STATUS register
*/
typedef enum
{
SIO_IDLE_Z = 0,
SIO_IDLE_HIGH = 1,
SIO_IDLE_LOW = 2,
}SIO_IDLEST_TypeDef;
/**
* @brief SIO TX DIR register
*/
typedef enum
{
SIO_TX_LSB = (0<<2),
SIO_TX_MSB = (1<<2),
}SIO_TXDIR_TypeDef;
/**
* @brief SIO LENOBH register
*/
typedef enum
{
SIO_OBH_1BIT = (0<<8),
SIO_OBH_2BIT = (1<<8),
SIO_OBH_3BIT = (2<<8),
SIO_OBH_4BIT = (3<<8),
SIO_OBH_5BIT = (4<<8),
SIO_OBH_6BIT = (5<<8),
SIO_OBH_7BIT = (6<<8),
SIO_OBH_8BIT = (7<<8),
}SIO_LENOBH_TypeDef;
/**
* @brief SIO LENOBL register
*/
typedef enum
{
SIO_OBL_1BIT = (0<<11),
SIO_OBL_2BIT = (1<<11),
SIO_OBL_3BIT = (2<<11),
SIO_OBL_4BIT = (3<<11),
SIO_OBL_5BIT = (4<<11),
SIO_OBL_6BIT = (5<<11),
SIO_OBL_7BIT = (6<<11),
SIO_OBL_8BIT = (7<<11),
}SIO_LENOBL_TypeDef;
/**
* @brief SIO RX EDGE register
*/
typedef enum
{
SIO_RX_RISE = 0,
SIO_RX_FALL = 1,
SIO_RX_RISE_FALL = 2,
}SIO_BSTSEL_TypeDef;
/**
* @brief SIO RX TRG MODE register
*/
typedef enum
{
SIO_RX_DEB = (0<<3),
SIO_RX_FLT30NS = (1<<3),
}SIO_TRGMODE_TypeDef;
/**
* @brief SIO RX ALIGNEN register
*/
typedef enum
{
SIO_RX_ALIGNDIS = (0<<28),
SIO_RX_ALIGNEN = (1<<28),
}SIO_ALIGNEN_TypeDef;
/**
* @brief SIO RX DIR register
*/
typedef enum
{
SIO_RX_MSB = (0<<29),
SIO_RX_LSB = (1<<29),
}SIO_RXDIR_TypeDef;
/**
* @brief SIO RX MODE register
*/
typedef enum
{
SIO_RMODE0 = (0<<30),
SIO_RMODE1 = (1<<30),
}SIO_RXMODE_TypeDef;
/**
* @brief SIO BREAKEN register
*/
typedef enum
{
SIO_BREAKDIS = (0<<0),
SIO_BREAKEN = (1<<0),
}SIO_BREAKEN_TypeDef;
/**
* @brief SIO BREAKLVL register
*/
typedef enum
{
SIO_BREAKLVL_LOW = (0<<1),
SIO_BREAKLVL_HIGH = (1<<1),
}SIO_BREAKLVL_TypeDef;
/**
* @brief SIO TORSTEN register
*/
typedef enum
{
SIO_TORSTDIS = (0<<15),
SIO_TORSTEN = (1<<15),
}SIO_TORSTEN_TypeDef;
/**
* @brief LPT INT MASK SET/CLR Set
*/
typedef enum
{
SIO_TXDNE = (0x01 << 0),
SIO_RXDNE = (0x01 << 1),
SIO_TXBUFEMPT = (0x01 << 2),
SIO_RXBUFEMPT = (0x01 << 3),
SIO_BREAK = (0x01 << 4),
SIO_TIME = (0x01 << 5),
}SIO_IMSCR_TypeDef;
#define TX_D0 (0X00)
#define TX_D1 (0X01)
#define TX_DL (0X02)
#define TX_DH (0X03)
extern void SIO_DeInit(void);
extern void SIO_IO_Init(SIO_IOG_TypeDef IOGx);
extern void SIO_TX_Init(SIO_CLK_TypeDef CLKX,U8_T TCKPRSX);
extern void SIO_TX_Configure(SIO_IDLEST_TypeDef IDLEX,SIO_TXDIR_TypeDef TXDIRX,U8_T TXBUFLENX,U8_T TXCNTX,U8_T D0DURX,U8_T D1DURX,SIO_LENOBH_TypeDef LENOBHX,
SIO_LENOBL_TypeDef LENOBLX,U8_T HSQX,U8_T LSQX);
extern void SIO_TXBUF_Set(U8_T D30,U8_T D28,U8_T D26,U8_T D24,U8_T D22,U8_T D20,U8_T D18,U8_T D16,
U8_T D14,U8_T D12,U8_T D10,U8_T D08,U8_T D06,U8_T D04,U8_T D02,U8_T D00);
extern void SIO_RX_Init(SIO_CLK_TypeDef CLKX,SIO_RXDEB_TypeDef RXDEBX,U8_T DEBCKSX);
extern void SIO_RX_Configure0(SIO_BSTSEL_TypeDef BSTSELX,SIO_TRGMODE_TypeDef TRGMX,U8_T SPLCNTX,U8_T EXTRACTX,U8_T HITHRX,
SIO_ALIGNEN_TypeDef ALIGNX,SIO_RXDIR_TypeDef RXDIRX,SIO_RXMODE_TypeDef RXMODEX,U8_T RXLENX,U8_T RXBUFLENX,U8_T RXKPRSX);
extern void SIO_RX_Configure1(SIO_BREAKEN_TypeDef BREAKX,SIO_BREAKLVL_TypeDef BREAKLVLX,U8_T BREKCNTX,SIO_TORSTEN_TypeDef TORSTX,U8_T TOCNTX);
extern void SIO_ConfigInterrupt_CMD(FunctionalStatus NewState,SIO_IMSCR_TypeDef SIO_IMSCR_X);
extern void SIO_INT_ENABLE(void);
extern void SIO_INT_DISABLE(void);
/*************************************************************/
#endif /**< apt32f102_sio_H */

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/*
******************************************************************************
* @file apt32f102_spi.c
* @author APT AE Team
* @version V1.025
* @date 2020/06/08
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_spi_H
#define _apt32f102_spi_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************** spi Registers Definition ****************************
******************************************************************************/
/*******************************************************************************
* SSPCR0 : Control Register 0
*******************************************************************************/
#define SSP_DSS(val) (((val-1) & 0x0Ful) << 0) /**< Data Size Select */
#define SSP_FRF(val) (((val) & 0x03ul) << 4) /**< Frame Format */
#define SSP_SPO (0x01ul << 6) /**< SSPCLK Polarity */
#define SSP_SPH (0x01ul << 7) /**< SSPCLK Phase */
#define SSP_SCR(val) (((val) & 0x0FFul) << 8) /**< Serial Clock Rate */
/*******************************************************************************
* SSPCR1 : Control Register 1
*******************************************************************************/
#define SSP_LBM (0x01ul << 0) /**< Loopback mode */
#define SSP_SSE (0x01ul << 1) /**< Synchronous Serial Port Enable */
#define SSP_MS (0x01ul << 2) /**< Master or Slave Mode Select */
#define SSP_SOD (0x01ul << 3) /**< Slave Mode Output Disable */
#define SSP_RXIFLSELFRF(val) (((val) & 0x07ul) << 4)
/**< Receive interrupt FIFO level select */
/*******************************************************************************
* SSPDR : Data Register
*******************************************************************************/
#define SSP_DATA(val) (((val) & 0x0FFFF) << 0) /**< Transmit/Receive FIFO */
/*******************************************************************************
* SSPSR : Status Register
*******************************************************************************/
#define SSP_TFE (0x01ul << 0) /**< Transmit FIFO Empty */
#define SSP_TNF (0x01ul << 1) /**< Transmit FIFO is not Full */
#define SSP_RNE (0x01ul << 2) /**< Receive is not Empty */
#define SSP_RFF (0x01ul << 3) /**< Receive FIFO Full */
#define SSP_BSY (0x01ul << 4) /**< PrimeCell SSP Busy Flag */
/*******************************************************************************
* SSPCPSR : Clock prescale register
*******************************************************************************/
#define SSP_CPSDVSR(val) (((val) & 0x0FF) << 0) /**< Clock Prescale Devisor */
/*******************************************************************************
* SSPIMSC : Interrupt mask set and clear register
*******************************************************************************/
#define SSP_RORIM (0x01ul << 0) /**< Receive Overrun Interrupt Mask */
#define SSP_RTIM (0x01ul << 1) /**< Receive Timeout Interrupt Mask */
#define SSP_RXIM (0x01ul << 2) /**< Receive FIFO Interrupt Mask */
#define SSP_TXIM (0x01ul << 3) /**< Transmit FIFO interrupt Mask */
/*******************************************************************************
* SSPRIS : Raw interrupt status register
*******************************************************************************/
#define SSP_RORRIS (0x01ul << 0)
/**< Gives the Raw Interrupt Status of the SSPRORINTR Interrupt */
#define SSP_RTRIS (0x01ul << 1)
/**< Gives the raw interrupt state of the SSPRTINTR interrupt */
#define SSP_RXRIS (0x01ul << 2)
/**< Gives the raw interrupt state of the SSPRXINTR interrupt */
#define SSP_TXRIS (0x01ul << 3)
/**< Gives the raw interrupt state of the SSPTXINTR interrupt */
/*******************************************************************************
* SSPMIS : Masked interrupt status register
*******************************************************************************/
#define SSP_RORRIS (0x01ul << 0)
/**<Gives the receive over run masked interrupt status of SSPRORINTR interrupt*/
#define SSP_RTRIS (0x01ul << 1)
/**<Gives the receive timeout masked interrupt state of SSPRTINTR interrupt */
#define SSP_RXRIS (0x01ul << 2)
/**<Gives the receive FIFO masked interrupt state of SSPRXINTR interrupt */
#define SSP_TXRIS (0x01ul << 3)
/**<Gives the transmit FIFO masked interrupt state of SSPTXINTR interrupt */
/*******************************************************************************
* SSPICR : Interrupt clear register
*******************************************************************************/
#define SSP_RORIC (0x01ul << 0) /**< Clears the SSPRORINTR interrupt */
#define SSP_RTIC (0x01ul << 1) /**< Clears the SSPRTINTR interrupt */
/*******************************************************************************
***************************** SSP REGISTER MASK *******************************
*******************************************************************************/
#define SSP_CR0_MASK (0x0000FFFFul) /**< Control Register 0 mask */
#define SSP_CR1_MASK (0x0000007Ful) /**< Control Register 1 mask */
#define SSP_DR_MASK (0x0000FFFFul)
/**< Receive FIFO(read) and transmit FIFO data register(write) mask */
#define SSP_SR_MASK (0x0000001Ful) /**< Status register mask */
#define SSP_CPSR_MASK (0x000000FFul) /**< Clock prescale register mask */
#define SSP_IMSCR_MASK (0x0000000Ful)
/**< Interrupt mask set and clear register mask */
#define SSP_RISR_MASK (0x0000000Ful) /**< Raw interrupt status register mask*/
#define SSP_MISR_MASK (0x0000000Ful)
/**< Masked interrupt status register mask */
#define SSP_ICR_MASK (0x00000003ul) /**< Interrupt clear register mask */
/*******************************************************************************
************************* SSP REGISTER RESET VALUE ****************************
*******************************************************************************/
#define SSP_CR0_RST (0x00000000ul) /**< Control Register 0 reset value */
#define SSP_CR1_RST (0x00000010ul) /**< Control Register 1 reset value */
#define SSP_DR_RST (0x00000000ul)
/**< Receive FIFO(read) and transmit FIFO data register(write) reset value */
#define SSP_SR_RST (0x00000003ul) /**< Status register reset value */
#define SSP_CPSR_RST (0x00000000ul)
/**< Clock prescale register reset value */
#define SSP_IMSCR_RST (0x00000000ul)
/**< Interrupt mask set and clear register reset value */
#define SSP_RISR_RST (0x00000008ul)
/**< Raw interrupt status register reset value*/
#define SSP_MISR_RST (0x00000000ul)
/**< Masked interrupt status register reset value */
#define SSP_ICR_RST (0x00000000ul)
/**< Interrupt clear register reset value */
/*******************************************************************************
***************************** SSP MACROS DEFINITION **************************
*******************************************************************************/
/** Set CR0 register */
#define CSP_SSP_SET_CR0(ssp, val) ((ssp)->CR0 = (val & 0xFFFFFFCFul))
/** Get CR0 register */
#define CSP_SSP_GET_CR0(ssp) ((ssp)->CR0)
/** Set CR1 register */
#define CSP_SSP_SET_CR1(ssp, val) ((ssp)->CR1 = (val & 0xFFFF000Ful))
/** Get CR1 register */
#define CSP_SSP_GET_CR1(ssp) ((ssp)->CR1)
/** Set DR register */
#define CSP_SSP_SET_DR(ssp, val) ((ssp)->DR = (val))
/** Get DR register */
#define CSP_SSP_GET_DR(ssp) ((ssp)->DR)
/** Get SR register */
#define CSP_SSP_GET_SR(ssp) ((ssp)->SR)
/** Set CPSR register */
#define CSP_SSP_SET_CPSR(ssp, val) ((ssp)->CPSR = (val & 0xFFFF00FFul))
/** Get CPSR register */
#define CSP_SSP_GET_CPSR(ssp) ((ssp)->CPSR)
/** Set IMSC register */
#define CSP_SSP_SET_IMSCR(ssp, val) ((ssp)->IMSC = (val & 0xFFFF000Ful))
/** Get IMSC register */
#define CSP_SSP_GET_IMSCR(ssp) ((ssp)->IMSCR)
/** Get RIS register */
#define CSP_SSP_GET_RISR(ssp) ((ssp)->RISR)
/** Get MIS register */
#define CSP_SSP_GET_MISR(ssp) ((ssp)->MISR
/** Set ICR register */
#define CSP_SSP_SET_ICR(ssp, val) ((ssp)->ICR = (val & 0xFFFF0003ul))
/** @addtogroup spi Registers RST Value
* @{
*/
#define SPI_CR0_RST (0x00000000) /**< CR0 reset value */
#define SPI_CR1_RST (0x00000000) /**< CR1 reset value */
#define SPI_DR_RST (0x00000000) /**< DR reset value */
#define SPI_SR_RST (0x00000003) /**< SR reset value */
#define SPI_CPSR_RST (0x00000000) /**< CPSR reset value */
#define SPI_IMSCR_RST (0x00000000) /**< IMSCR reset value */
#define SPI_RISR_RST (0x00000008) /**< RISR reset value */
#define SPI_MISR_RST (0x00000000) /**< MISR reset value */
#define SPI_ICR_RST (0x00000000) /**< ICR reset value */
/**
* @brief SPI INT MASK SET/CLR Set
*/
typedef enum
{
SPI_PORIM = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Receive overflow Interrupt */
SPI_RTIM = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Receive timeout Interrupt */
SPI_RXIM = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Receive FIFO Interrupt */
SPI_TXIM = ((CSP_REGISTER_T)(0x01ul << 3)) /**< transmit FIFO Interrupt */
}SPI_IMSCR_TypeDef;
/**
* @brief SPI IO selection
*/
typedef enum
{
SPI_G0 = 0,
SPI_G1 = 1,
SPI_G2 = 2
}SPI_IO_TypeDef;
/**
* @brief SPI Data Size selection
*/
typedef enum
{
SPI_DATA_SIZE_4BIT = 3,
SPI_DATA_SIZE_5BIT = 4,
SPI_DATA_SIZE_6BIT = 5,
SPI_DATA_SIZE_7BIT = 6,
SPI_DATA_SIZE_8BIT = 7,
SPI_DATA_SIZE_9BIT = 8,
SPI_DATA_SIZE_10BIT = 9,
SPI_DATA_SIZE_11BIT = 10,
SPI_DATA_SIZE_12BIT = 11,
SPI_DATA_SIZE_13BIT = 12,
SPI_DATA_SIZE_14BIT = 13,
SPI_DATA_SIZE_15BIT = 14,
SPI_DATA_SIZE_16BIT = 15
}SPI_DATA_SIZE_TypeDef;
/**
* @brief SPI SPO selection
*/
typedef enum
{
SPI_SPO_0 = 0,
SPI_SPO_1 = 1
}SPI_SPO_TypeDef;
/**
* @brief SPI SPH selection
*/
typedef enum
{
SPI_SPH_0 = 0,
SPI_SPH_1 = 1
}SPI_SPH_TypeDef;
/**
* @brief SPI LBM selection
*/
typedef enum
{
SPI_LBM_0 = 0,
SPI_LBM_1 = 1
}SPI_LBM_TypeDef;
/**
* @brief SPI RXIFLSEL selection
*/
typedef enum
{
SPI_RXIFLSEL_1_8 = 0x01,
SPI_RXIFLSEL_1_4 = 0x02,
SPI_RXIFLSEL_1_2 = 0x04
}SPI_RXIFLSEL_TypeDef;
/******************************************************************************
********************** SPI External Functions Declaration **********************
******************************************************************************/
extern void SPI_DeInit(void);
extern void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP);
extern void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR );
extern void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR);
extern void SPI_WRITE_BYTE(U16_T wdata);
extern void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth);
extern void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X);
extern void SPI_Int_Enable(void);
extern void SPI_Int_Disable(void);
extern void SPI_Wakeup_Enable(void);
extern void SPI_Wakeup_Disable(void);
#endif /**< apt32f102_spi_H */
/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/

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Source/include/apt32f102_syscon.h Normal file
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/*
******************************************************************************
* @file main.c
* @author APT AE Team
* @version V1.09
* @date 2021/07/30
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_syscon_H
#define _apt32f102_syscon_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
/******************************************************************************
************************* syscon Registers Definition *************************
******************************************************************************/
/** @addtogroup SYSCON Registers Reset Value
* @{
*/
#define SYSCON_IDCCR_RST ((CSP_REGISTER_T)0x00000001)
#define SYSCON_GCER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_GCDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_GCSR_RST ((CSP_REGISTER_T)0x00081103)
#define SYSCON_CKST_RST ((CSP_REGISTER_T)0x00000103)
#define SYSCON_RAMCHK_RST ((CSP_REGISTER_T)0x0000ffff)
#define SYSCON_EFLCHK_RST ((CSP_REGISTER_T)(0X0<<24)|0xffffff)
#define SYSCON_SCLKCR_RST ((CSP_REGISTER_T)0xD22Dul<<16)
#define SYSCON_PCLKCR_RST ((CSP_REGISTER_T)0x00000100)
#define SYSCON_PCER0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCDR0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCSR0_RST ((CSP_REGISTER_T)0x005107d1)
#define SYSCON_PCER1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCDR1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_PCSR1_RST ((CSP_REGISTER_T)0x3023f80)
#define SYSCON_OSTR_RST ((CSP_REGISTER_T)0x70ff3bff)
#define SYSCON_LVDCR_RST ((CSP_REGISTER_T)0x0000000a)
#define SYSCON_CLCR_RST ((CSP_REGISTER_T)0x00000100)
#define SYSCON_PWRCR_RST ((CSP_REGISTER_T)0x141f1f00)
#define SYSCON_IMER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IMDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IMCR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IAR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_ICR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_RISR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_MISR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIRT_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIFT_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIER_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIDR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIMR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIAR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXICR_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EXIRS_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_IWDCR_RST ((CSP_REGISTER_T)0x0000070C)
#define SYSCON_IWDCNT_RST ((CSP_REGISTER_T)0x000003fe)
#define SYSCON_PWROPT_RST ((CSP_REGISTER_T)0x00004040)
#define SYSCON_EVTRG_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EVPS_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_EVSWF_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG0_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG1_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG2_RST ((CSP_REGISTER_T)0x00000000)
#define SYSCON_UREG3_RST ((CSP_REGISTER_T)0x00000000)
//SCLKCR
#define SYSCLK_KEY (0xD22Dul<<16)
//PCLK CONTROL
#define PCLK_KEY (0xC33Cul<<16)
//IDCCR
#define CLKEN (0X01ul)
#define CPUFTRST_EN (0X00<<1)
#define CPUFTRST_DIS (0XA<<1)
#define SWRST (0X01ul<<7)
#define IDCCR_KEY (0xE11Eul<<16)
//LVDCR
#define LVDFLAG (0x01ul<<15) //0: VDD is higher than LVD threshold selected with INTDET_LVL bits. 1: VDD is lower than LVD threshold selected with INTDET_LVL bits
#define LVD_KEY (0xB44Bul<<16)
//IECR IEDR IAR ICR IMSR RISR ISR
//Interrupt Enable/Disable/Active/Clear Control Register
//Interrupt Masking/Raw Interrupt/Masked Status Register
#define ISOSC_ST (0x01ul)
#define IMOSC_ST (0x01ul<<1)
#define ESOSC_ST (0x01ul<<2)
#define EMOSC_ST (0x01ul<<3)
#define HFOSC_ST (0x01ul<<4)
#define SYSCLK_ST (0x01ul<<7)
#define IWDT_INT_ST (0x01ul<<8)
#define WKI_INT_ST (0x01ul<<9)
#define RAMERRINT_ST (0X01ul<<10)
#define LVD_INT_ST (0x01ul<<11)
#define HWD_ERR_ST (0X01ul<<12)
#define EFL_ERR_ST (0X01ul<<13)
#define OPTERR_INT (0X01ul<<14)
#define EM_CMLST_ST (0x01ul<<18)
#define EM_EVTRG0_ST (0x01ul<<19)
#define EM_EVTRG1_ST (0x01ul<<20)
#define EM_EVTRG2_ST (0x01ul<<21)
#define EM_EVTRG3_ST (0x01ul<<22)
#define CMD_ERR_ST (0x01ul<<29)
//RSR
//SYSCON Reset Status Register
#define PORST (0X01ul)
#define LVRRST (0X01ul<<1)
#define EXTRST (0X01ul<<2)
#define ALVRST (0X01ul<<3)
#define IWDRST (0X01ul<<4)
#define EMCMRST (0X01ul<<6)
#define CPURSTREQ (0X01ul<<7)
#define SWRST_RSR (0X01ul<<8)
#define CPUFAULT_RSR (0X01ul<<9)
#define SRAM_RSR (0X01ul<<11)
#define EFL_ERR (0X01ul<<12)
#define WWDTRST (0X01ul<<13)
//IWDCR
#define Check_IWDT_BUSY (0x01ul<<12) //Indicates the independent watchdog operation
#define IWDT_KEY (0x8778ul<<16)
//IWDCNT
#define CLR_IWDT (0x5aul<<24)
//IWDEDR
#define Enable_IWDT (0x0)
#define Disable_IWDT (0x55aa)
#define IWDTEDR_KEY (0x7887ul<<16)
#define CORET_IRQ 0
#define SYSCON_IRQ 1
#define IFC_IRQ 2
#define ADC_IRQ 3
#define EPT0_IRQ 4
#define WWDT_IRQ 6
#define EXI0_IRQ 7
#define EXI1_IRQ 8
#define GPT0_IRQ 9
#define RTC_IRQ 12
#define UART0_IRQ 13
#define UART1_IRQ 14
#define UART2_IRQ 15
#define I2C_IRQ 17
#define SPI_IRQ 19
#define SIO_IRQ 20
#define EXI2_IRQ 21
#define EXI3_IRQ 22
#define EXI4_IRQ 23
#define CA_IRQ 24
#define TKEY_IRQ 25
#define LPT_IRQ 26
#define BT0_IRQ 28
#define BT1_IRQ 29
/**
* @brief SYSCON General Control
*/
typedef enum
{
ENDIS_ISOSC = (CSP_REGISTER_T)(0x01ul),
ENDIS_IMOSC = (CSP_REGISTER_T)(0x01ul<<1),
ENDIS_EMOSC = (CSP_REGISTER_T)(0x01ul<<3),
ENDIS_HFOSC = (CSP_REGISTER_T)(0x01ul<<4),
ENDIS_IDLE_PCLK = (CSP_REGISTER_T)(0x01ul<<8),
ENDIS_SYSTICK = (CSP_REGISTER_T)(0x01ul<<11)
}SYSCON_General_CMD_TypeDef;
/**
* @brief Selected SYSCON CLK
*/
typedef enum
{
SYSCLK_IMOSC = (CSP_REGISTER_T)0x0ul, //IMOSC selected
SYSCLK_EMOSC = (CSP_REGISTER_T)0x1ul, //EMOSC selected
SYSCLK_HFOSC = (CSP_REGISTER_T)0x2ul, //HFOSC selected
SYSCLK_ISOSC = (CSP_REGISTER_T)0x4ul //ISOSC selected
}SystemCLK_TypeDef;
/**
* @brief SYSCON CLK Div
*/
typedef enum
{
HCLK_DIV_1 = (CSP_REGISTER_T)(0x1ul<<8),
HCLK_DIV_2 = (CSP_REGISTER_T)(0x2ul<<8),
HCLK_DIV_3 = (CSP_REGISTER_T)(0x3ul<<8),
HCLK_DIV_4 = (CSP_REGISTER_T)(0x4ul<<8),
HCLK_DIV_5 = (CSP_REGISTER_T)(0x5ul<<8),
HCLK_DIV_6 = (CSP_REGISTER_T)(0x6ul<<8),
HCLK_DIV_7 = (CSP_REGISTER_T)(0x7ul<<8),
HCLK_DIV_8 = (CSP_REGISTER_T)(0x8ul<<8),
HCLK_DIV_12 = (CSP_REGISTER_T)(0x9ul<<8),
HCLK_DIV_16 = (CSP_REGISTER_T)(0xAul<<8),
HCLK_DIV_24 = (CSP_REGISTER_T)(0xBul<<8),
HCLK_DIV_32 = (CSP_REGISTER_T)(0xCul<<8),
HCLK_DIV_64 = (CSP_REGISTER_T)(0xDul<<8),
HCLK_DIV_128 = (CSP_REGISTER_T)(0xEul<<8),
HCLK_DIV_256 = (CSP_REGISTER_T)(0xFul<<8)
}SystemCLK_Div_TypeDef;
/**
* @brief PCLK Div
*/
typedef enum
{
PCLK_DIV_1 = (CSP_REGISTER_T)(0x00ul<<8),
PCLK_DIV_2 = (CSP_REGISTER_T)(0x01ul<<8),
PCLK_DIV_4 = (CSP_REGISTER_T)(0x02ul<<8),
PCLK_DIV_8 = (CSP_REGISTER_T)(0x04ul<<8),
PCLK_DIV_16 = (CSP_REGISTER_T)(0x08ul<<8)
}PCLK_Div_TypeDef;
/**
* @brief LVD enable and disable
*/
typedef enum
{
ENABLE_LVDEN = (CSP_REGISTER_T)0x00, //Power down LVD module
DISABLE_LVDEN = (CSP_REGISTER_T)0x0a //Power down LVD module
}X_LVDEN_TypeDef;
/**
* @brief Detection voltage level to trigger the LVD interrupt
*/
typedef enum
{
INTDET_LVL_2_1V = (CSP_REGISTER_T)(0X00ul<<8), //2.1V
INTDET_LVL_2_4V = (CSP_REGISTER_T)(0X01ul<<8), //2.4V
INTDET_LVL_2_7V = (CSP_REGISTER_T)(0X02ul<<8), //2.7V
INTDET_LVL_3_0V = (CSP_REGISTER_T)(0X03ul<<8), //3.0V
INTDET_LVL_3_3V = (CSP_REGISTER_T)(0X04ul<<8), //3.3V
INTDET_LVL_3_6V = (CSP_REGISTER_T)(0X05ul<<8), //3.6V
INTDET_LVL_3_9V = (CSP_REGISTER_T)(0X06ul<<8), //3.9V
}INTDET_LVL_X_TypeDef;
/**
* @brief Detection voltage level to generate reset
*/
typedef enum
{
RSTDET_LVL_1_9V = (CSP_REGISTER_T)(0X00ul<<12), //1.9V
RSTDET_LVL_2_2V = (CSP_REGISTER_T)(0X01ul<<12), //2.2V
RSTDET_LVL_2_5V = (CSP_REGISTER_T)(0X02ul<<12), //2.5V
RSTDET_LVL_2_8V = (CSP_REGISTER_T)(0X03ul<<12), //2.8V
RSTDET_LVL_3_1V = (CSP_REGISTER_T)(0X04ul<<12), //3.1V
RSTDET_LVL_3_4V = (CSP_REGISTER_T)(0X05ul<<12), //3.4V
RSTDET_LVL_3_7V = (CSP_REGISTER_T)(0X06ul<<12), //3.7V
RSTDET_LVL_4_0V = (CSP_REGISTER_T)(0X07ul<<12) //4.0V
}RSTDET_LVL_X_TypeDef;
/**
* @brief Detection voltage level to trigger the LVD interrupt
*/
typedef enum
{
ENABLE_LVD_INT = (CSP_REGISTER_T)(0X01ul<<11), //ENABLE LVD INT
DISABLE_LVD_INT = (CSP_REGISTER_T)(0X00ul<<11) //DISABLE LVD INT
}X_LVD_INT_TypeDef;
/**
* @brief EXI PIN
*/
typedef enum
{
EXI_PIN0 = (CSP_REGISTER_T)(0X01ul),
EXI_PIN1 = (CSP_REGISTER_T)(0X01ul<<1),
EXI_PIN2 = (CSP_REGISTER_T)(0X01ul<<2),
EXI_PIN3 = (CSP_REGISTER_T)(0X01ul<<3),
EXI_PIN4 = (CSP_REGISTER_T)(0X01ul<<4),
EXI_PIN5 = (CSP_REGISTER_T)(0X01ul<<5),
EXI_PIN6 = (CSP_REGISTER_T)(0X01ul<<6),
EXI_PIN7 = (CSP_REGISTER_T)(0X01ul<<7),
EXI_PIN8 = (CSP_REGISTER_T)(0X01ul<<8),
EXI_PIN9 = (CSP_REGISTER_T)(0X01ul<<9),
EXI_PIN10 = (CSP_REGISTER_T)(0X01ul<<10),
EXI_PIN11 = (CSP_REGISTER_T)(0X01ul<<11),
EXI_PIN12 = (CSP_REGISTER_T)(0X01ul<<12),
EXI_PIN13 = (CSP_REGISTER_T)(0X01ul<<13),
EXI_PIN14 = (CSP_REGISTER_T)(0X01ul<<14),
EXI_PIN15 = (CSP_REGISTER_T)(0X01ul<<15),
EXI_PIN16 = (CSP_REGISTER_T)(0X01ul<<16),
EXI_PIN17 = (CSP_REGISTER_T)(0X01ul<<17),
EXI_PIN18 = (CSP_REGISTER_T)(0X01ul<<18),
EXI_PIN19 = (CSP_REGISTER_T)(0X01ul<<19),
}SYSCON_EXIPIN_TypeDef;
/**
* @brief EXT register
*/
typedef enum
{
_EXIRT = 0,
_EXIFT = 1,
}EXI_tringer_mode_TypeDef;
/**
* @brief SYSON IWDT TIME SET
*/
typedef enum
{
IWDT_TIME_125MS = (CSP_REGISTER_T)(0x00ul<<8), //IWDT_TIME 0x00fff
IWDT_TIME_250MS = (CSP_REGISTER_T)(0x01ul<<8), //IWDT_TIME 0x01fff
IWDT_TIME_500MS = (CSP_REGISTER_T)(0x02ul<<8), //IWDT_TIME 0x03fff
IWDT_TIME_1S = (CSP_REGISTER_T)(0x03ul<<8), //IWDT_TIME 0x07fff
IWDT_TIME_2S = (CSP_REGISTER_T)(0x04ul<<8), //IWDT_TIME 0x0ffff //2M ISOSC 2sec
IWDT_TIME_3S = (CSP_REGISTER_T)(0x05ul<<8), //IWDT_TIME 0x16fff
IWDT_TIME_4S = (CSP_REGISTER_T)(0x06ul<<8), //IWDT_TIME 0x1ffff
IWDT_TIME_8S = (CSP_REGISTER_T)(0x07ul<<8) //IWDT_TIME 0x3ffff
}IWDT_TIME_TypeDef;
/**
* @brief SYSON IWDT TIME DIV SET
*/
typedef enum
{
IWDT_INTW_DIV_1 = (0x00ul<<2), //1/8 of IWDT_TIME
IWDT_INTW_DIV_2 = (0x01ul<<2), //2/8 of IWDT_TIME
IWDT_INTW_DIV_3 = (0x02ul<<2), //3/8 of IWDT_TIME
IWDT_INTW_DIV_4 = (0x03ul<<2), //4/8 of IWDT_TIME
IWDT_INTW_DIV_5 = (0x04ul<<2), //5/8 of IWDT_TIME
IWDT_INTW_DIV_6 = (0x05ul<<2), //6/8 of IWDT_TIME
IWDT_INTW_DIV_7 = (0x06ul<<2) //7/8 of IWDT_TIME
}IWDT_TIMEDIV_TypeDef;
/**
* @brief IMOSC SELECTE SET
*/
typedef enum
{
IMOSC_SELECTE_5556K = (0x00ul<<0),
IMOSC_SELECTE_4194K = (0x01ul<<0),
IMOSC_SELECTE_2097K = (0x02ul<<0),
IMOSC_SELECTE_131K = (0x03ul<<0)
}IMOSC_SELECTE_TypeDef;
/**
* @brief HFOSC SELECTE SET
*/
typedef enum
{
HFOSC_SELECTE_48M = (0x0ul<<4),
HFOSC_SELECTE_24M = (0x1ul<<4),
HFOSC_SELECTE_12M = (0x2ul<<4),
HFOSC_SELECTE_6M = (0x3ul<<4)
}HFOSC_SELECTE_TypeDef;
/**
* @brief EM Filter set
*/
typedef enum
{
EM_FLSEL_5ns = (0x0ul<<26),
EM_FLSEL_10ns = (0x1ul<<26),
EM_FLSEL_15ns = (0x2ul<<26),
EM_FLSEL_20ns = (0x3ul<<26)
}EM_Filter_TypeDef;
/**
* @brief EM Filter CMD
*/
typedef enum
{
EM_FLEN_DIS = (0x0ul<<25),
EM_FLEN_EN = (0x1ul<<25)
}EM_Filter_CMD_TypeDef;
/**
* @brief EM LFSEL BIT
*/
typedef enum
{
EM_LFSEL_DIS = (0x0ul<<10),
EM_LFSEL_EN = (0x1ul<<10)
}EM_LFSEL_TypeDef;
/**
* @brief EM Systemclk data
*/
typedef enum
{
EMOSC_24M = 0,
EMOSC_16M = 1,
EMOSC_12M = 2,
EMOSC_8M = 3,
EMOSC_4M = 4,
EMOSC_36K = 5,
IMOSC = 6,
ISOSC = 7,
HFOSC_48M = 8,
HFOSC_24M = 9,
HFOSC_12M = 10,
HFOSC_6M = 11
}SystemClk_data_TypeDef;
typedef enum
{
CLO_PA02 = 0, //PA0.0 as clo
CLO_PA08 = 1, //PA0.8 as clo
}CLO_IO_TypeDef;
typedef enum
{
INTDET_POL_fall = (1<<6), //fall Trigger
INTDET_POL_X_rise = (2<<6), //rise Trigger
INTDET_POL_X_riseORfall = (3<<6), //fall or rise Trigger
}INTDET_POL_X_TypeDef;
typedef enum
{
//IOMAP0
PIN_I2C_SCL = 0X00, //
PIN_I2C_SDA = 0X01, //
PIN_GPT_CHA = 0X02, //
PIN_GPT_CHB = 0X03, //
PIN_SPI_MOSI = 0X04, //
PIN_SPI_MISO = 0X05, //
PIN_SPI_SCK = 0X06, //
PIN_SPI_NSS = 0X07, //
//IOMAP1
PIN_UART0_RX = 0X10, //
PIN_UART0_TX = 0X11, //
PIN_EPT_CHAX = 0X12, //
PIN_EPT_CHBX = 0X13, //
PIN_EPT_CHCX = 0X14, //
PIN_EPT_CHAY = 0X15, //
PIN_EPT_CHBY = 0X16, //
PIN_EPT_CHCY = 0X17, //
}IOMAP_DIR_TypeDef;
/**
* @brief CLOMX Systemclk data
*/
typedef enum
{
CLO_ISCLK = 0,
CLO_IMCLK = 1,
CLO_EMCLK = 3,
CLO_HFCLK = 4,
CLO_RTCCLK = 6,
CLO_PCLK = 7,
CLO_HCLK = 8,
CLO_IWDTCLK = 9,
CLO_SYSCLK = 0X0D,
}SystemClk_CLOMX_TypeDef;
/**
* @brief CLOMX Systemclk data
*/
typedef enum
{
CLO_DIV0 = 1,
CLO_DIV4 = 0,
CLO_DIV2 = 2,
CLO_DIV8 = 4,
CLO_DIV16 = 5,
}SystemClk_CLODIV_TypeDef;
/** @addtogroup SYSCON_Exported_functions
* @{
*/
extern void SYSCON_RST_VALUE(void);
extern void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X );
extern void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X);
extern void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x );
extern void SYSCON_WDT_CMD(FunctionalStatus NewState);
extern void SYSCON_IWDCNT_Reload(void);
extern void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X );
extern void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X);
extern void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode);
extern void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN);
extern void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io);
extern U32_T SYSCON_Read_CINF0(void);
extern U32_T SYSCON_Read_CINF1(void);
extern void SYSCON_INT_Priority(void);
extern void EXI0_Int_Enable(void);
extern void EXI0_Int_Disable(void);
extern void EXI1_Int_Enable(void);
extern void EXI1_Int_Disable(void);
extern void EXI2_Int_Enable(void);
extern void EXI2_Int_Disable(void);
extern void EXI3_Int_Enable(void);
extern void EXI3_Int_Disable(void);
extern void EXI4_Int_Enable(void);
extern void EXI4_Int_Disable(void);
extern void SYSCON_Int_Enable(void);
extern void SYSCON_Int_Disable(void);
extern void PCLK_goto_idle_mode(void);
extern void PCLK_goto_deepsleep_mode(void);
extern void LVD_Int_Enable(void);
extern void LVD_Int_Disable(void);
extern void IWDT_Int_Enable(void);
extern void IWDT_Int_Disable(void);
extern void EXI0_WakeUp_Enable(void);
extern void EXI0_WakeUp_Disable(void);
extern void EXI1_WakeUp_Enable(void);
extern void EXI1_WakeUp_Disable(void);
extern void EXI2_WakeUp_Enable(void);
extern void EXI2_WakeUp_Disable(void);
extern void EXI3_WakeUp_Enable(void);
extern void EXI3_WakeUp_Disable(void);
extern void EXI4_WakeUp_Enable(void);
extern void EXI4_WakeUp_Disable(void);
extern void SYSCON_WakeUp_Enable(void);
extern void SYSCON_WakeUp_Disable(void);
extern void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE);
extern void SYSCON_Software_Reset(void);
extern void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X);
extern void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X);
extern void SystemCLK_Clear(void);
extern void GPIO_Remap(CSP_GPIO_T *GPIOx,uint8_t bit,IOMAP_DIR_TypeDef iomap_data);
extern void SYSCON_CLO_SRC_SET(SystemClk_CLOMX_TypeDef clomxr,SystemClk_CLODIV_TypeDef clodivr);
extern void Set_INT_Priority(U8_T int_name,U8_T int_level);
extern U32_T Read_Reset_Status(void);
#endif /**< apt32f102_syscon_H */
/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_tkey.h
* @author APT AE Team
* @version V1.01
* @date 2019/04/05
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#ifndef _apt32f102_TK_H
#define _apt32f102_TK_H
#include "apt32f102.h"
/**
* @brief tkey mode register
*/
typedef enum
{
TK_HM_DIS = 0<<0,
TK_HM_EN = 1<<0,
}TKEY_HMEN_TypeDef;
/**
* @brief tkey mode register
*/
typedef enum
{
TK_SINGLE = 0<<1,
TK_SEQ = 1<<1,
}TKEY_MODE_TypeDef;
/**
* @brief tkey ckspr register
*/
typedef enum
{
TK_CKSPR_DIS = 0<<9,
TK_CKSPR_EN = 1<<9,
}TKEY_CKSPR_TypeDef;
/**
* @brief tkey CKRND register
*/
typedef enum
{
TK_CKRND_DIS = 0<<10,
TK_CKRND_EN = 1<<10,
}TKEY_CKRND_TypeDef;
/**
* @brief tkey CKFEQ register
*/
typedef enum
{
TK_CKFEQ_LOW = 0<<11,
TK_CKREQ_HIGH = 1<<11,
}TKEY_CKFEQ_TypeDef;
/**
* @brief tkey RSSEL register
*/
typedef enum
{
TK_RSSEL_OVW = 0<<12,
TK_RSSEL_OverTHR = 1<<12,
}TKEY_RSSEL_TypeDef;
/**
* @brief tkey IDLEP register
*/
typedef enum
{
TK_IDLEP_DIS = 0<<14,
TK_IDLEP_EN = 1<<14,
}TKEY_IDLEP_TypeDef;
/**
* @brief tkey DSR register
*/
typedef enum
{
TK_DSR_Z = 0<<16,
TK_DSR_LOW = 1<<16,
TK_DSR_HIGH = 2<<16,
}TKEY_DSR_TypeDef;
/**
* @brief tkey TSCANSTB register
*/
typedef enum
{
TK_STB_1 = 0<<20,
TK_STB_2 = 1<<20,
TK_STB_3 = 2<<20,
TK_STB_4 = 3<<20,
}TKEY_TSSTB_TypeDef;
/**
* @brief tkey OTHRCN register
*/
typedef enum
{
TK_DCKDIV_0 = 0<<12,
TK_DCKDIV_2 = 1<<12,
TK_DCKDIV_4 = 2<<12,
TK_DCKDIV_8 = 3<<12,
}TKEY_DCKDIV_TypeDef;
#define TK_PSEL_FVR 0
#define TK_PSEL_AVDD 1
#define TK_FVR_2048V 0
#define TK_FVR_4096V 1
#define TK_EC_1V 0
#define TK_EC_2V 1
#define TK_EC_3V 2
#define TK_EC_3_6V 3
U32_T TK_IO_ENABLE; //Tkey IO使能 bit=1 表示使能对应的 TCHx 做 touch key 功能，低位至高位的顺序对应 TCH0~TCH16
U16_T TK_senprd[17]; //Tkey 通道扫描周期配置 值越大灵敏度越高，但不能超过理论值否则按键无法扫描通过，常用值不大于 150
U16_T TK_Triggerlevel[17]; //Tkey 通道触发门槛值配置 值越大门槛值越高，取值范围为按键差值的 50%~60%，未使用的通道设置成 0xFF
U8_T Press_debounce_data; //Tkey 触发去抖配置 按下去抖 1~10，默认配置为 5
U8_T Release_debounce_data; //Tkey 释放去抖配置 释放去抖 1~10，默认配置为 5
U16_T TK_icon[17];
U8_T MultiTimes_Filter; //OFFSET 滤波倍数 大于等于 4 时，表示开启相应的倍数滤波；小于 4 时表示倍数滤波关闭；默认配置关闭
U8_T Valid_Key_Num; //最多有效按键个数 此配置表示允许同时按下按键时最多有效个数。默认为 4
U8_T Key_mode; //Tkey 按键模式 0 表示单键模式，1 表示多键模式
U8_T Base_Speed; //Baseline 更新速度 数值越小，baseline 更新速度越快；数值越大，baseline 更新速度越慢；默认为 10 约 100ms
U32_T TK_longpress_time; //按键长按强制更新时间设置 长按键强制更新配置。时间= TK_longpress_time*1s；默认 16 秒
U32_T TK_BaseCnt; //按键扫描基准时间配置 若系统时钟修改时需要修改此参数，保证基准时间为 10ms；计算公式 TK_BaseCnt=10ms*PCLK/8-1，默认 59999 数值基于 48MHz
U16_T TK_PSEL_MODE;
U16_T TK_FVR_LEVEL;
U16_T TK_EC_LEVEL;
U8_T TK_Lowpower_mode;
U8_T TK_Lowpower_level;
U8_T TK_Wakeup_level;
//****************************************************************
#define TK_CLK_EN (TKEY->CLKEN|=0X01)
#define TK_CLK_DIS (TKEY->CLKEN&=0XFFE)
#define TK_SCANTIME_DIS (0<<12)
#define TK_SCANTIME_1ms (1<<12)
#define TK_SCANTIME_1_5ms (2<<12)
#define TK_SCANTIME_2ms (3<<12)
#define TK_SCANTIME_3ms (4<<12)
#define TK_SCANTIME_5ms (5<<12)
#define TK_SCANTIME_10ms (6<<12)
#define TK_SCANTIME_100ms (7<<12)
#define TKEY_TCHEN(val) (val) /**< TKEY CH Enable */
#define TKEY_ICON(val) (((val) & 0x0Ful) << 8)
#define TKEY_START (0x01ul << 0)
#define TKEY_SINDNE (0x01ul << 0)
#define TKEY_DNE (0x01ul << 1)
#define TKEY_THR (0x01ul << 2)
#define TKEY_FLW (0x01ul << 3)
#define TKEY_OVW (0x01ul << 4)
#define TKEY_TIME (0x01ul << 5)
#define TCH_EN(val) (0x01<<val)
extern void tk_init(void);
extern void tk_Reinit(void);
extern void tk_prgm(void);
extern void TK_Baseline_prog(void);
extern void tk_parameter_init(void);
extern volatile U16_T offset_data0_abs[17];
extern volatile U16_T offset_data1_abs[17];
extern volatile U16_T offset_data2_abs[17];
extern volatile U16_T sampling_data0[17];
extern volatile U16_T baseline_data0[17];
extern volatile S16_T offset_data0[17];
extern volatile U16_T sampling_data1[17];
extern volatile U16_T baseline_data1[17];
extern volatile S16_T offset_data1[17];
extern volatile U16_T sampling_data2[17];
extern volatile U16_T baseline_data2[17];
extern volatile S16_T offset_data2[17];
extern volatile U32_T Key_Map;
extern void TK_setup_sleep(void);
extern void TK_quit_sleep(void);
extern volatile U8_T base_update_f;
#endif /**< apt32f102_tkey.h */

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/*
******************************************************************************
* @file apt32f102_types_local.h
* @author APT AE Team
* @version V1.08
* @date 2021/06/21
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
#ifndef TYPES_LOCAL_H
#define TYPES_LOCAL_H
/**************************************************************************/
/**************************************************************************
STANDARD DEFINES
**************************************************************************/
#define NIL '\000'
#define TRUE 1
#define FALSE 0
#define YES 1
#define NO 0
#define ON 1
#define OFF 0
#define GOOD 1
#define BAD 0
#define BELL 7 /* Ring the bell */
#define MAX_SINT16 32767
#define CPNULL ((char *)0)
#define NONENTRY -1.0E12
#define DPIE (DOUBLE)3.141592653589793
/* other stuff... */
#define STRNCPY(a,b,c) strncpy (a,b,c); (*((a)+(c)) = 0x00);
/**************************************************************************
STANDARD TYPEDEFS
The ANSI C std defines:
short <= int <= long
char >= 8 bits
short >= 16 bits
long >= 32 bits
(from Harbison & Steele, "C, A Ref. Manual" 3rd ed. p. 99)
so all ANSI C compliant compilers will accept the following.
**************************************************************************/
#ifndef CSP_TYPES_H
#define CSP_TYPES_H
/* Signed Types */
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;
/* Unsigned Types */
typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;
/* Float Types */
typedef float F32_T;
typedef double F64_T;
/* Boolean types declared as U8_T, as enums are generated as 16 bit */
typedef U8_T B_T;
/* Definitions for the two members of the Boolean type */
#ifndef FALSE
#define FALSE ((B_T) 0)
#endif
#ifndef TRUE
#define TRUE ((B_T) 1)
#endif
/* UNUSED Definition for unused Interrupt numbers * and unused PDC channels */
/* in the CHIP structure. (cf. CSP.C file) */
#ifndef UNUSED
#define UNUSED ((U8_T) 0xFF)
#endif
/* NULL definition */
#ifndef NULL
#define NULL 0
#endif
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
/******************************************************************************
* Peripherals Type
******************************************************************************/
typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;
#endif /* CSP_TYPE_H */
/* define 8 bit types */
typedef unsigned char UINT8;
typedef signed char SINT8;
/* define 16 bit types */
typedef unsigned short UINT16;
typedef signed short SINT16;
/* define 32 bit types */
typedef unsigned long UINT32;
typedef signed long SINT32;
typedef void VOID;
typedef signed char CHAR; /* be careful of EOF!!! (EOF = -1) */
typedef unsigned char BOOL;
typedef signed long TIME_T;
typedef float SINGLE;
#ifdef DOUBLE
#undef DOUBLE
#endif
typedef double DOUBLE;
typedef struct
{
unsigned bit0 : 1;
unsigned bit1 : 1;
unsigned bit2 : 1;
unsigned bit3 : 1;
unsigned bit4 : 1;
unsigned bit5 : 1;
unsigned bit6 : 1;
unsigned bit7 : 1;
} REG8;
typedef struct
{
unsigned bit0 : 1;
unsigned bit1 : 1;
unsigned bit2 : 1;
unsigned bit3 : 1;
unsigned bit4 : 1;
unsigned bit5 : 1;
unsigned bit6 : 1;
unsigned bit7 : 1;
unsigned bit8 : 1;
unsigned bit9 : 1;
unsigned bit10: 1;
unsigned bit11: 1;
unsigned bit12: 1;
unsigned bit13: 1;
unsigned bit14: 1;
unsigned bit15: 1;
} REG16;
/**************************************************************************
STANDARD STRING TYPEDEFS
**************************************************************************/
typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
/********************************************/
/* STANDARD SYSTEM SIZES */
/********************************************/
#define SIZE_UINT8 (size_t)(sizeof (UINT8 ))
#define SIZE_SINT8 (size_t)(sizeof (SINT8 ))
#define SIZE_UINT16 (size_t)(sizeof (UINT16))
#define SIZE_SINT16 (size_t)(sizeof (SINT16))
#define SIZE_UINT32 (size_t)(sizeof (UINT32))
#define SIZE_SINT32 (size_t)(sizeof (SINT32))
#define SIZE_VOID (size_t)(sizeof (VOID ))
#define SIZE_CHAR (size_t)(sizeof (CHAR ))
#define SIZE_BOOL (size_t)(sizeof (BOOL ))
#define SIZE_TIME_T (size_t)(sizeof (TIME_T))
#define SIZE_SINGLE (size_t)(sizeof (SINGLE))
#define SIZE_DOUBLE (size_t)(sizeof (DOUBLE))
#define SIZE_STRING_3 (size_t)(sizeof (STRING_3 ))
#define SIZE_STRING_5 (size_t)(sizeof (STRING_5 ))
#define SIZE_STRING_8 (size_t)(sizeof (STRING_8 ))
#define SIZE_STRING_10 (size_t)(sizeof (STRING_10 ))
#define SIZE_STRING_12 (size_t)(sizeof (STRING_12 ))
#define SIZE_STRING_16 (size_t)(sizeof (STRING_16 ))
#define SIZE_STRING_24 (size_t)(sizeof (STRING_24 ))
#define SIZE_STRING_30 (size_t)(sizeof (STRING_30 ))
#define SIZE_STRING_32 (size_t)(sizeof (STRING_32 ))
#define SIZE_STRING_48 (size_t)(sizeof (STRING_48 ))
#define SIZE_STRING_50 (size_t)(sizeof (STRING_50 ))
#define SIZE_STRING_60 (size_t)(sizeof (STRING_60 ))
#define SIZE_STRING_80 (size_t)(sizeof (STRING_80 ))
#define SIZE_STRING_132 (size_t)(sizeof (STRING_132))
#define SIZE_STRING_256 (size_t)(sizeof (STRING_256))
#define SIZE_STRING_512 (size_t)(sizeof (STRING_512))
/**************************************************************************
STANDARD BIT MANIPULATIONS
**************************************************************************/
#define SETBIT( target, bit ) ((target) |= (1u << (bit)))
#define CLRBIT( target, bit ) ((target) &= ~(1u << (bit)))
#define TOGBIT( target, bit ) ((target) ^= (1u << (bit)))
#define ISBITSET( target, bit ) (!!((target) & (1u << (bit))))
#define ISBITCLR( target, bit ) ( !((target) & (1u << (bit))))
/**************************************************************************/
#endif
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/

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/*
******************************************************************************
* @file apt32f102_uart.h
* @author APT AE Team
* @version V1.13
* @date 2021/12/13
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_uart_H
#define _apt32f102_uart_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
typedef enum
{
UART_PAR_NONE =0<<8, //无校验位
UART_PAR_EVEN =4<<8, //偶校验位
UART_PAR_ODD =5<<8, //奇校验位
UART_PAR_SPACE =6<<8, //0校验位
UART_PAR_MARK =7<<8 //1校验位
}UART_PAR_TypeDef;
/**
* @brief UART IO setting
*/
typedef enum
{
IO_UART0 = 0,
IO_UART1 = 1,
IO_UART2 = 2,
}UART_NUM_TypeDef;
/*****************************************************************************
************************** UART Function defined *****************************
******************************************************************************/
#define UART_RESET_VALUE (0x00000000)
/** SR : UART Status Register */
#define UART_TX_FULL (0x01ul << 0) /**< Transmitter full */
#define UART_RX_FULL (0x01ul << 1) /**< Receiver full */
#define UART_TX_OVER (0x01ul << 2) /**< Transmitter buff over */
#define UART_RX_OVER (0x01ul << 3) /**< Receiver buff over */
/** CTRL : UART Control Register */
#define UART_TX (0x01ul << 0) /**< Transmitter Enable/disable */
#define UART_RX (0x01ul << 1) /**< Receiver Enable/disable */
#define UART_TX_INT (0x01ul << 2) /**< Transmitter INT Enable/disable */
#define UART_RX_INT (0x01ul << 3) /**< Receiver INT Enable/disable */
#define UART_TX_IOV (0x01ul << 4) /**< Transmitter INTOver Enable/disable*/
#define UART_RX_IOV (0x01ul << 5) /**< Receiver INTOver Enable/disable */
#define UART_PARUTY_ERR_INT (0x01ul << 7) /**< PARUTY ERROR Status */
#define UART_TX_FIFO_INT (0x01ul << 12) /**< TX fifo int Enable/disable */
#define UART_RX_FIFO_INT (0x01ul << 13) /**< RX fifo int Enable/disable */
#define UART_RX_FIFOOV_INT (0x01ul << 18) /**< RX fifo int over Enable/disable */
#define UART_TX_DONE_INT (0x01ul << 19) /**< Receiver TX done Enable/disable */
//#define UART_TEST_MODE (0x01ul << 6) /**< =1 Test mode */
/** ISR : UART Interrupt Status Register */
#define UART_TX_INT_S (0x01ul << 0) /**< Transmitter INT Status */
#define UART_RX_INT_S (0x01ul << 1) /**< Receiver INTStatus */
#define UART_TX_IOV_S (0x01ul << 2) /**< Transmitter INTOver Status */
#define UART_RX_IOV_S (0x01ul << 3) /**< Receiver INTOver Status */
#define UART_PARUTY_ERR_S (0x01ul << 4) /**< PARUTY ERROR Status */
#define UART_TXMIS_S (0x01ul << 5) /**< tx fifo Status */
#define UART_RXMIS_S (0x01ul << 6) /**< rx fifo Status */
#define UART_RORMIS_S (0x01ul << 7) /**< rx fifo over Status */
#define UART_TX_DONE_S (0x01ul << 19) /**< Receiver INTOver Status */
/** Set DATA register */
#define CSP_UART_SET_DATA(uart, val) ((uart)->DATA = (val))
/** Get DATA register */
#define CSP_UART_GET_DATA(uart) ((uart)->DATA)
/** Set SR register */
#define CSP_UART_SET_SR(uart, val) ((uart)->SR = (val))
/** Get SR register */
#define CSP_UART_GET_SR(uart) ((uart)->SR)
/** Set CTRL register */
#define CSP_UART_SET_CTRL(uart, val) ((uart)->CTRL = (val))
/** Get CTRL register */
#define CSP_UART_GET_CTRL(uart) ((uart)->CTRL)
/** Set ISR register */
#define CSP_UART_SET_ISR(uart, val) ((uart)->ISR = (val))
/** Get ISR register */
#define CSP_UART_GET_ISR(uart) ((uart)->ISR)
/** Set BRDIV register */
#define CSP_UART_SET_BRDIV(uart, val) ((uart)->BRDIV = (val))
/** Get BRDIV register */
#define CSP_UART_GET_BRDIV(uart) ((uart)->BRDIV)
/** UART External Variable Declaration */
#define UART_BUFSIZE 32
extern volatile U16_T RxDataBuf[12];
extern volatile U16_T RxDataPtr;
extern volatile U16_T TxDataPtr;
extern volatile U8_T RxDataFlag;
extern volatile U8_T TxDataFlag;
extern volatile U8_T Uart_send_Length;
extern volatile U16_T Uart_send_Length_temp;
extern volatile U8_T Uart_buffer[UART_BUFSIZE];
/** UART External Functions Declaration */
extern void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTClose(CSP_UART_T *uart);
extern void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8);
extern void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16);
extern U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16);
extern U8_T UART_ReturnRxByte(CSP_UART_T *uart);
extern U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16);
extern void UART0_DeInit(void);
extern void UART1_DeInit(void);
extern void UART2_DeInit(void);
extern void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G);
extern void UART0_Int_Enable(void);
extern void UART1_Int_Enable(void);
extern void UART2_Int_Enable(void);
extern void UART0_Int_Disable(void);
extern void UART1_Int_Disable(void);
extern void UART2_Int_Disable(void);
extern void UART0_WakeUp_Enable(void);
extern void UART1_WakeUp_Enable(void);
extern void UART2_WakeUp_Enable(void);
extern void UART0_WakeUp_Disable(void);
extern void UART1_WakeUp_Disable(void);
extern void UART2_WakeUp_Disable(void);
extern void UART0_CONFIG(void);
extern void UART1_CONFIG(void);
extern void UART2_CONFIG(void);
extern void UARTTTransmit_data_set(CSP_UART_T *uart );
extern void UARTTransmit_INT_Send(CSP_UART_T *uart );
#endif /**< apt32f102_types_local_H */
/******************* (C) COPYRIGHT 2016 APT Chip *****END OF FILE****/

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Source/include/apt32f102_wwdt.h Normal file
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/*
******************************************************************************
* @file apt32f102_wwdt.h
* @author APT AE Team
* @version V1.02
* @date 2020/11/20
******************************************************************************
*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _apt32f102_wwdt_H
#define _apt32f102_wwdt_H
/* Includes ------------------------------------------------------------------*/
#include "apt32f102.h"
#define WWDT_RESET_VALUE (0x00000000)
//--------------------------------------------------------------------------------
//-----------------------------wwdt value enum define--------------------------
//--------------------------------------------------------------------------------
/**
* @brief PSC DIV register
*/
typedef enum
{
PCLK_4096_DIV0 = (0<<8),
PCLK_4096_DIV2 = (1<<8),
PCLK_4096_DIV4 = (2<<8),
PCLK_4096_DIV8 = (3<<8),
}WWDT_PSCDIV_TypeDef;
/**
* @brief WWDT DEBUG MODE register
*/
typedef enum
{
WWDT_DBGDIS = (0<<10),
WWDT_DBGEN = (1<<10),
}WWDT_DBGEN_TypeDef;
#define WWDT_EVI 0X01
extern void WWDT_DeInit(void);
extern void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX);
extern void WWDT_CMD(FunctionalStatus NewState);
extern void WWDT_CNT_Load(U8_T cnt_data);
extern void WWDT_Int_Config(FunctionalStatus NewState);
/*************************************************************/
#endif /**< apt32f102_wwdt_H */
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/