236 lines
13 KiB
C
236 lines
13 KiB
C
/*
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******************************************************************************
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* @file apt32f102_adc.h
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* @author APT AE Team
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* @version V1.13
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_adc_H
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#define _apt32f102_adc_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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/******************************************************************************
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************************* ADC12 Registers reset value ************************
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******************************************************************************/
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#define ADC_ECR_RST (0x00000000ul) /**< ECR reset value */
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#define ADC_DCR_RST (0x00000000ul) /**< DCR reset value */
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#define ADC_PMSR_RST (0x00000000ul) /**< PMSR reset value */
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#define ADC_CR_RST (0x80000000ul) /**< CR reset value */
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#define ADC_MR_RST (0x00000000ul) /**< MR reset value */
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#define ADC_CSR_RST (0x00000000ul) /**< CSR reset value */
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#define ADC_SR_RST (0x00000000ul) /**< SR reset value */
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#define ADC_IER_RST (0x00000000ul) /**< IER reset value */
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#define ADC_IDR_RST (0x00000000ul) /**< IDR reset value */
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#define ADC_IMR_RST (0x00000000ul) /**< IMR reset value */
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#define ADC_SEQx_RST (0x00000000ul) /**< SEQx reset value */
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#define ADC_DR_RST (0x00000000ul) /**< DR reset value */
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#define ADC_CMP0_RST (0x00000000ul) /**< CMP0 reset value */
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#define ADC_CMP1_RST (0x00000000ul) /**< CMP1 reset value */
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/**
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* @brief ADC12 Control register
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*/
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typedef enum
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{
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ADC12_SWRST = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Software Reset */
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ADC12_ADCEN = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Enable */
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ADC12_ADCDIS = ((CSP_REGISTER_T)(0x01ul << 2)), /**< ADC Disable */
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ADC12_START = ((CSP_REGISTER_T)(0x01ul << 3)), /**< Start Conversion */
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ADC12_STOP = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Stop Conversion */
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ADC12_SWTRG = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Stop Conversion */
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ADC12_AVGEN = ((CSP_REGISTER_T)(0x01ul << 12)), /**< Conversion data get average */
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ADC12_AVGDIS = ((CSP_REGISTER_T)(0x00ul << 12)), /**< Conversion data get last one */
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}ADC12_Control_TypeDef;
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/**
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* @brief ADC12 IMR register
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*/
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typedef enum
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{
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//CSR SR, IER, IDR, IMR Registers
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ADC12_EOC = ((CSP_REGISTER_T)(0x01ul << 0)), /**< End Of Conversion */
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ADC12_READY = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Ready to Start */
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ADC12_OVR = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Over Run */
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ADC12_CMP0H = ((CSP_REGISTER_T)(0x01ul << 4)), /**< Higher than CMP1 */
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ADC12_CMP0L = ((CSP_REGISTER_T)(0x01ul << 5)), /**< Lower than CMP1 */
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ADC12_CMP1H = ((CSP_REGISTER_T)(0x01ul << 6)), /**< Higher than CMP2 */
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ADC12_CMP1L = ((CSP_REGISTER_T)(0x01ul << 7)), /**< Lower than CMP2 */
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ADC12_SEQ_END0 = ((CSP_REGISTER_T)(0x01ul << 16)), /**< SEQ0 Convert end */
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ADC12_SEQ_END1 = ((CSP_REGISTER_T)(0x01ul << 17)), /**< SEQ1 Convert end */
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ADC12_SEQ_END2 = ((CSP_REGISTER_T)(0x01ul << 18)), /**< SEQ2 Convert end */
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ADC12_SEQ_END3 = ((CSP_REGISTER_T)(0x01ul << 19)), /**< SEQ3 Convert end */
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ADC12_SEQ_END4 = ((CSP_REGISTER_T)(0x01ul << 20)), /**< SEQ4 Convert end */
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ADC12_SEQ_END5 = ((CSP_REGISTER_T)(0x01ul << 21)), /**< SEQ5 Convert end */
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ADC12_SEQ_END6 = ((CSP_REGISTER_T)(0x01ul << 22)), /**< SEQ6 Convert end */
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ADC12_SEQ_END7 = ((CSP_REGISTER_T)(0x01ul << 23)), /**< SEQ7 Convert end */
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ADC12_SEQ_END8 = ((CSP_REGISTER_T)(0x01ul << 24)), /**< SEQ8 Convert end */
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ADC12_SEQ_END9 = ((CSP_REGISTER_T)(0x01ul << 25)), /**< SEQ9 Convert end */
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ADC12_SEQ_END10 = ((CSP_REGISTER_T)(0x01ul << 26)), /**< SEQ10 Convert end */
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ADC12_SEQ_END11 = ((CSP_REGISTER_T)(0x01ul << 27)), /**< SEQ11 Convert end */
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ADC12_SEQ_END12 = ((CSP_REGISTER_T)(0x01ul << 28)), /**< SEQ12 Convert end */
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ADC12_SEQ_END13 = ((CSP_REGISTER_T)(0x01ul << 29)), /**< SEQ13 Convert end */
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ADC12_SEQ_END14 = ((CSP_REGISTER_T)(0x01ul << 30)), /**< SEQ14 Convert end */
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ADC12_SEQ_END15 = ((CSP_REGISTER_T)(0x01ul << 31)), /**< SEQ15 Convert end */
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/* SR Register Only */
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ADC12_ADCENS = ((CSP_REGISTER_T)(0x01ul << 8)), /**< ADC Enable Status */
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ADC12_CTCVS = ((CSP_REGISTER_T)(0x01ul << 9)) /**< Continuous Conversion Status*/
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}
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ADC12_IMR_TypeDef;
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/**
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* @brief ADC12 CLK ENABLE AND DISABLE
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*/
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typedef enum
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{
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ADC_CLK_CR = ((CSP_REGISTER_T)(0x01ul << 1)), /**< ADC Clock */
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ADC12_IPIDCODE_MASK = ((CSP_REGISTER_T)(0x3FFFFFFul << 4)), /**< ADC IPIDCODE mask */
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ADC_DEBUG_MODE = ((CSP_REGISTER_T)(0x01ul << 31)) /**< Debug Mode Enable */
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}
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ADC12_CLK_TypeDef;
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/**
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* @brief ADC12 Bit slection
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*/
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typedef enum
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{
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ADC12_12BIT = 1, /**< 12bit mode */
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ADC12_10BIT = 0, /**< 10bit mode */
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ADC12_10BITor12BIT = ((CSP_REGISTER_T)(0x01ul<<31))
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}ADC12_10bitor12bit_TypeDef;
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/**
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* @brief ADC12 Convertion mode
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*/
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typedef enum
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{
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One_shot_mode = 0,
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Continuous_mode = 1,
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CONTCV = (CSP_REGISTER_T)0x01<<31 //Continuous Conversion 0: One shot mode. 1: Continuous mode.
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}ADC12_ConverMode_TypeDef;
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/**
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* @brief ADC12 NBRCMPx selection
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*/
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typedef enum
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{
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NBRCMP0_TypeDef = 0,
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NBRCMP1_TypeDef = 1
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}
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ADC12_NBRCMPx_TypeDef;
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/**
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* @brief ADC12 NBRCMPx_HorL selection
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*/
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typedef enum
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{
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NBRCMPX_L_TypeDef = 0,
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NBRCMPX_H_TypeDef = 1
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}
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ADC12_NBRCMPx_HorL_TypeDef;
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/**
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* @brief ADC12 SEQx register
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*/
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typedef enum
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{
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ADC12_ADCIN0 = (CSP_REGISTER_T)(0x0ul), /**< ADC Analog Input 0 */
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ADC12_ADCIN1 = (CSP_REGISTER_T)(0x1ul), /**< ADC Analog Input 1 */
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ADC12_ADCIN2 = (CSP_REGISTER_T)(0x2ul), /**< ADC Analog Input 2 */
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ADC12_ADCIN3 = (CSP_REGISTER_T)(0x3ul), /**< ADC Analog Input 3 */
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ADC12_ADCIN4 = (CSP_REGISTER_T)(0x4ul), /**< ADC Analog Input 4 */
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ADC12_ADCIN5 = (CSP_REGISTER_T)(0x5ul), /**< ADC Analog Input 5 */
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ADC12_ADCIN6 = (CSP_REGISTER_T)(0x6ul), /**< ADC Analog Input 6 */
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ADC12_ADCIN7 = (CSP_REGISTER_T)(0x7ul), /**< ADC Analog Input 7 */
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ADC12_ADCIN8 = (CSP_REGISTER_T)(0x8ul), /**< ADC Analog Input 8 */
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ADC12_ADCIN9 = (CSP_REGISTER_T)(0x9ul), /**< ADC Analog Input 9 */
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ADC12_ADCIN10 = (CSP_REGISTER_T)(0x0Aul), /**< ADC Analog Input 10 */
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ADC12_ADCIN11 = (CSP_REGISTER_T)(0x0Bul), /**< ADC Analog Input 11 */
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ADC12_ADCIN12 = (CSP_REGISTER_T)(0x0Cul), /**< ADC Analog Input 12 */
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ADC12_ADCIN13 = (CSP_REGISTER_T)(0x0Dul), /**< ADC Analog Input 13 */
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ADC12_ADCIN14 = (CSP_REGISTER_T)(0x0Eul), /**< ADC Analog Input 14 */
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ADC12_ADCIN15 = (CSP_REGISTER_T)(0x0Ful), /**< ADC Analog Input 15 */
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//ADC12_ADCIN16 = (CSP_REGISTER_T)(0x10ul), /**< ADC Analog Input 16 */
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//ADC12_ADCIN17 = (CSP_REGISTER_T)(0x11ul), /**< ADC Analog Input 17 */
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//ADC12_ADCIN18 = (CSP_REGISTER_T)(0x12ul), /**< ADC Analog Input 18 */
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//ADC12_ADCIN19 = (CSP_REGISTER_T)(0x13ul), /**< ADC Analog Input 19 */
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//ADC12_ADCIN20 = (CSP_REGISTER_T)(0x14ul), /**< ADC Analog Input 20 */
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//ADC12_ADCIN21 = (CSP_REGISTER_T)(0x15ul), /**< ADC Analog Input 21 */
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//ADC12_ADCIN22 = (CSP_REGISTER_T)(0x16ul), /**< ADC Analog Input 22 */
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//ADC12_ADCIN23 = (CSP_REGISTER_T)(0x17ul), /**< ADC Analog Input 23 */
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//ADC12_ADCIN24 = (CSP_REGISTER_T)(0x18ul), /**< ADC Analog Input 24 */
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//ADC12_ADCIN25 = (CSP_REGISTER_T)(0x19ul), /**< ADC Analog Input 25 */
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//ADC12_ADCIN26 = (CSP_REGISTER_T)(0x1Aul), /**< ADC Analog Input 26 */
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//ADC12_ADCIN27 = (CSP_REGISTER_T)(0x1Bul) /**< ADC Analog Input 27 */
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ADC12_INTVREF = (CSP_REGISTER_T)(0x1Cul),
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ADC12_DIV4_VDD = (CSP_REGISTER_T)(0x1Dul),
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ADC12_VSS = (CSP_REGISTER_T)(0x1Eul),
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}
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ADC12_InputSet_TypeDef;
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/**
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* @brief ADC12 Convertion repeat number
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*/
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typedef enum
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{
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ADC12_CV_RepeatNum1 = (CSP_REGISTER_T)(0x0ul<<8)|(0x0ul<<13), /**< ADC Convertion number 1 */
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ADC12_CV_RepeatNum2 = (CSP_REGISTER_T)(0x1ul<<8)|(0x1ul<<13), /**< ADC Convertion number 2 */
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ADC12_CV_RepeatNum4 = (CSP_REGISTER_T)(0x2ul<<8)|(0x2ul<<13), /**< ADC Convertion number 4 */
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ADC12_CV_RepeatNum8 = (CSP_REGISTER_T)(0x3ul<<8)|(0x3ul<<13), /**< ADC Convertion number 8 */
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ADC12_CV_RepeatNum16 = (CSP_REGISTER_T)(0x4ul<<8)|(0x4ul<<13), /**< ADC Convertion number 16 */
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ADC12_CV_RepeatNum32 = (CSP_REGISTER_T)(0x5ul<<8)|(0x5ul<<13), /**< ADC Convertion number 32 */
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ADC12_CV_RepeatNum64 = (CSP_REGISTER_T)(0x6ul<<8)|(0x6ul<<13), /**< ADC Convertion number 64 */
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ADC12_CV_RepeatNum128 = (CSP_REGISTER_T)(0x7ul<<8)|(0x7ul<<13), /**< ADC Convertion number 128 */
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ADC12_CV_RepeatNum256 = (CSP_REGISTER_T)(0x8ul<<8)|(0x8ul<<13), /**< ADC Convertion number 256 */
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ADC12_CV_RepeatNum512 = (CSP_REGISTER_T)(0x9ul<<8)|(0x9ul<<13) /**< ADC Convertion number 512 */
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}ADC12_CV_RepeatNum_TypeDef;
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/**
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* @brief ADC12 VREFP VREFN Selecte
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*/
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typedef enum
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{
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ADC12_VREFP_VDD_VREFN_VSS = 0,
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ADC12_VREFP_EXIT_VREFN_VSS = 1,
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ADC12_VREFP_FVR2048_VREFN_VSS = 2,
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ADC12_VREFP_FVR4096_VREFN_VSS = 3,
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//ADC12_VREFP_INTVREF0750_VREFN_VSS = 4,
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ADC12_VREFP_INTVREF1000_VREFN_VSS = 5,
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ADC12_VREFP_VDD_VREFN_EXIT = 6,
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ADC12_VREFP_EXIT_VREFN_EXIT = 7,
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ADC12_VREFP_FVR2048_VREFN_EXIT = 8,
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ADC12_VREFP_FVR4096_VREFN_EXIT = 9,
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//ADC12_VREFP_INTVREF0750_VREFN_EXIT = 10,
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ADC12_VREFP_INTVREF1000_VREFN_EXIT = 11
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}ADC12_VREFP_VREFN_Selected_TypeDef;
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extern void ADC12_RESET_VALUE(void);
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extern void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x );
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extern void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState);
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extern uint8_t ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit);
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extern void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState);
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extern void ADC12_Software_Reset(void);
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extern void ADC12_CMD(FunctionalStatus NewState);
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extern void ADC12_ready_wait(void);
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extern void ADC12_EOC_wait(void);
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extern void ADC12_SEQEND_wait(U8_T val);
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extern U16_T ADC12_DATA_OUPUT(U16_T Data_index );
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extern void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver );
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extern void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X );
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extern void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data );
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extern void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
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ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx);
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extern U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL);
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extern void ADC_Int_Enable(void);
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extern void ADC_Int_Disable(void);
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extern void ADC12_CONFIG(void);
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extern void adc12_SHR_SET(U8_T adc12_SHR);
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#endif /**< apt32f102_adc_H */
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/******************* (C) COPYRIGHT 2020 APT Chip *****END OF FILE****/ |