139 lines
7.9 KiB
ArmAsm
139 lines
7.9 KiB
ArmAsm
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.global __main
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.weak __main
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.global __e_rom
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.weak __e_rom
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.global __s_ram_data_1
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.weak __s_ram_data_1
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.global __e_ram_data_1
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.weak __e_ram_data_1
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.global __s_ram_bss_1
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.weak __s_ram_bss_1
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.global __e_ram_bss_1
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.weak __e_ram_bss_1
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.global __s_ram_data_2
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.weak __s_ram_data_2
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.global __e_ram_data_2
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.weak __e_ram_data_2
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.global __s_ram_bss_2
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.weak __s_ram_bss_2
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.global __e_ram_bss_2
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.weak __e_ram_bss_2
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.global __s_ram_data_3
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.weak __s_ram_data_3
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.global __e_ram_data_3
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.weak __e_ram_data_3
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.global __s_ram_bss_3
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.weak __s_ram_bss_3
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.global __e_ram_bss_3
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.weak __e_ram_bss_3
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.global __s_ram_data_4
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.weak __s_ram_data_4
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.global __e_ram_data_4
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.weak __e_ram_data_4
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.global __s_ram_bss_4
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.weak __s_ram_bss_4
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.global __e_ram_bss_4
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.weak __e_ram_bss_4
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.global __s_ram_data_5
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.weak __s_ram_data_5
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.global __e_ram_data_5
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.weak __e_ram_data_5
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.global __s_ram_bss_5
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.weak __s_ram_bss_5
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.global __e_ram_bss_5
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.weak __e_ram_bss_5
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.global __ChipInitHandler
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.weak __ChipInitHandler
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.text
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.align 3
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__bss_initialization:
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subu a2, a3
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lsri a2, 2
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cmpnei a2, 0
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bf 2f
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movi a1, 0
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1:
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stw a1, (a3)
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addi a3, 4
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subi a2, 1
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cmpnei a2, 0
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bt 1b
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2:
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jmp r15
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__rom_decompression:
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cmphs a1, a2
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bt 4f
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3:
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ld.w a3, (a0, 0)
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st.w a3, (a1, 0)
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addi a0, 4
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addi a1, 4
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cmphs a1, a2
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bf 3b
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4:
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jmp r15
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__main:
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mov r6, r15
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lrw a3, __s_ram_bss_1
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lrw a2, __e_ram_bss_1
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bsr __bss_initialization
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lrw a3, __s_ram_bss_2
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lrw a2, __e_ram_bss_2
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bsr __bss_initialization
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lrw a3, __s_ram_bss_3
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lrw a2, __e_ram_bss_3
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bsr __bss_initialization
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lrw a3, __s_ram_bss_4
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lrw a2, __e_ram_bss_4
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bsr __bss_initialization
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lrw a3, __s_ram_bss_5
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lrw a2, __e_ram_bss_5
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bsr __bss_initialization
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lrw a0, __e_rom
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lrw a1, __s_ram_data_1
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lrw a2, __e_ram_data_1
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bsr __rom_decompression
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lrw a1, __s_ram_data_2
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lrw a2, __e_ram_data_2
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bsr __rom_decompression
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lrw a1, __s_ram_data_3
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lrw a2, __e_ram_data_3
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bsr __rom_decompression
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lrw a1, __s_ram_data_4
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lrw a2, __e_ram_data_4
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bsr __rom_decompression
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lrw a1, __s_ram_data_5
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lrw a2, __e_ram_data_5
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bsr __rom_decompression
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#ifdef __CSKYABIV2__
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subi sp, 4
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stw r6, (sp, 0)
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lrw a0, __ChipInitHandler
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cmpnei a0, 0
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bf 1f
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jsr a0
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1:
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lrw a0, main
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jsr a0
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#else
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subi sp, 8
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stw r6, (sp, 0)
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lrw a0, __ChipInitHandler
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cmpnei a0, 0
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bf 1f
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jsri __ChipInitHandler
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1:
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jsri main
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#endif
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ldw r15, (sp, 0)
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#ifdef __CSKYABIV2__
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addi sp, 4
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#else
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addi sp, 8
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#endif
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jmp r15
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