293 lines
12 KiB
C
293 lines
12 KiB
C
/*
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******************************************************************************
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* @file apt32f102_spi.c
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* @author APT AE Team
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* @version V1.025
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* @date 2020/06/08
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_spi_H
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#define _apt32f102_spi_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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/******************************************************************************
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************************** spi Registers Definition ****************************
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******************************************************************************/
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/*******************************************************************************
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* SSPCR0 : Control Register 0
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*******************************************************************************/
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#define SSP_DSS(val) (((val-1) & 0x0Ful) << 0) /**< Data Size Select */
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#define SSP_FRF(val) (((val) & 0x03ul) << 4) /**< Frame Format */
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#define SSP_SPO (0x01ul << 6) /**< SSPCLK Polarity */
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#define SSP_SPH (0x01ul << 7) /**< SSPCLK Phase */
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#define SSP_SCR(val) (((val) & 0x0FFul) << 8) /**< Serial Clock Rate */
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/*******************************************************************************
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* SSPCR1 : Control Register 1
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*******************************************************************************/
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#define SSP_LBM (0x01ul << 0) /**< Loopback mode */
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#define SSP_SSE (0x01ul << 1) /**< Synchronous Serial Port Enable */
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#define SSP_MS (0x01ul << 2) /**< Master or Slave Mode Select */
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#define SSP_SOD (0x01ul << 3) /**< Slave Mode Output Disable */
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#define SSP_RXIFLSELFRF(val) (((val) & 0x07ul) << 4)
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/**< Receive interrupt FIFO level select */
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/*******************************************************************************
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* SSPDR : Data Register
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*******************************************************************************/
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#define SSP_DATA(val) (((val) & 0x0FFFF) << 0) /**< Transmit/Receive FIFO */
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/*******************************************************************************
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* SSPSR : Status Register
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*******************************************************************************/
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#define SSP_TFE (0x01ul << 0) /**< Transmit FIFO Empty */
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#define SSP_TNF (0x01ul << 1) /**< Transmit FIFO is not Full */
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#define SSP_RNE (0x01ul << 2) /**< Receive is not Empty */
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#define SSP_RFF (0x01ul << 3) /**< Receive FIFO Full */
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#define SSP_BSY (0x01ul << 4) /**< PrimeCell SSP Busy Flag */
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/*******************************************************************************
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* SSPCPSR : Clock prescale register
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*******************************************************************************/
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#define SSP_CPSDVSR(val) (((val) & 0x0FF) << 0) /**< Clock Prescale Devisor */
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/*******************************************************************************
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* SSPIMSC : Interrupt mask set and clear register
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*******************************************************************************/
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#define SSP_RORIM (0x01ul << 0) /**< Receive Overrun Interrupt Mask */
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#define SSP_RTIM (0x01ul << 1) /**< Receive Timeout Interrupt Mask */
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#define SSP_RXIM (0x01ul << 2) /**< Receive FIFO Interrupt Mask */
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#define SSP_TXIM (0x01ul << 3) /**< Transmit FIFO interrupt Mask */
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/*******************************************************************************
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* SSPRIS : Raw interrupt status register
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*******************************************************************************/
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#define SSP_RORRIS (0x01ul << 0)
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/**< Gives the Raw Interrupt Status of the SSPRORINTR Interrupt */
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#define SSP_RTRIS (0x01ul << 1)
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/**< Gives the raw interrupt state of the SSPRTINTR interrupt */
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#define SSP_RXRIS (0x01ul << 2)
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/**< Gives the raw interrupt state of the SSPRXINTR interrupt */
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#define SSP_TXRIS (0x01ul << 3)
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/**< Gives the raw interrupt state of the SSPTXINTR interrupt */
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/*******************************************************************************
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* SSPMIS : Masked interrupt status register
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*******************************************************************************/
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#define SSP_RORRIS (0x01ul << 0)
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/**<Gives the receive over run masked interrupt status of SSPRORINTR interrupt*/
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#define SSP_RTRIS (0x01ul << 1)
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/**<Gives the receive timeout masked interrupt state of SSPRTINTR interrupt */
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#define SSP_RXRIS (0x01ul << 2)
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/**<Gives the receive FIFO masked interrupt state of SSPRXINTR interrupt */
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#define SSP_TXRIS (0x01ul << 3)
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/**<Gives the transmit FIFO masked interrupt state of SSPTXINTR interrupt */
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/*******************************************************************************
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* SSPICR : Interrupt clear register
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*******************************************************************************/
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#define SSP_RORIC (0x01ul << 0) /**< Clears the SSPRORINTR interrupt */
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#define SSP_RTIC (0x01ul << 1) /**< Clears the SSPRTINTR interrupt */
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/*******************************************************************************
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***************************** SSP REGISTER MASK *******************************
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*******************************************************************************/
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#define SSP_CR0_MASK (0x0000FFFFul) /**< Control Register 0 mask */
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#define SSP_CR1_MASK (0x0000007Ful) /**< Control Register 1 mask */
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#define SSP_DR_MASK (0x0000FFFFul)
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/**< Receive FIFO(read) and transmit FIFO data register(write) mask */
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#define SSP_SR_MASK (0x0000001Ful) /**< Status register mask */
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#define SSP_CPSR_MASK (0x000000FFul) /**< Clock prescale register mask */
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#define SSP_IMSCR_MASK (0x0000000Ful)
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/**< Interrupt mask set and clear register mask */
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#define SSP_RISR_MASK (0x0000000Ful) /**< Raw interrupt status register mask*/
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#define SSP_MISR_MASK (0x0000000Ful)
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/**< Masked interrupt status register mask */
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#define SSP_ICR_MASK (0x00000003ul) /**< Interrupt clear register mask */
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/*******************************************************************************
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************************* SSP REGISTER RESET VALUE ****************************
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*******************************************************************************/
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#define SSP_CR0_RST (0x00000000ul) /**< Control Register 0 reset value */
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#define SSP_CR1_RST (0x00000010ul) /**< Control Register 1 reset value */
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#define SSP_DR_RST (0x00000000ul)
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/**< Receive FIFO(read) and transmit FIFO data register(write) reset value */
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#define SSP_SR_RST (0x00000003ul) /**< Status register reset value */
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#define SSP_CPSR_RST (0x00000000ul)
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/**< Clock prescale register reset value */
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#define SSP_IMSCR_RST (0x00000000ul)
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/**< Interrupt mask set and clear register reset value */
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#define SSP_RISR_RST (0x00000008ul)
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/**< Raw interrupt status register reset value*/
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#define SSP_MISR_RST (0x00000000ul)
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/**< Masked interrupt status register reset value */
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#define SSP_ICR_RST (0x00000000ul)
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/**< Interrupt clear register reset value */
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/*******************************************************************************
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***************************** SSP MACROS DEFINITION **************************
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*******************************************************************************/
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/** Set CR0 register */
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#define CSP_SSP_SET_CR0(ssp, val) ((ssp)->CR0 = (val & 0xFFFFFFCFul))
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/** Get CR0 register */
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#define CSP_SSP_GET_CR0(ssp) ((ssp)->CR0)
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/** Set CR1 register */
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#define CSP_SSP_SET_CR1(ssp, val) ((ssp)->CR1 = (val & 0xFFFF000Ful))
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/** Get CR1 register */
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#define CSP_SSP_GET_CR1(ssp) ((ssp)->CR1)
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/** Set DR register */
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#define CSP_SSP_SET_DR(ssp, val) ((ssp)->DR = (val))
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/** Get DR register */
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#define CSP_SSP_GET_DR(ssp) ((ssp)->DR)
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/** Get SR register */
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#define CSP_SSP_GET_SR(ssp) ((ssp)->SR)
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/** Set CPSR register */
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#define CSP_SSP_SET_CPSR(ssp, val) ((ssp)->CPSR = (val & 0xFFFF00FFul))
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/** Get CPSR register */
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#define CSP_SSP_GET_CPSR(ssp) ((ssp)->CPSR)
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/** Set IMSC register */
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#define CSP_SSP_SET_IMSCR(ssp, val) ((ssp)->IMSC = (val & 0xFFFF000Ful))
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/** Get IMSC register */
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#define CSP_SSP_GET_IMSCR(ssp) ((ssp)->IMSCR)
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/** Get RIS register */
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#define CSP_SSP_GET_RISR(ssp) ((ssp)->RISR)
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/** Get MIS register */
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#define CSP_SSP_GET_MISR(ssp) ((ssp)->MISR
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/** Set ICR register */
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#define CSP_SSP_SET_ICR(ssp, val) ((ssp)->ICR = (val & 0xFFFF0003ul))
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/** @addtogroup spi Registers RST Value
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* @{
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*/
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#define SPI_CR0_RST (0x00000000) /**< CR0 reset value */
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#define SPI_CR1_RST (0x00000000) /**< CR1 reset value */
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#define SPI_DR_RST (0x00000000) /**< DR reset value */
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#define SPI_SR_RST (0x00000003) /**< SR reset value */
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#define SPI_CPSR_RST (0x00000000) /**< CPSR reset value */
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#define SPI_IMSCR_RST (0x00000000) /**< IMSCR reset value */
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#define SPI_RISR_RST (0x00000008) /**< RISR reset value */
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#define SPI_MISR_RST (0x00000000) /**< MISR reset value */
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#define SPI_ICR_RST (0x00000000) /**< ICR reset value */
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/**
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* @brief SPI INT MASK SET/CLR Set
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*/
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typedef enum
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{
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SPI_PORIM = ((CSP_REGISTER_T)(0x01ul << 0)), /**< Receive overflow Interrupt */
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SPI_RTIM = ((CSP_REGISTER_T)(0x01ul << 1)), /**< Receive timeout Interrupt */
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SPI_RXIM = ((CSP_REGISTER_T)(0x01ul << 2)), /**< Receive FIFO Interrupt */
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SPI_TXIM = ((CSP_REGISTER_T)(0x01ul << 3)) /**< transmit FIFO Interrupt */
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}SPI_IMSCR_TypeDef;
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/**
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* @brief SPI IO selection
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*/
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typedef enum
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{
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SPI_G0 = 0,
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SPI_G1 = 1,
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SPI_G2 = 2
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}SPI_IO_TypeDef;
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/**
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* @brief SPI Data Size selection
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*/
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typedef enum
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{
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SPI_DATA_SIZE_4BIT = 3,
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SPI_DATA_SIZE_5BIT = 4,
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SPI_DATA_SIZE_6BIT = 5,
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SPI_DATA_SIZE_7BIT = 6,
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SPI_DATA_SIZE_8BIT = 7,
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SPI_DATA_SIZE_9BIT = 8,
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SPI_DATA_SIZE_10BIT = 9,
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SPI_DATA_SIZE_11BIT = 10,
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SPI_DATA_SIZE_12BIT = 11,
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SPI_DATA_SIZE_13BIT = 12,
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SPI_DATA_SIZE_14BIT = 13,
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SPI_DATA_SIZE_15BIT = 14,
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SPI_DATA_SIZE_16BIT = 15
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}SPI_DATA_SIZE_TypeDef;
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/**
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* @brief SPI SPO selection
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*/
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typedef enum
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{
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SPI_SPO_0 = 0,
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SPI_SPO_1 = 1
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}SPI_SPO_TypeDef;
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/**
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* @brief SPI SPH selection
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*/
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typedef enum
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{
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SPI_SPH_0 = 0,
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SPI_SPH_1 = 1
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}SPI_SPH_TypeDef;
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/**
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* @brief SPI LBM selection
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*/
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typedef enum
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{
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SPI_LBM_0 = 0,
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SPI_LBM_1 = 1
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}SPI_LBM_TypeDef;
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/**
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* @brief SPI RXIFLSEL selection
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*/
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typedef enum
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{
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SPI_RXIFLSEL_1_8 = 0x01,
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SPI_RXIFLSEL_1_4 = 0x02,
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SPI_RXIFLSEL_1_2 = 0x04
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}SPI_RXIFLSEL_TypeDef;
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/******************************************************************************
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********************** SPI External Functions Declaration **********************
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******************************************************************************/
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extern void SPI_DeInit(void);
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extern void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP);
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extern void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR );
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extern void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR);
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extern void SPI_WRITE_BYTE(U16_T wdata);
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extern void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth);
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extern void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X);
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extern void SPI_Int_Enable(void);
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extern void SPI_Int_Disable(void);
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extern void SPI_Wakeup_Enable(void);
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extern void SPI_Wakeup_Disable(void);
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#endif /**< apt32f102_spi_H */
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/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/ |