212 lines
7.8 KiB
C
212 lines
7.8 KiB
C
/*
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******************************************************************************
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* @file apt32f102_spi.c
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* @author APT AE Team
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* @version V1.10
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* @date 2021/08/25
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#include "apt32f102_spi.h"
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/* defines -------------------------------------------------------------------*/
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/* -------- variables ---------------------------------------------------------*/
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/* externs--------------------------------------------------------------------*/
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extern void delay_nus(unsigned int t);
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/*************************************************************/
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//SPI RESET,CLEAR ALL REGISTER
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_DeInit(void)
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{
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SPI0->CR0 = SPI_CR0_RST;
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SPI0->CR1 = SPI_CR1_RST;
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//SPI0->DR = SPI_DR_RST;
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SPI0->SR = SPI_SR_RST;
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SPI0->CPSR = SPI_CPSR_RST;
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SPI0->IMSCR = SPI_IMSCR_RST;
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SPI0->RISR = SPI_RISR_RST;
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SPI0->MISR = SPI_MISR_RST;
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SPI0->ICR = SPI_ICR_RST;
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}
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/*************************************************************/
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//SPI NSS IO Initial
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP)
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{
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if(SPI_NSS_IO_GROUP==0)
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{
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GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0x05000000; //PA0.6
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}
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else if(SPI_NSS_IO_GROUP==1)
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{
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GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF) | 0x00800000; //PB0.5
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}
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}
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/*************************************************************/
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//SPI Master Init
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//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_SPO_X,SPI_SPH_X,SPI_LBM_X,SPI_SCR,SPI_CPSDVSR
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//SPI_IO:SPI_G0,SPI_G1,SPI_G2
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//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT
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//SPI_SPO_X:SPI_SPO_0,SPI_SPO_1
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//SPI_SPH_X:SPI_SPH_0,SPI_SPH_1
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//SPI_LBM_X:SPI_LBM_0,SPI_LBM_1
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//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2
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//SPI_SCR:0~255
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//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254
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//ReturnValue:NONE
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/*************************************************************/
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//SPI Baud rate:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
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//FPCLK (max) → 2 × FSSPCLKOUT (max) master Fastest speed
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void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR )
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{
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if (SPI_IO==SPI_G0)
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{
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GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800;
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GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MOSI,PA0.8->SPI_MIS0
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}
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else if(SPI_IO==SPI_G1)
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{
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GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MOSI,PA0.11->SPI_MIS0
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}
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else if(SPI_IO==SPI_G2)
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{
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GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4
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GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15
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}
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SPI0->CPSR=SPI_CPSDVSR;
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SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPO_X<<6)|(SPI_SPH_X<<7)|(SPI_SCR<<8);
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SPI0->CR1|=0X02|SPI_LBM_X|(SPI_RXIFLSEL_X<<4);
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}
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/*************************************************************/
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//SPI Slave Init
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//EntryParameter:SPI_IO,SPI_DATA_SIZE_x,SPI_RXIFLSEL_X,SPI_SCR,SPI_CPSDVSR
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//SPI_DATA_SIZE_x:SPI_DATA_SIZE_4BIT~SPI_DATA_SIZE_16BIT
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//SPI_RXIFLSEL_X:SPI_RXIFLSEL_1_8,SPI_RXIFLSEL_1_4,SPI_RXIFLSEL_1_2
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//SPI_SCR:0~255
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//SPI_CPSDVSR:2~254,Must be an even number between 2 and 254
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//ReturnValue:NONE
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/*************************************************************/
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//SPI波特率:FSSPCLK = FPCLK / (CPSDVR × (1 + SCR))
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//FPCLK (max) → 12 × FSSPCLKIN (max) slave Fastest speed
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void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR)
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{
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if (SPI_IO==SPI_G0)
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{
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GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF00FF) | 0x00008800;
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GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0x00000008; //PB0.2->SPI_SCK,PB0.3->SPI_MISO,PA0.8->SPI_MOSI
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}
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else if(SPI_IO==SPI_G1)
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{
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GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF000F) | 0x00004440; //PA0.9->SPI_SCK,PA0.10->SPI_MISO,PA0.11->SPI_MOSI
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}
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else if(SPI_IO==SPI_G2)
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{
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GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF) | 0x00080000; //SPI_SCK->PB0.4
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GPIOA0->CONHR = (GPIOA0->CONHR&0X00FFFFFF) | 0x88000000; //SPI_MOSI->PA0.14,SPI_MISO->PA0.15
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}
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SPI0->CR0|=SPI_DATA_SIZE_x|(SPI_SPH_X<<7)|(SPI_SCR<<8);
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SPI0->CPSR=SPI_CPSDVSR;
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SPI0->CR1|=0X06|(SPI_RXIFLSEL_X<<4);
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}
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/*************************************************************/
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//SPI WRITE BYTE
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_WRITE_BYTE(U16_T wdata)
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{
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while(((SPI0->SR) & SSP_TNF) != SSP_TNF);
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SPI0->DR = wdata;
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while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //wait for transmition finish
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}
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/*************************************************************/
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//SPI READ BYTE
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth)
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{
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U8_T i;
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while(((SPI0->SR) & SSP_TNF) != SSP_TNF); //Transmit FIFO is not full？
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SPI0->DR = wdata;
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while(((SPI0->SR) & SSP_BSY) == SSP_BSY); //Send or receive over？
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delay_nus(1);
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*rdata = SPI0->DR;
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for(i=0;i<Longth;i++)
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{
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while(((SPI0->SR) & SSP_TNF) != SSP_TNF);
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SPI0->DR=0;
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while(((SPI0->SR) & SSP_BSY) == SSP_BSY);
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*(rdata+i) = SPI0->DR; //get data from FIFO
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}
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}
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/*************************************************************/
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//SPI inturrpt Configure
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//EntryParameter:SPI_IMSCR_X,NewState
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//SPI_IMSCR_X:SPI_PORIM,SPI_RTIM,SPI_RXIM,SPI_TXIM
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//NewState:ENABLE,DISABLE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X)
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{
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if (NewState != DISABLE)
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{
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SPI0->IMSCR |= SPI_IMSCR_X; //SET
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}
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else
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{
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SPI0->IMSCR &= ~SPI_IMSCR_X; //CLR
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}
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}
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/*************************************************************/
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//SPI Interrupt enable
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_Int_Enable(void)
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{
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INTC_ISER_WRITE(SPI_INT);
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}
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/*************************************************************/
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//SPI Interrupt disalbe
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_Int_Disable(void)
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{
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INTC_ICER_WRITE(SPI_INT);
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}
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/*************************************************************/
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//SPI Interrupt wake up enable
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_Wakeup_Enable(void)
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{
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INTC_IWER_WRITE(SPI_INT);
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}
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/*************************************************************/
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//SPI Interrupt wake up disalbe
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//EntryParameter:NONE
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//ReturnValue:NONE
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/*************************************************************/
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void SPI_Wakeup_Disable(void)
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{
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INTC_IWDR_WRITE(SPI_INT);
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}
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/******************* (C) COPYRIGHT 2018 APT Chip *****END OF FILE****/ |