695 lines
17 KiB
C
695 lines
17 KiB
C
/*
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******************************************************************************
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* @file apt32f102_gpt.h
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_gpt_H
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#define _apt32f102_gpt_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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#define GPT_RESET_VALUE (0x00000000)
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//--------------------------------------------------------------------------------
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//-----------------------------GPT value enum define--------------------------
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//--------------------------------------------------------------------------------
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/**
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* @brief GPT CLK EN register
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*/
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typedef enum
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{
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GPTCLK_DIS = 0,
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GPTCLK_EN = 1,
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}GPT_CLK_TypeDef;
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/**
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* @brief GPT CLK SOURCE register
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*/
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typedef enum
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{
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GPT_PCLK = (0<<3),
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GPT_TRGUSR3 = (1<<3),
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}GPT_CSS_TypeDef;
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/**
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* @brief GPT START SHADOW register
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*/
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typedef enum
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{
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GPT_SHADOW = (0<<6),
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GPT_IMMEDIATE= (1<<6),
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}GPT_SHDWSTP_TypeDef;
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/**
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* @brief GPT COUNT EDGE register
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*/
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typedef enum
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{
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DIR_INCREASE = (0<<3),
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DIR_DECREASE= (1<<3),
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}GPT_CNTDIR_TypeDef;
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/**
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* @brief GPT COUNT EDGE register
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*/
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typedef enum
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{
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GPT_INCREASE = (0<<0),
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GPT_DECREASE= (1<<0),
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GPT_IN_DECREASE= (2<<0),
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}GPT_CNTMD_TypeDef;
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/**
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* @brief GPT START SYN EN register
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*/
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typedef enum
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{
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GPT_SWSYNDIS= (0<<2),
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GPT_SWSYNEN= (1<<2),
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}GPT_SWSYN_TypeDef;
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/**
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* @brief GPT ILDE IO Status register
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*/
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typedef enum
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{
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GPT_IDLE_Z= (0<<3),
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GPT_IDLE_LOW= (1<<3),
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}GPT_IDLEST_TypeDef;
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/**
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* @brief GPT PRDLD register
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*/
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typedef enum
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{
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GPT_PRDLD_PEND= (0<<4),
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GPT_PRDLD_LOAD_SYNC= (1<<4),
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GPT_PRDLD_ZERO_LOAD_SYNC= (2<<4),
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GPT_PRDLD_IMMEDIATELY= (3<<4),
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}GPT_PRDLD0_TypeDef;
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/**
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* @brief GPT CAPLDEN register
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*/
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typedef enum
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{
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GPT_CAP_DIS= (0<<8),
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GPT_CAP_EN= (1<<8),
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}GPT_CAPLDEN_TypeDef;
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/**
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* @brief GPT BURST register
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*/
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typedef enum
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{
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GPT_BURST_DIS= (0<<9),
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GPT_BURST_EN= (1<<9),
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}GPT_BURST_TypeDef;
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/**
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* @brief GPT BURST register
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*/
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typedef enum
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{
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GPT_CG_CHAX= (0<<11),
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GPT_CG_CHBX= (1<<11),
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}GPT_CGSRC_TypeDef;
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/**
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* @brief GPT CGFLT register
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*/
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typedef enum
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{
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GPT_CGFLT_00= (0<<13),
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GPT_CGFLT_02= (1<<13),
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GPT_CGFLT_03= (2<<13),
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GPT_CGFLT_04= (3<<13),
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GPT_CGFLT_06= (4<<13),
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GPT_CGFLT_08= (5<<13),
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GPT_CGFLT_16= (6<<13),
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GPT_CGFLT_32= (7<<13),
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}GPT_CGFLT_TypeDef;
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/**
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* @brief GPT PSCLD register
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*/
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typedef enum
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{
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GPT_PRDLD_ZERO= (0<<16),
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GPT_PRDLD_PRD= (1<<16),
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GPT_PRDLD_ZERO_PRD= (2<<16),
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GPT_PRDLD_NONE= (3<<16),
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}GPT_PSCLD_TypeDef;
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/**
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* @brief GPT CAPMD register
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*/
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typedef enum
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{
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GPT_CAPMD_CONTINUOUS= (0<<20),
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GPT_CAPMD_ONCE= (1<<20),
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}GPT_CAPMD_TypeDef;
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/**
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* @brief GPT LDARST register
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*/
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typedef enum
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{
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GPT_LDARST_EN= (0<<23),
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GPT_LDARST_DIS= (1<<23),
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}GPT_LDARST_TypeDef;
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/**
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* @brief GPT LDBRST register
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*/
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typedef enum
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{
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GPT_LDBRST_EN= (0<<24),
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GPT_LDBRST_DIS= (1<<24),
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}GPT_LDBRST_TypeDef;
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/**
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* @brief GPT OPM register
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*/
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typedef enum
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{
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GPT_OPM_CONTINUOUS= (0<<6),
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GPT_OPM_ONCE= (1<<6),
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}GPT_OPM_TypeDef;
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/**
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* @brief GPT CKS register
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*/
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typedef enum
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{
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GPT_CKS_PCLK= (0<<10),
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GPT_CKS_PCLKDIV2= (1<<10),
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}GPT_CKS_TypeDef;
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/**
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* @brief GPT WAVE register
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*/
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typedef enum
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{
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GPT_CAPTURE_MODE= (0<<18),
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GPT_WAVE_MODE= (1<<18),
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}GPT_WAVE_TypeDef;
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/**
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* @brief GPT SYNCEN register
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*/
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typedef enum
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{
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GPT_SYNCUSR0_EN= (1<<0),
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GPT_SYNCUSR1_EN= (1<<1),
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GPT_SYNCUSR2_EN= (1<<2),
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GPT_SYNCUSR3_EN= (1<<3),
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GPT_SYNCUSR4_EN= (1<<4),
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GPT_SYNCUSR5_EN= (1<<5)
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}GPT_SYNCENX_TypeDef;
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/**
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* @brief GPT OSTMDX register
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*/
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typedef enum
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{
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GPT_OSTMD0_CONTINUOUS= (0<<8),
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GPT_OSTMD0_ONCE= (1<<8),
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GPT_OSTMD1_CONTINUOUS= (0<<9),
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GPT_OSTMD1_ONCE= (1<<9),
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GPT_OSTMD2_CONTINUOUS= (0<<10),
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GPT_OSTMD2_ONCE= (1<<10),
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GPT_OSTMD3_CONTINUOUS= (0<<11),
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GPT_OSTMD3_ONCE= (1<<11),
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GPT_OSTMD4_CONTINUOUS= (0<<12),
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GPT_OSTMD4_ONCE= (1<<12),
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GPT_OSTMD5_CONTINUOUS= (0<<13),
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GPT_OSTMD5_ONCE= (1<<13),
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}GPT_OSTMDX_TypeDef;
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/**
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* @brief GPT TXREARM0 register
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*/
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typedef enum
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{
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GPT_TXREARM_DIS= (0<<22),
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GPT_TXREARM_T1= (1<<22),
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GPT_TXREARM_T2= (2<<22),
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GPT_TXREARM_T1_T2= (3<<22),
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}GPT_TXREARM0_TypeDef;
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/**
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* @brief GPT TRGO0SEL register
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*/
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typedef enum
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{
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GPT_TRGO0SEL_SR0= (0<<24),
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GPT_TRGO0SEL_SR1= (1<<24),
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GPT_TRGO0SEL_SR2= (2<<24),
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GPT_TRGO0SEL_SR3= (3<<24),
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GPT_TRGO0SEL_SR4= (4<<24),
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GPT_TRGO0SEL_SR5= (5<<24),
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GPT_TRGO0SEL_RSVD= (6<<24),
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}GPT_TRGO0SEL_TypeDef;
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/**
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* @brief GPT TRGO0SEL register
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*/
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typedef enum
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{
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GPT_TRG10SEL_SR0= (0<<27),
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GPT_TRG10SEL_SR1= (1<<27),
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GPT_TRG10SEL_SR2= (2<<27),
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GPT_TRG10SEL_SR3= (3<<27),
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GPT_TRG10SEL_SR4= (4<<27),
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GPT_TRG10SEL_SR5= (5<<27),
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GPT_TRG10SEL_RSVD= (6<<27),
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}GPT_TRGO1SEL_TypeDef;
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/**
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* @brief GPT AREARM register
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*/
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typedef enum
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{
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GPT_AREARM_DIS= (0<<30),
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GPT_AREARM_ZERO= (1<<30),
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GPT_AREARM_PRD= (2<<30),
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GPT_AREARM_ZERO_PRD= (3<<30),
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}GPT_AREARM_TypeDef;
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/**
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* @brief BT INT MASK SET/CLR Set
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*/
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typedef enum
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{
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GPT_TRGEV0 = (0x01 << 0),
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GPT_TRGEV1 = (0x01 << 1),
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GPT_TRGEV2 = (0x01 << 2),
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GPT_TRGEV3 = (0x01 << 3),
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}GPT_IMSCR_TypeDef;
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/**
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* @brief GPT IO Set
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*/
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typedef enum
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{
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GPT_CHA_PB01 = 0,
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GPT_CHA_PA09 = 1,
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GPT_CHA_PA010 = 2,
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GPT_CHB_PA010 = 3,
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GPT_CHB_PA011 = 4,
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GPT_CHB_PB00 = 5,
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GPT_CHB_PB01 = 6,
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}GPT_IOSET_TypeDef;
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/**
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* @brief CMPA SHADOW/IMMEDIATE
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*/
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typedef enum
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{
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GPT_CMPA_SHADOW = (0x00 << 0),
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GPT_CMPA_IMMEDIATE = (0x01 << 0),
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}GPT_SHDWCMPA_TypeDef;
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/**
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* @brief CMPB SHADOW/IMMEDIATE
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*/
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typedef enum
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{
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GPT_CMPB_SHADOW = (0x00 << 1),
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GPT_CMPB_IMMEDIATE = (0x01 << 1),
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}GPT_SHDWCMPB_TypeDef;
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/**
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* @brief CMPA LOAD MODE
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*/
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typedef enum
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{
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GPT_LoadA_ZERO = (0x01 << 4),
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GPT_LoadA_PRD = (0x02 << 4),
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GPT_LoadA_EXT_SYNC = (0x04 << 4),
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GPT_LoadA_NONE = (0x00 << 4),
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}GPT_LDAMD_TypeDef;
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/**
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* @brief CMPB LOAD MODE
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*/
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typedef enum
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{
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GPT_LoadB_ZERO = (0x01 << 4),
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GPT_LoadB_PRD = (0x02 << 4),
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GPT_LoadB_EXT_SYNC = (0x04 << 4),
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GPT_LoadB_NONE = (0x00 << 4),
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}GPT_LDBMD_TypeDef;
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/**
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* @brief WAVEA SHADOW/IMMEDIATE
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*/
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typedef enum
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{
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GPT_WAVEA_SHADOW = (0x00 << 0),
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GPT_WAVEA_IMMEDIATE = (0x01 << 0),
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}GPT_SHDWAQA_TypeDef;
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/**
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* @brief WAVEB SHADOW/IMMEDIATE
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*/
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typedef enum
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{
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GPT_WAVEB_SHADOW = (0x00 << 1),
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GPT_WAVEB_IMMEDIATE = (0x01 << 1),
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}GPT_SHDWAQB_TypeDef;
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/**
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* @brief ACTIVE A LOAD MODE
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*/
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typedef enum
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{
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GPT_AQLDA_ZERO = (0x01 << 2),
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GPT_AQLDA_PRD = (0x02 << 2),
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GPT_AQLDA_EXT_SYNC = (0x04 << 2),
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GPT_AQLDA_NONE = (0x00 << 2),
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}GPT_AQLDA_TypeDef;
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/**
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* @brief ACTIVE B LOAD MODE
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*/
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typedef enum
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{
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GPT_AQLDB_ZERO = (0x01 << 5),
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GPT_AQLDB_PRD = (0x02 << 5),
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GPT_AQLDB_EXT_SYNC = (0x04 << 5),
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GPT_AQLDB_NONE = (0x00 << 5),
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}GPT_AQLDB_TypeDef;
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/**
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* @brief CASEL MODE
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*/
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typedef enum
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{
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GPT_CASEL_CMPA = (0x00 << 20),
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GPT_CASEL_CMPB = (0x01 << 20),
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}GPT_CASEL_TypeDef;
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/**
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* @brief CBSEL MODE
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*/
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typedef enum
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{
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GPT_CBSEL_CMPA = (0x00 << 22),
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GPT_CBSEL_CMPB = (0x01 << 22),
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}GPT_CBSEL_TypeDef;
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/**
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* @brief CBSEL MODE
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*/
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typedef enum
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{
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GPT_CHA = 0,
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GPT_CHB = 1,
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}GPT_GPTCHX_TypeDef;
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/**
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* @brief A FORCE ENABLE
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*/
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typedef enum
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{
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GPT_CHA_FORCE_DIS = 0,
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GPT_CHA_FORCE_EN = 1,
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}GPT_CHAFORCE_TypeDef;
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/**
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* @brief B FORCE ENABLE
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*/
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typedef enum
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{
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GPT_CHB_FORCE_DIS = 0<<4,
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GPT_CHB_FORCE_EN = 1<<4,
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}GPT_CHBFORCE_TypeDef;
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/**
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* @brief FORCE LOAD
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*/
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typedef enum
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{
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GPT_FORCELD_ZERO = (0<<16),
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GPT_FORCELD_PRD = (1<<16),
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GPT_FORCELD__ZERO_PRD = (3<<16),
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}GPT_FORCELD_TypeDef;
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/**
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* @brief FORCE A
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*/
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typedef enum
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{
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GPT_FORCECHA_LOW = (1<<0),
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GPT_FORCECHA_HIGH = (2<<0),
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}GPT_FORCEA_TypeDef;
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/**
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* @brief FORCE B
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*/
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typedef enum
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{
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GPT_FORCECHB_LOW = (1<<2),
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GPT_FORCECHB_HIGH = (2<<2),
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}GPT_FORCEB_TypeDef;
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/**
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* @brief GPT SRCSEL register
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*/
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typedef enum
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{
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GPT_SRCSEL_DIS= (0<<0),
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GPT_SRCSEL_TRGUSR0EN= (1<<0),
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GPT_SRCSEL_TRGUSR1EN= (2<<0),
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GPT_SRCSEL_TRGUSR2EN= (3<<0),
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GPT_SRCSEL_TRGUSR3EN= (4<<0),
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GPT_SRCSEL_TRGUSR4EN= (5<<0),
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GPT_SRCSEL_TRGUSR5EN= (6<<0)
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}GPT_SRCSEL_TypeDef;
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/**
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* @brief GPT BLKINV register
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*/
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typedef enum
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{
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GPT_BLKINV_DIS= (0<<4),
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GPT_BLKINV_EN= (1<<4),
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}GPT_BLKINV_TypeDef;
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/**
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* @brief GPT CROSSMD register
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*/
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typedef enum
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{
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GPT_ALIGNMD_PRD= (0<<5),
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GPT_ALIGNMD_ZRO= (1<<5),
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GPT_ALIGNMD_PRD_ZRO= (2<<5),
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GPT_ALIGNMD_T1= (3<<5),
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}GPT_ALIGNMD_TypeDef;
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/**
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* @brief GPT CROSSMD register
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*/
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typedef enum
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{
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GPT_CROSSMD_DIS= (0<<7),
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GPT_CROSSMD_EN= (1<<7),
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}GPT_CROSSMD_TypeDef;
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/**
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* @brief GPT TRGSRC0 register
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*/
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typedef enum
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{
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GPT_TRGSRC0_DIS= (0<<0),
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GPT_TRGSRC0_ZRO= (1<<0),
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GPT_TRGSRC0_PRD= (2<<0),
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GPT_TRGSRC0_ZRO_PRD= (3<<0),
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GPT_TRGSRC0_CMPA_INC= (4<<0),
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GPT_TRGSRC0_CMPA_DEC= (5<<0),
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GPT_TRGSRC0_CMPB_INC= (6<<0),
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GPT_TRGSRC0_CMPB_DEC= (7<<0),
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GPT_TRGSRC0_EXTSYNC= (0X0C<<0),
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GPT_TRGSRC0_PE0= (0X0D<<0),
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GPT_TRGSRC0_PE1= (0X0E<<0),
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GPT_TRGSRC0_PE2= (0X0F<<0),
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}GPT_TRGSRC0_TypeDef;
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/**
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* @brief GPT TRGSRC1 register
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*/
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typedef enum
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{
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GPT_TRGSRC1_DIS= (0<<4),
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GPT_TRGSRC1_ZRO= (1<<4),
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GPT_TRGSRC1_PRD= (2<<4),
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GPT_TRGSRC1_ZRO_PRD= (3<<4),
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GPT_TRGSRC1_CMPA_INC= (4<<4),
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GPT_TRGSRC1_CMPA_DEC= (5<<4),
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GPT_TRGSRC1_CMPB_INC= (6<<4),
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GPT_TRGSRC1_CMPB_DEC= (7<<4),
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GPT_TRGSRC1_EXTSYNC= (0X0C<<4),
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GPT_TRGSRC1_PE0= (0X0D<<4),
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GPT_TRGSRC1_PE1= (0X0E<<4),
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GPT_TRGSRC1_PE2= (0X0F<<4),
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}GPT_TRGSRC1_TypeDef;
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|
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/**
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* @brief GPT CNT0INITEN register
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|
*/
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typedef enum
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|
{
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GPT_CNT0INIT_DIS= (0<<16),
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GPT_CNT0INIT_EN= (1<<16),
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}GPT_CNT0INIT_TypeDef;
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|
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/**
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|
* @brief GPT CNT1INITEN register
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|
*/
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|
typedef enum
|
|
{
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GPT_CNT1INIT_DIS= (0<<17),
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GPT_CNT1INIT_EN= (1<<17),
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}GPT_CNT1INIT_TypeDef;
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|
|
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/**
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|
* @brief GPT ESYN0OE register
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|
*/
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|
typedef enum
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|
{
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GPT_ESYN0OE_DIS= (0<<20),
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|
GPT_ESYN0OE_EN= (1<<20),
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|
}GPT_ESYN0OE_TypeDef;
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|
|
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/**
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|
* @brief GPT ESYN1OE register
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|
*/
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|
typedef enum
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|
{
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|
GPT_ESYN1OE_DIS= (0<<21),
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|
GPT_ESYN1OE_EN= (1<<21),
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|
}GPT_ESYN1OE_TypeDef;
|
|
|
|
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/**
|
|
* @brief GPT CNTMD selected
|
|
*/
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|
typedef enum
|
|
{
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|
GPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
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|
GPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
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|
GPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
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|
}GPT_CNTMD_SELECTE_Type;
|
|
|
|
/**
|
|
* @brief GPT CAPMD selected
|
|
*/
|
|
typedef enum
|
|
{
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|
GPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
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|
GPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
|
|
}GPT_CAPMD_SELECTE_Type;
|
|
|
|
/**
|
|
* @brief GPT CMPC RST CMD
|
|
*/
|
|
typedef enum
|
|
{
|
|
GPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
|
|
GPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
|
|
}GPT_LOAD_CMPC_RST_CMD_Type;
|
|
/**
|
|
* @brief GPT CMPD RST CMD
|
|
*/
|
|
typedef enum
|
|
{
|
|
GPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
|
|
GPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
|
|
}GPT_LOAD_CMPD_RST_CMD_Type;
|
|
|
|
#define CH_ZRO_NONE (0X00)
|
|
#define CH_ZRO_LOW (0X01)
|
|
#define CH_ZRO_HIGH (0X02)
|
|
#define CH_ZRO_REVS (0X03)
|
|
#define CH_PRD_NONE (0X00)
|
|
#define CH_PRD_LOW (0X01)
|
|
#define CH_PRD_HIGH (0X02)
|
|
#define CH_PRD_REVS (0X03)
|
|
#define CH_CAU_NONE (0X00)
|
|
#define CH_CAU_LOW (0X01)
|
|
#define CH_CAU_HIGH (0X02)
|
|
#define CH_CAU_REVS (0X03)
|
|
#define CH_CAD_NONE (0X00)
|
|
#define CH_CAD_LOW (0X01)
|
|
#define CH_CAD_HIGH (0X02)
|
|
#define CH_CAD_REVS (0X03)
|
|
#define CH_CBU_NONE (0X00)
|
|
#define CH_CBU_LOW (0X01)
|
|
#define CH_CBU_HIGH (0X02)
|
|
#define CH_CBU_REVS (0X03)
|
|
#define CH_CBD_NONE (0X00)
|
|
#define CH_CBD_LOW (0X01)
|
|
#define CH_CBD_HIGH (0X02)
|
|
#define CH_CBD_REVS (0X03)
|
|
#define CH_T1U_NONE (0X00)
|
|
#define CH_T1U_LOW (0X01)
|
|
#define CH_T1U_HIGH (0X02)
|
|
#define CH_T1U_REVS (0X03)
|
|
#define CH_T1D_NONE (0X00)
|
|
#define CH_T1D_LOW (0X01)
|
|
#define CH_T1D_HIGH (0X02)
|
|
#define CH_T1D_REVS (0X03)
|
|
#define CH_T2U_NONE (0X00)
|
|
#define CH_T2U_LOW (0X01)
|
|
#define CH_T2U_HIGH (0X02)
|
|
#define CH_T2U_REVS (0X03)
|
|
#define CH_T2D_NONE (0X00)
|
|
#define CH_T2D_LOW (0X01)
|
|
#define CH_T2D_HIGH (0X02)
|
|
#define CH_T2D_REVS (0X03)
|
|
|
|
|
|
#define FORCE_ACT_NONE 0
|
|
#define FORCE_ACT_LOW 1
|
|
#define FORCE_ACT_HIGH 2
|
|
#define FORCE_ACT_REVS 3
|
|
|
|
|
|
#define GPT_INT_TRGEV0 (0X01)
|
|
#define GPT_INT_TRGEV1 (0X01<<1)
|
|
#define GPT_INT_TRGEV2 (0X01<<2)
|
|
#define GPT_INT_TRGEV3 (0X01<<3)
|
|
#define GPT_INT_CAPLD0 (0X01<<4)
|
|
#define GPT_INT_CAPLD1 (0X01<<5)
|
|
#define GPT_INT_CAPLD2 (0X01<<6)
|
|
#define GPT_INT_CAPLD3 (0X01<<7)
|
|
#define GPT_INT_CAU (0X01<<8)
|
|
#define GPT_INT_CAD (0X01<<9)
|
|
#define GPT_INT_CBU (0X01<<10)
|
|
#define GPT_INT_CBD (0X01<<11)
|
|
#define GPT_INT_PEND (0X01<<16)
|
|
|
|
|
|
|
|
#define GPT_SYNCUSR0 (0X01)
|
|
#define GPT_SYNCUSR1 (0X01<<1)
|
|
#define GPT_SYNCUSR2 (0X01<<2)
|
|
#define GPT_SYNCUSR3 (0X01<<3)
|
|
#define GPT_SYNCUSR4 (0X01<<4)
|
|
#define GPT_SYNCUSR5 (0X01<<5)
|
|
#define GPT_DEBUG_MODE (0x01<<1)
|
|
|
|
|
|
|
|
extern void GPT_DeInit(void);
|
|
extern void GPT_IO_Init(GPT_IOSET_TypeDef IONAME);
|
|
extern void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX);
|
|
extern void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
|
|
GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX);
|
|
extern void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX);
|
|
extern void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
|
|
U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX);
|
|
extern void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX);
|
|
extern void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX);
|
|
extern void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX);
|
|
extern void GPT_Debug_Mode(FunctionalStatus NewState);
|
|
extern void GPT_Start(void);
|
|
extern void GPT_Stop(void);
|
|
extern void GPT_Soft_Reset(void);
|
|
extern void GPT_Cap_Rearm(void);
|
|
extern void GPT_REARM_Write(void);
|
|
extern U8_T GPT_REARM_Read(void);
|
|
extern void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA);
|
|
extern U16_T GPT_PRDR_Read(void);
|
|
extern U16_T GPT_CMPA_Read(void);
|
|
extern U16_T GPT_CMPB_Read(void);
|
|
extern U16_T GPT_CNT_Read(void);
|
|
extern void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X);
|
|
extern void GPT_INT_ENABLE(void);
|
|
extern void GPT_INT_DISABLE(void);
|
|
extern void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
|
|
GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx);
|
|
extern void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
|
|
U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA);
|
|
extern void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
|
|
GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt);
|
|
extern void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
|
|
, GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
|
|
GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP );
|
|
/*************************************************************/
|
|
|
|
#endif /**< apt32f102_gpt_H */
|
|
|
|
/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ |