280 lines
6.8 KiB
C
280 lines
6.8 KiB
C
/*
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******************************************************************************
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* @file apt32f102_lpt.h
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* @author APT AE Team
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* @version V1.08
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* @date 2021/06/21
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******************************************************************************
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*THIS SOFTWARE WHICH IS FOR ILLUSTRATIVE PURPOSES ONLY WHICH PROVIDES
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*CUSTOMER WITH CODING INFORMATION REGARDING THEIR PRODUCTS.
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*APT CHIP SHALL NOT BE HELD RESPONSIBILITY ADN LIABILITY FOR ANY DIRECT,
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*INDIRECT DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF
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*SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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*CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.AND APT CHIP RESERVES
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*THE RIGHT TO MAKE CHANGES IN THE SOFTWARE WITHOUT NOTIFICATION
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _apt32f102_lpt_H
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#define _apt32f102_lpt_H
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/* Includes ------------------------------------------------------------------*/
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#include "apt32f102.h"
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#define LPT_RESET_VALUE (0x00000000)
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//--------------------------------------------------------------------------------
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//-----------------------------LPT value enum define--------------------------
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//--------------------------------------------------------------------------------
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/**
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* @brief LPT CLK EN register
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*/
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typedef enum
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{
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LPTCLK_DIS = 0,
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LPTCLK_EN = 1,
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}LPT_CLK_TypeDef;
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/**
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* @brief LPT CLK source register
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*/
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typedef enum
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{
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LPT_PCLK_DIV4= (0<<2),
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LPT_ISCLK = (1<<2),
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LPT_IMCLK_DIV4 = (2<<2),
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LPT_EMCLK = (3<<2),
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LPT_IN_RISE = (4<<2),
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LPT_IN_FALL = (5<<2),
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}LPT_CSS_TypeDef;
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/**
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* @brief LPT START SHADOW register
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*/
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typedef enum
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{
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LPT_SHADOW = (0<<6),
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LPT_IMMEDIATE= (1<<6),
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}LPT_SHDWSTP_TypeDef;
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/**
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* @brief LPT CLK div register
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*/
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typedef enum
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{
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LPT_PSC_DIV0= 0,
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LPT_PSC_DIV2= 1,
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LPT_PSC_DIV4= 2,
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LPT_PSC_DIV8= 3,
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LPT_PSC_DIV16= 4,
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LPT_PSC_DIV32= 5,
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LPT_PSC_DIV64= 6,
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LPT_PSC_DIV128= 7,
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LPT_PSC_DIV256= 8,
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LPT_PSC_DIV512= 9,
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LPT_PSC_DIV1024= 0X0A,
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LPT_PSC_DIV2048= 0X0B,
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LPT_PSC_DIV4096= 0X0C,
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}LPT_PSCDIV_TypeDef;
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/**
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* @brief LPT START SYN EN register
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*/
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typedef enum
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{
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LPT_SWSYNDIS= (0<<2),
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LPT_SWSYNEN= (1<<2),
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}LPT_SWSYN_TypeDef;
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/**
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* @brief LPT IO stop status register
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*/
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typedef enum
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{
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LPT_IDLE_Z= (0<<3), //High-impedance output
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LPT_IDLE_LOW= (1<<3),
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}LPT_IDLEST_TypeDef;
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/**
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* @brief LPT PRDLD register
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*/
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typedef enum
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{
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LPT_PRDLD_IMMEDIATELY= (0<<4),
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LPT_PRDLD_DUTY_END= (1<<4),
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}LPT_PRDLD_TypeDef;
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/**
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* @brief LPT POL register
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*/
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typedef enum
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{
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LPT_POL_HIGH= (0<<5),
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LPT_POL_LOW= (1<<5),
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}LPT_POL_TypeDef;
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/**
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* @brief LPT OPM register
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*/
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typedef enum
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{
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LPT_OPM_CONTINUOUS= (0<<6),
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LPT_OPM_ONCE= (1<<6),
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}LPT_OPM_TypeDef;
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/**
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* @brief LPT FLTIPSCLD register
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*/
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typedef enum
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{
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LPT_FLTIPSCLD_NULL= (0<<10),
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LPT_FLTIPSCLD_EN= (1<<10),
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}LPT_FLTIPSCLD_TypeDef;
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/**
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* @brief LPT FLTDEB register
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*/
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typedef enum
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{
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LPT_FLTDEB_00= (0<<13),
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LPT_FLTDEB_02= (1<<13),
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LPT_FLTDEB_03= (2<<13),
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LPT_FLTDEB_04= (3<<13),
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LPT_FLTDEB_06= (4<<13),
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LPT_FLTDEB_08= (5<<13),
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LPT_FLTDEB_16= (6<<13),
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LPT_FLTDEB_32= (7<<13),
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}LPT_FLTDEB_TypeDef;
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/**
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* @brief LPT PSCLD register
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*/
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typedef enum
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{
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LPT_PSCLD_0= (0<<16), //PSCR
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LPT_PSCLD_1= (1<<16),
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}LPT_PSCLD_TypeDef;
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/**
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* @brief LPT CMPLD register
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*/
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typedef enum
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{
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LPT_CMPLD_IMMEDIATELY= (0<<17),
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LPT_CMPLD_DUTY_END= (1<<17),
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}LPT_CMPLD_TypeDef;
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/**
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* @brief LPT TRGENX register
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*/
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typedef enum
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{
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LPT_TRGEN_DIS= (0<<0),
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LPT_TRGEN_EN= (1<<0),
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}LPT_TRGENX_TypeDef;
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/**
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* @brief LPT OSTMDX register
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*/
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typedef enum
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{
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LPT_OSTMD_CONTINUOUS= (0<<8),
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LPT_OSTMD_ONCE= (1<<8),
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}LPT_OSTMDX_TypeDef;
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/**
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* @brief LPT AREARM register
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*/
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typedef enum
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{
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LPT_AREARM_DIS= (0<<30),
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LPT_AREARM_EN= (1<<30),
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}LPT_AREARM_TypeDef;
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/**
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* @brief LPT SRCSEL register
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*/
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typedef enum
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{
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LPT_SRCSEL_DIS= (0<<0),
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LPT_SRCSEL_EN= (1<<0),
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}LPT_SRCSEL_TypeDef;
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/**
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* @brief LPT BLKINV register
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*/
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typedef enum
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{
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LPT_BLKINV_DIS= (0<<4),
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LPT_BLKINV_EN= (1<<4),
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}LPT_BLKINV_TypeDef;
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/**
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* @brief LPT CROSSMD register
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*/
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typedef enum
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{
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LPT_CROSSMD_DIS= (0<<7),
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LPT_CROSSMD_EN= (1<<7),
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}LPT_CROSSMD_TypeDef;
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/**
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* @brief LPT TRGSRC0 register
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*/
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typedef enum
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{
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LPT_TRGSRC0_DIS= (0<<0),
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LPT_TRGSRC0_ZRO= (1<<0),
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LPT_TRGSRC0_PRD= (2<<0),
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LPT_TRGSRC0_ZRO_PRD= (3<<0),
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LPT_TRGSRC0_CMP= (4<<0),
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}LPT_TRGSRC0_TypeDef;
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/**
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* @brief LPT ESYN0OE register
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*/
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typedef enum
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{
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LPT_ESYN0OE_DIS= (0<<20),
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LPT_ESYN0OE_EN= (1<<20),
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}LPT_ESYN0OE_TypeDef;
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/**
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* @brief LPT INT MASK SET/CLR Set
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*/
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typedef enum
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{
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LPT_TRGEV0 = (0x01 << 0),
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LPT_MATCH = (0x01 << 1),
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LPT_PEND = (0x01 << 2),
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}LPT_IMSCR_TypeDef;
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/**
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* @brief LPT IO Set
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*/
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typedef enum
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{
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LPT_OUT_PA09 = 0,
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LPT_OUT_PB01 = 1,
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LPT_IN_PA10 = 2,
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}LPT_IOSET_TypeDef;
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#define LPT_DEBUG_MODE (0X01<<1)
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extern void LPT_DeInit(void);
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extern void LPT_IO_Init(LPT_IOSET_TypeDef IONAME);
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extern void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,
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LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX);
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extern void LPT_Debug_Mode(FunctionalStatus NewState);
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extern void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA);
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extern void LPT_CNT_Write(U16_T CNT_DATA);
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extern U16_T LPT_PRDR_Read(void);
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extern U16_T LPT_CMP_Read(void);
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extern U16_T LPT_CNT_Read(void);
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extern void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
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LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX);
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extern void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX);
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extern void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
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LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA);
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extern void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA);
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extern void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA);
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extern void LPT_Soft_Trigger(void);
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extern void LPT_Start(void);
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extern void LPT_Stop(void);
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extern void LPT_Soft_Reset(void);
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extern void LPT_REARM_Write(void);
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extern U8_T LPT_REARM_Read(void);
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extern void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X);
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extern void LPT_INT_ENABLE(void);
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extern void LPT_INT_DISABLE(void);
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/*************************************************************/
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#endif /**< apt32f102_lpt_H */
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/******************* (C) COPYRIGHT 2019 APT Chip *****END OF FILE****/ |